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Sample records for vlsi architecture reconfigurable

  1. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug;

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a photodetector (PD) array. The core component of the architecture......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  2. A novel reconfigurable optical interconnect architecture using an Opto-VLSI processor and a 4-f imaging system.

    Science.gov (United States)

    Shen, Mingya; Xiao, Feng; Alameh, Kamal

    2009-12-07

    A novel reconfigurable optical interconnect architecture for on-board high-speed data transmission is proposed and experimentally demonstrated. The interconnect architecture is based on the use of an Opto-VLSI processor in conjunction with a 4-f imaging system to achieve reconfigurable chip-to-chip or board-to-board data communications. By reconfiguring the phase hologram of an Opto-VLSI processor, optical data generated by a vertical Cavity Surface Emitting Laser (VCSEL) associated to a chip (or a board) is arbitrarily steered to the photodetector associated to another chip (or another board). Experimental results show that the optical interconnect losses range from 5.8dB to 9.6dB, and that the maximum crosstalk level is below -36dB. The proposed architecture is tested for high-speed data transmission, and measured eye diagrams display good eye opening for data rate of up to 10Gb/s.

  3. VLSI Architectures for Computing DFT's

    Science.gov (United States)

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  4. High-speed (2.5 Gbps) reconfigurable inter-chip optical interconnects using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal E; Lee, Yong-Tak; Chung, Il-Sug

    2006-07-24

    Reconfigurablele optical interconnects enable flexible and high-performance communication in multi-chip architectures to be arbitrarily adapted, leading to efficient parallel signal processing. The use of Opto-VLSI processors as beam steerers and multicasters for reconfigurable inter-chip optical interconnection is discussed. We demonstrate, as proof-of-concept, 2.5 Gbps reconfigurable optical interconnects between an 850nm vertical cavity surface emitting lasers (VCSEL) array and a photodiode (PD) array integrated onto a PCB by driving two Opto-VLSI processors with steering and multicasting digital phase holograms. The architecture is experimentally demonstrated through three scenarios showing its flexibility to perform single, multicasting, and parallel reconfigurable optical interconnects. To our knowledge, this is the first reported high-speed reconfigurable N-to-N optical interconnects architecture, which will have a significant impact on the flexibility and efficiency of large shared-memory multiprocessor machines.

  5. An efficient interpolation filter VLSI architecture for HEVC standard

    Science.gov (United States)

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  6. Reconfigurable Parallel Data Flow Architecture

    CERN Document Server

    Naji, Hamid Reza

    2010-01-01

    This paper presents a reconfigurable parallel data flow architecture. This architecture uses the concepts of multi-agent paradigm in reconfigurable hardware systems. The utilization of this new paradigm has the potential to greatly increase the flexibility, efficiency, expandability of data flow systems and to provide an attractive alternative to the current set of disjoint approaches that are currently applied to this problem domain. The ability of methodology to implement data flow type processing with different models is presented in this paper.

  7. Power Efficient Sub-Array in Reconfigurable VLSI Meshes

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan

    2005-01-01

    Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.

  8. An Efficient Reconfigurable Architecture for Fingerprint Recognition

    Directory of Open Access Journals (Sweden)

    Satish S. Bhairannawar

    2016-01-01

    Full Text Available The fingerprint identification is an efficient biometric technique to authenticate human beings in real-time Big Data Analytics. In this paper, we propose an efficient Finite State Machine (FSM based reconfigurable architecture for fingerprint recognition. The fingerprint image is resized, and Compound Linear Binary Pattern (CLBP is applied on fingerprint, followed by histogram to obtain histogram CLBP features. Discrete Wavelet Transform (DWT Level 2 features are obtained by the same methodology. The novel matching score of CLBP is computed using histogram CLBP features of test image and fingerprint images in the database. Similarly, the DWT matching score is computed using DWT features of test image and fingerprint images in the database. Further, the matching scores of CLBP and DWT are fused with arithmetic equation using improvement factor. The performance parameters such as TSR (Total Success Rate, FAR (False Acceptance Rate, and FRR (False Rejection Rate are computed using fusion scores with correlation matching technique for FVC2004 DB3 Database. The proposed fusion based VLSI architecture is synthesized on Virtex xc5vlx30T-3 FPGA board using Finite State Machine resulting in optimized parameters.

  9. Reconfigurable optical power splitter/combiner based on Opto-VLSI processing.

    Science.gov (United States)

    Mustafa, Haithem; Xiao, Feng; Alameh, Kamal

    2011-10-24

    A novel 1×4 reconfigurable optical splitter/combiner structure based on Opto-VLSI processor and 4-f imaging system with high resolution is proposed and experimentally demonstrated. By uploading optimized multicasting phase holograms onto the software-driven Opto-VLSI processor, an input optical signal is dynamically split into different output fiber ports with user-defined splitting ratios. Also, multiple input optical signals are dynamically combined with arbitrary user-defined weights.

  10. Adaptive reconfigurable distributed sensor architecture

    Science.gov (United States)

    Akey, Mark L.

    1997-07-01

    The infancy of unattended ground based sensors is quickly coming to an end with the arrival of on-board GPS, networking, and multiple sensing capabilities. Unfortunately, their use is only first-order at best: GPS assists with sensor report registration; networks push sensor reports back to the warfighter and forwards control information to the sensors; multispectral sensing is a preset, pre-deployment consideration; and the scalability of large sensor networks is questionable. Current architectures provide little synergy among or within the sensors either before or after deployment, and do not map well to the tactical user's organizational structures and constraints. A new distributed sensor architecture is defined which moves well beyond single sensor, single task architectures. Advantages include: (1) automatic mapping of tactical direction to multiple sensors' tasks; (2) decentralized, distributed management of sensor resources and tasks; (3) software reconfiguration of deployed sensors; (4) network scalability and flexibility to meet the constraints of tactical deployments, and traditional combat organizations and hierarchies; and (5) adaptability to new battlefield communication paradigms such as BADD (Battlefield Analysis and Data Dissemination). The architecture is supported in two areas: a recursive, structural definition of resource configuration and management via loose associations; and a hybridization of intelligent software agents with tele- programming capabilities. The distributed sensor architecture is examined within the context of air-deployed ground sensors with acoustic, communication direction finding, and infra-red capabilities. Advantages and disadvantages of the architecture are examined. Consideration is given to extended sensor life (up to 6 months), post-deployment sensor reconfiguration, limited on- board sensor resources (processor and memory), and bandwidth. It is shown that technical tasking of the sensor suite can be automatically

  11. The Molen compiler for reconfigurable architectures

    NARCIS (Netherlands)

    Moscu Panainte, E.

    2007-01-01

    In this dissertation, we present the Molen compiler framework that targets reconfigurable architectures under the Molen Programming Paradigm. More specifically, we introduce a set of compiler optimizations that address one of the main shortcomings of the reconfigurable architectures, namely the reco

  12. Implementing neural architectures using analog VLSI circuits

    Science.gov (United States)

    Maher, Mary Ann C.; Deweerth, Stephen P.; Mahowald, Misha A.; Mead, Carver A.

    1989-05-01

    Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems.

  13. Low complexity reconfigurable architecture for the 5/3 and 9/7 discrete wavelet transform

    Institute of Scientific and Technical Information of China (English)

    Xiong Chengyi; Tian Jinwen; Liu Jian

    2006-01-01

    Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexing, as well as embedded boundary data extension technique, is adopted to optimize the design of the architecture. These reduce significantly the required numbers of the multipliers, adders and registers, as well as the amount of accessing external memory, and lead to decrease efficiently the hardware cost and power consumption of the design. The architecture is designed to generate an output per clock cycle, and the detailed component and the approximation of the input signal are available alternately. Experimental simulation and comparison results are presented, which demonstrate that the proposed architecture has lower hardware complexity, thus it is adapted for embedded applications. The presented architecture is simple, regular and scalable, and well suited for VLSI implementation.

  14. VLSI ARCHITECTURE OF AN AREA EFFICIENT IMAGE INTERPOLATION

    Directory of Open Access Journals (Sweden)

    John Moses C

    2014-05-01

    Full Text Available Image interpolation is widely used in many image processing applications, such as digital camera, mobile phone, tablet and display devices. Image interpolation is a method of estimating the new data points within the range of discrete set of known data points. Image interpolation can also be referred as image scaling, image resizing, image re-sampling and image zooming. This paper presents VLSI (Very Large Scale Integration architecture of an area efficient image interpolation algorithm for any two dimensional (2-D image scalar. This architecture is implemented in FPGA (Field Programmable Gate Array and the performance of this system is simulated using Xilinx system generator and synthesized using Xilinx ISE smulation tool. Various VLSI parameters such as combinational path delay, CPU time, memory usage, number of LUTs (Look Up Tables are measured from the synthesis report.

  15. VLSI neural system architecture for finite ring recursive reduction.

    Science.gov (United States)

    Zhang, D; Jullien, G A

    1996-12-01

    The use of neural-like networks to implement finite ring computations has been presented in a previous paper. This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including module reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.

  16. Digital VLSI algorithms and architectures for support vector machines.

    Science.gov (United States)

    Anguita, D; Boni, A; Ridella, S

    2000-06-01

    In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

  17. Hybrid VLSI/QCA Architecture for Computing FFTs

    Science.gov (United States)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  18. Automatic Hardware Generation for Reconfigurable Architectures

    NARCIS (Netherlands)

    Nane, R.

    2014-01-01

    Reconfigurable Architectures (RA) have been gaining popularity rapidly in the last decade for two reasons. First, processor clock frequencies reached threshold values past which power dissipation becomes a very difficult problem to solve. As a consequence, alternatives were sought to keep improving

  19. A VLSI architecture for simplified arithmetic Fourier transform algorithm

    Science.gov (United States)

    Reed, Irving S.; Shih, Ming-Tang; Truong, T. K.; Hendon, E.; Tufts, D. W.

    1992-01-01

    The arithmetic Fourier transform (AFT) is a number-theoretic approach to Fourier analysis which has been shown to perform competitively with the classical FFT in terms of accuracy, complexity, and speed. Theorems developed in a previous paper for the AFT algorithm are used here to derive the original AFT algorithm which Bruns found in 1903. This is shown to yield an algorithm of less complexity and of improved performance over certain recent AFT algorithms. A VLSI architecture is suggested for this simplified AFT algorithm. This architecture uses a butterfly structure which reduces the number of additions by 25 percent of that used in the direct method.

  20. Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing.

    Science.gov (United States)

    Fey, D; Kasche, B; Burkert, C; Tschäche, O

    1998-01-10

    A concept for a parallel digital signal processor based on opticalinterconnections and optoelectronic VLSI circuits is presented. Itis shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperformspurely electronic solutions. The usefulness of low-level algorithmsfrom the add-and-shift class is emphasized. These algorithms leadto fine-grain, massively parallel on-chip processor architectures withhigh demands for optical off-chip interconnections. A comparativeperformance analysis shows the superiority of a bit-serialarchitecture. This architecture is mapped onto an optoelectronicthree-dimensional circuit, and the necessary optical interconnectionscheme is specified.

  1. Efficient VLSI architecture for training radial basis function networks.

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-03-19

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  2. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Directory of Open Access Journals (Sweden)

    Wen-Jyi Hwang

    2013-03-01

    Full Text Available This paper presents a novel VLSI architecture for the training of radial basis function (RBF networks. The architecture contains the circuits for fuzzy C-means (FCM and the recursive Least Mean Square (LMS operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA. It is used as a hardware accelerator in a system on programmable chip (SOPC for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired.

  3. Architecturally Reconfigurable Development of Mobile Games

    DEFF Research Database (Denmark)

    Zhang, Weishan

    2005-01-01

    Mobile game development must face the problem of multiple hardware and software platforms, which will bring large number of variants. To cut the development and maintenance efforts, in this paper, we present an architecturally reconfigurable software product line approach to develop mobile games....... Mobile game domain variants could be handled uniformly and traced across all kinds of software assets. The architecture and configuration mechanism in our approach make optimizations that built into meta-components propagated to all product line members. We show this approach with an industrial Role......-Playing-Game product line, which achieved not only development and maintenance gains, but also performance enhancements....

  4. DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

    Directory of Open Access Journals (Sweden)

    David Raphaël

    2008-01-01

    Full Text Available Abstract Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13  m CMOS SoC implementing a specialized DART cluster is presented.

  5. Design of Analog VLSI Architecture for DCT

    Directory of Open Access Journals (Sweden)

    M.Thiruveni

    2012-08-01

    Full Text Available When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP algorithms to reduce the area and power requirement in theexisting Digital CMOS implementations. Discrete Cosine Transform (DCT with signed coefficients have been designed andimplemented in this paper. The problems of digital DCTs viz., quantization error, round-off noise, high power consumption and largearea are overcome by the proposed implementation. It can be used to develop the architecture design of DFT, DST and DHT.

  6. Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture.

    Science.gov (United States)

    Abdelhalim, K; Smolyakov, V; Genov, R

    2011-10-01

    A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

  7. Novel broadband reconfigurable optical add-drop multiplexer employing custom fiber arrays and Opto-VLSI processors.

    Science.gov (United States)

    Xiao, Feng; Juswardy, Budi; Alameh, Kamal; Lee, Yong Tak

    2008-08-04

    A reconfigurable optical add/drop multiplexer (ROADM) structure based on using a custom-made fiber array and an Opto-VLSI processor is proposed and demonstrated. The fiber array consists of N pairs of angled fibers corresponding to N channels, each of which can independently perform add, drop, and thru functions through a reconfigurable Opto-VLSI beam steerer. Experimental results show that the ROADM structure can attain an average add, drop/thru insertion loss of 5.5 dB and a uniformity of 0.3 dB over a wide bandwidth from 1524 nm to 1576 nm, and a drop/thru crosstalk level as small as -40 dB.

  8. An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Cavallaro Joseph R

    2006-01-01

    Full Text Available We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI of size with complexity to some FFT operations with complexity and the inverse of some submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the high-order receiver from partitioned submatrices. This leads to more parallel VLSI design with further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

  9. Partial Reconfiguration on FPGAs Architectures, Tools and Applications

    CERN Document Server

    Koch, Dirk

    2013-01-01

    This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed.  Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system.  The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems.  Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.   Provides comprehensive overview of state-of-the-art partial run-time reconfiguration techniques, including architectures, methods, and tools; Focuses on real applications that will benefit from partial reconfiguration; �...

  10. Modular reconfigurable machines incorporating modular open architecture control

    CSIR Research Space (South Africa)

    Padayachee, J

    2008-01-01

    Full Text Available degrees of freedom on a single platform. A corresponding modular Open Architecture Control (OAC) system is presented. OAC overcomes the inflexibility of fixed proprietary automation, ensuring that MRMs provide the reconfigurability and extensibility...

  11. VLSI Implementation of Hybrid Algorithm Architecture for Speech Enhancement

    Directory of Open Access Journals (Sweden)

    Jigar Shah

    2012-07-01

    Full Text Available The speech enhancement techniques are required to improve the speech signal quality without causing any offshoot in many applications. Recently the growing use of cellular and mobile phones, hands free systems, VoIP phones, voice messaging service, call service centers etc. require efficient real time speech enhancement and detection strategies to make them superior over conventional speech communication systems. The speech enhancement algorithms are required to deal with additive noise and convolutive distortion that occur in any wireless communication system. Also the single channel (one microphone signal is available in real environments. Hence a single channel hybrid algorithm is used which combines minimum mean square error-log spectral amplitude (MMSE-LSA algorithm for additive noise removal and the relative spectral amplitude (RASTA algorithm for reverberation cancellation. The real time and embedded implementation on directly available DSP platforms like TMS320C6713 shows some defects. Hence the VLSI implementation using semi-custom (e.g. FPGA or full-custom approach is required. One such architecture is proposed in this paper.

  12. Efficient VLSI architecture of CAVLC decoder with power optimized

    Institute of Scientific and Technical Information of China (English)

    CHEN Guang-hua; HU Deng-ji; ZHANG Jin-yi; ZHENG Wei-feng; ZENG Wei-min

    2009-01-01

    This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code (CAVLC) decoder with power optimized for the H.264/advanced video coding (AVC) standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore's decoding,arithmetic operation is combined with finite state machine (FSM), which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

  13. Reconfigurable transceiver architecture for multiband RF-frontends

    CERN Document Server

    Gonzalez Rodriguez, Erick

    2016-01-01

      This book investigates and discusses the hardware design and implementation to achieve smart air interfaces with a reduced number of Radio Frequency (RF) transmitter and receiver chains, or even with a single reconfigurable RF-Frontend in the user terminal. Various hardware challenges are identified and addressed to enable the implementation of autonomous reconfigurable RF-Frontend architectures. Such challenges are (i) the conception of a transceiver with wide tuning range of at least up to 6 GHz, (ii) the system integration of reconfigurable technologies targeting current compact devices that demand voltages up to 100 V for adaptive controlling and (iii) the realization of a multiband and multistandard antenna module employing agile components to provide flexible frequency coverage. A solid design of a reconfigurable frontend is proposed from the RF part to the digital baseband. The system integration of different components in the reconfigurable RF-Frontend of a portable-oriented device architecture is ...

  14. An Opto-VLSI-based reconfigurable optical adddrop multiplexer employing an off-axis 4-f imaging system.

    Science.gov (United States)

    Shen, Mingya; Xiao, Feng; Ahderom, Selam; Alameh, Kamal

    2009-08-03

    A novel reconfigurable optical add-drop multiplexer (ROADM) structure is proposed and demonstrated experimentally. The ROADM structure employs two arrayed waveguide gratings (AWGs), an array of optical fiber pairs, an array of 4-f imaging microlenses that are offset in relation to the axis of symmetry of the fiber pairs, and a reconfigurable Opto-VLSI processor that switches various wavelength channels between the fiber pairs to achieve add or drop multiplexing. Experimental results are shown, which demonstrate the principle of add/drop multiplexing with crosstalk of less than -27dB and insertion loss of less than 8dB over the Cband for drop and through operation modes.

  15. Reconfigurable radio systems network architectures and standards

    CERN Document Server

    Iacobucci, Maria Stella

    2013-01-01

    This timely book provides a standards-based view of the development, evolution, techniques and potential future scenarios for the deployment of reconfigurable radio systems.  After an introduction to radiomobile and radio systems deployed in the access network, the book describes cognitive radio concepts and capabilities, which are the basis for reconfigurable radio systems.  The self-organizing network features introduced in 3GPP standards are discussed and IEEE 802.22, the first standard based on cognitive radio, is described. Then the ETSI reconfigurable radio systems functional ar

  16. Reconfigurable materials: Algorithm for architectural origami

    Science.gov (United States)

    Paik, Jamie

    2017-01-01

    An algorithm has been developed allowing the rational design of origami-inspired materials that can be rearranged to change their properties. This might open the way to strategies for making reconfigurable robots. See Article p.347

  17. DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency

    Directory of Open Access Journals (Sweden)

    Sébastien Pillement

    2007-12-01

    Full Text Available Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functional-level reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13 μm CMOS SoC implementing a specialized DART cluster is presented.

  18. Towards effective modeling and programming multi-core tiled reconfigurable architectures

    NARCIS (Netherlands)

    Rovers, K.C.; Burgwal, van de M.D.; Kuper, J.; Smit, G.J.M.

    2009-01-01

    For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modeling and programming such systems remains an issue. We will advocate a mod

  19. Reconfigurable Multicore Architectures for Streaming Applications

    NARCIS (Netherlands)

    Smit, Gerardus Johannes Maria; Kokkeler, Andre B.J.; Rauwerda, G.K.; Jacobs, J.W.M.; Nicolescu, G.; Mosterman, P.J.

    2009-01-01

    This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items

  20. Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-06-01

    Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

  1. Temporal Partitioning and Multi-Processor Scheduling for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    This poster presentation outlines a proposed framework for handling mapping of signal processing applications to heterogeneous reconfigurable architectures. The methodology consists of an extension to traditional multi-processor scheduling by creating a separate HW track for generation of groups...... of tasks that are handled similarly to SW processes in a traditional multi-processor scheduling context....

  2. Dataflow-based reconfigurable architecture for streaming applications

    NARCIS (Netherlands)

    Niedermeier, A.; Kuper, J.; Smit, G.J.M.

    2012-01-01

    Coarse-grain reconfigurable arrays often rely on an imperative programming approach including a read/write mechanism for memory access. In this paper, we present an architecture composed of a configurable array of computing cores and memory blocks in which both the execution mechanism and configurat

  3. Trustworthy reconfigurable systems enhancing the security capabilities of reconfigurable hardware architectures

    CERN Document Server

    Feller, Thomas

    2014-01-01

    ?Thomas Feller sheds some light on trust anchor architectures fortrustworthy reconfigurable systems. He is presenting novel concepts enhancing the security capabilities of reconfigurable hardware.Almost invisible to the user, many computer systems are embedded into everyday artifacts, such as cars, ATMs, and pacemakers. The significant growth of this market segment within the recent years enforced a rethinking with respect to the security properties and the trustworthiness of these systems. The trustworthiness of a system in general equates to the integrity of its system components. Hardware-b

  4. Reconfigurable VLSI implementation for learning vector quantization with on-chip learning circuit

    Science.gov (United States)

    Zhang, Xiangyu; An, Fengwei; Chen, Lei; Jürgen Mattausch, Hans

    2016-04-01

    As an alternative to conventional single-instruction-multiple-data (SIMD) mode solutions with massive parallelism for self-organizing-map (SOM) neural network models, this paper reports a memory-based proposal for the learning vector quantization (LVQ), which is a variant of SOM. A dual-mode LVQ system, enabling both on-chip learning and classification, is implemented by using a reconfigurable pipeline with parallel p-word input (R-PPPI) architecture. As a consequence of the reuse of R-PPPI for solving the most severe computational demands in both modes, power dissipation and Si-area consumption can be dramatically reduced in comparison to previous LVQ implementations. In addition, the designed LVQ ASIC has high flexibility with respect to feature-vector dimensionality and reference-vector number, allowing the execution of many different machine-learning applications. The fabricated test chip in 180 nm CMOS with parallel 8-word inputs and 102 K-bit on-chip memory achieves low power consumption of 66.38 mW (at 75 MHz and 1.8 V) and high learning speed of (R + 1) × \\lceil d/8 \\rceil + 10 clock cycles per d-dimensional sample vector where R is the reference-vector number.

  5. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  6. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  7. A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture

    NARCIS (Netherlands)

    Guo, Y.; Hoede, C.; Smit, G.J.M.; Plaks, T.P.; DeMara, R.; Gokhale, M.; Guccione, S.; Platzner, M.; Smit, G.J.M.; Wirthlin, M.

    2006-01-01

    In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purpose processor, the programmability of a coarse-grained reconfigurable architecture is limited. The limitation might be th

  8. Design of a real-time open architecture controller for a reconfigurable machine tool

    CSIR Research Space (South Africa)

    Masekamela, I

    2008-11-01

    Full Text Available The paper presents the design and the development of a real-time, open architecture controller that is used for control of reconfigurable manufacturing tools (RMTs) in reconfigurable manufacturing systems (RMS). The controller that is presented can...

  9. Multicore technology architecture, reconfiguration, and modeling

    CERN Document Server

    Qadri, Muhammad Yasir

    2013-01-01

    The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing. The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debu

  10. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  11. VLSI architectures for computing multiplications and inverses in GF(2-m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.; Reed, I. S.

    1983-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  12. VLSI architectures for computing multiplications and inverses in GF(2m)

    Science.gov (United States)

    Wang, C. C.; Truong, T. K.; Shao, H. M.; Deutsch, L. J.; Omura, J. K.

    1985-01-01

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  13. Reconfigurable Hardware Architecture for Network Intrusion Detection System

    Directory of Open Access Journals (Sweden)

    A. Kaleel Rahuman

    2012-01-01

    Full Text Available Intrusion rule processing in reconfigurable hardware enables intrusion detection and prevention. The use of reconfigurable hardware for network security applications has great strides as Field Programmable Gate Array (FPGA devices have provided larger and faster resources. This proposes architecture called “BV-TCAM” is presented, which is implemented for an FPGA-based Network Intrusion Detection Systems (NIDS. The BV-TCAM architecture combines the Ternary Content Addressable Memory (TCAM and Bit Vector (BV algorithm to effectively compress the data representation and throughput. A tree bitmap implementation of the BV algorithm is used for source and destination port lookup while a TCAM performs lookup for other header fields, which can be represented as a prefix or exact value. With the aid of small embedded TCAM, packet classification can be implemented in relatively small part of the available logic of an FPGA. The BV-TCAM architecture has been modelled by VHDL. Simulations were performed by MODELSIM. This architecture have to be synthesized and implement our design using Xilinx FPGA device."

  14. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  15. OLLAF: A Fine Grained Dynamically Reconfigurable Architecture for OS Support

    Directory of Open Access Journals (Sweden)

    Garcia Samuel

    2009-01-01

    Full Text Available Fine Grained Dynamically Reconfigurable Architecture (FGDRA offers a flexibility for embedded systems with a great power processing efficiency by exploiting optimizations opportunities at architectural level thanks to their fine configuration granularity. But this increase design complexity that should be abstracted by tools and operating system. In order to have a usable solution, a good inter-overlapping between tools, OS, and platform must exist. In this paper we present OLLAF, an FGDRA specially designed to efficiently support an OS. The studies presented here show the contribution of this architecture in terms of hardware context management and preemption support. Studies presented here show the gain that can be obtained, by using OLLAF instead of a classical FPGA, in terms of context management and preemption overhead.

  16. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  17. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  18. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Science.gov (United States)

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  19. A Parallel-based Lifting Algorithm and VLSI Architecture for DWT

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A novel Parallel-Based Lifting Algorithm (PBLA) for Discrete Wavelet Transform (DWT), exploiting the parallelism of arithmetic operations in all lifting steps, is proposed in this paper. It leads to reduce the critical path latency of computation, and to reduce the complexity of hardware implementation as well. The detailed derivation on the proposed algorithm, as well as the resulting Very Large Scale Integration (VLSI) architecture, is introduced, taking the 9/7 DWT as an example but without loss of generality. In comparison with the Conventional Lifting Algorithm Based Implementation (CLABI), the critical path latency of the proposed architecture is reduced by more than half from (4Tm + 8Ta)to Tm + 4Ta, and is competitive to that of Convolution-Based Implementation (CBI), but the new implementation will save significantly in hardware. The experimental results demonstrate that the proposed architecture has good performance in both increasing working frequency and reducing area.

  20. A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA

    Directory of Open Access Journals (Sweden)

    Nishi Pandey

    2015-10-01

    Full Text Available Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its implementation is increasing day by day. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry select adder (CSA. Modified CSA depend on booth encoder (BEC Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family

  1. Dynamic reconfigurable architectures and transparent optimization techniques automatic acceleration of software execution

    CERN Document Server

    Fl, Antonio Carlos

    2010-01-01

    This book provides a clear review of static and dynamic architecture optimization strategies in the field of reconfigurable computing. It includes a number of case studies and a quantitative analysis of the DIM architecture.

  2. Reconfigurable architecture for MIMO systems based on CORDIC operators

    Science.gov (United States)

    Wang, Hongzhi; Leray, Pierre; Palicot, Jacques

    2006-09-01

    The MIMO system is an attractive technology for wireless 3G/4G systems. In this article we propose the realization on FPGA of a MIMO 'V-BLAST Square Root' algorithm based on a variable number of CORDIC operators. The CORDIC operator is highly suitable for this implementation as it only relies on simple techniques of addition and vector offsets. This square root algorithm architecture is reconfigurable in order to adapt itself to different numbers of antennas and different data rates. The proposed architecture can achieve a data rate of 600 Mbit/s in a Virtex-II FPGA circuit from Xilinx for the MIMO system with QPSK modulation. To cite this article: H. Wang et al., C. R. Physique 7 (2006).

  3. A novel VLSI processor architecture for supercomputing arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

    1993-01-01

    Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

  4. VLSI architecture of NEO spike detection with noise shaping filter and feature extraction using informative samples.

    Science.gov (United States)

    Hoang, Linh; Yang, Zhi; Liu, Wentai

    2009-01-01

    An emerging class of multi-channel neural recording systems aims to simultaneously monitor the activity of many neurons by miniaturizing and increasing the number of recording channels. Vast volume of data from the recording systems, however, presents a challenge for processing and transmitting wirelessly. An on-chip neural signal processor is needed for filtering uninterested recording samples and performing spike sorting. This paper presents a VLSI architecture of a neural signal processor that can reliably detect spike via a nonlinear energy operator, enhance spike signal over noise ratio by a noise shaping filter, and select meaningful recording samples for clustering by using informative samples. The architecture is implemented in 90-nm CMOS process, occupies 0.2 mm(2), and consumes 0.5 mW of power.

  5. An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

    Science.gov (United States)

    Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

    2016-09-01

    The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

  6. A novel VLSI architecture of arithmetic encoder with reduced memory in SPIHT

    Science.gov (United States)

    Liu, Kai; Li, YunSong; Belyaev, Eugeniy

    2010-08-01

    The paper presents a context-based arithmetic coder's VLSI architecture used in SPIHT with reduced memory, which is used for high speed real-time applications. For hardware implementation, a dedicated context model is proposed for the coder. Each context can be processed in parallel and high speed operators are used for interval calculations. An embedded register array is used for cumulative frequency update. As a result, the coder can consume one symbol at each clock cycle. After FPGA synthesis and simulation, the throughput of our coder is comparable with those of similar hardware architectures used in ASIC technology. Especially, the memory capacity of the coder is smaller than those of corresponding systems.

  7. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  8. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  9. On VLSI Design of Rank-Order Filtering using DCRAM Architecture.

    Science.gov (United States)

    Lin, Meng-Chun; Dung, Lan-Rong

    2008-02-01

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7μm(2) and the VLSI implementation of ROF can operate at 256 MHz for 1.8V supply.

  10. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  11. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Directory of Open Access Journals (Sweden)

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  12. Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

    Institute of Scientific and Technical Information of China (English)

    Li Zhang; Don Xie; Di Wu

    2006-01-01

    The Video part of AVS (Audio Video Coding Standard) has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV (high definition television) content. Based on the original FFSBM (fast full search blocking matching),this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD (motion vector difference). A VLSI (very large scale integration) architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.

  13. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  14. A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

    CERN Document Server

    Sharma, Hrishikesh

    2011-01-01

    Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been p...

  15. High-performance VLSI architectures for turbo decoders with QPP interleaver

    Science.gov (United States)

    Verma, Shivani; Kumar, S.

    2015-04-01

    This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW - SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of 'mod' operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

  16. Heterogeneous reconfigurable processors for real-time baseband processing from algorithm to architecture

    CERN Document Server

    Zhang, Chenxin; Öwall, Viktor

    2016-01-01

    This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. •Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfigur...

  17. Comparison Study on Three Different Reconfigurable Optical Add Drop Multiplexer Architectures

    Institute of Scientific and Technical Information of China (English)

    ZHOU Bin; ZHANG Yang-an; HUANG Yong-qing; REN Xiao-min

    2007-01-01

    In this paper, we present the evolution of reconfigurable optical add drop multiplexer(ROADM) technologies, and compare three main ROADM architectures available on the market today. Three architectures include broadcast-select and demux-switch-mux[and the integrated version planar lightwave circuit(PLC)] and wavelengths-selective switch.

  18. Field Programmable DSP Arrays - A Novel Reconfigurable Architecture for Efficient Reliazation of Digital Signal Processing Functions

    Directory of Open Access Journals (Sweden)

    Amitabha Sinha

    2013-04-01

    Full Text Available Digital Signal Processing functions are widely used in real time high speed applications. Those functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is redolent to FPGA, but with basic fixed Common Modules (CMs (like adders, subtractors, multipliers, scaling units, shifters instead of CLBs. This pape r introduces the development of a reconfigurable DSP processor that integrates different filter and transform functions. The switching between DSP functions is occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility, parallelism and scalability.

  19. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Science.gov (United States)

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  20. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  1. Designing A Re-Configurable Fractional Fourier Transform Architecture Using Systolic Array

    Directory of Open Access Journals (Sweden)

    Anal Acharya

    2010-11-01

    Full Text Available FRFT (Fractional Fourier Transforms algorithm, which has been derived from DFT, computes the angular domains within the time and frequency domains. This algorithm is increasingly used in the field of signal filtering, quantum mechanics and optical physics. In this paper we develop an efficient, systolic, re-configurable architecture for a particular type of FRFT called MA-CDFRFT (Multi Angle Centered Discrete FRFT. The benefit of this particular type of FRFT is that it computes all the signal components within equally spaced angles. Systolic architecture is used for this computation as it has certain advantages over the other forms like simplicity, regularity, concurrency and computation intensive The resultant product so developed should meet the challenges of today's market like marketable and cheap along with meeting customer demands. This calls for the architecture to be re-configurable. Re-configurable computer consist of a standard processor and an array of re-configurable hardware. The main processor would control the behavior of the re-configurable hardware. The re-configurable hardware would then be tailored to perform a specific task, such as image processing or pattern matching applications, as if it was built to perform this task exclusively.

  2. Generic Multimedia Multimodal Agents Paradigms and Their Dynamic Reconfiguration at the Architectural Level

    Directory of Open Access Journals (Sweden)

    H. Djenidi

    2004-09-01

    Full Text Available The multimodal fusion for natural human-computer interaction involves complex intelligent architectures which are subject to the unexpected errors and mistakes of users. These architectures should react to events occurring simultaneously, and possibly redundantly, from different input media. In this paper, intelligent agent-based generic architectures for multimedia multimodal dialog protocols are proposed. Global agents are decomposed into their relevant components. Each element is modeled separately. The elementary models are then linked together to obtain the full architecture. The generic components of the application are then monitored by an agent-based expert system which can then perform dynamic changes in reconfiguration, adaptation, and evolution at the architectural level. For validation purposes, the proposed multiagent architectures and their dynamic reconfiguration are applied to practical examples, including a W3C application.

  3. ARCHITECTURE IN RECONFIGURABLE MANUFACTURING SYSTEM*%可重构制造系统的体系结构

    Institute of Scientific and Technical Information of China (English)

    郭志平

    2001-01-01

    可重构制造系统是现代企业生存和发展的基本手段,具有较高可重构性的企业能在难以预测的环境中,面对竞争对手脱颖而出.本文从可重构制造系统的概念,组织体系,商业体系,产品体系及信息体系等方面研究了可重构制造系统的体系结构,探讨了可重构制造系统的可行性.%Reconfigurable manufacturing system is an essential means for a modern enterprise to survive and. develop. The enterprise of having reconfigurable manufacturing ability can go beyond from other enterprise and be well always at a constantly changing and unforeseeing environment. This paper discusses architecture in reconfigurable manufacturing system from the six aspects of the concept of reconfigurable manufacturing system, reconfigurable organization architecture, reconfigurable business architecture, reconfigurable product architecture and reconfigurable workshop machine architecture and reconfigurable information architecture. Their relations one anther and contexts show the architecture frame of a manufacture system in this paper.

  4. Optimizing the architecture of SFQ-RDP (Single Flux Quantum- Reconfigurable Datapath)

    OpenAIRE

    Mehdipour, Farhad; Honda, Hiroaki; Kataoka, Hiroshi; Inoue, Koji; Murakami, Kazuaki

    2009-01-01

    A large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is designed to overcome the issues originating from the CMOS technology. The LSRDP micro-architecture design procedure and its outcome will be presented in this paper.

  5. Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

    Directory of Open Access Journals (Sweden)

    Liang Ying-Chang

    2005-01-01

    Full Text Available This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP -based communication systems, including orthogonal frequency-division multiplexing (OFDM, single-carrier cyclic-prefix (SCCP system, multicarrier (MC code-division multiple access (MC-CDMA, MC direct-sequence CDMA (MC-DS-CDMA, CP-based CDMA (CP-CDMA, and CP-based direct-sequence CDMA (CP-DS-CDMA. A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.

  6. A Highly Parallelized MIMO Detector for Vector-Based Reconfigurable Architectures

    OpenAIRE

    Zhang, Chenxin; Liu, Liang; Wang, Yian; Zhu, Meifang; Edfors, Ove; Öwall, Viktor

    2013-01-01

    This paper presents a highly parallelized MIMO signal detection algorithm targeting vector-based reconfigurable architectures. The detector achieves high data-level parallelism and near-ML performance by adopting a vector-architecture-friendly technique - parallel node perturbation. To further reduce the computational complexity, imbalanced node and successive partial node expansion schemes in conjunction with sorted QR decomposition are applied. The effectiveness of the proposed algorithm is...

  7. On fast iterative mapping algorithms for stripe based coarse-grained reconfigurable architectures

    Science.gov (United States)

    Mehta, Gayatri; Patel, Krunalkumar; Pollard, Nancy S.

    2015-01-01

    Reconfigurable devices have potential for great flexibility/efficiency, but mapping algorithms onto these architectures is a long-standing challenge. This paper addresses this challenge for stripe based coarse-grained reconfigurable architectures (CGRAs) by drawing on insights from graph drawing. We adapt fast, iterative algorithms from hierarchical graph drawing to the problem of mapping to stripe based architectures. We find that global sifting is 98 times as fast as simulated annealing and produces very compact designs with 17% less area on average, at a cost of 5% greater wire length. Interleaving iterations of Sugiyama and global sifting is 40 times as fast as simulated annealing and achieves somewhat more compact designs with 1.8% less area on average, at a cost of only 1% greater wire length. These solutions can enable fast design space exploration, rapid performance testing, and flexible programming of CGRAs "in the field."

  8. An Adaptive Filtering System Configurations and Architecture on Reconfigurable Platform

    Directory of Open Access Journals (Sweden)

    Dipen B. Patel

    2014-03-01

    Full Text Available This paper proposed the implementation of adaptive filters on reconfigurable platform. Adaptive filter is an essential part of digital signal systems, have been widely used and its implementation takes a great deal, there is no dedicated IC for adaptive filter. When FPGA implemented in such area, provides a lot of facilities to the designers and also offer a better solution for filtering the data. Adaptive signal processing evolved from the techniques developed to enable the adaptive control of time- varying systems. Filtering data in real-time requires dedicated hardware to meet demanding time requirements and provide the highest processing performance, but is inflexible for changes. When a design demands the use of a DSP, design adaptability is crucial, then FPGA may offer a better solution. Reconfigurable hardware devices offer both the flexibility of computer software, and the ability to construct custom high performance computing circuits. Adaptive filter implemented using Field Programmable Gate Arrays (FPGAs due to some of their attractive advantages include flexibility and programmability, availability of tens to hundreds of hardware multipliers available on a chip. Keywords -

  9. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  10. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  11. MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture

    DEFF Research Database (Denmark)

    Wu, Kehuai; Kanstein, Andreas; Madsen, Jan;

    2007-01-01

    -ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl’s law, this paper proposes to extend ADRES to MT-ADRES (Multi-Threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned in multiple...... smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation that exploits...... a mix of thread-level parallelism and instruction-level parallelism....

  12. Reconfigurable Architecture for Minimizing the Network Delays in the Multi-core Systems

    Directory of Open Access Journals (Sweden)

    D. Venkatavara Prasad

    2015-03-01

    Full Text Available Noc architecture performs better comparing to bus based when the number of processors is small. On the other hand bus based performs better than noc when number of the processors is large. This leads to new architecture which is hybrid bus based architecture where each node is packet switched in a mesh network of noc architecture that contains bus based system with small number of processors. Few results showed that this hybrid architecture performs optimally better than either purely noc based or purely bus based architecture. Hybrid architecture contains a processor connected to the bus, the bus in turn connected to the router. Each processor contains a private Level 1 (L1 cache. When hybrid architecture is preferable, the optimal number of processors on each bus subsystem varies based on the application. Hence the proposed architecture allows scalable bus-based multiprocessor subsystems on each node in the NoC. This system provides a multi-bus execution environment where each processor is connected to a bus and the bus-based subsystems communicate via routers connected in a mesh-style configuration. The system can be reconfigured to vary the number of bus subsystems and the number of processors on each subsystem. This architecture provides reliability and adaptability and reduces the network delays. Implementing and presenting the details of architecture and experimental results using ns2 indicating the advantages of this architecture.

  13. Efficient Architecture for Spike Sorting in Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Sheng-Ying Lai

    2013-11-01

    Full Text Available This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA and fuzzy C-means (FCM algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA. It is embedded in a System-on-Chip (SOC platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

  14. Application-Aware Optimization of Redundant Resources for the Reconfigurable Self-Healing eDNA Hardware Architecture

    DEFF Research Database (Denmark)

    Boesen, Michael Reibel; Madsen, Jan; Pop, Paul

    2011-01-01

    In this paper we are interested in the mapping of embedded applications on a dynamically reconfigurable self-healing hardware architecture known as the eDNA (electronic DNA) architecture. The architecture consists of an array of cells interconnected through a 2D-mesh topology. Each cell consists ...

  15. Application-Aware Optimization of Redundant Resources for the Reconfigurable Self-Healing eDNA Hardware Architecture

    DEFF Research Database (Denmark)

    Boesen, Michael Reibel; Madsen, Jan; Pop, Paul

    2011-01-01

    In this paper we are interested in the mapping of embedded applications on a dynamically reconfigurable self-healing hardware architecture known as the eDNA (electronic DNA) architecture. The architecture consists of an array of cells interconnected through a 2D-mesh topology. Each cell consists ...

  16. Study of heterogeneous and reconfigurable architectures in the communication domain

    Directory of Open Access Journals (Sweden)

    H. T. Feldkaemper

    2003-01-01

    Full Text Available One of the most challenging design issues for next generations of (mobile communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC. For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

  17. Study of heterogeneous and reconfigurable architectures in the communication domain

    Science.gov (United States)

    Feldkaemper, H. T.; Blume, H.; Noll, T. G.

    2003-05-01

    One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

  18. A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications

    Directory of Open Access Journals (Sweden)

    H. Ho

    2009-01-01

    Full Text Available A reconfigurable systolic array (RSA architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE cell is connected to its nearest neighbors via configurable switch (SW elements, enables array expansion for parallel processing and facilitates time sharing computation of high-throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization technique has been employed to reduce the overall number of vector-matrix products to be mapped on the RSA. The hardware complexity and throughput of the RSA-based DFT structures have been evaluated and compared against several conventional modular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase filter circuits are also presented. The RSA architecture offers significant flexibility and computational capacity for applications that require real time reconfiguration and high-density computing.

  19. A Reconfigurable Hybrid Architecture for HomePNA3.1/ Ethernet MAC

    Directory of Open Access Journals (Sweden)

    Mohammad Khalily Dermany

    2011-12-01

    Full Text Available With the growing demands of home networking, the existing networking technologies are not able to satisfy user expectations any more. HomePNA (Home Phoneline Networking Alliance is a solution for having high bandwidth without new cabling.In this paper, we propose a new reconfigurable hybrid architecture for HomePNA3.0. We implement the architecture in behavioural level using VHDL language. Our implementation was able to have HomePNA3.1 and Ethernet MACs together. The system synthesis show that our implementation decrease number of logical element by 32%.

  20. VLSI neuroprocessors

    Science.gov (United States)

    Kemeny, Sabrina E.

    1994-01-01

    Electronic and optoelectronic hardware implementations of highly parallel computing architectures address several ill-defined and/or computation-intensive problems not easily solved by conventional computing techniques. The concurrent processing architectures developed are derived from a variety of advanced computing paradigms including neural network models, fuzzy logic, and cellular automata. Hardware implementation technologies range from state-of-the-art digital/analog custom-VLSI to advanced optoelectronic devices such as computer-generated holograms and e-beam fabricated Dammann gratings. JPL's concurrent processing devices group has developed a broad technology base in hardware implementable parallel algorithms, low-power and high-speed VLSI designs and building block VLSI chips, leading to application-specific high-performance embeddable processors. Application areas include high throughput map-data classification using feedforward neural networks, terrain based tactical movement planner using cellular automata, resource optimization (weapon-target assignment) using a multidimensional feedback network with lateral inhibition, and classification of rocks using an inner-product scheme on thematic mapper data. In addition to addressing specific functional needs of DOD and NASA, the JPL-developed concurrent processing device technology is also being customized for a variety of commercial applications (in collaboration with industrial partners), and is being transferred to U.S. industries. This viewgraph p resentation focuses on two application-specific processors which solve the computation intensive tasks of resource allocation (weapon-target assignment) and terrain based tactical movement planning using two extremely different topologies. Resource allocation is implemented as an asynchronous analog competitive assignment architecture inspired by the Hopfield network. Hardware realization leads to a two to four order of magnitude speed-up over conventional

  1. A coarse-grained reconfigurable computing architecture with loop self-pipelining

    Institute of Scientific and Technical Information of China (English)

    DOU Yong; WU GuiMing; XU JinHui; ZHOU XingMing

    2009-01-01

    Reconfigurable computing tries to achieve the balance between high efficiency of custom computing and flexibility of general-purpose computing. This paper presents the Implementation techniques in LEAP, a coarse-grained reconfigurable array, and proposes a speculative execution mechanism for dynamic loop scheduling with the goal of one iteration per cycle and Implementation techniques to support decoupling synchronization between the token generator and the collector. This paper also in-troduces the techniques of exploiting both data dependences of intra- and inter-Iteration, with the help of two instructions for special data reuses in the loop-carried dependences. The experimental results show that the number of memory accesses reaches on average 3% of an RISC processor simulator with no memory optimization. In a practical Image matching application, LEAP architecture achieves about 34 times of speedup in execution cycles, compared with general-purpose processors.

  2. eDNA: A Bio-Inspired Reconfigurable Hardware Cell Architecture Supporting Self-organisation and Self-healing

    DEFF Research Database (Denmark)

    Boesen, Michael Reibel; Madsen, Jan

    2009-01-01

    This paper presents the concept of a biological inspired reconfigurable hardware cell architecture which supports self-organisation and self-healing. Two fundamental processes in biology, namely fertilization-to-birth and cell self-healing have inspired the development of this cell architecture. ...

  3. Reconfigurable Transceiver and Software-Defined Radio Architecture and Technology Evaluated for NASA Space Communications

    Science.gov (United States)

    Reinhart, Richard C.; Kacpura, Thomas J.

    2004-01-01

    The NASA Glenn Research Center is investigating the development and suitability of a software-based open-architecture for space-based reconfigurable transceivers (RTs) and software-defined radios (SDRs). The main objectives of this project are to enable advanced operations and reduce mission costs. SDRs are becoming more common because of the capabilities of reconfigurable digital signal processing technologies such as field programmable gate arrays and digital signal processors, which place radio functions in firmware and software that were traditionally performed with analog hardware components. Features of interest of this communications architecture include nonproprietary open standards and application programming interfaces to enable software reuse and portability, independent hardware and software development, and hardware and software functional separation. The goals for RT and SDR technologies for NASA space missions include prelaunch and on-orbit frequency and waveform reconfigurability and programmability, high data rate capability, and overall communications and processing flexibility. These operational advances over current state-of-art transceivers will be provided to reduce the power, mass, and cost of RTs and SDRs for space communications. The open architecture for NASA communications will support existing (legacy) communications needs and capabilities while providing a path to more capable, advanced waveform development and mission concepts (e.g., ad hoc constellations with self-healing networks and high-rate science data return). A study was completed to assess the state of the art in RT architectures, implementations, and technologies. In-house researchers conducted literature searches and analysis, interviewed Government and industry contacts, and solicited information and white papers from industry on space-qualifiable RTs and SDRs and their associated technologies for space-based NASA applications. The white papers were evaluated, compiled, and

  4. Research on the Architecture of a Basic Reconfigurable Information Communication Network

    Directory of Open Access Journals (Sweden)

    Ruimin Wang

    2013-01-01

    Full Text Available The current information network cannot fundamentally meet some urgent requirements, such as providing ubiquitous information services and various types of heterogeneous network, supporting diverse and comprehensive network services, possessing high quality communication effects, ensuring the security and credibility of information interaction, and implementing effective supervisory control. This paper provides the theory system for the basic reconfigurable information communication network based on the analysis of present problems on the Internet and summarizes the root of these problems. It also provides an in-depth discussion about the related technologies and the prime components of the architecture.

  5. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  6. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  7. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  8. Real-Time 3D Face Acquisition Using Reconfigurable Hybrid Architecture

    Directory of Open Access Journals (Sweden)

    Mitéran Johel

    2007-01-01

    Full Text Available Acquiring 3D data of human face is a general problem which can be applied in face recognition, virtual reality, and many other applications. It can be solved using stereovision. This technique consists in acquiring data in three dimensions from two cameras. The aim is to implement an algorithmic chain which makes it possible to obtain a three-dimensional space from two two-dimensional spaces: two images coming from the two cameras. Several implementations have already been considered. We propose a new simple real-time implementation based on a hybrid architecture (FPGA-DSP, allowing to consider an embedded and reconfigurable processing. Then we show our method which provides depth map of face, dense and reliable, and which can be implemented on an embedded architecture. A various architecture study led us to a judicious choice allowing to obtain the desired result. The real-time data processing is implemented in an embedded architecture. We obtain a dense face disparity map, precise enough for considered applications (multimedia, virtual worlds, biometrics and using a reliable method.

  9. A HIGH-PERFORMANCE VLSI ARCHITECTURE OF EBCOT BLOCK CODING IN JPEG2000

    Institute of Scientific and Technical Information of China (English)

    Liu Kai; Wu Chengke; Li Yunsong

    2006-01-01

    The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.

  10. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  11. Architecture Logicielles pour des Applications h\\'et\\'erog\\`enes, distribu\\'ees et reconfigurables

    CERN Document Server

    Louberry, Christine; Roose, Philippe

    2008-01-01

    The recent apparition of mobile wireless sensor aware to their physical environment and able to process information must allow proposing applications able to take into account their physical context and to react according to the changes of the environment. It suppose to design applications integrating both software and hardware components able to communicate. Applications must use context information from components to measure the quality of the proposed services in order to adapt them in real time. This work is interested in the integration of sensors in distributed applications. It present a service oriented software architecture allowing to manage and to reconfigure applications in heterogeneous environment where entities of different nature collaborate: software components and wireless sensors.

  12. The Fifth NASA Symposium on VLSI Design

    Science.gov (United States)

    1993-01-01

    The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design.

  13. An implantable VLSI architecture for real time spike sorting in cortically controlled Brain Machine Interfaces.

    Science.gov (United States)

    Aghagolzadeh, Mehdi; Zhang, Fei; Oweiss, Karim

    2010-01-01

    Brain Machine Interface (BMI) systems demand real-time spike sorting to instantaneously decode the spike trains of simultaneously recorded cortical neurons. Real-time spike sorting, however, requires extensive computational power that is not feasible to implement in implantable BMI architectures, thereby requiring transmission of high-bandwidth raw neural data to an external computer. In this work, we describe a miniaturized, low power, programmable hardware module capable of performing this task within the resource constraints of an implantable chip. The module computes a sparse representation of the spike waveforms followed by "smart" thresholding. This cascade restricts the sparse representation to a subset of projections that preserve the discriminative features of neuron-specific spike waveforms. In addition, it further reduces telemetry bandwidth making it feasible to wirelessly transmit only the important biological information to the outside world, thereby improving the efficiency, practicality and viability of BMI systems in clinical applications.

  14. Design and Realization of Array Signal Processor VLSI Architecture for Phased Array System

    Directory of Open Access Journals (Sweden)

    D. Govind Rao

    2016-08-01

    Full Text Available A method for implementing an array signal processor for phased array radars. The array signal processor can receive planar array antenna inputs and can process it. It is based on the application of Adaptive Digital beam formers using FPGAs. Adaptive filter algorithm used here is Inverse Q-R Decomposition based Recursive Least Squares (IQRD-RLS [1] algorithm. Array signal processor based on FPGAs is suitable in the areas of Phased Array Radar receiver, where speed, accuracy and numerical stability are of utmost important. Using IQRD-RLS algorithm, optimal weights are calculated in much less time compared to conventional QRD-RLS algorithm. A customized multiple FPGA board comprising three Kintex-7 FPGAs is employed to implement array signal processor. The proposed architecture can form multiple beams from planar array antenna elements

  15. Opto-VLSI-based photonic true-time delay architecture for broadband adaptive nulling in phased array antennas.

    Science.gov (United States)

    Juswardy, Budi; Xiao, Feng; Alameh, Kamal

    2009-03-16

    This paper proposes a novel Opto-VLSI-based tunable true-time delay generation unit for adaptively steering the nulls of microwave phased array antennas. Arbitrary single or multiple true-time delays can simultaneously be synthesized for each antenna element by slicing an RF-modulated broadband optical source and routing specific sliced wavebands through an Opto-VLSI processor to a high-dispersion fiber. Experimental results are presented, which demonstrate the principle of the true-time delay unit through the generation of 5 arbitrary true-time delays of up to 2.5 ns each.

  16. A new hardware-efficient algorithm and reconfigurable architecture for image contrast enhancement.

    Science.gov (United States)

    Huang, Shih-Chia; Chen, Wen-Chieh

    2014-10-01

    Contrast enhancement is crucial when generating high quality images for image processing applications, such as digital image or video photography, liquid crystal display processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyzes. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 frames/s at high definition resolution 1920 × 1080.

  17. Code generator for implementing dual tree complex wavelet transform on reconfigurable architectures for mobile applications.

    Science.gov (United States)

    Canbay, Ferhat; Levent, Vecdi Emre; Serbes, Gorkem; Ugurdag, H Fatih; Goren, Sezer; Aydin, Nizamettin

    2016-09-01

    The authors aimed to develop an application for producing different architectures to implement dual tree complex wavelet transform (DTCWT) having near shift-invariance property. To obtain a low-cost and portable solution for implementing the DTCWT in multi-channel real-time applications, various embedded-system approaches are realised. For comparison, the DTCWT was implemented in C language on a personal computer and on a PIC microcontroller. However, in the former approach portability and in the latter desired speed performance properties cannot be achieved. Hence, implementation of the DTCWT on a reconfigurable platform such as field programmable gate array, which provides portable, low-cost, low-power, and high-performance computing, is considered as the most feasible solution. At first, they used the system generator DSP design tool of Xilinx for algorithm design. However, the design implemented by using such tools is not optimised in terms of area and power. To overcome all these drawbacks mentioned above, they implemented the DTCWT algorithm by using Verilog Hardware Description Language, which has its own difficulties. To overcome these difficulties, simplify the usage of proposed algorithms and the adaptation procedures, a code generator program that can produce different architectures is proposed.

  18. Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

    Directory of Open Access Journals (Sweden)

    Farouk Smith

    2015-07-01

    Full Text Available This paper propose a Virtual-Field Programmable Gate Array (V-FPGA architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized. By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA; and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm; applying evolution constraints; and optimizing the fitness function. A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness. We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column. Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.

  19. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  20. Wide-range, picoampere-sensitivity multichannel VLSI potentiostat for neurotransmitter sensing.

    Science.gov (United States)

    Murari, Kartikeya; Thakor, Nitish; Stanacevic, Milutin; Cauwenberghs, Gert

    2004-01-01

    Neurotransmitter sensing is critical in studying nervous pathways and neurological disorders. A 16-channel current-measuring VLSI potentiostat with multiple ranges from picoamperes to microamperes is presented for electrochemical detection of electroactive neurotransmitters like dopamine, nitric oxide etc. The analog-to-digital converter design employs a current-mode, first-order single-bit delta-sigma modulator architecture with a two-stage, digitally reconfigurable oversampling ratio for ranging the conversion scale. An integrated prototype is fabricated in CMOS technology, and experimentally characterized. Real-time multi-channel acquisition of dopamine concentration in vitro is performed with a microfabricated sensor array.

  1. A system-level design method for cognitive radio on a reconfigurable multi-processor architecture

    NARCIS (Netherlands)

    Zhang, Qiwei; Kokkeler, A.B.J.; Smit, G.J.M.

    2007-01-01

    The future trend of software defined radio (SDR) platforms moves toward reconfigurable Multiprocessor System-on−Chips (MPSoCs). However, there is a gap between the modelling of the dynamic radio applications and the optimized implementation of the application on reconfigurable multiprocessor archite

  2. Modeling safety instrumented systems with MooN voting architectures addressing system reconfiguration for testing

    Energy Technology Data Exchange (ETDEWEB)

    Torres-Echeverria, A.C., E-mail: alextorres74@yahoo.com.m [Department of Automatic Control and System Engineering, University of Sheffield, Mappin Street, Sheffield S1 3JD (United Kingdom); Martorell, S. [Department of Chemical and Nuclear Engineering, Polytechnic University of Valencia, Cami de Vera sn, 4602 Valencia (Spain); Thompson, H.A. [Department of Automatic Control and System Engineering, University of Sheffield, Mappin Street, Sheffield S1 3JD (United Kingdom)

    2011-05-15

    This paper addresses the modeling of probability of dangerous failure on demand and spurious trip rate of safety instrumented systems that include MooN voting redundancies in their architecture. MooN systems are a special case of k-out-of-n systems. The first part of the article is devoted to the development of a time-dependent probability of dangerous failure on demand model with capability of handling MooN systems. The model is able to model explicitly common cause failure and diagnostic coverage, as well as different test frequencies and strategies. It includes quantification of both detected and undetected failures, and puts emphasis on the quantification of common cause failure to the system probability of dangerous failure on demand as an additional component. In order to be able to accommodate changes in testing strategies, special treatment is devoted to the analysis of system reconfiguration (including common cause failure) during test of one of its components, what is then included in the model. Another model for spurious trip rate is also analyzed and extended under the same methodology in order to empower it with similar capabilities. These two models are powerful enough, but at the same time simple, to be suitable for handling of dependability measures in multi-objective optimization of both system design and test strategies for safety instrumented systems. The level of modeling detail considered permits compliance with the requirements of the standard IEC 61508. The two models are applied to brief case studies to demonstrate their effectiveness. The results obtained demonstrated that the first model is adequate to quantify time-dependent PFD of MooN systems during different system states (i.e. full operation, test and repair) and different MooN configurations, which values are averaged to obtain the PFD{sub avg}. Also, it was demonstrated that the second model is adequate to quantify STR including spurious trips induced by internal component failure

  3. A Reconfigurable Architecture for Rotation Invariant Multi-View Face Detection Based on a Novel Two-Stage Boosting Method

    Directory of Open Access Journals (Sweden)

    Zhengbin Pang

    2009-01-01

    Full Text Available We present a reconfigurable architecture model for rotation invariant multi-view face detection based on a novel two-stage boosting method. A tree-structured detector hierarchy is designed to organize multiple detector nodes identifying pose ranges of faces. We propose a boosting algorithm for training the detector nodes. The strong classifier in each detector node is composed of multiple novelly designed two-stage weak classifiers. With a shared output space of multicomponents vector, each detector node deals with the multidimensional binary classification problems. The design of the hardware architecture which fully exploits the spatial and temporal parallelism is introduced in detail. We also study the reconfiguration of the architecture for finding an appropriate tradeoff among the hardware implementation cost, the detection accuracy, and speed. Experiments on FPGA show that high accuracy and marvelous speed are achieved compared with previous related works. The execution time speedups range from 14.68 to 20.86 for images with size of 160×120 up to 800×600 when our FPGA design (98 MHz is compared with software solution on PC (Pentium 4 2.8 GHz.

  4. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  5. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Science.gov (United States)

    Sabatini, Silvio P.; Solari, Fabio; Cavalleri, Paolo; Bisio, Giacomo Mario

    2003-12-01

    We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth), from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations) on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  6. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Directory of Open Access Journals (Sweden)

    Silvio P. Sabatini

    2003-06-01

    Full Text Available We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth, from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  7. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  8. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  9. A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture

    OpenAIRE

    Biswas, Nripendra N; SRINIVAS, S; Dharanendra, Trishala

    1987-01-01

    The paper describes a multistage shuffle interconnection network which is controlled by a central monitor. A control code broadcast by the monitor to all the basic switching elements of the network simultaneously, makes the network dynamically reconfigurable. The control code plays three vital roles. Firstly, it establishes conflict-free paths between several source-destination pairs. Thus the problem of collision, a major obstacle of a self-routing network,is completely eliminated. Secondly,...

  10. A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams

    Directory of Open Access Journals (Sweden)

    Mühlbauer Felix

    2006-01-01

    Full Text Available This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.

  11. A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams

    Directory of Open Access Journals (Sweden)

    Christophe Bobda

    2006-10-01

    Full Text Available This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.

  12. EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

    OpenAIRE

    Stroobandt, D; Varbanescu, AL; Ciobanu, CB; Al Kadi, M; Brokalakis , A; Charitopoulos, G; Todman, T.; Niu, X.; Pnevmatikatos, D.; A. Kulkarni; Vansteenkiste, E; Luk, W; Santambrogio, MD; Sciuto, D.; Huebner, M

    2016-01-01

    To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the E...

  13. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  14. On reconfigurable tiled multi-core programming

    NARCIS (Netherlands)

    Rovers, Kenneth C.; Burgwal, van de Marcel D.; Kuper, Jan; Kokkeler, Andre B.J.; Smit, Gerard J.M.

    2009-01-01

    For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modelling and programming such systems remains an issue. A semantic model has

  15. Reconfigurable architecture based on fiber bragg gratings for indoor networks (Arquitectura reconfigurable basada en redes de difracción de Bragg para redes convergentes indoor ópticas

    Directory of Open Access Journals (Sweden)

    Gustavo Adolfo Puerto-Leguizamón

    2016-01-01

    Full Text Available This paper presents an approach for dynamic reconfiguration of wavelength channels for future indoor network architectures. The approach exploits the tunability and the rejection profile of Fiber Bragg Gratings (FBG to implement service distribution strategies that includes Unicast, Broadcast and Multicast scenarios for fixed and mobile users. Experimental demonstrations based on two implementations show results with 1% average degradation for Error Vector Magnitude (EVM values and up to 2,2 dB for 1x10-12 Bit Error Rate (BER. In particular, the proposed architectures fit for large in-building networks

  16. Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks

    DEFF Research Database (Denmark)

    Bogdanov, Andrey; Kavun, Elif Bilge; Tischhauser, Elmar

    2012-01-01

    in a vast range of parameters. The new hardware architecture allows us to verify the existing theoretical models for the complexity estimation in linear cryptanalysis. The designed hardware architecture is realized on two Xilinx Virtex-6 XC6VLX240T FPGAs for smaller block lengths, and on RIVYERA platform...... with 128 Xilinx Spartan-3 XC3S5000 FPGAs for larger block lengths....

  17. ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2008-01-01

    links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based...

  18. A reconfigurable function array architecture for 3G and 4G wireless terminals

    NARCIS (Netherlands)

    Heysters, Paul M.; Bouma, Henri; Smit, Jaap; Smit, Gerard J.M.

    2002-01-01

    Advance in low-power hand-held multimedia systems requires exploration of novel system architectures. In conventional computer architectures, an increase in processing power also implies an increase in energy consumption. In a mobile system this results in a shorter operating-time. Limiting the gene

  19. A reconfigurable function array architecture for 3G and 4G wireless terminals

    NARCIS (Netherlands)

    Heysters, P.M.; Bouma, Henri; Smit, Jaap; Smit, Gerardus Johannes Maria; Havinga, Paul J.M.

    Advance in low-power hand-held multimedia systems requires exploration of novel system architectures. In conventional computer architectures, an increase in processing power also implies an increase in energy consumption. In a mobile system this results in a shorter operating-time. Limiting the

  20. A reconfigurable function array architecture for 3G and 4G wireless terminals

    NARCIS (Netherlands)

    Heysters, P.M.; Bouma, Henri; Smit, Jaap; Smit, Gerardus Johannes Maria; Havinga, Paul J.M.

    2002-01-01

    Advance in low-power hand-held multimedia systems requires exploration of novel system architectures. In conventional computer architectures, an increase in processing power also implies an increase in energy consumption. In a mobile system this results in a shorter operating-time. Limiting the gene

  1. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  2. Design and implementation of Gbps VLSI architecture of the cipher engine orienting to IEEE 802.11ac%面向802.11ac的安全加速引擎Gbps VLSI架构设计与实现

    Institute of Scientific and Technical Information of China (English)

    潘志鹏; 吴斌; 尉志伟; 叶甜春

    2015-01-01

    针对IEEE 802.11i协议中多种安全协议实现进行研究,结合以IEEE 802.11ac协议为代表的下一代无线局域网( WLAN)系统对高吞吐率的需求,提出了一种支持WEP/TKIP/CCMP协议的多模、高速安全加速引擎的大规模集成电路( VLSI)架构. 提出了基于哈希算法的密钥信息查找算法,缩小了查找时钟延迟. 基于复合域的运算方式实现高级加密标准( AES)算法,提出双AES运算核的并行架构实现计数器与密码分组链接( CCM)模式,提升运算吞吐率的同时也降低了引擎的响应延迟. 经过FPGA实现和ASIC流片验证表明,该安全加速引擎具备可重构性,处理延迟仅为33个时钟周期,在322 MHz工作频率下运算吞吐率可达3.747 Gbit/s.%In this paper, the implementation of multiple security protocols for IEEE 802.11i was researched. A very large scale integration ( VLSI) architecture of the multi-mode cipher engine supporting WEP/TKIP/CCMP proto-cols was presented taking into account the demand for high throughput of the next generation wireless local area net-work ( WLAN) system that is represented by IEEE 802.11ac. A key searching algorithm based on Hash scheme was proposed to reduce the lookup clock latency. For the high throughput hardware implementation of advanced encryp-tion standard ( AES) algorithm, composite field arithmetic was employed. In order to improve the data throughput and reduce the response time, dual AES computing core with parallel structure was used to implement the cipher block chaining message authentication code ( CCM) mode. The proposed design was implemented in both FPGA and ASIC. The results show that the cipher engine with reconfiguration architecture can achieve 33 clock cycles, and the computing throughput is 3.747 Gbit/s when the work frequency is 322 MHz.

  3. VLSI placement

    Energy Technology Data Exchange (ETDEWEB)

    Hojat, S.

    1986-01-01

    The placement problem of assigning modules to module sites in a regular array must be addressed in VLSI and WSI. The placement problem of assigning heterogeneous modules to module sites in a regular array is NP-complete. The placement problem could be simplified if one could find a footprint with the property that all modules of the optimum placement occupy locations in the footprint, with no vacancies within the footprint region. If such footprints were known, they could be precomputed for each system size and the optimization problem would be reduced to a search of placements meeting the footprint constraint. The author shows that the placement problem could not be simplified by finding footprints. As result, several heuristic algorithms for the placement problem were developed and compared to each other and other established algorithms with respect to time complexity and performance measured, by the expected distance traversed by an intermodule message. Compared to previous algorithms, one new heuristic algorithm gave better performance in a shorter execution time on all test examples.

  4. MT-ADRES: multi-threading on coarse-grained reconfigurable architecture

    DEFF Research Database (Denmark)

    Wu, Kehuai; Kanstein, Andreas; Madsen, Jan;

    2008-01-01

    -ILP architectures achieve only low parallelism when executing partially sequential code segments, which is also known as Amdahl's law, this article proposes to extend ADRES to MT-ADRES (multi-threaded ADRES) to also exploit thread-level parallelism. On MT-ADRES architectures, the array can be partitioned...... in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation...... that exploits a mix of thread-level parallelism and instruction-level parallelism....

  5. Micro-Task Processing in Heterogeneous Reconfigurable Systems

    Institute of Scientific and Technical Information of China (English)

    Sebastian Wallner

    2005-01-01

    New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices (e.g., FPGAs). One of the new promising architectures are Configurable System-on-Chip (CSoC) solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller (mTC) unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results are given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.

  6. Hardware And Software Architectures For Reconfigurable Time-Critical Control Tasks

    Directory of Open Access Journals (Sweden)

    Adam Piłat

    2007-01-01

    Full Text Available The most popular configuration of the controlled laboratory test-rigs is the personalcomputer (PC equipped with the I/O board. The dedicated software components allowsto conduct a wide range of user-defined tasks. The typical configuration functionality canbe customized by PC hardware components and their programmable reconfiguration. Thenext step in the automatic control system design is the embedded solution. Usually, thedesign process of the embedded control system is supported by the high-level software. Thededicated programming tools support multitasking property of the microcontroller by selectionof different sampling frequencies of algorithm blocks. In this case the multi-layer andmultitasking control strategy can be realized on the chip. The proposed solutions implementrapid prototyping approach. The available toolkits and device drivers integrate system-leveldesign environment and the real-time application software, transferring the functionality ofMATLAB/Simulink programs to PCs or microcontrolers application environment.

  7. IMPLEMENTATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR PHYSICAL HYBRID INDICATOR CHANNEL OF LTE-ADVANCED USING PARTIAL RECONFIGURATION IN ML605 VIRTEX-6 DEVICE

    Directory of Open Access Journals (Sweden)

    S. Syed Ameer Abbas

    2014-09-01

    Full Text Available LTE-A (Long Term Evolution-Advanced is the fourth generation technology to increase the speed of wireless data network. The LTE-A Physical layer provides both data and control information between an enhanced base station and mobile user equipment which is quite complex and consists of a mixture of technologies. Since there is requirement for more resources to accommodate all the channels in a single FPGA, Partial Reconfiguration (PR technique is introduced to configure the total hardware into sub modules that configure and operate in different instants of time. PR enables a part of FPGA to be reconfigured, while the rest continues to function without any interruptions and reduces the hardware resource power and fabric area. This work proposes the realization of transmitter and receiver architecture of Physical Hybrid Indicator Channel (PHICH channel for LTE-A using partial reconfiguration on xc6vlx240tff1156-1 FPGA. The receiver architecture for PHICH is to report the correct reception of uplink user data to the User Equipment (UE in the form of Acknowledgment (ACK, or Negative ACK (NACK in a 1 millisecond duration sub-frame of Long Term Evolution (LTE System. The modules for the different diversities are reconfigured based on the control signals from the transmitter.

  8. Integration of the Reconfigurable Self-Healing eDNA Architecture in an Embedded System

    Science.gov (United States)

    Boesen, Michael Reibel; Keymeulen, Didier; Madsen, Jan; Lu, Thomas; Chao, Tien-Hsin

    2011-01-01

    In this work we describe the first real world case study for the self-healing eDNA (electronic DNA) architecture by implementing the control and data processing of a Fourier Transform Spectrometer (FTS) on an eDNA prototype. For this purpose the eDNA prototype has been ported from a Xilinx Virtex 5 FPGA to an embedded system consisting of a PowerPC and a Xilinx Virtex 5 FPGA. The FTS instrument features a novel liquid crystal waveguide, which consequently eliminates all moving parts from the instrument. The addition of the eDNA architecture to do the control and data processing has resulted in a highly fault-tolerant FTS instrument. The case study has shown that the early stage prototype of the autonomous self-healing eDNA architecture is expensive in terms of execution time.

  9. MT-ADRES: multi-threading on coarse-grained reconfigurable architecture

    DEFF Research Database (Denmark)

    Wu, Kehuai; Kanstein, Andreas; Madsen, Jan

    2008-01-01

    in multiple smaller arrays that can execute threads in parallel. Because the partition can be changed dynamically, this extension provides more flexibility than a multi-core approach. This article presents details of the enhanced architecture and results obtained from an MPEG-2 decoder implementation...

  10. Integration of the Reconfigurable Self-Healing eDNA Architecture in an Embedded System

    DEFF Research Database (Denmark)

    Boesen, Michael Reibel; Keymeulen, Didier; Madsen, Jan

    2011-01-01

    In this work we describe the first real world case study for the self-healing eDNA (electronic DNA) architecture by implementing the control and data processing of a Fourier Transform Spectrometer (FTS) on an eDNA prototype. For this purpose the eDNA prototype has been ported from a Xilinx Virtex...

  11. Reconfigurable Equiplets Operating System A Hybrid Architecture to Combine Flexibility and Performance for Manufacturing

    NARCIS (Netherlands)

    Telgen, Daniël; Puik, Erik; Moergestel, leo van; Bakker, Tommas; Meyer, John-Jules

    2015-01-01

    Author supplied: Abstract—The growing importance and impact of new technologies are changing many industries. This effect is especially noticeable in the manufacturing industry. This paper explores a practical implementation of a hybrid architecture for the newest generation of manufacturing systems

  12. Design of a real-time open architecture controller for reconfigurable machine tool

    CSIR Research Space (South Africa)

    Masekamela, I

    2008-06-01

    Full Text Available modular structure in form of modular machines and open architecture controllers that can quickly change the physical structure and appropriately adjust the control system to adapt to the new production requirements. The paper aims to present the design...

  13. Reconfigurable Equiplets Operating System A Hybrid Architecture to Combine Flexibility and Performance for Manufacturing

    NARCIS (Netherlands)

    Daniël Telgen; Ing. Erik Puik; Leo van Moergestel; John-Jules Meyer; Tommas Bakker

    2015-01-01

    Author supplied: Abstract—The growing importance and impact of new technologies are changing many industries. This effect is especially noticeable in the manufacturing industry. This paper explores a practical implementation of a hybrid architecture for the newest generation of manufacturing

  14. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  15. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  16. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...... in connection with VLSI design are defined in terms of Pure Ruby and their properties proved. The design process is illustrated by several non-trivial examples of standard VLSI problems....

  17. Reconfiguration of tree architecture under the effect of wind, competition for light, and annual growth

    Science.gov (United States)

    Eloy, Christophe

    2015-11-01

    In general, trees have self-similar architectures with longer and thicker branches near the roots. Yet, branch segments grown each year always have approximately the same length. This hierarchy of branch lengths and the whole self-similar characteristics results in fact from a continuous process of growth of new branches and shedding of old ones. To assess how such a process affects tree architecture, a functional-structural mechanically-based model of virtual trees is developed. In this model, trees grow into fractal structures to promote efficient photosynthesis in a competing environment. In addition, branch diameters increase in response to wind-induced loads. The results of this model suggest that most self-similar characteristics of trees can be explained by considering that tree are growing structure able to resist mechanical loads due to wind efficiently.

  18. Real-Time Algebraic Derivative Estimations Using a Novel Low-Cost Architecture Based on Reconfigurable Logic

    Directory of Open Access Journals (Sweden)

    Rafael Morales

    2014-05-01

    Full Text Available Time derivative estimation of signals plays a very important role in several fields, such as signal processing and control engineering, just to name a few of them. For that purpose, a non-asymptotic algebraic procedure for the approximate estimation of the system states is used in this work. The method is based on results from differential algebra and furnishes some general formulae for the time derivatives of a measurable signal in which two algebraic derivative estimators run simultaneously, but in an overlapping fashion. The algebraic derivative algorithm presented in this paper is computed online and in real-time, offering high robustness properties with regard to corrupting noises, versatility and ease of implementation. Besides, in this work, we introduce a novel architecture to accelerate this algebraic derivative estimator using reconfigurable logic. The core of the algorithm is implemented in an FPGA, improving the speed of the system and achieving real-time performance. Finally, this work proposes a low-cost platform for the integration of hardware in the loop in MATLAB.

  19. 支持跨粒度重构的制造执行系统体系结构%Manufacturing execution system architecture supporting cross-grain reconfiguration

    Institute of Scientific and Technical Information of China (English)

    黄毅; 郑力; 向晴; 危凯权

    2011-01-01

    To enable Manufacturing Execution Systems (MES) keep working well with related production systems, i.e.response to more intensive & more complicated reconfiguration demand, a Reconfigurable Manufacturing Execution Systems Architecture (RMESA) supporting cross-grained reconfiguration was proposed.Based on reconfiguration demand details, technologies such as domain driven and modularization design were used to decompose MES into module layers with definite responsibility and grain dissimilarity.Main architecture of upper layer was generalized to reduce MES complexity, and modules in lower layer were generalized to collect reusable modules to support modeling in strong cohesion and low coupling.Finally, the proposed architecture was proved to be effective by application example.%为保持制造执行系统与生产系统同步,以响应更密集、更复杂的制造执行系统重构需求,提出一套支持跨粒度重构的制造执行系统体系结构.该结构基于重构需求细节,使用领域驱动设计、模块化设计等技术,将制造执行系统解构为职责明确、粒度相异的模块层级,一方面归纳通用的上层模块主体框架以有效分割制造执行系统的复杂度,另一方面归纳标准的下层模块以支持高内聚、低耦合的模型复用.通过在实际案例中的应用,验证了所提体系结构的有效性.

  20. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  1. VLSI Processor For Vector Quantization

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.

  2. An architecture for the efficient implementation of compressive sampling reconstruction algorithms in reconfigurable hardware

    Science.gov (United States)

    Ortiz, Fernando E.; Kelmelis, Eric J.; Arce, Gonzalo R.

    2007-04-01

    According to the Shannon-Nyquist theory, the number of samples required to reconstruct a signal is proportional to its bandwidth. Recently, it has been shown that acceptable reconstructions are possible from a reduced number of random samples, a process known as compressive sampling. Taking advantage of this realization has radical impact on power consumption and communication bandwidth, crucial in applications based on small/mobile/unattended platforms such as UAVs and distributed sensor networks. Although the benefits of these compression techniques are self-evident, the reconstruction process requires the solution of nonlinear signal processing algorithms, which limit applicability in portable and real-time systems. In particular, (1) the power consumption associated with the difficult computations offsets the power savings afforded by compressive sampling, and (2) limited computational power prevents these algorithms to maintain pace with the data-capturing sensors, resulting in undesirable data loss. FPGA based computers offer low power consumption and high computational capacity, providing a solution to both problems simultaneously. In this paper, we present an architecture that implements the algorithms central to compressive sampling in an FPGA environment. We start by studying the computational profile of the convex optimization algorithms used in compressive sampling. Then we present the design of a pixel pipeline suitable for FPGA implementation, able to compute these algorithms.

  3. K-Channel: A Multifunctional Architecture for Dynamically Reconfigurable Sample Processing in Droplet Microfluidics.

    Science.gov (United States)

    Doonan, Steven R; Bailey, Ryan C

    2017-03-13

    By rapidly creating libraries of thousands of unique, miniaturized reactors, droplet microfluidics provides a powerful method for automating high-throughput chemical analysis. In order to engineer in-droplet assays, microfluidic devices must add reagents into droplets, remove fluid from droplets, and perform other necessary operations, each typically provided by a unique, specialized geometry. Unfortunately, modifying device performance or changing operations usually requires re-engineering the device among these specialized geometries, a time-consuming and costly process when optimizing in-droplet assays. To address this challenge in implementing droplet chemistry, we have developed the "K-channel," which couples a cross-channel flow to the segmented droplet flow to enable a range of operations on passing droplets. K-channels perform reagent injection (0-100% of droplet volume), fluid extraction (0-50% of droplet volume), and droplet splitting (1:1-1:5 daughter droplet ratio). Instead of modifying device dimensions or channel configuration, adjusting external conditions, such as applied pressure and electric field, selects the K-channel process and tunes its magnitude. Finally, interfacing a device-embedded magnet allows selective capture of 96% of droplet-encapsulated superparamagnetic beads during 1:1 droplet splitting events at ∼400 Hz. Addition of a second K-channel for injection (after the droplet splitting K-channel) enables integrated washing of magnetic beads within rapidly moving droplets. Ultimately, the K-channel provides an exciting opportunity to perform many useful droplet operations across a range of magnitudes without requiring architectural modifications. Therefore, we envision the K-channel as a versatile, easy to use microfluidic component enabling diverse, in-droplet (bio)chemical manipulations.

  4. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  5. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  6. VLSI Universal Noiseless Coder

    Science.gov (United States)

    Rice, Robert F.; Lee, Jun-Ji; Fang, Wai-Chi

    1989-01-01

    Proposed universal noiseless coder (UNC) compresses stream of data signals for efficient transmission in channel of limited bandwidth. Noiseless in sense original data completely recoverable from output code. System built as very-large-scale integrated (VLSI) circuit, compressing data in real time at input rates as high as 24 Mb/s, and possibly faster, depending on specific design. Approach yields small, lightweight system operating reliably and consuming little power. Constructed as single, compact, low-power VLSI circuit chip. Design of VLSI circuit chip made specific to code algorithms. Entire UNC fabricated in single chip, worst-case power dissipation less than 1 W.

  7. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  8. VLSI Reliability in Europe

    NARCIS (Netherlands)

    Verweij, Jan F.

    1993-01-01

    Several issue's regarding VLSI reliability research in Europe are discussed. Organizations involved in stimulating the activities on reliability by exchanging information or supporting research programs are described. Within one such program, ESPRIT, a technical interest group on IC reliability was

  9. Reconfigurable Computing for Dynamically Reprogrammable Communications Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This project addresses the need for a framework and domain architecture suitable for reconfigurable transceivers and associated component technologies. The goal of...

  10. Dynamically reconfigurable bio-inspired hardware

    OpenAIRE

    Upegui Posada, Andres Emilio

    2006-01-01

    During the last several years, reconfigurable computing devices have experienced an impressive development in their resource availability, speed, and configurability. Currently, commercial FPGAs offer the possibility of self-reconfiguring by partially modifying their configuration bitstream, providing high architectural flexibility, while guaranteeing high performance. These configurability features have received special interest from computer architects: one can find several reconfigurable c...

  11. A radial basis function neurocomputer implemented with analog VLSI circuits

    Science.gov (United States)

    Watkins, Steven S.; Chau, Paul M.; Tawel, Raoul

    1992-01-01

    An electronic neurocomputer which implements a radial basis function neural network (RBFNN) is described. The RBFNN is a network that utilizes a radial basis function as the transfer function. The key advantages of RBFNNs over existing neural network architectures include reduced learning time and the ease of VLSI implementation. This neurocomputer is based on an analog/digital hybrid design and has been constructed with both custom analog VLSI circuits and a commercially available digital signal processor. The hybrid architecture is selected because it offers high computational performance while compensating for analog inaccuracies, and it features the ability to model large problems.

  12. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  13. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  14. Modular reconfigurable machine tools: design, control and evaluation

    CSIR Research Space (South Africa)

    Padayachee, J

    2009-11-01

    Full Text Available -process capacity scaling. Scalable production capacity and adjustable system functionality are the key objectives of reconfigurable manufacturing. Index terms: Reconfigurable Manufacturing Systems, Modular Reconfigurable Machines, Open Architecture Control...] identify the fixed mechanical architectures and proprietary control systems found in CNC and DMT equipment as the specific drawback in effectively implementing these classes of equipment in RMS. Koren et al.[3] proposed the development of reconfigurable...

  15. A Motion Adaptive De-interlacing Technique and VLSI Architecture%一种运动自适应去隔行技术及其VLSI结构

    Institute of Scientific and Technical Information of China (English)

    普玉伟; 叶兵; 曾德瑞; 蒋特林

    2011-01-01

    An efficient motion adaptive de-interlacing is proposed in this paper. The mixing pixels is classified to fast motion, slow motion or static region according to the motion detection of the same parity field, the corresponding interpolation method is used in different motion region. The edge detection uses the improved ELA algorithm which overcomes the traditional ELA algorithm's deficiency at processing horizontal edge, and the edge is preserved effectively. Compared with motion compensated algorithm, our proposed algorithm required lower computational complexity, and it is easier to implement by VLSI .The experiment shows that the proposed algorithm gains better de-interlacing and high peak signal-to-noise ratio.%提出一种有效的运动自适应去隔行算法.该算法通过对同极性的相邻场进行运动检测,把插值点所处的区域分为快速运动区域、慢速运动区域和静止区域,对不同的区域采用不同的插值算法.在边缘检测方面,采用改进型ELA算法克服了传统的ELA算法处理水平边缘方面的不足,使边缘得到有效保护.与运动补偿算法相比,该算法计算复杂度较低,易于VLSI实现.实验结果显示,该算法取得了良好的去隔行效果和较高的峰值信噪比.

  16. NASA Space Engineering Research Center for VLSI systems design

    Science.gov (United States)

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  17. Very Large Scale Integration (VLSI).

    Science.gov (United States)

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  18. New Methodologies for Parallel Architecture

    Institute of Scientific and Technical Information of China (English)

    Dong-Rui Fan; Xiao-Wei Li; Guo-Jie Li

    2011-01-01

    Moore's law continues to grant computer architects ever more transistors in the foreseeable future,and parallelism is the key to continued performance scaling in modern microprocessors.In this paper,the achievements in our research project,which is supported by the National Basic Research 973 Program of China,on parallel architecture,are systematically presented.The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized,including architecture level optimization,compiler and languag~supported technologies,reliability,power-performance efficient design,test and verification challenges,and platform building.Two prototype chips,a multiheavy-core Godson-3 and a many-light-core Godson-T,are described to demonstrate the highly scalable and reconfigurable parallel architecture designs.We also present some of our achievements appearing in ISCA,MICRO,ISSCC,HPCA,PLDI,PACT,IJCAI,Hot Chips,DATE,IEEE Trans.VLSI,IEEE Micro,IEEE Trans.Computers,etc.

  19. An 8×8/4×4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4K×2K H.264/AVC Encoder

    Science.gov (United States)

    Fan, Yibo; Liu, Jialiang; Zhang, Dexue; Zeng, Xiaoyang; Chen, Xinhua

    Fidelity Range Extension (FRExt) (i.e. High Profile) was added to the H.264/AVC recommendation in the second version. One of the features included in FRExt is the Adaptive Block-size Transform (ABT). In order to conform to the FRExt, a Fractional Motion Estimation (FME) architecture is proposed to support the 8×8/4×4 adaptive Hadamard Transform (8×8/4×4 AHT). The 8×8/4×4 AHT circuit contributes to higher throughput and encoding performance. In order to increase the utilization of SATD (Sum of Absolute Transformed Difference) Generator (SG) in unit time, the proposed architecture employs two 8-pel interpolators (IP) to time-share one SG. These two IPs can work in turn to provide the available data continuously to the SG, which increases the data throughput and significantly reduces the cycles that are needed to process one Macroblock. Furthermore, this architecture also exploits the linear feature of Hadamard Transform to generate the quarter-pel SATD. This method could help to shorten the long datapath in the second-step of two-iteration FME algorithm. Finally, experimental results show that this architecture could be used in the applications requiring different performances by adjusting the supported modes and operation frequency. It can support the real-time encoding of the seven-mode 4K×2K@24fps or six-mode 4K×2K@30fps video sequences.

  20. Reconfigurable antennas

    CERN Document Server

    Bernhard, Jennifer

    2007-01-01

    This lecture explores the emerging area of reconfigurable antennas from basic concepts that provide insight into fundamental design approaches to advanced techniques and examples that offer important new capabilities for next-generation applications. Antennas are necessary and critical components of communication and radar systems, but sometimes their inability to adjust to new operating scenarios can limit system performance. Making antennas reconfigurable so that their behavior can adapt with changing system requirements or environmental conditions can ameliorate or eliminate these restricti

  1. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  2. An Efficient Architecture Design of Reconfigurable Float-point FFT Processor%高效可配置浮点FFT处理器设计

    Institute of Scientific and Technical Information of China (English)

    桑红石; 高伟

    2012-01-01

    Large resource cost is the design bottleneck of high-precision float-point FFT processor,a novel R2/22SDF reconfigurable architecture using shared-butterfly which employs single-port-based FIFO.Radix 2/22algorithm and pipeline architecture,which is suitable for float-point design,can reduce the multiplicative complexity and improve the multiplication efficiency.The FIFO memory using double-width single-port ram can avoid the larger area and power coat of dual-port ram.Two butterfly units can be merged by the proposed shared-butterfly architecture,which solves the low utilization factor problem of traditional single-path-delay-feedback architecture.The float-point design cost is efficiently reduced and the calculator utilization factor is improved,compared with the traditional pipeline method.%为了克服高精度浮点FFT处理器具有较大资源开销的设计瓶颈,采用基于单口存储器的FIFO构建共享蝶形结构的R2/22SDF流水可配置结构.采用适合浮点设计的基2/22算法实现流水结构,不仅有利于可配置电路的实现,还能够有效减少复数乘法次数,提高复数乘法器的计算效率.采用双倍数据位宽的单口存储器实现FIFO存储器,有效避免了双口存储器面积和功耗较大的问题.改进的蝶形共享结构实现两级蝶形的合并,解决了单路径延迟反馈流水线结构蝶形单元利用率低的问题.与传统流水线结构FFT处理器设计相比,有效降低了浮点设计中的资源开销,提高了计算单元的利用效率.

  3. Resource optimised reconfigurable modular parallel pipelined stochastic approximation-based self-tuning regulator architecture with reduced latency

    Directory of Open Access Journals (Sweden)

    Varghese Mathew Vaidyan

    2015-09-01

    Full Text Available Present self-tuning regulator architectures based on recursive least-square estimation are computationally expensive and require large amount of resources and time in generating the first control signal due to computational bottlenecks imposed by the calculations involved in estimation stage, different stages of matrix multiplications and the number of intermediate variables at each iteration and precludes its use in applications that have fast required response times and those which run on embedded computing platforms with low-power or low-cost requirements with constraints on resource usage. A salient feature of this study is that a new modular parallel pipelined stochastic approximation-based self-tuning regulator architecture which reduces the time required to generate the first control signal, reduces resource usage and reduces the number of intermediate variables is proposed. Fast matrix multiplication, pipelining and high-speed arithmetic function implementations were used for improving the performance. Results of implementation demonstrate that the proposed architecture has an improvement in control signal generation time by 38% and reduction in resource usage by 41% in terms of multipliers and 44.4% in terms of adders compared with the best existing related work, opening up new possibilities for the application of online embedded self-tuning regulators.

  4. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  5. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  6. Lunar Applications in Reconfigurable Computing

    Science.gov (United States)

    Somervill, Kevin

    2008-01-01

    NASA s Constellation Program is developing a lunar surface outpost in which reconfigurable computing will play a significant role. Reconfigurable systems provide a number of benefits over conventional software-based implementations including performance and power efficiency, while the use of standardized reconfigurable hardware provides opportunities to reduce logistical overhead. The current vision for the lunar surface architecture includes habitation, mobility, and communications systems, each of which greatly benefit from reconfigurable hardware in applications including video processing, natural feature recognition, data formatting, IP offload processing, and embedded control systems. In deploying reprogrammable hardware, considerations similar to those of software systems must be managed. There needs to be a mechanism for discovery enabling applications to locate and utilize the available resources. Also, application interfaces are needed to provide for both configuring the resources as well as transferring data between the application and the reconfigurable hardware. Each of these topics are explored in the context of deploying reconfigurable resources as an integral aspect of the lunar exploration architecture.

  7. Mixed voltage VLSI design

    Science.gov (United States)

    Panwar, Ramesh; Rennels, David; Alkalaj, Leon

    1993-01-01

    A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

  8. Reconfigurable Computing

    CERN Document Server

    Cardoso, Joao MP

    2011-01-01

    As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a comp

  9. Organizational Reconfiguration and Strategic Response

    DEFF Research Database (Denmark)

    Møller Larsen, Marcus; Pedersen, Torben

    2014-01-01

    The purpose of this paper is to investigate the effect of the organizational reconfiguration of offshoring on firms’ strategies. A consequence of offshoring is the need to reintegrate the geographically relocated organizational activities into a coherent organizational architecture. In order to do...

  10. Opto-VLSI-based N × M wavelength selective switch.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal

    2013-07-29

    In this paper, we propose and experimentally demonstrate a novel N × M wavelength selective switch (WSS) architecture based on the use of an Opto-VLSI processor. Through a two-stage beamsteering process, wavelength channels from any input optical fiber port can be switched into any output optical fiber port. A proof-of-concept 2 × 3 WSS structure is developed, demonstrating flexible wavelength selective switching with an insertion loss around 15 dB.

  11. VLSI circuits for bidirectional interface to peripheral and visceral nerves.

    Science.gov (United States)

    Greenwald, Elliot; Wang, Qihong; Thakor, Nitish V

    2015-08-01

    This paper presents an architecture for sensing nerve signals and delivering functional electrical stimulation to peripheral and visceral nerves. The design is based on the very large scale integration (VLSI) technology and amenable to interface to microelectrodes and building a fully implantable system. The proposed stimulator was tested on the vagus nerve and is under further evaluation and testing of various visceral nerves and their functional effects on the innervated organs.

  12. VLSI circuits for high speed data conversion

    Science.gov (United States)

    Wooley, Bruce A.

    1994-05-01

    The focus of research has been the study of fundamental issues in the design and testing of data conversion interfaces for high performance VLSI signal processing and communications systems. Because of the increased speed and density that accompany the continuing scaling of VLSI technologies, digital means of processing, communicating, and storing information are rapidly displacing their analog counterparts across a broadening spectrum of applications. In such systems, the limitations on system performance generally occur at the interfaces between the digital representation of information and the analog environment in which the system is embedded. Specific results of this research include the design and implementation of low-power BiCMOS comparators and sample-and-hold amplifiers operating at clock rates as high as 200 MHz, the design and integration of a 12-bit, 5 MHz CMOS A/D converter employing a two-step architecture and a novel self-calibrating comparator, the design and integration of an optoelectronic communications receiver front-end in a GaAs-on-Si technology, the initiation of research into the use of an active silicon substrate probe card for fully testing high-performance mixed-signal circuits at the wafer level, and a preliminary study of means for correcting dynamic errors in high-performance A/D converters.

  13. Image processing using reconfigurable FPGAs

    Science.gov (United States)

    Ferguson, Lee

    1996-10-01

    The use of reconfigurable field-programmable gate arrays (FPGAs) for imaging applications show considerable promise to fill the gap that often occurs when digital signal processor chips fail to meet performance specifications. Single chip DSPs do not have the overall performance to meet the needs of many imaging applications, particularly in real-time designs. Using multiple DSPs to boost performance often presents major design challenges in maintaining data alignment and process synchronization. These challenges can impose serious cost, power consumption and board space penalties. Image processing requires manipulating massive amounts of data at high-speed. Although DSP chips can process data at high-speeds, their architectures can inhibit overall system performance in real-time imaging. The rate of operations can be increased when they are performed in dedicated hardware, such as special-purpose imaging devices and FPGAs, which provides the horsepower necessary to implement real-time image processing products successfully and cost-effectively. For many fixed applications, non-SRAM- based (antifuse or flash-based) FPGAs provide the raw speed to accomplish standard high-speed functions. However, in applications where algorithms are continuously changing and compute operations must be modified, only SRAM-based FPGAs give enough flexibility. The addition of reconfigurable FPGAs as a flexible hardware facility enables DSP chips to perform optimally. The benefits primarily stem from optimizing the hardware for the algorithms or the use of reconfigurable hardware to enhance the product architecture. And with SRAM-based FPGAs that are capable of partial dynamic reconfiguration, such as the Cache-Logic FPGAs from Atmel, continuous modification of data and logic is not only possible, it is practical as well. First we review the particular demands of image processing. Then we present various applications and discuss strategies for exploiting the capabilities of

  14. Synaptic dynamics in analog VLSI.

    Science.gov (United States)

    Bartolozzi, Chiara; Indiveri, Giacomo

    2007-10-01

    Synapses are crucial elements for computation and information transfer in both real and artificial neural systems. Recent experimental findings and theoretical models of pulse-based neural networks suggest that synaptic dynamics can play a crucial role for learning neural codes and encoding spatiotemporal spike patterns. Within the context of hardware implementations of pulse-based neural networks, several analog VLSI circuits modeling synaptic functionality have been proposed. We present an overview of previously proposed circuits and describe a novel analog VLSI synaptic circuit suitable for integration in large VLSI spike-based neural systems. The circuit proposed is based on a computational model that fits the real postsynaptic currents with exponentials. We present experimental data showing how the circuit exhibits realistic dynamics and show how it can be connected to additional modules for implementing a wide range of synaptic properties.

  15. An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing

    Directory of Open Access Journals (Sweden)

    Doumenis Demosthenes

    2011-01-01

    Full Text Available QAM is a widely used multilevel modulation technique, with a variety of applications in data radio communication systems. Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraints of emerging applications. This work presents the architecture of a highly parallel QAM modulator, using MPSoC-based design flow and design methodology, which offers multirate modulation. The proposed MPSoC architecture is modular and provides dynamic reconfiguration of the QAM utilizing on-chip interconnection networks, offering high data rates (more than 1 Gbps, even at low modulation levels (16-QAM. Furthermore, the proposed QAM implementation integrates a hardware-based resource allocation algorithm that can provide better throughput and fault tolerance, depending on the on-chip interconnection network congestion and run-time faults. Preliminary results from this work have been published in the Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010. The current version of the work includes a detailed description of the proposed system architecture, extends the results significantly using more test cases, and investigates the impact of various design parameters. Furthermore, this work investigates the use of the hardware resource allocation algorithm as a graceful degradation mechanism, providing simulation results about the performance of the QAM in the presence of faulty components.

  16. VLSI IMPLEMENTATION OF CHANNEL ESTIMATION FOR MIMO-OFDM TRANSCEIVER

    Directory of Open Access Journals (Sweden)

    Joseph Gladwin Sekar

    2013-01-01

    Full Text Available In this study the VLSI architecture for MIMO-OFDM transceiver and the algorithm for the implementation of MMSE detection in MIMO-OFDM system is proposed. The implemented MIMO-OFDM system is capable of transmitting data at high throughput in physical layer and provides optimized hardware resources while achieving the same data rate. The proposed architecture has low latency, high throughput and efficient resource utilization. The result obtained is compared with the MATLAB results for verification. The main aim is to reduce the hardware complexity of the channel estimation.

  17. Design of Analog VLSI Architecture for DCT

    OpenAIRE

    2012-01-01

    When implementing real-time DSP algorithms on digital circuits, the system is always constrained by limited speed, accuracy and roundoff noise. These limitations must be taken into account for the design and implementation stages. Doubling the dynamic rate of theanalog DCT is expensive, whereas in digital DCT an addition of 1 bit in data path is adequate. This paper proposes a novel approach ofanalog CMOS implementation technique for Digital Signal Processing (DSP) algorithms to reduce the ar...

  18. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  19. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  20. Realization of Reconfigurable Virtual Environments for Virtual Testing

    Institute of Scientific and Technical Information of China (English)

    Wen-Yan Wu; Zheng-Xu Zhao

    2005-01-01

    This paper presents the design and implementation of reconfigurable virtual environments (VEs) for virtual testing. It proposes a hybrid design approach that is derived from a so-called integration and composition of the reconfiguration strategy. The designing process has thus evolved from binding virtual objects using reconfiguration rules within the context of virtual testing scenarios. Therefore reconfigurable virtual environments are established with improved flexibility and scalability, tailored to a wide range of virtual testing applications. Those virtual environments integrate virtual testing scenarios, data acquisition, databases, rule mapping and application interfaces, which yield modular testing functions and an open-ended system architecture with a set of extensible interface tools to realize data exchange within reconfigurable VEs.This enables virtual testing scenarios to be reconfigured interactively based on real time data and communication between virtual environments and real environments. A virtual testing application has been implemented using reconfigurable VEs.

  1. Parallel optical interconnects utilizing VLSI/FLC spatial light modulators

    Science.gov (United States)

    Genco, Sheryl M.

    1991-12-01

    Interconnection architectures are a cornerstone of parallel computing systems. However, interconnections can be a bottleneck in conventional computer architectures because of queuing structures that are necessary to handle the traffic through a switch at very high data rates and bandwidths. These issues must find new solutions to advance the state of the art in computing beyond the fundamental limit of silicon logic technology. Today's optoelectronic (OE) technology in particular VLSI/FLC spatial light modulators (SLMs) can provide a unique and innovative solution to these issues. This paper reports on the motivations for the system, describes the major areas of architectural requirements, discusses interconnection topologies and processor element alternatives, and documents an optical arbitration (i.e., control) scheme using `smart' SLMs and optical logic gates. The network topology is given in section 2.1 `Architectural Requirements -- Networks,' but it should be noted that the emphasis is on the optical control scheme (section 2.4) and the system.

  2. A Design Methodology for Optoelectronic VLSI

    Science.gov (United States)

    2007-01-01

    it for the layout of large-scale VLSI circuits such as bit-parallel datapaths , crossbars, RAMs, megacells and cores. These VLSI circuits have custom...by the 64-bit ALU and the 64-bit register file circuits. Typically, these VLSI circuits use a datapath layout style that creates a highly regular row...and column structure. The datapath layout style is preferred for multiple-bit processing circuits because it achieves uniform timing for all bits in a

  3. A Coherent VLSI Environment

    Science.gov (United States)

    1987-03-31

    smallest and largest eigenvalues of YH and AminAH and Am,..AH represent the smallest and largest eigenvalues of YAH, respectively. Fig. 3b illustrates a...101, Princeton U. Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International

  4. Three-dimensional design methodologies for tree-based FPGA architecture

    CERN Document Server

    Pangracious, Vinod; Mehrez, Habib

    2015-01-01

    This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

  5. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors

    Directory of Open Access Journals (Sweden)

    S. K. Nandy

    1994-01-01

    Full Text Available Design Rule Checking is a compute-intensive VLSI CAD tool. In this paper we propose a parallel algorithm to perform Design Rule Check (DRC of Layout geometries in a VLSI layout. The algorithm assumes the parallel architecture to be a two-dimensional mesh of processors. The algorithm is based on a linear quadtree representation of the layout. Through a complexity analysis it is shown that it is possible to achieve a linear speedup in DRC with respect to the number of processors.

  6. VLSI Watermark Implementations and Applications

    OpenAIRE

    Shoshan, Yonatan; Fish, Alexander; Li, Xin; Jullien, Graham,; Yadid-Pecht, Orly

    2008-01-01

    This paper presents an up to date review of digital watermarking (WM) from a VLSI designer point of view. The reader is introduced to basic principles and terms in the field of image watermarking. It goes through a brief survey on WM theory, laying out common classification criterions and discussing important design considerations and trade-offs. Elementary WM properties such as robustness, computational complexity and their influence on image quality are discussed. Common att...

  7. RESEARCH ON FRAMEWORK OF RAPIDLY RECONFIGURABLE INFORMATION SYSTEM

    Institute of Scientific and Technical Information of China (English)

    LiXurong; DingQiulin; XuHuanliang

    2002-01-01

    Changes and reconfiguration of information systems(ISs)are two kernel concepts of rapidil reconfigurable in-formation system(RRIS).It is the abilitise to evolve with changes that make RRIS superior to the traditional ISs.Hierarchical architecture of RRIS is put forward.And then a component-based framework of RRIS is discussed including its building and designing in detail.

  8. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides.Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  9. Implementation of Plasmonics in VLSI

    Directory of Open Access Journals (Sweden)

    Shreya Bhattacharya

    2012-12-01

    Full Text Available This Paper presents the idea of Very Large Scale Integration (VLSI using Plasmonic Waveguides. Current VLSI techniques are facing challenges with respect to clock frequencies which tend to scale up, making it more difficult for the designers to distribute and maintain low clock skew between these high frequency clocks across the entire chip. Surface Plasmons are light waves that occur at a metal/dielectric interface, where a group of electrons is collectively moving back and forth. These waves are trapped near the surface as they interact with the plasma of electrons near the surface of the metal. The decay length of SPs into the metal is two orders of magnitude smaller than the wavelength of the light in air. This feature of SPs provides the possibility of localization and the guiding of light in sub wavelength metallic structures, and it can be used to construct miniaturized optoelectronic circuits with sub wavelength components. In this paper, various methods of doing the same have been discussed some of which include DLSPPW’s, Plasmon waveguides by self-assembly, Silicon-based plasmonic waveguides etc. Hence by using Plasmonic chips, the speed, size and efficiency of microprocessor chips can be revolutionized thus bringing a whole new dimension to VLSI design.

  10. Reconfigurable network processing platforms

    NARCIS (Netherlands)

    Kachris, C.

    2007-01-01

    This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network pr

  11. DESIGN OF A RECONFIGURABLE DSP PROCESSOR WITH BIT EFFICIENT RESIDUE NUMBER SYSTEM

    Directory of Open Access Journals (Sweden)

    Chaitali Biswas Dutta

    2012-10-01

    Full Text Available Residue Number System (RNS, which originates from the Chinese Remainder Theorem, offers a promising future in VLSI because of its carry-free operations in addition, subtraction and multiplication. This property of RNS is very helpful to reduce the complexity of calculation in many applications. A residue number system represents a large integer using a set of smaller integers, called residues. But the area overhead, cost and speed not only depend on this word length, but also the selection of moduli, which is a very crucial step for residue system. This parameter determines bit efficiency, area, frequency etc. In this paper a new moduli set selection technique is proposed to improve bit efficiency which can be used to construct a residue system for digital signal processing environment. Subsequently, it is theoretically proved and illustrated using examples, that the proposed solution gives better results than the schemes reported in the literature. The novelty of the architecture is shown by comparison the different schemes reported in the literature. Using the novel moduli set, a guideline for a Reconfigurable Processor is presented here that can process some predefined functions. As RNS minimizes the carry propagation, the scheme can be implemented in Real Time Signal Processing & other fields where high speed computations are required.

  12. An Efficient Micro Control Unit with a Reconfigurable Filter Design for Wireless Body Sensor Networks (WBSNs

    Directory of Open Access Journals (Sweden)

    Chiung-An Chen

    2012-11-01

    Full Text Available In this paper, a low-cost, low-power and high performance micro control unit (MCU core is proposed for wireless body sensor networks (WBSNs. It consists of an asynchronous interface, a register bank, a reconfigurable filter, a slop-feature forecast, a lossless data encoder, an error correct coding (ECC encoder, a UART interface, a power management (PWM, and a multi-sensor controller. To improve the system performance and expansion abilities, the asynchronous interface is added for handling signal exchanges between different clock domains. To eliminate the noise of various bio-signals, the reconfigurable filter is created to provide the functions of average, binomial and sharpen filters. The slop-feature forecast and the lossless data encoder is proposed to reduce the data of various biomedical signals for transmission. Furthermore, the ECC encoder is added to improve the reliability for the wireless transmission and the UART interface is employed the proposed design to be compatible with wireless devices. For long-term healthcare monitoring application, a power management technique is developed for reducing the power consumption of the WBSN system. In addition, the proposed design can be operated with four different bio-sensors simultaneously. The proposed design was successfully tested with a FPGA verification board. The VLSI architecture of this work contains 7.67-K gate counts and consumes the power of 5.8 mW or 1.9 mW at 100 MHz or 133 MHz processing rate using a TSMC 0.18 μm or 0.13 μm CMOS process. Compared with previous techniques, this design achieves higher performance, more functions, more flexibility and higher compatibility than other micro controller designs.

  13. Reconfigurable Secondary Composite Building Blocks for Expandable Habitable Structure Project

    Data.gov (United States)

    National Aeronautics and Space Administration — ZIN Technologies, Inc. will provide a preliminary design showing the feasibility of a Reconfigurable Multi-functional Architecture (RMA) for a deployable floor...

  14. Reconfigurable antenna pattern verification

    Science.gov (United States)

    Drexler, Jerome P. (Inventor); Becker, Robert C. (Inventor); Meyers, David W. (Inventor); Muldoon, Kelly P. (Inventor)

    2013-01-01

    A method of verifying programmable antenna configurations is disclosed. The method comprises selecting a desired antenna configuration from a plurality of antenna configuration patterns, with the selected antenna configuration forming at least one reconfigurable antenna from reconfigurable antenna array elements. The method validates the formation of the selected antenna configuration to determine antenna performance of the at least one reconfigurable antenna.

  15. Review: “Implementation of Feedforward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology”

    Directory of Open Access Journals (Sweden)

    Miss. Rachana R. Patil

    2015-01-01

    Full Text Available Main focus of project is on implementation of Neural Network Architecture (NNA with on chip learning on Analog VLSI Technology for signal processing application. In the proposed paper the analog components like Gilbert Cell Multiplier (GCM, Neuron Activation Function (NAF are used to implement artificial NNA. Analog components used comprises of multiplier, adder and tan sigmoidal function circuit using MOS transistor. This Neural Architecture is trained using Back Propagation (BP Algorithm in analog domain with new techniques of weight storage. Layout design and verification of above design is carried out using VLSI Backend Microwind 3.1 software Tool. The technology used to design layout is 32 nm CMOS Technology

  16. Reconfigurable Communication Processor:A New Approach for Network Processor

    Institute of Scientific and Technical Information of China (English)

    孙华; 陈青山; 张文渊

    2003-01-01

    As the traditional RISC +ASIC/ASSP approach for network processor design can not meet the today'srequirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost theperformance to ASIC level while reserve the programmability of the traditional RISC based system. This papercovers both the hardware architecture and the software development environment architecture.

  17. Researching and implementation of reconfigurable Hash chip based on FPGA

    Institute of Scientific and Technical Information of China (English)

    Yang Xiaohui; Dai Zibin; Liu Yuanfeng; Wang Ting

    2007-01-01

    The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be flexibly implemented with the aid of a reconfigurable cryptographic chip and can be used in many fields. This article takes an example for the SHA-1/224/256 algorithms, and then designs a reconfigurable cryptographic chip based on the thought and method of the reconfigurable architecture. Finally, this paper gives the implementation result based on the FPGA of the family of Stratix II of Altera Corporation, and presents a good research trend for resolving the storage in hardware implementation using FPGAs.

  18. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  19. Towards Shop Floor Hardware Reconfiguration for Industrial Collaborative Robots

    DEFF Research Database (Denmark)

    Schou, Casper; Madsen, Ole

    2016-01-01

    In this paper we propose a roadmap for hardware reconfiguration of industrial collaborative robots. As a flexible resource, the collaborative robot will often need transitioning to a new task. Our goal is, that this transitioning should be done by the shop floor operators, not highly specialized...... engineers. The hard- ware reconfiguration framework adopts a modular architecture for the collabo- rative robot which dictates a clear segmentation of the robot into well-defined exchangeable modules. Four main objectives for the hardware reconfiguration framework; 1) Modular architecture, 2) Module...

  20. Anti-Tamper Method for Field Programmable Gate Arrays Through Dynamic Reconfiguration and Decoy Circuits

    Science.gov (United States)

    2008-03-27

    Reconfigurable FPGAs”. IEICE Trans. Fundam. Electron . Commun. Comput. Sci., E89-A(12):3416–3426, 2006. ISSN 0916-8508. 42. Tseng, C. “Lock Your Designs...Implementation of the Advanced Encryption Standard”. IEEE Transactions on Computers, 52(4):493–505, April 2003. URL http://euler.ecs.umass.edu/research...Bushnell, Vishwani D. Agrawal. Essentials of Electronic Testing for Digital Memory & Mixed-Signal VLSI Circuits. Springer, 2000. ISBN 0-7923- 7991-8. 35

  1. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  2. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  3. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  4. VLSI implementation of neural networks.

    Science.gov (United States)

    Wilamowski, B M; Binfet, J; Kaynak, M O

    2000-06-01

    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more complex and hard to train, but provide an outstanding control surface with much less error than that of a fuzzy controller. There are also some problems that have to be solved before the networks can be implemented on VLSI chips. First, an approximation function needs to be developed because CMOS neural networks have an activation function different than any function used in neural network software. Next, this function has to be used to train the network. Finally, the last problem for VLSI designers is the quantization effect caused by discrete values of the channel length (L) and width (W) of MOS transistor geometries. Two neural networks were designed in 1.5 microm technology. Using adequate approximation functions solved the problem of activation function. With this approach, trained networks were characterized by very small errors. Unfortunately, when the weights were quantized, errors were increased by an order of magnitude. However, even though the errors were enlarged, the results obtained from neural network hardware implementations were superior to the results obtained with fuzzy system approach.

  5. Event-driven neural integration and synchronicity in analog VLSI.

    Science.gov (United States)

    Yu, Theodore; Park, Jongkil; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

    2012-01-01

    Synchrony and temporal coding in the central nervous system, as the source of local field potentials and complex neural dynamics, arises from precise timing relationships between spike action population events across neuronal assemblies. Recently it has been shown that coincidence detection based on spike event timing also presents a robust neural code invariant to additive incoherent noise from desynchronized and unrelated inputs. We present spike-based coincidence detection using integrate-and-fire neural membrane dynamics along with pooled conductance-based synaptic dynamics in a hierarchical address-event architecture. Within this architecture, we encode each synaptic event with parameters that govern synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. Spike-based coincidence detection is observed and analyzed in measurements on a log-domain analog VLSI implementation of the integrate-and-fire neuron and conductance-based synapse dynamics.

  6. Design, Development and Pre-Flight Testing of the Communications, Navigation, and Networking Reconfigurable Testbed (Connect) to Investigate Software Defined Radio Architecture on the International Space Station

    Science.gov (United States)

    Over, Ann P.; Barrett, Michael J.; Reinhart, Richard C.; Free, James M.; Cikanek, Harry A., III

    2011-01-01

    The Communication Navigation and Networking Reconfigurable Testbed (CoNNeCT) is a NASA-sponsored mission, which will investigate the usage of Software Defined Radios (SDRs) as a multi-function communication system for space missions. A softwaredefined radio system is a communication system in which typical components of the system (e.g., modulators) are incorporated into software. The software-defined capability allows flexibility and experimentation in different modulation, coding and other parameters to understand their effects on performance. This flexibility builds inherent redundancy and flexibility into the system for improved operational efficiency, real-time changes to space missions and enhanced reliability/redundancy. The CoNNeCT Project is a collaboration between industrial radio providers and NASA. The industrial radio providers are providing the SDRs and NASA is designing, building and testing the entire flight system. The flight system will be integrated on the Express Logistics Carrier (ELC) on the International Space Station (ISS) after launch on the H-IIB Transfer Vehicle in 2012. This paper provides an overview of the technology research objectives, payload description, design challenges and pre-flight testing results.

  7. Reconfigurable environmentally adaptive computing

    Science.gov (United States)

    Coxe, Robin L. (Inventor); Galica, Gary E. (Inventor)

    2008-01-01

    Described are methods and apparatus, including computer program products, for reconfigurable environmentally adaptive computing technology. An environmental signal representative of an external environmental condition is received. A processing configuration is automatically selected, based on the environmental signal, from a plurality of processing configurations. A reconfigurable processing element is reconfigured to operate according to the selected processing configuration. In some examples, the environmental condition is detected and the environmental signal is generated based on the detected condition.

  8. Introduction to Reconfigurable Supercomputing

    CERN Document Server

    Lanzagorta, Marco; Rosenberg, Robert

    2010-01-01

    This book covers technologies, applications, tools, languages, procedures, advantages, and disadvantages of reconfigurable supercomputing using Field Programmable Gate Arrays (FPGAs). The target audience is the community of users of High Performance Computers (HPe who may benefit from porting their applications into a reconfigurable environment. As such, this book is intended to guide the HPC user through the many algorithmic considerations, hardware alternatives, usability issues, programming languages, and design tools that need to be understood before embarking on the creation of reconfigur

  9. Reconfigurable logic design case

    Science.gov (United States)

    Ma, Shing-Fat F.; Knight, John; Plett, Calvin

    2002-07-01

    This design case identifies generalizable features of a course-grained reconfigurable FPGA, Chameleon's reconfigurable platform. An FFT is used to identify typical design practices, problems, and solutions in targeting such a platform. This paper focuses on datapath mapping, separating it into functional design and placement of reconfigurable resources. In addition to exploring the design methodology, it analyzes numerical artifacts, demonstrates efficient packing of the data path, and highlights differences from ASIC design.

  10. A dynamically reconfigurable data stream processing system

    Energy Technology Data Exchange (ETDEWEB)

    Nogiec, J.M.; Trombly-Freytag, K.; /Fermilab

    2004-11-01

    This paper describes a component-based framework for data stream processing that allows for configuration, tailoring, and runtime system reconfiguration. The system's architecture is based on a pipes and filters pattern, where data is passed through routes between components. A network of pipes and filters can be dynamically reconfigured in response to a preplanned sequence of processing steps, operator intervention, or a change in one or more data streams. This framework provides several mechanisms supporting dynamic reconfiguration and can be used to build static data stream processing applications such as monitoring or data acquisition systems, as well as self-adjusting systems that can adapt their processing algorithm, presentation layer, or data persistency layer in response to changes in input data streams.

  11. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity.

    Science.gov (United States)

    Indiveri, Giacomo; Chicca, Elisabetta; Douglas, Rodney

    2006-01-01

    We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

  12. High Speed Reconfigurable FFT Design by Vedic Mathematics

    CERN Document Server

    Raman, Ashish; Sarin, R K

    2010-01-01

    The Fast Fourier Transform (FFT) is a computationally intensive digital signal processing (DSP) function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation. In this paper, a reconfigurable FFT design using Vedic multiplier with high speed and small area is presented. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 4x4 bit multiplication operation is fragmented reconfigurable FFT modules. The 4x4 multiplication modules are implemented using small 2x2bit multipliers. Reconfigurability at run time is provided for attaining power saving. The reconfigurable FFT has been designed, optimized and implemented on an FPGA based system. This reconfigurable FFT is having the high speed and small area as compared to the conventional FFT.

  13. 一种面向能耗的可重构片上统一存储架构%Energy-oriented reconfigurable on-chip unified memory architecture

    Institute of Scientific and Technical Information of China (English)

    凌明; 张阳; 梅晨; 武建平; 王欢

    2011-01-01

    研究了一种新型的针对指令的可重构片上统一存储器架构,能通过配置信息动态地实现Cache和SPM的相互转换,并设计了一套基于Cache相变行为图的动态配置管理算法.为了满足程序执行不同阶段对片上存储资源的需求,对程序的执行特征进行研究并采用了一种基于程序跳转块的程序阶段动态监测与预测技术.通过对程序阶段的预测实现配置信息的快速上下文切换,缩短了重构时间.实验结果表明,采用该优化策略,使用4kB的架构对程序指令段进行优化,与4kB四路组关联的Cache相比,在保证系统性能的前提下,系统能耗平均降低15.98%,最高能耗降低34.03%.%A dynamic reconfigurable on-chip unified memory hierarchy (RcfgMem) is explored. The given resource of RcfgMem can be divided into certain size of Cache and SPM (scratch-pad memory) by the configuration. And a dynamic configuration management algorithm is provided based on Cache behavior phase graph. The characteristics of program execution are studied and a phase detect logic based on basic block vector is used. The configuration context can be shifted quickly by predicting the program phase. The experiment results show that compared with 4 kB 4-way associate instruction Cache, the total energy consumption can be reduced by 15. 98% on average 34.03% to the utmost without performance degradation.

  14. Architectures for block Toeplitz systems

    NARCIS (Netherlands)

    Bouras, Ilias; Glentis, George-Othon; Kalouptsidis, Nicholas

    1996-01-01

    In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and th

  15. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  16. VLSI design techniques for floating-point computation

    Energy Technology Data Exchange (ETDEWEB)

    Bose, B. K.

    1988-01-01

    The thesis presents design techniques for floating-point computation in VLSI. A basis for area-time design decisions for arithmetic and memory operations is formulated from a study of computationally intensive programs. Tradeoffs in the design and implementation of an efficient coprocessor interface are studied, together with the implications of hardware support for the IEEE Floating-Point Standard. Algorithm area-time tradeoffs for basic arithmetic functions are analyzed in light of changing technology. Details of a single-chip floating-point unit designed in two-micron CMOS for SPUR are described, including special design considerations for very wide data paths. The pervasive effects of scaling technology on different levels of design are explored, from devices and circuits, through logic and micro-architecture, to algorithms and systems.

  17. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  18. Reconfigurable MEMS OADM Systems

    Institute of Scientific and Technical Information of China (English)

    A. Q. Liu; J. Li; Q. X. Zhang; W. D. Zhong; C. Lu

    2003-01-01

    This paper proposes a serial reconfigurable OADM consisting of optical circulator and 2 × 2 MEMS optical switch and tunable FBG. Based on MEMS technology, the OADM is demonstrated to increase the flexibility, decrease the cost andimprove the reliability.

  19. Optically Controlled Reconfigurable Filtenna

    Directory of Open Access Journals (Sweden)

    L. G. Silva

    2016-01-01

    Full Text Available This work is regarding the development of a novel antenna called optically controlled reconfigurable filtenna, which is based on the integration of a broadband printed antenna with a bandpass reconfigurable RF filter. The filter is designed by applying defected microstrip structure (DMS technique and positioned in printed antenna feeding line in order to keep the same size of the original antenna. The filtenna bandwidth is optically reconfigurable by using two photoconductive silicon switches excited by CW laser at 808 nm. Numerical results rely on independent and switchable operational modes through the 2.4 and 5.1 GHz ISM bands, whereas measurements demonstrate two reconfigurable modes based on single-band/dual-band operation over the same frequency bands. The proposed device is validated by theoretical, numerical, and experimental results.

  20. Reconfigurable L-Band Radar

    Science.gov (United States)

    Rincon, Rafael F.

    2008-01-01

    The reconfigurable L-Band radar is an ongoing development at NASA/GSFC that exploits the capability inherently in phased array radar systems with a state-of-the-art data acquisition and real-time processor in order to enable multi-mode measurement techniques in a single radar architecture. The development leverages on the L-Band Imaging Scatterometer, a radar system designed for the development and testing of new radar techniques; and the custom-built DBSAR processor, a highly reconfigurable, high speed data acquisition and processing system. The radar modes currently implemented include scatterometer, synthetic aperture radar, and altimetry; and plans to add new modes such as radiometry and bi-static GNSS signals are being formulated. This development is aimed at enhancing the radar remote sensing capabilities for airborne and spaceborne applications in support of Earth Science and planetary exploration This paper describes the design of the radar and processor systems, explains the operational modes, and discusses preliminary measurements and future plans.

  1. VLSI implementation of a template subtraction algorithm for real-time stimulus artifact rejection.

    Science.gov (United States)

    Limnuson, Kanokwan; Lu, Hui; Chiel, Hillel J; Mohseni, Pedram

    2010-01-01

    In this paper, we present very-large-scale integrated (VLSI) implementation of a template subtraction algorithm for stimulus artifact rejection (SAR) in real time with applicability to closed-loop neuroprostheses. The SAR algorithm is based upon an infinite impulse response (IIR) temporal filtering technique, which can be efficiently implemented in VLSI with reduced power consumption and silicon area. We demonstrate that initialization of the memory within the system architecture using the first recorded stimulus artifact significantly decreases system response time as compared to the case without memory initialization. Two sets of pre-recorded neural data from an Aplysia californica are used to simulate the functionality of the proposed VLSI architecture in AMS 0.35 microm complementary metal-oxide-semiconductor (CMOS) technology. Depending upon the reproducibility in the shape of stimulus artifacts in vivo, the system eliminates virtually all artifacts in real time and recovers the extracellular neural activity with microW-level power consumption from 1.5 V.

  2. Architectural Engineers

    DEFF Research Database (Denmark)

    Petersen, Rikke Premer

    The design professions have always been an amorphous phenomena difficult to merge under one label. New constellations continually emerge, questioning, stretching, and reconfiguring the understanding of design and the professional practices linked to it. In this paper the idea of architectural eng...... with new types of competences and be able to manoeuvre in new types of constellations, but concurrently core competences must be preserved and the time of study kept at a minimum....

  3. SSI/MSI/LSI/VLSI/ULSI.

    Science.gov (United States)

    Alexander, George

    1984-01-01

    Discusses small-scale integrated (SSI), medium-scale integrated (MSI), large-scale integrated (LSI), very large-scale integrated (VLSI), and ultra large-scale integrated (ULSI) chips. The development and properties of these chips, uses of gallium arsenide, Josephson devices (two superconducting strips sandwiching a thin insulator), and future…

  4. COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems

    DEFF Research Database (Denmark)

    Wu, Kehuai; Madsen, Jan

    2007-01-01

    task model which extends the classical real-time task model to support the additional states and latencies needed to capture dynamically reconfigurable behavior, ii) propose a coprocessor- coupled reconfigurable architecture which has hardware runtime support for task execution, task reallocation...

  5. Mapping streaming applications on a reconfigurable MPSoC platform at run-time

    NARCIS (Netherlands)

    Hölzenspies, P.K.F.; Smit, G.J.M.; Kuper, J.

    2007-01-01

    In this paper we present a method for mapping streaming applications, with real-time requirements, onto a reconfigurable MPSoC. In this method, the performance of the hardware architecture (the reconfigurable Processing Element, the Network Interface and the Network-on-Chip) is integrated in the per

  6. Rational design of reconfigurable prismatic architected materials

    Science.gov (United States)

    Overvelde, Johannes T. B.; Weaver, James C.; Hoberman, Chuck; Bertoldi, Katia

    2017-01-01

    Advances in fabrication technologies are enabling the production of architected materials with unprecedented properties. Most such materials are characterized by a fixed geometry, but in the design of some materials it is possible to incorporate internal mechanisms capable of reconfiguring their spatial architecture, and in this way to enable tunable functionality. Inspired by the structural diversity and foldability of the prismatic geometries that can be constructed using the snapology origami technique, here we introduce a robust design strategy based on space-filling tessellations of polyhedra to create three-dimensional reconfigurable materials comprising a periodic assembly of rigid plates and elastic hinges. Guided by numerical analysis and physical prototypes, we systematically explore the mobility of the designed structures and identify a wide range of qualitatively different deformations and internal rearrangements. Given that the underlying principles are scale-independent, our strategy can be applied to the design of the next generation of reconfigurable structures and materials, ranging from metre-scale transformable architectures to nanometre-scale tunable photonic systems.

  7. Rational design of reconfigurable prismatic architected materials.

    Science.gov (United States)

    Overvelde, Johannes T B; Weaver, James C; Hoberman, Chuck; Bertoldi, Katia

    2017-01-18

    Advances in fabrication technologies are enabling the production of architected materials with unprecedented properties. Most such materials are characterized by a fixed geometry, but in the design of some materials it is possible to incorporate internal mechanisms capable of reconfiguring their spatial architecture, and in this way to enable tunable functionality. Inspired by the structural diversity and foldability of the prismatic geometries that can be constructed using the snapology origami technique, here we introduce a robust design strategy based on space-filling tessellations of polyhedra to create three-dimensional reconfigurable materials comprising a periodic assembly of rigid plates and elastic hinges. Guided by numerical analysis and physical prototypes, we systematically explore the mobility of the designed structures and identify a wide range of qualitatively different deformations and internal rearrangements. Given that the underlying principles are scale-independent, our strategy can be applied to the design of the next generation of reconfigurable structures and materials, ranging from metre-scale transformable architectures to nanometre-scale tunable photonic systems.

  8. Architectural Engineers

    DEFF Research Database (Denmark)

    Petersen, Rikke Premer

    The design professions have always been an amorphous phenomena difficult to merge under one label. New constellations continually emerge, questioning, stretching, and reconfiguring the understanding of design and the professional practices linked to it. In this paper the idea of architectural...... engineering is addresses from two perspectives – as an educational response and an occupational constellation. Architecture and engineering are two of the traditional design professions and they frequently meet in the occupational setting, but at educational institutions they remain largely estranged....... The paper builds on a multi-sited study of an architectural engineering program at the Technical University of Denmark and an architectural engineering team within an international engineering consultancy based on Denmark. They are both responding to new tendencies within the building industry where...

  9. Analog CMOS Nonlinear Cells and Their Applications in VLSI Signal and Information Processing

    Science.gov (United States)

    Khachab, Nabil Ibrahim

    1990-01-01

    The development of reconfigurable analog CMOS building blocks and their applications in analog VLSI is discussed and introduced in much the same way a logic gate is used in digital VLSI. They simultaneously achieve four -quadrant multiplication and division. These applications include multiplication, signal squaring, division, signal inversion, amplitude modulation. New all MOS implementations of the Hopfield like neural networks are developed by using the new cells. In addition new and novel techniques for sensor linearization and for MOSFET-C programmable-Q and omega_{n} filters are introduced. The new designs are simple, versatile, programmable and make effective use of analog CAD tools. Moreover, they are easily extendable to other technologies such as GaAs and BiCMOS. The objective of these designs is to achieve reduction in Silicon area and power consumption and reduce the interconnections between cells. It is also sought to provide a robust design that is CAD-compatible and make effective use of the standard cell library approach. This will offer more versatility and flexibility for analog signal processing systems and neural networks. Some of these new cells and a 3-neuron neural system are fabricated in a 2mum CMOS process. Experimental results of these circuits verify the validity of this new design approach.

  10. Utilizing nonlinearity of transistors for reconfigurable chaos computation

    Science.gov (United States)

    Ditto, William; Kia, Behnam

    2014-03-01

    A VLSI circuit design for chaos computing is presented that exploits the intrinsic nonlinearity of transistors to implement a novel approach for conventional and chaotic computing circuit design. In conventional digital circuit design and implementation, transistors are simply switched on or off. We argue that by using the full range of nonlinear dynamics of transistors, we can design and build more efficient computational elements and logic blocks. Furthermore, the nonlinearity of these transistor circuits can be used to program the logic block to implement different types of computational elements that can be reconfigured. Because the intrinsic nonlinear dynamics of the transistors are utilized the resulting circuits typically require fewer transistors compared to conventional digital circuits as we exploit the intrinsic nonlinearity of the transistors to realize computations. This work was done with support from ONR grant N00014-12-1-0026 and from an ONR STTR and First Pass Engineering.

  11. Reconfiguring trade mark law

    DEFF Research Database (Denmark)

    Elsmore, Matthew James

    2013-01-01

    -border setting, with a particular focus on small business and consumers. The article's overall message is to call for a rethink of received wisdom suggesting that trade marks are effective trade-enabling devices. The case is made for reassessing how we think about European trade mark law.......First, this article argues that trade mark law should be approached in a supplementary way, called reconfiguration. Second, the article investigates such a reconfiguration of trade mark law by exploring the interplay of trade marks and service transactions in the Single Market, in the cross...

  12. Reconfigurable, Cognitive Software-Defined Radio

    Science.gov (United States)

    Bhat, Arvind

    2015-01-01

    Software-defined radio (SDR) technology allows radios to be reconfigured to perform different communication functions without using multiple radios to accomplish each task. Intelligent Automation, Inc., has developed SDR platforms that switch adaptively between different operation modes. The innovation works by modifying both transmit waveforms and receiver signal processing tasks. In Phase I of the project, the company developed SDR cognitive capabilities, including adaptive modulation and coding (AMC), automatic modulation recognition (AMR), and spectrum sensing. In Phase II, these capabilities were integrated into SDR platforms. The reconfigurable transceiver design employs high-speed field-programmable gate arrays, enabling multimode operation and scalable architecture. Designs are based on commercial off-the-shelf (COTS) components and are modular in nature, making it easier to upgrade individual components rather than redesigning the entire SDR platform as technology advances.

  13. A Coherent VLSI Design Environment

    Science.gov (United States)

    1987-03-31

    In the figure, AminH and Ama.H represent the smallest and largest eigenvalues I of YH and AminAH and AmaAH represent the smallest and largest...Press, Princeton, NJ, 1970. [17] G. Clark and R. Zippel, "Schema: An Architecture for Knowledge Based Design," International Conference on Computer-Aided

  14. Compensating Inhomogeneities of Neuromorphic VLSI Devices Via Short-Term Synaptic Plasticity.

    Science.gov (United States)

    Bill, Johannes; Schuch, Klaus; Brüderle, Daniel; Schemmel, Johannes; Maass, Wolfgang; Meier, Karlheinz

    2010-01-01

    Recent developments in neuromorphic hardware engineering make mixed-signal VLSI neural network models promising candidates for neuroscientific research tools and massively parallel computing devices, especially for tasks which exhaust the computing power of software simulations. Still, like all analog hardware systems, neuromorphic models suffer from a constricted configurability and production-related fluctuations of device characteristics. Since also future systems, involving ever-smaller structures, will inevitably exhibit such inhomogeneities on the unit level, self-regulation properties become a crucial requirement for their successful operation. By applying a cortically inspired self-adjusting network architecture, we show that the activity of generic spiking neural networks emulated on a neuromorphic hardware system can be kept within a biologically realistic firing regime and gain a remarkable robustness against transistor-level variations. As a first approach of this kind in engineering practice, the short-term synaptic depression and facilitation mechanisms implemented within an analog VLSI model of I&F neurons are functionally utilized for the purpose of network level stabilization. We present experimental data acquired both from the hardware model and from comparative software simulations which prove the applicability of the employed paradigm to neuromorphic VLSI devices.

  15. Reconfigurable Parallel Computer Architectures for Space Applications

    Science.gov (United States)

    2012-08-07

    63 B-1. Dependency diagram of the hardware blocks implemented with VHDL .................. 64 C-1. The...distribution is unlimited. The CU has been fully implemented in a FPGA using VHDL . The CU hardware design is depicted in Figure 12. It consists of a main...Description of the ports of the I2C block designed using VHDL Port Name Direction Size (in bits) Function reset Input 1 Reset the system. This asynchronous

  16. High Speed Reconfigurable FIR Filter using Russian Peasant Multiplier with Sklansky Adder

    Directory of Open Access Journals (Sweden)

    K. Gunasekaran

    2014-12-01

    Full Text Available The Reconfigurable FIR filters are commonly used digital filters which find its major applications in digital signal processing and multi-standard wireless communications. The Direct form of FIR filter used in DSP application which consumes more area and power. To overcome this problem Multiplier Control Signal Decision (MCSD window schemes is incorporated into direct form FIR filter in order to dynamically change the filter order. Conventional reconfigurable FIR filter is designed using Russian Peasant Multiplier which consumes more area and delay due to poor performance of adder used in multiplication unit. In this study, modified reconfigurable FIR filter is designed to further reduce the area, power and time. In proposed Reconfigurable FIR filter, a Wallace adder is replaced by carry select adder with sklansky adder in Russian Peasant Multiplication technique. Hence, modified Reconfigurable FIR filter with carry select adder with sklansky adder consumes less area, delay and power than the conventional Reconfigurable FIR architecture with Russian Peasant Multiplication technique.

  17. Reconfigurable system design and verification

    CERN Document Server

    Hsiung, Pao-Ann; Huang, Chun-Hsian

    2009-01-01

    Reconfigurable systems have pervaded nearly all fields of computation and will continue to do so for the foreseeable future. Reconfigurable System Design and Verification provides a compendium of design and verification techniques for reconfigurable systems, allowing you to quickly search for a technique and determine if it is appropriate to the task at hand. It bridges the gap between the need for reconfigurable computing education and the burgeoning development of numerous different techniques in the design and verification of reconfigurable systems in various application domains. The text e

  18. XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Gaurav Purohit

    2016-01-01

    Full Text Available This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW implementation of new architecture uses Lookup Table (LUT for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

  19. Reconfiguration of Mobile Robot

    Directory of Open Access Journals (Sweden)

    Ashish K. Thakre

    2012-03-01

    Full Text Available Dynamic Partial Reconfiguration (DPR of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire system interruption. In this paper, we will implement a line follower robot for the white line as well as for black line; both these modules will be programmed in VHDL. The robot will dynamically reconfigure the FPGA in the run-time while the robot senses black line after white line or vice-versa. This design includes two modules one is static and the other is partially reconfigurable regions (PRR which is a dynamic region. The controllers are the static modules used for controlling the flow of data to and from the reconfigurable modules to the external world (host environment through busmacros. Whereas white line and black line modules are designed as dynamic modules. Different hardware modules will be used such as Sensors and actuators , all these modules will be interfaced using FPGA controller. The speed of motor is controlled using pulse width modulation (PWM using VHDL

  20. Reconfigurable layout problem

    NARCIS (Netherlands)

    Meng, G.; Heragu, S.S.; Zijm, H.

    2004-01-01

    This paper addresses the reconfigurable layout problem, which differs from traditional, robust and dynamic layout problems mainly in two aspects: first, it assumes that production data are available only for the current and upcoming production period. Second, it considers queuing performance measure

  1. Reconfigurable layout problem

    NARCIS (Netherlands)

    Meng, G.; Heragu, S.S.; Heragu, S.S.; Zijm, Willem H.M.

    2004-01-01

    This paper addresses the reconfigurable layout problem, which differs from traditional, robust and dynamic layout problems mainly in two aspects: first, it assumes that production data are available only for the current and upcoming production period. Second, it considers queuing performance measure

  2. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  3. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  4. Hydra: an Energy-efficient and Reconfigurable Network Interface

    NARCIS (Netherlands)

    van de Burgwal, M.D.; Smit, Gerardus Johannes Maria; Rauwerda, G.K.; Heysters, P.M.

    In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces

  5. The ReNoC Reconfigurable Network-on-Chip

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo; Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2011-01-01

    This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use in general-purpose multiprocessor system-on-chip platforms, and which enables application-specific logical NoC topologies to be configured, thus providing both efficiency and flexibility...

  6. Mapping Applications to a Coarse Grain Reconfigurable System

    NARCIS (Netherlands)

    Guo, Y.; Smit, Gerardus Johannes Maria; Broersma, Haitze J.; Rosien, M.A.J.; Heysters, P.M.; Omondi, A.; Sedukhin, S.

    This paper introduces a method which can be used to map applications written in a high level source language program, like C, to a coarse grain reconfigurable architecture, MONTIUM. The source code is first translated into a control data flow graph. Then after applying graph clustering, scheduling

  7. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  8. Leak detection utilizing analog binaural (VLSI) techniques

    Science.gov (United States)

    Hartley, Frank T. (Inventor)

    1995-01-01

    A detection method and system utilizing silicon models of the traveling wave structure of the human cochlea to spatially and temporally locate a specific sound source in the presence of high noise pandemonium. The detection system combines two-dimensional stereausis representations, which are output by at least three VLSI binaural hearing chips, to generate a three-dimensional stereausis representation including both binaural and spectral information which is then used to locate the sound source.

  9. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  10. Modular VLSI Reed-Solomon Decoder

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie

    1991-01-01

    Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

  11. Generating Weighted Test Patterns for VLSI Chips

    Science.gov (United States)

    Siavoshi, Fardad

    1990-01-01

    Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

  12. VLSI Structure for an All Digital Receiver for CDMA PABX Handset

    Institute of Scientific and Technical Information of China (English)

    ZhouShidong; BiGuangguo

    1995-01-01

    In this paper,a VLSI architecture of a CDMA receiver is put forward for wirelesss PABX handset.To meet the critically low cost and power consumption requirement with neglectable per-formance degradation,some new techniques are employed to reduce hardware complexity,including base band processing,chip-rate sampling,low ADC resolution,absolute value detector,double branch acquisition ,and modified carrier phase compensation.Performance of experimental system fits well with theoretical predition ,and the practical SNR lose compared with ideal reception is about 2-3dB.

  13. Decentralized autonomous planning of cluster reconfiguration for fractionated spacecraft

    Science.gov (United States)

    Chu, Jing; Guo, Jian; Gill, Eberhard

    2016-06-01

    Autonomous cluster operation such as cluster reconfiguration is one of the enabling technologies for fractionated spacecraft. By virtue of the multi-agent system theory, this paper presents an organizational architecture for fractionated spacecraft, which not only enables autonomous cluster operations but also facilitates its non-traditional attributes. Within this organizational architecture, a decentralized framework is proposed to solve cluster reconfiguration problems based on primal and dual decomposition, where subgradient methods are adopted to include reconfiguration cases with non-differentiable objectives. Two typical constraints are considered: final configuration constraints representing coupling variables and collision avoidance constraints representing coupling constraints, both of which are non-convex. General schemes are proposed to convexify those constraints via the linearization and convex restriction technology. Then final configuration constraints are tackled by primal decomposition, while collision avoidance constraints by dual decomposition. To the end, multi-level primal and dual decompositions are employed to solve reconfiguration problems with both coupling variables and coupling constraints. For illustration an example of in-plane cluster reconfiguration is solved and compared with the centralized approach the solution is optimal.

  14. Training probabilistic VLSI models on-chip to recognise biomedical signals under hardware nonidealities.

    Science.gov (United States)

    Jiang, P C; Chen, H

    2006-01-01

    VLSI implementation of probabilistic models is attractive for many biomedical applications. However, hardware non-idealities can prevent probabilistic VLSI models from modelling data optimally through on-chip learning. This paper investigates the maximum computational errors that a probabilistic VLSI model can tolerate when modelling real biomedical data. VLSI circuits capable of achieving the required precision are also proposed.

  15. Optoelectronic Correlator Architecture for Shift Invariant Target Recognition

    CERN Document Server

    Monjur, Mehjabin S; Tripathi, Renu; Donoghue, John; Shahriar, M S

    2013-01-01

    In this paper, we present theoretical details and the underlying architecture of a hybrid optoelectronic correlator that correlates images using SLMs, detectors and VLSI chips. The proposed architecture bypasses the nonlinear material such as photorefractive polymer film by using detectors instead, and the phase information is yet conserved by the interference of plane waves with the images.

  16. Analogue VLSI for probabilistic networks and spike-time computation.

    Science.gov (United States)

    Murray, A

    2001-02-01

    The history and some of the methods of analogue neural VLSI are described. The strengths of analogue techniques are described, along with residual problems to be solved. The nature of hardware-friendly and hardware-appropriate algorithms is reviewed and suggestions are offered as to where analogue neural VLSI's future lies.

  17. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  18. eTissue: An Adaptive Reconfigurable Bio-Inspired Hardware Architecture%电子组织:一种具有自适应能力的可重构仿生硬件结构

    Institute of Scientific and Technical Information of China (English)

    徐佳庆; 窦勇; 吕启; 冯雪

    2012-01-01

    In the field of fault tolerance, adaptive bio-inspired hardware is springing up in recent years. The robustness of human blood system is derived from substitution among homogeneous cells mechanism, differentiation of adult stem cells mechanism, and conversion between heterogeneous cells mechanism. Illumined by the mechanisms mentioned above, this paper presents a bio-inspired adaptive reconfigurable hardware architecture named electronic tissue (eTissue). Different from existing multicellular array, eTissue recognizes and processes data based on data tag, which loosely couples operations and processing elements, consequently equips eTissue with flexible cell replacement capability. We implement substitution among homogeneous cells, differentiation of adult stem cells, and conversion between heterogeneous cells based on this flexible cell replacement capability. These mechanisms compose the hierarchical self-healing of eTissue, and the self-evolution of eTissue is derived from differentiation of adult stem cells and conversion between heterogeneous cells. We implement the eTissue prototype system in FPGA, and conduct fault-injection experiments to attest to its self-healing and self-evolution capability. Finally, we analyze and discuss the robustness of eTissue.%具有自适应能力的仿生硬件是容错领域一个新兴的研究方向.同类细胞替换、成体干细胞分化和异类细胞转化等生物机制是人体血液组织健壮性的重要来源.受这些生物机制的启发,提出了一种名为电子组织的自适应可重构多细胞阵列结构.该结构采用了基于标记与识别的数据处理方式,解除了传统多细胞阵列结构中操作与细胞单元间的严格绑定的数据处理方式,使得电子组织具备了更为灵活的细胞单元替换能力,并在此基础上实现了同类细胞替换、成体干细胞分化和异类细胞转化3种仿生机制.这3种机制使电子组织具备了层次化的自我修复能力;成

  19. Software-Reconfigurable Processors for Spacecraft

    Science.gov (United States)

    Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

    2005-01-01

    A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

  20. Reconfigurable nanomechanical photonic metamaterials.

    Science.gov (United States)

    Zheludev, Nikolay I; Plum, Eric

    2016-01-01

    The changing balance of forces at the nanoscale offers the opportunity to develop a new generation of spatially reconfigurable nanomembrane metamaterials in which electromagnetic Coulomb, Lorentz and Ampère forces, as well as thermal stimulation and optical signals, can be engaged to dynamically change their optical properties. Individual building blocks of such metamaterials, the metamolecules, and their arrays fabricated on elastic dielectric membranes can be reconfigured to achieve optical modulation at high frequencies, potentially reaching the gigahertz range. Mechanical and optical resonances enhance the magnitude of actuation and optical response within these nanostructures, which can be driven by electric signals of only a few volts or optical signals with power of only a few milliwatts. We envisage switchable, electro-optical, magneto-optical and nonlinear metamaterials that are compact and silicon-nanofabrication-technology compatible with functionalities surpassing those of natural media by orders of magnitude in some key design parameters.

  1. Optically Reconfigurable Photonic Devices

    CERN Document Server

    Wang, Qian; Gholipour, Behrad; Wang, Chih-Ming; Yuan, Guanghui; Teng, Jinghua; Zheludev, Nikolay I

    2015-01-01

    Optoelectronic components with adjustable parameters, from variable-focal-length lenses to spectral filters that can change functionality upon stimulation, have enormous technological importance. Tuning of such components is conventionally achieved by either micro- or nano-mechanical actuation of their consitutive parts, stretching or application of thermal stimuli. Here we report a new dielectric metasurface platform for reconfigurable optical components that are created with light in a non-volatile and reversible fashion. Such components are written, erased and re-written as two-dimensional binary or grey-scale patterns into a nanoscale film of phase change material by inducing a refractive-index-changing phase-transition with tailored trains of femtosecond pulses. We combine germanium-antimony-tellurium-based films optimized for high-optical-contrast ovonic switching with a sub-wavelength-resolution optical writing process to demonstrate technologically relevant devices: visible-range reconfigurable bi-chr...

  2. Bandwidth Reconfigurable Metamaterial Arrays

    Directory of Open Access Journals (Sweden)

    Nathanael J. Smith

    2014-01-01

    Full Text Available Metamaterial structures provide innovative ways to manipulate electromagnetic wave responses to realize new applications. This paper presents a conformal wideband metamaterial array that achieves as much as 10 : 1 continuous bandwidth. This was done by using interelement coupling to concurrently achieve significant wave slow-down and cancel the inductance stemming from the ground plane. The corresponding equivalent circuit of the resulting array is the same as that of classic metamaterial structures. In this paper, we present a wideband Marchand-type balun with validation measurements demonstrating the metamaterial (MTM array’s bandwidth from 280 MHz to 2800 MHz. Bandwidth reconfiguration of this class of array is then demonstrated achieving a variety of band-pass or band-rejection responses within its original bandwidth. In contrast with previous bandwidth and frequency response reconfigurations, our approach does not change the aperture’s or ground plane’s geometry, nor does it introduce external filtering structures. Instead, the new responses are realized by making simple circuit changes into the balanced feed integrated with the wideband MTM array. A variety of circuit changes can be employed using MEMS switches or variable lumped loads within the feed and 5 example band-pass and band-rejection responses are presented. These demonstrate the potential of the MTM array’s reconfiguration to address a variety of responses.

  3. Recent Developments in Reconfigurable and Multiband Antenna Technology

    Directory of Open Access Journals (Sweden)

    N. Haider

    2013-01-01

    Full Text Available A comparative analysis of various reconfigurable and multiband antenna concepts is presented. In order to satisfy the requirements for the advanced systems used in modern wireless and radar applications, different multiband and reconfigurable antennas have been proposed and investigated in the past years. In this paper, these design concepts have been classified into three basic approaches: tunable/switchable antenna integration with radio-frequency switching devices, wideband or multiband antenna integration with tunable filters, and array architectures with the same aperture utilized for different operational modes. Examples of each design approach are discussed along with their inherent benefits and challenges.

  4. Modelling of Human Glottis in VLSI for Low Power Architectures

    CERN Document Server

    Raj, Nikhil

    2010-01-01

    The Glottal Source is an important component of voice as it can be considered as the excitation signal to the voice apparatus. Nowadays, new techniques of speech processing such as speech recognition and speech synthesis use the glottal closure and opening instants. Current models of the glottal waves derive their shape from approximate information rather than from exactly measured data. General method concentrate on assessment of the glottis opening using optical, acoustical methods, or on visualization of the larynx position using ultrasound, computer tomography or magnetic resonance imaging techniques. In this work, circuit model of Human Glottis using MOS is designed by exploiting fluid volume velocity to current, fluid pressure to voltage, and linear and nonlinear mechanical impedances to linear and nonlinear electrical impedances. The glottis modeled as current source includes linear, non-linear impedances to represent laminar and turbulent flow respectively, in vocal tract. The MOS modelling and simula...

  5. VLSI architecture for a Reed-Solomon decoder

    Science.gov (United States)

    Hsu, In-Shek (Inventor); Truong, Trieu-Kie (Inventor)

    1992-01-01

    A basic single-chip building block for a Reed-Solomon (RS) decoder system is partitioned into a plurality of sections, the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10 and 8 bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10 and 8 bit operation.

  6. 3-D VLSI Architecture Implementation for Data Fusion Problems

    Science.gov (United States)

    Duong, T.; Weldon, D.; Thomas, T.

    1999-01-01

    This paper gives an overview of hardware implementation techniques employed in solving real-time classification problems using Neural Network, Principle Component Analysis (PCA), and Independent Component Analysis (ICA) techniques.

  7. Cascaded VLSI neural network architecture for on-line learning

    Science.gov (United States)

    Duong, Tuan A. (Inventor); Daud, Taher (Inventor); Thakoor, Anilkumar P. (Inventor)

    1995-01-01

    High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A comparison-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.

  8. VLSI Architecture Of A Binary Up/Down Counter

    Science.gov (United States)

    Hsu, In-Shek; Truong, Trieu-Kie; Reed, I. S.

    1988-01-01

    Identical stages contain relatively-few logic gates. New algorithm simplifies design of binary up/down counter. Design suitable for very-large-scale integrated circuits. Contains simple "pipeline" array of identical cells. Programmable logic unit converts increment and decrement input signals to "U" and "D" signals required by algorithm of counter.

  9. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Science.gov (United States)

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  10. Parallel VLSI design for the fast -D DWT core algorithm

    Institute of Scientific and Technical Information of China (English)

    WEI Benjie; LIU Mingye; ZHOU Yihua; CHENG Baodong

    2007-01-01

    By studying the core algorithm of a three-dimensional discrete wavelet transform (3-D DWT) in depth,this Paper divides it into three one-dimensional discrete wavelet transforms (1-D DWTs).Based on the implementation of a 3-D DWT software,a parallel architecture design of a very large-scale integration(VLSI)is produced.It needs three dual-port random-access memory(RAM)to store the temporary results and transpose the matrix,then builds up a pipeline model composed of the three 1-D DWTs.In the design.the finite state machine(FSM)is used well to control the flow.Compared with the serial mode.the experimental results of the post synthesized simulation show that the design method is correct and effective.It can increase the processing speed by about 66%.work at 59 MHz,and meet the real-time needs of the video encoder.

  11. VLSI Circuits for High Speed Data Conversion

    Science.gov (United States)

    1994-05-16

    Meeting, pp. 289-292, Sept. 199 1. [4] Behzad Razavi , "High-Speed, Nigh-Resolution Analog-to-Digital Conversion in VLSI Technologies, Ph.D. Thesis... Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High- Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-192...Dec. 1992. [8] Behzad Razavi and Bruce A. Wooley, "A 12-Bkt 5-MSamplesoc Two-Step CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 27, pp

  12. Self arbitrated VLSI asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, S.; Maki, G.

    1990-01-01

    A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.

  13. Single Spin Logic Implementation of VLSI Adders

    CERN Document Server

    Shukla, Soumitra

    2011-01-01

    Some important VLSI adder circuits are implemented using quantum dots (qd) and Spin Polarized Scanning Tunneling Microscopy (SPSTM) in Single Spin Logic (SSL) paradigm. A simple comparison between these adder circuits shows that the mirror adder implementation in SSL does not carry any advantage over CMOS adder in terms of complexity and number of qds, opposite to the trend observed in their charge-based counterparts. On the contrary, the transmission gate adder, Static and Dynamic Manchester carry gate adders in SSL reduce the complexity and number of qds, in harmony with the trend shown in transistor adders.

  14. An Analog VLSI Saccadic Eye Movement System

    OpenAIRE

    1994-01-01

    In an effort to understand saccadic eye movements and their relation to visual attention and other forms of eye movements, we - in collaboration with a number of other laboratories - are carrying out a large-scale effort to design and build a complete primate oculomotor system using analog CMOS VLSI technology. Using this technology, a low power, compact, multi-chip system has been built which works in real-time using real-world visual inputs. We describe in this paper the performance of a...

  15. Communication Protocols Augmentation in VLSI Design Applications

    Directory of Open Access Journals (Sweden)

    Kanhu Charan Padhy

    2015-05-01

    Full Text Available With the advancement in communication System, the use of various protocols got a sharp rise in the different applications. Especially in the VLSI design for FPGAs, ASICS, CPLDs, the application areas got expanded to FPGA based technologies. Today, it has moved from commercial application to the defence sectors like missiles & aerospace controls. In this paper the use of FPGAs and its interface with various application circuits in the communication field for data (textual & visual & control transfer is discussed. To be specific, the paper discusses the use of FPGA in various communication protocols like SPI, I2C, and TMDS in synchronous mode in Digital System Design using VHDL/Verilog.

  16. VLSI binary multiplier using residue number systems

    Energy Technology Data Exchange (ETDEWEB)

    Barsi, F.; Di Cola, A.

    1982-01-01

    The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.

  17. Algorithms, architectures and information systems security

    CERN Document Server

    Sur-Kolay, Susmita; Nandy, Subhas C; Bagchi, Aditya

    2008-01-01

    This volume contains articles written by leading researchers in the fields of algorithms, architectures, and information systems security. The first five chapters address several challenging geometric problems and related algorithms. These topics have major applications in pattern recognition, image analysis, digital geometry, surface reconstruction, computer vision and in robotics. The next five chapters focus on various optimization issues in VLSI design and test architectures, and in wireless networks. The last six chapters comprise scholarly articles on information systems security coverin

  18. Image processing algorithm acceleration using reconfigurable macro processor model

    Institute of Scientific and Technical Information of China (English)

    孙广富; 陈华明; 卢焕章

    2004-01-01

    The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of reconfigurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented.Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of "hardware" function that can be called by the DSP in high-level algorithm.It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.

  19. Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

    Directory of Open Access Journals (Sweden)

    Soundous Chairat

    2017-05-01

    Full Text Available This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI technology at 0.6 V and a 1.1 ns/bit latency per stage.

  20. Modeling and analyzing architectural change with alloy

    DEFF Research Database (Denmark)

    Hansen, Klaus Marius; Ingstrup, Mads

    2010-01-01

    to the uptake of reconfiguration techniques in industry. Using the Alloy language and associated tool, we propose a practical way to formally model and analyze runtime architectural change expressed as architectural scripts. Our evaluation shows the performance to be acceptable; our experience......Although adaptivity based on reconfiguration has the potential to improve dependability of systems, the cost of a failed attempt at reconfiguration is prohibitive in precisely the applications where high dependability is required. Existing work on formal modeling and verification of architectural...... reconfigurations partly achieve the goal of ensuring correctness, however the formalisms used often lack tool support and the ensuing models have uncertain relation to a concrete implementation. Thus a practical way to ensure with formal certainty that specific architectural changes are correct remains a barrier...

  1. Remote hardware-reconfigurable robotic camera

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

    2001-10-01

    In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

  2. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  3. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  4. The VLSI-PLM Board: Design, Construction, and Testing

    Science.gov (United States)

    1989-03-01

    Computer Aided Design CB- Xenologic Corporation’s X-1 cache board DAS - Digital Analysis System EECS - Electrical Engineering and Computer...PLM Board is to debug the VLSI-PLM Chip [STN88] and to interface the chip to the Xenologic Corporation’s X-1 cache board. The chip is a high...a wire-wrapped board designed for debugging VLSI-PLM [STN88] and connecting VLSI- PLM to the cache board of Xenologic Corporation’s X-1 system. The

  5. Design and implementation of a high-speed reconfigurable cipher chip

    Institute of Scientific and Technical Information of China (English)

    Gao Nana; Li Zhancai; Wang Qin

    2006-01-01

    A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfiguration analysis of algorithms, the design of reconfigurable processing units and a new reconfigurable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the operating frequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.

  6. Transparent Dynamic reconfiguration for CORBA

    NARCIS (Netherlands)

    Almeida, João Paulo A.; Wegdam, Maarten; Sinderen, van Marten; Nieuwenhuis, Lambert; Blair, G.; Schmidt, D.; Tari, Z.

    2001-01-01

    Distributed systems with high availability requirements have to support some form of dynamic reconfiguration. This means that they must provide the ability to be maintained or upgraded without being taken off-line. Building a distributed system that allows dynamic reconfiguration is very intrusive t

  7. RF MEMS Based Reconfigurable Antennas

    Science.gov (United States)

    Simons, Rainee N.

    2004-01-01

    The presentation will first of all address the advantages of RF MEMS circuit in antenna applications and also the need for electronically reconfigurable antennas. Next, discuss some of the recent examples of RF MEMS based reconfigurable microstrip antennas. Finally, conclude the talk with a summary of MEMS antenna performance.

  8. Specifying structural constraints of architectural patterns in the ARCHERY language

    Energy Technology Data Exchange (ETDEWEB)

    Sanchez, Alejandro [Departamento de Informática, Universidad Nacional de San Luis, Ejército de los Andes 950, D5700HHW San Luis (Argentina); HASLab INESC TEC and Universidade do Minho, Campus de Gualtar, 4710-057 Braga (Portugal); Barbosa, Luis S. [HASLab INESC TEC and Universidade do Minho, Campus de Gualtar, 4710-057 Braga (Portugal); Riesco, Daniel [Departamento de Informática, Universidad Nacional de San Luis, Ejército de los Andes 950, D5700HHW San Luis (Argentina)

    2015-03-10

    ARCHERY is an architectural description language for modelling and reasoning about distributed, heterogeneous and dynamically reconfigurable systems in terms of architectural patterns. The language supports the specification of architectures and their reconfiguration. This paper introduces a language extension for precisely describing the structural design decisions that pattern instances must respect in their (re)configurations. The extension is a propositional modal logic with recursion and nominals referencing components, i.e., a hybrid µ-calculus. Its expressiveness allows specifying safety and liveness constraints, as well as paths and cycles over structures. Refinements of classic architectural patterns are specified.

  9. Reconfigurable Integrated Optoelectronics

    Directory of Open Access Journals (Sweden)

    Richard Soref

    2011-01-01

    Full Text Available Integrated optics today is based upon chips of Si and InP. The future of this chip industry is probably contained in the thrust towards optoelectronic integrated circuits (OEICs and photonic integrated circuits (PICs manufactured in a high-volume foundry. We believe that reconfigurable OEICs and PICs, known as ROEICs and RPICs, constitute the ultimate embodiment of integrated photonics. This paper shows that any ROEIC-on-a-chip can be decomposed into photonic modules, some of them fixed and some of them changeable in function. Reconfiguration is provided by electrical control signals to the electro-optical building blocks. We illustrate these modules in detail and discuss 3D ROEIC chips for the highest-performance signal processing. We present examples of our module theory for RPIC optical lattice filters already constructed, and we propose new ROEICs for directed optical logic, large-scale matrix switching, and 2D beamsteering of a phased-array microwave antenna. In general, large-scale-integrated ROEICs will enable significant applications in computing, quantum computing, communications, learning, imaging, telepresence, sensing, RF/microwave photonics, information storage, cryptography, and data mining.

  10. Reconfigurable multiport EPON repeater

    Science.gov (United States)

    Oishi, Masayuki; Inohara, Ryo; Agata, Akira; Horiuchi, Yukio

    2009-11-01

    An extended reach EPON repeater is one of the solutions to effectively expand FTTH service areas. In this paper, we propose a reconfigurable multi-port EPON repeater for effective accommodation of multiple ODNs with a single OLT line card. The proposed repeater, which has multi-ports in both OLT and ODN sides, consists of TRs, BTRs with the CDR function and a reconfigurable electrical matrix switch, can accommodate multiple ODNs to a single OLT line card by controlling the connection of the matrix switch. Although conventional EPON repeaters require full OLT line cards to accommodate subscribers from the initial installation stage, the proposed repeater can dramatically reduce the number of required line cards especially when the number of subscribers is less than a half of the maximum registerable users per OLT. Numerical calculation results show that the extended reach EPON system with the proposed EPON repeater can save 17.5% of the initial installation cost compared with a conventional repeater, and can be less expensive than conventional systems up to the maximum subscribers especially when the percentage of ODNs in lightly-populated areas is higher.

  11. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  12. Recursive Architecture for the Forward and Inverse Modified Discrete Cosine Transfer

    Institute of Scientific and Technical Information of China (English)

    LUJunming; JIANGGuoxiong; LINZhenghui

    2003-01-01

    Recursive algorithms have been found very effective for realization using software and very large scale integrated circuit (VLSI) techniques. In this paper, an efficient recursive algorithm for the forward and inverse modified discrete cosine transfer (IMDCT) with arbitrary length is presented. This new recursive structure for the transform kernels of the MDCT and IMDCT can reduce the computational complexity. The proposed regular ar-chitecture is particularly suitable for parallel VLSI realiza-tion.

  13. The 1992 4th NASA SERC Symposium on VLSI Design

    Science.gov (United States)

    Whitaker, Sterling R.

    1992-01-01

    Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design.

  14. Interaction of algorithm and implementation for analog VLSI stereo vision

    Science.gov (United States)

    Hakkarainen, J. M.; Little, James J.; Lee, Hae-Seung; Wyatt, John L., Jr.

    1991-07-01

    Design of a high-speed stereo vision system in analog VLSI technology is reported. The goal is to determine how the advantages of analog VLSI--small area, high speed, and low power-- can be exploited, and how the effects of its principal disadvantages--limited accuracy, inflexibility, and lack of storage capacity--can be minimized. Three stereo algorithms are considered, and a simulation study is presented to examine details of the interaction between algorithm and analog VLSI implementation. The Marr-Poggio-Drumheller algorithm is shown to be best suited for analog VLSI implementation. A CCD/CMOS stereo system implementation is proposed, capable of operation at 6000 image frame pairs per second for 48 X 48 images, and faster than frame rate operation on 256 X 256 binocular image pairs.

  15. A Flexible System Level Design Methodology Targeting Run-Time Reconfigurable FPGAs

    Directory of Open Access Journals (Sweden)

    Houzet Dominique

    2007-01-01

    Full Text Available Abstract Reconfigurable computing is certainly one of the most important emerging research topics on digital processing architectures over the last few years. The introduction of run-time reconfiguration (RTR on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose, we present an automatic design generation methodology for heterogeneous architectures based on DSPs and FPGAs that ease and speed RTR implementation. We focus on how to take into account specificities of partially reconfigurable components from a high-level specification during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of an FPGA with automatic management of the reconfiguration process. Furthermore, this automatic design generation enables a reconfiguration prefetching technique to minimize reconfiguration latency and buffer-merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. This implementation example illustrates the benefits of the proposed design methodology.

  16. A First Step Towards High-Level Cost Models for the Implementation of SDRs on Multiprocessing Reconfigurable Systems

    DEFF Research Database (Denmark)

    Le Moullec, Yannick

    2011-01-01

    VLSI technological advances provide designers with more and more powerful and flexible platforms such as reconfigurable heterogeneous multiprocessing systems based on FPGAs. At the same time, the applications which are to be implemented onto such platforms are increasingly more and more complex...... into account. We believe that such models could be used for rapidly comparing implementation alternatives at a high level of abstraction and for guiding the designer during the (pre)analysis phase of the design flow for the implementation of e.g. SDR platforms....

  17. Reconfigurable computing the theory and practice of FPGA-based computation

    CERN Document Server

    Hauck, Scott

    2010-01-01

    Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design- the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems. Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardwa

  18. Finite Field Arithmetic Architecture Based on Cellular Array

    Directory of Open Access Journals (Sweden)

    Kee-Won Kim

    2015-05-01

    Full Text Available Recently, various finite field arithmetic structures are introduced for VLSI circuit implementation on cryptosystems and error correcting codes. In this study, we present an efficient finite field arithmetic architecture based on cellular semi-systolic array for Montgomery multiplication by choosing a proper Montgomery factor which is highly suitable for the design on parallel structures. Therefore, our architecture has reduced a time complexity by 50% compared to typical architecture.

  19. NASA Space Engineering Research Center for VLSI System Design

    Science.gov (United States)

    1993-01-01

    This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

  20. Design and Verification of High-Speed VLSI Physical Design

    Institute of Scientific and Technical Information of China (English)

    Dian Zhou; Rui-Ming Li

    2005-01-01

    With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.

  1. VLSI Circuit Configuration Using Satisfiability Logic in Hopfield Network

    Directory of Open Access Journals (Sweden)

    Mohd Asyraf Mansor

    2016-09-01

    Full Text Available Very large scale integration (VLSI circuit comprises of integrated circuit (IC with transistors in a single chip, widely used in many sophisticated electronic devices. In our paper, we proposed VLSI circuit design by implementing satisfiability problem in Hopfield neural network as circuit verification technique. We restrict our logic construction to 2-Satisfiability (2-SAT and 3- Satisfiability (3-SAT clauses in order to suit with the transistor configuration in VLSI circuit. In addition, we developed VLSI circuit based on Hopfield neural network in order to detect any possible error earlier than the manual circuit design. Microsoft Visual C++ 2013 is used as a platform for training, testing and validating of our proposed design. Hence, the performance of our proposed technique evaluated based on global VLSI configuration, circuit accuracy and the runtime. It has been observed that the VLSI circuits (HNN-2SAT and HNN-3SAT circuit developed by proposed design are better than the conventional circuit due to the early error detection in our circuit.

  2. Optimal Reconfiguration of Tetrahedral Formations

    Science.gov (United States)

    Huntington, Geoffrey; Rao, Anil V.; Hughes, Steven P.

    2004-01-01

    The problem of minimum-fuel formation reconfiguration for the Magnetospheric Multi-Scale (MMS) mission is studied. This reconfiguration trajectory optimization problem can be posed as a nonlinear optimal control problem. In this research, this optimal control problem is solved using a spectral collocation method called the Gauss pseudospectral method. The objective of this research is to provide highly accurate minimum-fuel solutions to the MMS formation reconfiguration problem and to gain insight into the underlying structure of fuel-optimal trajectories.

  3. Reconfigurable nanowire electronics - A review

    Science.gov (United States)

    Weber, W. M.; Heinzig, A.; Trommer, J.; Martin, D.; Grube, M.; Mikolajick, T.

    2014-12-01

    Reconfigurable nanowire transistors merge the electrical properties of unipolar n- and p-type FETs into a single type of device with identic technology, geometry and composition. These four-terminal nanowire transistors employ an electric signal to dynamically program unipolar n- or p-type behavior. More than reducing the technological complexity, they open up the possibility of dynamically programming the functions of circuits at the device level, i.e. enabling a fine-grain reconfiguration of complex functions. We will review different reconfigurable concepts, analyze the transport properties and finally assess their maturity for building circuits.

  4. Reconfiguring Maternity Care?

    DEFF Research Database (Denmark)

    Johannsen, Nis

    were not obstacles which the proposed changes should overcome, but are on the contrary necessary, as it is the alliances between the particular interests and the proposed changes that motor the initiatives. The interests were not invented through the initiatives but are formed through history. Although...... at a hospital and a group of researchers which included me. Both initiatives involved numerous seemingly different interests that were held together and related to reconfiguring maternity care. None of the initiatives can unequivocally be labelled a success, as neither managed to change maternity care, at least...... not in the intended manner. It was, however, an achievement to relate the different interests for a period. In this dissertation I will elucidate the proposed changes in the initiatives as well as expound on the manner in which they were proposed. It is argued that the different interests involved in the initiatives...

  5. Repetition or Reconfiguration

    DEFF Research Database (Denmark)

    Vaarst Andersen, Kristina

    Experience, measured as seniority, is seldom sufficient to explain individual professionals’ abilities to contribute with valuable knowledge to team production. We need to pay attention to professionals’ knowledge and its fit to the project they engage in. In many industries and settings, the cog......Experience, measured as seniority, is seldom sufficient to explain individual professionals’ abilities to contribute with valuable knowledge to team production. We need to pay attention to professionals’ knowledge and its fit to the project they engage in. In many industries and settings...... and reconfiguration. The results indicate that project performance benefits form contributions from individuals holding diverse knowledge only when projects aim for high differentiation levels. This positive association is not just moderated, it may even be reversed in the case of professionals participating in low...

  6. VLSI Design of a Turbo Decoder

    Science.gov (United States)

    Fang, Wai-Chi

    2007-01-01

    A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

  7. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  8. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  9. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  10. PLA realizations for VLSI state machines

    Science.gov (United States)

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  11. Reconfigurable, Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The nature of human exploration missions to the Moon and Mars demands a frequency-agile, reconfigurable, durable digital radio delivering telemetry, ranging, voice,...

  12. VLSI circuit techniques and technologies for ultrahigh speed data conversion interfaces

    Science.gov (United States)

    Wooley, Bruce A.

    1991-04-01

    The performance of digital VLSI signal processing and communications systems is often limited by the data conversion interfaces between digital system-level components and the analog environment in which those components are embedded. The focus of this program has been research into the fundamental nature of such interfaces in systems that digitally process high-bandwidth signals for purposes such as radar imaging, high-resolution graphics, high-definition video, mobile and fiber-optic communications, and broadband instrumentation. Effort has been devoted to the study of both generic circuit functions, such as sampling and comparison, and architectural alternatives relevant to the implementation of high-speed data converters in present and emerging VLSI technologies. Specific results of the research include the design and realization of novel low-power CMOS and BiCMOS sampled-data comparators operating at rates as high as 200 MHz, the exploration of various design approaches to the implementation of high-speed sample-and-hold circuits in CMOS and BiCMOS technologies, and the design of a subranging CMOS analog-to-digital converter that provides 12-bit resolution at a conversion rate of 10 MHz.

  13. Operating System for Runtime Reconfigurable Multiprocessor Systems

    Directory of Open Access Journals (Sweden)

    Diana Göhringer

    2011-01-01

    Full Text Available Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip. Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System, which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.

  14. Schematic Approach to Information Services Reconfiguration

    Directory of Open Access Journals (Sweden)

    Sabah Al-Fedaghi

    2015-02-01

    Full Text Available Information system change is concerned with deliberate modifications to an organization’s technical and organiza‐ tional subsystems that deal with information. Changes result in adjustments being made to the configuration of information systems that could have an impact on the operations of those systems. This paper examines the problem of interference between old configuration activi‐ ties, new configuration activities and reconfiguration activities that occur due to overlapping modes. The paper proposes a novel form of depicting and solving the problem based on a flow-based conceptualization in which a configuration can be viewed as a system of flow systems organized architecturally, described by their internal flows, and connected by external flows and triggering. This method of diagramming is applied to a complex case study involving the reconfiguration of an office workflow for order processing described in BPMN. The diagrams resulting from this method and the BPMN diagrams are then examined side by side. Accordingly, the conclusion is that a new high-level representation seems more system‐ atic as a foundation for building a conceptual schema of business processes.

  15. Advances in Reconfigurable Mechanisms and Robots I

    CERN Document Server

    Zoppi, Matteo; Kong, Xianwen

    2012-01-01

    Advances in Reconfigurable Mechanisms and Robots I provides a selection of key papers presented in The Second ASME/IFToMM International Conference on Reconfigurable Mechanisms and Robots (ReMAR 2012) held on 9th -11th  July 2012 in Tianjin, China. This ongoing series of conferences will be covered in this ongoing collection of books.   A total of seventy-eight papers are divided into seven parts to cover the topology, kinematics and design of reconfigurable mechanisms with the reconfiguration theory, analysis and synthesis, and present the current research and development in the field of reconfigurable mechanisms including reconfigurable parallel mechanisms. In this aspect, the recent study and development of reconfigurable robots are further presented with the analysis and design and with their control and development. The bio-inspired mechanisms and subsequent reconfiguration are explored in the challenging fields of rehabilitation and minimally invasive surgery. Advances in Reconfigurable Mechanisms and ...

  16. Reconfigurable Reflectarrays and Array Lenses for Dynamic Antenna Beam Control: A Review

    CERN Document Server

    Hum, Sean Victor

    2013-01-01

    Advances in reflectarrays and array lenses with electronic beam-forming capabilities are enabling a host of new possibilities for these high-performance, low-cost antenna architectures. This paper reviews enabling technologies and topologies of reconfigurable reflectarray and array lens designs, and surveys a range of experimental implementations and achievements that have been made in this area in recent years. The paper describes the fundamental design approaches employed in realizing reconfigurable designs, and explores advanced capabilities of these nascent architectures, such as multi-band operation, polarization manipulation, frequency agility, and amplification. Finally, the paper concludes by discussing future challenges and possibilities for these antennas.

  17. VLSI Implementation of Encryption and Decryption System Using Hamming Code Algorithm

    Directory of Open Access Journals (Sweden)

    Fazal Noorbasha

    2014-04-01

    Full Text Available In this paper, we propose an optimized VLSI implementation of encryption and decryption system using hamming code algorithm. In the present field of communication has got many applications, and in every field the data is encoded at the transmitter and transfer on a communication channel and receive at the receiver after data is decoded. During the broadcast of data it might get degraded because of some noise on the channel. So it is crucial for the receiver to have some function which can recognize and correct the error in the received data. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. In order to do that the proposed method uses a Field Programmable Gate Array (FPGA. It is known that FPGA provides quick implementation and fast hardware verification. It gives facilities of reconfiguring the design construct unlimited number of times. The HDL code is written in verilog, Gate Level Circuit and Layout is implemented in CMOS technology.

  18. 一种改进信道化结构的宽带信号重构方法%A Wide-Band Signal Reconfiguration Method Based on Improved Channelized Architecture

    Institute of Scientific and Technical Information of China (English)

    高希光; 左佑

    2015-01-01

    数字信道化技术广泛用于宽带信号处理领域,传统的信道化结构由于信道数和抽取(内插)数相等,相邻信道存在混叠问题,对于跨信道信号接收、重构存在很大程度失真。提出一种改进的信道化结构,推导了相应的多相滤波高效算法,最后通过Matlab仿真验证该算法具有很好的改进效果。%Digital channelized technique is widely applied on the wide-band signal processing area. As the number of channels equals to the decimating factor(also inserting factor),classic channelized structure has to face the aliasing issues from the overlapping channels, which em-ploys great distortion for the wide-band signal receiving and reconfiguration. An improved chan-nelized structure is proposed,which also deduces the poly-phase filter banks algorithm. Finally the simulation by Matlab shows the method has an excellent result.

  19. Effects of multi-context information recorded at different regions in holographic polymer-dispersed liquid crystal on optical reconfiguration

    Science.gov (United States)

    Ogiwara, Akifumi; Watanabe, Minoru

    2016-08-01

    A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by constructing a laser illumination system to implement successive laser exposures at different small regions in a glass cell filled with LC composites. The context pattern arrangements for circuit information are designed in a 3 × 3 in.2 photomask by electron beam lithography, and they are recorded as laser interference patterns at nine regions separated in an HPDLC sample by a laser interferometer composed of movable pinhole and photomask plates placed on motorized stages. The multi-context information reconstructed from the different regions in the HPDLC is written to a photodiode array in a gate-array VLSI by switching only the position of laser irradiation using the displacement of the pinhole plate under the control of a personal computer (PC). The effects of multi-context information recorded at different regions in the HPDLC on optical reconfiguration are discussed in terms of the optical system composed of ORGA VLSI and HPDLC memory. The internal structures in the HPDLC memory formed by multi-context recording are investigated by scanning electron microscopy (SEM) observation, and the configurations composed of LC and polymer phases are revealed at various regions in the HPDLC memory.

  20. Knowledge-based synthesis of custom VLSI physical design tools: First steps

    Science.gov (United States)

    Setliff, Dorothy E.; Rutenbar, Rob A.

    A description is given of how program synthesis techniques can be applied to the synthesis of technology-sensitive VLSI physical design tools. Physical design refers to the process of reducing a structural description of a piece of hardware down to the geometric layout of an integrated circuit. Successful physical design tools must cope with shifting technology and application environments. The goal is to automatically generate a tool's implementation to match the application. The authors describe a synthesis architecture that combines knowledge of the application domain and knowledge of generic programming mechanics. The approach uses a very high-level language to describe algorithms, domain and programming knowledge to select appropriate algorithms and data structures, and code generation to arrive at final executable code. Results are presented detailing the performance and implementation of ELF, a prototype generator for wire-routing applications. Comparisons between a hand-crafted router and an automatically synthesized router are presented.

  1. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  2. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    P.A.HarshaVardhini

    2012-04-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wide band communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multi bit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  3. High Speed Continuous-Time Bandpass Σ∆ADC for Mixed Signal VLSI Chips

    Directory of Open Access Journals (Sweden)

    M.Madhavi Latha

    2012-05-01

    Full Text Available With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆ converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

  4. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  5. Synchronous Control of Reconfiguration in Fractal Component-based Systems -- a Case Study

    CERN Document Server

    Bouhadiba, Tayeb; Delaval, Gwenaël; Rutten, Éric

    2011-01-01

    In the context of component-based embedded systems, the management of dynamic reconfiguration in adaptive systems is an increasingly important feature. The Fractal component-based framework, and its industrial instantiation MIND, provide for support for control operations in the lifecycle of components. Nevertheless, the use of complex and integrated architectures make the management of this reconfiguration operations difficult to handle by programmers. To address this issue, we propose to use Synchronous languages, which are a complete approach to the design of reactive systems, based on behavior models in the form of transition systems. Furthermore, the design of closed-loop reactive managers of reconfigurations can benefit from formal tools like Discrete Controller Synthesis. In this paper we describe an approach to concretely integrate synchronous reconfiguration managers in Fractal component-based systems. We describe how to model the state space of the control problem, and how to specify the control obj...

  6. A Web-Based Integration Procedure for the Development of Reconfigurable Robotic Work-Cells

    Directory of Open Access Journals (Sweden)

    Paulo Ferreira

    2013-07-01

    Full Text Available Concepts related to the development of reconfigurable manufacturing systems (RMS and methodologies to provide the best practices in the processing industry and factory automation, such as system integration and web‐based technology, are major issues in designing next‐generation manufacturing systems (NGMS. Adaptable and integrable devices are crucial for the success of NGMS. In robotic cells the integration of manufacturing components is essential to accelerate system adaptability. Sensors, control architectures and communication technologies have contributed to achieving further agility in reconfigurable factories. In this work a web‐based robotic cell integration procedure is proposed to aid the identification of reconfigurable issues and requirements. This methodology is applied to an industrial robot manipulator to enhance system flexibility towards the development of a reconfigurable robotic platform.

  7. ProperCAD: A portable object-oriented parallel environment for VLSI CAD

    Science.gov (United States)

    Ramkumar, Balkrishna; Banerjee, Prithviraj

    1993-01-01

    Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. A new project under way to address this problem is described. A Portable object-oriented parallel environment for CAD algorithms (ProperCAD) is being developed. The objectives of this research are (1) to develop new parallel algorithms that run in a portable object-oriented environment (CAD algorithms using a general purpose platform for portable parallel programming called CARM is being developed and a C++ environment that is truly object-oriented and specialized for CAD applications is also being developed); and (2) to design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface (permitting the parallel algorithm to benefit from future developments in sequential algorithms). One CAD application that has been implemented as part of the ProperCAD project, flat VLSI circuit extraction, is described. The algorithm, its implementation, and its performance on a range of parallel machines are discussed in detail. It currently runs on an Encore Multimax, a Sequent Symmetry, Intel iPSC/2 and i860 hypercubes, a NCUBE 2 hypercube, and a network of Sun Sparc workstations. Performance data for other applications that were developed are provided: namely test pattern generation for sequential circuits, parallel logic synthesis, and standard cell placement.

  8. MEMS-Reconfigurable Metamaterials and Antenna Applications

    OpenAIRE

    Tomislav Debogovic; Julien Perruisseau-Carrier

    2014-01-01

    This paper reviews some of our contributions to reconfigurable metamaterials, where dynamic control is enabled by micro-electro-mechanical systems (MEMS) technology. First, we show reconfigurable composite right/left handed transmission lines (CRLH-TLs) having state of the art phase velocity variation and loss, thereby enabling efficient reconfigurable phase shifters and leaky-wave antennas (LWA). Second, we present very low loss metasurface designs with reconfigurable reflection properties, ...

  9. Network-based reconfiguration routes for a self-reconfigurable robot

    Institute of Scientific and Technical Information of China (English)

    LIU JinGuo; MA ShuGen; WANG YueChao; LI Bin

    2008-01-01

    This paper presents a network-based analysis approach for the reconfiguration problem of a self-reconfigurable robot.The self-reconfigurable modular robot named "AMOEBA-Ⅰ" has nine kinds of non-isomorphic configurations that consist of a configuration network.Each configuration of the robot is defined to be a node in the weighted and directed configuration network.The transformation from one configuration to another is represented by a directed path with nonnegative weight.Graph theory is applied in the reconfiguration analysis,where reconfiguration route,reconfigurable matrix and route matrix are defined according to the topological information of these configurations.Algorithms in graph theory have been used in enumerating the available reconfiguration routes and deciding the best reconfiguration route.Numerical analysis and experimental simulation results prove the validity of the approach proposed in this paper.And it is potentially suitable for other self-reconfigurable robots' configuration control and reconfiguration planning.

  10. Efficient architectures for streaming applications

    NARCIS (Netherlands)

    Smit, Gerard J.M.; Kokkeler, André B.J.; Wolkotte, Pascal T.; Burgwal, van de Marcel D.; Heysters, Paul M.; Athanas, P.; Becker, J.; Brebner, G.; Teich, J.

    2006-01-01

    This presentation will focus on algorithms and reconfigurable tiled architectures for streaming DSP applications. The tile concept will not only be applied on chip level but also on board-level and system-level. The tile concept has a number of advantages: (1) depending on the requirements more or l

  11. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  12. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  13. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  14. PRCA:A highly efficient computing architecture

    Institute of Scientific and Technical Information of China (English)

    Luo Xingguo

    2014-01-01

    Applications can only reach 8 %~15 % of utilization on modern computer systems. There are many obstacles to improving system efficiency. The key root is the conflict between the fixed general computer architecture and the variable requirements of applications. Proactive reconfigurable computing architecture (PRCA) is proposed to improve computing efficiency. PRCA dynamically constructs an efficient computing ar chitecture for a specific application via reconfigurable technology by perceiving requirements,workload and utilization of computing resources. Proactive decision support system (PDSS),hybrid reconfigurable computing array (HRCA) and reconfigurable interconnect (RIC) are intensively researched as the key technologies. The principles of PRCA have been verified with four applications on a test bed. It is shown that PRCA is feasible and highly efficient.

  15. A First Step Towards High-Level Cost Models for the Implementation of SDRs on Multiprocessing Reconfigurable Systems

    DEFF Research Database (Denmark)

    Le Moullec, Yannick

    2011-01-01

    -In-Progress paper we introduce our set of high-level estimation models for Area-Time costs of applications mapped onto FPGA-based multiprocessing reconfigurable architectures. In particular, we suggest models for static and dynamic implementations, taking various internal and external architectural elements...

  16. Antenna reconfiguration verification and validation

    Science.gov (United States)

    Becker, Robert C. (Inventor); Meyers, David W. (Inventor); Muldoon, Kelly P. (Inventor); Carlson, Douglas R. (Inventor); Drexler, Jerome P. (Inventor)

    2009-01-01

    A method of testing the electrical functionality of an optically controlled switch in a reconfigurable antenna is provided. The method includes configuring one or more conductive paths between one or more feed points and one or more test point with switches in the reconfigurable antenna. Applying one or more test signals to the one or more feed points. Monitoring the one or more test points in response to the one or more test signals and determining the functionality of the switch based upon the monitoring of the one or more test points.

  17. Reconfigurable FFT Processor – A Broader Perspective Survey

    Directory of Open Access Journals (Sweden)

    V.Sarada

    2013-04-01

    Full Text Available The FFT(Fast Fourier Transform processing is one of the key procedure in the popular orthogonal frequency division multiplexing(OFDM based communication system such as Digital AudioBroadcasting(DAB,Digital Video Broadcasting Terrestrial(DVB- T,Asymmetric Digital Subscriber Loop(ADSL etc.These application domain require performing FFT in various size from 64 to 8192 point. Implementing each FFT on a dedicated IP presents a great overhead in silicon area of the chip. By supporting the different sizes of FFT for new wireless telecommunication standard may increase the time to market it. This consideration make FFT ideal candidate for reconfigurable implementation. Efficient implementation of the FFT processor with small area, low power and speed is very important. This survey paper aims at a study on efficient algorithm and architecture for reconfigurable FFT design and observes common traits of the good contribution.

  18. Self-reconfiguring microservices

    DEFF Research Database (Denmark)

    Gabbrielli, Maurizio; Giallorenzo, Saverio; Guidi, Claudio

    2016-01-01

    Microservices is an emerging paradigm for the development of distributed systems that, originating from Service-Oriented Architecture, focuses on the small dimension, the loose coupling, and the dynamic topology of services. Microservices are particularly appropriate for the development...... of distributed systems in the Cloud. However, their dynamic nature calls for suitable techniques for their automatic deployment. In this paper we address this problem and we propose JRO (Jolie Redeployment Optimiser), a tool for the automatic and optimised deployment of microservices written in the Jolie...

  19. Secure computing on reconfigurable systems

    NARCIS (Netherlands)

    Fernandes Chaves, R.J.

    2007-01-01

    This thesis proposes a Secure Computing Module (SCM) for reconfigurable computing systems. SC provides a protected and reliable computational environment, where data security and protection against malicious attacks to the system is assured. SC is strongly based on encryption algorithms and on the

  20. Channel Communication and Reconfigurable Hardware

    NARCIS (Netherlands)

    Bos, M.; Havinga, Paul J.M.; Smit, Gerardus Johannes Maria; Karelse, F.

    2000-01-01

    Many applications can be structured as a set of processes or threads that communicate via channels. These threads can be executed on various platforms (e.g. general purpose CPU, DSP, FPGA, etc). In our research we apply channels as a basic communication mechanism between threads in a reconfigurable

  1. Secure computing on reconfigurable systems

    NARCIS (Netherlands)

    Fernandes Chaves, R.J.

    2007-01-01

    This thesis proposes a Secure Computing Module (SCM) for reconfigurable computing systems. SC provides a protected and reliable computational environment, where data security and protection against malicious attacks to the system is assured. SC is strongly based on encryption algorithms and on the a

  2. CMOS VLSI Layout and Verification of a SIMD Computer

    Science.gov (United States)

    Zheng, Jianqing

    1996-01-01

    A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

  3. A special purpose silicon compiler for designing supercomputing VLSI systems

    Science.gov (United States)

    Venkateswaran, N.; Murugavel, P.; Kamakoti, V.; Shankarraman, M. J.; Rangarajan, S.; Mallikarjun, M.; Karthikeyan, B.; Prabhakar, T. S.; Satish, V.; Venkatasubramaniam, P. R.

    1991-01-01

    Design of general/special purpose supercomputing VLSI systems for numeric algorithm execution involves tackling two important aspects, namely their computational and communication complexities. Development of software tools for designing such systems itself becomes complex. Hence a novel design methodology has to be developed. For designing such complex systems a special purpose silicon compiler is needed in which: the computational and communicational structures of different numeric algorithms should be taken into account to simplify the silicon compiler design, the approach is macrocell based, and the software tools at different levels (algorithm down to the VLSI circuit layout) should get integrated. In this paper a special purpose silicon (SPS) compiler based on PACUBE macrocell VLSI arrays for designing supercomputing VLSI systems is presented. It is shown that turn-around time and silicon real estate get reduced over the silicon compilers based on PLA's, SLA's, and gate arrays. The first two silicon compiler characteristics mentioned above enable the SPS compiler to perform systolic mapping (at the macrocell level) of algorithms whose computational structures are of GIPOP (generalized inner product outer product) form. Direct systolic mapping on PLA's, SLA's, and gate arrays is very difficult as they are micro-cell based. A novel GIPOP processor is under development using this special purpose silicon compiler.

  4. Boolean approaches to graph embeddings related to VLSI

    Institute of Scientific and Technical Information of China (English)

    刘彦佩

    2001-01-01

    This paper discusses the development of Boolean methods in some topics on graph em-beddings which are related to VLSI. They are mainly the general theory of graph embeddability, the orientabilities of a graph and the rectilinear layout of an electronic circuit.

  5. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  6. Tungsten and other refractory metals for VLSI applications II

    Energy Technology Data Exchange (ETDEWEB)

    Broadbent, E.K.

    1987-01-01

    This book presents papers on tungsten and other refractory metals for VLSI applications. Topics include the following: Selectivity loss and nucleation on insulators, fundamental reaction and growth studies, chemical vapor deposition of tungsten, chemical vapor deposition of molybdenum, reactive ion etching of refractory metal films; and properties of refractory metals deposited by sputtering.

  7. An Interactive Multimedia Learning Environment for VLSI Built with COSMOS

    Science.gov (United States)

    Angelides, Marios C.; Agius, Harry W.

    2002-01-01

    This paper presents Bigger Bits, an interactive multimedia learning environment that teaches students about VLSI within the context of computer electronics. The system was built with COSMOS (Content Oriented semantic Modelling Overlay Scheme), which is a modelling scheme that we developed for enabling the semantic content of multimedia to be used…

  8. An Automated Test Framework for Experimenting with Stochastic Behavior in Reconfigurable Logic

    DEFF Research Database (Denmark)

    Birklykke, Alex Aaen; Le Moullec, Yannick; Alminde, Lars

    2012-01-01

    -level. As an experimental platform, we propose to use an FPGA due to the proven value of reconfigurable architectures in design space exploration. We hypothesize that stochastic behavior can be introduced in FPGAs using external noise sources; a fact that is later confirmed by characterizing the behavior of an FPGA IO...

  9. A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

    Directory of Open Access Journals (Sweden)

    Diana Göhringer

    2009-01-01

    Full Text Available Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.

  10. Robot Electronics Architecture

    Science.gov (United States)

    Garrett, Michael; Magnone, Lee; Aghazarian, Hrand; Baumgartner, Eric; Kennedy, Brett

    2008-01-01

    An electronics architecture has been developed to enable the rapid construction and testing of prototypes of robotic systems. This architecture is designed to be a research vehicle of great stability, reliability, and versatility. A system according to this architecture can easily be reconfigured (including expanded or contracted) to satisfy a variety of needs with respect to input, output, processing of data, sensing, actuation, and power. The architecture affords a variety of expandable input/output options that enable ready integration of instruments, actuators, sensors, and other devices as independent modular units. The separation of different electrical functions onto independent circuit boards facilitates the development of corresponding simple and modular software interfaces. As a result, both hardware and software can be made to expand or contract in modular fashion while expending a minimum of time and effort.

  11. Adaptive Architectural Envelope

    DEFF Research Database (Denmark)

    Foged, Isak Worre; Kirkegaard, Poul Henning

    2010-01-01

    different shape alternatives. The adaptive structure is a proposal for a responsive building envelope which is an idea of a first level operational framework for present and future investigations towards performance based responsive architectures through a set of responsive typologies. A mock- up concept......Recent years have seen an increasing variety of applications of adaptive architectural structures for improvement of structural performance by recognizing changes in their environments and loads, adapting to meet goals, and using past events to improve future performance or maintain serviceability....... The general scopes of this paper are to develop a new adaptive kinetic architectural structure, particularly a reconfigurable architectural structure which can transform body shape from planar geometries to hyper-surfaces using different control strategies, i.e. a transformation into more than one or two...

  12. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  13. ETSI-Standard Reconfigurable Mobile Device for Supporting the Licensed Shared Access

    Directory of Open Access Journals (Sweden)

    Kyunghoon Kim

    2016-01-01

    Full Text Available In order for a Mobile Device (MD to support the Licensed Shared Access (LSA, the MD should be reconfigurable, meaning that the configuration of a MD must be adaptively changed in accordance with the communication standard adopted in a given LSA system. Based on the standard architecture for reconfigurable MD defined in Working Group (WG 2 of the Technical Committee (TC Reconfigurable Radio System (RRS of the European Telecommunications Standards Institute (ETSI, this paper presents a procedure to transfer control signals among the software entities of a reconfigurable MD required for implementing the LSA. This paper also presents an implementation of a reconfigurable MD prototype that realizes the proposed procedure. The modem and Radio Frequency (RF part of the prototype MD are implemented with the NVIDIA GeForce GTX Titan Graphic Processing Unit (GPU and the Universal Software Radio Peripheral (USRP N210, respectively. With a preset scenario that consists of five time slots from different signal environments, we demonstrate superb performance of the reconfigurable MD in comparison to the conventional nonreconfigurable MD in terms of the data receiving rate available in the LSA band at 2.3–2.4 GHz.

  14. On Control Strategies for Responsive Architectural Structures

    DEFF Research Database (Denmark)

    Kirkegaard, Poul Henning; Parigi, Dario

    2012-01-01

    The present paper considers control of responsive architectural structures for improvement of structural performance by recognizing changes in their environments and loads, adapting to meet goals, and using past events to improve future performance or maintain serviceability. The general scope...... of the paper is to discuss control strategies for responsive architectural structures, particularly reconfigurable architectural structures which can transform body shape, i.e. a transformation into more than one or two different shape alternatives....

  15. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers

    Directory of Open Access Journals (Sweden)

    Rozita Teymourzadeh

    2010-01-01

    Full Text Available Problem statement: The need for high performance transceiver with high Signal to Noise Ratio (SNR has driven the communication system to utilize latest technique identified as over sampling systems. It was the most economical modulator and decimation in communication system. It has been proven to increase the SNR and is used in many high performance systems such as in the Analog to Digital Converter (ADC for wireless transceiver. Approach: This research presented the design of the novel class of decimation and its VLSI implementation which was the sub-component in the over sampling technique. The design and realization of main unit of decimation stage that was the Cascaded Integrator Comb (CIC filter, the associated half band filters and the droop correction are also designed. The Verilog HDL code in Xilinx ISE environment has been derived to describe the proposed advanced CIC filter properties. Consequently, Virtex-II FPGA board was used to implement and test the design on the real hardware. The ASIC design implementation was performed accordingly and resulted power and area measurement on chip core layout. Results: The proposed design focused on the trade-off between the high speed and the low power consumption as well as the silicon area and high resolution for the chip implementation which satisfies wireless communication systems. The synthesis report illustrates the maximum clock frequency of 332 MHz with the active core area of 0.308×0.308 mm2. Conclusion: It can be concluded that VLSI implementation of proposed filter architecture is an enabler in solving problems that affect communication capability in DSP application.

  16. Low-complexity systolic architecture for inversion

    Institute of Scientific and Technical Information of China (English)

    Yuan Danshou; Rong Mengtian

    2006-01-01

    A modified extended binary Euclid's algorithm which is more regularly iterative for computing an inversion in GF(2m) is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has area complexity of O(m), latency of 5m-2, and throughput of 1/m. Compared with other serial systolic architectures, the proposed one has the smallest area complexity, shorter latency. It is highly regular, modular, and thus well suited for high-speed VLSI design.

  17. Symmetric reconfigurable capacity assignment in a bidirectional DWDM access network.

    Science.gov (United States)

    Ortega, Beatriz; Mora, José; Puerto, Gustavo; Capmany, José

    2007-12-10

    This paper presents a novel architecture for DWDM bidirectional access networks providing symmetric dynamic capacity allocation for both downlink and uplink signals. A foldback arrayed waveguide grating incorporating an optical switch enables the experimental demonstration of flexible assignment of multiservice capacity. Different analog and digital services, such as CATV, 10 GHz-tone, 155Mb/s PRBS and UMTS signals have been transmitted in order to successfully test the system performance under different scenarios of total capacity distribution from the Central Station to different Base Stations with two reconfigurable extra channels for each down and upstream direction.

  18. A reconfigurable optoelectronic interconnect technology for multi-processor networks

    Energy Technology Data Exchange (ETDEWEB)

    Lu, Y.C.; Cheng, J. [Univ. of New Mexico, Albuquerque, NM (United States). Center for High Technology Materials; Zolper, J.C.; Klem, J. [Sandia National Labs., Albuquerque, NM (United States)

    1995-05-01

    This paper describes a new optical interconnect architecture and the integrated optoelectronic circuit technology for implementing a parallel, reconfigurable, multiprocessor network. The technology consists of monolithic array`s of optoelectronic switches that integrate vertical-cavity surface-emitting lasers with three-terminal heterojunction phototransistors, which effectively combined the functions of an optical transceiver and an optical spatial routing switch. These switches have demonstrated optical switching at 200 Mb/s, and electrical-to-optical data conversion at > 500 Mb/s, with a small-signal electrical-to-optical modulation bandwidth of {approximately} 4 GHz.

  19. Reconfigurable microfluidic nanoparticle trapping using dielectrophoresis for chemical detection

    Science.gov (United States)

    Salemmilani, Reza; Piorek, Brian; Moskovits, Martin; Meinhart, Carl

    2016-11-01

    We report a microfluidic particle manipulation platform based on dielectrophoresis (DEP) to capture and release nanoscale particles cyclically via reconfigurable traps. DEP is routinely used in microfluidic devices for capturing and trapping cells and particles of various sizes, however the trapping of small nanoparticles by DEP is challenging due to the inverse relationship of the DEP force with particle size. The architecture we describe uses electrically insulating silica beads of micron scale in conjunction with DEP electrodes configured to manipulate nanoscale particles for microfluidic applications such as filtration and chemical detection. Department of Mechanical Engineering, University of California, Santa Barbara, California 93106, United States.

  20. Reconfigurable quadruple quantum dots in a silicon nanowire transistor

    Energy Technology Data Exchange (ETDEWEB)

    Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F. [Hitachi Cambridge Laboratory, J. J. Thomson Avenue, Cambridge CB3 0HE (United Kingdom); Tagliaferri, M. L. V. [Laboratorio MDM, CNR-IMM, Via C. Olivetti 2, 20864 Agrate Brianza (MB) (Italy); Dipartimento di Scienza dei Materiali, Universit di Milano-Bicocca, Via Cozzi 53, 20125 Milano (Italy); Vinet, M. [CEA/LETI-MINATEC, CEA-Grenoble, 17 rue des martyrs, F-38054 Grenoble (France); Sanquer, M. [SPSMS, UMR-E CEA/UJF-Grenoble 1, INAC, 17 rue des Martyrs, 38054 Grenoble (France); Ferguson, A. J. [Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE (United Kingdom)

    2016-05-16

    We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

  1. Reconfigurable RF Energy Harvester with Customized Differential PCB Antenna

    Directory of Open Access Journals (Sweden)

    Alessandro Bertacchini

    2015-11-01

    Full Text Available In this work, a Radio Frequency (RF Energy Harvester comprised of a differential Radio Frequency-to-Direct Current (RF-DC converter realized in ST130 nm Complementary Metal-Oxide-Semiconductor (CMOS technology and a customized broadband Printed Circuit Board (PCB antenna with inductive coupling feeding is presented. Experimental results show that the system can work with different carrier frequencies and thanks to its reconfigurable architecture the proposed converter is able to provide a regulated output voltage of 2 V over a 14 dB of RF input power range. The conversion efficiency of the whole system peaks at 18% under normal outdoor working conditions.

  2. Origami tubes with reconfigurable polygonal cross-sections.

    Science.gov (United States)

    Filipov, E T; Paulino, G H; Tachi, T

    2016-01-01

    Thin sheets can be assembled into origami tubes to create a variety of deployable, reconfigurable and mechanistically unique three-dimensional structures. We introduce and explore origami tubes with polygonal, translational symmetric cross-sections that can reconfigure into numerous geometries. The tubular structures satisfy the mathematical definitions for flat and rigid foldability, meaning that they can fully unfold from a flattened state with deformations occurring only at the fold lines. The tubes do not need to be straight and can be constructed to follow a non-linear curved line when deployed. The cross-section and kinematics of the tubular structures can be reprogrammed by changing the direction of folding at some folds. We discuss the variety of tubular structures that can be conceived and we show limitations that govern the geometric design. We quantify the global stiffness of the origami tubes through eigenvalue and structural analyses and highlight the mechanical characteristics of these systems. The two-scale nature of this work indicates that, from a local viewpoint, the cross-sections of the polygonal tubes are reconfigurable while, from a global viewpoint, deployable tubes of desired shapes are achieved. This class of tubes has potential applications ranging from pipes and micro-robotics to deployable architecture in buildings.

  3. Design of reconfigurable logic controllers

    CERN Document Server

    Bukowiec, Arkadiusz; Doligalski, Michał; Tkacz, Jacek

    2016-01-01

    This book presents the original concepts and modern techniques for specification, synthesis, optimisation and implementation of parallel logical control devices. It deals with essential problems of reconfigurable control systems like dependability, modularity and portability. Reconfigurable systems require a wider variety of design and verification options than the application-specific integrated circuits. The book presents a comprehensive selection of possible design techniques. The diversity of the modelling approaches covers Petri nets, state machines and activity diagrams. The preferences of the presented optimization and synthesis methods are not limited to increasing of the efficiency of resource use. One of the biggest advantages of the presented methods is the platform independence, the FPGA devices and single board computers are some of the examples of possible platforms. These issues and problems are illustrated with practical cases of complete control systems. If you expect a new look at the recon...

  4. Reconfigurable Microwave Photonic Topological Insulator

    Science.gov (United States)

    Goryachev, Maxim; Tobar, Michael E.

    2016-12-01

    Using full 3D finite-element simulation and underlining Hamiltonian models, we demonstrate reconfigurable photonic analogues of topological insulators on a regular lattice of tunable posts in a reentrant 3D lumped element-type system. The tunability allows a dynamical in situ change of media chirality and other properties via the alteration of the same parameter for all posts, and as a result, great flexibility in the choice of bulk-edge configurations. Additionally, one-way photon transport without an external magnetic field is demonstrated. The ideas are illustrated by using both full finite-element simulation as well as simplified harmonic oscillator models. Dynamical reconfigurability of the proposed systems paves the way to a class of systems that can be employed for random access, topological signal processing, and sensing.

  5. Reconfigurable Microwave Photonic Topological Insulator

    CERN Document Server

    Goryachev, Maxim

    2016-01-01

    We demonstrate reconfigurable photonic analogues of topological insulators on a regular lattice of tunable posts in a re-entrant 3D lumped element type system. The tunability allows dynamical {\\it in-situ} change of media chirality and other properties via change of a single post parameter, and as a result, great flexibility in choice of bulk/edge configurations. Additionally, one way photon transport without external magnetic field is demonstrated. The ideas are illustrated by using both full finite element simulation as well as simplified harmonic oscillator models. Reconfigurability of the proposed systems paves the wave to a new class of systems that can be employed for random access, topological signal processing and sensing.

  6. Dynamic reconfiguration in sensor middleware

    OpenAIRE

    Grace, P.; Coulson, G; Blair, Gordon S.; Porter, B. (collab.); Hughes, Daniel

    2006-01-01

    Middleware solutions for sensor networks have so far mainly focused on communication abstractions, ad-hoc message routing protocols, and power conservation techniques. We argue that customisation and dynamic reconfiguration of sensor network middleware are additional important dimensions to consider. This paper describes a sensor middleware that can be customised to suit different sensor application types, and provides a reflective approach for co-ordinated network-wide dynamic reconfiguratio...

  7. Structures with Reconfigurable Circulatory Systems

    Science.gov (United States)

    2008-05-16

    crosslinked material; whereas exposure to a different wavelength of light should reverse the crosslinking reaction and reform a liquid material...terminated LDI- glycerol polymer. Structures with Reconfigurable Circulatory Systems - Clark, Beckman, Cho, Weiland, and Bielawski 3 C..,c (Glutathione...reduced) (Glutathione, oxidized) C 4 V ’ " - .- x,,, ’- %. Figure 1:3. Scheme 11: Dissolution-gelation of Cysteine terminated LDI- glycerol polymer gel

  8. Lattice reconfiguration and phononic band-gap adaptation via origami folding

    Science.gov (United States)

    Thota, M.; Li, S.; Wang, K. W.

    2017-02-01

    We introduce a framework of utilizing origami folding to redistribute the inclusions of a phononic structure to achieve significant phononic band-gap adaptation. Cylindrical inclusions are attached to the vertices of a Miura-Ori sheet, whose 1 degree-of-freedom rigid folding can enable fundamental reconfigurations in the underlying periodic architecture via switching between different Bravais lattice types. Such a reconfiguration can drastically change the wave propagation behavior in terms of band gap and provide a scalable and practical means for broadband wave tailoring.

  9. Novel Highly Parallel and Systolic Architectures Using Quantum Dot-Based Hardware

    Science.gov (United States)

    Fijany, Amir; Toomarian, Benny N.; Spotnitz, Matthew

    1997-01-01

    VLSI technology has made possible the integration of massive number of components (processors, memory, etc.) into a single chip. In VLSI design, memory and processing power are relatively cheap and the main emphasis of the design is on reducing the overall interconnection complexity since data routing costs dominate the power, time, and area required to implement a computation. Communication is costly because wires occupy the most space on a circuit and it can also degrade clock time. In fact, much of the complexity (and hence the cost) of VLSI design results from minimization of data routing. The main difficulty in VLSI routing is due to the fact that crossing of the lines carrying data, instruction, control, etc. is not possible in a plane. Thus, in order to meet this constraint, the VLSI design aims at keeping the architecture highly regular with local and short interconnection. As a result, while the high level of integration has opened the way for massively parallel computation, practical and full exploitation of such a capability in many applications of interest has been hindered by the constraints on interconnection pattern. More precisely. the use of only localized communication significantly simplifies the design of interconnection architecture but at the expense of somewhat restricted class of applications. For example, there are currently commercially available products integrating; hundreds of simple processor elements within a single chip. However, the lack of adequate interconnection pattern among these processing elements make them inefficient for exploiting a large degree of parallelism in many applications.

  10. MEMS-Reconfigurable Metamaterials and Antenna Applications

    Directory of Open Access Journals (Sweden)

    Tomislav Debogovic

    2014-01-01

    Full Text Available This paper reviews some of our contributions to reconfigurable metamaterials, where dynamic control is enabled by microelectromechanical systems (MEMS technology. First, we show reconfigurable composite right-/left-handed transmission lines (CRLH-TLs having state of the art phase velocity variation and loss, thereby enabling efficient reconfigurable phase shifters and leaky-wave antennas (LWA. Second, we present very low loss metasurface designs with reconfigurable reflection properties, applicable in reflectarrays and partially reflective surface (PRS antennas. All the presented devices have been fabricated and experimentally validated. They operate in X- and Ku-bands.

  11. Reconfigurable metamaterials for terahertz wave manipulation

    Science.gov (United States)

    Hashemi, Mohammed R.; Cakmakyapan, Semih; Jarrahi, Mona

    2017-09-01

    Reconfigurable metamaterials have emerged as promising platforms for manipulating the spectral and spatial properties of terahertz waves without being limited by the characteristics of naturally existing materials. Here, we present a comprehensive overview of various types of reconfigurable metamaterials that are utilized to manipulate the intensity, phase, polarization, and propagation direction of terahertz waves. We discuss various reconfiguration mechanisms based on optical, electrical, thermal, and mechanical stimuli while using semiconductors, superconductors, phase-change materials, graphene, and electromechanical structures. The advantages and disadvantages of different reconfigurable metamaterial designs in terms of modulation efficiency, modulation bandwidth, modulation speed, and system complexity are discussed in detail.

  12. Reconfiguration of Analog Electronics for Extreme Environments

    Science.gov (United States)

    Stoica, Adrian; Zebulum, Ricardo; Keymeulen, Didier; Guo, Xin

    2005-01-01

    This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfgurable devices were exposed to, and degraded by, high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms.

  13. MEMS-reconfigurable metamaterials and antenna applications

    CERN Document Server

    Debogovic, Tomislav

    2014-01-01

    This paper reviews some of our contributions to reconfigurable metamaterials, where dynamic control is enabled by micro-electro-mechanical systems (MEMS) technology. First, we show reconfigurable composite right/left handed transmission lines (CRLH-TLs) having state of the art phase velocity variation and loss, thereby enabling efficient reconfigurable phase shifters and leaky-wave antennas (LWA). Second, we present very low loss metasurface designs with reconfigurable reflection properties, applicable in reflectarrays and partially reflective surface (PRS) antennas. All the presented devices have been fabricated and experimentally validated. They operate in X- and Ku-bands.

  14. Reconfigurable cognitive transceiver for opportunistic networks

    Science.gov (United States)

    Maso, Marco; Baştuğ, Ejder; Cardoso, Leonardo S.; Debbah, Mérouane; Özdemir, Özgür

    2014-12-01

    In this work, we provide the implementation and analysis of a cognitive transceiver for opportunistic networks. We focus on a previously introduced dynamic spectrum access (DSA) - cognitive radio (CR) solution for primary-secondary coexistence in opportunistic orthogonal frequency division multiplexing (OFDM) networks, called cognitive interference alignment (CIA). The implementation is based on software-defined radio (SDR) and uses GNU Radio and the universal software radio peripheral (USRP) as the implementation toolkit. The proposed flexible transceiver architecture allows efficient on-the-fly reconfigurations of the physical layer into OFDM, CIA or a combination of both. Remarkably, its responsiveness is such that the uplink and downlink channel reciprocity from the medium perspective, inherent to time division duplex (TDD) communications, can be effectively verified and exploited. We show that CIA provides approximately 10 dB of interference isolation towards the OFDM receiver with respect to a fully random precoder. This result is obtained under suboptimal conditions, which indicates that further gains are possible with a better optimization of the system. Our findings point towards the usefulness of a practical CIA implementation, as it yields a non-negligible performance for the secondary system, while providing interference shielding to the primary receiver.

  15. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  16. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Directory of Open Access Journals (Sweden)

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  17. VLSI physical design analyzer: A profiling and data mining tool

    Science.gov (United States)

    Somani, Shikha; Verma, Piyush; Madhavan, Sriram; Batarseh, Fadi; Pack, Robert C.; Capodieci, Luigi

    2015-03-01

    Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.

  18. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  19. A novel 3D algorithm for VLSI floorplanning

    Science.gov (United States)

    Rani, D. Gracia N.; Rajaram, S.; Sudarasan, Athira

    2013-01-01

    3-D VLSI circuit is becoming a hot issue because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement in VLSI Physical design. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We analyze and categorize some state-of-the-art 3-D representations, and propose a Ternary tree model for 3-D nonslicing floorplans, extending the B*tree from 2D.This paper proposes a novel optimization algorithm for packing of 3D rectangular blocks. The new techniques considered are Differential evolutionary algorithm (DE) is very fast in that it evaluates the feasibility of a Ternary tree representation. Experimental results based on MCNC benchmark with constraints show that our proposed Differential Evolutionary (DE) can quickly produce optimal solutions.

  20. VLSI design for fault-dictionary based testability

    Science.gov (United States)

    Miller, Charles D.

    The fault-dictionary approach to isolating failures in digital circuits provides inferior isolation accuracy compared to that which is now generally attained with other isolation methods. This limitation is particularly apparent when circuits which use bidirectional bus configurations are being tested. For this reason, fault-dictionary-based isolation has serious economic implications when testing digital circuits which use expensive VLSI or HSIC devices. However, by incorporating relatively minor circuit additions into the design of VLSI and HSIC devices, the normal set/scan or equivalent testability pins can additionally serve to improve actual fault-isolation accuracy. The described additions for improving fault-dictionary-based fault isolation require little semiconductor area, and one configuration even serves to prevent bus-drive conflicts.

  1. Opto-VLSI-based tunable single-mode fiber laser.

    Science.gov (United States)

    Xiao, Feng; Alameh, Kamal; Lee, Tongtak

    2009-10-12

    A new tunable fiber ring laser structure employing an Opto-VLSI processor and an erbium-doped fiber amplifier (EDFA) is reported. The Opto-VLSI processor is able to dynamically select and couple a waveband from the gain spectrum of the EDFA into a fiber ring, leading to a narrow-linewidth high-quality tunable laser output. Experimental results demonstrate a tunable fiber laser of linewidth 0.05 nm and centre wavelength tuned over the C-band with a 0.05 nm step. The measured side mode suppression ratio (SMSR) is greater than 35 dB and the laser output power uniformity is better than 0.25 dB. The laser output is very stable at room temperature.

  2. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  3. Vlsi Implementation of Edge Detection for Images

    Directory of Open Access Journals (Sweden)

    T. Mahalakshmi

    2012-12-01

    Full Text Available Edge is the boundary between the image and its background. Edge detection in general is defined as the local maxima obtained from high pass filters, but an optimized edge detector should mark the edges with respect to luminance or brightness changes. It is easy to obtain them in software implementation but for hardware implementation there is an issue with percentage of accuracy and processing time. This study discusses various edge detection algorithms and proposes an optimized edge detector which provides the solution for mentioned above issue. Since FPGA provides practical solutions for most of the image processing problems, the proposed architecture has been developed using Matlab System generator. Experimental results show the accuracy of edge detected using proposed architecture.

  4. A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

    Directory of Open Access Journals (Sweden)

    Jim Harkin

    2009-01-01

    Full Text Available FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE, incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

  5. A systematic method for configuring VLSI networks of spiking neurons.

    Science.gov (United States)

    Neftci, Emre; Chicca, Elisabetta; Indiveri, Giacomo; Douglas, Rodney

    2011-10-01

    An increasing number of research groups are developing custom hybrid analog/digital very large scale integration (VLSI) chips and systems that implement hundreds to thousands of spiking neurons with biophysically realistic dynamics, with the intention of emulating brainlike real-world behavior in hardware and robotic systems rather than simply simulating their performance on general-purpose digital computers. Although the electronic engineering aspects of these emulation systems is proceeding well, progress toward the actual emulation of brainlike tasks is restricted by the lack of suitable high-level configuration methods of the kind that have already been developed over many decades for simulations on general-purpose computers. The key difficulty is that the dynamics of the CMOS electronic analogs are determined by transistor biases that do not map simply to the parameter types and values used in typical abstract mathematical models of neurons and their networks. Here we provide a general method for resolving this difficulty. We describe a parameter mapping technique that permits an automatic configuration of VLSI neural networks so that their electronic emulation conforms to a higher-level neuronal simulation. We show that the neurons configured by our method exhibit spike timing statistics and temporal dynamics that are the same as those observed in the software simulated neurons and, in particular, that the key parameters of recurrent VLSI neural networks (e.g., implementing soft winner-take-all) can be precisely tuned. The proposed method permits a seamless integration between software simulations with hardware emulations and intertranslatability between the parameters of abstract neuronal models and their emulation counterparts. Most important, our method offers a route toward a high-level task configuration language for neuromorphic VLSI systems.

  6. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    OpenAIRE

    Chávez-Bracamontes Ramón; García-López Reyna Itzel; Gurrola-Navarro Marco Antonio; Bandala-Sánchez Manuel

    2015-01-01

    This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored ...

  7. DESIGN AND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORK

    OpenAIRE

    2011-01-01

    Nature has evolved highly advanced systems capable of performing complex computations, adoption and learning using analog computations. Furthermore nature has evolved techniques to deal with imprecise analog computations by using redundancy and massive connectivity. In this paper we are making use of Artificial Neural Network to demonstrate the way in which the biological system processes in analog domain. We are using 180nm CMOS VLSI technology for implementing circuits which ...

  8. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  9. Diseño digital : una perspectiva VLSI-CMOS

    OpenAIRE

    Alcubilla González, Ramón; Pons Nin, Joan; Bardés Llorensí, Daniel

    1996-01-01

    Bibliografia El presente texto aporta el material necesario para un curso introductorio de Electrónica Digital. Incluye los conceptos fundamentales de diseño clásico de circuitos lógicos combinacionales y secuenciales. Adicionalmente se introducen aspectos de diseño de circuitos integrados con tecnología VLSI-CMOS. Se ha incidido particularmente en los elementos de autoaprendizaje mediante la inclusión de numerosos ejemplos y problemas.

  10. A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism

    Directory of Open Access Journals (Sweden)

    S. Ramachandran

    2002-01-01

    Full Text Available A dynamically reconfigurable scheme for video encoder to switch among many different applications is presented. The scheme is suitable for FPGA implementation and conforms to JPEG, MPEG-1, MPEG-2, and H.263 standards. The scheme has emerged as an efficient and cost-effective solution for video compression as a result of innovative design using well-partitioned algorithms, highly pipelined architecture and coarse-grain parallelism. The reconfiguration time of the video encoder is less than 320 μs while switching from one standard to another. Although the dynamic reconfiguration scheme is presented for a video encoder, the same design methodology may be applied effectively for any other application.

  11. Evolution of a designless nanoparticle network into reconfigurable Boolean logic

    Science.gov (United States)

    Bose, S. K.; Lawrence, C. P.; Liu, Z.; Makarenko, K. S.; van Damme, R. M. J.; Broersma, H. J.; van der Wiel, W. G.

    2015-12-01

    Natural computers exploit the emergent properties and massive parallelism of interconnected networks of locally active components. Evolution has resulted in systems that compute quickly and that use energy efficiently, utilizing whatever physical properties are exploitable. Man-made computers, on the other hand, are based on circuits of functional units that follow given design rules. Hence, potentially exploitable physical processes, such as capacitive crosstalk, to solve a problem are left out. Until now, designless nanoscale networks of inanimate matter that exhibit robust computational functionality had not been realized. Here we artificially evolve the electrical properties of a disordered nanomaterials system (by optimizing the values of control voltages using a genetic algorithm) to perform computational tasks reconfigurably. We exploit the rich behaviour that emerges from interconnected metal nanoparticles, which act as strongly nonlinear single-electron transistors, and find that this nanoscale architecture can be configured in situ into any Boolean logic gate. This universal, reconfigurable gate would require about ten transistors in a conventional circuit. Our system meets the criteria for the physical realization of (cellular) neural networks: universality (arbitrary Boolean functions), compactness, robustness and evolvability, which implies scalability to perform more advanced tasks. Our evolutionary approach works around device-to-device variations and the accompanying uncertainties in performance. Moreover, it bears a great potential for more energy-efficient computation, and for solving problems that are very hard to tackle in conventional architectures.

  12. DESIGN OF RECONFIGURABLE MANUFACTURING SYSTEMS WITH STRONGLY COUPLED NATURE

    Institute of Scientific and Technical Information of China (English)

    Bl Zhuming; LANG Sherman Y T; WANG Lihui

    2007-01-01

    Today's manufacturing environment forces manufacturing companies to make as many product variations as possible at affordable costs within a short time. Mass customisation is one of most important technologies for companies to achieve their objectives. Efforts to mass customisation should be made on two aspects: ① To modularize products and make them as less differences as possible; ② To design manufacturing resources and make them provide as many processes variations as possible. This paper reports our recent work on aspect ②, i.e. how to design a reconfigurable manufacturing system (RMS) so that it can be competent to accomplish various processes optimally; Reconfigurable robot system (RRS) is taken as an example. RMS design involves architecture design and configuration design, and configuration design is further divided in design analysis and design synthesis. Axiomatic design theory (ADT) is applied to architecture design, the features and issues of RRS configuration design are discussed, automatic modelling method is developed for design analysis, and concurrent design methodology is presented for design synthesis.

  13. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  14. VLSI (Very Large Scale Integration) Design Tools Reference Manual - Release 1.0.

    Science.gov (United States)

    1983-10-01

    34" SUBCXT Sabna N1 < N2 N3 ... > 1_V/NW VLSI Release 1 -18- * SPICE User’s Guide UW/NW VLSI Consortium Examples: .SUBCKT OPAMP 12 3 4 A circuit definition... OPAMP This card must be the last one for any subcircuit definition. The subcircuit name, if included, indicates which subcircuit definition is being

  15. Efficient Runtime Management of Reconfigurable Hardware Resources

    NARCIS (Netherlands)

    Marconi, T.

    2011-01-01

    Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford som

  16. Control Reconfigurability of Bilinear Hydraulic Drive Systems

    DEFF Research Database (Denmark)

    Shaker, Hamid Reza; Tahavori, Maryamsadat

    2011-01-01

    be effective if sufficient redundancy does not exist in the process. A measure for control reconfigurability which reveals the level of redundancy in connection with feedback control is proposed in this paper for bilinear systems. The proposed control reconfigurability measure is the extension of its gramian...

  17. Reconfigurable Radio-Over-Fiber Networks [Invited

    DEFF Research Database (Denmark)

    Vegas Olmos, Juan José; Tafur Monroy, Idelfonso

    2015-01-01

    This paper discusses reconfigurable Radio-over-Fiber networks, including activities in coherent remote access units, silicon photonics for microwave photonics and optical switching.......This paper discusses reconfigurable Radio-over-Fiber networks, including activities in coherent remote access units, silicon photonics for microwave photonics and optical switching....

  18. Multiple-Morphs Adaptive Stream Architecture

    Institute of Scientific and Technical Information of China (English)

    Mei Wen; Nan Wu; Hai-Yan Li; Chun-Yuan Zhang

    2005-01-01

    In modern VLSI technology, hundreds of thousands of arithmetic units fit on a 1cm2 chip. The challenge is supplying them with instructions and data. Stream architecture is able to solve the problem well. However, the applications suited for typical stream architecture are limited. This paper presents the definition of regular stream and irregular stream,and then describes MASA (Multiple-morphs Adaptive Stream Architecture) prototype system which supports different execution models according to applications' stream characteristics. This paper first discusses MASA architecture and stream model, and then explores the features and advantages of MASA through mapping stream applications to hardware.Finally MASA is evaluated by ten benchmarks. The result is encouraging.

  19. Robust Reconfiguration of A Distribution System

    Energy Technology Data Exchange (ETDEWEB)

    Moradzadeh, Benyamin [University of Tennessee, Knoxville (UTK); Tomsovic, Kevin [University of Tennessee, Knoxville (UTK)

    2017-01-01

    In this paper, a robust reconfiguration approach based on Mixed Integer Programming (MIP) is proposed to minimize loss in distribution systems. A Depth-First Search (DFS) algorithm to enumerate possible loops provides radiality constraint. This provides a general solution to the radiality constraint for distribution system reconfiguration/expansion problems. Still, imprecision and ambiguity in net loads, i.e. load minus renewable generation, due to lack of sufficient measurements and high utilization of demand response programs and renewable resources, creates challenges for effective reconfiguration. Deterministic optimization of reconfiguration may no lead to optimal/feasible results. Two methods to address these uncertainties are introduced in this paper: one, based on a stochastic MIP (SMIP) formulation and two, based on a fuzzy MIP (FMIP) formulation. Case studies demonstrate the robustness and efficiency of the proposed reconfiguration methods.

  20. Formation reconfiguration in restricted three body problem

    Institute of Scientific and Technical Information of China (English)

    Shengping Gong; Junfeng Li; Hexi Baoyin; Yunfeng Gao

    2007-01-01

    Reconfiguration of formation flying around a halo orbit of the Sun-Earth restricted three body system is investigated with impulse maneuvers. For a short time reconfiguration, the two-impulse maneuver is investigated with both analytical and numerical methods and the BeginningEnding (BE) method is proven to be an energy-optimal one of all two-impulse (TI) reconfigurations, and the energy consumption of BE is independent of the position of the chief spacecraft, and decreases with the reconfiguration time.Then, genetic algorithm is adopted to optimize the energy consumption. The results show that the optimal energy increases with radius difference between the initial and final orbits, and decreases with the reconfiguration time.

  1. Implementing Workflow Reconfiguration in WS-BPEL

    DEFF Research Database (Denmark)

    Mazzara, Manuel; Dragoni, Nicola; Zhou, Mu

    2012-01-01

    This paper investigates the problem of dynamic reconfiguration by means of a workflow-based case study used for discussion. We state the requirements on a system implementing the workflow and its reconfiguration, and we describe the system’s design in BPMN. WS-BPEL, a language that would not natu......This paper investigates the problem of dynamic reconfiguration by means of a workflow-based case study used for discussion. We state the requirements on a system implementing the workflow and its reconfiguration, and we describe the system’s design in BPMN. WS-BPEL, a language that would...... not naturally support dynamic change, is used as a target for implementation. The WS-BPEL recovery framework is here exploited to implement the reconfiguration using principles derived from previous research in process algebra and two mappings from BPMN to WS-BPEL are presented, one automatic and only mostly...

  2. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  3. Transformational electronics are now reconfiguring

    Science.gov (United States)

    Rojas, Jhonathan P.; Hussain, Aftab M.; Arevalo, A.; Foulds, I. G.; Torres Sevilla, Galo A.; Nassar, Joanna M.; Hussain, Muhammad M.

    2015-05-01

    Current developments on enhancing our smart living experience are leveraging the increased interest for novel systems that can be compatible with foldable, wrinkled, wavy and complex geometries and surfaces, and thus become truly ubiquitous and easy to deploy. Therefore, relying on innovative structural designs we have been able to reconfigure the physical form of various materials, to achieve remarkable mechanical flexibility and stretchability, which provides us with the perfect platform to develop enhanced electronic systems for application in entertainment, healthcare, fitness and wellness, military and manufacturing industry. Based on these novel structural designs we have developed a siliconbased network of hexagonal islands connected through double-spiral springs, forming an ultra-stretchable (~1000%) array for full compliance to highly asymmetric shapes and surfaces, as well as a serpentine design used to show an ultrastretchable (~800%) and flexible, spatially reconfigurable, mobile, metallic thin film copper (Cu)-based, body-integrated and non-invasive thermal heater with wireless controlling capability, reusability, heating-adaptability and affordability due to low-cost complementary metal oxide semiconductor (CMOS)-compatible integration.

  4. Transformational electronics are now reconfiguring

    KAUST Repository

    Rojas, Jhonathan Prieto

    2015-05-22

    Current developments on enhancing our smart living experience are leveraging the increased interest for novel systems that can be compatible with foldable, wrinkled, wavy and complex geometries and surfaces, and thus become truly ubiquitous and easy to deploy. Therefore, relying on innovative structural designs we have been able to reconfigure the physical form of various materials, to achieve remarkable mechanical flexibility and stretchability, which provides us with the perfect platform to develop enhanced electronic systems for application in entertainment, healthcare, fitness and wellness, military and manufacturing industry. Based on these novel structural designs we have developed a siliconbased network of hexagonal islands connected through double-spiral springs, forming an ultra-stretchable (~1000%) array for full compliance to highly asymmetric shapes and surfaces, as well as a serpentine design used to show an ultrastretchable (~800%) and flexible, spatially reconfigurable, mobile, metallic thin film copper (Cu)-based, body-integrated and non-invasive thermal heater with wireless controlling capability, reusability, heating-adaptability and affordability due to low-cost complementary metal oxide semiconductor (CMOS)-compatible integration. © (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

  5. Multi-core Architectures and Streaming Applications

    NARCIS (Netherlands)

    Smit, Gerard J.M.; Kokkeler, André B.J.; Wolkotte, Pascal T.; Burgwal, van de Marcel D.; Mandoiu, I.; Kennings, A.

    2008-01-01

    In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digital signal processing (DSP) applications. The multi-core concept has a number of advantages: (1) depending on the requirements more or fewer cores can be switched on/off, (2) the multi-core structure f

  6. Dynamically Reconfigurable Processor for Floating Point Arithmetic

    Directory of Open Access Journals (Sweden)

    S. Anbumani,

    2014-01-01

    Full Text Available Recently, development of embedded processors is toward miniaturization and energy saving for ecology. On the other hand, high performance arithmetic circuits are required in a lot of application in science and technology. Dynamically reconfigurable processors have been developed to meet these requests. They can change circuit configuration according to instructions in program instantly during operations.This paper describes, a dynamically reconfigurable circuit for floating-point arithmetic is proposed. The arithmetic circuit consists of two single precision floating-point arithmetic circuits. It performs double precision floating-point arithmetic by reconfiguration. Dynamic reconfiguration changes circuit construction at one clock cycle during operation without stopping circuits. It enables reconfiguration of circuits in a few nano seconds. The proposed circuit is reconfigured in two modes. In first mode it performs one double precision floating-point arithmetic or else the circuit will perform two parallel operations of single precision floating-point arithmetic. The new system design reduces implementation area by reconfiguring common parts of each operation. It also increases the processing speed with a very little number of clocks.

  7. Implementation of Karp-Rabin string matching algorithm in reconfigurable hardware for network intrusion prevention system

    Science.gov (United States)

    Botwicz, Jakub; Buciak, Piotr; Sapiecha, Piotr

    2006-03-01

    Intrusion Prevention Systems (IPSs) have become widely recognized as a powerful tool and an important element of IT security safeguards. The essential feature of network IPSs is searching through network packets and matching multiple strings, that are fingerprints of known attacks. String matching is highly resource consuming and also the most significant bottleneck of IPSs. In this article an extension of the classical Karp-Rabin algorithm and its implementation architectures were examined. The result is a software, which generates a source code of a string matching module in hardware description language, that could be easily used to create an Intrusion Prevention System implemented in reconfigurable hardware. The prepared module matches the complete set of Snort IPS signatures achieving throughput of over 2 Gbps on an Altera Stratix I1 evaluation board. The most significant advantage of the proposed architecture is that the update of the patterns database does not require reconfiguration of the circuitry.

  8. The Chameleon Architecture for Streaming DSP Applications

    Directory of Open Access Journals (Sweden)

    André B. J. Kokkeler

    2007-02-01

    Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

  9. The Chameleon Architecture for Streaming DSP Applications

    Directory of Open Access Journals (Sweden)

    Heysters PaulM

    2007-01-01

    Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

  10. Low complexity VLSI implementation of CORDIC-based exponent calculation for neural networks

    Science.gov (United States)

    Aggarwal, Supriya; Khare, Kavita

    2012-11-01

    This article presents a low hardware complexity for exponent calculations based on CORDIC. The proposed CORDIC algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional CORDIC in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 × N ROM in the pre-processing unit for storing the initial coordinate values; it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed CORDIC processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx CORDIC Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

  11. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Science.gov (United States)

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  12. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Science.gov (United States)

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  13. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  14. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  15. Imaging with polycrystalline mercuric iodide detectors using VLSI readout

    Energy Technology Data Exchange (ETDEWEB)

    Turchetta, R.; Dulinski, W.; Husson, D.; Riester, J.L.; Schieber, M.; Zuck, A.; Melekhov, L.; Saado, Y.; Hermon, H.; Nissenbaum, J

    1999-06-01

    Potentially low cost and large area polycrystalline mercuric iodide room-temperature radiation detectors, with thickness of 100-600 {mu}m have been successfully tested with dedicated low-noise, low-power mixed signal VLSI electronics which can be used for compact, imaging solutions. The detectors are fabricated by depositing HgI{sub 2} directly on an insulating substrate having electrodes in the form of microstrips and pixels with an upper continuous electrode. The deposition is made either by direct evaporation or by screen printing HgI{sub 2} mixed with glue such as Poly-Vinyl-Butiral. The properties of these first-generation detectors are quite uniform from one detector to another. Also for each single detector the response is quite uniform and no charge loss in the inter-electrode space have been detected. Because of the low cost and of the polycrystallinity, detectors can be potentially fabricated in any size and shape, using standard ceramic technology equipment, which is an attractive feature where low cost and large area applications are needed. The detectors which act as radiation counters have been tested with a beta source as well as in a high-energy beam of 100 GeV muons at CERN, connected to VLSI, low noise electronics. Charge collection efficiency and uniformity have been studied. The charge is efficiently collected even in the space between strips indicating that fill factors of 100% could be reached in imaging applications with direct detection of radiation. Single photon counting capability is reached with VLSI electronics. These results show the potential of this material for applications demanding position sensitive, radiation resistant, room-temperature operating radiation detectors, where position resolution is essential, as it can be found in some applications in high-energy physics, nuclear medicine and astrophysics.

  16. Reconfigurable subsampling receiver architecture for wireless body area networks

    NARCIS (Netherlands)

    Zhao, D.; Serdijn, W.A.; Huang, L.; Dolmans, G.

    2011-01-01

    The wide range of wireless body area network (WBAN) applications gives rise to different system requirements for the carrier frequencies and data rates. In order to accommodate various standards in WBAN applications, a universal receiver system with good performance and low power is highly desirable

  17. A reconfigurable radio architecture for Cognitive Radio in emergency networks

    NARCIS (Netherlands)

    Zhang, Q.; Kokkeler, Andre B.J.; Smit, Gerardus Johannes Maria

    2006-01-01

    Cognitive Radio has been proposed as a promising technology to solve today’s spectrum scarcity problem. Cognitive Radio is able to sense the spectrum to find the free spectrum, which can be optimally used by Cognitive Radio without causing interference to the licensed user. In the scope of the

  18. Towards system level runtime design space exploration of reconfigurable architectures

    NARCIS (Netherlands)

    Sigdel, K.; Thompson, M.; Pimentel, A.D.; Bertels, K.

    2008-01-01

    The ever increasing intricacy of the systems and the increasing use of reconfigurble heterogeneous devices significantly enlarges the design complexity of the modern embedded systems. As a result, to create a good design, it is essential to perform Design Space Exploration( DSE) at various design

  19. Reconfigurable subsampling receiver architecture for wireless body area networks

    NARCIS (Netherlands)

    Zhao, D.; Serdijn, W.A.; Huang, L.; Dolmans, G.

    2011-01-01

    The wide range of wireless body area network (WBAN) applications gives rise to different system requirements for the carrier frequencies and data rates. In order to accommodate various standards in WBAN applications, a universal receiver system with good performance and low power is highly

  20. A reconfigurable radio architecture for Cognitive Radio in emergency networks

    NARCIS (Netherlands)

    Zhang, Q.; Kokkeler, Andre B.J.; Smit, Gerardus Johannes Maria

    2006-01-01

    Cognitive Radio has been proposed as a promising technology to solve today’s spectrum scarcity problem. Cognitive Radio is able to sense the spectrum to find the free spectrum, which can be optimally used by Cognitive Radio without causing interference to the licensed user. In the scope of the Adapt

  1. Scheduling Temporal Partitions in a Multiprocessing Paradigm for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    2009-01-01

    I rapporten er udviklet metoder og redskaber, som den kommunale planlægning kan benytte i håndteringen af demografi ske og kommunaløkonomiske udfordringer i fremtiden. Rapporten belyser, ved hjælp af spørgeskemaundersøgelse og fokusgruppeinterviews, tilflytterne til nybyggeri i Køge Kommune samt ...

  2. Reconfigurable middleware architectures for large scale sensor networks

    Energy Technology Data Exchange (ETDEWEB)

    Brennan, Sean M.

    2010-03-01

    Wireless sensor networks, in an e ffort to be energy efficient, typically lack the high-level abstractions of advanced programming languages. Though strong, the dichotomy between these two paradigms can be overcome. The SENSIX software framework, described in this dissertation, uniquely integrates constraint-dominated wireless sensor networks with the flexibility of object-oriented programming models, without violating the principles of either. Though these two computing paradigms are contradictory in many ways, SENSIX bridges them to yield a dynamic middleware abstraction unifying low-level resource-aware task recon figuration and high-level object recomposition.

  3. A Reconfigurable Radio Architecture for Cognitive Radio in Emergency Networks

    NARCIS (Netherlands)

    Zhang, Qiwei; Kokkeler, Andre B.J.; Smit, Gerard J.M.

    2006-01-01

    Cognitive Radio has been proposed as a promising technology to solve today's spectrum scarcity problem. Cognitive Radio is able to sense the spectrum to find the free spectrum, which can be optimally used by Cognitive Radio without causing interference to the licensed user. In the scope of the Adapt

  4. (Re)configuration based on model generation

    CERN Document Server

    Friedrich, Gerhard; Falkner, Andreas A; Haselböck, Alois; Schenner, Gottfried; Schreiner, Herwig; 10.4204/EPTCS.65.3

    2011-01-01

    Reconfiguration is an important activity for companies selling configurable products or services which have a long life time. However, identification of a set of required changes in a legacy configuration is a hard problem, since even small changes in the requirements might imply significant modifications. In this paper we show a solution based on answer set programming, which is a logic-based knowledge representation formalism well suited for a compact description of (re)configuration problems. Its applicability is demonstrated on simple abstractions of several real-world scenarios. The evaluation of our solution on a set of benchmark instances derived from commercial (re)configuration problems shows its practical applicability.

  5. Design of reconfigurable antennas using graph models

    CERN Document Server

    Costantine, Joseph; Christodoulou, Christos G; Christodoulou, Christos G

    2013-01-01

    This lecture discusses the use of graph models to represent reconfigurable antennas. The rise of antennas that adapt to their environment and change their operation based on the user's request hasn't been met with clear design guidelines. There is a need to propose some rules for the optimization of any reconfigurable antenna design and performance. Since reconfigurable antennas are seen as a collection of self-organizing parts, graph models can be introduced to relate each possible topology to a corresponding electromagnetic performance in terms of achieving a characteristic frequency of oper

  6. VLSI implementations of threshold logic-a comprehensive survey.

    Science.gov (United States)

    Beiu, V; Quintana, J M; Avedillo, M J

    2003-01-01

    This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

  7. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  8. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  9. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  10. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...... that can provide a resource allocation policy and enforcement of this policy. It can be used in networks in order to provide defined allocation policies (fairness) and improve network robustness. The presented design illustrates how the theoretical weighted fair queueing model can be approximated...

  11. An adaptive, lossless data compression algorithm and VLSI implementations

    Science.gov (United States)

    Venbrux, Jack; Zweigle, Greg; Gambles, Jody; Wiseman, Don; Miller, Warner H.; Yeh, Pen-Shu

    1993-01-01

    This paper first provides an overview of an adaptive, lossless, data compression algorithm originally devised by Rice in the early '70s. It then reports the development of a VLSI encoder/decoder chip set developed which implements this algorithm. A recent effort in making a space qualified version of the encoder is described along with several enhancements to the algorithm. The performance of the enhanced algorithm is compared with those from other currently available lossless compression techniques on multiple sets of test data. The results favor our implemented technique in many applications.

  12. A VLSI Algorithm for Calculating the Treee to Tree Distance

    Institute of Scientific and Technical Information of China (English)

    徐美瑞; 刘小林

    1993-01-01

    Given two ordered,labeled trees βand α,to find the distance from tree β to tree α is an important problem in many fields,for example,the pattern recognition field.In this paper,a VLSI algorithm for calculating the tree-to-tree distance is presented.The computation structure of the algorithm is a 2-D Mesh with the size m&n.and the time is O(m=n),where m,n are the numbers of nodes of the tree βand tree α,respectively.

  13. Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, B

    1999-07-01

    This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

  14. Value Assessment of Distribution Network Reconfiguration: A Danish Case Study

    DEFF Research Database (Denmark)

    Vaskantiras, Georgios; You, Shi

    2016-01-01

    Distribution network reconfiguration is a mechanism that can improve the distribution system performance from multiple perspectives. In the context of smart grid wherein the degrees of automation and intelligence are high, the potential value of network reconfiguration can be significant...... that although the reconfiguration is performed to achieve a single objective, the overall network performance is improved. In addition, the value achieved by reconfiguration can be very sensitive to the reconfiguration frequency and the associated cost....

  15. Researches on Reconfigurable Antenna in CEMLAB at UESTC

    Institute of Scientific and Technical Information of China (English)

    WANG Bing-zhong; XIAO Shao-qiu; ZHANG Yong; YANG Xue-song; WU Wei-xia

    2006-01-01

    This paper summarizes the achievement and progress in the research on reconfigurable antenna since 2001, in Computational Electromagnetics Laboratory (CEMLAB) at University of Electronic Science and Technology of China (UESTC). Several typical reconfigurable antennas are introduced, which can realize frequency, pattern or frequency-pattern reconfigurability by electrically controlling methods. Some techniques involved in the design and analysis of reconfigurable antennas are reported. At last, the development trend of reconfigurable antenna is predicted in the conclusions.

  16. Reconfigurable Mixed Mode Universal Filter

    Directory of Open Access Journals (Sweden)

    Neelofer Afzal

    2014-01-01

    Full Text Available This paper presents a novel mixed mode universal filter configuration capable of working in voltage and transimpedance mode. The proposed single filter configuration can be reconfigured digitally to realize all the five second order filter functions (types at single output port. Other salient features of proposed configuration include independently programmable filter parameters, full cascadability, and low sensitivity figure. However, all these features are provided at the cost of quite large number of active elements. It needs three digitally programmable current feedback amplifiers and three digitally programmable current conveyors. Use of six active elements is justified by introducing three additional reduced hardware mixed mode universal filter configurations and its comparison with reported filters.

  17. Reconfigurable optical assembly of nanostructures

    Science.gov (United States)

    Montelongo, Yunuen; Yetisen, Ali K.; Butt, Haider; Yun, Seok-Hyun

    2016-06-01

    Arrangements of nanostructures in well-defined patterns are the basis of photonic crystals, metamaterials and holograms. Furthermore, rewritable optical materials can be achieved by dynamically manipulating nanoassemblies. Here we demonstrate a mechanism to configure plasmonic nanoparticles (NPs) in polymer media using nanosecond laser pulses. The mechanism relies on optical forces produced by the interference of laser beams, which allow NPs to migrate to lower-energy configurations. The resulting NP arrangements are stable without any external energy source, but erasable and rewritable by additional recording pulses. We demonstrate reconfigurable optical elements including multilayer Bragg diffraction gratings, volumetric photonic crystals and lenses, as well as dynamic holograms of three-dimensional virtual objects. We aim to expand the applications of optical forces, which have been mostly restricted to optical tweezers. Holographic assemblies of nanoparticles will allow a new generation of programmable composites for tunable metamaterials, data storage devices, sensors and displays.

  18. Radiation effects in reconfigurable FPGAs

    Science.gov (United States)

    Quinn, Heather

    2017-04-01

    Field-programmable gate arrays (FPGAs) are co-processing hardware used in image and signal processing. FPGA are programmed with custom implementations of an algorithm. These algorithms are highly parallel hardware designs that are faster than software implementations. This flexibility and speed has made FPGAs attractive for many space programs that need in situ, high-speed signal processing for data categorization and data compression. Most commercial FPGAs are affected by the space radiation environment, though. Problems with TID has restricted the use of flash-based FPGAs. Static random access memory based FPGAs must be mitigated to suppress errors from single-event upsets. This paper provides a review of radiation effects issues in reconfigurable FPGAs and discusses methods for mitigating these problems. With careful design it is possible to use these components effectively and resiliently.

  19. DSP algorithms in FPGA: proposition of a new architecture

    Science.gov (United States)

    Kolasinski, Piotr; Zabolotny, Wojciech

    2008-01-01

    This paper presents a new reconfigurable architecture created in FPGA which is optimized for DSP algorithms like digital filters or digital transforms. The architecture tries to combine advantages of typical architectures like DSP processors and datapath architecture, while avoiding their drawbacks. The architecture is built from blocks called Operational Units (OU). Each Operational Unit contains the Control Unit (CU), which controls its operation. The Operational Units may operate in parallel, which shortens the processing time. This structure is also highly flexible, because all OUs may operate independently, executing their own programs. User may customize connections between units and modify architecture by adding new modules.

  20. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)

    OpenAIRE

    1996-01-01

    Higher performance is gained through a new architecture which implements a new method of computational resource allocation, utilization and programming based on the concept of Worm-hole Run-Time Reconfiguration (RTR). A stream-driven Worm-hole RTR methodology extends contemporary data-flow paradigms to utilize the dynamic creation of operators and pathways, based upon stream processing in which parcels of data move through custom created pathways and interact with other parcels to achieve the...

  1. Research on Multi-Agent Based Framework of Reconfigurable Shop Floor Control System

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    Manufacturing systems are in a dynamically changing e nvironment with uncertainty. Management of complexity, changes and disturbances is one of the key issues of production. The traditional hierarchical control of CIM systems limits the agility and the flexibility of the shop floor control sys tems and makes the reconfiguration and maintenance of shop floor control systems need high cost and much time. So new architectures are required to meet these c hallenges for the shop floor control systems. Rec...

  2. Architecture on Architecture

    DEFF Research Database (Denmark)

    Olesen, Karen

    2016-01-01

    This paper will discuss the challenges faced by architectural education today. It takes as its starting point the double commitment of any school of architecture: on the one hand the task of preserving the particular knowledge that belongs to the discipline of architecture, and on the other hand...... that is not scientific or academic but is more like a latent body of data that we find embedded in existing works of architecture. This information, it is argued, is not limited by the historical context of the work. It can be thought of as a virtual capacity – a reservoir of spatial configurations that can...... the autonomy of architecture, not as an esoteric concept but as a valid source of information in a pragmatic design practice, may help us overcome the often-proclaimed dichotomy between formal autonomy and a societally committed architecture. It follows that in architectural education there can be a close...

  3. Radiation tolerant back biased CMOS VLSI

    Science.gov (United States)

    Maki, Gary K. (Inventor); Gambles, Jody W. (Inventor); Hass, Kenneth J. (Inventor)

    2003-01-01

    A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

  4. China's Reconfigurable Planet Probing Robot

    Institute of Scientific and Technical Information of China (English)

    RenShufang

    2005-01-01

    Research of reconfigurable planet probing robot conducted by the Shenyang Institute of Automation of the Chinese Academy of Science (SIA-CAS) has passed appraisal of 863 Program sresearch on intelligent robots.

  5. Control Reconfigurability of Bilinear Hydraulic Drive Systems

    DEFF Research Database (Denmark)

    Shaker, Hamid Reza; Tahavori, Maryamsadat

    2011-01-01

    be effective if sufficient redundancy does not exist in the process. A measure for control reconfigurability which reveals the level of redundancy in connection with feedback control is proposed in this paper for bilinear systems. The proposed control reconfigurability measure is the extension of its gramian......The objective of the methods within the framework of the plug and play process control and particularly fault tolerant control is to establish control techniques which guarantee a certain performance through control reconfiguration at the occurrence of the faults or changes. These methods cannot......-based analogous counterpart, which has been previously proposed for the linear processes. The control reconfigurability is calculated for the bilinear models of an electro-hydraulic drive to show its relevance to redundant actuating capabilities in the models....

  6. Performance Monitoring in Transparent Reconfigurable WDM Networks

    Institute of Scientific and Technical Information of China (English)

    Chun-Kit.Chan; Frank; Tong

    2003-01-01

    This paper classifies and surveys different approaches proposed for performance monitoring, in particular the optical signal-to-noise ratio (OSNR) monitoring, in transparent reconfigurable WDM networks. Some considerations for future monitoring schemes are discussed.

  7. Reconfigurable/Reprogrammable Communication Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The future of reconfigurable/reprogrammable transceivers with !Y 1 Gbps transmission and reception data rates for future NASA space communications applications will...

  8. Roles and Self-Reconfigurable Robots

    DEFF Research Database (Denmark)

    Dvinge, Nicolai; Schultz, Ulrik Pagh; Christensen, David Johan

    2007-01-01

    A self-reconfigurable robot is a robotic device that can change its own shape. Self-reconfigurable robots are commonly built from multiple identical modules that can manipulate each other to change the shape of the robot. The robot can also perform tasks such as locomotion without changing shape....... Programming a modular, self-reconfigurable robot is however a complicated task: the robot is essentially a real-time, distributed embedded system, where control and communication paths often are tightly coupled to the current physical configuration of the robot. To facilitate the task of programming modular......, self-reconfigurable robots, we have developed a declarative, role-based language that allows the programmer to associate roles and behavior to structural elements in a modular robot. Based on the role declarations, a dedicated middleware for high-level distributed communication is generated...

  9. Elements of Autonomous Self-Reconfigurable Robots

    DEFF Research Database (Denmark)

    Christensen, David Johan

    In this thesis, we study several central elements of autonomous self-reconfigurable modular robots. Unlike conventional robots such robots are: i) Modular, since robots are assembled from numerous robotic modules. ii) Reconfigurable, since the modules can be combined in a variety of ways. iii) Self......-reconfigurable, since the modules themselves are able to change how they are combined. iv) Autonomous, since robots control themselves without human guidance. Such robots are attractive to study since they in theory have several desirable characteristics, such as versatility, reliability and cheapness. In practice...... robots: design, scalability, self-reconfiguration and adaptation. The first element we consider is the design of systems, modules, robots, and behaviors. We introduce a number of design principles that will guide our designs throughout the thesis. The design principles advocate simple, extendable...

  10. MEMS-Enabled Smart Reconfigurable Antennas Project

    Data.gov (United States)

    National Aeronautics and Space Administration — A prototype wearable smart reconfigurable antenna for the Suit will be built to be used during NASA's EVA operations on lunar surface. The design is based on the...

  11. Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI.

    Science.gov (United States)

    Cameron, Katherine; Boonsobhak, Vasin; Murray, Alan; Renshaw, David

    2005-11-01

    A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithm's performance. Results from 0.35 microm CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithm's natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

  12. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  13. Flexible optofluidic waveguide platform with multi-dimensional reconfigurability

    Science.gov (United States)

    Parks, Joshua W.; Schmidt, Holger

    2016-09-01

    Dynamic reconfiguration of photonic function is one of the hallmarks of optofluidics. A number of approaches have been taken to implement optical tunability in microfluidic devices. However, a device architecture that allows for simultaneous high-performance microfluidic fluid handling as well as dynamic optical tuning has not been demonstrated. Here, we introduce such a platform based on a combination of solid- and liquid-core polydimethylsiloxane (PDMS) waveguides that also provides fully functioning microvalve-based sample handling. A combination of these waveguides forms a liquid-core multimode interference waveguide that allows for multi-modal tuning of waveguide properties through core liquids and pressure/deformation. We also introduce a novel lifting-gate lightvalve that simultaneously acts as a fluidic microvalve and optical waveguide, enabling mechanically reconfigurable light and fluid paths and seamless incorporation of controlled particle analysis. These new functionalities are demonstrated by an optical switch with >45 dB extinction ratio and an actuatable particle trap for analysis of biological micro- and nanoparticles.

  14. Flexible optofluidic waveguide platform with multi-dimensional reconfigurability

    Science.gov (United States)

    Parks, Joshua W.; Schmidt, Holger

    2016-01-01

    Dynamic reconfiguration of photonic function is one of the hallmarks of optofluidics. A number of approaches have been taken to implement optical tunability in microfluidic devices. However, a device architecture that allows for simultaneous high-performance microfluidic fluid handling as well as dynamic optical tuning has not been demonstrated. Here, we introduce such a platform based on a combination of solid- and liquid-core polydimethylsiloxane (PDMS) waveguides that also provides fully functioning microvalve-based sample handling. A combination of these waveguides forms a liquid-core multimode interference waveguide that allows for multi-modal tuning of waveguide properties through core liquids and pressure/deformation. We also introduce a novel lifting-gate lightvalve that simultaneously acts as a fluidic microvalve and optical waveguide, enabling mechanically reconfigurable light and fluid paths and seamless incorporation of controlled particle analysis. These new functionalities are demonstrated by an optical switch with >45 dB extinction ratio and an actuatable particle trap for analysis of biological micro- and nanoparticles. PMID:27597164

  15. Reconfigurable SRTM System for Road Traffic in Kingdom of Bahrain

    Directory of Open Access Journals (Sweden)

    El-Medany Wael

    2016-12-01

    Full Text Available This paper presents reconfigurable hardware architecture for smart road traffic system based on Field Programmable Gate Array (FPGA. The design can be reconfigured for different timing of the traffic signals according to the received and collected data read by the different sensors on the road; the design has been described using VHDL (VHSIC Hardware Description Language. The SRTM (Smart Road Traffic Management System has some more features that help passenger to avoid traffic jamming by sending the collected information through web/mobile applications to find the best road between the start and destination points, which will be displayed on Google maps, at the same time it will also shows the points of traffic jamming on Google maps. SRTM system can also manage emergency vehicles such as ambulance and fire fighter and also can send snapshots and video streaming for different roads and junctions to show the points of traffic jamming. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level.

  16. Integrating Reconfigurable Hardware-Based Grid for High Performance Computing

    Directory of Open Access Journals (Sweden)

    Julio Dondo Gazzano

    2015-01-01

    Full Text Available FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC. The impressive speed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process with fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some difficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study to identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms, and the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high performance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application deployment is described. An example application and a comparison with other hardware and software implementations are shown. Experimental results show that the proposed architecture offers encouraging advantages for deployment of high performance distributed applications simplifying development process.

  17. Reconfigurable exciton-plasmon interconversion for nanophotonic circuits

    Science.gov (United States)

    Lee, Hyun Seok; Luong, Dinh Hoa; Kim, Min Su; Jin, Youngjo; Kim, Hyun; Yun, Seokjoon; Lee, Young Hee

    2016-11-01

    The recent challenges for improving the operation speed of nanoelectronics have motivated research on manipulating light in on-chip integrated circuits. Hybrid plasmonic waveguides with low-dimensional semiconductors, including quantum dots and quantum wells, are a promising platform for realizing sub-diffraction limited optical components. Meanwhile, two-dimensional transition metal dichalcogenides (TMDs) have received broad interest in optoelectronics owing to tightly bound excitons at room temperature, strong light-matter and exciton-plasmon interactions, available top-down wafer-scale integration, and band-gap tunability. Here, we demonstrate principal functionalities for on-chip optical communications via reconfigurable exciton-plasmon interconversions in ~200-nm-diameter Ag-nanowires overlapping onto TMD transistors. By varying device configurations for each operation purpose, three active components for optical communications are realized: field-effect exciton transistors with a channel length of ~32 μm, field-effect exciton multiplexers transmitting multiple signals through a single NW and electrical detectors of propagating plasmons with a high On/Off ratio of~190. Our results illustrate the unique merits of two-dimensional semiconductors for constructing reconfigurable device architectures in integrated nanophotonic circuits.

  18. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  19. Universal Reconfiguration of (Hyper-)cubic Robots

    OpenAIRE

    Abel, Zachary; Kominers, Scott D.

    2008-01-01

    We study a simple reconfigurable robot model which has not been previously examined: cubic robots comprised of three-dimensional cubic modules which can slide across each other and rotate about each others' edges. We demonstrate that the cubic robot model is universal, i.e., that an n-module cubic robot can reconfigure itself into any specified n-module configuration. Additionally, we provide an algorithm that efficiently plans and executes cubic robot motion. Our results directly extend to a...

  20. RF MEMS reconfigurable triangular patch antenna.

    Energy Technology Data Exchange (ETDEWEB)

    Christodoulou, Christos George (The University of New Mexico, Albuquerque, NM); Nordquist, Christopher Daniel; Feldner, Lucas Matthew

    2005-07-01

    A Ka-band RF MEMS enabled frequency reconfigurable triangular microstrip patch antenna has been designed for monolithic integration with RF MEMS phase shifters to demonstrate a low-cost monolithic passive electronically scanned array (PESA). This paper introduces our first prototype reconfigurable triangular patch antenna currently in fabrication. The aperture coupled patch antenna is fabricated on a dual-layer quartz/alumina substrate using surface micromachining techniques.

  1. A Reconfigurable Radiation Pattern Annular Slot Antenna

    OpenAIRE

    Aziz, NA; Radhi, A; Nilavalan, R

    2016-01-01

    This paper contemplate a theoretical analysis of a pattern reconfigurable antenna using annular slot antenna operating in low frequency. A shorting pin is inserted to allow the annular slot antenna to have an omnidirectional radiation pattern like a monopole antenna. The reconfigurable antenna consists of numerous metal cylinders arranged around the annular slot antenna. By controlling pin diodes associated with the metal cylinders, the antenna is capable of working up in different dire...

  2. RF MEMS reconfigurable triangular patch antenna.

    Energy Technology Data Exchange (ETDEWEB)

    Nordquist, Christopher Daniel; Christodoulou, Christos George (University of New Mexico, Albuquerque, NM); Feldner, Lucas Matthew

    2005-01-01

    A Ka-band RF MEMS enabled frequency reconfigurable triangular microstrip patch antenna has been designed for monolithic integration with RF MEMS phase shifters to demonstrate a low-cost monolithic passive electronically scanned array (PESA). This paper introduces our first prototype reconfigurable triangular patch antenna currently in fabrication. The aperture coupled patch antenna is fabricated on a dual-layer quartz/alumina substrate using surface micromachining techniques.

  3. Testing interconnected VLSI circuits in the Big Viterbi Decoder

    Science.gov (United States)

    Onyszchuk, I. M.

    1991-01-01

    The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

  4. New VLSI complexity results for threshold gate comparison

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1996-12-31

    The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers another particular solution, and spans from constant to logarithmic depths. These circuit complexity results are supplemented by fresh VLSI complexity results having applications to hardware implementations of neural networks and to VLSI-friendly learning algorithms. In order to estimate the area (A) and the delay (T), as well as the classical AT{sup 2}, we shall use the following {open_quote}cost functions{close_quote}: (i) the connectivity (i.e., sum of fan-ins) and the number-of-bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations allow us to compare the different solutions-which present very interesting fan-in dependent depth-size and area-delay tradeoffs - with respect to AT{sup 2}.

  5. A fast neural-network algorithm for VLSI cell placement.

    Science.gov (United States)

    Aykanat, Cevdet; Bultan, Tevfik; Haritaoğlu, Ismail

    1998-12-01

    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.

  6. Power Characterisation for Fine-Grain Reconfigurable Fabrics

    Directory of Open Access Journals (Sweden)

    Tobias Becker

    2010-01-01

    Full Text Available This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.

  7. Reconfigurable networking for coordinated multi-agent sensing and communications.

    Science.gov (United States)

    Sutton, Jeffrey P; Jamieson, Ian M D

    2002-12-01

    An implementation of a neurally-inspired system comprised of multiple mobile sensor-effector agents is described. Each agent has features of a complex neural network that is able to communicate and adjust its behavior depending upon a variety of parameters, including changes in the environment and the behavior of other agents. The system as a whole spatiotemporally reconfigures itself to perform coordinated behaviors not obtainable with single agents. Transient clustering of agents into functional subsystems to perform specific tasks generates a "system of systems" architecture. The interesting findings of this dynamic platform show that (a) the formation and dissolution of functional subsystems is a local phenomenon without the need for global control and (b) minimal intermittent communication among the agents can yield large-scale, coordinated, goal-driven behavior under a wide range of conditions.

  8. SAR++: A Multi-Channel Scalable and Reconfigurable SAR System

    DEFF Research Database (Denmark)

    Høeg, Flemming; Christensen, Erik Lintz

    2002-01-01

    SAR++ is a technology program aiming at developing know-how and technology needed to design the next generation civilian SAR systems. Technology has reached a state, which allows major parts of the digital subsystem to be built using custom-off-the-shelf (COTS) components. A design goal is to des......SAR++ is a technology program aiming at developing know-how and technology needed to design the next generation civilian SAR systems. Technology has reached a state, which allows major parts of the digital subsystem to be built using custom-off-the-shelf (COTS) components. A design goal...... is to design a modular, scalable and reconfigurable SAR system using such components, in order to ensure maximum flexibility for the users of the actual system and for future system updates. Having these aspects in mind the SAR++ system is presented with focus on the digital subsystem architecture...... and the analog to digital interface....

  9. Reconfigurable time-steered array-antenna beam former.

    Science.gov (United States)

    Frankel, M Y; Esman, R D

    1997-12-10

    We present and analyze a hardware-optimized technique that provides true-time-delay steering for broadband two-dimensional array-antenna applications. The technique improves on previous approaches by the reduction of the two-dimensional beam-former architecture complexity, by the provision of flexibility in time-delay unit selection, and by the potential reduction of optical loss. The technique relies on a one-dimensional bank of time-delay units to form the required time-delay gradient for proper off-broadside angle steering. A reconfigurable optical interconnection fabric is used to reassign dynamically the connections between the time-delay units and individual array elements of a two-dimensional array to effect the proper steering angle along the off-broadside cone.

  10. A Modular Re-configurable Rover System

    Science.gov (United States)

    Bouloubasis, A.; McKee, G.; Active Robotics Lab

    design allows the MTR to lift, lower, roll or tilt its body. It also provides the ability to lift any of the legs by nearly 300mm, enhancing internal re-configurability and therefore rough terrain stability off the robotic vehicle. A modular software and control architecture will be used so that integration to, and operation through the MTR, of different Packs can be demonstrated. An on-board high-level controller [4] will communicate with a small network of micro-controllers through an RS485 bus. Additional processing power could be obtained through a Pack with equivalent or higher computational capabilities. 1 The nature of the system offers many opportunities for behavior based control. The control system must accommodate not only rover based behaviors like obstacle avoidance and vehicle stabilization, but also any additional behaviors that different Packs may introduce. The Ego-Behavior Architecture (EBA) [5] comprises a number of behaviors which operate autonomously and independent of each other. This facilitates the design and suits the operation of the MTR since it fulfills the need for uncomplicated assimilation of new behaviors in the existing architecture. Our work at the moment focuses on the design and construction of the mechanical and electronic systems for the MTR and an associated Pack. References [1] NASA, Human Exploration of Mars: The Reference Mission (Version 3.0 with June, 1998 Addendum) of the NASA Mars Exploration Study Team, Exploration Office, Advanced Development Office, Lyndon B. Johnson Space Center, Houston, TX 77058, June, 1998. [2] A. Trebi-Ollennu, H Das Nayer, H Aghazarian, A ganino, P Pirjanian, B Kennedy, T Huntsberger and P Schenker, Mars Rover Pair Cooperatively Transporting a Long Payload, in Proceedings of the 2002 IEEE International Conference on Robotics and Automation, May 2002, pp. 3136-3141. [3] A. K. Bouloubasis, G. T McKee, P. S. Schenker, A Behavior-Based Manipulator for Multi-Robot Transport Tasks, in proceedings of the

  11. Turbo decoder architecture for beyond-4G applications

    CERN Document Server

    Wong, Cheng-Chi

    2013-01-01

    This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respec

  12. A VLSI Architecture Evaluation of a Syntax Element Level Parallel Arithmetic Entropy Coder for Parallel H.264 Encoder%一种用于并行H.264编码器的语法元素级分组并行算术编码器体系结构的评估

    Institute of Scientific and Technical Information of China (English)

    陈胜刚; 陈书明; 谷会涛; 刘尧

    2012-01-01

    设计了一种语法元素指令流驱动的全流水CABAC(Context-based Adaptive Binary Arithmetic Coding)熵编码VLSI结构,并对提出的语法元素级分组并行算术编码器的体系结构进行了设计和开销评估.该并行方法可以与现有符号级并行算法正交,可同时使用,适合大规模片上并行视频编码器;相比标准CABAC,增加约55%的晶体管即可实现2倍以上的符号处理加速比和>1Gbin/s的吞吐率.%This paper proposes a new CABAC pipeline driving by syntax element instructions and a GABAC-based parallel arithmetic entropy coder for on-chip large-scale parallel H.264 video coders is also presented in this paper. Furthermore, the hardware architecture and transistor cost of the new parallel entropy coder are evaluated. This new parallel entropy coder can cooperate with the traditional symbol-level parallel algorithms and it suits the manycore platform well.Compared with the traditional CABAC hardware,the new parallel entropy coder can double its throughput to > 1Gbins/s by a cost of 55% transistors.

  13. Configuration representation and reconfiguration optimization for the reconfigurable robots with independent manipulation

    Institute of Scientific and Technical Information of China (English)

    WANG MingHui; MA ShuGen; LI Bin; WANG YueChao

    2009-01-01

    Single module of the reconfigurable robots with independent manipulation can perform the actions of locomotion and manipulation. In conformity with the request for achieving autonomous operation in the unstructurized environment Instead of fixed operation in the structurized environment, these robots are applied in the complicated and dangerous environment. The existing researches on the configura-tion theory focus on the reconfigurable robots with limited locomotion and the ones with independent locomotion, not being applicable to the reconfigurable robots with independent manipulation. The vec-tor configuration is put forward, the research content of which contains the topology and locomotion direction of configuration, the posture and orientation and connection relation between modules. Mod-ule state vector and configuration state matrix are proposed for representation methodology for the swarm configuration of these reconfigurable robots, which supports transformation operation to repre-sent and trigger behavior motion of the module and reconfiguration between configurations. Optimiza-tion algorithm of assembly reconfiguration applying workload as the optimization target is presented, as well as optimization algorithm of transformation reconfiguration applying the Integration of pos-ture_orientation_workload and connection_workload. The result of optimization is the relation of state transformation between the initial configuration and the object one as the basic of reconfiguration plan and control.

  14. Reconfigurable mobile radio systems a snapshot of key aspects related to reconfigurability in wireless systems

    CERN Document Server

    Vivier, Guillaume

    2010-01-01

    Different aspects of the reconfigurability of mobile radio systems are analyzed in this book. These include services, object modeling applied to software radio, flexible spectrum management, trade-offs for building a reconfigurable terminal, an example of a pure software radio modem, adaptive MIMO techniques and analog-to-digital converters.

  15. Real-time simulation of biologically realistic stochastic neurons in VLSI.

    Science.gov (United States)

    Chen, Hsin; Saighi, Sylvain; Buhry, Laure; Renaud, Sylvie

    2010-09-01

    Neuronal variability has been thought to play an important role in the brain. As the variability mainly comes from the uncertainty in biophysical mechanisms, stochastic neuron models have been proposed for studying how neurons compute with noise. However, most papers are limited to simulating stochastic neurons in a digital computer. The speed and the efficiency are thus limited especially when a large neuronal network is of concern. This brief explores the feasibility of simulating the stochastic behavior of biological neurons in a very large scale integrated (VLSI) system, which implements a programmable and configurable Hodgkin-Huxley model. By simply injecting noise to the VLSI neuron, various stochastic behaviors observed in biological neurons are reproduced realistically in VLSI. The noise-induced variability is further shown to enhance the signal modulation of a neuron. These results point toward the development of analog VLSI systems for exploring the stochastic behaviors of biological neuronal networks in large scale.

  16. Vertically Coupled Microring Resonator Filter :Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo; Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  17. Vertically Coupled Microring Resonator Filter : Versatile Building Block for VLSI Filter Circuits

    Institute of Scientific and Technical Information of China (English)

    Yasuo Kokubun

    2003-01-01

    In this review, the recent progress in the development of vertically coupled micro-ring resonator filters is summarized and the potential applications of the filters leading to the development of VLSI photonics are described.

  18. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  19. Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

    Directory of Open Access Journals (Sweden)

    Zine El Abidine Alaoui Ismaili

    2009-08-01

    Full Text Available This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication.

  20. Architectural Prototyping

    DEFF Research Database (Denmark)

    Bardram, Jakob; Christensen, Henrik Bærbak; Hansen, Klaus Marius

    2004-01-01

    ' concerns with respect to a system under development. An architectural prototype is primarily a learning and communication vehicle used to explore and experiment with alternative architectural styles, features, and patterns in order to balance different architectural qualities. The use of architectural......A major part of software architecture design is learning how specific architectural designs balance the concerns of stakeholders. We explore the notion of "architectural prototypes", correspondingly architectural prototyping, as a means of using executable prototypes to investigate stakeholders...