Power efficient and high performance VLSI architecture for AES algorithm

Directory of Open Access Journals (Sweden)

K. Kalaiselvi

2015-09-01

Full Text Available Advanced encryption standard (AES algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay.

VLSI electronics microstructure science

CERN Document Server

1981-01-01

VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Directory of Open Access Journals (Sweden)

Rachmad Vidya Wicaksana Putra

2016-06-01

Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

Directory of Open Access Journals (Sweden)

Georgios Passas

2012-01-01

Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design

Directory of Open Access Journals (Sweden)

Erwan Fabiani

2009-01-01

Full Text Available This paper presents the “reconfigurable computing” teaching part of a computer science master course (first year on parallel architectures. The practical work sessions of this course rely on active pedagogy using problem-based learning, focused on designing a reconfigurable architecture for the implementation of an application class of image processing algorithms. We show how the successive steps of this project permit the student to experiment with several fundamental concepts of reconfigurable computing at different levels. Specific experiments include exploitation of architectural parallelism, dataflow and communicating component-based design, and configurability-specificity tradeoffs.

Trustworthy reconfigurable systems enhancing the security capabilities of reconfigurable hardware architectures

CERN Document Server

Feller, Thomas

2014-01-01

?Thomas Feller sheds some light on trust anchor architectures fortrustworthy reconfigurable systems. He is presenting novel concepts enhancing the security capabilities of reconfigurable hardware.Almost invisible to the user, many computer systems are embedded into everyday artifacts, such as cars, ATMs, and pacemakers. The significant growth of this market segment within the recent years enforced a rethinking with respect to the security properties and the trustworthiness of these systems. The trustworthiness of a system in general equates to the integrity of its system components. Hardware-b

Parallel VLSI Architecture

Science.gov (United States)

Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

1985-01-01

Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

Loop overhead reduction techniques for coarse grained reconfigurable architectures

NARCIS (Netherlands)

Vadivel, K.; Wijtvliet, M.; Jordans, R.; Corporaal, H.

2017-01-01

Due to their flexibility and high performance, Coarse Grained Reconfigurable Array (CGRA) are a topic of increasing research interest. However, CGRAs also have the potential to achieve very high energy efficiency in comparison to other reconfigurable architectures when hardware optimizations are

Block RAM-based architecture for real-time reconfiguration using Xilinx® FPGAs

Directory of Open Access Journals (Sweden)

Rikus le Roux

2015-07-01

Full Text Available Despite the advantages dynamic reconfiguration adds to a system, it only improves system performance if the execution time exceeds the configuration time. As a result, dynamic reconfiguration is only capable of improving the performance of quasi-static applications. In order to improve the performance of dynamic applications, researchers focus on improving the reconfiguration throughput. These approaches are mostly limited by the bus commonly used to connect the configuration controller to the memory, which contributes to the configuration time. A method proposed to ameliorate this overhead is an architecture utilizing localised block RAM (BRAM connected to the configuration controller to store the configuration bitstream. The aim of this paper is to illustrate the advantages of the proposed architecture, especially for reconfiguring real-time applications. This is done by validating the throughput of the architecture and comparing this to the maximum theoretical throughput of the internal configuration access port (ICAP. It was found that the proposed architecture is capable of reconfiguring an application within a time-frame suitable for real-time reconfiguration. The drawback of this method is that the BRAM is extremely limited and only a discrete set of configurations can be stored. This paper also proposes a method on how this can be mitigated without affecting the throughput.

Practical, redundant, failure-tolerant, self-reconfiguring embedded system architecture

Science.gov (United States)

Klarer, Paul R.; Hayward, David R.; Amai, Wendy A.

2006-10-03

This invention relates to system architectures, specifically failure-tolerant and self-reconfiguring embedded system architectures. The invention provides both a method and architecture for redundancy. There can be redundancy in both software and hardware for multiple levels of redundancy. The invention provides a self-reconfiguring architecture for activating redundant modules whenever other modules fail. The architecture comprises: a communication backbone connected to two or more processors and software modules running on each of the processors. Each software module runs on one processor and resides on one or more of the other processors to be available as a backup module in the event of failure. Each module and backup module reports its status over the communication backbone. If a primary module does not report, its backup module takes over its function. If the primary module becomes available again, the backup module returns to its backup status.

Heterogeneous reconfigurable processors for real-time baseband processing from algorithm to architecture

CERN Document Server

Zhang, Chenxin; Öwall, Viktor

2016-01-01

This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. •Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfigur...

Architecturally Reconfigurable Development of Mobile Games

DEFF Research Database (Denmark)

Zhang, Weishan

2005-01-01

. Mobile game domain variants could be handled uniformly and traced across all kinds of software assets. The architecture and configuration mechanism in our approach make optimizations that built into meta-components propagated to all product line members. We show this approach with an industrial Role-Playing-Game......Mobile game development must face the problem of multiple hardware and software platforms, which will bring large number of variants. To cut the development and maintenance efforts, in this paper, we present an architecturally reconfigurable software product line approach to develop mobile games...

Modular reconfigurable machines incorporating modular open architecture control

CSIR Research Space (South Africa)

Padayachee, J

2008-01-01

Full Text Available degrees of freedom on a single platform. A corresponding modular Open Architecture Control (OAC) system is presented. OAC overcomes the inflexibility of fixed proprietary automation, ensuring that MRMs provide the reconfigurability and extensibility...

VLSI implementations for image communications

CERN Document Server

Pirsch, P

1993-01-01

The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

Network topology exploration of mesh-based coarse-grain reconfigurable architectures

NARCIS (Netherlands)

Bansal, N.; Gupta, S.; Dutt, N.D.; Nicolau, A.; Gupta, R.

2004-01-01

Several coarse-grain reconfigurable architectures proposed recently consist of a large number of processing elements (PEs) connected in a mesh-like network topology. We study the effects of three aspects of network topology exploration on the performance of applications on these architectures: (a)

SmartCell: An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications

Directory of Open Access Journals (Sweden)

Liang Cao

2009-01-01

Full Text Available This paper presents SmartCell, a novel coarse-grained reconfigurable architecture, which tiles a large number of processor elements with reconfigurable interconnection fabrics on a single chip. SmartCell is able to provide high performance and energy efficient processing for stream-based applications. It can be configured to operate in various modes, such as SIMD, MIMD, and systolic array. This paper describes the SmartCell architecture design, including processing element, reconfigurable interconnection fabrics, instruction and control process, and configuration scheme. The SmartCell prototype with 64 PEs is implemented using 0.13  m CMOS standard cell technology. The core area is about 8.5  , and the power consumption is about 1.6 mW/MHz. The performance is evaluated through a set of benchmark applications, and then compared with FPGA, ASIC, and two well-known reconfigurable architectures including RaPiD and Montium. The results show that the SmartCell can bridge the performance and flexibility gap between ASIC and FPGA. It is also about 8% and 69% more energy efficient than Montium and RaPiD systems for evaluated benchmarks. Meanwhile, SmartCell can achieve 4 and 2 times more throughput gains when comparing with Montium and RaPiD, respectively. It is concluded that SmartCell system is a promising reconfigurable and energy efficient architecture for stream processing.

Architecture design of reconfigurable accelerators for demanding apllications.

NARCIS (Netherlands)

Jozwiak, L.; Jan, Y.

2010-01-01

This paper focuses on mastering the architecture development of reconfigurable hardware accelerators for highly demanding applications. It presents the results of our analysis of the main issues that have to be addressed when designing accelerators for demanding applications, when using as an

A novel configurable VLSI architecture design of window-based image processing method

Science.gov (United States)

Zhao, Hui; Sang, Hongshi; Shen, Xubang

2018-03-01

Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors

Directory of Open Access Journals (Sweden)

Shoaib Akram

2010-01-01

Full Text Available Interconnection networks for multicore processors are traditionally designed to serve a diversity of workloads. However, different workloads or even different execution phases of the same workload may benefit from different interconnect configurations. In this paper, we first motivate the need for workload-adaptive interconnection networks. Subsequently, we describe an interconnection network framework based on reconfigurable switches for use in medium-scale (up to 32 cores shared memory multicore processors. Our cost-effective reconfigurable interconnection network is implemented on a traditional shared bus interconnect with snoopy-based coherence, and it enables improved multicore performance. The proposed interconnect architecture distributes the cores of the processor into clusters with reconfigurable logic between clusters to support workload-adaptive policies for inter-cluster communication. Our interconnection scheme is complemented by interconnect-aware scheduling and additional interconnect optimizations which help boost the performance of multiprogramming and multithreaded workloads. We provide experimental results that show that the overall throughput of multiprogramming workloads (consisting of two and four programs can be improved by up to 60% with our configurable bus architecture. Similar gains can be achieved also for multithreaded applications as shown by further experiments. Finally, we present the performance sensitivity of the proposed interconnect architecture on shared memory bandwidth availability.

Design of a real-time open architecture controller for a reconfigurable machine tool

CSIR Research Space (South Africa)

Masekamela, I

2008-11-01

Full Text Available The paper presents the design and the development of a real-time, open architecture controller that is used for control of reconfigurable manufacturing tools (RMTs) in reconfigurable manufacturing systems (RMS). The controller that is presented can...

Three-dimensional design methodologies for tree-based FPGA architecture

CERN Document Server

Pangracious, Vinod; Mehrez, Habib

2015-01-01

This book focuses on the development of 3D design and implementation methodologies for Tree-based FPGA architecture. It also stresses the needs for new and augmented 3D CAD tools to support designs such as, the design for 3D, to manufacture high performance 3D integrated circuits and reconfigurable FPGA-based systems. This book was written as a text that covers the foundations of 3D integrated system design and FPGA architecture design. It was written for the use in an elective or core course at the graduate level in field of Electrical Engineering, Computer Engineering and Doctoral Research programs. No previous background on 3D integration is required, nevertheless fundamental understanding of 2D CMOS VLSI design is required. It is assumed that reader has taken the core curriculum in Electrical Engineering or Computer Engineering, with courses like CMOS VLSI design, Digital System Design and Microelectronics Circuits being the most important. It is accessible for self-study by both senior students and profe...

Vlsi implementation of flexible architecture for decision tree classification in data mining

Science.gov (United States)

Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

2017-07-01

The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

A Reconfigurable Design and Architecture of the Ethernet and HomePNA3.0 MAC

Science.gov (United States)

Khalilydermany, M.; Hosseinghadiry, M.

In this paper a reconfigurable architecture for Ethernet and HomePNA MAC is presented. By using this new architecture, Ethernet and HomePNA reconfigurable network card can be produced. This architecture has been implemented using VHDL language and after that synthesized on a chip. The differences between HomePNA (synchronized and unsynchronized mode) and Ethernet in collision detection mechanism and priority access to media have caused the need to separate architectures for Ethernet and HomePNA, but by using similarities of them, both the Ethernet and the HomePNA can be implemented in a single chip with a little extra hardware. The number of logical elements of the proposed architecture is increased by 19% in compare to when only an Ethernet MAC is implemented

Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

International Nuclear Information System (INIS)

Jones, W.F.; Byars, L.G.; Casey, M.E.

1988-01-01

A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Directory of Open Access Journals (Sweden)

Ying-Lun Chen

2015-08-01

Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-08-13

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

Science.gov (United States)

Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

2015-01-01

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

Science.gov (United States)

Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

1982-01-01

A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

VLSI signal processing technology

CERN Document Server

Swartzlander, Earl

1994-01-01

This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

Memory Based Machine Intelligence Techniques in VLSI hardware

OpenAIRE

James, Alex Pappachen

2012-01-01

We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures

Directory of Open Access Journals (Sweden)

Ghaffari Fakhreddine

2009-01-01

Full Text Available This paper presents an efficient dynamic and run-time Hardware/Software scheduling approach. This scheduling heuristic consists in mapping online the different tasks of a highly dynamic application in such a way that the total execution time is minimized. We consider soft real-time data flow graph oriented applications for which the execution time is function of the input data nature. The target architecture is composed of two processors connected to a dynamically reconfigurable hardware accelerator. Our approach takes advantage of the reconfiguration property of the considered architecture to adapt the treatment to the system dynamics. We compare our heuristic with another similar approach. We present the results of our scheduling method on several image processing applications. Our experiments include simulation and synthesis results on a Virtex V-based platform. These results show a better performance against existing methods.

VLSI design

CERN Document Server

Einspruch, Norman G

1986-01-01

VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

VLSI design

CERN Document Server

Basu, D K

2014-01-01

Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

Reconfiguration of Brain Network Architectures between Resting-State and Complexity-Dependent Cognitive Reasoning.

Science.gov (United States)

Hearne, Luke J; Cocchi, Luca; Zalesky, Andrew; Mattingley, Jason B

2017-08-30

Our capacity for higher cognitive reasoning has a measurable limit. This limit is thought to arise from the brain's capacity to flexibly reconfigure interactions between spatially distributed networks. Recent work, however, has suggested that reconfigurations of task-related networks are modest when compared with intrinsic "resting-state" network architecture. Here we combined resting-state and task-driven functional magnetic resonance imaging to examine how flexible, task-specific reconfigurations associated with increasing reasoning demands are integrated within a stable intrinsic brain topology. Human participants (21 males and 28 females) underwent an initial resting-state scan, followed by a cognitive reasoning task involving different levels of complexity, followed by a second resting-state scan. The reasoning task required participants to deduce the identity of a missing element in a 4 × 4 matrix, and item difficulty was scaled parametrically as determined by relational complexity theory. Analyses revealed that external task engagement was characterized by a significant change in functional brain modules. Specifically, resting-state and null-task demand conditions were associated with more segregated brain-network topology, whereas increases in reasoning complexity resulted in merging of resting-state modules. Further increments in task complexity did not change the established modular architecture, but affected selective patterns of connectivity between frontoparietal, subcortical, cingulo-opercular, and default-mode networks. Larger increases in network efficiency within the newly established task modules were associated with higher reasoning accuracy. Our results shed light on the network architectures that underlie external task engagement, and highlight selective changes in brain connectivity supporting increases in task complexity. SIGNIFICANCE STATEMENT Humans have clear limits in their ability to solve complex reasoning problems. It is thought that

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

Science.gov (United States)

Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

2016-12-07

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

Science.gov (United States)

Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

2014-01-01

This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

CERN Document Server

Pop, Paul; Madsen, Jan

2016-01-01

This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

A 10 Gb/s passive-components-based WDM-TDM reconfigurable optical access network architecture

NARCIS (Netherlands)

Tran, N.C.; Jung, H.D.; Okonkwo, C.M.; Tangdiongga, E.; Koonen, A.M.J.

2011-01-01

We propose a cost-effective, reconfigurable optical access network by employing passive components in the remote node and dual conventional optical transceivers in ONUs. The architecture is demonstrated with bidirectional transmission at 10 Gb/s.

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

Directory of Open Access Journals (Sweden)

Yuan-Jyun Chang

2016-12-01

Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

Science.gov (United States)

Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

1984-01-01

Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

eDNA: A Bio-Inspired Reconfigurable Hardware Cell Architecture Supporting Self-organisation and Self-healing

DEFF Research Database (Denmark)

Boesen, Michael Reibel; Madsen, Jan

2009-01-01

This paper presents the concept of a biological inspired reconfigurable hardware cell architecture which supports self-organisation and self-healing. Two fundamental processes in biology, namely fertilization-to-birth and cell self-healing have inspired the development of this cell architecture...... to simulate our self-organisation and self-healing algorithms and the results obtained from this looks promising....

Reconfigurable Autonomy for Future Planetary Rovers

Science.gov (United States)

Burroughes, Guy

Extra-terrestrial Planetary rover systems are uniquely remote, placing constraints in regard to communication, environmental uncertainty, and limited physical resources, and requiring a high level of fault tolerance and resistance to hardware degradation. This thesis presents a novel self-reconfiguring autonomous software architecture designed to meet the needs of extraterrestrial planetary environments. At runtime it can safely reconfigure low-level control systems, high-level decisional autonomy systems, and managed software architecture. The architecture can perform automatic Verification and Validation of self-reconfiguration at run-time, and enables a system to be self-optimising, self-protecting, and self-healing. A novel self-monitoring system, which is non-invasive, efficient, tunable, and autonomously deploying, is also presented. The architecture was validated through the use-case of a highly autonomous extra-terrestrial planetary exploration rover. Three major forms of reconfiguration were demonstrated and tested: first, high level adjustment of system internal architecture and goal; second, software module modification; and third, low level alteration of hardware control in response to degradation of hardware and environmental change. The architecture was demonstrated to be robust and effective in a Mars sample return mission use-case testing the operational aspects of a novel, reconfigurable guidance, navigation, and control system for a planetary rover, all operating in concert through a scenario that required reconfiguration of all elements of the system.

Electron beam effects on VLSI MOS conditions for testing and reconfiguration

International Nuclear Information System (INIS)

Girard, P.; Roche, F.M.; Pistoulet, B.

1986-01-01

Wafer scale integrated-MOS circuits problems related to test and reconfiguration by electron beams are analyzed. First of all the alterations in characteristics of MOS circuits submitted to an electron beam testing are considered. Then the capabilities of reconfiguration by an electron beam bombardment are discussed. The various phenomena involved are reviewed. Experimental data are reported and discussed on the light of data of the literature. (Auth.)

Real-Time 3D Face Acquisition Using Reconfigurable Hybrid Architecture

Directory of Open Access Journals (Sweden)

Mitéran Johel

2007-01-01

Full Text Available Acquiring 3D data of human face is a general problem which can be applied in face recognition, virtual reality, and many other applications. It can be solved using stereovision. This technique consists in acquiring data in three dimensions from two cameras. The aim is to implement an algorithmic chain which makes it possible to obtain a three-dimensional space from two two-dimensional spaces: two images coming from the two cameras. Several implementations have already been considered. We propose a new simple real-time implementation based on a hybrid architecture (FPGA-DSP, allowing to consider an embedded and reconfigurable processing. Then we show our method which provides depth map of face, dense and reliable, and which can be implemented on an embedded architecture. A various architecture study led us to a judicious choice allowing to obtain the desired result. The real-time data processing is implemented in an embedded architecture. We obtain a dense face disparity map, precise enough for considered applications (multimedia, virtual worlds, biometrics and using a reliable method.

VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

Directory of Open Access Journals (Sweden)

N.R. Divya

2014-08-01

Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

VLSI architectures for modern error-correcting codes

CERN Document Server

Zhang, Xinmiao

2015-01-01

Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

OpenAIRE

Maggiani , Luca; Salvadori , Claudio; Petracca , Matteo; Pagano , Paolo; Saletti , Roberto

2013-01-01

International audience; Smart Camera Networks (SCNs) is nowadays an emerging research field which represents the natural evolution of centralized computer vision applications towards full distributed and pervasive systems. In such a scenario, one of the biggest effort is in the definition of a flexible and reconfigurable SCN node architecture able to remotely support the possibility of updating the application parameters and changing the running computer vision applications at run-time. In th...

VLSI design

CERN Document Server

Chandrasetty, Vikram Arkalgud

2011-01-01

This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

VLSI in medicine

CERN Document Server

Einspruch, Norman G

1989-01-01

VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

2008-01-21

In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

VLSI electronics microstructure science

CERN Document Server

1982-01-01

VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

NASA Space Engineering Research Center for VLSI systems design

Science.gov (United States)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Reconfigurable radio systems network architectures and standards

CERN Document Server

Iacobucci, Maria Stella

2013-01-01

This timely book provides a standards-based view of the development, evolution, techniques and potential future scenarios for the deployment of reconfigurable radio systems.  After an introduction to radiomobile and radio systems deployed in the access network, the book describes cognitive radio concepts and capabilities, which are the basis for reconfigurable radio systems.  The self-organizing network features introduced in 3GPP standards are discussed and IEEE 802.22, the first standard based on cognitive radio, is described. Then the ETSI reconfigurable radio systems functional ar

Design and demonstration of a multitechnology FPGA for photonic information processing

Science.gov (United States)

Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

2003-11-01

We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

Parallel computation of nondeterministic algorithms in VLSI

Energy Technology Data Exchange (ETDEWEB)

Hortensius, P D

1987-01-01

This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

Research on the Architecture of a Basic Reconfigurable Information Communication Network

Directory of Open Access Journals (Sweden)

Ruimin Wang

2013-01-01

Full Text Available The current information network cannot fundamentally meet some urgent requirements, such as providing ubiquitous information services and various types of heterogeneous network, supporting diverse and comprehensive network services, possessing high quality communication effects, ensuring the security and credibility of information interaction, and implementing effective supervisory control. This paper provides the theory system for the basic reconfigurable information communication network based on the analysis of present problems on the Internet and summarizes the root of these problems. It also provides an in-depth discussion about the related technologies and the prime components of the architecture.

A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

Directory of Open Access Journals (Sweden)

Lu Wan

2012-01-01

Full Text Available We propose a fast data relay (FDR mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture. FDR can not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding inter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose the supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of applications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental results for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher performance than ADRES and RCP, respectively.

Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

Science.gov (United States)

Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

1989-01-01

The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

Science.gov (United States)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

VLSI structures for track finding

International Nuclear Information System (INIS)

Dell'Orso, M.

1989-01-01

We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

VLSI architecture and design for the Fermat Number Transform implementation

Energy Technology Data Exchange (ETDEWEB)

Pajayakrit, A.

1987-01-01

A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

Reconfigurable architecture based on fiber bragg gratings for indoor networks (Arquitectura reconfigurable basada en redes de difracción de Bragg para redes convergentes indoor ópticas

Directory of Open Access Journals (Sweden)

Gustavo Adolfo Puerto-Leguizamón

2016-01-01

Full Text Available This paper presents an approach for dynamic reconfiguration of wavelength channels for future indoor network architectures. The approach exploits the tunability and the rejection profile of Fiber Bragg Gratings (FBG to implement service distribution strategies that includes Unicast, Broadcast and Multicast scenarios for fixed and mobile users. Experimental demonstrations based on two implementations show results with 1% average degradation for Error Vector Magnitude (EVM values and up to 2,2 dB for 1x10-12 Bit Error Rate (BER. In particular, the proposed architectures fit for large in-building networks

A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

Science.gov (United States)

Shi, Cong; Luo, Gang

2018-04-01

This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

Directory of Open Access Journals (Sweden)

Sanjay Singh

2017-06-01

Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

Synthesis algorithm of VLSI multipliers for ASIC

Science.gov (United States)

Chua, O. H.; Eldin, A. G.

1993-01-01

Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

Directory of Open Access Journals (Sweden)

Sungho Kang

1996-01-01

Full Text Available In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element (PE array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.

Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

Directory of Open Access Journals (Sweden)

Sergio Saponara

2004-09-01

Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip

Directory of Open Access Journals (Sweden)

Diana Göhringer

2009-01-01

Full Text Available Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.

Plasma processing for VLSI

CERN Document Server

Einspruch, Norman G

1984-01-01

VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

IMPLEMENTATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR PHYSICAL HYBRID INDICATOR CHANNEL OF LTE-ADVANCED USING PARTIAL RECONFIGURATION IN ML605 VIRTEX-6 DEVICE

Directory of Open Access Journals (Sweden)

S. Syed Ameer Abbas

2014-09-01

Full Text Available LTE-A (Long Term Evolution-Advanced is the fourth generation technology to increase the speed of wireless data network. The LTE-A Physical layer provides both data and control information between an enhanced base station and mobile user equipment which is quite complex and consists of a mixture of technologies. Since there is requirement for more resources to accommodate all the channels in a single FPGA, Partial Reconfiguration (PR technique is introduced to configure the total hardware into sub modules that configure and operate in different instants of time. PR enables a part of FPGA to be reconfigured, while the rest continues to function without any interruptions and reduces the hardware resource power and fabric area. This work proposes the realization of transmitter and receiver architecture of Physical Hybrid Indicator Channel (PHICH channel for LTE-A using partial reconfiguration on xc6vlx240tff1156-1 FPGA. The receiver architecture for PHICH is to report the correct reception of uplink user data to the User Equipment (UE in the form of Acknowledgment (ACK, or Negative ACK (NACK in a 1 millisecond duration sub-frame of Long Term Evolution (LTE System. The modules for the different diversities are reconfigured based on the control signals from the transmitter.

Architecture for dynamically reconfigurable real-time lossless compression

Science.gov (United States)

Carter, Alison J.; Audsley, Neil C.

2004-05-01

Image compression is a computationally intensive task, which can be undertaken most efficiently by dedicated hardware. If a portable device is to carry out real-time compression on a variety of image types, then it may be useful to reconfigure the circuitry dynamically. Using commercial off-the shelf (COTS) chips, reconfiguration is usually implemented by a complete re-load from memory, but it is also possible to perform a partial reconfiguration. This work studies the use of programmable hardware devices to implement the lossless JPEG compression algorithm in real-time on a stream of independent image frames. The data rate is faster than can be compressed serially in hardware by a single processor, so the operation is split amongst several processors. These are implemented as programmable circuits, together with necessary buffering of input and output data. The timing of input and output, bearing in mind the different, and context-dependent amounts of data due to Huffman coding, is analyzed using storage-timing graphs. Because there may be differing parameters from one frame to the next, several different configurations are prepared and stored, ready to load as required. The scheduling of these reconfigurations, and the distribution/recombination of data streams is studied, giving an analysis of the real-time performance.

Reconfigurable Multicore Architectures for Streaming Applications

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Kokkeler, Andre B.J.; Rauwerda, G.K.; Jacobs, J.W.M.; Nicolescu, G.; Mosterman, P.J.

2009-01-01

This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items

Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks

DEFF Research Database (Denmark)

Bogdanov, Andrey; Kavun, Elif Bilge; Tischhauser, Elmar

2012-01-01

An accurate estimation of the success probability and data complexity of linear cryptanalysis is a fundamental question in symmetric cryptography. In this paper, we propose an efficient reconfigurable hardware architecture to compute the success probability and data complexity of Matsui's Algorithm...... block lengths ensures that any empirical observations are not due to differences in statistical behavior for artificially small block lengths. Rather surprisingly, we observed in previous experiments a significant deviation between the theory and practice for Matsui's Algorithm 2 for larger block sizes...

Accelerating artificial intelligence with reconfigurable computing

Science.gov (United States)

Cieszewski, Radoslaw

Reconfigurable computing is emerging as an important area of research in computer architectures and software systems. Many algorithms can be greatly accelerated by placing the computationally intense portions of an algorithm into reconfigurable hardware. Reconfigurable computing combines many benefits of both software and ASIC implementations. Like software, the mapped circuit is flexible, and can be changed over the lifetime of the system. Similar to an ASIC, reconfigurable systems provide a method to map circuits into hardware. Reconfigurable systems therefore have the potential to achieve far greater performance than software as a result of bypassing the fetch-decode-execute operations of traditional processors, and possibly exploiting a greater level of parallelism. Such a field, where there is many different algorithms which can be accelerated, is an artificial intelligence. This paper presents example hardware implementations of Artificial Neural Networks, Genetic Algorithms and Expert Systems.

Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

Science.gov (United States)

Yu, T; Sejnowski, T J; Cauwenberghs, G

2011-10-01

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

Compiling for Application Specific Computational Acceleration in Reconfigurable Architectures Final Report CRADA No. TSB-2033-01

Energy Technology Data Exchange (ETDEWEB)

De Supinski, B. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Caliga, D. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

2017-09-28

The primary objective of this project was to develop memory optimization technology to efficiently deliver data to, and distribute data within, the SRC-6's Field Programmable Gate Array- ("FPGA") based Multi-Adaptive Processors (MAPs). The hardware/software approach was to explore efficient MAP configurations and generate the compiler technology to exploit those configurations. This memory accessing technology represents an important step towards making reconfigurable symmetric multi-processor (SMP) architectures that will be a costeffective solution for large-scale scientific computing.

ALI (Autonomous Lunar Investigator): Revolutionary Approach to Exploring the Moon with Addressable Reconfigurable Technology

Science.gov (United States)

Clark, P. E.; Curtis, S. A.; Rilee, M. L.; Floyd, S. R.

2005-01-01

Addressable Reconfigurable Technology (ART) based structures: Mission Concepts based on Addressable Reconfigurable Technology (ART), originally studied for future ANTS (Autonomous Nanotechnology Swarm) Space Architectures, are now being developed as rovers for nearer term use in lunar and planetary surface exploration. The architecture is based on the reconfigurable tetrahedron as a building block. Tetrahedra are combined to form space-filling networks, shaped for the required function. Basic structural components are highly modular, addressable arrays of robust nodes (tetrahedral apices) from which highly reconfigurable struts (tetrahedral edges), acting as supports or tethers, are efficiently reversibly deployed/stowed, transforming and reshaping the structures as required.

A reconfigurable hybrid supervisory system for process control

International Nuclear Information System (INIS)

Garcia, H.E.; Ray, A.; Edwards, R.M.

1994-01-01

This paper presents a reconfigurable approach to decision and control systems for complex dynamic processes. The proposed supervisory control system is a reconfigurable hybrid architecture structured into three functional levels of hierarchy, namely, execution, supervision, and coordination. While the bottom execution level is constituted by either reconfigurable continuously varying or discrete event systems, the top two levels are necessarily governed by reconfigurable sets of discrete event decision and control systems. Based on the process status, the set of active control and supervisory algorithm is chosen. The reconfigurable hybrid system is briefly described along with a discussion on its implementation at the Experimental Breeder Reactor II of Argonne National Laboratory. A process control application of this hybrid system is presented and evaluated in an in-plant experiment

A reconfigurable hybrid supervisory system for process control

International Nuclear Information System (INIS)

Garcia, H.E.; Ray, A.; Edwards, R.M.

1994-01-01

This paper presents a reconfigurable approach to decision and control systems for complex dynamic processes. The proposed supervisory control system is a reconfigurable hybrid architecture structured into three functional levels of hierarchy, namely, execution, supervision, and coordination. While, the bottom execution level is constituted by either reconfigurable continuously varying or discrete event systems, the top two levels are necessarily governed by reconfigurable sets of discrete event decision and control systems. Based on the process status, the set of active control and supervisory algorithm is chosen. The reconfigurable hybrid system is briefly described along with a discussion on its implementation at the Experimental Breeder Reactor 2 of Argonne National Laboratory. A process control application of this hybrid system is presented and evaluated in an in-plant experiment

Rational design of reconfigurable prismatic architected materials

Science.gov (United States)

Overvelde, Johannes T. B.; Weaver, James C.; Hoberman, Chuck; Bertoldi, Katia

2017-01-01

Advances in fabrication technologies are enabling the production of architected materials with unprecedented properties. Most such materials are characterized by a fixed geometry, but in the design of some materials it is possible to incorporate internal mechanisms capable of reconfiguring their spatial architecture, and in this way to enable tunable functionality. Inspired by the structural diversity and foldability of the prismatic geometries that can be constructed using the snapology origami technique, here we introduce a robust design strategy based on space-filling tessellations of polyhedra to create three-dimensional reconfigurable materials comprising a periodic assembly of rigid plates and elastic hinges. Guided by numerical analysis and physical prototypes, we systematically explore the mobility of the designed structures and identify a wide range of qualitatively different deformations and internal rearrangements. Given that the underlying principles are scale-independent, our strategy can be applied to the design of the next generation of reconfigurable structures and materials, ranging from metre-scale transformable architectures to nanometre-scale tunable photonic systems.

VLSI Architecture and Design

OpenAIRE

Johnsson, Lennart

1980-01-01

Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible....

Hardware/software virtualization for the reconfigurable multicore platform.

NARCIS (Netherlands)

Ferger, M.; Al Kadi, M.; Hübner, M.; Koedam, M.L.P.J.; Sinha, S.S.; Goossens, K.G.W.; Marchesan Almeida, Gabriel; Rodrigo Azambuja, J.; Becker, Juergen

2012-01-01

This paper presents the Flex Tiles approach for the virtualization of hardware and software for a reconfigurable multicore architecture. The approach enables the virtualization of a dynamic tile-based hardware architecture consisting of processing tiles connected via a network-on-chip and a

Lithography for VLSI

CERN Document Server

Einspruch, Norman G

1987-01-01

VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

An information-theoretic approach to motor action decoding with a reconfigurable parallel architecture.

Science.gov (United States)

Craciun, Stefan; Brockmeier, Austin J; George, Alan D; Lam, Herman; Príncipe, José C

2011-01-01

Methods for decoding movements from neural spike counts using adaptive filters often rely on minimizing the mean-squared error. However, for non-Gaussian distribution of errors, this approach is not optimal for performance. Therefore, rather than using probabilistic modeling, we propose an alternate non-parametric approach. In order to extract more structure from the input signal (neuronal spike counts) we propose using minimum error entropy (MEE), an information-theoretic approach that minimizes the error entropy as part of an iterative cost function. However, the disadvantage of using MEE as the cost function for adaptive filters is the increase in computational complexity. In this paper we present a comparison between the decoding performance of the analytic Wiener filter and a linear filter trained with MEE, which is then mapped to a parallel architecture in reconfigurable hardware tailored to the computational needs of the MEE filter. We observe considerable speedup from the hardware design. The adaptation of filter weights for the multiple-input, multiple-output linear filters, necessary in motor decoding, is a highly parallelizable algorithm. It can be decomposed into many independent computational blocks with a parallel architecture readily mapped to a field-programmable gate array (FPGA) and scales to large numbers of neurons. By pipelining and parallelizing independent computations in the algorithm, the proposed parallel architecture has sublinear increases in execution time with respect to both window size and filter order.

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

Science.gov (United States)

Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

2014-05-01

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

Surface and interface effects in VLSI

CERN Document Server

Einspruch, Norman G

1985-01-01

VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

Architectural Analysis of Dynamically Reconfigurable Systems

Science.gov (United States)

Lindvall, Mikael; Godfrey, Sally; Ackermann, Chris; Ray, Arnab; Yonkwa, Lyly

2010-01-01

oTpics include: the problem (increased flexibility of architectural styles decrease analyzability, behavior emerges and varies depending on the configuration, does the resulting system run according to the intended design, and architectural decisions can impede or facilitate testing); top down approach to architecture analysis, detection of defects and deviations, and architecture and its testability; currently targeted projects GMSEC and CFS; analyzing software architectures; analyzing runtime events; actual architecture recognition; GMPUB in Dynamic SAVE; sample output from new approach; taking message timing delays into account; CFS examples of architecture and testability; some recommendations for improved testablity; and CFS examples of abstract interfaces and testability; CFS example of opening some internal details.

Reconfigurable Computing for Dynamically Reprogrammable Communications, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — This project addresses the need for a framework and domain architecture suitable for reconfigurable transceivers and associated component technologies. The goal of...

Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

Directory of Open Access Journals (Sweden)

Liang Ying-Chang

2005-01-01

Full Text Available This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP -based communication systems, including orthogonal frequency-division multiplexing (OFDM, single-carrier cyclic-prefix (SCCP system, multicarrier (MC code-division multiple access (MC-CDMA, MC direct-sequence CDMA (MC-DS-CDMA, CP-based CDMA (CP-CDMA, and CP-based direct-sequence CDMA (CP-DS-CDMA. A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.

High-throughput sample adaptive offset hardware architecture for high-efficiency video coding

Science.gov (United States)

Zhou, Wei; Yan, Chang; Zhang, Jingzhi; Zhou, Xin

2018-03-01

A high-throughput hardware architecture for a sample adaptive offset (SAO) filter in the high-efficiency video coding video coding standard is presented. First, an implementation-friendly and simplified bitrate estimation method of rate-distortion cost calculation is proposed to reduce the computational complexity in the mode decision of SAO. Then, a high-throughput VLSI architecture for SAO is presented based on the proposed bitrate estimation method. Furthermore, multiparallel VLSI architecture for in-loop filters, which integrates both deblocking filter and SAO filter, is proposed. Six parallel strategies are applied in the proposed in-loop filters architecture to improve the system throughput and filtering speed. Experimental results show that the proposed in-loop filters architecture can achieve up to 48% higher throughput in comparison with prior work. The proposed architecture can reach a high-operating clock frequency of 297 MHz with TSMC 65-nm library and meet the real-time requirement of the in-loop filters for 8 K × 4 K video format at 132 fps.

Reconfigurable vision system for real-time applications

Science.gov (United States)

Torres-Huitzil, Cesar; Arias-Estrada, Miguel

2002-03-01

Recently, a growing community of researchers has used reconfigurable systems to solve computationally intensive problems. Reconfigurability provides optimized processors for systems on chip designs, and makes easy to import technology to a new system through reusable modules. The main objective of this work is the investigation of a reconfigurable computer system targeted for computer vision and real-time applications. The system is intended to circumvent the inherent computational load of most window-based computer vision algorithms. It aims to build a system for such tasks by providing an FPGA-based hardware architecture for task specific vision applications with enough processing power, using the minimum amount of hardware resources as possible, and a mechanism for building systems using this architecture. Regarding the software part of the system, a library of pre-designed and general-purpose modules that implement common window-based computer vision operations is being investigated. A common generic interface is established for these modules in order to define hardware/software components. These components can be interconnected to develop more complex applications, providing an efficient mechanism for transferring image and result data among modules. Some preliminary results are presented and discussed.

Organizational Reconfiguration and Strategic Response

DEFF Research Database (Denmark)

Møller Larsen, Marcus; Pedersen, Torben

2014-01-01

this, firms need a high degree of architectural knowledge, which is typically gained through learning by doing. We therefore argue that firms with more offshoring experience are more likely to include organizational objectives in their offshoring strategies. We develop and find support......The purpose of this paper is to investigate the effect of the organizational reconfiguration of offshoring on firms’ strategies. A consequence of offshoring is the need to reintegrate the geographically relocated organizational activities into a coherent organizational architecture. In order to do...... for this hypothesis using a mixed-method approach based on a qualitative case study and comprehensive data from the Offshoring Research Network. These findings contribute to research on the organizational design and architecture of offshoring and the dynamics of organizational architectures....

An analog VLSI real time optical character recognition system based on a neural architecture

International Nuclear Information System (INIS)

Bo, G.; Caviglia, D.; Valle, M.

1999-01-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

An analog VLSI real time optical character recognition system based on a neural architecture

Energy Technology Data Exchange (ETDEWEB)

Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

1999-03-01

In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

Reconfigurable multi-DSP parallel computing architecture based on DSM%基于DSM的可重构多DSP并行处理架构

Institute of Scientific and Technical Information of China (English)

程鑫; 吴华春

2012-01-01

提出一种基于DSM的可在线重构多DSP并行处理架构,采用基于自定义内部总线的信息传递服务,在分布式物理内存上实现了统一编址的共享内存模型,减小了DSP之间的数据传递开销；设计基于VME总线的在线重构来实现针对消息传递服务的重定义,增强了并行计算架构的通用性.实验表明,采用此DSM能减小了并行DSP对共享数据同步访问开销,满足多轴精密同步运动控制系统需求.%A design of reconfigurable multi-digital signal processor (DSP) parallel computing architecture based on distributed shared memory (DSM) was proposed. A message-passing communication based on the user-defined internal bus (IB) was designed to implement a shared memory model on physically distributed memory, which decreased the data transmission overhead. Online reconfiguration mechanism was designed to implement message-passing communication reconfiguration, which in-creasd the universality of parallel architecture. The experiment shows that adopting the DSM introduced can reduce simultaneous access overhead to shared data, which satisfies the requirements of ultra-precise multi-axis motion control system.

Specifying structural constraints of architectural patterns in the ARCHERY language

International Nuclear Information System (INIS)

Sanchez, Alejandro; Barbosa, Luis S.; Riesco, Daniel

2015-01-01

ARCHERY is an architectural description language for modelling and reasoning about distributed, heterogeneous and dynamically reconfigurable systems in terms of architectural patterns. The language supports the specification of architectures and their reconfiguration. This paper introduces a language extension for precisely describing the structural design decisions that pattern instances must respect in their (re)configurations. The extension is a propositional modal logic with recursion and nominals referencing components, i.e., a hybrid µ-calculus. Its expressiveness allows specifying safety and liveness constraints, as well as paths and cycles over structures. Refinements of classic architectural patterns are specified

Specifying structural constraints of architectural patterns in the ARCHERY language

Energy Technology Data Exchange (ETDEWEB)

Sanchez, Alejandro [Departamento de Informática, Universidad Nacional de San Luis, Ejército de los Andes 950, D5700HHW San Luis (Argentina); HASLab INESC TEC and Universidade do Minho, Campus de Gualtar, 4710-057 Braga (Portugal); Barbosa, Luis S. [HASLab INESC TEC and Universidade do Minho, Campus de Gualtar, 4710-057 Braga (Portugal); Riesco, Daniel [Departamento de Informática, Universidad Nacional de San Luis, Ejército de los Andes 950, D5700HHW San Luis (Argentina)

2015-03-10

ARCHERY is an architectural description language for modelling and reasoning about distributed, heterogeneous and dynamically reconfigurable systems in terms of architectural patterns. The language supports the specification of architectures and their reconfiguration. This paper introduces a language extension for precisely describing the structural design decisions that pattern instances must respect in their (re)configurations. The extension is a propositional modal logic with recursion and nominals referencing components, i.e., a hybrid µ-calculus. Its expressiveness allows specifying safety and liveness constraints, as well as paths and cycles over structures. Refinements of classic architectural patterns are specified.

Reconfigurable computing the theory and practice of FPGA-based computation

CERN Document Server

Hauck, Scott

2010-01-01

Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap between the separate worlds of hardware and software design- the key feature of reconfigurable computing is its groundbreaking ability to perform computations in hardware to increase performance while retaining the flexibility of a software solution. Reconfigurable computers serve as affordable, fast, and accurate tools for developing designs ranging from single chip architectures to multi-chip and embedded systems. Scott Hauck and Andre DeHon have assembled a group of the key experts in the fields of both hardwa

Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

Science.gov (United States)

Chen, Paul; Butts, Mike; Budlong, Brad; Wasson, Paul

2008-04-01

This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides streamlined inter-processor connections with deterministically high performance. Software programmability, scalability, ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They exchange data and control through a network of self-synchronizing channels. A common application design pattern on this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and decompression, network processing, and graphics applications.

Electro-optic techniques for VLSI interconnect

Science.gov (United States)

Neff, J. A.

1985-03-01

A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

Multi-valued LSI/VLSI logic design

Science.gov (United States)

Santrakul, K.

A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

Dynamic Reconfiguration in Real-Time Systems Energy, Performance, and Thermal Perspectives

CERN Document Server

Wang, Weixun; Ranka, Sanjay

2013-01-01

Given the widespread use of real-time multitasking systems, there are tremendous optimization opportunities if reconfigurable computing can be effectively incorporated while maintaining performance and other design constraints of typical applications. The focus of this book is to describe the dynamic reconfiguration techniques that can be safely used in real-time systems. This book provides comprehensive approaches by considering synergistic effects of computation, communication as well as storage together to significantly improve overall performance, power, energy and temperature.  Provides a comprehensive introduction to optimization and dynamic reconfiguration techniques in real-time embedded systems; Covers state-of-the-art techniques and ongoing research in reconfigurable architectures; Focuses on algorithms tuned for dynamic reconfiguration techniques in real-time systems;  Provides reference for anyone designing low-power systems, energy-/temperature-constrained devices, and power-performance efficie...

Technology computer aided design simulation for VLSI MOSFET

CERN Document Server

Sarkar, Chandan Kumar

2013-01-01

Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

Wideband Monolithic Tile for Reconfigurable Phased Arrays

Science.gov (United States)

2017-03-01

interference and jamming. Previous reconfigurable architectures [1] were limited in bandwidth and performance by the use of discrete SMT components with...Settings Figure 7 shows the feed point and segment activation with control settings optimized for Gain, Horizontal Polarization, Steered at Phi = 15°, 6

Architectures for single-chip image computing

Science.gov (United States)

Gove, Robert J.

1992-04-01

This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

Adaptive Architectural Envelope

DEFF Research Database (Denmark)

Foged, Isak Worre; Kirkegaard, Poul Henning

2010-01-01

. The general scopes of this paper are to develop a new adaptive kinetic architectural structure, particularly a reconfigurable architectural structure which can transform body shape from planar geometries to hyper-surfaces using different control strategies, i.e. a transformation into more than one or two...

Wavelength-encoded OCDMA system using opto-VLSI processors.

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

Wavelength-encoded OCDMA system using opto-VLSI processors

Science.gov (United States)

Aljada, Muhsen; Alameh, Kamal

2007-07-01

We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

The Chameleon Architecture for Streaming DSP Applications

Directory of Open Access Journals (Sweden)

André B. J. Kokkeler

2007-02-01

Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

The Chameleon Architecture for Streaming DSP Applications

Directory of Open Access Journals (Sweden)

Heysters PaulM

2007-01-01

Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

Reconfigurable support vector machine classifier with approximate computing

NARCIS (Netherlands)

van Leussen, M.J.; Huisken, J.; Wang, L.; Jiao, H.; De Gyvez, J.P.

2017-01-01

Support Vector Machine (SVM) is one of the most popular machine learning algorithms. An energy-efficient SVM classifier is proposed in this paper, where approximate computing is utilized to reduce energy consumption and silicon area. A hardware architecture with reconfigurable kernels and

Reconfigurable, Cognitive Software-Defined Radio

Science.gov (United States)

Bhat, Arvind

2015-01-01

Software-defined radio (SDR) technology allows radios to be reconfigured to perform different communication functions without using multiple radios to accomplish each task. Intelligent Automation, Inc., has developed SDR platforms that switch adaptively between different operation modes. The innovation works by modifying both transmit waveforms and receiver signal processing tasks. In Phase I of the project, the company developed SDR cognitive capabilities, including adaptive modulation and coding (AMC), automatic modulation recognition (AMR), and spectrum sensing. In Phase II, these capabilities were integrated into SDR platforms. The reconfigurable transceiver design employs high-speed field-programmable gate arrays, enabling multimode operation and scalable architecture. Designs are based on commercial off-the-shelf (COTS) components and are modular in nature, making it easier to upgrade individual components rather than redesigning the entire SDR platform as technology advances.

Chameleon-reconfigurability in hand-held multimedia computers

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Bos, M.; Havinga, Paul J.M.; Smit, Jaap; Mullender, Sape J.; Gellersen, H.W.

In this paper a reconfigurable systems-architecture in combination with a QoS driven operating system is introduced that can deal with the inherent dynamics of future mobile systems. We claim that a radical new approach has to be taken in order to fulfill the requirements - in terms of processing

Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

Science.gov (United States)

Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

1985-01-01

The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Algorithms, architectures and information systems security

CERN Document Server

Sur-Kolay, Susmita; Nandy, Subhas C; Bagchi, Aditya

2008-01-01

This volume contains articles written by leading researchers in the fields of algorithms, architectures, and information systems security. The first five chapters address several challenging geometric problems and related algorithms. These topics have major applications in pattern recognition, image analysis, digital geometry, surface reconstruction, computer vision and in robotics. The next five chapters focus on various optimization issues in VLSI design and test architectures, and in wireless networks. The last six chapters comprise scholarly articles on information systems security coverin

Compact MOSFET models for VLSI design

CERN Document Server

Bhattacharyya, A B

2009-01-01

Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

Directory of Open Access Journals (Sweden)

Jim Harkin

2009-01-01

Full Text Available FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE, incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

Directory of Open Access Journals (Sweden)

Urard Pascal

2006-01-01

Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

Optimal energy management strategy for self-reconfigurable batteries

International Nuclear Information System (INIS)

Bouchhima, Nejmeddine; Schnierle, Marc; Schulte, Sascha; Birke, Kai Peter

2017-01-01

This paper proposes a novel energy management strategy for multi-cell high voltage batteries where the current through each cell can be controlled, called self-reconfigurable batteries. An optimized control strategy further enhances the energy efficiency gained by the hardware architecture of those batteries. Currently, achieving cell equalization by using the active balancing circuits is considered as the best way to optimize the energy efficiency of the battery pack. This study demonstrates that optimizing the energy efficiency of self-reconfigurable batteries is no more strongly correlated to the cell balancing. According to the features of this novel battery architecture, the energy management strategy is formulated as nonlinear dynamic optimization problem. To solve this optimal control, an optimization algorithm that generates the optimal discharge policy for a given driving cycle is developed based on dynamic programming and code vectorization. The simulation results show that the designed energy management strategy maximizes the system efficiency across the battery lifetime over conventional approaches. Furthermore, the present energy management strategy can be implemented online due to the reduced complexity of the optimization algorithm. - Highlights: • The energy efficiency of self-reconfigurable batteries is maximized. • The energy management strategy for the battery is formulated as optimal control problem. • Developing an optimization algorithm using dynamic programming techniques and code vectorization. • Simulation studies are conducted to validate the proposed optimal strategy.

An energy-efficient high-performance processor with reconfigurable data-paths using RSFQ circuits

International Nuclear Information System (INIS)

Takagi, Naofumi

2013-01-01

Highlights: ► An idea of a high-performance computer using RSFQ circuits is shown. ► An outline of processor with reconfigurable data-paths (RDPs) is shown. ► Architectural details of an SFQ-RDP are described. -- Abstract: We show recent progress in our research on an energy-efficient high-performance processor with reconfigurable data-paths (RDPs) using rapid single-flux-quantum (RSFQ) circuits. We mainly describe the architectural details of an RDP implemented using RSFQ circuits. An RDP consists of a lot of floating-point units (FPUs) and operand routing networks (ORNs) which connect the FPUs. We reconfigure the RDP to fit a computation, i.e., a group of floating-point operations, appearing in a ‘for’ loop of programs for numerical computations by setting the route in ORNs before the execution of the loop. In the RDP, a lot of FPUs work in parallel with pipelined fashion, and hence, very high-performance computation is achieved

Artificial immune system algorithm in VLSI circuit configuration

Science.gov (United States)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

A memory-array architecture for computer vision

Energy Technology Data Exchange (ETDEWEB)

Balsara, P.T.

1989-01-01

With the fast advances in the area of computer vision and robotics there is a growing need for machines that can understand images at a very high speed. A conventional von Neumann computer is not suited for this purpose because it takes a tremendous amount of time to solve most typical image processing problems. Exploiting the inherent parallelism present in various vision tasks can significantly reduce the processing time. Fortunately, parallelism is increasingly affordable as hardware gets cheaper. Thus it is now imperative to study computer vision in a parallel processing framework. The author should first design a computational structure which is well suited for a wide range of vision tasks and then develop parallel algorithms which can run efficiently on this structure. Recent advances in VLSI technology have led to several proposals for parallel architectures for computer vision. In this thesis he demonstrates that a memory array architecture with efficient local and global communication capabilities can be used for high speed execution of a wide range of computer vision tasks. This architecture, called the Access Constrained Memory Array Architecture (ACMAA), is efficient for VLSI implementation because of its modular structure, simple interconnect and limited global control. Several parallel vision algorithms have been designed for this architecture. The choice of vision problems demonstrates the versatility of ACMAA for a wide range of vision tasks. These algorithms were simulated on a high level ACMAA simulator running on the Intel iPSC/2 hypercube, a parallel architecture. The results of this simulation are compared with those of sequential algorithms running on a single hypercube node. Details of the ACMAA processor architecture are also presented.

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Directory of Open Access Journals (Sweden)

T. Kalavathi Devi

2015-01-01

Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

ETSI-Standard Reconfigurable Mobile Device for Supporting the Licensed Shared Access

Directory of Open Access Journals (Sweden)

Kyunghoon Kim

2016-01-01

Full Text Available In order for a Mobile Device (MD to support the Licensed Shared Access (LSA, the MD should be reconfigurable, meaning that the configuration of a MD must be adaptively changed in accordance with the communication standard adopted in a given LSA system. Based on the standard architecture for reconfigurable MD defined in Working Group (WG 2 of the Technical Committee (TC Reconfigurable Radio System (RRS of the European Telecommunications Standards Institute (ETSI, this paper presents a procedure to transfer control signals among the software entities of a reconfigurable MD required for implementing the LSA. This paper also presents an implementation of a reconfigurable MD prototype that realizes the proposed procedure. The modem and Radio Frequency (RF part of the prototype MD are implemented with the NVIDIA GeForce GTX Titan Graphic Processing Unit (GPU and the Universal Software Radio Peripheral (USRP N210, respectively. With a preset scenario that consists of five time slots from different signal environments, we demonstrate superb performance of the reconfigurable MD in comparison to the conventional nonreconfigurable MD in terms of the data receiving rate available in the LSA band at 2.3–2.4 GHz.

A Web-Based Integration Procedure for the Development of Reconfigurable Robotic Work-Cells

Directory of Open Access Journals (Sweden)

Paulo Ferreira

2013-07-01

Full Text Available Concepts related to the development of reconfigurable manufacturing systems (RMS and methodologies to provide the best practices in the processing industry and factory automation, such as system integration and web-based technology, are major issues in designing next-generation manufacturing systems (NGMS. Adaptable and integrable devices are crucial for the success of NGMS. In robotic cells the integration of manufacturing components is essential to accelerate system adaptability. Sensors, control architectures and communication technologies have contributed to achieving further agility in reconfigurable factories. In this work a web-based robotic cell integration procedure is proposed to aid the identification of reconfigurable issues and requirements. This methodology is applied to an industrial robot manipulator to enhance system flexibility towards the development of a reconfigurable robotic platform.

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

National Research Council Canada - National Science Library

Horiuchi, Timothy K; Krishnaprasad, P. S

2007-01-01

.... This includes multiple efforts related to a VLSI-based echolocation system being developed in one of our laboratories from algorithm development, bat flight data analysis, to VLSI circuit design...

Real-time FPGA architectures for computer vision

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2000-03-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

SDN-controlled topology-reconfigurable optical mobile fronthaul architecture for bidirectional CoMP and low latency inter-cell D2D in the 5G mobile era.

Science.gov (United States)

Cvijetic, Neda; Tanaka, Akihiro; Kanonakis, Konstantinos; Wang, Ting

2014-08-25

We demonstrate the first SDN-controlled optical topology-reconfigurable mobile fronthaul (MFH) architecture for bidirectional coordinated multipoint (CoMP) and low latency inter-cell device-to-device (D2D) connectivity in the 5G mobile networking era. SDN-based OpenFlow control is used to dynamically instantiate the CoMP and inter-cell D2D features as match/action combinations in control plane flow tables of software-defined optical and electrical switching elements. Dynamic re-configurability is thereby introduced into the optical MFH topology, while maintaining back-compatibility with legacy fiber deployments. 10 Gb/s peak rates with <7 μs back-to-back transmission latency and 29.6 dB total power budget are experimentally demonstrated, confirming the attractiveness of the new approach for optical MFH of future 5G mobile systems.

Multicore technology architecture, reconfiguration, and modeling

CERN Document Server

Qadri, Muhammad Yasir

2013-01-01

The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing. The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debu

Nano lasers in photonic VLSI

NARCIS (Netherlands)

Hill, M.T.; Oei, Y.S.; Smit, M.K.

2007-01-01

We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

An Embedded Reconfigurable Logic Module

Science.gov (United States)

Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

2002-01-01

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

Turbo decoder architecture for beyond-4G applications

CERN Document Server

Wong, Cheng-Chi

2013-01-01

This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respec

A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

Science.gov (United States)

Shimonomura, Kazuhiro; Yagi, Tetsuya

2005-07-01

In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

Remote hardware-reconfigurable robotic camera

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

2001-10-01

In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

Real-Time Algebraic Derivative Estimations Using a Novel Low-Cost Architecture Based on Reconfigurable Logic

Science.gov (United States)

Morales, Rafael; Rincón, Fernando; Gazzano, Julio Dondo; López, Juan Carlos

2014-01-01

Time derivative estimation of signals plays a very important role in several fields, such as signal processing and control engineering, just to name a few of them. For that purpose, a non-asymptotic algebraic procedure for the approximate estimation of the system states is used in this work. The method is based on results from differential algebra and furnishes some general formulae for the time derivatives of a measurable signal in which two algebraic derivative estimators run simultaneously, but in an overlapping fashion. The algebraic derivative algorithm presented in this paper is computed online and in real-time, offering high robustness properties with regard to corrupting noises, versatility and ease of implementation. Besides, in this work, we introduce a novel architecture to accelerate this algebraic derivative estimator using reconfigurable logic. The core of the algorithm is implemented in an FPGA, improving the speed of the system and achieving real-time performance. Finally, this work proposes a low-cost platform for the integration of hardware in the loop in MATLAB. PMID:24859033

Las Vegas is better than determinism in VLSI and distributed computing

DEFF Research Database (Denmark)

Mehlhorn, Kurt; Schmidt, Erik Meineche

1982-01-01

In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

International Nuclear Information System (INIS)

Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

Energy Technology Data Exchange (ETDEWEB)

Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

2005-01-01

A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

Lithography requirements in complex VLSI device fabrication

International Nuclear Information System (INIS)

Wilson, A.D.

1985-01-01

Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

Handbook of VLSI chip design and expert systems

CERN Document Server

Schwarz, A F

1993-01-01

Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

VLSI micro- and nanophotonics science, technology, and applications

CERN Document Server

Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

2011-01-01

Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

Science.gov (United States)

2010-10-01

spatial navigation in mammals. We have designed, fabricated, and are now testing a neuromorphic VLSI chip that implements a spike-based, attractor...Control Laws and Neuromorphic VLSI 5a. CONTRACT NUMBER 070402-7705 5b. GRANT NUMBER FA9550-07-1-0446 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S...implementations (custom Neuromorphic VLSI and robotics) we will apply important practical constraints that can lead to deeper insight into how and why efficient

Reconfigurable Model Execution in the OpenMDAO Framework

Science.gov (United States)

Hwang, John T.

2017-01-01

NASA's OpenMDAO framework facilitates constructing complex models and computing their derivatives for multidisciplinary design optimization. Decomposing a model into components that follow a prescribed interface enables OpenMDAO to assemble multidisciplinary derivatives from the component derivatives using what amounts to the adjoint method, direct method, chain rule, global sensitivity equations, or any combination thereof, using the MAUD architecture. OpenMDAO also handles the distribution of processors among the disciplines by hierarchically grouping the components, and it automates the data transfer between components that are on different processors. These features have made OpenMDAO useful for applications in aircraft design, satellite design, wind turbine design, and aircraft engine design, among others. This paper presents new algorithms for OpenMDAO that enable reconfigurable model execution. This concept refers to dynamically changing, during execution, one or more of: the variable sizes, solution algorithm, parallel load balancing, or set of variables-i.e., adding and removing components, perhaps to switch to a higher-fidelity sub-model. Any component can reconfigure at any point, even when running in parallel with other components, and the reconfiguration algorithm presented here performs the synchronized updates to all other components that are affected. A reconfigurable software framework for multidisciplinary design optimization enables new adaptive solvers, adaptive parallelization, and new applications such as gradient-based optimization with overset flow solvers and adaptive mesh refinement. Benchmarking results demonstrate the time savings for reconfiguration compared to setting up the model again from scratch, which can be significant in large-scale problems. Additionally, the new reconfigurability feature is applied to a mission profile optimization problem for commercial aircraft where both the parametrization of the mission profile and the

Design of a real-time open architecture controller for reconfigurable machine tool

CSIR Research Space (South Africa)

Masekamela, I

2008-06-01

Full Text Available requires appropriate business strategies and manufacturing technologies. More recently, the Reconfigurable Manufacturing System (RMS) concept was introduced to respond to this new market oriented manufacturing environment. In terms of design, RMS has a...

VLSI 'smart' I/O module development

Science.gov (United States)

Kirk, Dan

The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

Directory of Open Access Journals (Sweden)

Soundous Chairat

2017-05-01

Full Text Available This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI technology at 0.6 V and a 1.1 ns/bit latency per stage.

Dynamic Neural Fields as a Step Towards Cognitive Neuromorphic Architectures

Directory of Open Access Journals (Sweden)

Yulia eSandamirskaya

2014-01-01

Full Text Available Dynamic Field Theory (DFT is an established framework for modelling embodied cognition. In DFT, elementary cognitive functions such as memory formation, formation of grounded representations, attentional processes, decision making, adaptation, and learning emerge from neuronal dynamics. The basic computational element of this framework is a Dynamic Neural Field (DNF. Under constraints on the time-scale of the dynamics, the DNF is computationally equivalent to a soft winner-take-all (WTA network, which is considered one of the basic computational units in neuronal processing. Recently, it has been shown how a WTA network may be implemented in neuromorphic hardware, such as analogue Very Large Scale Integration (VLSI device. This paper leverages the relationship between DFT and soft WTA networks to systematically revise and integrate established DFT mechanisms that have previously been spread among different architectures. In addition, I also identify some novel computational and architectural mechanisms of DFT which may be implemented in neuromorphic VLSI devices using WTA networks as an intermediate computational layer. These specific mechanisms include the stabilization of working memory, the coupling of sensory systems to motor dynamics, intentionality, and autonomous learning. I further demonstrate how all these elements may be integrated into a unified architecture to generate behavior and autonomous learning.

R-GPU : A reconfigurable GPU architecture

NARCIS (Netherlands)

van den Braak, G.J.; Corporaal, H.

2016-01-01

Over the last decade, Graphics Processing Unit (GPU) architectures have evolved from a fixed-function graphics pipeline to a programmable, energy-efficient compute accelerator for massively parallel applications. The compute power arises from the GPU's Single Instruction/Multiple Threads

Control and Communication for a Secure and Reconfigurable Power Distribution System

Science.gov (United States)

Giacomoni, Anthony Michael

A major transformation is taking place throughout the electric power industry to overlay existing electric infrastructure with advanced sensing, communications, and control system technologies. This transformation to a smart grid promises to enhance system efficiency, increase system reliability, support the electrification of transportation, and provide customers with greater control over their electricity consumption. Upgrading control and communication systems for the end-to-end electric power grid, however, will present many new security challenges that must be dealt with before extensive deployment and implementation of these technologies can begin. In this dissertation, a comprehensive systems approach is taken to minimize and prevent cyber-physical disturbances to electric power distribution systems using sensing, communications, and control system technologies. To accomplish this task, an intelligent distributed secure control (IDSC) architecture is presented and validated in silico for distribution systems to provide greater adaptive protection, with the ability to proactively reconfigure, and rapidly respond to disturbances. Detailed descriptions of functionalities at each layer of the architecture as well as the whole system are provided. To compare the performance of the IDSC architecture with that of other control architectures, an original simulation methodology is developed. The simulation model integrates aspects of cyber-physical security, dynamic price and demand response, sensing, communications, intermittent distributed energy resources (DERs), and dynamic optimization and reconfiguration. Applying this comprehensive systems approach, performance results for the IEEE 123 node test feeder are simulated and analyzed. The results show the trade-offs between system reliability, operational constraints, and costs for several control architectures and optimization algorithms. Additional simulation results are also provided. In particular, the

Origami tubes with reconfigurable polygonal cross-sections.

Science.gov (United States)

Filipov, E T; Paulino, G H; Tachi, T

2016-01-01

Thin sheets can be assembled into origami tubes to create a variety of deployable, reconfigurable and mechanistically unique three-dimensional structures. We introduce and explore origami tubes with polygonal, translational symmetric cross-sections that can reconfigure into numerous geometries. The tubular structures satisfy the mathematical definitions for flat and rigid foldability, meaning that they can fully unfold from a flattened state with deformations occurring only at the fold lines. The tubes do not need to be straight and can be constructed to follow a non-linear curved line when deployed. The cross-section and kinematics of the tubular structures can be reprogrammed by changing the direction of folding at some folds. We discuss the variety of tubular structures that can be conceived and we show limitations that govern the geometric design. We quantify the global stiffness of the origami tubes through eigenvalue and structural analyses and highlight the mechanical characteristics of these systems. The two-scale nature of this work indicates that, from a local viewpoint, the cross-sections of the polygonal tubes are reconfigurable while, from a global viewpoint, deployable tubes of desired shapes are achieved. This class of tubes has potential applications ranging from pipes and micro-robotics to deployable architecture in buildings.

Origami tubes with reconfigurable polygonal cross-sections

Science.gov (United States)

Filipov, E. T.; Paulino, G. H.; Tachi, T.

2016-01-01

Thin sheets can be assembled into origami tubes to create a variety of deployable, reconfigurable and mechanistically unique three-dimensional structures. We introduce and explore origami tubes with polygonal, translational symmetric cross-sections that can reconfigure into numerous geometries. The tubular structures satisfy the mathematical definitions for flat and rigid foldability, meaning that they can fully unfold from a flattened state with deformations occurring only at the fold lines. The tubes do not need to be straight and can be constructed to follow a non-linear curved line when deployed. The cross-section and kinematics of the tubular structures can be reprogrammed by changing the direction of folding at some folds. We discuss the variety of tubular structures that can be conceived and we show limitations that govern the geometric design. We quantify the global stiffness of the origami tubes through eigenvalue and structural analyses and highlight the mechanical characteristics of these systems. The two-scale nature of this work indicates that, from a local viewpoint, the cross-sections of the polygonal tubes are reconfigurable while, from a global viewpoint, deployable tubes of desired shapes are achieved. This class of tubes has potential applications ranging from pipes and micro-robotics to deployable architecture in buildings. PMID:26997894

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

Science.gov (United States)

Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

2013-01-01

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation. PMID:24189331

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

Directory of Open Access Journals (Sweden)

Sheng-Ying Lai

2013-11-01

Full Text Available This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA and fuzzy C-means (FCM algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA. It is embedded in a System-on-Chip (SOC platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

Disruptive Logic Architectures and Technologies From Device to System Level

CERN Document Server

Gaillardon, Pierre-Emmanuel; Clermidy, Fabien

2012-01-01

This book discusses the opportunities offered by disruptive technologies to overcome the economical and physical limits currently faced by the electronics industry. It provides a new methodology for the fast evaluation of an emerging technology from an architectural perspective and discusses the implications from simple circuits to complex architectures. Several technologies are discussed, ranging from 3-D integration of devices (Phase Change Memories, Monolithic 3-D, Vertical NanoWires-based transistors) to dense 2-D arrangements (Double-Gate Carbon Nanotubes, Sublithographic Nanowires, Lithographic Crossbar arrangements). Novel architectural organizations, as well as the associated tools, are presented in order to explore this freshly opened design space. Describes a novel architectural organization for future reconfigurable systems; Includes a complete benchmarking toolflow for emerging technologies; Generalizes the description of reconfigurable circuits in terms of hierarchical levels; Assesses disruptive...

Emulation of Neural Networks on a Nanoscale Architecture

International Nuclear Information System (INIS)

Eshaghian-Wilner, Mary M; Friesz, Aaron; Khitun, Alex; Navab, Shiva; Parker, Alice C; Wang, Kang L; Zhou, Chongwu

2007-01-01

In this paper, we propose using a nanoscale spin-wave-based architecture for implementing neural networks. We show that this architecture can efficiently realize highly interconnected neural network models such as the Hopfield model. In our proposed architecture, no point-to-point interconnection is required, so unlike standard VLSI design, no fan-in/fan-out constraint limits the interconnectivity. Using spin-waves, each neuron could broadcast to all other neurons simultaneously and similarly a neuron could concurrently receive and process multiple data. Therefore in this architecture, the total weighted sum to each neuron can be computed by the sum of the values from all the incoming waves to that neuron. In addition, using the superposition property of waves, this computation can be done in O(1) time, and neurons can update their states quite rapidly

ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

Directory of Open Access Journals (Sweden)

V. I. Romanov

2016-01-01

Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

Software-defined reconfigurable microwave photonics processor.

Science.gov (United States)

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

Layered distributed architecture for plant automation

International Nuclear Information System (INIS)

Aravamuthan, G.; Verma, Yachika; Ranjan, Jyoti; Chachondia, Alka S.; Ganesh, G.

2005-01-01

The development of plant automation system and associated software remains one of the greatest challenges to the widespread implementation of highly adaptive re-configurable automation technology. This paper presents a layered distributed architecture for a plant automation system designed to support rapid reconfiguration and redeployment of automation components. The paper first presents evolution of automation architecture and their associated environment in the past few decades and then presents the concept of layered system architecture and the use of automation components to support the construction of a wide variety of automation system. It also highlights the role of standards and technology, which can be used in the development of automation components. We have attempted to adhere to open standards and technology for the development of automation component at a various layers. It also highlights the application of this concept in the development of an Operator Information System (OIS) for Advanced Heavy Water Reactor (AHWR). (author)

Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

CERN Document Server

2015-01-01

This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

Schematic Approach to Information Services Reconfiguration

Directory of Open Access Journals (Sweden)

Sabah Al-Fedaghi

2015-02-01

Full Text Available Information system change is concerned with deliberate modifications to an organization’s technical and organiza‐ tional subsystems that deal with information. Changes result in adjustments being made to the configuration of information systems that could have an impact on the operations of those systems. This paper examines the problem of interference between old configuration activi‐ ties, new configuration activities and reconfiguration activities that occur due to overlapping modes. The paper proposes a novel form of depicting and solving the problem based on a flow-based conceptualization in which a configuration can be viewed as a system of flow systems organized architecturally, described by their internal flows, and connected by external flows and triggering. This method of diagramming is applied to a complex case study involving the reconfiguration of an office workflow for order processing described in BPMN. The diagrams resulting from this method and the BPMN diagrams are then examined side by side. Accordingly, the conclusion is that a new high-level representation seems more system‐ atic as a foundation for building a conceptual schema of business processes.

The VLSI handbook

CERN Document Server

Chen, Wai-Kai

2007-01-01

Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

Computational Strategies for the Architectural Design of Bending Active Structures

DEFF Research Database (Denmark)

Tamke, Martin; Nicholas, Paul

2013-01-01

Active bending introduces a new level of integration into the design of architectural structures, and opens up new complexities for the architectural design process. In particular, the introduction of material variation reconfigures the design space. Through the precise specification...

Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

Science.gov (United States)

2007-03-31

IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

A parallel architecture for digital filtering using Fermat number transforms

Science.gov (United States)

Truong, T. K.; Reed, I. S.; Yeh, C.-S.; Shao, H. M.

1983-01-01

In this correspondence, a parallel architecture is developed to compute the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT). In particular, a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. The overlap-save method is generalized for the FNT to realize a digital filter of arbitrary length. The generalized overlap-save method alleviates the usual dynamic range limitation of FNT's of long transform lengths. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNT's of 128 points. Its architecture is regular, simple, and flexible, and therefore naturally suitable for VLSI implementation.

A second generation 50 Mbps VLSI level zero processing system prototype

Science.gov (United States)

Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

1994-01-01

Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

SACFIR: SDN-Based Application-Aware Centralized Adaptive Flow Iterative Reconfiguring Routing Protocol for WSNs.

Science.gov (United States)

Aslam, Muhammad; Hu, Xiaopeng; Wang, Fan

2017-12-13

Smart reconfiguration of a dynamic networking environment is offered by the central control of Software-Defined Networking (SDN). Centralized SDN-based management architectures are capable of retrieving global topology intelligence and decoupling the forwarding plane from the control plane. Routing protocols developed for conventional Wireless Sensor Networks (WSNs) utilize limited iterative reconfiguration methods to optimize environmental reporting. However, the challenging networking scenarios of WSNs involve a performance overhead due to constant periodic iterative reconfigurations. In this paper, we propose the SDN-based Application-aware Centralized adaptive Flow Iterative Reconfiguring (SACFIR) routing protocol with the centralized SDN iterative solver controller to maintain the load-balancing between flow reconfigurations and flow allocation cost. The proposed SACFIR's routing protocol offers a unique iterative path-selection algorithm, which initially computes suitable clustering based on residual resources at the control layer and then implements application-aware threshold-based multi-hop report transmissions on the forwarding plane. The operation of the SACFIR algorithm is centrally supervised by the SDN controller residing at the Base Station (BS). This paper extends SACFIR to SDN-based Application-aware Main-value Centralized adaptive Flow Iterative Reconfiguring (SAMCFIR) to establish both proactive and reactive reporting. The SAMCFIR transmission phase enables sensor nodes to trigger direct transmissions for main-value reports, while in the case of SACFIR, all reports follow computed routes. Our SDN-enabled proposed models adjust the reconfiguration period according to the traffic burden on sensor nodes, which results in heterogeneity awareness, load-balancing and application-specific reconfigurations of WSNs. Extensive experimental simulation-based results show that SACFIR and SAMCFIR yield the maximum scalability, network lifetime and stability

SACFIR: SDN-Based Application-Aware Centralized Adaptive Flow Iterative Reconfiguring Routing Protocol for WSNs

Directory of Open Access Journals (Sweden)

Muhammad Aslam

2017-12-01

Full Text Available Smart reconfiguration of a dynamic networking environment is offered by the central control of Software-Defined Networking (SDN. Centralized SDN-based management architectures are capable of retrieving global topology intelligence and decoupling the forwarding plane from the control plane. Routing protocols developed for conventional Wireless Sensor Networks (WSNs utilize limited iterative reconfiguration methods to optimize environmental reporting. However, the challenging networking scenarios of WSNs involve a performance overhead due to constant periodic iterative reconfigurations. In this paper, we propose the SDN-based Application-aware Centralized adaptive Flow Iterative Reconfiguring (SACFIR routing protocol with the centralized SDN iterative solver controller to maintain the load-balancing between flow reconfigurations and flow allocation cost. The proposed SACFIR’s routing protocol offers a unique iterative path-selection algorithm, which initially computes suitable clustering based on residual resources at the control layer and then implements application-aware threshold-based multi-hop report transmissions on the forwarding plane. The operation of the SACFIR algorithm is centrally supervised by the SDN controller residing at the Base Station (BS. This paper extends SACFIR to SDN-based Application-aware Main-value Centralized adaptive Flow Iterative Reconfiguring (SAMCFIR to establish both proactive and reactive reporting. The SAMCFIR transmission phase enables sensor nodes to trigger direct transmissions for main-value reports, while in the case of SACFIR, all reports follow computed routes. Our SDN-enabled proposed models adjust the reconfiguration period according to the traffic burden on sensor nodes, which results in heterogeneity awareness, load-balancing and application-specific reconfigurations of WSNs. Extensive experimental simulation-based results show that SACFIR and SAMCFIR yield the maximum scalability, network lifetime

Motion estimation for video coding efficient algorithms and architectures

CERN Document Server

Chakrabarti, Indrajit; Chatterjee, Sumit Kumar

2015-01-01

The need of video compression in the modern age of visual communication cannot be over-emphasized. This monograph will provide useful information to the postgraduate students and researchers who wish to work in the domain of VLSI design for video processing applications. In this book, one can find an in-depth discussion of several motion estimation algorithms and their VLSI implementation as conceived and developed by the authors. It records an account of research done involving fast three step search, successive elimination, one-bit transformation and its effective combination with diamond search and dynamic pixel truncation techniques. Two appendices provide a number of instances of proof of concept through Matlab and Verilog program segments. In this aspect, the book can be considered as first of its kind. The architectures have been developed with an eye to their applicability in everyday low-power handheld appliances including video camcorders and smartphones.

Sustainable, Reliable Mission-Systems Architecture

Science.gov (United States)

O'Neil, Graham; Orr, James K.; Watson, Steve

2007-01-01

A mission-systems architecture, based on a highly modular infrastructure utilizing: open-standards hardware and software interfaces as the enabling technology is essential for affordable and sustainable space exploration programs. This mission-systems architecture requires (a) robust communication between heterogeneous system, (b) high reliability, (c) minimal mission-to-mission reconfiguration, (d) affordable development, system integration, and verification of systems, and (e) minimal sustaining engineering. This paper proposes such an architecture. Lessons learned from the Space Shuttle program and Earthbound complex engineered system are applied to define the model. Technology projections reaching out 5 years are mde to refine model details.

A VLSI image processor via pseudo-mersenne transforms

International Nuclear Information System (INIS)

Sei, W.J.; Jagadeesh, J.M.

1986-01-01

The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

Synthesis of on-chip control circuits for mVLSI biochips

DEFF Research Database (Denmark)

Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

2017-01-01

them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

Emerging Applications for High K Materials in VLSI Technology

Science.gov (United States)

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Emerging Applications for High K Materials in VLSI Technology

Directory of Open Access Journals (Sweden)

Robert D. Clark

2014-04-01

Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Reconfigurable optical interconnection network for multimode optical fiber sensor arrays

Science.gov (United States)

Chen, R. T.; Robinson, D.; Lu, H.; Wang, M. R.; Jannson, T.; Baumbick, R.

1992-01-01

A single-source, single-detector architecture has been developed to implement a reconfigurable optical interconnection network multimode optical fiber sensor arrays. The network was realized by integrating LiNbO3 electrooptic (EO) gratings working at the Raman Na regime and a massive fan-out waveguide hologram (WH) working at the Bragg regime onto a multimode glass waveguide. The glass waveguide utilized the whole substrate as a guiding medium. A 1-to-59 massive waveguide fan-out was demonstrated using a WH operating at 514 nm. Measured diffraction efficiency of 59 percent was experimentally confirmed. Reconfigurability of the interconnection was carried out by generating an EO grating through an externally applied electric field. Unlike conventional single-mode integrated optical devices, the guided mode demonstrated has an azimuthal symmetry in mode profile which is the same as that of a fiber mode.

Harnessing VLSI System Design with EDA Tools

CERN Document Server

Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

2012-01-01

This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

Reconfigurable Charge Pump Circuit with Variable Pumping Frequency Scheme for Harvesting Solar Energy under Various Sunlight Intensities

Directory of Open Access Journals (Sweden)

Jeong Heon Kim

2014-01-01

Full Text Available We propose variable pumping frequency (VPF scheme which is merged with the previous reconfigurable charge pump (RCP circuit that can change its architecture according to a given sunlight condition. Here, merging the VPF scheme with the architecture reconfiguration can improve percentage output currents better by 21.4% and 22.4% than RCP circuit with the fixed pumping frequencies of 7 MHz and 15 MHz, respectively. Comparing the VPF scheme with real maximum power points (MPP, the VPF can deliver 91.9% of the maximum amount of output current to the load on average. In terms of the power and area overheads, the VPF scheme proposed in this paper consumes the power by 0.4% of the total power consumption and occupies the layout area by 1.61% of the total layout area.

CMOS VLSI Active-Pixel Sensor for Tracking

Science.gov (United States)

Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

2004-01-01

An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

Optical chirp z-transform processor with a simplified architecture.

Science.gov (United States)

Ngo, Nam Quoc

2014-12-29

Using a simplified chirp z-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp z-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.

Reconfigurable chaotic logic gates based on novel chaotic circuit

International Nuclear Information System (INIS)

Behnia, S.; Pazhotan, Z.; Ezzati, N.; Akhshani, A.

2014-01-01

Highlights: • A novel method for implementing logic gates based on chaotic maps is introduced. • The logic gates can be implemented without any changes in the threshold voltage. • The chaos-based logic gates may serve as basic components of future computing devices. - Abstract: The logical operations are one of the key issues in today’s computer architecture. Nowadays, there is a great interest in developing alternative ways to get the logic operations by chaos computing. In this paper, a novel implementation method of reconfigurable logic gates based on one-parameter families of chaotic maps is introduced. The special behavior of these chaotic maps can be utilized to provide same threshold voltage for all logic gates. However, there is a wide interval for choosing a control parameter for all reconfigurable logic gates. Furthermore, an experimental implementation of this nonlinear system is presented to demonstrate the robustness of computing capability of chaotic circuits

A wideband software reconfigurable modem

Science.gov (United States)

Turner, J. H., Jr.; Vickers, H.

A wideband modem is described which provides signal processing capability for four Lx-band signals employing QPSK, MSK and PPM waveforms and employs a software reconfigurable architecture for maximum system flexibility and graceful degradation. The current processor uses a 2901 and two 8086 microprocessors per channel and performs acquisition, tracking, and data demodulation for JITDS, GPS, IFF and TACAN systems. The next generation processor will be implemented using a VHSIC chip set employing a programmable complex array vector processor module, a GP computer module, customized gate array modules, and a digital array correlator. This integrated processor has application to a wide number of diverse system waveforms, and will bring the benefits of VHSIC technology insertion into avionic antijam communications systems.

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Reconfigurable Hardware for Compressing Hyperspectral Image Data

Science.gov (United States)

Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

2010-01-01

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

Modeling safety instrumented systems with MooN voting architectures addressing system reconfiguration for testing

International Nuclear Information System (INIS)

Torres-Echeverria, A.C.; Martorell, S.; Thompson, H.A.

2011-01-01

This paper addresses the modeling of probability of dangerous failure on demand and spurious trip rate of safety instrumented systems that include MooN voting redundancies in their architecture. MooN systems are a special case of k-out-of-n systems. The first part of the article is devoted to the development of a time-dependent probability of dangerous failure on demand model with capability of handling MooN systems. The model is able to model explicitly common cause failure and diagnostic coverage, as well as different test frequencies and strategies. It includes quantification of both detected and undetected failures, and puts emphasis on the quantification of common cause failure to the system probability of dangerous failure on demand as an additional component. In order to be able to accommodate changes in testing strategies, special treatment is devoted to the analysis of system reconfiguration (including common cause failure) during test of one of its components, what is then included in the model. Another model for spurious trip rate is also analyzed and extended under the same methodology in order to empower it with similar capabilities. These two models are powerful enough, but at the same time simple, to be suitable for handling of dependability measures in multi-objective optimization of both system design and test strategies for safety instrumented systems. The level of modeling detail considered permits compliance with the requirements of the standard IEC 61508. The two models are applied to brief case studies to demonstrate their effectiveness. The results obtained demonstrated that the first model is adequate to quantify time-dependent PFD of MooN systems during different system states (i.e. full operation, test and repair) and different MooN configurations, which values are averaged to obtain the PFD avg . Also, it was demonstrated that the second model is adequate to quantify STR including spurious trips induced by internal component failure and

Optimizing Vector-Quantization Processor Architecture for Intelligent Query-Search Applications

Science.gov (United States)

Xu, Huaiyu; Mita, Yoshio; Shibata, Tadashi

2002-04-01

The architecture of a very large scale integration (VLSI) vector-quantization processor (VQP) has been optimized to develop a general-purpose intelligent query-search agent. The agent performs a similarity-based search in a large-volume database. Although similarity-based search processing is computationally very expensive, latency-free searches have become possible due to the highly parallel maximum-likelihood search architecture of the VQP chip. Three architectures of the VQP chip have been studied and their performances are compared. In order to give reasonable searching results according to the different policies, the concept of penalty function has been introduced into the VQP. An E-commerce real-estate agency system has been developed using the VQP chip implemented in a field-programmable gate array (FPGA) and the effectiveness of such an agency system has been demonstrated.

Adaptive WTA with an analog VLSI neuromorphic learning chip.

Science.gov (United States)

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

Efficient Algorithm and Architecture of Critical-Band Transform for Low-Power Speech Applications

Directory of Open Access Journals (Sweden)

Gan Woon-Seng

2007-01-01

Full Text Available An efficient algorithm and its corresponding VLSI architecture for the critical-band transform (CBT are developed to approximate the critical-band filtering of the human ear. The CBT consists of a constant-bandwidth transform in the lower frequency range and a Brown constant- transform (CQT in the higher frequency range. The corresponding VLSI architecture is proposed to achieve significant power efficiency by reducing the computational complexity, using pipeline and parallel processing, and applying the supply voltage scaling technique. A 21-band Bark scale CBT processor with a sampling rate of 16 kHz is designed and simulated. Simulation results verify its suitability for performing short-time spectral analysis on speech. It has a better fitting on the human ear critical-band analysis, significantly fewer computations, and therefore is more energy-efficient than other methods. With a 0.35 m CMOS technology, it calculates a 160-point speech in 4.99 milliseconds at 234 kHz. The power dissipation is 15.6 W at 1.1 V. It achieves 82.1 power reduction as compared to a benchmark 256-point FFT processor.

Impact of reconfiguration period and photovoltaic penetration on distribution grid reconfiguration

DEFF Research Database (Denmark)

Chittur Ramaswamy, Parvathy; Deconinck, Geert; Pillai, Jayakrishnan Radhakrishna

2014-01-01

of reconfiguration and its impact on network losses in the context of time-varying load. Though reconfiguring a network reduces the losses, this paper calls for a comparison of number of switching vs. the loss reduction in order to decide the period of reconfiguration. This paper considers also the impact of varying...... photovoltaic (PV) penetration on the resulting optimal configuration. It validates the method of using a parameter namely minimum loss reduction parameter to avoid tedious computational efforts in finding the optimal configuration when an infinitesimal change in PV penetration occurs....

Roles and Self-Reconfigurable Robots

DEFF Research Database (Denmark)

Dvinge, Nicolai; Schultz, Ulrik Pagh; Christensen, David Johan

2007-01-01

A self-reconfigurable robot is a robotic device that can change its own shape. Self-reconfigurable robots are commonly built from multiple identical modules that can manipulate each other to change the shape of the robot. The robot can also perform tasks such as locomotion without changing shape......., significantly simplifying the task of programming self-reconfigurable robots. Our language fully supports programming the ATRON self-reconfigurable robot, and has been used to implement several controllers running both on the physical modules and in simulation.......A self-reconfigurable robot is a robotic device that can change its own shape. Self-reconfigurable robots are commonly built from multiple identical modules that can manipulate each other to change the shape of the robot. The robot can also perform tasks such as locomotion without changing shape....... Programming a modular, self-reconfigurable robot is however a complicated task: the robot is essentially a real-time, distributed embedded system, where control and communication paths often are tightly coupled to the current physical configuration of the robot. To facilitate the task of programming modular...

Trace-based post-silicon validation for VLSI circuits

CERN Document Server

Liu, Xiao

2014-01-01

This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

Applications of an architecture design and assessment system (ADAS)

Science.gov (United States)

Gray, F. Gail; Debrunner, Linda S.; White, Tennis S.

1988-01-01

A new Architecture Design and Assessment System (ADAS) tool package is introduced, and a range of possible applications is illustrated. ADAS was used to evaluate the performance of an advanced fault-tolerant computer architecture in a modern flight control application. Bottlenecks were identified and possible solutions suggested. The tool was also used to inject faults into the architecture and evaluate the synchronization algorithm, and improvements are suggested. Finally, ADAS was used as a front end research tool to aid in the design of reconfiguration algorithms in a distributed array architecture.

Software Architecture Evolution

Science.gov (United States)

2013-12-01

system’s major components occurring via a Java Message Service message bus [69]. This architecture was designed to promote loose coupling of soft- ware...play reconfiguration of the system. The components were Java -based and platform-independent; the interfaces by which they communicated were based on...The MPCS database, a MySQL database used for storing telemetry as well as some other information, such as logs and commanding data [68]. This

A software architecture for adaptive modular sensing systems.

Science.gov (United States)

Lyle, Andrew C; Naish, Michael D

2010-01-01

By combining a number of simple transducer modules, an arbitrarily complex sensing system may be produced to accommodate a wide range of applications. This work outlines a novel software architecture and knowledge representation scheme that has been developed to support this type of flexible and reconfigurable modular sensing system. Template algorithms are used to embed intelligence within each module. As modules are added or removed, the composite sensor is able to automatically determine its overall geometry and assume an appropriate collective identity. A virtual machine-based middleware layer runs on top of a real-time operating system with a pre-emptive kernel, enabling platform-independent template algorithms to be written once and run on any module, irrespective of its underlying hardware architecture. Applications that may benefit from easily reconfigurable modular sensing systems include flexible inspection, mobile robotics, surveillance, and space exploration.

Classification of Reconfiguration Resources and Lead Time for Reconfigurable Manufacturing Systems

NARCIS (Netherlands)

Ing. Erik Puik; Daniël Telgen; Leo van Moergestel; Darek Ceglarek

2014-01-01

From the article: Manufacturing technology can improve the turnover of a company if it enables fast market introduction for volume production. Reconfigurable equipment is developed to meet the growing demand for more agile production. Modular reconfiguration, defined as changing the structure of

A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams

Directory of Open Access Journals (Sweden)

Christophe Bobda

2006-10-01

Full Text Available This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.

A Dynamic Reconfigurable Hardware/Software Architecture for Object Tracking in Video Streams

Directory of Open Access Journals (Sweden)

Mühlbauer Felix

2006-01-01

Full Text Available This paper presents the design and implementation of a feature tracker on an embedded reconfigurable hardware system. Contrary to other works, the focus here is on the efficient hardware/software partitioning of the feature tracker algorithm, a viable data flow management, as well as an efficient use of memory and processor features. The implementation is done on a Xilinx Spartan 3 evaluation board and the results provided show the superiority of our implementation compared to the other works.

WDM Optical Access Network for Full-Duplex and Reconfigurable Capacity Assignment Based on PolMUX Technique

Directory of Open Access Journals (Sweden)

Jose Mora

2014-12-01

Full Text Available We present a novel bidirectional WDM-based optical access network featuring reconfigurable capacity assignment. The architecture relies on the PolMUX technique allowing a compact, flexible, and bandwidth-efficient router in addition to source-free ONUs and color-less ONUs for cost/complexity minimization. Moreover, the centralized architecture contemplates remote management and control of polarization. High-quality transmission of digital signals is demonstrated through different routing scenarios where all channels are dynamically assigned in both downlink and uplink directions.

A Knowledge Based Approach to VLSI CAD

Science.gov (United States)

1983-09-01

Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

A neuromorphic VLSI device for implementing 2-D selective attention systems.

Science.gov (United States)

Indiveri, G

2001-01-01

Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Characterization of robotics parallel algorithms and mapping onto a reconfigurable SIMD machine

Science.gov (United States)

Lee, C. S. G.; Lin, C. T.

1989-01-01

The kinematics, dynamics, Jacobian, and their corresponding inverse computations are six essential problems in the control of robot manipulators. Efficient parallel algorithms for these computations are discussed and analyzed. Their characteristics are identified and a scheme on the mapping of these algorithms to a reconfigurable parallel architecture is presented. Based on the characteristics including type of parallelism, degree of parallelism, uniformity of the operations, fundamental operations, data dependencies, and communication requirement, it is shown that most of the algorithms for robotic computations possess highly regular properties and some common structures, especially the linear recursive structure. Moreover, they are well-suited to be implemented on a single-instruction-stream multiple-data-stream (SIMD) computer with reconfigurable interconnection network. The model of a reconfigurable dual network SIMD machine with internal direct feedback is introduced. A systematic procedure internal direct feedback is introduced. A systematic procedure to map these computations to the proposed machine is presented. A new scheduling problem for SIMD machines is investigated and a heuristic algorithm, called neighborhood scheduling, that reorders the processing sequence of subtasks to reduce the communication time is described. Mapping results of a benchmark algorithm are illustrated and discussed.

Advances in Reconfigurable Mechanisms and Robots I

CERN Document Server

Zoppi, Matteo; Kong, Xianwen

2012-01-01

Advances in Reconfigurable Mechanisms and Robots I provides a selection of key papers presented in The Second ASME/IFToMM International Conference on Reconfigurable Mechanisms and Robots (ReMAR 2012) held on 9th -11th  July 2012 in Tianjin, China. This ongoing series of conferences will be covered in this ongoing collection of books.   A total of seventy-eight papers are divided into seven parts to cover the topology, kinematics and design of reconfigurable mechanisms with the reconfiguration theory, analysis and synthesis, and present the current research and development in the field of reconfigurable mechanisms including reconfigurable parallel mechanisms. In this aspect, the recent study and development of reconfigurable robots are further presented with the analysis and design and with their control and development. The bio-inspired mechanisms and subsequent reconfiguration are explored in the challenging fields of rehabilitation and minimally invasive surgery. Advances in Reconfigurable Mechanisms and ...

Advanced symbolic analysis for VLSI systems methods and applications

CERN Document Server

Shi, Guoyong; Tlelo Cuautle, Esteban

2014-01-01

This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

A Software Architecture for Adaptive Modular Sensing Systems

Directory of Open Access Journals (Sweden)

Andrew C. Lyle

2010-08-01

Full Text Available By combining a number of simple transducer modules, an arbitrarily complex sensing system may be produced to accommodate a wide range of applications. This work outlines a novel software architecture and knowledge representation scheme that has been developed to support this type of flexible and reconfigurable modular sensing system. Template algorithms are used to embed intelligence within each module. As modules are added or removed, the composite sensor is able to automatically determine its overall geometry and assume an appropriate collective identity. A virtual machine-based middleware layer runs on top of a real-time operating system with a pre-emptive kernel, enabling platform-independent template algorithms to be written once and run on any module, irrespective of its underlying hardware architecture. Applications that may benefit from easily reconfigurable modular sensing systems include flexible inspection, mobile robotics, surveillance, and space exploration.

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Introduction to Reconfigurable Supercomputing

CERN Document Server

Lanzagorta, Marco; Rosenberg, Robert

2010-01-01

This book covers technologies, applications, tools, languages, procedures, advantages, and disadvantages of reconfigurable supercomputing using Field Programmable Gate Arrays (FPGAs). The target audience is the community of users of High Performance Computers (HPe who may benefit from porting their applications into a reconfigurable environment. As such, this book is intended to guide the HPC user through the many algorithmic considerations, hardware alternatives, usability issues, programming languages, and design tools that need to be understood before embarking on the creation of reconfigur

Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

CERN Document Server

Williams, John

2008-01-01

This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

Nested Reconfigurable Robots: Theory, Design, and Realization

Directory of Open Access Journals (Sweden)

Ning Tan

2015-07-01

Full Text Available Rather than the conventional classification method, we propose to divide modular and reconfigurable robots into intra-, inter-, and nested reconfigurations. We suggest designing the robot with nested reconfigurability, which utilizes individual robots with intra-reconfigurability capable of combining with other homogeneous/heterogeneous robots (inter-reconfigurability. The objective of this approach is to generate more complex morphologies for performing specific tasks that are far from the capabilities of a single module or to respond to programmable assembly requirements. In this paper, we discuss the theory, concept, and initial mechanical design of Hinged-Tetro, a self-reconfigurable module conceived for the study of nested reconfiguration. Hinged-Tetro is a mobile robot that uses the principle of hinged dissection of polyominoes to transform itself into any of the seven one-sided tetrominoes in a straightforward way. The robot can also combine with other modules for shaping complex structures or giving rise to a robot with new capabilities. Finally, the validation experiments verify the nested reconfigurability of Hinged-Tetro. Extensive tests and analyses of intra-reconfiguration are provided in terms of energy and time consumptions. Experiments using two robots validate the inter-reconfigur ability of the proposed module.

Resource Allocation for A Mobile Application Oriented Architecture

NARCIS (Netherlands)

Guo, Y.; Smit, Gerardus Johannes Maria; Lu, W.W.; Xie, X.

2005-01-01

A Montium is a coarse-grained reconfigurable architecture designed by the CADTES group of the University of Twente for mobile applications. This paper presents a resource allocation method to allocate variables to storage places and to schedule data movements for the Montium. The resource allocation

Operating System for Runtime Reconfigurable Multiprocessor Systems

Directory of Open Access Journals (Sweden)

Diana Göhringer

2011-01-01

Full Text Available Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip. Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System, which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.

Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

Energy Technology Data Exchange (ETDEWEB)

Zhang, B

1999-07-01

This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

Numerical analysis of electromigration in thin film VLSI interconnections

NARCIS (Netherlands)

Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

1995-01-01

Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

SpaceWire model development technology for satellite architecture.

Energy Technology Data Exchange (ETDEWEB)

Eldridge, John M.; Leemaster, Jacob Edward; Van Leeuwen, Brian P.

2011-09-01

Packet switched data communications networks that use distributed processing architectures have the potential to simplify the design and development of new, increasingly more sophisticated satellite payloads. In addition, the use of reconfigurable logic may reduce the amount of redundant hardware required in space-based applications without sacrificing reliability. These concepts were studied using software modeling and simulation, and the results are presented in this report. Models of the commercially available, packet switched data interconnect SpaceWire protocol were developed and used to create network simulations of data networks containing reconfigurable logic with traffic flows for timing system distribution.

Reconfigurable network processing platforms

NARCIS (Netherlands)

Kachris, C.

2007-01-01

This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network

Heavy ion tests on programmable VLSI

International Nuclear Information System (INIS)

Provost-Grellier, A.

1989-11-01

The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

Reconfigurable Computing

CERN Document Server

Cardoso, Joao MP

2011-01-01

As the complexity of modern embedded systems increases, it becomes less practical to design monolithic processing platforms. As a result, reconfigurable computing is being adopted widely for more flexible design. Reconfigurable Computers offer the spatial parallelism and fine-grained customizability of application-specific circuits with the postfabrication programmability of software. To make the most of this unique combination of performance and flexibility, designers need to be aware of both hardware and software issues. FPGA users must think not only about the gates needed to perform a comp

Reconfiguration of distribution nets

International Nuclear Information System (INIS)

Latorre Bayona, Gerardo; Angarita Marquez, Jorge Luis

2000-01-01

Starting of the location of the reconfiguration problem inside the context of the operation of distribution nets, of the quality indicators definition and of the presentation of the alternatives more used for reduction of technical losses, they are related diverse reconfiguration methodologies proposed in the technical literature, pointing out their three principals limitations; also are presents the results of lost obtained starting from simulation works carried out in distribution circuits of the ESSA ESP, which permitting to postulate the reconfiguration of nets like an excellent alternative to reduce technical losses

The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

International Nuclear Information System (INIS)

Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

1993-01-01

An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

Science.gov (United States)

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

2015-01-12

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

A First Step Towards High-Level Cost Models for the Implementation of SDRs on Multiprocessing Reconfigurable Systems

DEFF Research Database (Denmark)

Le Moullec, Yannick

2011-01-01

-In-Progress paper we introduce our set of high-level estimation models for Area-Time costs of applications mapped onto FPGA-based multiprocessing reconfigurable architectures. In particular, we suggest models for static and dynamic implementations, taking various internal and external architectural elements...... into account. We believe that such models could be used for rapidly comparing implementation alternatives at a high level of abstraction and for guiding the designer during the (pre)analysis phase of the design flow for the implementation of e.g. SDR platforms....

Design of two easily-testable VLSI array multipliers

Energy Technology Data Exchange (ETDEWEB)

Ferguson, J.; Shen, J.P.

1983-01-01

Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

Direct kinematics solution architectures for industrial robot manipulators: Bit-serial versus parallel

Science.gov (United States)

Lee, J.; Kim, K.

1991-01-01

A Very Large Scale Integration (VLSI) architecture for robot direct kinematic computation suitable for industrial robot manipulators was investigated. The Denavit-Hartenberg transformations are reviewed to exploit a proper processing element, namely an augmented CORDIC. Specifically, two distinct implementations are elaborated on, such as the bit-serial and parallel. Performance of each scheme is analyzed with respect to the time to compute one location of the end-effector of a 6-links manipulator, and the number of transistors required.

Direct kinematics solution architectures for industrial robot manipulators: Bit-serial versus parallel

Science.gov (United States)

Lee, J.; Kim, K.

A Very Large Scale Integration (VLSI) architecture for robot direct kinematic computation suitable for industrial robot manipulators was investigated. The Denavit-Hartenberg transformations are reviewed to exploit a proper processing element, namely an augmented CORDIC. Specifically, two distinct implementations are elaborated on, such as the bit-serial and parallel. Performance of each scheme is analyzed with respect to the time to compute one location of the end-effector of a 6-links manipulator, and the number of transistors required.

Tabu Search-based Synthesis of Digital Microfluidic Biochips with Dynamically Reconfigurable Non-rectangular Devices

DEFF Research Database (Denmark)

Maftei, Elena; Pop, Paul; Madsen, Jan

2010-01-01

they are highly reconfigurable and scalable. A digital biochip is composed of a two-dimensional array of cells, together with reservoirs for storing the samples and reagents. Several adjacent cells are dynamically grouped to form a virtual device, on which operations are performed. So far, researchers have...... assumed that throughout its execution, an operation is performed on a rectangular virtual device, whose position remains fixed. However, during the execution of an operation, the virtual device can be reconfigured to occupy a different group of cells on the array, forming any shape, not necessarily...... rectangular. In this paper, we present a Tabu Search metaheuristic for the synthesis of digital microfluidic biochips, which, starting from a biochemical application and a given biochip architecture, determines the allocation, resource binding, scheduling and placement of the operations in the application...

Hardware And Software Architectures For Reconfigurable Time-Critical Control Tasks

Directory of Open Access Journals (Sweden)

Adam Piłat

2007-01-01

Full Text Available The most popular configuration of the controlled laboratory test-rigs is the personalcomputer (PC equipped with the I/O board. The dedicated software components allowsto conduct a wide range of user-defined tasks. The typical configuration functionality canbe customized by PC hardware components and their programmable reconfiguration. Thenext step in the automatic control system design is the embedded solution. Usually, thedesign process of the embedded control system is supported by the high-level software. Thededicated programming tools support multitasking property of the microcontroller by selectionof different sampling frequencies of algorithm blocks. In this case the multi-layer andmultitasking control strategy can be realized on the chip. The proposed solutions implementrapid prototyping approach. The available toolkits and device drivers integrate system-leveldesign environment and the real-time application software, transferring the functionality ofMATLAB/Simulink programs to PCs or microcontrolers application environment.

Rapidly Re-Configurable Flight Simulator Tools for Crew Vehicle Integration Research and Design

Science.gov (United States)

Pritchett, Amy R.

2002-01-01

While simulation is a valuable research and design tool, the time and difficulty required to create new simulations (or re-use existing simulations) often limits their application. This report describes the design of the software architecture for the Reconfigurable Flight Simulator (RFS), which provides a robust simulation framework that allows the simulator to fulfill multiple research and development goals. The core of the architecture provides the interface standards for simulation components, registers and initializes components, and handles the communication between simulation components. The simulation components are each a pre-compiled library 'plugin' module. This modularity allows independent development and sharing of individual simulation components. Additional interfaces can be provided through the use of Object Data/Method Extensions (OD/ME). RFS provides a programmable run-time environment for real-time access and manipulation, and has networking capabilities using the High Level Architecture (HLA).

Applications of VLSI circuits to medical imaging

International Nuclear Information System (INIS)

O'Donnell, M.

1988-01-01

In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

An Automated Test Framework for Experimenting with Stochastic Behavior in Reconfigurable Logic

DEFF Research Database (Denmark)

Birklykke, Alex Aaen; Le Moullec, Yannick; Alminde, Lars

2012-01-01

In this paper, we present an automated test frame- work for the characterization of stochastic behavior in logic circuits. The framework is intended as a platform for experimenting with and providing statistics on digital architectures given behavioral uncertainties at the gate-level. As an exper......In this paper, we present an automated test frame- work for the characterization of stochastic behavior in logic circuits. The framework is intended as a platform for experimenting with and providing statistics on digital architectures given behavioral uncertainties at the gate...... block subject to voltage/frequency scaling and Vdd -noise. The framework provides easy interfacing with laboratory equipment, design of experiment capabilities and automatic test execution, thus providing a powerful tool for characterizing stochastic behavior in reconfigurable logic....

Study of heterogeneous and reconfigurable architectures in the communication domain

Science.gov (United States)

Feldkaemper, H. T.; Blume, H.; Noll, T. G.

2003-05-01

One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

Implementing Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

NARCIS (Netherlands)

Rivaton, Arnaud; Quevremont, Jérôme; Zhang, Q.; Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Nurmi, J.; Takala, J.; Hamalainen, T.D.

2005-01-01

To improve power figures of a dual ARM9 RISC core architecture targeting low-power digital broadcasting applications, the addition of a coarse-grain architecture is considered. This paper introduces two of these structures: PACT's XPP technology and the Montium, developed by the University of

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

DEFF Research Database (Denmark)

Stensgaard, Mikkel Bystrup; Sparsø, Jens

2008-01-01

links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based...

MEMS-Reconfigurable Metamaterials and Antenna Applications

Directory of Open Access Journals (Sweden)

Tomislav Debogovic

2014-01-01

Full Text Available This paper reviews some of our contributions to reconfigurable metamaterials, where dynamic control is enabled by microelectromechanical systems (MEMS technology. First, we show reconfigurable composite right-/left-handed transmission lines (CRLH-TLs having state of the art phase velocity variation and loss, thereby enabling efficient reconfigurable phase shifters and leaky-wave antennas (LWA. Second, we present very low loss metasurface designs with reconfigurable reflection properties, applicable in reflectarrays and partially reflective surface (PRS antennas. All the presented devices have been fabricated and experimentally validated. They operate in X- and Ku-bands.

Dynamic Reconfiguration in Planetary Exploration

DEFF Research Database (Denmark)

Cohn, Marisa

2014-01-01

In taking into account the ways in which material and social realms are constitutively entangled within organizations, it is rhetorically tempting to say that technologies and social structures reconfigure each other. But what does it mean to reconfigure? How does one "figure" the other and how do...... we fully embrace a mutually constitutive relationship when examining fluid relations? This paper delves into these questions by exploring how physical, social, material, technological, and organizational arrangements dynamically reconfigure each other in the duration of organizational practice. Using...... be gained by focusing attention on the dynamic reconfigurations between social and material realms. In so doing, we call attention to the ways in which current sociomaterial perspectives have difficulty articulating the shifting, figural, asymmetric and dynamic negotiations between people, social structures...

Architecture and program structures for a special purpose finite element computer

Energy Technology Data Exchange (ETDEWEB)

Norrie, D.H.; Norrie, C.W.

1983-01-01

The development of very large scale integration (VLSI) has made special-purpose computers economically possible. With such a machine, the loss of flexibility compared with a general-purpose computer can be offset by the increased speed which can be obtained by tailoring the architecture to the particular problem or class of problem. The first kind of special-purpose machine has its architecture modelled on the physical structure of the problem and the second kind has its design tailored to the computational algorithm used. The parallel finite element machine (PARFEM) being designed at the University of Calgary for the solution of finite element problems is of the second kind. Its conceptual design is described and progress to date outlined. 14 references.

High performance VLSI telemetry data systems

Science.gov (United States)

Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

1990-01-01

NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

Science.gov (United States)

Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

2011-09-01

Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

Grasp planning for a reconfigurable parallel robot with an underactuated arm structure

Directory of Open Access Journals (Sweden)

M. Riedel

2010-12-01

Full Text Available In this paper, a novel approach of grasp planning is applied to find out the appropriate grasp points for a reconfigurable parallel robot called PARAGRIP (Parallel Gripping. This new handling system is able to manipulate objects in the six-dimensional Cartesian space by several robotic arms using only six actuated joints. After grasping, the contact elements at the end of the underactuated arm mechanisms are connected to the object which forms a closed loop mechanism similar to the architecture of parallel manipulators. As the mounting and grasp points of the arms can easily be changed, the manipulator can be reconfigured to match the user's preferences and needs. This paper raises the question, how and where these grasp points are to be placed on the object to perform well for a certain manipulation task.

This paper was presented at the IFToMM/ASME International Workshop on Underactuated Grasping (UG2010, 19 August 2010, Montréal, Canada.

Study of heterogeneous and reconfigurable architectures in the communication domain

Directory of Open Access Journals (Sweden)

H. T. Feldkaemper

2003-01-01

Full Text Available One of the most challenging design issues for next generations of (mobile communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC. For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

VLSI top-down design based on the separation of hierarchies

NARCIS (Netherlands)

Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

1986-01-01

Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

VLSI Design with Alliance Free CAD Tools: an Implementation Example

Directory of Open Access Journals (Sweden)

Chávez-Bracamontes Ramón

2015-07-01

Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

Harness: Heterogeneous Adaptable Reconfigurable Networked Systems -- U.S. Department of Energy Grant DE-FG02-99ER25379 Final Project Report

Energy Technology Data Exchange (ETDEWEB)

Vaidy Sunderam

2003-07-02

Issues in reconfigurability and adaptability in heterogeneous distributed systems for high-performance computing are the focus of the work funded by this grant. Our efforts are part of an ongoing research project in metacomputing and are a follow on to the DOE funded PVM system that has witnessed over a decade of use at numerous institutions worldwide. The current project, termed Harness, investigates novel methodologies and tools for distributed metacomputing, focusing on dynamically reconfigurable software frameworks. During the first phase, we defined the metacomputing architecture embodied in Harness and developed prototype subsystems as proof of concept exercises. Subsequently, we designed and developed a complete software framework manifesting the Harness architecture, and also developed several tools and subsystems that demonstrated the viability and effectiveness of our proposed model for next generation metacomputing. We then used this substrate to emulate multiple programming environments on Harness, and conducted performance evaluation and tuning exercises. The main research results from these efforts include the establishment of software metacomputing systems as viable and cost-effective alternatives to MPPs; the demonstration of dynamic and reconfigurable platforms as effective methods of tailoring parallel computing environments; the development of methodologies to construct plugin modules for component-based distributed systems; contributions to performance modeling and optimization in emulated software environments; and software architectures for multi- and mixed-paradigm parallel distributed computing. Details and specifics on these and other results have been reported in numerous publications, and are manifested in software systems, all of which may be accessed at or via the website http://www.mathcs.emory.edu/harness/

SABRE: a bio-inspired fault-tolerant electronic architecture

International Nuclear Information System (INIS)

Bremner, P; Samie, M; Dragffy, G; Pipe, A G; Liu, Y; Tempesti, G; Timmis, J; Tyrrell, A M

2013-01-01

As electronic devices become increasingly complex, ensuring their reliable, fault-free operation is becoming correspondingly more challenging. It can be observed that, in spite of their complexity, biological systems are highly reliable and fault tolerant. Hence, we are motivated to take inspiration for biological systems in the design of electronic ones. In SABRE (self-healing cellular architectures for biologically inspired highly reliable electronic systems), we have designed a bio-inspired fault-tolerant hierarchical architecture for this purpose. As in biology, the foundation for the whole system is cellular in nature, with each cell able to detect faults in its operation and trigger intra-cellular or extra-cellular repair as required. At the next level in the hierarchy, arrays of cells are configured and controlled as function units in a transport triggered architecture (TTA), which is able to perform partial-dynamic reconfiguration to rectify problems that cannot be solved at the cellular level. Each TTA is, in turn, part of a larger multi-processor system which employs coarser grain reconfiguration to tolerate faults that cause a processor to fail. In this paper, we describe the details of operation of each layer of the SABRE hierarchy, and how these layers interact to provide a high systemic level of fault tolerance. (paper)

A dynamically reconfigurable logic cell: from artificial neural networks to quantum-dot cellular automata

Science.gov (United States)

Naqvi, Syed Rameez; Akram, Tallha; Iqbal, Saba; Haider, Sajjad Ali; Kamran, Muhammad; Muhammad, Nazeer

2018-02-01

Considering the lack of optimization support for Quantum-dot Cellular Automata, we propose a dynamically reconfigurable logic cell capable of implementing various logic operations by means of artificial neural networks. The cell can be reconfigured to any 2-input combinational logic gate by altering the strength of connections, called weights and biases. We demonstrate how these cells may appositely be organized to perform multi-bit arithmetic and logic operations. The proposed work is important in that it gives a standard implementation of an 8-bit arithmetic and logic unit for quantum-dot cellular automata with minimal area and latency overhead. We also compare the proposed design with a few existing arithmetic and logic units, and show that it is more area efficient than any equivalent available in literature. Furthermore, the design is adaptable to 16, 32, and 64 bit architectures.

Reconfigurable metamaterials for terahertz wave manipulation

Science.gov (United States)

Hashemi, Mohammed R.; Cakmakyapan, Semih; Jarrahi, Mona

2017-09-01

Reconfigurable metamaterials have emerged as promising platforms for manipulating the spectral and spatial properties of terahertz waves without being limited by the characteristics of naturally existing materials. Here, we present a comprehensive overview of various types of reconfigurable metamaterials that are utilized to manipulate the intensity, phase, polarization, and propagation direction of terahertz waves. We discuss various reconfiguration mechanisms based on optical, electrical, thermal, and mechanical stimuli while using semiconductors, superconductors, phase-change materials, graphene, and electromechanical structures. The advantages and disadvantages of different reconfigurable metamaterial designs in terms of modulation efficiency, modulation bandwidth, modulation speed, and system complexity are discussed in detail.

High-speed architecture for the decoding of trellis-coded modulation

Science.gov (United States)

Osborne, William P.

1992-01-01

Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

Symmetric reconfigurable capacity assignment in a bidirectional DWDM access network.

Science.gov (United States)

Ortega, Beatriz; Mora, José; Puerto, Gustavo; Capmany, José

2007-12-10

This paper presents a novel architecture for DWDM bidirectional access networks providing symmetric dynamic capacity allocation for both downlink and uplink signals. A foldback arrayed waveguide grating incorporating an optical switch enables the experimental demonstration of flexible assignment of multiservice capacity. Different analog and digital services, such as CATV, 10 GHz-tone, 155Mb/s PRBS and UMTS signals have been transmitted in order to successfully test the system performance under different scenarios of total capacity distribution from the Central Station to different Base Stations with two reconfigurable extra channels for each down and upstream direction.

Development of Radhard VLSI electronics for SSC calorimeters

International Nuclear Information System (INIS)

Dawson, J.W.; Nodulman, L.J.

1989-01-01

A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

International Nuclear Information System (INIS)

Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

2016-01-01

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

Energy Technology Data Exchange (ETDEWEB)

Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

2014-01-31

The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

Science.gov (United States)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Implementing Workflow Reconfiguration in WS-BPEL

DEFF Research Database (Denmark)

Mazzara, Manuel; Dragoni, Nicola; Zhou, Mu

2012-01-01

This paper investigates the problem of dynamic reconfiguration by means of a workflow-based case study used for discussion. We state the requirements on a system implementing the workflow and its reconfiguration, and we describe the system’s design in BPMN. WS-BPEL, a language that would not natu......This paper investigates the problem of dynamic reconfiguration by means of a workflow-based case study used for discussion. We state the requirements on a system implementing the workflow and its reconfiguration, and we describe the system’s design in BPMN. WS-BPEL, a language that would...... not naturally support dynamic change, is used as a target for implementation. The WS-BPEL recovery framework is here exploited to implement the reconfiguration using principles derived from previous research in process algebra and two mappings from BPMN to WS-BPEL are presented, one automatic and only mostly...

A Survey on FPGA-Based Sensor Systems: Towards Intelligent and Reconfigurable Low-Power Sensors for Computer Vision, Control and Signal Processing

Directory of Open Access Journals (Sweden)

Gabriel J. García

2014-03-01

Full Text Available The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc., reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

A survey on FPGA-based sensor systems: towards intelligent and reconfigurable low-power sensors for computer vision, control and signal processing.

Science.gov (United States)

García, Gabriel J; Jara, Carlos A; Pomares, Jorge; Alabdo, Aiman; Poggi, Lucas M; Torres, Fernando

2014-03-31

The current trend in the evolution of sensor systems seeks ways to provide more accuracy and resolution, while at the same time decreasing the size and power consumption. The use of Field Programmable Gate Arrays (FPGAs) provides specific reprogrammable hardware technology that can be properly exploited to obtain a reconfigurable sensor system. This adaptation capability enables the implementation of complex applications using the partial reconfigurability at a very low-power consumption. For highly demanding tasks FPGAs have been favored due to the high efficiency provided by their architectural flexibility (parallelism, on-chip memory, etc.), reconfigurability and superb performance in the development of algorithms. FPGAs have improved the performance of sensor systems and have triggered a clear increase in their use in new fields of application. A new generation of smarter, reconfigurable and lower power consumption sensors is being developed in Spain based on FPGAs. In this paper, a review of these developments is presented, describing as well the FPGA technologies employed by the different research groups and providing an overview of future research within this field.

Space-Based Reconfigurable Software Defined Radio Test Bed Aboard International Space Station

Science.gov (United States)

Reinhart, Richard C.; Lux, James P.

2014-01-01

The National Aeronautical and Space Administration (NASA) recently launched a new software defined radio research test bed to the International Space Station. The test bed, sponsored by the Space Communications and Navigation (SCaN) Office within NASA is referred to as the SCaN Testbed. The SCaN Testbed is a highly capable communications system, composed of three software defined radios, integrated into a flight system, and mounted to the truss of the International Space Station. Software defined radios offer the future promise of in-flight reconfigurability, autonomy, and eventually cognitive operation. The adoption of software defined radios offers space missions a new way to develop and operate space transceivers for communications and navigation. Reconfigurable or software defined radios with communications and navigation functions implemented in software or VHDL (Very High Speed Hardware Description Language) provide the capability to change the functionality of the radio during development or after launch. The ability to change the operating characteristics of a radio through software once deployed to space offers the flexibility to adapt to new science opportunities, recover from anomalies within the science payload or communication system, and potentially reduce development cost and risk by adapting generic space platforms to meet specific mission requirements. The software defined radios on the SCaN Testbed are each compliant to NASA's Space Telecommunications Radio System (STRS) Architecture. The STRS Architecture is an open, non-proprietary architecture that defines interfaces for the connections between radio components. It provides an operating environment to abstract the communication waveform application from the underlying platform specific hardware such as digital-to-analog converters, analog-to-digital converters, oscillators, RF attenuators, automatic gain control circuits, FPGAs, general-purpose processors, etc. and the interconnections among

Security Policy for a Generic Space Exploration Communication Network Architecture

Science.gov (United States)

Ivancic, William D.; Sheehe, Charles J.; Vaden, Karl R.

2016-01-01

This document is one of three. It describes various security mechanisms and a security policy profile for a generic space-based communication architecture. Two other documents accompany this document- an Operations Concept (OpsCon) and a communication architecture document. The OpsCon should be read first followed by the security policy profile described by this document and then the architecture document. The overall goal is to design a generic space exploration communication network architecture that is affordable, deployable, maintainable, securable, evolvable, reliable, and adaptable. The architecture should also require limited reconfiguration throughout system development and deployment. System deployment includes subsystem development in a factory setting, system integration in a laboratory setting, launch preparation, launch, and deployment and operation in space.

Word-serial Architectures for Filtering and Variable Rate Decimation

Directory of Open Access Journals (Sweden)

Eugene Grayver

2002-01-01

Full Text Available A new flexible architecture is proposed for word-serial filtering and variable rate decimation/interpolation. The architecture is targeted for low power applications requiring medium to low data rate and is ideally suited for implementation on either an ASIC or an FPGA. It combines the small size and low power of an ASIC with the programmability and flexibility of a DSP. An efficient memory addressing scheme eliminates the need for power hungry shift registers and allows full reconfiguration. The decimation ratio, filter length and filter coefficients can all be changed in real time. The architecture takes advantage of coefficient symmetries in linear phase filters and in polyphase components.

Evolution of the Milieu Approach for Software Development for the Polymorphous Computing Architecture Program

National Research Council Canada - National Science Library

Dandass, Yoginder

2004-01-01

A key goal of the DARPA Polymorphous Computing Architectures (PCA) program is to develop reactive closed-loop systems that are capable of being dynamically reconfigured in order to respond to changing mission scenarios...

VLSI Design of Trusted Virtual Sensors

Directory of Open Access Journals (Sweden)

Macarena C. Martínez-Rodríguez

2018-01-01

Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

VLSI Design of Trusted Virtual Sensors.

Science.gov (United States)

Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

2018-01-25

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

1.25 Gbit/s bidirectional link in an access network employing a reconfigurable optical add/drop multiplexer and a reflective semiconductor optical amplifier

NARCIS (Netherlands)

Urban, P.J.; de Laat, M.M.; Klein, E.J.; Koonen, A.M.J.; Khoe, G.D.; de Waardt, H.; Marciniak, M.; Jaworski, M.; Zdabiwicz, M.

2008-01-01

In this paper, we demonstrate symmetrical bidirectional transmission of 1.25 Gbit/s wavelength channels in an access network link employing centralized light generation, colourless optical network unit (ONU) and a reconfigurable optical add/drop multiplexer (ROADM). The architecture of ONU is based

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam

2011-12-01

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

Facilitating preemptive hardware system design using partial reconfiguration techniques.

Science.gov (United States)

Dondo Gazzano, Julio; Rincon, Fernando; Vaderrama, Carlos; Villanueva, Felix; Caba, Julian; Lopez, Juan Carlos

2014-01-01

In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems. In real-time systems, the deadline for critical task can compel the preemption of noncritical one. Besides, an asynchronous event can demand immediate attention and, then, force launching a reconfiguration process for high-priority task implementation. If the asynchronous event is previously scheduled, an explicit activation of the reconfiguration process is performed. If the event cannot be previously programmed, such as in dynamically scheduled systems, an implicit activation to the reconfiguration process is demanded. This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope with this issue. Furthermore, the reconfiguration service introduced in this work allows remote invocation of the reconfiguration process and then the remote integration of off-chip components. A model that offers component location transparency is also presented to enhance and facilitate system integration.

Design and Implementation of a Sort-Free K-Best Sphere Decoder

KAUST Repository

Mondal, Sudip

2012-10-18

This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as quantized metrics result in a high throughput VLSI architecture with lower power and area consumption compared to state of the art published systems. Functionality is confirmed via an FPGA implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized ASIC implementation in a 65nm CMOS technology.

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

Directory of Open Access Journals (Sweden)

Jen-Chih Kuo

2003-12-01

Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

Decentralized Sliding Mode Observer Based Dual Closed-Loop Fault Tolerant Control for Reconfigurable Manipulator against Actuator Failure

Science.gov (United States)

Zhao, Bo; Li, Yuanchun

2015-01-01

This paper considers a decentralized fault tolerant control (DFTC) scheme for reconfigurable manipulators. With the appearance of norm-bounded failure, a dual closed-loop trajectory tracking control algorithm is proposed on the basis of the Lyapunov stability theory. Characterized by the modularization property, the actuator failure is estimated by the proposed decentralized sliding mode observer (DSMO). Moreover, the actuator failure can be treated in view of the local joint information, so its control performance degradation is independent of other normal joints. In addition, the presented DFTC scheme is significantly simplified in terms of the structure of the controller due to its dual closed-loop architecture, and its feasibility is highly reflected in the control of reconfigurable manipulators. Finally, the effectiveness of the proposed DFTC scheme is demonstrated using simulations. PMID:26181826

Decentralized Sliding Mode Observer Based Dual Closed-Loop Fault Tolerant Control for Reconfigurable Manipulator against Actuator Failure.

Directory of Open Access Journals (Sweden)

Bo Zhao

Full Text Available This paper considers a decentralized fault tolerant control (DFTC scheme for reconfigurable manipulators. With the appearance of norm-bounded failure, a dual closed-loop trajectory tracking control algorithm is proposed on the basis of the Lyapunov stability theory. Characterized by the modularization property, the actuator failure is estimated by the proposed decentralized sliding mode observer (DSMO. Moreover, the actuator failure can be treated in view of the local joint information, so its control performance degradation is independent of other normal joints. In addition, the presented DFTC scheme is significantly simplified in terms of the structure of the controller due to its dual closed-loop architecture, and its feasibility is highly reflected in the control of reconfigurable manipulators. Finally, the effectiveness of the proposed DFTC scheme is demonstrated using simulations.

Elements of Autonomous Self-Reconfigurable Robots

DEFF Research Database (Denmark)

Christensen, David Johan

In this thesis, we study several central elements of autonomous self-reconfigurable modular robots. Unlike conventional robots such robots are: i) Modular, since robots are assembled from numerous robotic modules. ii) Reconfigurable, since the modules can be combined in a variety of ways. iii) Self......-reconfigurable, since the modules themselves are able to change how they are combined. iv) Autonomous, since robots control themselves without human guidance. Such robots are attractive to study since they in theory have several desirable characteristics, such as versatility, reliability and cheapness. In practice...... however, it is challenging to realize such characteristics since state-of-the-art systems and solutions suffer from several inherent technical and theoretical problems and limitations. In this thesis, we address these challenges by exploring four central elements of autonomous self-reconfigurable modular...

Development methods for VLSI-processors

International Nuclear Information System (INIS)

Horninger, K.; Sandweg, G.

1982-01-01

The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

Silicon Processors Using Organically Reconfigurable Techniques (SPORT)

Science.gov (United States)

2014-05-19

AFRL-OSR-VA-TR-2014-0132 SILICON PROCESSORS USING ORGANICALLY RECONFIGURABLE TECHNIQUES ( SPORT ) Dennis Prather UNIVERSITY OF DELAWARE Final Report 05...5a. CONTRACT NUMBER Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) 5b. GRANT NUMBER FA9550-10-1-0363 5c...Contract: Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) Contract #: FA9550-10-1-0363 Reporting Period: 1 July 2010 – 31 December

Novel Cross-Type Network for Wide-Tuning-Range Reconfigurable Multiband Antennas

Directory of Open Access Journals (Sweden)

Chieh-Sen Lee

2014-01-01

Full Text Available This paper presents a cross-type network design with a novel reconfigurable functionality to realize a tunable multiband antenna. By attaching a reconfigurable network at the feeding port of a broadband antenna, multi-input impedance adjustment enables the production of multimatching operating bands. Each band can be independently controlled by a single component with a considerably wide tuning range and high selectivity. The experiments in this study involved using an ultra-wideband (UWB antenna connected to the proposed cross-type network. The tunable antenna operates in a dual band of fL (1.39 to 2.34 GHz and fH (2.1 to 3.6 GHz with tunable frequency ratios of 168% and 132%, respectively. The average bandwidths at fL and fH are approximately 50 MHz and 148 MHz, respectively, implying narrowband operation. The measured radiation pattern revealed that the tunable antenna exhibits a nearly omnidirectional radiation pattern at both 1.8 and 3.5 GHz. The network circuit architecture can be extended to the multiband function type by adopting this matching approach. The amount of shunt matches determines the number of operation bands.

Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

Science.gov (United States)

Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

2017-12-01

Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

Reconfigurable Diodes Based on Vertical WSe2 Transistors with van der Waals Bonded Contacts.

Science.gov (United States)

Avsar, Ahmet; Marinov, Kolyo; Marin, Enrique Gonzalez; Iannaccone, Giuseppe; Watanabe, Kenji; Taniguchi, Takashi; Fiori, Gianluca; Kis, Andras

2018-05-01

New device concepts can increase the functionality of scaled electronic devices, with reconfigurable diodes allowing the design of more compact logic gates being one of the examples. In recent years, there has been significant interest in creating reconfigurable diodes based on ultrathin transition metal dichalcogenide crystals due to their unique combination of gate-tunable charge carriers, high mobility, and sizeable band gap. Thanks to their large surface areas, these devices are constructed under planar geometry and the device characteristics are controlled by electrostatic gating through rather complex two independent local gates or ionic-liquid gating. In this work, similar reconfigurable diode action is demonstrated in a WSe 2 transistor by only utilizing van der Waals bonded graphene and Co/h-BN contacts. Toward this, first the charge injection efficiencies into WSe 2 by graphene and Co/h-BN contacts are characterized. While Co/h-BN contact results in nearly Schottky-barrier-free charge injection, graphene/WSe 2 interface has an average barrier height of ≈80 meV. By taking the advantage of the electrostatic transparency of graphene and the different work-function values of graphene and Co/h-BN, vertical devices are constructed where different gate-tunable diode actions are demonstrated. This architecture reveals the opportunities for exploring new device concepts. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

2011-01-01

-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

Drift chamber tracking with a VLSI neural network

International Nuclear Information System (INIS)

Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

1992-10-01

We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

Reconfiguring Urban Sustainability Transitions, Analysing Multiplicity

Directory of Open Access Journals (Sweden)

Mike Hodson

2017-02-01

Full Text Available Cities, and the networked infrastructures that sustain urban life, are seen as crucial sites for creating more sustainable futures. Yet, although there are many plans, the realisation of sustainable urban infrastructures on the ground is uneven. To develop better ways of understanding why this is the case, the paper makes a conceptual contribution by engaging with current understanding of urban sustainability transitions, using urban sustainable mobility as a reference point. It extends these insights to argue that urban transitions are not about technological or social innovation per se, but about how multiple innovations are experimented with, combined and reconfigured in existing urban contexts and how such processes are governed. There are potentially many ways in which urban sustainable mobility can be reconfigured contextually. Innovation is in the particular form of reconfiguration rather than individual technologies. To make analytical sense of this multiplicity, a preliminary framework is developed that offers the potential to think about urban transitions as contextual and reconfigurational. We argue that there is a need to embrace multiplicity and to understand its relationships to forms of reconfiguration, through empirical exploration and further theoretical and conceptual development. The preliminary framework is a contribution to doing so and we set out future directions for research.

Field-programmable custom computing technology architectures, tools, and applications

CERN Document Server

Luk, Wayne; Pocek, Ken

2000-01-01

Field-Programmable Custom Computing Technology: Architectures, Tools, and Applications brings together in one place important contributions and up-to-date research results in this fast-moving area. In seven selected chapters, the book describes the latest advances in architectures, design methods, and applications of field-programmable devices for high-performance reconfigurable systems. The contributors to this work were selected from the leading researchers and practitioners in the field. It will be valuable to anyone working or researching in the field of custom computing technology. It serves as an excellent reference, providing insight into some of the most challenging issues being examined today.

Distribution grid reconfiguration reduces power losses and helps integrate renewables

International Nuclear Information System (INIS)

Lueken, Colleen; Carvalho, Pedro M.S.; Apt, Jay

2012-01-01

A reconfigurable network can change its topology by opening and closing switches on power lines. We use real wind, solar, load, and cost data and a model of a reconfigurable distribution grid to show that reconfiguration allows a grid operator to reduce operational losses as well as to accept more intermittent renewable generation than a static configuration can. Net present value analysis of automated switch technology shows that the return on investment is negative for this test network when considering only loss reduction, but that the investment is attractive under certain conditions when reconfiguration is used to minimize curtailment. - Highlights: ► Reconfiguration may reduce losses in grids with solar or wind distributed generation. ► Reconfigurable networks can accept more solar or wind DG than static ones. ► Using reconfiguration for loss reduction would not create a positive ROI. ► Using reconfiguration to reduce curtailment usually would create a positive ROI.

From stretchable to reconfigurable inorganic electronics

KAUST Repository

Nassar, Joanna M.

2016-05-06

Today’s state-of-the-art electronics are high performing, energy efficient, multi-functional and cost effective. However, they are also typically rigid and brittle. With the emergence of the Internet of Everything, electronic applications are expanding into previously unexplored areas, like healthcare, smart wearable artifacts, and robotics. One major challenge is the physical asymmetry of target application surfaces, which often cause mechanical stretching, contracting, twisting and other deformations to the application. In this review paper, we explore materials, processes, mechanics and devices that enable physically stretchable and reconfigurable electronics. While the concept of stretchable electronics is commonly used in practice, the notion of physically reconfigurable electronics is still in its infancy. Because organic materials are commonly naturally stretchable and physically deformable, we predominantly focus on electronics made from inorganic materials that have the capacity for physical stretching and reconfiguration while retaining their intended attributes. We emphasize how applications of electronics dictate theory to integration strategy for stretchable and reconfigurable inorganic electronics.

Multimode Communication Protocols Enabling Reconfigurable Radios

Directory of Open Access Journals (Sweden)

Berlemann Lars

2005-01-01

Full Text Available This paper focuses on the realization and application of a generic protocol stack for reconfigurable wireless communication systems. This focus extends the field of software-defined radios which usually concentrates on the physical layer. The generic protocol stack comprises common protocol functionality and behavior which are extended through specific parts of the targeted radio access technology. This paper considers parameterizable modules of basic protocol functions residing in the data link layer of the ISO/OSI model. System-specific functionality of the protocol software is realized through adequate parameterization and composition of the generic modules. The generic protocol stack allows an efficient realization of reconfigurable protocol software and enables a completely reconfigurable wireless communication system. It is a first step from side-by-side realized, preinstalled modes in a terminal towards a dynamic reconfigurable anymode terminal. The presented modules of the generic protocol stack can also be regarded as a toolbox for the accelerated and cost-efficient development of future communication protocols.

High-energy heavy ion testing of VLSI devices for single event ...

Indian Academy of Sciences (India)

Unknown

per describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) ... The experimental set up employed to produce low flux of heavy ions viz. silicon ... through which they pass, leaving behind a wake of elec- ... for use in Bus Management Unit (BMU) and bulk CMOS ... was scheduled.

Design, Modelling and Analysis of a Workflow Reconfiguration

DEFF Research Database (Denmark)

Mazzara, Manuel; Abouzaid, Faisal; Dragoni, Nicola

2011-01-01

This paper describes a case study involving the reconfiguration of an office workflow. We state the requirements on a system implementing the workflow and its reconfiguration, and describe the system’s design in BPMN. We then use an asynchronous pi-calculus and Web.1 to model the design and to ve......This paper describes a case study involving the reconfiguration of an office workflow. We state the requirements on a system implementing the workflow and its reconfiguration, and describe the system’s design in BPMN. We then use an asynchronous pi-calculus and Web.1 to model the design...

Reconfiguring trade mark law

DEFF Research Database (Denmark)

Elsmore, Matthew James

2013-01-01

-border setting, with a particular focus on small business and consumers. The article's overall message is to call for a rethink of received wisdom suggesting that trade marks are effective trade-enabling devices. The case is made for reassessing how we think about European trade mark law.......First, this article argues that trade mark law should be approached in a supplementary way, called reconfiguration. Second, the article investigates such a reconfiguration of trade mark law by exploring the interplay of trade marks and service transactions in the Single Market, in the cross...

The AMchip: A VLSI associative memory for track finding

International Nuclear Information System (INIS)

Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

1992-01-01

An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

Science.gov (United States)

Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

2012-01-01

Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

Emergent auditory feature tuning in a real-time neuromorphic VLSI system

Directory of Open Access Journals (Sweden)

Sadique eSheik

2012-02-01

Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

Science.gov (United States)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

Optimization of metallic microheaters for high-speed reconfigurable silicon photonics.

Science.gov (United States)

Atabaki, A H; Shah Hosseini, E; Eftekhar, A A; Yegnanarayanan, S; Adibi, A

2010-08-16

The strong thermooptic effect in silicon enables low-power and low-loss reconfiguration of large-scale silicon photonics. Thermal reconfiguration through the integration of metallic microheaters has been one of the more widely used reconfiguration techniques in silicon photonics. In this paper, structural and material optimizations are carried out through heat transport modeling to improve the reconfiguration speed of such devices, and the results are experimentally verified. Around 4 micros reconfiguration time are shown for the optimized structures. Moreover, sub-microsecond reconfiguration time is experimentally demonstrated through the pulsed excitation of the microheaters. The limitation of this pulsed excitation scheme is also discussed through an accurate system-level model developed for the microheater response.

Using Software Technology to Specify Abstract Interfaces in VLSI Design.

Science.gov (United States)

1985-01-01

with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

Secure computing on reconfigurable systems

OpenAIRE

Fernandes Chaves, R.J.

2007-01-01

This thesis proposes a Secure Computing Module (SCM) for reconfigurable computing systems. SC provides a protected and reliable computational environment, where data security and protection against malicious attacks to the system is assured. SC is strongly based on encryption algorithms and on the attestation of the executed functions. The use of SC on reconfigurable devices has the advantage of being highly adaptable to the application and the user requirements, while providing high performa...

Reconfiguring Maternity Care?

DEFF Research Database (Denmark)

Johannsen, Nis

This dissertation constitutes a reflection on two initiatives seeking to reconfigure maternity care. One initiative sought to digitalise maternity records and included a pilot run of an electronic maternity record in a Danish county. The other consisted of a collaboration between a maternity ward...... at a hospital and a group of researchers which included me. Both initiatives involved numerous seemingly different interests that were held together and related to reconfiguring maternity care. None of the initiatives can unequivocally be labelled a success, as neither managed to change maternity care, at least...... experimental designs are constructed. The consequences and the politics of the proposed changes are engaged with in laboratory manner through collaborative development of the designs and through exposing them to members of field of maternity care...

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

Science.gov (United States)

Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

2005-06-01

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

Design of reconfigurable antennas using graph models

CERN Document Server

Costantine, Joseph; Christodoulou, Christos G; Christodoulou, Christos G

2013-01-01

This lecture discusses the use of graph models to represent reconfigurable antennas. The rise of antennas that adapt to their environment and change their operation based on the user's request hasn't been met with clear design guidelines. There is a need to propose some rules for the optimization of any reconfigurable antenna design and performance. Since reconfigurable antennas are seen as a collection of self-organizing parts, graph models can be introduced to relate each possible topology to a corresponding electromagnetic performance in terms of achieving a characteristic frequency of oper

Graphene-based Yagi-Uda antenna with reconfigurable radiation patterns

Energy Technology Data Exchange (ETDEWEB)

Wu, Yongle, E-mail: wuyongle138@gmail.com; Qu, Meijun; Jiao, Lingxiao; Liu, Yuanan [School of Electronic Engineering, Beijing Key Laboratory of Work Safety Intelligent Monitoring, Beijing University of Posts and Telecommunications, P. O. Box. 282, Beijing, 100876 (China); Ghassemlooy, Zabih [Optical Communications Research Group, NCRLab, Faculty of Engineering and Environment, Northumbria University, Newcastle upon Tyne, NE1 8ST (United Kingdom)

2016-06-15

This paper presents a radiation pattern reconfigurable Yagi-Uda antenna based on graphene operating at terahertz frequencies. The antenna can be reconfigured to change the main beam pattern into two or four different radiation directions. The proposed antenna consists of a driven dipole radiation conductor, parasitic strips and embedded graphene. The hybrid graphene-metal implementation enables the antenna to have dynamic surface conductivity, which can be tuned by changing the chemical potentials. Therefore, the main beam direction, the resonance frequency, and the front-to-back ratio of the proposed antenna can be controlled by tuning the chemical potentials of the graphene embedded in different positions. The proposed two-beam reconfigurable Yagi-Uda antenna can achieve excellent unidirectional symmetrical radiation pattern with the front-to-back ratio of 11.9 dB and the10-dB impedance bandwidth of 15%. The different radiation directivity of the two-beam reconfigurable antenna can be achieved by controlling the chemical potentials of the graphene embedded in the parasitic stubs. The achievable peak gain of the proposed two-beam reconfigurable antenna is about 7.8 dB. Furthermore, we propose a four-beam reconfigurable Yagi-Uda antenna, which has stable reflection-coefficient performance although four main beams in reconfigurable cases point to four totally different directions. The corresponding peak gain, front-to-back ratio, and 10-dB impedance bandwidth of the four-beam reconfigurable antenna are about 6.4 dB, 12 dB, and 10%, respectively. Therefore, this novel design method of reconfigurable antennas is extremely promising for beam-scanning in terahertz and mid-infrared plasmonic devices and systems.

Autonomous Dynamically Self-Organizing and Self-Healing Distributed Hardware Architecture - the eDNA Concept

Science.gov (United States)

Boesen, Michael Reibel; Madsen, Jan; Keymeulen, Didier

2011-01-01

This paper presents the current state of the autonomous dynamically self-organizing and self-healing electronic DNA (eDNA) hardware architecture (patent pending). In its current prototype state, the eDNA architecture is capable of responding to multiple injected faults by autonomously reconfiguring itself to accommodate the fault and keep the application running. This paper will also disclose advanced features currently available in the simulation model only. These features are future work and will soon be implemented in hardware. Finally we will describe step-by-step how an application is implemented on the eDNA architecture.

Reconfigurable fault tolerant avionics system

Science.gov (United States)

Ibrahim, M. M.; Asami, K.; Cho, Mengu

This paper presents the design of a reconfigurable avionics system based on modern Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA) to be used in future generations of nano satellites. A major concern in satellite systems and especially nano satellites is to build robust systems with low-power consumption profiles. The system is designed to be flexible by providing the capability of reconfiguring itself based on its orbital position. As Single Event Upsets (SEU) do not have the same severity and intensity in all orbital locations, having the maximum at the South Atlantic Anomaly (SAA) and the polar cusps, the system does not have to be fully protected all the time in its orbit. An acceptable level of protection against high-energy cosmic rays and charged particles roaming in space is provided within the majority of the orbit through software fault tolerance. Check pointing and roll back, besides control flow assertions, is used for that level of protection. In the minority part of the orbit where severe SEUs are expected to exist, a reconfiguration for the system FPGA is initiated where the processor systems are triplicated and protection through Triple Modular Redundancy (TMR) with feedback is provided. This technique of reconfiguring the system as per the level of the threat expected from SEU-induced faults helps in reducing the average dynamic power consumption of the system to one-third of its maximum. This technique can be viewed as a smart protection through system reconfiguration. The system is built on the commercial version of the (XC5VLX50) Xilinx Virtex5 FPGA on bulk silicon with 324 IO. Simulations of orbit SEU rates were carried out using the SPENVIS web-based software package.

A Sustainable, Reliable Mission-Systems Architecture that Supports a System of Systems Approach to Space Exploration

Science.gov (United States)

Watson, Steve; Orr, Jim; O'Neil, Graham

2004-01-01

A mission-systems architecture based on a highly modular "systems of systems" infrastructure utilizing open-standards hardware and software interfaces as the enabling technology is absolutely essential for an affordable and sustainable space exploration program. This architecture requires (a) robust communication between heterogeneous systems, (b) high reliability, (c) minimal mission-to-mission reconfiguration, (d) affordable development, system integration, and verification of systems, and (e) minimum sustaining engineering. This paper proposes such an architecture. Lessons learned from the space shuttle program are applied to help define and refine the model.

Go reconfigure: how fish change shape as they swim and evolve.

Science.gov (United States)

Long, John H; Porter, Marianne E; Root, Robert G; Liew, Chun Wai

2010-12-01

The bodies of fish change shape over propulsive, behavioral, developmental, and evolutionary time scales, a general phenomenon that we call "reconfiguration". Undulatory, postural, and form-reconfiguration can be distinguished, studied independently, and examined in terms of mechanical interactions and evolutionary importance. Using a combination of live, swimming fishes and digital robotic fish that are autonomous and self-propelled, we examined the functional relation between undulatory and postural reconfiguration in forward swimming, backward swimming, and yaw turning. To probe how postural and form reconfiguration interact, the yaw turning of leopard sharks was examined using morphometric and kinematic analyses. To test how undulatory reconfiguration might evolve, the digital robotic fish were subjected to selection for enhanced performance in a simulated ecology in which each individual had to detect and move towards a food source. In addition to the general issue of reconfiguration, these investigations are united by the fact that the dynamics of undulatory and postural reconfigurations are predicted to be determined, in part, by the structural stiffness of the fish's body. Our method defines undulatory reconfiguration as the combined, point-by-point periodic motion of the body, leaving postural reconfiguration as the combined deviations from undulatory reconfiguration. While undulatory reconfiguration appears to be the sole or primary propulsive driver, postural reconfiguration may contribute to propulsion in hagfish and it is correlated with differences in forward, and backward, swimming in lamprey. Form reconfigures over developmental time in leopard sharks in a manner that is consistent with an allometric scaling theory in which structural stiffness of the body is held constant. However, correlation of a form proxy for structural stiffness of the body suggests that body stiffness may scale in order to limit maximum postural reconfiguration during routine

Lattice Automata for Control of Self-Reconfigurable Robots

DEFF Research Database (Denmark)

Støy, Kasper

2015-01-01

are extreme versatility and robustness. The organisation of self-reconfigurable robots in a lattice structure and the emphasis on local communication between modules mean that lattice automata are a useful basis for control of self-reconfigurable robots. However, there are significant differences which arise...... mainly from the physical nature of self-reconfigurable robots as opposed to the virtual nature of lattice automata. The problems resulting from these differences are mutual exclusion, handling motion constraints of modules, and unrealistic assumption about global, spatial orientation. Despite...... these problems the self-reconfigurable robot community has successfully applied lattice automata to simple control problems. However, for more complex problems hybrid solutions based on lattice automata and distributed algorithms are used. Hence, lattice automata have shown to have potential for the control...

VLSI Technology for Cognitive Radio

Science.gov (United States)

VIJAYALAKSHMI, B.; SIDDAIAH, P.

2017-08-01

One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

Directory of Open Access Journals (Sweden)

Di Wu

2010-01-01

Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

Integration of the Reconfigurable Self-Healing eDNA Architecture in an Embedded System

Science.gov (United States)

Boesen, Michael Reibel; Keymeulen, Didier; Madsen, Jan; Lu, Thomas; Chao, Tien-Hsin

2011-01-01

In this work we describe the first real world case study for the self-healing eDNA (electronic DNA) architecture by implementing the control and data processing of a Fourier Transform Spectrometer (FTS) on an eDNA prototype. For this purpose the eDNA prototype has been ported from a Xilinx Virtex 5 FPGA to an embedded system consisting of a PowerPC and a Xilinx Virtex 5 FPGA. The FTS instrument features a novel liquid crystal waveguide, which consequently eliminates all moving parts from the instrument. The addition of the eDNA architecture to do the control and data processing has resulted in a highly fault-tolerant FTS instrument. The case study has shown that the early stage prototype of the autonomous self-healing eDNA architecture is expensive in terms of execution time.

A multi coding technique to reduce transition activity in VLSI circuits

International Nuclear Information System (INIS)

Vithyalakshmi, N.; Rajaram, M.

2014-01-01

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

Science.gov (United States)

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Design of a VLSI Decoder for Partially Structured LDPC Codes

Directory of Open Access Journals (Sweden)

Fabrizio Vacca

2008-01-01

of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

Modular reconfigurable machine tools: design, control and evaluation

CSIR Research Space (South Africa)

Padayachee, J

2009-11-01

Full Text Available The reconfigurable manufacturing system (RMS) paradigm encapsulates methodologies that enable manufacturing systems to cope effectively with market and product changes. This research presents the design and evaluation of modular reconfigurable...

3rd IEEE/IFToMM International Conference on Reconfigurable Mechanisms and Robots

CERN Document Server

Kong, Xianwen; Dai, Jian; ReMAR 2015; Advances in Reconfigurable Mechanisms and Robots II

2016-01-01

This book presents the most recent advances in the research and applications of reconfigurable mechanisms and robots. It collects 93 independently reviewed papers presented at the Third ASME/IFToMM International Conference on Reconfigurable Mechanisms and Robots (ReMAR 2015) held in Beijing, China, 20-22 July 2015. The conference papers are organized into seven parts to cover the reconfiguration theory, topology, kinematics and design of reconfigurable mechanisms including reconfigurable parallel mechanisms. The most recent results on reconfigurable robots are presented including their analysis, design, simulation and control. Bio-inspired mechanisms are also explored in the challenging fields of rehabilitation and minimally invasive surgery. This book further addresses deployable mechanisms and origami-inspired mechanisms and showcases a wide range of successful applications of reconfigurable mechanisms and robots. Advances in Reconfigurable Mechanisms and Robots II should be of interest for researchers, eng...

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems (Habilitation)

NARCIS (Netherlands)

Ziener, Daniel

2017-01-01

In this treatise,  my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined. The efficiency of reconfigurable systems can be improved by loading optimized data paths on-the-fly on an

Formal verification an essential toolkit for modern VLSI design

CERN Document Server

Seligman, Erik; Kumar, M V Achutha Kiran

2015-01-01

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

DPL/Daedalus design environment (for VLSI)

Energy Technology Data Exchange (ETDEWEB)

Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

1981-01-01

The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Directory of Open Access Journals (Sweden)

Paolo Meloni

2012-01-01

Full Text Available Application Specific Instruction-set Processors (ASIPs expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed as an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.

Distinguishing Reconfiguration and Compound-cue Retrieval in Task Switching

Directory of Open Access Journals (Sweden)

Gordon D Logan

2010-10-01

Full Text Available Many researchers claim that task switching requires reconfiguration of the cognitive system. Others claim that task switching involves cue-based memory retrieval processes and not reconfiguration. We evaluate these competing claims by developing both reconfiguration and cue-based memory models in a common theoretical framework and by fitting the models to' target functions', which show how performance on individual target stimuli varies depending on the task subjects perform on the targets. Our analyses show that the process of compound-cue retrieval – using the task cue and the target as joint retrieval cues to select a response from memory – is sufficient to explain target functions for parity and magnitude judgments of digits and that reconfiguration does not seem to add anything to the explanation. We address the generality of this conclusion and speculate about the conditions under which reconfiguration may be necessary for task switching.

Design Tools for Reconfigurable Hardware in Orbit (RHinO)

Science.gov (United States)

French, Mathew; Graham, Paul; Wirthlin, Michael; Larchev, Gregory; Bellows, Peter; Schott, Brian

2004-01-01

The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. These tools leverage an established FPGA design environment and focus primarily on space effects mitigation and power optimization. The project is creating software to automatically test and evaluate the single-event-upsets (SEUs) sensitivities of an FPGA design and insert mitigation techniques. Extensions into the tool suite will also allow evolvable algorithm techniques to reconfigure around single-event-latchup (SEL) events. In the power domain, tools are being created for dynamic power visualiization and optimization. Thus, this technology seeks to enable the use of Reconfigurable Hardware in Orbit, via an integrated design tool-suite aiming to reduce risk, cost, and design time of multimission reconfigurable space processors using SRAM-based FPGAs.

Implementation of an Optical-Wireless Network with Spectrum Sensing and Dynamic Resource Allocation Using Optically Controlled Reconfigurable Antennas

Directory of Open Access Journals (Sweden)

E. Raimundo-Neto

2014-01-01

Full Text Available This work proposes the concept and reports the implementation of an adaptive and cognitive radio over fiber architecture. It is aimed at dealing with the new demands for convergent networks by means of simultaneously providing the functionalities of multiband radiofrequency spectrum sensing, dynamic resource allocation, and centralized processing capability, as well as the use of optically controlled reconfigurable antennas and radio over fiber technology. The performance of this novel and innovative architecture has been evaluated in a geographically distributed optical-wireless network under real conditions and for different fiber lengths. Experimental results demonstrate reach extension of more than 40 times and an enhancement of more than 30 dB in the carrier to interference plus noise ratio parameter.

Reconfigurable layout problem

NARCIS (Netherlands)

Meng, G.; Heragu, S.S.; Heragu, S.S.; Zijm, Willem H.M.

2004-01-01

This paper addresses the reconfigurable layout problem, which differs from traditional, robust and dynamic layout problems mainly in two aspects: first, it assumes that production data are available only for the current and upcoming production period. Second, it considers queuing performance

Autonomous distributed self-organizing and self-healing hardware architecture - The eDNA concept

DEFF Research Database (Denmark)

Boesen, Michael Reibel; Madsen, Jan; Keymeulen, Didier

2011-01-01

This paper presents the current state of the autonomous distributed self-organizing and self-healing electronic DNA (eDNA) hardware architecture (patent pending). In its current prototype state, the eDNA architecture is capable of responding to multiple injected faults by autonomously reconfiguring...... itself to accommodate the fault and keep the application running. This paper will also disclose advanced features currently available in the simulation model only. These features are future work and will soon be implemented in hardware. Finally we will describe step-by-step how an application...

An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

DEFF Research Database (Denmark)

Paaske, Erik; Pedersen, Steen; Sparsø, Jens

1991-01-01

Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

Motion camera based on a custom vision sensor and an FPGA architecture

Science.gov (United States)

Arias-Estrada, Miguel

1998-09-01

A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

First results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

1986-01-01

A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

An FPGA-based reconfigurable DDC algorithm

Science.gov (United States)

Juszczyk, B.; Kasprowicz, G.

2016-09-01

This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

Value Assessment of Distribution Network Reconfiguration: A Danish Case Study

DEFF Research Database (Denmark)

Vaskantiras, Georgios; You, Shi

2016-01-01

. This paper presents a case study-based analysis to explore the potential value of reconfiguration in detail. The study is performed using a 10kV distribution grid of Denmark, while reconfiguration is applied to minimize the energy losses under both normal and post-fault conditions. The results show......Distribution network reconfiguration is a mechanism that can improve the distribution system performance from multiple perspectives. In the context of smart grid wherein the degrees of automation and intelligence are high, the potential value of network reconfiguration can be significant...

VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

Directory of Open Access Journals (Sweden)

Fazal NOORBASHA

2012-08-01

Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

Memory controllers for mixed-time-criticality systems architectures, methodologies and trade-offs

CERN Document Server

Goossens, Sven; Akesson, Benny; Goossens, Kees

2016-01-01

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Reconfigurable Mobile Multimedia

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Bos, M.; Havinga, Paul J.M.; Smit, Jaap

1999-01-01

This paper discusses reconfigurability issues in lowpower hand-held multimedia systems, with particular emphasis on energy conservation. We claim that a radical new approach has to be taken in order to fulfill the requirements - in terms of processing power and energy consumption - of future mobile

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Directory of Open Access Journals (Sweden)

Akila Gothandaraman

2010-01-01

Full Text Available Recent advances in Field-Programmable Gate Array (FPGA technology make reconfigurable computing using FPGAs an attractive platform for accelerating scientific applications. We develop a deeply pipelined and parallel architecture for Quantum Monte Carlo simulations using FPGAs. Quantum Monte Carlo simulations enable us to obtain the structural and energetic properties of atomic clusters. We experiment with different pipeline structures for each component of the design and develop a deeply pipelined architecture that provides the best performance in terms of achievable clock rate, while at the same time has a modest use of the FPGA resources. We discuss the details of the pipelined and generic architecture that is used to obtain the potential energy and wave function of a cluster of atoms.

Fast-prototyping of VLSI

International Nuclear Information System (INIS)

Saucier, G.; Read, E.

1987-01-01

Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

Reconfiguring The Supply Chain For Complex Engineered Products

DEFF Research Database (Denmark)

Wæhrens, Brian Vejrum; Asmussen, Jesper Normann

2016-01-01

of the SC, the product and market requirements. This paper seeks to investigate the factors which create a need for supply chain reconfiguration in the context of the Complex Product Systems, together with the enablers and barriers for successfully realizing supply chain improvements through reconfiguration....

CogWnet: A Resource Management Architecture for Cognitive Wireless Networks

KAUST Repository

Alqerm, Ismail

2013-07-01

With the increasing adoption of wireless communication technologies, there is a need to improve management of existing radio resources. Cognitive radio is a promising technology to improve the utilization of wireless spectrum. Its operating principle is based on building an integrated hardware and software architecture that configures the radio to meet application requirements within the constraints of spectrum policy regulations. However, such an architecture must be able to cope with radio environment heterogeneity. In this paper, we propose a cognitive resource management architecture, called CogWnet, that allocates channels, re-configures radio transmission parameters to meet QoS requirements, ensures reliability, and mitigates interference. The architecture consists of three main layers: Communication Layer, which includes generic interfaces to facilitate the communication between the cognitive architecture and TCP/IP stack layers; Decision-Making Layer, which classifies the stack layers input parameters and runs decision-making optimization algorithms to output optimal transmission parameters; and Policy Layer to enforce policy regulations on the selected part of the spectrum. The efficiency of CogWnet is demonstrated through a testbed implementation and evaluation.

Operating System Concepts for Reconfigurable Computing: Review and Survey

OpenAIRE

Marcel Eckert; Dominik Meyer; Jan Haase; Bernd Klauer

2016-01-01

One of the key future challenges for reconfigurable computing is to enable higher design productivity and a more easy way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system. This article gives historical review and a summary on ideas and key concepts to include reconfigurable computing aspects in operating systems. The arti...

Architectural design for a low cost FPGA-based traffic signal detection system in vehicles

Science.gov (United States)

López, Ignacio; Salvador, Rubén; Alarcón, Jaime; Moreno, Félix

2007-05-01

In this paper we propose an architecture for an embedded traffic signal detection system. Development of Advanced Driver Assistance Systems (ADAS) is one of the major trends of research in automotion nowadays. Examples of past and ongoing projects in the field are CHAMELEON ("Pre-Crash Application all around the vehicle" IST 1999-10108), PREVENT (Preventive and Active Safety Applications, FP6-507075, http://www.prevent-ip.org/) and AVRT in the US (Advanced Vision-Radar Threat Detection (AVRT): A Pre-Crash Detection and Active Safety System). It can be observed a major interest in systems for real-time analysis of complex driving scenarios, evaluating risk and anticipating collisions. The system will use a low cost CCD camera on the dashboard facing the road. The images will be processed by an Altera Cyclone family FPGA. The board does median and Sobel filtering of the incoming frames at PAL rate, and analyzes them for several categories of signals. The result is conveyed to the driver. The scarce resources provided by the hardware require an architecture developed for optimal use. The system will use a combination of neural networks and an adapted blackboard architecture. Several neural networks will be used in sequence for image analysis, by reconfiguring a single, generic hardware neural network in the FPGA. This generic network is optimized for speed, in order to admit several executions within the frame rate. The sequence will follow the execution cycle of the blackboard architecture. The global, blackboard architecture being developed and the hardware architecture for the generic, reconfigurable FPGA perceptron will be explained in this paper. The project is still at an early stage. However, some hardware implementation results are already available and will be offered in the paper.

Flexible feature-space-construction architecture and its VLSI implementation for multi-scale object detection

Science.gov (United States)

Luo, Aiwen; An, Fengwei; Zhang, Xiangyu; Chen, Lei; Huang, Zunkai; Jürgen Mattausch, Hans

2018-04-01

Feature extraction techniques are a cornerstone of object detection in computer-vision-based applications. The detection performance of vison-based detection systems is often degraded by, e.g., changes in the illumination intensity of the light source, foreground-background contrast variations or automatic gain control from the camera. In order to avoid such degradation effects, we present a block-based L1-norm-circuit architecture which is configurable for different image-cell sizes, cell-based feature descriptors and image resolutions according to customization parameters from the circuit input. The incorporated flexibility in both the image resolution and the cell size for multi-scale image pyramids leads to lower computational complexity and power consumption. Additionally, an object-detection prototype for performance evaluation in 65 nm CMOS implements the proposed L1-norm circuit together with a histogram of oriented gradients (HOG) descriptor and a support vector machine (SVM) classifier. The proposed parallel architecture with high hardware efficiency enables real-time processing, high detection robustness, small chip-core area as well as low power consumption for multi-scale object detection.

Reconfigurability of behavioural specifications for manufacturing systems

Science.gov (United States)

Schmidt, Klaus Werner

2017-12-01

Reconfigurable manufacturing systems (RMS) support flexibility in the product variety and the configuration of the manufacturing system itself in order to enable quick adjustments to new products and production requirements. As a consequence, an essential feature of RMS is their ability to rapidly modify the control strategy during run-time. In this paper, the particular problem of changing the specified operation of a RMS, whose logical behaviour is modelled as a finite state automaton, is addressed. The notion of reconfigurability of specifications (RoS) is introduced and it is shown that the stated reconfiguration problem can be formulated as a controlled language convergence problem. In addition, algorithms for the verification of RoS and the construction of a reconfiguration supervisor are proposed. The supervisor is realised in a modular way which facilitates the extension by new configurations. Finally, it is shown that a supremal nonblocking and controllable strict subautomaton of the plant automaton that fulfils RoS exists in case RoS is violated for the plant automaton itself and an algorithm for the computation of this strict subautomaton is presented. The developed concepts and results are illustrated by a manufacturing cell example.

THE ARCHITECTURAL PATRONAGE AND POLITICAL PROWESS OF HEROD THE GREAT

Directory of Open Access Journals (Sweden)

Vivian A. Laughlin

2016-07-01

Full Text Available After supporting Marc Antony in the Battle of Actium (31 B.C., King Herod, fearful of losing his power, went to Rome, apologized to Augustus and assured him that he was his biggest supporter. Augustus, giving Herod an opportunity to redeem himself, allowed him to return to Judea as King of the Jews. In an effort for Herod to express his continued commitment to Rome, he reconfigured his building styles by making cities that  would depict Rome in the Levant. Herod created architecture that implemented Roman technology, designs, and styles, while co-mingling them with his existing Hellenistic style of architecture that made him forever remembered as Herod the Great.

A Benefit Analysis of Infusing Wireless into Aircraft and Fleet Operations - Report to Seedling Project Efficient Reconfigurable Cockpit Design and Fleet Operations Using Software Intensive, Network Enabled, Wireless Architecture (ECON)

Science.gov (United States)

Alexandrov, Natalia; Holmes, Bruce J.; Hahn, Andrew S.

2016-01-01

We report on an examination of potential benefits of infusing wireless technologies into various areas of aircraft and airspace operations. The analysis is done in support of a NASA seedling project Efficient Reconfigurable Cockpit Design and Fleet Operations Using Software Intensive, Network Enabled Wireless Architecture (ECON). The study has two objectives. First, we investigate one of the main benefit hypotheses of the ECON proposal: that the replacement of wired technologies with wireless would lead to significant weight reductions on an aircraft, among other benefits. Second, we advance a list of wireless technology applications and discuss their system benefits. With regard to the primary hypothesis, we conclude that the promise of weight reduction is premature. Specificity of the system domain and aircraft, criticality of components, reliability of wireless technologies, the weight of replacement or augmentation equipment, and the cost of infusion must all be taken into account among other considerations, to produce a reliable estimate of weight savings or increase.

A Versatile Simulation Environment of FTC Architectures for Large Transport Aircraft

OpenAIRE

Ossmann, Daniel; Varga, Andreas; Simon, Hecker

2010-01-01

We present a simulation environment with 3-D stereo visualization facilities destined for an easy setup and versatile assessment of fault detection and diagnosis based fault tolerant control systems. This environment has been primarily developed as a technology demonstrator of advanced reconfigurable flight control systems and is based on a realistic six degree of freedom flexible aircraft model. The aircraft control system architecture includes a flexible fault detection and diagnosis syste...

Design Flow Instantiation for Run-Time Reconfigurable Systems: A Case Study

Directory of Open Access Journals (Sweden)

Yang Qu

2007-12-01

Full Text Available Reconfigurable system is a promising alternative to deliver both flexibility and performance at the same time. New reconfigurable technologies and technology-dependent tools have been developed, but a complete overview of the whole design flow for run-time reconfigurable systems is missing. In this work, we present a design flow instantiation for such systems using a real-life application. The design flow is roughly divided into two parts: system level and implementation. At system level, our supports for hardware resource estimation and performance evaluation are applied. At implementation level, technology-dependent tools are used to realize the run-time reconfiguration. The design case is part of a WCDMA decoder on a commercially available reconfigurable platform. The results show that using run-time reconfiguration can save over 40% area when compared to a functionally equivalent fixed system and achieve 30 times speedup in processing time when compared to a functionally equivalent pure software design.

Operating System Concepts for Reconfigurable Computing: Review and Survey

Directory of Open Access Journals (Sweden)

Marcel Eckert

2016-01-01

Full Text Available One of the key future challenges for reconfigurable computing is to enable higher design productivity and a more easy way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system. This article gives historical review and a summary on ideas and key concepts to include reconfigurable computing aspects in operating systems. The article also presents an overview on published and available operating systems targeting the area of reconfigurable computing. The purpose of this article is to identify and summarize common patterns among those systems that can be seen as de facto standard. Furthermore, open problems, not covered by these already available systems, are identified.

Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

Science.gov (United States)

Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

1991-01-01

A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

Energy-efficient specialization of functional units in a Coarse-Grained Reconfigurable Array

International Nuclear Information System (INIS)

Van Essen, B.; Panda, R.; Wood, A.; Ebeling, C.; Hauck, S.

2010-01-01

Functional units provide the backbone of any spatial accelerator by providing the computing resources. The desire for having rich and expensive functional units is in tension with producing a regular and energy-efficient computing fabric. This paper explores the design trade-off between complex, universal functional units and simpler, limited functional units. We show that a modest amount of specialization reduces the area-delay-energy product of an optimized architecture to 0.86x a baseline architecture. Furthermore, we provide a design guideline that allows an architect to customize the contents of the computing fabric just by examining the profile of benchmarks within the application domains. Functional units are the core of compute-intensive spatial accelerators. They perform the computation of interest with support from local storage and communication structures. Ideally, the functional units will provide rich functionality, supporting operations ranging from simple addition, to fused multiply-adds, to advanced transcendental functions and domain specific operations like add-compare-select. However, the total opportunity cost to support the more complex operations is a function of the cost of the hardware, the rate of occurrence of the operation in the application domain, and the inefficiency of emulating the operation with simpler operators. Examples of operations that are typically emulated in spatial accelerators are division and trigonometric functions, which can be solved using table-lookup based algorithms and the CORDIC algorithm. One reason to avoid having direct hardware support for complex operations in a tiled architecture like a Coarse-Grained Reconfigurable Array (CGRA) is that the expensive hardware will typically need to be replicated in some or all of the architecture's tiles. Tiled architecture are designed such that their tiles are either homogeneous or heterogeneous. Homogeneous architectures are simpler to design but heterogeneous

Hierarchically assembled DNA origami tubules with reconfigurable chirality

International Nuclear Information System (INIS)

Chen, Haorong; Cha, Tae-Gon; Pan, Jing; Choi, Jong Hyun

2013-01-01

The dynamic reconfiguration of a hierarchically assembled tubular structure is demonstrated using the DNA origami technique. Short cylindrical DNA origami monomers are synthesized and linked into elongated tubules, which can then be disassembled via toehold-mediated strand displacement. The disassembled subunits are subsequently linked into tubules of a different chirality. The reconfiguration is performed with the subunits carrying dumbbell hairpin DNA oligonucleotides or gold nanoparticles (AuNPs). The reconfiguration of higher order origami structures presented here is useful for constructing dynamic nanostructures that exceed the size limit of single DNA origami and may facilitate the study of molecular or particle interactions by tuning their relative distance and organization. (paper)

Pass-band reconfigurable spoof surface plasmon polaritons

Science.gov (United States)

Zhang, Hao Chi; He, Pei Hang; Gao, Xinxin; Tang, Wen Xuan; Cui, Tie Jun

2018-04-01

In this paper, we introduce a new scheme to construct the band-pass tunable filter based on the band-pass reconfigurable spoof surface plasmon polaritons (SPPs), whose cut-off frequencies at both sides of the passband can be tuned through changing the direct current (DC) bias of varactors. Compared to traditional technology (e.g. microstrip filters), the spoof SPP structure can provide more tight field confinement and more significant field enhancement, which is extremely valuable for many system applications. In order to achieve this scheme, we proposed a specially designed SPP filter integrated with varactors and DC bias feeding structure to support the spoof SPP passband reconfiguration. Furthermore, the full-wave simulated result verifies the outstanding performance on both efficiency and reconfiguration, which has the potential to be widely used in advanced intelligent systems.

Multi-net optimization of VLSI interconnect

CERN Document Server

Moiseev, Konstantin; Wimer, Shmuel

2015-01-01

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

Energy Technology Data Exchange (ETDEWEB)

Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

1992-01-01

The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

Manipulating waves with LEGO® bricks: A versatile experimental platform for metamaterial architectures

International Nuclear Information System (INIS)

Celli, Paolo; Gonella, Stefano

2015-01-01

In this letter, we discuss a versatile, fully reconfigurable experimental platform for the investigation of phononic phenomena in metamaterial architectures. The approach revolves around the use of 3D laser vibrometry to reconstruct global and local wavefield features in specimens obtained through simple arrangements of LEGO ® bricks on a thin baseplate. The agility by which it is possible to reconfigure the brick patterns into a nearly endless spectrum of topologies makes this an effective approach for rapid experimental proof of concept, as well as a powerful didactic tool, in the arena of phononic crystals and metamaterials engineering. We use our platform to provide a compelling visual illustration of important spatial wave manipulation effects (waveguiding and seismic isolation), and to elucidate fundamental dichotomies between Bragg-based and locally resonant bandgap mechanisms

Manipulating waves with LEGO bricks: A versatile experimental platform for metamaterial architectures

Science.gov (United States)

Celli, Paolo; Gonella, Stefano

2015-08-01

In this letter, we discuss a versatile, fully reconfigurable experimental platform for the investigation of phononic phenomena in metamaterial architectures. The approach revolves around the use of 3D laser vibrometry to reconstruct global and local wavefield features in specimens obtained through simple arrangements of LEGO® bricks on a thin baseplate. The agility by which it is possible to reconfigure the brick patterns into a nearly endless spectrum of topologies makes this an effective approach for rapid experimental proof of concept, as well as a powerful didactic tool, in the arena of phononic crystals and metamaterials engineering. We use our platform to provide a compelling visual illustration of important spatial wave manipulation effects (waveguiding and seismic isolation), and to elucidate fundamental dichotomies between Bragg-based and locally resonant bandgap mechanisms.

Short-Term Load Forecasting-Based Automatic Distribution Network Reconfiguration

Energy Technology Data Exchange (ETDEWEB)

Jiang, Huaiguang [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Ding, Fei [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Zhang, Yingchen [National Renewable Energy Laboratory (NREL), Golden, CO (United States)

2017-08-23

In a traditional dynamic network reconfiguration study, the optimal topology is determined at every scheduled time point by using the real load data measured at that time. The development of the load forecasting technique can provide an accurate prediction of the load power that will happen in a future time and provide more information about load changes. With the inclusion of load forecasting, the optimal topology can be determined based on the predicted load conditions during a longer time period instead of using a snapshot of the load at the time when the reconfiguration happens; thus, the distribution system operator can use this information to better operate the system reconfiguration and achieve optimal solutions. This paper proposes a short-term load forecasting approach to automatically reconfigure distribution systems in a dynamic and pre-event manner. Specifically, a short-term and high-resolution distribution system load forecasting approach is proposed with a forecaster based on support vector regression and parallel parameters optimization. The network reconfiguration problem is solved by using the forecasted load continuously to determine the optimal network topology with the minimum amount of loss at the future time. The simulation results validate and evaluate the proposed approach.

Reconfigurable Sensor Monitoring System

Science.gov (United States)

Alhorn, Dean C. (Inventor); Dutton, Kenneth R. (Inventor); Howard, David E. (Inventor); Smith, Dennis A. (Inventor)

2017-01-01

A reconfigurable sensor monitoring system includes software tunable filters, each of which is programmable to condition one type of analog signal. A processor coupled to the software tunable filters receives each type of analog signal so-conditioned.

International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

CERN Document Server

Shirur, Yasha; Prasad, Rekha

2013-01-01

This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

Built-in self-repair of VLSI memories employing neural nets

Science.gov (United States)

Mazumder, Pinaki

1998-10-01

The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

System-level tools and reconfigurable computing for next-generation HWIL systems

Science.gov (United States)

Stark, Derek; McAulay, Derek; Cantle, Allan J.; Devlin, Malachy

2001-08-01

Previous work has been presented on the creation of computing architectures called DIME, which addressed the particular computing demands of hardware in the loop systems. These demands include low latency, high data rates and interfacing. While it is essential to have a capable platform for handling and processing of the data streams, the tools must also complement this so that a system's engineer is able to construct their final system. The paper will present the work in the area of integration of system level design tools, such as MATLAB and SIMULINK, with a reconfigurable computing platform. This will demonstrate how algorithms can be implemented and simulated in a familiar rapid application development environment before they are automatically transposed for downloading directly to the computing platform. This complements the established control tools, which handle the configuration and control of the processing systems leading to a tool suite for system development and implementation. As the development tools have evolved the core-processing platform has also been enhanced. These improved platforms are based on dynamically reconfigurable computing, utilizing FPGA technologies, and parallel processing methods that more than double the performance and data bandwidth capabilities. This offers support for the processing of images in Infrared Scene Projectors with 1024 X 1024 resolutions at 400 Hz frame rates. The processing elements will be using the latest generation of FPGAs, which implies that the presented systems will be rated in terms of Tera (1012) operations per second.

Glenn Reconfigurable User-interface and Virtual reality Exploration (GURVE) Laboratory

Data.gov (United States)

Federal Laboratory Consortium — The GRUVE (Glenn Reconfigurable User-interface and Virtual reality Exploration) Lab is a reconfigurable, large screen display facility at Nasa Glenn Research Center....

Study on data acquisition system based on reconfigurable cache technology

Science.gov (United States)

Zhang, Qinchuan; Li, Min; Jiang, Jun

2018-03-01

Waveform capture rate is one of the key features of digital acquisition systems, which represents the waveform processing capability of the system in a unit time. The higher the waveform capture rate is, the larger the chance to capture elusive events is and the more reliable the test result is. First, this paper analyzes the impact of several factors on the waveform capture rate of the system, then the novel technology based on reconfigurable cache is further proposed to optimize system architecture, and the simulation results show that the signal-to-noise ratio of signal, capacity, and structure of cache have significant effects on the waveform capture rate. Finally, the technology is demonstrated by the engineering practice, and the results show that the waveform capture rate of the system is improved substantially without significant increase of system's cost, and the technology proposed has a broad application prospect.

A distributed, hardware reconfigurable and packet switched real-time control and data acquisition system

International Nuclear Information System (INIS)

Batista, A.J.N.; Combo, A.; Sousa, J.; Varandas, C.A.F.

2002-01-01

The architecture of a synchronized event-based control and data acquisition system that aims to improve significantly the performance of actual systems is presented. The design explores recent developments in data transport, signal processing and system synchronization. Data transport between the acquisition, processing and storing devices and at backplane level will be performed by InfiniBand, a low latency packet switched network standard. Data processing algorithms will be performed in a mixture of digital signal processors and reconfigurable field programmable gate arrays. Both devices will be programmed from a descriptive high-level mathematical language. Acquisition synchronization, data stamping and event management will be performed through a specialized low latency synchronous optical network for the time critical signals

Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

Science.gov (United States)

Brouwer, Randall Jay

1991-01-01

The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

PLA realizations for VLSI state machines

Science.gov (United States)

Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

1990-01-01

A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

Science.gov (United States)

Corliss, Walter F., II

1989-03-01

The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

Optically controlled reconfigurable antenna for 5G future broadband cellular communication networks

DEFF Research Database (Denmark)

Costa, I.F. da; Spadoti, D. H.; Cerqueira Sodre Jr., Arismar

2017-01-01

This paper presents an optically controlled reconfigurable antenna for millimetre-wave frequency range. Silicon switches are used to control the optical reconfiguration, modifying the frequency response and radiation pattern of the antenna design. Therefore, the system can switch between the ligh......This paper presents an optically controlled reconfigurable antenna for millimetre-wave frequency range. Silicon switches are used to control the optical reconfiguration, modifying the frequency response and radiation pattern of the antenna design. Therefore, the system can switch between...

Reconfigurable antennas radiations using plasma Faraday cage

OpenAIRE

Barro , Oumar Alassane; Himdi , Mohamed; Lafond , Olivier

2015-01-01

International audience; This letter presents a new reconfigurable plasma antenna associated with a Faraday cage. The Faraday cage is realized using a fluorescent lamp. A patch antenna with a broadside radiation pattern or a monopole antenna with an end-fire radiation pattern , operating at 2.45 GHz, is placed inside Faraday cage. The performance of the reconfigurable system is observed in terms of input reflection coefficient, gain and radiation pattern via simulation and measurement. It is s...

Terrain Adaptive Reconfiguration of Mobility

Data.gov (United States)

National Aeronautics and Space Administration — Develop an algorithm (and software) to automatically adapt a reconfigurable robot to different types of terrains for improved mobility, that compared to SOA:...

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

Science.gov (United States)

Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

2016-11-01

The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

Portable reconfigurable detection and assessment system

International Nuclear Information System (INIS)

Blattman, D.A.

1991-01-01

Rapidly changing geopolitical issues throughout the world have made the ability to effectively respond to political, military, terrorist and peace-keeping requirements increasingly important. Recent Middle East events indicate a continuing escalation in these activities. These activities are defining the requirements for a rapidly deployable, portable, real-time detection and assessment operational security system that is reconfigurable to site specific threats. This paper describes such a system Mobile Operational Detection and Assessment system (MODAS); a commercially-off-the shelf (COTS) integrated and reconfigurable hardware/software system solution for the ever-changing geopolitical security issues of the Nineties

Desenvolvimento de hardware reconfigurável de criptografia assimétrica

Directory of Open Access Journals (Sweden)

Otávio Souza Martins Gomes

2015-01-01

Full Text Available Este artigo apresenta o resultado parcial do desenvolvimento de uma interface de hardware reconfigurável para criptografia assimétrica que permite a troca segura de dados. Hardwares reconfiguráveis permitem o desenvolvimento deste tipo de dispositivo com segurança e flexibilidade e possibilitam a mudança de características no projeto com baixo custo e de forma rápida.Palavras-chave: Criptografia. Hardware. ElGamal. FPGA. Segurança. Development of an asymmetric cryptography reconfigurable harwadre ABSTRACTThis paper presents some conclusions and choices about the development of an asymmetric cryptography reconfigurable hardware interface to allow a safe data communication. Reconfigurable hardwares allows the development of this kind of device with safety and flexibility, and offer the possibility to change some features with low cost and in a fast way.Keywords: Cryptography. Hardware. ElGamal. FPGAs. Security.

Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

National Research Council Canada - National Science Library

Altmeyer, Ronald

2002-01-01

This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

Self-Healing Many-Core Architecture: Analysis and Evaluation

Directory of Open Access Journals (Sweden)

Arezoo Kamran

2016-01-01

Full Text Available More pronounced aging effects, more frequent early-life failures, and incomplete testing and verification processes due to time-to-market pressure in new fabrication technologies impose reliability challenges on forthcoming systems. A promising solution to these reliability challenges is self-test and self-reconfiguration with no or limited external control. In this work a scalable self-test mechanism for periodic online testing of many-core processor has been proposed. This test mechanism facilitates autonomous detection and omission of faulty cores and makes graceful degradation of the many-core architecture possible. Several test components are incorporated in the many-core architecture that distribute test stimuli, suspend normal operation of individual processing cores, apply test, and detect faulty cores. Test is performed concurrently with the system normal operation without any noticeable downtime at the application level. Experimental results show that the proposed test architecture is extensively scalable in terms of hardware overhead and performance overhead that makes it applicable to many-cores with more than a thousand processing cores.

PV Reconfiguration Systems: a Technical and Economic Study

Directory of Open Access Journals (Sweden)

Caruso M.

2017-03-01

Full Text Available Dynamical electrical array reconfiguration strategies for grid-connected PV systems have been proposed as solution to improve energy production due to the mismatch effect of PV plants during partial shading conditions. Strategies are based on the use of dynamic connections between PV panels given by the employment of switches that allow for each panel the series, parallel or exclusion connections, physically changing the electrical connections between the related PV modules, consequentially modifying the layout of the plant. Usually the cost of the dynamic matrix is not taken into account. This novel work evaluates the economic advantages obtained by the use of reconfiguration strategies in PV systems, by taking into consideration the price of energy due to incentives in different European and non-European countries and correlates it with the employment of two types of reconfigurators, with different internal structures. For each of the incentives proposed by the different Countries, the main strength and weakness points of the possible investment are highlighted and critically analyzed. From this analysis, it can be stated that the adoption of reconfiguration systems, in certain cases, can be a very convenient solution.

Towards Reconfigurable, Separable and Hard Real-Time Hybrid Simulation and Test Systems

Science.gov (United States)

Quartier, F.; Delatte, B.; Joubert, M.

2009-05-01

Formation flight needs several new technologies, new disciplines, new approaches and above all, more concurrent engineering by more players. One of the problems to be addressed are more complex simulation and test systems that are easy to re-configure to include parts of the target hardware and that can provide sufficient power to handle simulation cores that are requiring one to two orders of magnitude more processing power than the current technology provides. Critical technologies that are already addressed by CNES and Spacebel are study model reuse and simulator reconfigurability (Basiles), model portability (SMP2) and the federation of several simulators using HLA. Two more critical issues are addressed in ongoing R&D work by CNES and Spacebel and are covered by this paper and concern the time engineering and management. The first issue concerns separability (characterisation, identification and handling of separable subsystems) and the consequences on practical systems. Experiments on the Pleiades operational simulator have shown that adding precise simulation of instruments such as Doris and the Star Tracker can be added without significantly impacting overall performance. Improved time analysis leads to better system understanding and testability. The second issue concerns architectures for distributed hybrid simulators systems that provide hard real-time capabilities and can react with a relative time precision and jitter that is in the 10 to 50 µsecond range using mainstream PC's and mainstream Operating Systems. This opens a way to make smaller economic hardware test systems that can be reconfigured to make large hardware test systems without restarting development. Although such systems were considered next to impossible till now, distributed hard real-time systems are getting in reach when modern but mainstream electronics are used and when processor cores can be isolated and reserved for real-time cores. This requires a complete rethinking of the

An adaptive cryptographic accelerator for network storage security on dynamically reconfigurable platform

Science.gov (United States)

Tang, Li; Liu, Jing-Ning; Feng, Dan; Tong, Wei

2008-12-01

Existing security solutions in network storage environment perform poorly because cryptographic operations (encryption and decryption) implemented in software can dramatically reduce system performance. In this paper we propose a cryptographic hardware accelerator on dynamically reconfigurable platform for the security of high performance network storage system. We employ a dynamic reconfigurable platform based on a FPGA to implement a PowerPCbased embedded system, which executes cryptographic algorithms. To reduce the reconfiguration latency, we apply prefetch scheduling. Moreover, the processing elements could be dynamically configured to support different cryptographic algorithms according to the request received by the accelerator. In the experiment, we have implemented AES (Rijndael) and 3DES cryptographic algorithms in the reconfigurable accelerator. Our proposed reconfigurable cryptographic accelerator could dramatically increase the performance comparing with the traditional software-based network storage systems.

Trajectory Generation and Stability Analysis for Reconfigurable Klann Mechanism Based Walking Robot

Directory of Open Access Journals (Sweden)

Jaichandar Kulandaidaasan Sheba

2016-06-01

Full Text Available Reconfigurable legged robots based on one degree of freedom are highly desired because they are effective on rough and irregular terrains and they provide mobility in such terrain with simple control schemes. It is necessary that reconfigurable legged robots should maintain stability during rest and motion, with a minimum number of legs while maintaining their full range of walking patterns resulting from different gait configuration. In this paper we present a method to generate input trajectory for reconfigurable quadruped robots based on Klann mechanism to properly synchronize movement. Six useful gait cycles based on this reconfigurable Klann mechanism for quadruped robots has been clearly shown here. The platform stability for these six useful gait cycles are validated through simulated results which clearly shows the capabilities of reconfigurable design.

Efficient integration of plug-in electric vehicles via reconfigurable microgrids

International Nuclear Information System (INIS)

Kavousi-Fard, Abdollah; Khodaei, Amin

2016-01-01

This paper investigates the viability of the reconfigurable microgrids (RMGs) in facilitating the integration of plug-in electric vehicles (PEVs). The reconfiguration ability of microgrids, which is enabled by the use of remotely controlled switches (RCSs), will support the high penetration of PEVs and renewable distributed generators (DGs) while reducing the total operation cost and potentially enhance microgrid reliability. The objective of the proposed optimal scheduling problem is to minimize the total cost of power supply by distributed energy resources (DERs) and upstream network energy exchange, battery degradation cost in PEVs, cost of switching during the reconfiguration, and expected customer interruption costs as a reliability index. To address the high level of the uncertainties in the problem, a scenario-based stochastic framework is devised to capture the uncertainties associated with the charging and discharging values of PEVs, number of PEVs in each fleet, time of the daily trips for PEVs, hourly load consumption, hourly output power of renewable DGs, and hourly market price. The satisfying performance and merits of the proposed model are examined on a test microgrid. - Highlights: • Introduction of reconfigurable microgrids for providing flexible structure to manage electric loads. • Assessing the effects of the reconfiguration on the integration of PEVs. • Introduction of a stochastic framework for reducing operation and reliability costs in microgrids. • Introduction of a smart charge/discharge scheme for PEVs based on V2G during the reconfiguration.

Reconfiguring Cooperative Work by Visualizing EPR on Large Projected Screens

DEFF Research Database (Denmark)

Simonsen, Jesper

Simonsen, J. (2006): Reconfiguring Cooperative Work by Visualizing EPR on Large Projected Screens, Paper presented at the PDC 2006 workshop on: Reconfiguring Healthcare: Issues in Computer Supported Cooperative Work in Healthcare Environments. Participatory Design Conference, Trento, Italy, August...

Short-Term Load Forecasting Based Automatic Distribution Network Reconfiguration: Preprint

Energy Technology Data Exchange (ETDEWEB)

Jiang, Huaiguang [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Ding, Fei [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Zhang, Yingchen [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Jiang, Huaiguang [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Ding, Fei [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Zhang, Yingchen [National Renewable Energy Laboratory (NREL), Golden, CO (United States)

2017-07-26

In the traditional dynamic network reconfiguration study, the optimal topology is determined at every scheduled time point by using the real load data measured at that time. The development of load forecasting technique can provide accurate prediction of load power that will happen in future time and provide more information about load changes. With the inclusion of load forecasting, the optimal topology can be determined based on the predicted load conditions during the longer time period instead of using the snapshot of load at the time when the reconfiguration happens, and thus it can provide information to the distribution system operator (DSO) to better operate the system reconfiguration to achieve optimal solutions. Thus, this paper proposes a short-term load forecasting based approach for automatically reconfiguring distribution systems in a dynamic and pre-event manner. Specifically, a short-term and high-resolution distribution system load forecasting approach is proposed with support vector regression (SVR) based forecaster and parallel parameters optimization. And the network reconfiguration problem is solved by using the forecasted load continuously to determine the optimal network topology with the minimum loss at the future time. The simulation results validate and evaluate the proposed approach.

Reconfigurable Integrated Optoelectronics

Directory of Open Access Journals (Sweden)

Richard Soref

2011-01-01

Full Text Available Integrated optics today is based upon chips of Si and InP. The future of this chip industry is probably contained in the thrust towards optoelectronic integrated circuits (OEICs and photonic integrated circuits (PICs manufactured in a high-volume foundry. We believe that reconfigurable OEICs and PICs, known as ROEICs and RPICs, constitute the ultimate embodiment of integrated photonics. This paper shows that any ROEIC-on-a-chip can be decomposed into photonic modules, some of them fixed and some of them changeable in function. Reconfiguration is provided by electrical control signals to the electro-optical building blocks. We illustrate these modules in detail and discuss 3D ROEIC chips for the highest-performance signal processing. We present examples of our module theory for RPIC optical lattice filters already constructed, and we propose new ROEICs for directed optical logic, large-scale matrix switching, and 2D beamsteering of a phased-array microwave antenna. In general, large-scale-integrated ROEICs will enable significant applications in computing, quantum computing, communications, learning, imaging, telepresence, sensing, RF/microwave photonics, information storage, cryptography, and data mining.

The Complete Reconfiguration of Dendritic Gold

Science.gov (United States)

Paneru, Govind; Flanders, Bret

2014-03-01

Reconfigurability-by-design is an important strategy in modern materials science, as materials with this capability could potentially be used to confer hydrophobic, lipophobic, or anti-corrosive character to substrates in a regenerative manner. The present work extends the directed electrochemical nanowire assembly (DENA) methodology, which is a technique that employs alternating voltages to grow single crystalline metallic nanowires and nano-dendrites from simple salt solutions, to enable the complete dissolution of macroscopic arrays of metallic dendrites following their growth. Our main finding is that structural reconfiguration of dendritic gold is induced by changes in the MHz-level frequencies of voltages that are applied to the dendrites. Cyclic voltammetry and micro-Raman spectroscopy have been used to show that dendritic gold grows and dissolves by the same chemical mechanisms as bulk gold. Hence, the redox chemistry that occurs at the crystal-solution interface is no different than the established electrochemistry of gold. What differs in this process and allows for reconfiguration to occur is the diffusive behavior of the gold chloride molecules in the solution adjacent to the interface. We will present a simple model that captures the physics of this behavior.

Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware

Directory of Open Access Journals (Sweden)

Christophe Bobda

2009-01-01

Full Text Available We present a methodology based on self-organization to manage resources in networked embedded systems based on reconfigurable hardware. Two points are detailed in this paper, the monitoring system used to analyse the system and the Local Marketplaces Global Symbiosis (LMGS concept defined for self-organization of dynamically reconfigurable nodes.

Multilevel Simulation of Heterogeneous Reconfigurable Platforms

Directory of Open Access Journals (Sweden)

Damien Picard

2009-01-01

Full Text Available This paper presents a general system-level simulation and testing methodology for reconfigurable System-on-Chips, starting from behavioral specifications of system activities to multilevel simulations of accelerated tasks running on the reconfigurable circuit. The system is based on a common objectoriented environment that offers valuable debugging and probing facilities as well as integrated testing features. Our system brings these benefits to the hardware simulation, while enforcing validation through characterization tests and interoperability through on-demand mainstream tools connections. This framework has been partially developed in the scope of the EU Morpheus project and is used to validate our contribution to the spatial design task.

Hardware architecture and associated programming flow for the design of digital fault-tolerant systems

International Nuclear Information System (INIS)

Peyret, Thomas

2014-01-01

Whether in automotive with heat stress or in aerospace and nuclear field subjected to cosmic, neutron and gamma radiation, the environment can lead to the development of faults in electronic systems. These faults, which can be transient or permanent, will lead to erroneous results that are unacceptable in some application contexts. The use of so-called rad-hard components is sometimes compromised due to their high costs and supply problems associated with export rules. This thesis proposes a joint hardware and software approach independent of integration technology for using digital programmable devices in environments that generate faults. Our approach includes the definition of a Coarse Grained Re-configurable Architecture (CGRA) able to execute entire application code but also all the hardware and software mechanisms to make it tolerant to transient and permanent faults. This is achieved by the combination of redundancy and dynamic reconfiguration of the CGRA based on a library of configurations generated by a complete conception flow. This implemented flow relies on a flow to map a code represented as a Control and Data Flow Graph (CDFG) on the CGRA architecture by obtaining directly a large number of different configurations and allows to exploit the full potential of architecture. This work, which has been validated through experiments with applications in the field of signal and image processing, has been the subject of two publications in international conferences and of two patents. (author) [fr

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses.

Science.gov (United States)

Qiao, Ning; Mostafa, Hesham; Corradi, Federico; Osswald, Marc; Stefanini, Fabio; Sumislawska, Dora; Indiveri, Giacomo

2015-01-01

Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm(2), and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

Manipulating waves with LEGO{sup ®} bricks: A versatile experimental platform for metamaterial architectures

Energy Technology Data Exchange (ETDEWEB)

Celli, Paolo, E-mail: pcelli@umn.edu; Gonella, Stefano, E-mail: sgonella@umn.edu [Department of Civil, Environmental, and Geo- Engineering, University of Minnesota, Minneapolis, Minnesota 55455 (United States)

2015-08-24

In this letter, we discuss a versatile, fully reconfigurable experimental platform for the investigation of phononic phenomena in metamaterial architectures. The approach revolves around the use of 3D laser vibrometry to reconstruct global and local wavefield features in specimens obtained through simple arrangements of LEGO{sup ®} bricks on a thin baseplate. The agility by which it is possible to reconfigure the brick patterns into a nearly endless spectrum of topologies makes this an effective approach for rapid experimental proof of concept, as well as a powerful didactic tool, in the arena of phononic crystals and metamaterials engineering. We use our platform to provide a compelling visual illustration of important spatial wave manipulation effects (waveguiding and seismic isolation), and to elucidate fundamental dichotomies between Bragg-based and locally resonant bandgap mechanisms.

Periodic Application of Concurrent Error Detection in Processor Array Architectures. PhD. Thesis -

Science.gov (United States)

Chen, Paul Peichuan

1993-01-01

Processor arrays can provide an attractive architecture for some applications. Featuring modularity, regular interconnection and high parallelism, such arrays are well-suited for VLSI/WSI implementations, and applications with high computational requirements, such as real-time signal processing. Preserving the integrity of results can be of paramount importance for certain applications. In these cases, fault tolerance should be used to ensure reliable delivery of a system's service. One aspect of fault tolerance is the detection of errors caused by faults. Concurrent error detection (CED) techniques offer the advantage that transient and intermittent faults may be detected with greater probability than with off-line diagnostic tests. Applying time-redundant CED techniques can reduce hardware redundancy costs. However, most time-redundant CED techniques degrade a system's performance.

El Diseño Modular en el contexto del desarrollo de Máquinas Herramienta Reconfigurables. // Modular Design in the development of reconfigurable Machine Tools´ context.

Directory of Open Access Journals (Sweden)

R. Pérez Rodríguez

2005-05-01

Full Text Available Las tendencias actuales en los procesos de manufactura reflejan los cambios en las demandas de los clientes. En nuestrosdías, el mercado requiere inexorablemente de productos cada vez más personalizados, por lo que se tiende de unaproducción masiva hacia un tipo específico de producción, en menos tiempo y con menos costos de producción. Enrespuesta a esta necesidad, la nueva generación de máquinas herramienta debe de ser reconfigurable e inteligente. Lascaracterísticas principales de las Máquinas Reconfigurables e Inteligentes son la modularidad, convertibilidad, flexibilidady efectividad en los costos. Este artículo presenta un enfoque para el diseño modular de máquinas herramienta, basado en elportafolio de productos del constructor de máquinas. La metodología parte de un conjunto de requerimientos funcionalesdefinidos por el constructor de máquinas y ofrece una descripción de los posibles módulos que pueden ser desarrolladospara una determinada máquina herramienta reconfigurable.Palabras claves: Diseño modular, máquinas herramienta, reconfigurable, inteligente.___________________________________________________________________________Abstract.The manufacturing tendencies reflect the changes on the customer demands. Nowadays, the market is constantly requiringmore customized products, moving from mass production to “one-of-a-kind production” in less time with lower productioncosts. In response to this need, the next generation of machine tools should be reconfigurable and intelligent.Reconfigurability allows for the reduction of machine design lead time, machine set-up and ramp-up time. The principalcharacteristics of the Reconfigurable and Intelligent Machines are modularity, convertibility, flexibility and costeffectiveness.This paper presents an approach for the design of machine tools modules, based on the product portfolio ofthe machine tool builder. The methodology takes as input a set of functional requirements

THE ARCHITECTURAL PATRONAGE AND POLITICAL PROWESS OF HEROD THE GREAT

OpenAIRE

Vivian A. Laughlin

2016-01-01

After supporting Marc Antony in the Battle of Actium (31 B.C.), King Herod, fearful of losing his power, went to Rome, apologized to Augustus and assured him that he was his biggest supporter. Augustus, giving Herod an opportunity to redeem himself, allowed him to return to Judea as King of the Jews. In an effort for Herod to express his continued commitment to Rome, he reconfigured his building styles by making cities that  would depict Rome in the Levant. Herod created architecture that imp...

Hierarchical Control Architecture for Demand Response in Smart Grid Scenario

DEFF Research Database (Denmark)

Bhattarai, Bishnu Prasad; Bak-Jensen, Birgitte; Mahat, Pukar

2013-01-01

, a number of issues, including DR enabling technologies, control strategy, and control architecture, are still under discussion. This paper outlines novel control requirements based on the categorization of existing DR techniques. More specifically, the roles and responsibilities of smart grid actors...... effective tool for optimum asset utilization and to avoid or delay the need for new infrastructure investment. Furthermore, most of the power networks are under the process of reconfiguration to realize the concept of smart grid and are at the transforming stage to support various forms of DR. However...... for every DR category are allotted and their mode of interactions to coordinate individual as well as coordinative goals is described. Next, hierarchical control architecture (HCA) is developed for the overall coordination of control strategies for individual DR categories. The involved issues are discussed...

Orientalist Orientals: re-conceptualizing Ottoman architecture in the late Empire

Directory of Open Access Journals (Sweden)

Sibel Bozdogan

2015-12-01

Full Text Available Review of Ahmet Ersoy, Architecture and the Late Ottoman Historical Imaginary: Reconfiguring the Architectural Past in a Modernizing Empire: Late Ottoman Empire’s concerted effort to forge a modern imperial identity to better position itself within the emerging world system was accompanied by a proto-nationalist desire for an authentic cultural past. In the field of art and architecture, the result was a new interest and patriotic pride in the Islamic artistic and architectural heritage of the Empire, along with an intense period of creative engagement with European artistic and scholarly discourses. The book offers a meticulously historicized account of what emerged as a major intellectual effort to construct a genealogy for Ottoman architecture, to make it intelligible in terms of Western architectural theory and above all, to recast it as a historically evolving style capable of revival in the modern world. In doing so, it critically engages with recent scholarly debates on modernity, historicism, romanticism, orientalism, nationalism, revivalism, cosmopolitanism, authenticity, eclecticism and hybridity among other topics. Taking issue with both the received “westernization paradigm” and its companion, the notorious “decline thesis” in terms of which the architecture of Ottoman Tanzimat has long been written, it gives us a more complex, more nuanced, more cosmopolitan and more ambivalent picture. As such, it makes a major contribution to Ottoman/ Turkish studies, to the historiography of Islamic architecture and to cross-cultural studies in general.

Configuration Method Design for Reconfigurable Manufacturing System with the aid of Plant Simulation

DEFF Research Database (Denmark)

Li, Yang; Zhang, Shuai; Bilberg, Arne

2014-01-01

A new Reconfigurable Manufacturing System structure has been recently designed by a large consumer goods manufacturer in Europe, aiming to balance the performance of productivity and flexibility. This article shows an exploratory research on the (re)configuration procedure of the new RMS structure....... Following the procedure which is designed in this paper, the (re)configuration of RMS can be managed as part of the daily operation with the help of computer simulation. Keywords: Plant Simulation, Tecnomatix, Reconfigurable Manufacturing System, modular manufacturing....

Centralised versus Decentralised Control Reconfiguration for Collaborating Underwater Robots

DEFF Research Database (Denmark)

Furno, Lidia; Nielsen, Mikkel Cornelius; Blanke, Mogens

2015-01-01

The present paper introduces an approach to fault-tolerant reconfiguration for collaborating underwater robots. Fault-tolerant reconfiguration is obtained using the virtual actuator approach, Steen (2005). The paper investigates properties of a centralised versus a decentralised implementation an...... an underwater drill needs to be transported and positioned by three collaborating robots as part of an underwater autonomous operation....

Compact Interconnection Networks Based on Quantum Dots

Science.gov (United States)

Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

2003-01-01

Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary

Applications of the scalable coherent interface to data acquisition at LHC

CERN Document Server

Bogaerts, A; Divià, R; Müller, H; Parkman, C; Ponting, P J; Skaali, B; Midttun, G; Wormald, D; Wikne, J; Falciano, S; Cesaroni, F; Vinogradov, V I; Kristiansen, E H; Solberg, B; Guglielmi, A M; Worm, F H; Bovier, J; Davis, C; CERN. Geneva. Detector Research and Development Committee

1991-01-01

We propose to use the Scalable Coherent Interface (SCI) as a very high speed interconnect between LHC detector data buffers and farms of commercial trigger processors. Both the global second and third level trigger can be based on SCI as a reconfigurable and scalable system. SCI is a proposed IEEE standard which uses fast point-to-point links to provide computer-bus like services. It can connect a maximum of 65 536 nodes (memories or processors), providing data transfer rates of up to 1 Gbyte/s. Scalable data acquisition systems can be built using either simple SCI rings or complex switches. The interconnections may be flat cables, coaxial cables, or optical fibres. SCI protocols have been entirely implemented in VLSI, resulting in a significant simplification of data acquisition software. Novel SCI features allow efficient implementation of both data and processor driven readout architectures. In particular, a very efficient implementation of the third level trigger can be achieved by combining SCI's shared ...

Green provisioning of the traffic partition grooming in robust, reconfigurable and heterogeneous optical networks

Science.gov (United States)

Hou, Weigang; Yu, Yao; Song, Qingyang; Gong, Xiaoxue

2013-01-01

In recent years, various high-speed network architectures have been widespread deployed. Dense Wavelength Division Multiplexing (DWDM) has gained favor as a terabit solution. The optical circuit switching has also been provided for "sub-rate" aggregation. Such that, the granular types of demands tend to be diverse and must be evaluated. However, current dedicated optical networks do not offer sufficient flexibility to satisfy the requirements of demands with such wide range of granularities. The traffic grooming becomes a power-efficient one only when it does not utilize the aggregation of Coarse-Granularity (CG) demands. The waveband switching merely provides port-cost-effective connections for CG demands regardless of fine-granularity ones. Consequently, in this paper, we devise a heterogeneous grooming method called traffic partition grooming. It combines the power efficiency advantage of the traffic grooming under fine-granularity environment and the port savings advantage of the waveband switching under coarse-granularity environment to provide green provisioning. In addition, the optical virtual topology self-reconfigures along with various optimization objectives variation and has the robustness to determine the pre-unknown information. This paper is also the first work on investigating the issue of Robust, Reconfigurable and Heterogeneous Optical Networking (R2HON). The effective green provisioning and OPEX savings of our R2HON have been demonstrated by numerical simulations.

Software Productivity of Field Experiments Using the Mobile Agents Open Architecture with Workflow Interoperability

Science.gov (United States)

Clancey, William J.; Lowry, Michael R.; Nado, Robert Allen; Sierhuis, Maarten

2011-01-01

We analyzed a series of ten systematically developed surface exploration systems that integrated a variety of hardware and software components. Design, development, and testing data suggest that incremental buildup of an exploration system for long-duration capabilities is facilitated by an open architecture with appropriate-level APIs, specifically designed to facilitate integration of new components. This improves software productivity by reducing changes required for reconfiguring an existing system.

Compact, Frequency Reconfigurable, Printed Monopole Antenna

Directory of Open Access Journals (Sweden)

Ricardo Gonçalves

2012-01-01

Full Text Available This paper proposes a possible implementation of a compact printed monopole antenna, useful to operate in UMTS and WLAN bands. In order to accomplish that, a miniaturization technique based on the application of chip inductors is used in conjunction with frequency reconfiguration capability. The chip inductors change the impedance response of the monopole, allowing to reduce the resonant frequency. In order to be able to operate the antenna in these two different frequencies, an antenna reconfiguration technique based on PIN diodes is applied. This procedure allows the change of the active form of the antenna leading to a shift in the resonant frequency. The prototype measurements show good agreement with the simulation results.

A Modular Re-configurable Rover System

Science.gov (United States)

Bouloubasis, A.; McKee, G.; Active Robotics Lab

design allows the MTR to lift, lower, roll or tilt its body. It also provides the ability to lift any of the legs by nearly 300mm, enhancing internal re-configurability and therefore rough terrain stability off the robotic vehicle. A modular software and control architecture will be used so that integration to, and operation through the MTR, of different Packs can be demonstrated. An on-board high-level controller [4] will communicate with a small network of micro-controllers through an RS485 bus. Additional processing power could be obtained through a Pack with equivalent or higher computational capabilities. 1 The nature of the system offers many opportunities for behavior based control. The control system must accommodate not only rover based behaviors like obstacle avoidance and vehicle stabilization, but also any additional behaviors that different Packs may introduce. The Ego-Behavior Architecture (EBA) [5] comprises a number of behaviors which operate autonomously and independent of each other. This facilitates the design and suits the operation of the MTR since it fulfills the need for uncomplicated assimilation of new behaviors in the existing architecture. Our work at the moment focuses on the design and construction of the mechanical and electronic systems for the MTR and an associated Pack. References [1] NASA, Human Exploration of Mars: The Reference Mission (Version 3.0 with June, 1998 Addendum) of the NASA Mars Exploration Study Team, Exploration Office, Advanced Development Office, Lyndon B. Johnson Space Center, Houston, TX 77058, June, 1998. [2] A. Trebi-Ollennu, H Das Nayer, H Aghazarian, A ganino, P Pirjanian, B Kennedy, T Huntsberger and P Schenker, Mars Rover Pair Cooperatively Transporting a Long Payload, in Proceedings of the 2002 IEEE International Conference on Robotics and Automation, May 2002, pp. 3136-3141. [3] A. K. Bouloubasis, G. T McKee, P. S. Schenker, A Behavior-Based Manipulator for Multi-Robot Transport Tasks, in proceedings of the

Using instability to reconfigure smart structures in a spring-mass model

Science.gov (United States)

Zhang, Jiaying; McInnes, Colin R.

2017-07-01

Multistable phenomenon have long been used in mechanism design. In this paper a subset of unstable configurations of a smart structure model will be used to develop energy-efficient schemes to reconfigure the structure. This new concept for reconfiguration uses heteroclinic connections to transition the structure between different unstable equal-energy states. In an ideal structure model zero net energy input is required for the reconfiguration, compared to transitions between stable equilibria across a potential barrier. A simple smart structure model is firstly used to identify sets of equal-energy unstable configurations using dynamical systems theory. Dissipation is then added to be more representative of a practical structure. A range of strategies are then used to reconfigure the smart structure using heteroclinic connections with different approaches to handle dissipation.

Autonomous Reconfiguration Procedures for EJB-based Enterprise Applications

OpenAIRE

Vogel, Thomas; Bruhn, Jens; Wirtz, Guido

2018-01-01

Enterprise Applications (EA) are complex software systems for supporting the business of companies. Evolution of an EA should not affect its availability, e.g., because of a temporal shutdown, business operations may be affected. One possibility to address this problem is the seamless reconfiguration of the affected EA, i.e., applying the relevant changes while the system is running. Our approach to seamless reconfiguration focuses on component-oriented EAs. It is based on the Autonomic Compu...

Operation of a Fast-RICH Prototype with VLSI readout electronics

Energy Technology Data Exchange (ETDEWEB)

Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

1994-04-01

We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

Dynamic Reconfiguration in Mobile Systems

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Glesner, Manfred; Zipf, Peter; Smit, L.T.; Havinga, Paul J.M.; Heysters, P.M.; Renovell, Michel; Rosien, M.A.J.

Dynamically reconfigurable systems have the potential of realising efficient systems as well as providing adaptability to changing system requirements. Such systems are suitable for future mobile multimedia systems that have limited battery resources, must handle diverse data types, and must operate

Reconfiguration in Mobile Multimedia Systems

NARCIS (Netherlands)

Smit, Gerardus Johannes Maria; Havinga, Paul J.M.; Bos, M.; Smit, L.T.; Heysters, P.M.

2000-01-01

Dynamically reconfigurable systems offer the potential for realising efficient systems as well as providing adaptability to changing system requirements. Such systems are suitable for future mobile multimedia systems that have limited battery resources, must handle diverse data types, and must

Reconfigurable, Intelligently-Adaptive, Communication System, an SDR Platform

Science.gov (United States)

Roche, Rigoberto J.; Shalkhauser, Mary Jo; Hickey, Joseph P.; Briones, Janette C.

2016-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework to abstract the application software from the radio platform hardware. STRS aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. The NASA Glenn Research Center (GRC) team made a software defined radio (SDR) platform STRS compliant by adding an STRS operating environment and a field programmable gate array (FPGA) wrapper, capable of implementing each of the platforms interfaces, as well as a test waveform to exercise those interfaces. This effort serves to provide a framework toward waveform development onto an STRS compliant platform to support future space communication systems for advanced exploration missions. The use of validated STRS compliant applications provides tested code with extensive documentation to potentially reduce risk, cost and e ort in development of space-deployable SDRs. This paper discusses the advantages of STRS, the integration of STRS onto a Reconfigurable, Intelligently-Adaptive, Communication System (RIACS) SDR platform, and the test waveform and wrapper development e orts. The paper emphasizes the infusion of the STRS Architecture onto the RIACS platform for potential use in next generation flight system SDRs for advanced exploration missions.

A Re-configurable On-line Learning Spiking Neuromorphic Processor comprising 256 neurons and 128K synapses

Directory of Open Access Journals (Sweden)

Ning eQiao

2015-04-01

Full Text Available Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm 2 , and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities.

Reconfigurable manufacturing execution system for pipe cutting

Science.gov (United States)

Yin, Y. H.; Xie, J. Y.

2011-08-01

This article presents a reconfigurable manufacturing execution system (RMES) filling the gap between enterprise resource planning and resource layer for pipe-cutting production with mass customisation and rapid adaptation to dynamic market, which consists of planning and scheduling layer and executive control layer. Starting from customer's task and process requirements, the cutting trajectories are planned under generalised mathematical model able to reconfigure in accordance with various intersecting types' joint, and all tasks are scheduled by nesting algorithm to maximise the utilisation rate of rough material. This RMES for pipe cutting has been effectively implemented in more than 100 companies.

Reconfigurable Robust Routing for Mobile Outreach Network

Science.gov (United States)

Lin, Ching-Fang

2010-01-01

The Reconfigurable Robust Routing for Mobile Outreach Network (R3MOO N) provides advanced communications networking technologies suitable for the lunar surface environment and applications. The R3MOON techn ology is based on a detailed concept of operations tailored for luna r surface networks, and includes intelligent routing algorithms and wireless mesh network implementation on AGNC's Coremicro Robots. The product's features include an integrated communication solution inco rporating energy efficiency and disruption-tolerance in a mobile ad h oc network, and a real-time control module to provide researchers an d engineers a convenient tool for reconfiguration, investigation, an d management.

A Novel Design of Frequency Reconfigurable Antenna for UWB Application

Science.gov (United States)

Yang, Xiaolin; Yu, Ziliang; Wu, Zheng; Shen, Huajiao

2016-09-01

In this paper, we present a novel frequency reconfigurable antenna which could be easily operate in a single notched-band (WiMAX (3.3-3.6 GHz)) UWB frequency band, another single notched-band (WLAN (5-6 GHz)) UWB frequency band and the dual band-notched UWB frequency band (the stopband covers the WiMAX (3.3-3.6 GHz) and WLAN (5-6 GHz)). The reconfigurability is achieved by changing the states of PIN diodes. The simulated results are in agreement well with the measured results. And the measured patterns are slightly changed with antenna reconfiguration. The proposed antenna is a good candidate for various UWB applications.

Modular, Reconfigurable, High-Energy Technology Development

Science.gov (United States)

Carrington, Connie; Howell, Joe

2006-01-01

The Modular, Reconfigurable High-Energy (MRHE) Technology Demonstrator project was to have been a series of ground-based demonstrations to mature critical technologies needed for in-space assembly of a highpower high-voltage modular spacecraft in low Earth orbit, enabling the development of future modular solar-powered exploration cargo-transport vehicles and infrastructure. MRHE was a project in the High Energy Space Systems (HESS) Program, within NASA's Exploration Systems Research and Technology (ESR&T) Program. NASA participants included Marshall Space Flight Center (MSFC), the Jet Propulsion Laboratory (JPL), and Glenn Research Center (GRC). Contractor participants were the Boeing Phantom Works in Huntsville, AL, Lockheed Martin Advanced Technology Center in Palo Alto, CA, ENTECH, Inc. in Keller, TX, and the University of AL Huntsville (UAH). MRHE's technical objectives were to mature: (a) lightweight, efficient, high-voltage, radiation-resistant solar power generation (SPG) technologies; (b) innovative, lightweight, efficient thermal management systems; (c) efficient, 100kW-class, high-voltage power delivery systems from an SPG to an electric thruster system; (d) autonomous rendezvous and docking technology for in-space assembly of modular, reconfigurable spacecraft; (e) robotic assembly of modular space systems; and (f) modular, reconfigurable distributed avionics technologies. Maturation of these technologies was to be implemented through a series of increasingly-inclusive laboratory demonstrations that would have integrated and demonstrated two systems-of-systems: (a) the autonomous rendezvous and docking of modular spacecraft with deployable structures, robotic assembly, reconfiguration both during assembly and (b) the development and integration of an advanced thermal heat pipe and a high-voltage power delivery system with a representative lightweight high-voltage SPG array. In addition, an integrated simulation testbed would have been developed

Machine Learning Control For Highly Reconfigurable High-Order Systems

Science.gov (United States)

2015-01-02

calibration and applications,” Mechatronics and Embedded Systems and Applications (MESA), 2010 IEEE/ASME International Conference on, IEEE, 2010, pp. 38–43...AFRL-OSR-VA-TR-2015-0012 MACHINE LEARNING CONTROL FOR HIGHLY RECONFIGURABLE HIGH-ORDER SYSTEMS John Valasek TEXAS ENGINEERING EXPERIMENT STATION...DIMENSIONAL RECONFIGURABLE SYSTEMS FA9550-11-1-0302 Period of Performance 1 July 2011 – 29 September 2014 John Valasek Aerospace Engineering

Design and Evaluation of a Reconfigurable Manufacturing System

DEFF Research Database (Denmark)

Zhang, Shuai; Li, Yang; Bilberg, Arne

2014-01-01

In modern manufacturing industry, reconfigurable manufacturing system (RMS) is a promising concept in the research arena. A new RMS system structure has been recently designed by a large consumer goods manufacturer in Europe, aiming to improve its production efficiency. This article shows...... implemented in this consumer goods manufacturer can be effectively (re)configured as part of the daily operations, and the configuration is analyzed by computer simulation before release. Flexibility can be increased considerably meanwhile the system can maintain an acceptable productivity....

Tunable and reconfigurable multi-tap microwave photonic filter based on dynamic Brillouin gratings in fibers.

Science.gov (United States)

Sancho, J; Primerov, N; Chin, S; Antman, Y; Zadok, A; Sales, S; Thévenaz, L

2012-03-12

We propose and experimentally demonstrate new architectures to realize multi-tap microwave photonic filters, based on the generation of a single or multiple dynamic Brillouin gratings in polarization maintaining fibers. The spectral range and selectivity of the proposed periodic filters is extensively tunable, simply by reconfiguring the positions and the number of dynamic gratings along the fiber respectively. In this paper, we present a complete analysis of three different configurations comprising a microwave photonic filter implementation: a simple notch-type Mach-Zehnder approach with a single movable dynamic grating, a multi-tap performance based on multiple dynamic gratings and finally a stationary grating configuration based on the phase modulation of two counter-propagating optical waves by a common pseudo-random bit sequence (PRBS).

A Framework for Hardware-Accelerated Services Using Partially Reconfigurable SoCs

Directory of Open Access Journals (Sweden)

MACHIDON, O. M.

2016-05-01

Full Text Available The current trend towards ?Everything as a Service? fosters a new approach on reconfigurable hardware resources. This innovative, service-oriented approach has the potential of bringing a series of benefits for both reconfigurable and distributed computing fields by favoring a hardware-based acceleration of web services and increasing service performance. This paper proposes a framework for accelerating web services by offloading the compute-intensive tasks to reconfigurable System-on-Chip (SoC devices, as integrated IP (Intellectual Property cores. The framework provides a scalable, dynamic management of the tasks and hardware processing cores, based on dynamic partial reconfiguration of the SoC. We have enhanced security of the entire system by making use of the built-in detection features of the hardware device and also by implementing active counter-measures that protect the sensitive data.

Carbon nanotube based VLSI interconnects analysis and design

CERN Document Server

Kaushik, Brajesh Kumar

2015-01-01

The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

Design of reconfigurable logic controllers

CERN Document Server

Bukowiec, Arkadiusz; Doligalski, Michał; Tkacz, Jacek

2016-01-01

This book presents the original concepts and modern techniques for specification, synthesis, optimisation and implementation of parallel logical control devices. It deals with essential problems of reconfigurable control systems like dependability, modularity and portability. Reconfigurable systems require a wider variety of design and verification options than the application-specific integrated circuits. The book presents a comprehensive selection of possible design techniques. The diversity of the modelling approaches covers Petri nets, state machines and activity diagrams. The preferences of the presented optimization and synthesis methods are not limited to increasing of the efficiency of resource use. One of the biggest advantages of the presented methods is the platform independence, the FPGA devices and single board computers are some of the examples of possible platforms. These issues and problems are illustrated with practical cases of complete control systems. If you expect a new look at the recon...

Reconfigurable engineered motile semiconductor microparticles.

Science.gov (United States)

Ohiri, Ugonna; Shields, C Wyatt; Han, Koohee; Tyler, Talmage; Velev, Orlin D; Jokerst, Nan

2018-05-03

Locally energized particles form the basis for emerging classes of active matter. The design of active particles has led to their controlled locomotion and assembly. The next generation of particles should demonstrate robust control over their active assembly, disassembly, and reconfiguration. Here we introduce a class of semiconductor microparticles that can be comprehensively designed (in size, shape, electric polarizability, and patterned coatings) using standard microfabrication tools. These custom silicon particles draw energy from external electric fields to actively propel, while interacting hydrodynamically, and sequentially assemble and disassemble on demand. We show that a number of electrokinetic effects, such as dielectrophoresis, induced charge electrophoresis, and diode propulsion, can selectively power the microparticle motions and interactions. The ability to achieve on-demand locomotion, tractable fluid flows, synchronized motility, and reversible assembly using engineered silicon microparticles may enable advanced applications that include remotely powered microsensors, artificial muscles, reconfigurable neural networks and computational systems.

Content-addressable read/write memories for image analysis

Science.gov (United States)

Snyder, W. E.; Savage, C. D.

1982-01-01

The commonly encountered image analysis problems of region labeling and clustering are found to be cases of search-and-rename problem which can be solved in parallel by a system architecture that is inherently suitable for VLSI implementation. This architecture is a novel form of content-addressable memory (CAM) which provides parallel search and update functions, allowing speed reductions down to constant time per operation. It has been proposed in related investigations by Hall (1981) that, with VLSI, CAM-based structures with enhanced instruction sets for general purpose processing will be feasible.

Functional verification of dynamically reconfigurable FPGA-based systems

CERN Document Server

Gong, Lingkan

2015-01-01

This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an i...

Adaptive laser link reconfiguration using constraint propagation

Science.gov (United States)

Crone, M. S.; Julich, P. M.; Cook, L. M.

1993-01-01

This paper describes Harris AI research performed on the Adaptive Link Reconfiguration (ALR) study for Rome Lab, and focuses on the application of constraint propagation to the problem of link reconfiguration for the proposed space based Strategic Defense System (SDS) Brilliant Pebbles (BP) communications system. According to the concept of operations at the time of the study, laser communications will exist between BP's and to ground entry points. Long-term links typical of RF transmission will not exist. This study addressed an initial implementation of BP's based on the Global Protection Against Limited Strikes (GPALS) SDI mission. The number of satellites and rings studied was representative of this problem. An orbital dynamics program was used to generate line-of-site data for the modeled architecture. This was input into a discrete event simulation implemented in the Harris developed COnstraint Propagation Expert System (COPES) Shell, developed initially on the Rome Lab BM/C3 study. Using a model of the network and several heuristics, the COPES shell was used to develop the Heuristic Adaptive Link Ordering (HALO) Algorithm to rank and order potential laser links according to probability of communication. A reduced set of links based on this ranking would then be used by a routing algorithm to select the next hop. This paper includes an overview of Constraint Propagation as an Artificial Intelligence technique and its embodiment in the COPES shell. It describes the design and implementation of both the simulation of the GPALS BP network and the HALO algorithm in COPES. This is described using a 59 Data Flow Diagram, State Transition Diagrams, and Structured English PDL. It describes a laser communications model and the heuristics involved in rank-ordering the potential communication links. The generation of simulation data is described along with its interface via COPES to the Harris developed View Net graphical tool for visual analysis of communications

Reconfigurable Wave Velocity Transmission Lines for Phased Arrays

Science.gov (United States)

Host, Nick; Chen, Chi-Chih; Volakis, John L.; Miranda, Felix

2013-01-01

Phased array antennas showcase many advantages over mechanically steered systems. However, they are also more complex, heavy and most importantly costly. This presentation paper presents a concept which overcomes these detrimental attributes by eliminating all of the phase array backend (including phase shifters). Instead, a wave velocity reconfigurable transmission line is used in a series fed array arrangement to allow phase shifting with one small (100mil) mechanical motion. Different configurations of the reconfigurable wave velocity transmission line are discussed and simulated and experimental results are presented.

Distributed sensor and actuator reconfiguration for fault-tolerant networked control systems

NARCIS (Netherlands)

Herdeiro Teixeira, A.M.; Araujo, Jose; Sandberg, Henrik; Johansson, Karl H.

2017-01-01

In this paper, we address the problem of distributed reconfiguration of networked control systems upon the removal of misbehaving sensors and actuators. In particular, we consider systems with redundant sensors and actuators cooperating to recover from faults. Reconfiguration is performed while

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding

Science.gov (United States)

Lapotre, Vianney; Gogniat, Guy; Baghdadi, Amer; Diguet, Jean-Philippe

2017-12-01

The multiplication of connected devices goes along with a large variety of applications and traffic types needing diverse requirements. Accompanying this connectivity evolution, the last years have seen considerable evolutions of wireless communication standards in the domain of mobile telephone networks, local/wide wireless area networks, and Digital Video Broadcasting (DVB). In this context, intensive research has been conducted to provide flexible turbo decoder targeting high throughput, multi-mode, multi-standard, and power consumption efficiency. However, flexible turbo decoder implementations have not often considered dynamic reconfiguration issues in this context that requires high speed configuration switching. Starting from this assessment, this paper proposes the first solution that allows frame-by-frame run-time configuration management of a multi-processor turbo decoder without compromising the decoding performances.

Integration of the Reconfigurable Self-Healing eDNA Architecture in an Embedded System

DEFF Research Database (Denmark)

Boesen, Michael Reibel; Keymeulen, Didier; Madsen, Jan

2011-01-01

In this work we describe the first real world case study for the self-healing eDNA (electronic DNA) architecture by implementing the control and data processing of a Fourier Transform Spectrometer (FTS) on an eDNA prototype. For this purpose the eDNA prototype has been ported from a Xilinx Virtex 5...

A novel approach to gait synchronization and transition for reconfigurable walking platforms

Directory of Open Access Journals (Sweden)

Shunsuke Nansai

2015-04-01

Full Text Available Legged robots based on one degree-of-freedom reconfigurable planar leg mechanisms, that are capable of generating multiple useful gaits, are highly desired due to the possibility of handling environments and tasks of high complexity while maintaining simple control schemes. An essential consideration in these reconfigurable legged robots is to attain stability in motion, at rest as well as while transforming from one configuration to another with the minimum number of legs as long as the full range of their walking patterns, resulting from the different gait cycles of their legs, is achieved. To this end, in this paper, we present a method for the generation of input joint trajectories to properly synchronize the movement of quadruped robots with reconfigurable legs. The approach is exemplified in a four-legged robot with reconfigurable Jansen legs capable of generating up to six useful different gait cycles. The proposed technique is validated through simulated results that show the platform׳s stability across its six feasible walking patterns and during gait transition phases, thus considerably extending the capabilities of the non-reconfigurable design.

High-Performance Monitoring Architecture for Large-Scale Distributed Systems Using Event Filtering

Science.gov (United States)

Maly, K.

1998-01-01

Monitoring is an essential process to observe and improve the reliability and the performance of large-scale distributed (LSD) systems. In an LSD environment, a large number of events is generated by the system components during its execution or interaction with external objects (e.g. users or processes). Monitoring such events is necessary for observing the run-time behavior of LSD systems and providing status information required for debugging, tuning and managing such applications. However, correlated events are generated concurrently and could be distributed in various locations in the applications environment which complicates the management decisions process and thereby makes monitoring LSD systems an intricate task. We propose a scalable high-performance monitoring architecture for LSD systems to detect and classify interesting local and global events and disseminate the monitoring information to the corresponding end- points management applications such as debugging and reactive control tools to improve the application performance and reliability. A large volume of events may be generated due to the extensive demands of the monitoring applications and the high interaction of LSD systems. The monitoring architecture employs a high-performance event filtering mechanism to efficiently process the large volume of event traffic generated by LSD systems and minimize the intrusiveness of the monitoring process by reducing the event traffic flow in the system and distributing the monitoring computation. Our architecture also supports dynamic and flexible reconfiguration of the monitoring mechanism via its Instrumentation and subscription components. As a case study, we show how our monitoring architecture can be utilized to improve the reliability and the performance of the Interactive Remote Instruction (IRI) system which is a large-scale distributed system for collaborative distance learning. The filtering mechanism represents an Intrinsic component integrated

Development of reconfigurable analog and digital circuits for plasma diagnostics measurement systems

International Nuclear Information System (INIS)

Srivastava, Amit Kumar; Sharma, Atish; Raval, Tushar

2009-01-01

In long pulse discharge tokamak, a large number of diagnostic channels are being used to understand the complex behavior of plasma. Different diagnostics demand different types of analog and digital processing for plasma parameters measurement. This leads to variable requirements of signal processing for diagnostic measurement. For such types of requirements, we have developed hardware with reconfigurable electronic devices, which provide flexible solution for rapid development of measurement system. Here the analog processing is achieved by Field Programmable Analog Array (FPAA) integrated circuit while reconfigurable digital devices (CPLD/FPGA) achieve digital processing. FPAA's provide an ideal integrated platform for implementing low to medium complexity analog signal processing. With dynamic reconfigurability, the functionality of the FPAA can be reconfigured in-system by the designer or on the fly by a microprocessor. This feature is quite useful to manipulate the tuning or the construction of any part of the analog circuit without interrupting operation of the FPAA, thus maintaining system integrity. The hardware operation control logic circuits are configured in the reconfigurable digital devices (CPLD/FPGA) to control proper hardware functioning. These reconfigurable devices provide the design flexibility and save the component space on the board. It also provides the flexibility for various setting through software. The circuit controlling commands are either issued by computer/processor or generated by circuit itself. (author)

Reconfigurable dual-band metamaterial antenna based on liquid crystals

Science.gov (United States)

Che, Bang-Jun; Meng, Fan-Yi; Lyu, Yue-Long; Wu, Qun

2018-05-01

In this paper, a novel reconfigurable dual-band metamaterial antenna with a continuous beam that is electrically steered in backward to forward directions is first proposed by employing a liquid crystal (LC)-loaded tunable extended composite right-/left-handed (E-CRLH) transmission line (TL). The frequency-dependent property of the E-CRLH TL is analyzed and a compact unit cell based on the nematic LC is proposed to realize the tunable dual band characteristics. The phase constant of the proposed unit cell can be dynamically continuously tuned from negative to positive values in two operating bands by changing the bias voltage of the loaded LC material. A resulting dual band fixed-frequency beam steering property has been predicted by numerical simulations and experimentally verified. The measured results show that the fabricated reconfigurable antenna features an electrically controlled continuous beam steering from backward  ‑16° to forward  +13° at 7.2 GHz and backward  ‑9° to forward  +17° at 9.4 GHz, respectively. This electrically controlled beam steering range turns out to be competitive with the previously reported single band reconfigurable antennas. Besides, the measured and simulated results of the proposed reconfigurable dual-band metamaterial antenna are in good agreement.

Reconfigurable Radio Access Unit for DWDM to W-Band Wireless Conversion

DEFF Research Database (Denmark)

Chorchos, Łukasz; Rommel, Simon; Turkiewicz, Jarosław P.

2017-01-01

In this letter a reconfigurable Remote Access Unit (RAU) is proposed and demonstrated, interfacing dense wavelength division multiplexed (DWDM) optical and W-band wireless links. The RAU is composed of a tunable local oscillator, a narrow optical filter and a control unit, making it reconfigurable...

On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors

Directory of Open Access Journals (Sweden)

Mariusz Grad

2012-01-01

Full Text Available Reconfigurable instruction set processors provide the possibility of tailor the instruction set of a CPU to a particular application. While this customization process could be performed during runtime in order to adapt the CPU to the currently executed workload, this use case has been hardly investigated. In this paper, we study the feasibility of moving the customization process to runtime and evaluate the relation of the expected speedups and the associated overheads. To this end, we present a tool flow that is tailored to the requirements of this just-in-time ASIP specialization scenario. We evaluate our methods by targeting our previously introduced Woolcano reconfigurable ASIP architecture for a set of applications from the SPEC2006, SPEC2000, MiBench, and SciMark2 benchmark suites. Our results show that just-in-time ASIP specialization is promising for embedded computing applications, where average speedups of 5x can be achieved by spending 50 minutes for custom instruction identification and hardware generation. These overheads will be compensated if the applications execute for more than 2 hours. For the scientific computing benchmarks, the achievable speedup is only 1.2x, which requires significant execution times in the order of days to amortize the overheads.

A Novel Docking System for Modular Self-Reconfigurable Robots

Directory of Open Access Journals (Sweden)

Tan Zhang

2017-10-01

Full Text Available Existing self-reconfigurable robots achieve connections and disconnections by a separate drive of the docking system. In this paper, we present a new docking system with which the connections and disconnections are driven by locomotion actuators, without the need for a separate drive, which reduces the weight and the complexity of the modules. This self-reconfigurable robot consists of two types of fundamental modules, i.e., active and passive modules. By the docking system, two types of connections are formed with the fundamental modules, and the docking and undocking actions are achieved through simple control with less sensory feedback. This paper describes the design of the robotic modules, the docking system, the docking process, and the docking force analysis. An experiment is performed to demonstrate the self-reconfigurable robot with the docking system.

High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

Science.gov (United States)

Ly, Daniel Le; Chow, Paul

2010-11-01

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

Reconfigurable remote access unit for W-band Radio-over-Fiber transmission

DEFF Research Database (Denmark)

Chorchos, Łukasz; Rommel, Simon; Turkiewicz, Jarosław P.

2016-01-01

There is a growing demand for cost-effective radio over fibre transmission techniques. In this paper, we propose and realize the reconfigurable remote access unit for radio-over-fiber transmission. The reconfigurable unit is build from the tunable filter and laser as well as remote controller...

Materials challenges for repeatable RF wireless device reconfiguration with microfluidic channels

Science.gov (United States)

Griffin, Anthony S.; Sottos, Nancy R.; White, Scott R.

2018-03-01

Recently, adaptive wireless devices have utilized displacement of EGaIn within microchannels as an electrical switching mechanism to enable reconfigurable electronics. Device reconfiguration using EGaIn in microchannels overcomes many challenges encountered by more traditional reconfiguration mechanisms such as diodes and microelectromechanical systems (MEMS). Reconfiguration using EGaIn is severely limited by undesired permanent shorting due to retention of the liquid in microchannels caused by wetting and rapid oxide skin formation. Here, we investigate the conditions which prevent repeatable electrical switching using EGaIn in microchannels. Initial contact angle tests of EGaIn on epoxy surfaces demonstrate the wettability of EGaIn on flat surfaces. SEM cross-sections of microchannels reveal adhesion of EGaIn residue to channel walls. Micro-computed tomography (microCT) scans of provide volumetric measurements of EGaIn remaining inside channels after flow cycling. Non-wetting coatings are proposed as materials based strategy to overcome these issues in future work.

A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

Science.gov (United States)

Zou, Liang; Fu, Zhuang; Zhao, YanZheng; Yang, JunYan

2010-07-01

This paper proposes a kind of pipelined electric circuit architecture implemented in FPGA, a very large scale integrated circuit (VLSI), which efficiently deals with the real time non-uniformity correction (NUC) algorithm for infrared focal plane arrays (IRFPA). Dual Nios II soft-core processors and a DSP with a 64+ core together constitute this image system. Each processor undertakes own systematic task, coordinating its work with each other's. The system on programmable chip (SOPC) in FPGA works steadily under the global clock frequency of 96Mhz. Adequate time allowance makes FPGA perform NUC image pre-processing algorithm with ease, which has offered favorable guarantee for the work of post image processing in DSP. And at the meantime, this paper presents a hardware (HW) and software (SW) co-design in FPGA. Thus, this systematic architecture yields an image processing system with multiprocessor, and a smart solution to the satisfaction with the performance of the system.

Reconfigurable multiport EPON repeater

Science.gov (United States)

Oishi, Masayuki; Inohara, Ryo; Agata, Akira; Horiuchi, Yukio

2009-11-01

An extended reach EPON repeater is one of the solutions to effectively expand FTTH service areas. In this paper, we propose a reconfigurable multi-port EPON repeater for effective accommodation of multiple ODNs with a single OLT line card. The proposed repeater, which has multi-ports in both OLT and ODN sides, consists of TRs, BTRs with the CDR function and a reconfigurable electrical matrix switch, can accommodate multiple ODNs to a single OLT line card by controlling the connection of the matrix switch. Although conventional EPON repeaters require full OLT line cards to accommodate subscribers from the initial installation stage, the proposed repeater can dramatically reduce the number of required line cards especially when the number of subscribers is less than a half of the maximum registerable users per OLT. Numerical calculation results show that the extended reach EPON system with the proposed EPON repeater can save 17.5% of the initial installation cost compared with a conventional repeater, and can be less expensive than conventional systems up to the maximum subscribers especially when the percentage of ODNs in lightly-populated areas is higher.

A game-theoretic formulation of the homogeneous self-reconfiguration problem

KAUST Repository

Pickem, Daniel; Egerstedt, Magnus; Shamma, Jeff S.

2015-01-01

In this paper we formulate the homogeneous two- and three-dimensional self-reconfiguration problem over discrete grids as a constrained potential game. We develop a game-theoretic learning algorithm based on the Metropolis-Hastings algorithm that solves the self-reconfiguration problem in a globally optimal fashion. Both a centralized and a fully decentralized algorithm are presented and we show that the only stochastically stable state is the potential function maximizer, i.e. the desired target configuration. These algorithms compute transition probabilities in such a way that even though each agent acts in a self-interested way, the overall collective goal of self-reconfiguration is achieved. Simulation results confirm the feasibility of our approach and show convergence to desired target configurations.

A game-theoretic formulation of the homogeneous self-reconfiguration problem

KAUST Repository

Pickem, Daniel

2015-12-15

In this paper we formulate the homogeneous two- and three-dimensional self-reconfiguration problem over discrete grids as a constrained potential game. We develop a game-theoretic learning algorithm based on the Metropolis-Hastings algorithm that solves the self-reconfiguration problem in a globally optimal fashion. Both a centralized and a fully decentralized algorithm are presented and we show that the only stochastically stable state is the potential function maximizer, i.e. the desired target configuration. These algorithms compute transition probabilities in such a way that even though each agent acts in a self-interested way, the overall collective goal of self-reconfiguration is achieved. Simulation results confirm the feasibility of our approach and show convergence to desired target configurations.

Design and Fabrication of a Reconfigurable MEMS-Based Antenna

KAUST Repository

Martinez, Miguel Angel Galicia

2011-06-22

This thesis presents the design and fabrication of a customized in house Micro-Electro-Mechanical-Systems (MEMS) process based on-chip antenna that is both frequency and polarization reconfigurable. It is designed to work at both 60 GHz and 77 GHz through MEMS switches. This antenna can also work in both horizontal and vertical linear polarizations by utilizing a moveable plate. The design is intended for Wireless Personal Area Networks (WPAN) and automotive radar applications. Typical on-chip antennas are inefficient and difficult to reconfigure. Therefore, the focus of this work is to develop an efficient on-chip antenna solution, which is reconfigurable in frequency and in polarization. A fractal bowtie antenna is employed for this thesis, which achieves frequency reconfigurability through MEMS switches. The design is simulated in industry standard Electromagnetic (EM) simulator Ansoft HFSS. A novel concept for horizontal to vertical linear polarization agility is introduced which incorporates a moveable polymer plate. For this work, a microprobe is used to move the plate from the horizontal to vertical position. For testing purposes, a novel mechanism has been designed in order to feed the antenna with RF-probes in both horizontal and vertical positions. A simulated gain of approximately 0 dB is achieved at both target frequencies (60 and 77 GHz), in both horizontal and vertical positions. In all the cases mentioned above (both frequencies and positions), the antenna is well matched (< -10 dB) to the 50 Ω system impedance. Similarly, the radiation nulls are successfully shifted by changing the position of the antenna from horizontal to vertical. The complete design and fabrication of the reconfigurable MEMS antenna has been done at KAUST facilities. Some challenges have been encountered during its realization due to the immaturity of the customized MEMS fabrication process. Nonetheless, a first fabrication attempt has highlighted such shortcomings. According

A reconfigurable strategy for distributed digital process control

International Nuclear Information System (INIS)

Garcia, H.E.; Ray, A.; Edwards, R.M.

1990-01-01

A reconfigurable control scheme is proposed which, unlike a preprogrammed one, uses stochastic automata to learn the current operating status of the environment (i.e., the plant, controller, and communication network) by dynamically monitoring the system performance and then switching to the appropriate controller on the basis of these observations. The potential applicability of this reconfigurable control scheme to electric power plants is being investigated. The plant under consideration is the Experimental Breeder Reactor (EBR-II) at the Argonne National Laboratory site in Idaho. The distributed control system is emulated on a ring network where the individual subsystems are hosted as follows: (1) the reconfigurable control modules are located in one of the network modules called Multifunction Controller; (2) the learning modules are resident in a VAX 11/785 mainframe computer; and (3) a detailed model of the plant under control is executed in the same mainframe. This configuration is a true representation of the network-based control system in the sense that it operates in real time and is capable of interacting with the actual plant

Analysis of Reconfigured Control Loop with a Virtual Actuator

Directory of Open Access Journals (Sweden)

Anna Filasova

2011-01-01

Full Text Available Control reconfiguration changes the control structure in response to a fault detected in the plant. This becomes necessary, because a major fault like loss of an actuator breaks the corresponding control loop and therefore renders the whole system inoperable.  An important aim of control reconfiguration is to change the control structure as little as possible, since every change bears the potential of practical problems. The proposed solution is to keep the original controller in the loop and to add an extension called virtual actuator that implements the necessary changes of the control structure. The virtual actuator translates between the signals of the nominal controller and the signal of the faulty plants. This paper is concerned with the analysis of reconfigured loop with a virtual actuator for the system with the faulty actuator. The proposed analysis is illustrated on numerical example.

A Method for Design of Modular Reconfigurable Machine Tools

Directory of Open Access Journals (Sweden)

Zhengyi Xu

2017-02-01

Full Text Available Presented in this paper is a method for the design of modular reconfigurable machine tools (MRMTs. An MRMT is capable of using a minimal number of modules through reconfiguration to perform the required machining tasks for a family of parts. The proposed method consists of three steps: module identification, module determination, and layout synthesis. In the first step, the module components are collected from a family of general-purpose machines to establish a module library. In the second step, for a given family of parts to be machined, a set of needed modules are selected from the module library to construct a desired reconfigurable machine tool. In the third step, a final machine layout is decided though evaluation by considering a number of performance indices. Based on this method, a software package has been developed that can design an MRMT for a given part family.

Reconfiguration in FPGA-Based Multi-Core Platforms for Hard Real-Time Applications

DEFF Research Database (Denmark)

Pezzarossa, Luca; Schoeberl, Martin; Sparsø, Jens

2016-01-01

-case execution-time of tasks of an application that determines the systems ability to respond in time. To support this focus, the platform must provide service guarantees for both communication and computation resources. In addition, many hard real-time applications have multiple modes of operation, and each......In general-purpose computing multi-core platforms, hardware accelerators and reconfiguration are means to improve performance; i.e., the average-case execution time of a software application. In hard real-time systems, such average-case speed-up is not in itself relevant - it is the worst...... mode has specific requirements. An interesting perspective on reconfigurable computing is to exploit run-time reconfiguration to support mode changes. In this paper we explore approaches to reconfiguration of communication and computation resources in the T-CREST hard real-time multi-core platform...

A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

DEFF Research Database (Denmark)

Pezzarossa, Luca; Schoeberl, Martin; Sparsø, Jens

2017-01-01

-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes......In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading....... The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example...

Liquid metal-based reconfigurable and stretchable photolithography

International Nuclear Information System (INIS)

Kim, Daeyoung; Yoo, Jun Hyeon; Lee, Jeong-Bong

2016-01-01

Conventional ultraviolet (UV) lithography typically uses a photomask made of a fused silica plate covered with a layer of UV opaque material such as chromium. The photomask has passive binary patterns of UV opaque and UV transparent regions and the pattern is unalterable. We report a novel real-time dynamically reconfigurable photomask technology using a liquid metal (as a UV opaque material) filled in polydimethylsiloxane (PDMS, as a UV transparent material) microfluidic channels. We found that the gallium-based liquid metal (e.g. Galinstan ® ) is opaque in broad spectrum of light in the wavelength from 325 nm to 850 nm while the PDMS is highly transparent in this wide range of spectrum. We made both bright field and dark field microfluidic photomasks and transferred various patterns onto a positive photoresist. A 7-segment display microfluidic channel photomask was also fabricated and decimal numerals (from ‘0’ to ‘9’) were patterned with one photomask by dynamically reconfiguring decimal numeral shapes with on-demand injection and withdrawal of the liquid metal in specific segment microfluidic channels in the photomask. In addition, utilizing mechanical flexibility of the PDMS and the liquid metal, reconfiguration of the patterns in a microfluidic photomask under stretching was successfully tested. (paper)

Repetition or Reconfiguration

DEFF Research Database (Denmark)

Andersen, Kristina Vaarst

, the cognitive quality of knowledge held by individual professionals is the key microfoundation for project level performance. This paper empirically tests effects of project participants with and without knowledge diversity for project level performance for projects aiming for varying degrees of repetition...... and reconfiguration. The results indicate that project performance benefits form contributions from individuals holding diverse knowledge only when projects aim for high differentiation levels. This positive association is not just moderated, it may even be reversed in the case of professionals participating in low...

Multi-criteria grey relational approach to evaluating reconfigurable manufacturing configurations

OpenAIRE

Rehman, A. U.

2017-01-01

In response to highly dynamic markets, manufacturing industries need alternative feasible manufacturing strategies. The strategy currently adopted is to reconfigure the existing manufacturing system. The conditions to reconfigure existing configurations change from time to time. An attempt is made to identify and apply an approach to evaluate these configurations. The paper proposes a grey relational decision-making approach. The approach takes into account multiple performance measures. The ...

Reconfigurable Manufacturing System Design and Implementation

DEFF Research Database (Denmark)

Hadar, Ronen; Bilberg, Arne

2013-01-01

is meant primarily to show the physical feasibility of the system and provide a first-look into a real production application of the RMS ideas. The purpose of this paper is to present the design of the manufacturer’s RMS proof of concept, its implementation, and evaluation results.......Reconfigurable Manufacturing Systems (RMS) have been an increasing area of interest in the research arena. However, it seems that current literature is lacking application and implementation cases where RMS are simulated, tested, and evaluated as a feasible manufacturing concept. A Manufacturer...... of Consumer Goods identified the potential of the RMS concept and decided to investigate the concept in a real production installation. The result of this development is a proof of concept of a changeable and reconfigurable assembly and decoration system based on the principles of RMS. This proof of concept...

Reconfigurable Patch Antenna Radiations Using Plasma Faraday Shield Effect

OpenAIRE

Barro , Oumar Alassane; Himdi , Mohamed; Lafond , Olivier

2016-01-01

International audience; This letter presents a new reconfigurable antenna associated with a plasma Faraday shield effect. The Faraday shield effect is realized by using a fluorescent lamp. A patch antenna operating at 2.45 GHz is placed inside the lamp. The performance of the reconfigurable system is observed in terms of S11, gain and radiation patterns by simulation and measurement. It is shown that by switching ON the fluorescent lamp, the gain of the antenna decreases and the antenna syste...

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

Science.gov (United States)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Initial beam test results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Adolphsen, C.; Litke, A.; Schwarz, A.

1986-01-01

Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

Reconfigurable control of a power plant deaerator using learning automata

International Nuclear Information System (INIS)

Garcia, H.E.; Ray, A.; Edwards, R.M.

1991-01-01

A deaerating feedwater heater, equipped with a water level controller and a pressure controller, has been chosen to investigate the feasibility of a reconfigurable control scheme for power plants by incorporating the concept of learning automata. In this paper simulation results based on a model of the Experimental Breeder Reactor (EBR-II) at the Argonne National Laboratory site in Idaho are presented to demonstrate the efficacy of the reconfigurable control scheme

Software defined radio (SDR) architecture for concurrent multi-satellite communications

Science.gov (United States)

Maheshwarappa, Mamatha R.

SDRs have emerged as a viable approach for space communications over the last decade by delivering low-cost hardware and flexible software solutions. The flexibility introduced by the SDR concept not only allows the realisation of concurrent multiple standards on one platform, but also promises to ease the implementation of one communication standard on differing SDR platforms by signal porting. This technology would facilitate implementing reconfigurable nodes for parallel satellite reception in Mobile/Deployable Ground Segments and Distributed Satellite Systems (DSS) for amateur radio/university satellite operations. This work outlines the recent advances in embedded technologies that can enable new communication architectures for concurrent multi-satellite or satellite-to-ground missions where multi-link challenges are associated. This research proposes a novel concept to run advanced parallelised SDR back-end technologies in a Commercial-Off-The-Shelf (COTS) embedded system that can support multi-signal processing for multi-satellite scenarios simultaneously. The initial SDR implementation could support only one receiver chain due to system saturation. However, the design was optimised to facilitate multiple signals within the limited resources available on an embedded system at any given time. This was achieved by providing a VHDL solution to the existing Python and C/C++ programming languages along with parallelisation so as to accelerate performance whilst maintaining the flexibility. The improvement in the performance was validated at every stage through profiling. Various cases of concurrent multiple signals with different standards such as frequency (with Doppler effect) and symbol rates were simulated in order to validate the novel architecture proposed in this research. Also, the architecture allows the system to be reconfigurable by providing the opportunity to change the communication standards in soft real-time. The chosen COTS solution provides a

VLSI-based video event triggering for image data compression

Science.gov (United States)

Williams, Glenn L.

1994-02-01

Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

Reconfigurable Three-Dimensional Gold Nanorod Plasmonic Nanostructures Organized on DNA Origami Tripod.

Science.gov (United States)

Zhan, Pengfei; Dutta, Palash K; Wang, Pengfei; Song, Gang; Dai, Mingjie; Zhao, Shu-Xia; Wang, Zhen-Gang; Yin, Peng; Zhang, Wei; Ding, Baoquan; Ke, Yonggang

2017-02-28

Distinct electromagnetic properties can emerge from the three-dimensional (3D) configuration of a plasmonic nanostructure. Furthermore, the reconfiguration of a dynamic plasmonic nanostructure, driven by physical or chemical stimuli, may generate a tailored plasmonic response. In this work, we constructed a 3D reconfigurable plasmonic nanostructure with controllable, reversible conformational transformation using bottom-up DNA self-assembly. Three gold nanorods (AuNRs) were positioned onto a reconfigurable DNA origami tripod. The internanorod angle and distance were precisely tuned through operating the origami tripod by toehold-mediated strand displacement. The transduction of conformational change manifested into a controlled shift of the plasmonic resonance peak, which was studied by dark-field microscopy, and agrees well with electrodynamic calculations. This new 3D plasmonic nanostructure not only provides a method to study the plasmonic resonance of AuNRs at prescribed 3D conformations but also demonstrates that DNA origami can serve as a general self-assembly platform for constructing various 3D reconfigurable plasmonic nanostructures with customized optical properties.

Fast Optimal Replica Placement with Exhaustive Search Using Dynamically Reconfigurable Processor

Directory of Open Access Journals (Sweden)

Hidetoshi Takeshita

2011-01-01

Full Text Available This paper proposes a new replica placement algorithm that expands the exhaustive search limit with reasonable calculation time. It combines a new type of parallel data-flow processor with an architecture tuned for fast calculation. The replica placement problem is to find a replica-server set satisfying service constraints in a content delivery network (CDN. It is derived from the set cover problem which is known to be NP-hard. It is impractical to use exhaustive search to obtain optimal replica placement in large-scale networks, because calculation time increases with the number of combinations. To reduce calculation time, heuristic algorithms have been proposed, but it is known that no heuristic algorithm is assured of finding the optimal solution. The proposed algorithm suits parallel processing and pipeline execution and is implemented on DAPDNA-2, a dynamically reconfigurable processor. Experiments show that the proposed algorithm expands the exhaustive search limit by the factor of 18.8 compared to the conventional algorithm search limit running on a Neumann-type processor.

Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration

DEFF Research Database (Denmark)

Nannarelli, Alberto; Re, M.; Cardarilli, Gian Carlo

2017-01-01

Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over-clocking th......Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over...

A Domain-Specific Language for Programming Self-Reconfigurable Robots

DEFF Research Database (Denmark)

Schultz, Ulrik Pagh; Christensen, David Johan; Støy, Kasper

2007-01-01

. Programming a modular, self-reconfigurable robot is however a complicated task: the robot is essentially a real-time, distributed embedded system, where control and communication paths often are tightly coupled to the current physical configuration of the robot. To facilitate the task of programming modular......, self-reconfigurable robots, we have developed a declarative, role-based language that allows the programmer to define roles and behavior independently of the concrete physical structure of the robot. Roles are compiled to mobile code fragments that distribute themselves over the physical structure...

Parallel algorithms and architecture for computation of manipulator forward dynamics

Science.gov (United States)

Fijany, Amir; Bejczy, Antal K.

1989-01-01

Parallel computation of manipulator forward dynamics is investigated. Considering three classes of algorithms for the solution of the problem, that is, the O(n), the O(n exp 2), and the O(n exp 3) algorithms, parallelism in the problem is analyzed. It is shown that the problem belongs to the class of NC and that the time and processors bounds are of O(log2/2n) and O(n exp 4), respectively. However, the fastest stable parallel algorithms achieve the computation time of O(n) and can be derived by parallelization of the O(n exp 3) serial algorithms. Parallel computation of the O(n exp 3) algorithms requires the development of parallel algorithms for a set of fundamentally different problems, that is, the Newton-Euler formulation, the computation of the inertia matrix, decomposition of the symmetric, positive definite matrix, and the solution of triangular systems. Parallel algorithms for this set of problems are developed which can be efficiently implemented on a unique architecture, a triangular array of n(n+2)/2 processors with a simple nearest-neighbor interconnection. This architecture is particularly suitable for VLSI and WSI implementations. The developed parallel algorithm, compared to the best serial O(n) algorithm, achieves an asymptotic speedup of more than two orders-of-magnitude in the computation the forward dynamics.

Low Power Implementation of Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

NARCIS (Netherlands)

Zhang, Q.; Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Rivaton, Arnaud; Quevremont, Jérôme

2005-01-01

The DRM standard for digital radio broadcast in the AM band requires integrated devices for radio receivers at very low power. A System on Chip (SoC) call DiMITRI was developed based on a dual ARM9 RISC core architecture. Analyses showed that most computation power is used in the Coded Orthogonal

Exploration Space Suit Architecture and Destination Environmental-Based Technology Development

Science.gov (United States)

Hill, Terry R.; McFarland, Shane M.; Korona, F. Adam

2013-01-01

This paper continues forward where EVA Space Suit Architecture: Low Earth Orbit Vs. Moon Vs. Mars left off in the development of a space suit architecture that is modular in design and could be reconfigured prior to launch or during any given mission depending on the tasks or destination. This space suit system architecture and technologies required based on human exploration (EVA) destinations will be discussed, and how these systems should evolve to meet the future exploration EVA needs of the US human space flight program. A series of exercises and analyses provided a strong indication that the Constellation Program space suit architecture, with its maximum reuse of technology and functionality across a range of mission profiles and destinations, is postured to provide a viable solution for future space exploration missions. The destination environmental analysis demonstrates that the modular architecture approach could provide the lowest mass and mission cost for the protection of the crew, given any human mission outside of low-Earth orbit. Additionally, some of the high-level trades presented here provide a review of the environmental and nonenvironmental design drivers that will become increasingly important as humans venture farther from Earth. The presentation of destination environmental data demonstrates a logical clustering of destination design environments that allows a focused approach to technology prioritization, development, and design that will maximize the return on investment, largely independent of any particular design reference mission.

The Effects of Interference Suppression by a Reconfigurable Structure at DSSS-DPSK Receiver

Directory of Open Access Journals (Sweden)

B. Dimitrijevic

2010-12-01

Full Text Available In this paper we show the performances of DSSS-DPSK receiver where the interference rejection circuit is reconfigurable and is using ksi-structure. The results will be shown for the case of packet, as well as for the continuous QPSK interference. The results show that the proposed reconfiguration circuit, in case of packet QPSK interference, significantly decreases the error probability, compared to the system using only ksi-structure. Also, in case of continuous interference, the reconfigurable structure has equally good performance, regardless of interference power and its bitrate.

A Network Reconfiguration Method Considering Data Uncertainties in Smart Distribution Networks

Directory of Open Access Journals (Sweden)

Ke-yan Liu

2017-05-01

Full Text Available This work presents a method for distribution network reconfiguration with the simultaneous consideration of distributed generation (DG allocation. The uncertainties of load fluctuation before the network reconfiguration are also considered. Three optimal objectives, including minimal line loss cost, minimum Expected Energy Not Supplied, and minimum switch operation cost, are investigated. The multi-objective optimization problem is further transformed into a single-objective optimization problem by utilizing weighting factors. The proposed network reconfiguration method includes two periods. The first period is to create a feasible topology network by using binary particle swarm optimization (BPSO. Then the DG allocation problem is solved by utilizing sensitivity analysis and a Harmony Search algorithm (HSA. In the meanwhile, interval analysis is applied to deal with the uncertainties of load and devices parameters. Test cases are studied using the standard IEEE 33-bus and PG&E 69-bus systems. Different scenarios and comparisons are analyzed in the experiments. The results show the applicability of the proposed method. The performance analysis of the proposed method is also investigated. The computational results indicate that the proposed network reconfiguration algorithm is feasible.

A Reconfigurable Metal-Plasma Yagi-Yuda Antenna for Microwave Applications

Directory of Open Access Journals (Sweden)

Giulia Mansutti

2017-05-01

Full Text Available This paper is an extension of the work originally presented at the European Microwave Conference (EuMC about a reconfigurable hybrid metal-plasma Yagi-Uda antenna operating at 1.55 GHz: this antenna consists of metallic reflector and active element and two plasma directors. The conference work showed through full-wave numerical simulations (CST Microwave Studio how it is possible to achieve reconfigurability with respect to the gain by turning on/off the plasma discharges. However the model that was used to represent the plasma discharges was quite ideal, so one comment that was provided questioned the actual possibility of achieving reconfigurability in a real system. Consequently we performed extensive measurements of different plasma discharges and thanks to the collected data, we noticed some important differences between the full-wave numerical model of the plasma that we used in the conference paper and the actual plasma discharges that were generated in the experimental setup: the dielectric vessel and the metallic electrodes used respectively to confine and generate the plasma have an influence on the radiation pattern of the antenna and so they must be included in the design procedure; the cylindrical plasma discharge is much easier to realize when the cylinder diameter is at least 3mm; and finally the collision frequency of the plasma in realistic cases is pretty higher than the one adopted in our previous work. Therefore this work presents a feasibility study of a more detailed and realistic model of our antenna with respect to the plasma discharges. We will show that reconfigurability can still be achieved through a proper design of the overall antenna, thus paving the way to an actual realization of the proposed reconfigurable Yagi-Uda.

Diagnosis and Reconfiguration using Bayesian Networks: An Electrical Power System Case Study

Science.gov (United States)

Knox, W. Bradley; Mengshoel, Ole

2009-01-01

Automated diagnosis and reconfiguration are important computational techniques that aim to minimize human intervention in autonomous systems. In this paper, we develop novel techniques and models in the context of diagnosis and reconfiguration reasoning using causal Bayesian networks (BNs). We take as starting point a successful diagnostic approach, using a static BN developed for a real-world electrical power system. We discuss in this paper the extension of this diagnostic approach along two dimensions, namely: (i) from a static BN to a dynamic BN; and (ii) from a diagnostic task to a reconfiguration task. More specifically, we discuss the auto-generation of a dynamic Bayesian network from a static Bayesian network. In addition, we discuss subtle, but important, differences between Bayesian networks when used for diagnosis versus reconfiguration. We discuss a novel reconfiguration agent, which models a system causally, including effects of actions through time, using a dynamic Bayesian network. Though the techniques we discuss are general, we demonstrate them in the context of electrical power systems (EPSs) for aircraft and spacecraft. EPSs are vital subsystems on-board aircraft and spacecraft, and many incidents and accidents of these vehicles have been attributed to EPS failures. We discuss a case study that provides initial but promising results for our approach in the setting of electrical power systems.

Nanopatterned reconfigurable spin-textures for magnonics

Science.gov (United States)

Albisetti, E.; Petti, D.; Pancaldi, M.; Madami, M.; Tacchi, S.; Curtis, J.; King, W. P.; Papp, A.; Csaba, G.; Porod, W.; Vavassori, P.; Riedo, E.; Bertacco, R.

The control of spin-waves holds the promise to enable energy-efficient information transport and wave-based computing. Conventionally, the engineering of spin-waves is achieved via physically patterning magnetic structures such as magnonic crystals and micro-nanowires. We demonstrate a new concept for creating reconfigurable magnonic nanostructures, by crafting at the nanoscale the magnetic anisotropy landscape of a ferromagnet exchange-coupled to an antiferromagnet. By performing a highly localized field cooling with the hot tip of a scanning probe microscope, magnetic structures, with arbitrarily oriented magnetization and tunable unidirectional anisotropy, are patterned without modifying the film chemistry and topography. We demonstrate that, in such structures, the spin-wave excitation and propagation can be spatially controlled at remanence, and can be tuned by external magnetic fields. This opens the way to the use of nanopatterned spin-textures, such as domains and domain walls, for exciting and manipulating magnons in reconfigurable nanocircuits. Partially funded by the EC through project SWING (no. 705326).

The Gospel of Matthew: Reconfigured Torah

Directory of Open Access Journals (Sweden)

Richard B. Hays

2005-10-01

Full Text Available This essay surveys the evangelist Matthew’s reading of Israel’s Scripture. Rather than focusing only on Matthew’s distinctive formula quotations, we must observe the subtler ways that Matthew evokes scriptural images and patterns. The essay highlights four major aspects of Matthew’s reading of Scripture. (1 Matthew reads Israel’s Scripture as a story that highlights election, kingship, exile, and messianic salvation as the end of exile. (2 Matthew reconfigures Torah into a call for radical transformation of the heart. (3 Matthew highlights Scripture’s call for mercy, particularly by emphasizing Hosea 6:6 as the hermeneutical key to Torah. (4 Matthew interprets the mission to the Gentiles as the fulfilment of Israel’s destiny and the active embodiment of the authority of the Son of Man (Dn 7:13-14 over the whole world. Jointly taken, these strategies of interpretation produce a striking reconfiguration of Israel’s Torah.

Implementation of the Two-Point Angular Correlation Function on a High-Performance Reconfigurable Computer

Directory of Open Access Journals (Sweden)

Volodymyr V. Kindratenko

2009-01-01

Full Text Available We present a parallel implementation of an algorithm for calculating the two-point angular correlation function as applied in the field of computational cosmology. The algorithm has been specifically developed for a reconfigurable computer. Our implementation utilizes a microprocessor and two reconfigurable processors on a dual-MAP SRC-6 system. The two reconfigurable processors are used as two application-specific co-processors. Two independent computational kernels are simultaneously executed on the reconfigurable processors while data pre-fetching from disk and initial data pre-processing are executed on the microprocessor. The overall end-to-end algorithm execution speedup achieved by this implementation is over 90× as compared to a sequential implementation of the algorithm executed on a single 2.8 GHz Intel Xeon microprocessor.

Intelligent Reconfigurable System with Self-Dammage Assessmentand Control Stress Capabilities

Science.gov (United States)

Trivailo, P.; Plotnikova, L.; Kao, T. W.

2002-01-01

Modern space structures are constructed using a modular approach that facilitates their transportation and assembly in space. Modular architecture of space structures also enables reconfiguration of large structures such that they can adapt to possible changes in environment, and also allows use of the limited structural resources available in space for completion of a much larger variety of tasks. An increase in size and complexity demands development of materials with a "smart" or active structural modulus and also of effective control algorithms to control the motion of large flexible structures. This challenging task has generated a lot of interest amongst scientists and engineers during the last two decades, however, research into the development of control schemes which can adapt to structural configuration changes has received less attention. This is possibly due to the increased complexity caused by alterations in geometry, which inevitably lead to changes in the dynamic properties of the system. This paper presents results of the application of a decentralized control approach for active control of large flexible structures undergoing significant reconfigurations. The Control Component Synthesis methodology was used to build controlled components and to assemble them into a controlled flexible structure that meets required performance specifications. To illustrate the efficiency of the method, numerical simulations were conducted for 2D and 3D modular truss structures and a multi-link beam system. In each case the performance of the decentralized control system has been evaluated using pole location maps, step and impulse response simulations and frequency response analysis. The performance of the decentralized control system has been measured against the optimal centralised control system for various excitation scenarios. A special case where one of the local component controllers fails was also examined. For better interpretation of the efficiency of the

Multi-objective optimal operation of smart reconfigurable distribution grids

Directory of Open Access Journals (Sweden)

Abdollah Kavousi-Fard

2016-02-01

Full Text Available Reconfiguration is a valuable technique that can support the distribution grid from different aspects such as operation cost and loss reduction, reliability improvement, and voltage stability enhancement. An intelligent and efficient optimization framework, however, is required to reach the desired efficiency through the reconfiguration strategy. This paper proposes a new multi-objective optimization model to make use of the reconfiguration strategy for minimizing the power losses, improving the voltage profile, and enhancing the load balance in distribution grids. The proposed model employs the min-max fuzzy approach to find the most satisfying solution from a set of nondominated solutions in the problem space. Due to the high complexity and the discrete nature of the proposed model, a new optimization method based on harmony search (HS algorithm is further proposed. Moreover, a new modification method is suggested to increase the harmony memory diversity in the improvisation stage and increase the convergence ability of the algorithm. The feasibility and satisfying performance of the proposed model are examined on the IEEE 32-bus distribution system.

Modeling selective attention using a neuromorphic analog VLSI device.

Science.gov (United States)

Indiveri, G

2000-12-01

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

Exploration Space Suit Architecture: Destination Environmental-Based Technology Development

Science.gov (United States)

Hill, Terry R.

2010-01-01

This paper picks up where EVA Space Suit Architecture: Low Earth Orbit Vs. Moon Vs. Mars (Hill, Johnson, IEEEAC paper #1209) left off in the development of a space suit architecture that is modular in design and interfaces and could be reconfigured to meet the mission or during any given mission depending on the tasks or destination. This paper will walk though the continued development of a space suit system architecture, and how it should evolve to meeting the future exploration EVA needs of the United States space program. In looking forward to future US space exploration and determining how the work performed to date in the CxP and how this would map to a future space suit architecture with maximum re-use of technology and functionality, a series of thought exercises and analysis have provided a strong indication that the CxP space suit architecture is well postured to provide a viable solution for future exploration missions. Through the destination environmental analysis that is presented in this paper, the modular architecture approach provides the lowest mass, lowest mission cost for the protection of the crew given any human mission outside of low Earth orbit. Some of the studies presented here provide a look and validation of the non-environmental design drivers that will become every-increasingly important the further away from Earth humans venture and the longer they are away. Additionally, the analysis demonstrates a logical clustering of design environments that allows a very focused approach to technology prioritization, development and design that will maximize the return on investment independent of any particular program and provide architecture and design solutions for space suit systems in time or ahead of being required for any particular manned flight program in the future. The new approach to space suit design and interface definition the discussion will show how the architecture is very adaptable to programmatic and funding changes with

Switchable reconfiguration of nucleic acid nanostructures by stimuli-responsive DNA machines.

Science.gov (United States)

Liu, Xiaoqing; Lu, Chun-Hua; Willner, Itamar

2014-06-17

CONSPECTUS: The base sequence in DNA dictates structural and reactivity features of the biopolymer. These properties are implemented to use DNA as a unique material for developing the area of DNA nanotechnology. The design of DNA machines represents a rapidly developing research field in the area of DNA nanotechnology. The present Account discusses the switchable reconfiguration of nucleic acid nanostructures by stimuli-responsive DNA machines, and it highlights potential applications and future perspectives of the area. Programmed switchable DNA machines driven by various fuels and antifuels, such as pH, Hg(2+) ions/cysteine, or nucleic acid strands/antistrands, are described. These include the assembly of DNA tweezers, walkers, a rotor, a pendulum, and more. Using a pH-oscillatory system, the oscillatory mechanical operation of a DNA pendulum is presented. Specifically, the synthesis and "mechanical" properties of interlocked DNA rings are described. This is exemplified with the preparation of interlocked DNA catenanes and a DNA rotaxane. The dynamic fuel-driven reconfiguration of the catenane/rotaxane structures is followed by fluorescence spectroscopy. The use of DNA machines as functional scaffolds to reconfigurate Au nanoparticle assemblies and to switch the fluorescence features within fluorophore/Au nanoparticle conjugates between quenching and surface-enhanced fluorescence states are addressed. Specifically, the fluorescence features of the different DNA machines are characterized as a function of the spatial separation between the fluorophore and Au nanoparticles. The experimental results are supported by theoretical calculations. The future development of reconfigurable stimuli-responsive DNA machines involves fundamental challenges, such as the synthesis of molecular devices exhibiting enhanced complexities, the introduction of new fuels and antifuels, and the integration of new payloads being reconfigured by the molecular devices, such as enzymes or

An electron undulating ring for VLSI lithography

International Nuclear Information System (INIS)

Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

1985-01-01

The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

Convolving optically addressed VLSI liquid crystal SLM

Science.gov (United States)

Jared, David A.; Stirk, Charles W.

1994-03-01

We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

Transformational electronics are now reconfiguring

KAUST Repository

Rojas, Jhonathan Prieto

2015-05-22

Current developments on enhancing our smart living experience are leveraging the increased interest for novel systems that can be compatible with foldable, wrinkled, wavy and complex geometries and surfaces, and thus become truly ubiquitous and easy to deploy. Therefore, relying on innovative structural designs we have been able to reconfigure the physical form of various materials, to achieve remarkable mechanical flexibility and stretchability, which provides us with the perfect platform to develop enhanced electronic systems for application in entertainment, healthcare, fitness and wellness, military and manufacturing industry. Based on these novel structural designs we have developed a siliconbased network of hexagonal islands connected through double-spiral springs, forming an ultra-stretchable (~1000%) array for full compliance to highly asymmetric shapes and surfaces, as well as a serpentine design used to show an ultrastretchable (~800%) and flexible, spatially reconfigurable, mobile, metallic thin film copper (Cu)-based, body-integrated and non-invasive thermal heater with wireless controlling capability, reusability, heating-adaptability and affordability due to low-cost complementary metal oxide semiconductor (CMOS)-compatible integration. © (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Market-based multiagent system for reconfiguration of shipboard power systems

International Nuclear Information System (INIS)

Huang, Kai; Srivastava, Sanjeev K.; Cartes, David A.; Sun, Li-Hsiang

2009-01-01

On ships, the electric shipboard power system (SPS) supplies electrical power to critical functions such as navigation, communication, emergency systems, and in the case of warships, weapon systems. During ship operation, some parts of the SPS may become unavailable due to damage, fault, or maintenance. For the survivability and reliability of ships, it is desired to make the SPS highly reconfigurable. This paper presents a market-based multiagent system (MAS) for the reconfiguration of radial SPS. Radial SPSs are found on majority of ships. In the proposed MAS, each agent only communicates with its neighbor agents to make the system work in a fully decentralized manner. The MAS is implemented using Java Agent Development Framework (JADE), which is fully implemented in Java and compliant with Foundation of Intelligent Physical Agents (FIPA). An SPS with two generators and four loads is used for testing the proposed MAS. The results show the proposed MAS can successfully reconfigure a radial SPS. (author)

Implementation of Reconfigurable Manufacturing Systems, the Case of The LEGO Group

DEFF Research Database (Denmark)

Wang, Ying; Bilberg, Arne; Hadar, Ronen

of reconfigurable manufacturing systems (RMS). A literature review is made to describe the advantages and core characteristics of RMS. Based on the theory, a conceptual model is developed to analyze where RMS would be most suitable and have most benefits in The LEGO Group. Finally, the conclusion is drawn based...... on the analysis through the model. Keywords: Reconfigurable Manufacturing Systems, Conceptual Model of RMS, Production of The LEGO Group...

Easy Reconfiguration of Modular Industrial Collaborative Robots

DEFF Research Database (Denmark)

Schou, Casper

2016-01-01

the production staff collaborating to perform common tasks. This change of environment imposes a much more dynamic lifecycle for the robot which consequently requires new ways of interacting. This thesis investigates how the changeover to a new task on a collaborative robot can be performed by the shop floor...... operators already working alongside the robot. To effectively perform this changeover, the operator must both reconfigure the hardware of the robot and reprogram the robot to match the new task. To enable shop floor operators to quickly and intuitively program the robot, this thesis proposes the use...... of parametric, task-related robot skills with a manual parameterization method. Reconfiguring the hardware entails adding, removing, or modifying some of the robot’s components. This thesis investigate how software configurator tools can aid the operator in selecting appropriate hardware modules, and how agent...

Validation of multi-body modelling methodology for reconfigurable underwater robots

DEFF Research Database (Denmark)

Nielsen, M.C.; Eidsvik, O. A.; Blanke, Mogens

2016-01-01

This paper investigates the problem of employing reconfigurable robots in an underwater setting. The main results presented is the experimental validation of a modelling methodology for a system consisting of N dynamically connected robots with heterogeneous dynamics. Two distinct types...... of experiments are performed, a series of hydrostatic free-decay tests and a series of open-loop trajectory tests. The results are compared to a simulation based on the modelling methodology. The modelling methodology shows promising results for usage with systems composed of reconfigurable underwater modules...

Resource optimised reconfigurable modular parallel pipelined stochastic approximation-based self-tuning regulator architecture with reduced latency

Directory of Open Access Journals (Sweden)

Varghese Mathew Vaidyan

2015-09-01

Full Text Available Present self-tuning regulator architectures based on recursive least-square estimation are computationally expensive and require large amount of resources and time in generating the first control signal due to computational bottlenecks imposed by the calculations involved in estimation stage, different stages of matrix multiplications and the number of intermediate variables at each iteration and precludes its use in applications that have fast required response times and those which run on embedded computing platforms with low-power or low-cost requirements with constraints on resource usage. A salient feature of this study is that a new modular parallel pipelined stochastic approximation-based self-tuning regulator architecture which reduces the time required to generate the first control signal, reduces resource usage and reduces the number of intermediate variables is proposed. Fast matrix multiplication, pipelining and high-speed arithmetic function implementations were used for improving the performance. Results of implementation demonstrate that the proposed architecture has an improvement in control signal generation time by 38% and reduction in resource usage by 41% in terms of multipliers and 44.4% in terms of adders compared with the best existing related work, opening up new possibilities for the application of online embedded self-tuning regulators.

A framework for plasticity implementation on the SpiNNaker neural architecture.

Science.gov (United States)

Galluppi, Francesco; Lagorce, Xavier; Stromatias, Evangelos; Pfeiffer, Michael; Plana, Luis A; Furber, Steve B; Benosman, Ryad B

2014-01-01

Many of the precise biological mechanisms of synaptic plasticity remain elusive, but simulations of neural networks have greatly enhanced our understanding of how specific global functions arise from the massively parallel computation of neurons and local Hebbian or spike-timing dependent plasticity rules. For simulating large portions of neural tissue, this has created an increasingly strong need for large scale simulations of plastic neural networks on special purpose hardware platforms, because synaptic transmissions and updates are badly matched to computing style supported by current architectures. Because of the great diversity of biological plasticity phenomena and the corresponding diversity of models, there is a great need for testing various hypotheses about plasticity before committing to one hardware implementation. Here we present a novel framework for investigating different plasticity approaches on the SpiNNaker distributed digital neural simulation platform. The key innovation of the proposed architecture is to exploit the reconfigurability of the ARM processors inside SpiNNaker, dedicating a subset of them exclusively to process synaptic plasticity updates, while the rest perform the usual neural and synaptic simulations. We demonstrate the flexibility of the proposed approach by showing the implementation of a variety of spike- and rate-based learning rules, including standard Spike-Timing dependent plasticity (STDP), voltage-dependent STDP, and the rate-based BCM rule. We analyze their performance and validate them by running classical learning experiments in real time on a 4-chip SpiNNaker board. The result is an efficient, modular, flexible and scalable framework, which provides a valuable tool for the fast and easy exploration of learning models of very different kinds on the parallel and reconfigurable SpiNNaker system.

Outline of a Hardware Reconfiguration Framework for Modular Industrial Mobile Manipulators

DEFF Research Database (Denmark)

Schou, Casper; Bøgh, Simon; Madsen, Ole

2014-01-01

This paper presents concepts and ideas of a hard- ware reconfiguration framework for modular industrial mobile manipulators. Mobile manipulators pose a highly flexible pro- duction resource due to their ability to autonomously navigate between workstations. However, due to this high flexibility new...... approaches to the operation of the robots are needed. Reconfig- uring the robot to a new task should be carried out by shop floor operators and, thus, be both quick and intuitive. Late research has already proposed a method for intuitive robot programming. However, this relies on a predetermined hardware...... configuration. Finding a single multi-purpose hardware configuration suited to all tasks is considered unrealistic. As a result, the need for reconfiguration of the hardware is inevitable. In this paper an outline of a framework for making hardware reconfiguration quick and intuitive is presented. Two main...

SaRDIn - A Safe Reconfigurable Distributed Interlocking

DEFF Research Database (Denmark)

Fantechi, Alessandro; Gnesi, S.; Haxthausen, Anne Elisabeth

2016-01-01

Current computer-based interlocking systems most often have a centralized design, with all logic residing in a single computer. Centralized interlockings are complex to design. Following the general trend in Cyber-Physical Systems, the SaRDIn (Safe Reconfigurable Distributed Interlockings) concept...

Homogeneous and single-side-operational connector mechanism for self-reconfigurable, self-assembly and self-healing systems

Science.gov (United States)

Shen, Wei-Min (Inventor); Kovac, Robert M. (Inventor)

2012-01-01

Designs of single-end-operative reconfigurable genderless connectors that include a base, a plurality of movable jaws that are formed on the base and can engage to the jaws of another connector, and an actuator that is mounted on the base and can engage and move the jaws of the reconfigurable connector to connect the reconfigurable connector with another connector.

A reconfigurable all-optical VPN based on XGM effect of SOA in WDM PON

Science.gov (United States)

Hu, Xiaofeng; Zhang, Liang; Cao, Pan; Wang, Tao; Su, Yikai

2010-12-01

We propose and experimentally demonstrate a reconfigurable all-optical VPN scheme enabling intercommunications among different ONUs in a WDM PON. Reconfiguration is realized by dynamically setting wavelength conversion of optical VPN signal using a SOA in the OLT.

PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

Directory of Open Access Journals (Sweden)

T. Tharaneeswaran

2012-06-01

Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

Dynamic reconfiguration of human brain functional networks through neurofeedback.

Science.gov (United States)

Haller, Sven; Kopel, Rotem; Jhooti, Permi; Haas, Tanja; Scharnowski, Frank; Lovblad, Karl-Olof; Scheffler, Klaus; Van De Ville, Dimitri

2013-11-01

Recent fMRI studies demonstrated that functional connectivity is altered following cognitive tasks (e.g., learning) or due to various neurological disorders. We tested whether real-time fMRI-based neurofeedback can be a tool to voluntarily reconfigure brain network interactions. To disentangle learning-related from regulation-related effects, we first trained participants to voluntarily regulate activity in the auditory cortex (training phase) and subsequently asked participants to exert learned voluntary self-regulation in the absence of feedback (transfer phase without learning). Using independent component analysis (ICA), we found network reconfigurations (increases in functional network connectivity) during the neurofeedback training phase between the auditory target region and (1) the auditory pathway; (2) visual regions related to visual feedback processing; (3) insula related to introspection and self-regulation and (4) working memory and high-level visual attention areas related to cognitive effort. Interestingly, the auditory target region was identified as the hub of the reconfigured functional networks without a-priori assumptions. During the transfer phase, we again found specific functional connectivity reconfiguration between auditory and attention network confirming the specific effect of self-regulation on functional connectivity. Functional connectivity to working memory related networks was no longer altered consistent with the absent demand on working memory. We demonstrate that neurofeedback learning is mediated by widespread changes in functional connectivity. In contrast, applying learned self-regulation involves more limited and specific network changes in an auditory setup intended as a model for tinnitus. Hence, neurofeedback training might be used to promote recovery from neurological disorders that are linked to abnormal patterns of brain connectivity. Copyright © 2013 Elsevier Inc. All rights reserved.