WorldWideScience

Sample records for vliw integer microprocessor

  1. DEBUGGER DESIGN FOR MICROPROCESSOR WITH HYBRID ARCHITECTURE OF SUPERSCALAR-VLIW%面向 Superscalar与 VLIW 混合架构处理器的调试器设计

    Institute of Scientific and Technical Information of China (English)

    杨群; 李笑天; 何虎

    2015-01-01

    In this paper we describe the debugger design, which is based on GDB and with hybrid architecture of Superscalar and VLIW double-mode.The debugger design is divided into two parts, the proxy debugging side and the client.The proxy debugging side realises the RSP ( remote serial protocol )-based basic debugging proxy function, and the client side realises the target processor adding, debugger initialisation, and the processing of registers data and opcodes, etc.Test results demonstrate that this debugger achieves the program debugging functions such as remote debugging, checking, modifying the values of registers and memories, adding and deleting breakpoints, disassembly, checking stack information and single stepping, etc.%描述基于GDB的支持超标量( Superscalar)和超长指令字( VLIW)双模式混合架构的调试器设计. 该调试器设计分为代理调试端和客户端两部分,代理调试端实现基于RSP协议的基本调试代理功能,客户端实现目标处理器的添加,调试器初始化,寄存器数据、操作码等的处理. 测试结果表明调试器实现了远程调试,查看、修改寄存器及内存值,添加、删除断点,反汇编,查看栈信息及单步等程序调试功能.

  2. Microprocessors

    CERN Document Server

    Cornillie, O A R

    1985-01-01

    Microprocessors presents an overview of the state of the art in the field of microprocessors and illustrates, with the aid of patents, its utilization and application. Organized into six parts, the book begins with an introduction to the microprocessor, microcomputer, and software. Parts I-III focus on program control, digital control, and electrical motor control. Subsequent parts show the medical applications, measuring instruments, and treatment of data in microprocessors.

  3. A Design for VLIW Microprocessor Based on Minium Operation Unit%基于最小操作单元的VLIW微处理器设计

    Institute of Scientific and Technical Information of China (English)

    王昭顺; 王许书; 王俊宇

    2001-01-01

    in this paper, we presented a new method called granularity analysis method which can analyze developing history of microprocessor architecture, and predicted developing trend of microprocessor architecture with this method. After we presented a new architecture called Minium Operating Unit-Based (MOUB), we also designed and implement a microprocessor model of MOUB.%提出一种微处理器体系结构发展的分析方法一粒度分析方法,并用这种方法分析了微处理器体系结构的发展趋势.在此基础上提出基于最小操作单元MOUUB微处理器体系结构的设计思想,并设计实现了一个这种结构的微处理器模型.

  4. Efficient matrix inversion based on VLIW architecture

    Institute of Scientific and Technical Information of China (English)

    Li Zhang,Fu Li,; Guangming Shi

    2014-01-01

    Matrix inversion is a critical part in communication, signal processing and electromagnetic system. A flexible and scal-able very long instruction word (VLIW) processor with clustered architecture is proposed for matrix inversion. A global register file (RF) is used to connect al the clusters. Two nearby clusters share a local register file. The instruction sets are also designed for the VLIW processor. Experimental results show that the proposed VLIW architecture takes only 45 latency to invert a 4 × 4 matrix when running at 150 MHz. The proposed design is roughly five times faster than the DSP solution in processing speed.

  5. Reconfigurable VLIW Processor for Software Defined Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...

  6. Simulació d'arquitectures VLIW

    OpenAIRE

    2007-01-01

    L'objectiu d'aquest projecte es dissenyar i implementar en Java una interfície gràfica que permeti simular l'arquitectura VLIW. Ha d'interactuar amb un simulador ja existent, VEX, i amb l'usuari. VEX permet analitzar, desenvolupar i depurar codi escrit en C sobre un processador VLIW configurable, des dels recursos hardware fíns al comportament de la "caché". L'interfície gràfica desenvolupada es diu JavaVEX. Té el gran avantatge d'evitar la introducció de les comandes de text que necesita VEX...

  7. Stream Execution on Embedded Wide-Issue Clustered VLIW Architectures

    Directory of Open Access Journals (Sweden)

    Shan Yan

    2009-02-01

    Full Text Available Very long instruction word- (VLIW- based processors have become widely adopted as a basic building block in modern System-on-Chip designs. Advances in clustered VLIW architectures have extended the scalability of the VLIW architecture paradigm to a large number of functional units and very-wide-issue widths. A central challenge with wide-issue clustered VLIW architecture is the availability of programming and automated compiler methods that can fully utilize the available computational resources. Existing compilation approaches for clustered-VLIW architectures are based on extensions of previously developed scheduling algorithms that primarily focus on the maximization of instruction-level parallelism (ILP. However, many applications do not have sufficient ILP to fully utilize a large number of functional units. On the other hand, many applications in digital communications and multimedia processing exhibit enormous amounts of data-level parallelism (DLP. For these applications, the streaming programming paradigm has been developed to explicitly expose coarse-grained data-level parallelism as well as the locality of communication between coarse-grained computation kernels. In this paper, we investigate the mapping of stream programs to wide-issue clustered VLIW processors. Our work enables designers to leverage their existing investments in VLIW-based architecture platforms to harness the advantages of the stream programming paradigm.

  8. Stream Execution on Embedded Wide-Issue Clustered VLIW Architectures

    Directory of Open Access Journals (Sweden)

    Yan Shan

    2008-01-01

    Full Text Available Abstract Very long instruction word- (VLIW- based processors have become widely adopted as a basic building block in modern System-on-Chip designs. Advances in clustered VLIW architectures have extended the scalability of the VLIW architecture paradigm to a large number of functional units and very-wide-issue widths. A central challenge with wide-issue clustered VLIW architecture is the availability of programming and automated compiler methods that can fully utilize the available computational resources. Existing compilation approaches for clustered-VLIW architectures are based on extensions of previously developed scheduling algorithms that primarily focus on the maximization of instruction-level parallelism (ILP. However, many applications do not have sufficient ILP to fully utilize a large number of functional units. On the other hand, many applications in digital communications and multimedia processing exhibit enormous amounts of data-level parallelism (DLP. For these applications, the streaming programming paradigm has been developed to explicitly expose coarse-grained data-level parallelism as well as the locality of communication between coarse-grained computation kernels. In this paper, we investigate the mapping of stream programs to wide-issue clustered VLIW processors. Our work enables designers to leverage their existing investments in VLIW-based architecture platforms to harness the advantages of the stream programming paradigm.

  9. Microprocessor interfacing

    CERN Document Server

    Vears, R E

    2014-01-01

    Microprocessor Interfacing provides the coverage of the Business and Technician Education Council level NIII unit in Microprocessor Interfacing (syllabus U86/335). Composed of seven chapters, the book explains the foundation in microprocessor interfacing techniques in hardware and software that can be used for problem identification and solving. The book focuses on the 6502, Z80, and 6800/02 microprocessor families. The technique starts with signal conditioning, filtering, and cleaning before the signal can be processed. The signal conversion, from analog to digital or vice versa, is expl

  10. Microprocessor engineering

    CERN Document Server

    Holdsworth, B

    2013-01-01

    Microprocessor Engineering provides an insight in the structures and operating techniques of a small computer. The book is comprised of 10 chapters that deal with the various aspects of computing. The first two chapters tackle the basic arithmetic and logic processes. The third chapter covers the various memory devices, both ROM and RWM. Next, the book deals with the general architecture of microprocessor. The succeeding three chapters discuss the software aspects of machine operation, while the last remaining three chapters talk about the relationship of the microprocessor with the outside wo

  11. Fast 2D-DCT implementations for VLIW processors

    OpenAIRE

    Sohm, OP; Canagarajah, CN; Bull, DR

    1999-01-01

    This paper analyzes various fast 2D-DCT algorithms regarding their suitability for VLIW processors. Operations for truncation or rounding which are usually neglected in proposals for fast algorithms have also been taken into consideration. Loeffler's algorithm with parallel multiplications was found to be most suitable due to its parallel structure

  12. Architecture Design of a Variable Length Instruction Set VLIW DSP

    Institute of Scientific and Technical Information of China (English)

    SHEN Zheng; HE Hu; YANG Xu; JIA Di; SUN Yihe

    2009-01-01

    The cost of the central register file and the size of the program code limit the scalability of very long instruction word (VLIW) processors with increasing numbers of functional units. This paper presents the architectural design of a six-way VLIW digital signal processor (DSP) with clustered register files. The archi-tecture uses a variable length instruction set and supports dynamic instruction dispatching. The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB in-struction and data on-chip RAM. A compiler based on the Open64 was developed for the system. Evalua-tions show that the processor is suitable for high performance applications with a high code density and small program code size.

  13. Leakage-Aware Modulo Scheduling for Embedded VLIW Processors

    Institute of Scientific and Technical Information of China (English)

    Yong Guan; Jingling Xue

    2011-01-01

    As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word (VLIW) architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based (Directed Acyclic Graph) leakage-aware scheduling algorithm.

  14. The application of compiler-assisted multiple instruction retry to VLIW architectures

    Science.gov (United States)

    Chen, Shyh-Kwei; Fuchs, W. K.; Hwu, Wen-Mei W.

    1994-01-01

    Very Long Instruction Word (VLIW) architectures enhance performance by exploiting fine-grained instruction level parallelism. We describe the development of two compiler assisted multiple instruction word retry schemes for VLIW architectures. The first scheme utilizes the compiler techniques previously developed for processors with single functional units. A compiler generated hazard-free code with different degrees of rollback capability for uniprocessors is compacted by a modified VLIW trace scheduling algorithm. Nops are then inserted in the scheduled code words to resolve data hazards for VLIW architectures. Performance is compared under three parameters: the rollback distance for uni-processors; the number of functional units; and the rollback distance for VLIW architectures. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards. Performance results are shown for six benchmark programs.

  15. Integer anatomy

    Energy Technology Data Exchange (ETDEWEB)

    Doolittle, R. [ONR, Arlington, VA (United States)

    1994-11-15

    The title integer anatomy is intended to convey the idea of a systematic method for displaying the prime decomposition of the integers. Just as the biological study of anatomy does not teach us all things about behavior of species neither would we expect to learn everything about the number theory from a study of its anatomy. But, some number-theoretic theorems are illustrated by inspection of integer anatomy, which tend to validate the underlying structure and the form as developed and displayed in this treatise. The first statement to be made in this development is: the way structure of the natural numbers is displayed depends upon the allowed operations.

  16. Programming for microprocessors

    CERN Document Server

    Colin, Andrew John Theodore

    1979-01-01

    Programming for Microprocessors deals with the basics of programming for microprocessors and contains practical aids to programming. Topics covered range from assembly language and microprocessor design to the Motorola 6800, programming techniques, control of peripheral devices, and high-level languages. Emphasis is given to the computer-like aspects of microprocessors. This text is comprised of 12 chapters; the first of which provides a general overview of microprocessors, differences between hardwired and programmed devices, and different kinds of microprocessors. The reader is then introduc

  17. Integer programming

    CERN Document Server

    Conforti, Michele; Zambelli, Giacomo

    2014-01-01

    This book is an elegant and rigorous presentation of integer programming, exposing the subject’s mathematical depth and broad applicability. Special attention is given to the theory behind the algorithms used in state-of-the-art solvers. An abundance of concrete examples and exercises of both theoretical and real-world interest explore the wide range of applications and ramifications of the theory. Each chapter is accompanied by an expertly informed guide to the literature and special topics, rounding out the reader’s understanding and serving as a gateway to deeper study. Key topics include: formulations polyhedral theory cutting planes decomposition enumeration semidefinite relaxations Written by renowned experts in integer programming and combinatorial optimization, Integer Programming is destined to become an essential text in the field.

  18. An advanced compiler designed for a VLIW DSP for sensors-based systems.

    Science.gov (United States)

    Yang, Xu; He, Hu

    2012-01-01

    The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems. However, as VLIW codes are mainly compiled statically, the performance of a VLIW processor is dominated by the behavior of its compiler. In this paper, we present an advanced compiler designed for a VLIW DSP named Magnolia, which will be used in sensor-based systems. This compiler is based on the Open64 compiler. We have implemented several advanced optimization techniques in the compiler, and fulfilled the O3 level optimization. Benchmarks from the DSPstone test suite are used to verify the compiler. Results show that the code generated by our compiler can make the performance of Magnolia match that of the current state-of-the-art DSP processors.

  19. An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems

    Directory of Open Access Journals (Sweden)

    Hu He

    2012-04-01

    Full Text Available The VLIW architecture can be exploited to greatly enhance instruction level parallelism, thus it can provide computation power and energy efficiency advantages, which satisfies the requirements of future sensor-based systems. However, as VLIW codes are mainly compiled statically, the performance of a VLIW processor is dominated by the behavior of its compiler. In this paper, we present an advanced compiler designed for a VLIW DSP named Magnolia, which will be used in sensor-based systems. This compiler is based on the Open64 compiler. We have implemented several advanced optimization techniques in the compiler, and fulfilled the O3 level optimization. Benchmarks from the DSPstone test suite are used to verify the compiler. Results show that the code generated by our compiler can make the performance of Magnolia match that of the current state-of-the-art DSP processors.

  20. Microprocessors in Schools?

    Science.gov (United States)

    Cuthbert, L. G.

    1981-01-01

    Examines reasons for including microprocessors in school curricula. Indicates that practical work with microprocessors is not easy and discusses problems associated with using and constructing these control and processing devices of microcomputers. (SK)

  1. Microprocessor prosthetic knees.

    Science.gov (United States)

    Berry, Dale

    2006-02-01

    This article traces the development of microprocessor prosthetic knees from early research in the 1970s to the present. Read about how microprocessor knees work, functional options, patient selection, and the future of this prosthetic.

  2. Introduction to microprocessors

    CERN Document Server

    Aspinall, D

    1977-01-01

    Introduction to Microprocessors introduces the practicing engineer to microprocessors and covers topics ranging from components for information processing to hardware structures and addressing modes, along with support software and structured programming. General principles are illustrated with examples from commercial microprocessors.Comprised of 10 chapters, this book begins with an overview of digital information processing systems and their components, including logic circuits and large scale integration (LSI) digital circuits. A basic microprocessor structure is then described, and case s

  3. Microprocessors principles and applications

    CERN Document Server

    Debenham, Michael J

    1979-01-01

    Microprocessors: Principles and Applications deals with the principles and applications of microprocessors and covers topics ranging from computer architecture and programmed machines to microprocessor programming, support systems and software, and system design. A number of microprocessor applications are considered, including data processing, process control, and telephone switching. This book is comprised of 10 chapters and begins with a historical overview of computers and computing, followed by a discussion on computer architecture and programmed machines, paying particular attention to t

  4. Cumulative Timers for Microprocessors

    Science.gov (United States)

    Battle, John O.

    2007-01-01

    It has been proposed to equip future microprocessors with electronic cumulative timers, for essentially the same reasons for which land vehicles are equipped with odometers (total-distance-traveled meters) and aircraft are equipped with Hobbs meters (total-engine-operating time meters). Heretofore, there has been no way to determine the amount of use to which a microprocessor (or a product containing a microprocessor) has been subjected. The proposed timers would count all microprocessor clock cycles and could only be read by means of microprocessor instructions but, like odometers and Hobbs meters, could never be reset to zero without physically damaging the chip.

  5. VLIW DSP指令级精度模拟器的快速实现方法%Rapid implementation of instruction-level precision VLIW DSP simulator

    Institute of Scientific and Technical Information of China (English)

    朱大林; 郭德源; 何虎

    2013-01-01

    To Develop a simulator of a very long instruction word (VLIW) digital signal processor (DSP) with instruction-level precision at the lowest cost, and reduce the product develop lifecycle, a develop method based on an open source simulator (gem5) is presented. Firstly, the instruction execution processes of gem5 and VLIW DSP are analyzed respectively, it is pointed out that the conflict between the sequential execution with pure 32 bit instruction environment on gem5 simulator and the parallel execution with 16/32 mixed instruction environment on VLIW DSP is one of the difficulties in the development Then, based on the sequential execution model of gem5 simulator, a VLIW DSP model is constructed by adding a parallel judgment and execution mechanism and a 16/32 bit mix instruction fetch mechanism, A VLIW DSP simulator is implemented Finally, by running a set of test case for every instruction and a set of typical application of DSP, the validity and feasibility of the develop method is demonstrated%为了以最小代价开发出超长指令字(VLIW)数字信号处理器(DSP)的指令级精度的模拟器,缩短开发周期,提出了一种基于开源模拟器(gem5)的开发方法.对gem5模拟器和VLIW DSP的指令执行流程分别进行分析,指出指令在gem5模拟器上以纯32位指令环境顺序执行和指令在VLIW DSP上以16/32位混合指令环境并行执行之间的矛盾是开发的难点.在gem5的顺序执行模型的基础上,通过加入并行的判决、执行机制和16/32位混合指令的取指机制建立了VLIWDSP的模型,并具体实现了一款VLIW DSP的模拟器.通过一组针对每条指令的测试程序和一组DSP典型应用程序验证了该方法的正确性和可行性.

  6. Newnes microprocessor pocket book

    CERN Document Server

    Money, Steve

    2014-01-01

    Newnes Microprocessor Pocket Book explains the basic hardware operation of a microprocessor and describes the actions of the various types of instruction that can be executed. A summary of the characteristics of many of the popular microprocessors is presented. Apart from the popular 8- and 16-bit microprocessors, some details are also given of the popular single chip microcomputers and of the reduced instruction set computer (RISC) type processors such as the Transputer, Novix FORTH processor, and Acorn ARM processor.Comprised of 15 chapters, this book discusses the principles involved in bot

  7. Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Manju Rani

    2012-07-01

    Full Text Available FPGA implementation of 64-bit execute unit for VLIW processor, and improve power representation have been done in this paper. VHDL is used to modelled this architecture. VLIW stands for Very Long Instruction Word. This Processor Architecture is based on parallel processing in which more than one instruction is executed in parallel. This architecture is used to increase the instruction throughput. So this is the base of the modern Superscalar Processors. Basically VLIW is a RISC Processor. The difference is it contains long instruction as compared to RISC. This stage of the pipeline executes the instruction. This is the stage where the ALU (arithmetic logic unit is located. Execute stage are synthesized and targeted for Xilinx Virtex 4 FPGA and the results calculated for 64-bit Execute stage improve the power as compared to previous work done.

  8. Microprocessors and the Curriculum.

    Science.gov (United States)

    Pasahow, Edward J.

    1981-01-01

    Presents three approaches to teaching the use of a microprocessor: (1) a "generic" device on paper; (2) a "conglomeration" device, surveying a number of real products; and (3) the "how" course which covers a small number of actual but related microprocessors. (CT)

  9. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  10. Redundant Asynchronous Microprocessor System

    Science.gov (United States)

    Meyer, G.; Johnston, J. O.; Dunn, W. R.

    1985-01-01

    Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.

  11. Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures

    Directory of Open Access Journals (Sweden)

    Haijing Tang

    2013-01-01

    Full Text Available Clustering has become a common trend in very long instruction words (VLIW architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explicit inter-cluster data move operations in traditional bus-connected clustered (BCC VLIW architecture. However, the limit number of access ports to the global register file has become an issue which must be well addressed; otherwise the performance and energy consumption would be harmed. In this paper, we presented compiler optimization techniques for an RFCC VLIW architecture called Lily, which is designed for encryption systems. These techniques aim at optimizing performance and energy consumption for Lily architecture, through appropriate manipulation of the code generation process to maintain a better management of the accesses to the global register file. All the techniques have been implemented and evaluated. The result shows that our techniques can significantly reduce the penalty of performance and energy consumption due to access port limitation of global register file.

  12. Run-time Adaptable VLIW Processors: Resources, Performance, Power Consumption, and Reliability Trade-offs

    NARCIS (Netherlands)

    Anjam, F.

    2013-01-01

    In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor organizat

  13. Run-time Adaptable VLIW Processors: Resources, Performance, Power Consumption, and Reliability Trade-offs

    NARCIS (Netherlands)

    Anjam, F.

    2013-01-01

    In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor

  14. Generic interpreters and microprocessor verification

    Science.gov (United States)

    Windley, Phillip J.

    1990-01-01

    The following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocessors; (3) microprocessor verification; (4) determining correctness; (5) hierarchical decomposition; (6) interpreter theory; (7) AVM-1; (8) phase-level specification; and future work.

  15. The Integer Abacus.

    Science.gov (United States)

    Dirks, Michael K.

    1984-01-01

    The abacus method for instruction on addition, subtraction, and multiplication with integers is explained. How to represent the integers for each operation is detailed with words and illustrations. (MNS)

  16. Sums of Consecutive Integers

    Science.gov (United States)

    Pong, Wai Yan

    2007-01-01

    We begin by answering the question, "Which natural numbers are sums of consecutive integers?" We then go on to explore the set of lengths (numbers of summands) in the decompositions of an integer as such sums.

  17. An Interdisciplinary Microprocessor Project.

    Science.gov (United States)

    Wilcox, Alan D.; And Others

    1985-01-01

    Describes an unusual project in which third-year computer science students designed and built a four-bit multiplier circuit and then combines it with software to complete a full 16-bit multiplication. The multiplier was built using TTL components, interfaced with a Z-80 microprocessor system, and programed in assembly language. (JN)

  18. Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

    Directory of Open Access Journals (Sweden)

    Hoare Raymond R

    2006-01-01

    Full Text Available This paper presents an architecture that combines VLIW (very long instruction word processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1 a 4-way VLIW processor implemented in an FPGA, (2 large speedups through hardware functions, (3 a hardware/software interface with zero overhead, (4 a design methodology for implementing signal processing applications on this architecture, (5 tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to times that of software with an average times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

  19. Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

    Science.gov (United States)

    Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.

    2010-12-01

    The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

  20. Synchronous clock stopper for microprocessor

    Science.gov (United States)

    Kitchin, David A. (Inventor)

    1985-01-01

    A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.

  1. Mark IVA microprocessor support

    Science.gov (United States)

    Burford, A. L.

    1982-01-01

    The requirements and plans for the maintenance support of microprocessor-based controllers in the Deep Space Network Mark IVA System are discussed. Additional new interfaces and 16-bit processors have introduced problems not present in the Mark III System. The need for continuous training of maintenance personnel to maintain a level of expertise consistent with the sophistication of the required tools is also emphasized.

  2. Minerva multi-microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Widdoes, L.C. Jr.

    1975-12-01

    A multiprocessor system is described which is an experiment in low-cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described. 2 figures, 2 tables.

  3. Self-Checking Pairs Of Microprocessors

    Science.gov (United States)

    Smith, Brian S.

    1995-01-01

    Method of imparting fault tolerance to computer system provides for immediate detection of faults at microprocessor level. Shadow microprocessor provides nominal duplicate outputs to verify functioning of main microprocessor. When output signal on any pin of one microprocessor differs from that on corresponding pin of other microprocessor, comparator puts out alarm signal.

  4. Shutters with embedded microprocessors

    Science.gov (United States)

    Stephenson, S.

    2015-06-01

    Shutters are used to periodically provide a non-uniformity correction (NUC) calibration surface to micro bolometers. Many bolometer applications, such as TWS and DVE, require compact, power efficient actuators. Actuators in these applications, such as bistable solenoids and stepper motors, benefit from complex drive schemes. Consumer electronics products have generated compact, low-cost drive components that can be used to embed complex drives into these shutters. Shutter drives using these components maintain compactness and power efficiency while simplifying interfaces at minimal cost. Recently, several commercially available shutter systems have been created that incorporate embedded microprocessors into shutters usable for NUC correction of micro bolometers.

  5. Integers annual volume 2013

    CERN Document Server

    Landman, Bruce

    2014-01-01

    ""Integers"" is a refereed online journal devoted to research in the area of combinatorial number theory. It publishes original research articles in combinatorics and number theory. This work presents all papers of the 2013 volume in book form.

  6. A scalable and low power VLIW DSP core for embedded system design

    Institute of Scientific and Technical Information of China (English)

    Sheraz Anjum; CHEN Jie; HAN Liang; LIN Chuan; ZHANG Xiao-xiao; SU Ye-hua; Chip Cheng

    2008-01-01

    Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to exe-cute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less num-ber of functional units according to the intended application. Low power support was added by careful architectur-al design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations,especially for compute intensive applications such as wire-line and wireless communications, including infrastruc-ture and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effec-tively reduce the power consumption, chip area and time to market the intended final product.

  7. Autoregulatory mechanisms controlling the microprocessor.

    Science.gov (United States)

    Triboulet, Robinson; Gregory, Richard I

    2011-01-01

    The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature ∼22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part of a newly identified regulatory mechanism controlling Microprocessor activity.

  8. A TRNSYS microprocessor controller

    Science.gov (United States)

    Piessens, L. P.; Beckman, W. A.; Mitchell, J. W.

    A truth table approach is employed to model the operation of a microprocessor controller for a solar energy system. Using the simulation code TRNSYS, a parameter is added to stop iteration procedures which potentially could become endless as the program seeks a solution to a set of governing equations at the same time as a pump or switch is turned off, thus creating a stable mode of iteration. The simulation of control logic also includes comparisons between input signals in order to arrive at a choice of output control signals. Temperatures are the normal input signals, and additional input may be mass flow rate, insolation, and night setbacks. Techniques for identifying typographical errors in the control logic are explored, as are the effects of the time step size chosen. Results are presented of simulations of month-long operation of a solar system and primary loop control strategies.

  9. Introducing the Intel i860 64-bit microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Kohn, L.; Margulis, N. (Intel Corp., Santa Clara, CA (USA))

    1989-08-01

    The development of a single-chip i860 CPU 64-bit, RISC-based microprocessor is reported in this article. It executes parallel instructions using mainframe and supercomputer architectural concepts. The authors designed the 1,000,000-transistor, 10 mm x 15 mm processor for balanced integer, floating-point, and graphics performance. To accommodate their performance goals, they divided the chip area evenly between blocks for integer operations, floating-point operations, and instruction and data cache memories. Inclusion of the RISC (reduced instruction set computing) core, floating-point units, and caches on one chip allowed design of wider internal buses, eliminated interchip communication over-head, and enabled higher performance. As a result, the i860 avoids off-chip delays and allows users to scale the clock beyond the current 33- and 40- MHz speeds. Applications described include workstations, minicomputers, application accelerators for existing processors, and parallel supercomputers.

  10. Integer and combinatorial optimization

    CERN Document Server

    Nemhauser, George L

    1999-01-01

    Rave reviews for INTEGER AND COMBINATORIAL OPTIMIZATION ""This book provides an excellent introduction and survey of traditional fields of combinatorial optimization . . . It is indeed one of the best and most complete texts on combinatorial optimization . . . available. [And] with more than 700 entries, [it] has quite an exhaustive reference list.""-Optima ""A unifying approach to optimization problems is to formulate them like linear programming problems, while restricting some or all of the variables to the integers. This book is an encyclopedic resource for such f

  11. Integer Equal Flows

    Energy Technology Data Exchange (ETDEWEB)

    Meyers, C A; Schulz, A S

    2009-01-07

    The integer equal flow problem is an NP-hard network flow problem, in which all arcs in given sets R{sub 1}, ..., R{sub {ell}} must carry equal flow. We show this problem is effectively inapproximable, even if the cardinality of each set R{sub k} is two. When {ell} is fixed, it is solvable in polynomial time.

  12. Encrypted integer division

    NARCIS (Netherlands)

    Veugen, P.J.M.

    2010-01-01

    When processing signals in the encrypted domain, homomorphic encryption can be used to enable linear operations on encrypted data. Integer division of encrypted data however requires an additional protocol with the server and will be relatively expensive. We present new solutions for dividing encryp

  13. Cellular functions of the microprocessor.

    Science.gov (United States)

    Macias, Sara; Cordiner, Ross A; Cáceres, Javier F

    2013-08-01

    The microprocessor is a complex comprising the RNase III enzyme Drosha and the double-stranded RNA-binding protein DGCR8 (DiGeorge syndrome critical region 8 gene) that catalyses the nuclear step of miRNA (microRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as an endonuclease. Recent global analyses of microprocessor and Dicer proteins have suggested novel functions for these components independent of their role in miRNA biogenesis. A HITS-CLIP (high-throughput sequencing of RNA isolated by cross-linking immunoprecipitation) experiment designed to identify novel substrates of the microprocessor revealed that this complex binds and regulates a large variety of cellular RNAs. The microprocessor-mediated cleavage of several classes of RNAs not only regulates transcript levels, but also modulates alternative splicing events, independently of miRNA function. Importantly, DGCR8 can also associate with other nucleases, suggesting the existence of alternative DGCR8 complexes that may regulate the fate of a subset of cellular RNAs. The aim of the present review is to provide an overview of the diverse functional roles of the microprocessor.

  14. Extended gcd of quadratic integers

    CERN Document Server

    Miled, Abdelwaheb

    2010-01-01

    Computation of the extended gcd of two quadratic integers. The ring of integers considered is principal but could be euclidean or not euclidean ring. This method rely on principal ideal ring and reduction of binary quadratic forms.

  15. Microprocessors: from desktops to supercomputers.

    Science.gov (United States)

    Baskett, F; Hennessy, J L

    1993-08-13

    Continuing improvements in integrated circuit technology and computer architecture have driven microprocessors to performance levels that rival those of supercomputers-at a fraction of the price. The use of sophisticated memory hierarchies enables microprocessor-based machines to have very large memories built from commodity dynamic random access memory while retaining the high bandwidth and low access time needed in a high-performance machine. Parallel processors composed of these high-performance microprocessors are becoming the supercomputing technology of choice for scientific and engineering applications. The challenges for these new supercomputers have been in developing multiprocessor architectures that are easy to program and that deliver high performance without extraordinary programming efforts by users. Recent progress in multiprocessor architecture has led to ways to meet these challenges.

  16. Microprocessors in detectors and analysis

    Energy Technology Data Exchange (ETDEWEB)

    Siskind, E.J.

    1982-01-01

    The increasing need in high energy physics experiments for computation power for both online and offline applications, coupled with the current microprocessor revolution, has led to the examination of the use of microprocessors in various aspects of HEP computing. A brief (and admittedly somewhat biased) review is given of current hardware products, the costs of developing and producing hardware systems, and the costs of providing appropriate software support tools which allow one to make effective use of physicists' time, and the applicability of certain systems to the various needs of HEP computing.

  17. Investigating Students’ Development of Learning Integer Concept and Integer Addition

    Directory of Open Access Journals (Sweden)

    Nenden Octavarulia Shanty

    2016-09-01

    Full Text Available This research aimed at investigating students’ development of learning integer concept and integer addition. The investigation was based on analyzing students’ works in solving the given mathematical problems in each instructional activity designed based on Realistic Mathematics Education (RME levels. Design research was chosen to achieve and to contribute in developing a local instruction theory for teaching and learning of integer concept and integer addition. In design research, the Hypothetical Learning Trajectory (HLT plays important role as a design and research instrument. It was designed in the phase of preliminary design and tested to three students of grade six OASIS International School, Ankara – Turkey. The result of the experiments showed that temperature in the thermometer context could stimulate students’ informal knowledge of integer concept. Furthermore, strategies and tools used by the students in comparing and relating two temperatures were gradually be developed into a more formal mathematics. The representation of line inside thermometer which then called the number line could bring the students to the last activity levels, namely rules for adding integer, and became the model for more formal reasoning. Based on these findings, it can be concluded that students’ learning integer concept and integer addition developed through RME levels.Keywords: integer concept, integer addition, Realistic Mathematics Education DOI: http://dx.doi.org/10.22342/jme.7.2.3538.57-72

  18. Microprocessor Simulation: A Training Technique.

    Science.gov (United States)

    Oscarson, David J.

    1982-01-01

    Describes the design and application of a microprocessor simulation using BASIC for formal training of technicians and managers and as a management tool. Illustrates the utility of the modular approach for the instruction and practice of decision-making techniques. (SK)

  19. DSS 13 microprocessor antenna controller

    Science.gov (United States)

    Gosline, R. M.

    1988-01-01

    A microprocessor-based antenna monitor and control system with multiple CPUs are described. The system was developed as part of the unattended station project for DSS 13 and was enhanced for use by the SETI project. The operational features, hardware, and software designs are described, and a discussion is provided of the major problems encountered.

  20. Integer-valued trawl processes

    DEFF Research Database (Denmark)

    Barndorff-Nielsen, Ole E.; Lunde, Asger; Shephard, Neil;

    2014-01-01

    This paper introduces a new continuous-time framework for modelling serially correlated count and integer-valued data. The key component in our new model is the class of integer-valued trawl processes, which are serially correlated, stationary, infinitely divisible processes. We analyse the proba......This paper introduces a new continuous-time framework for modelling serially correlated count and integer-valued data. The key component in our new model is the class of integer-valued trawl processes, which are serially correlated, stationary, infinitely divisible processes. We analyse...

  1. Microprocessor controlled transdermal drug delivery.

    Science.gov (United States)

    Subramony, J Anand; Sharma, Ashutosh; Phipps, J B

    2006-07-06

    Transdermal drug delivery via iontophoresis is reviewed with special focus on the delivery of lidocaine for local anesthesia and fentanyl for patient controlled acute therapy such as postoperative pain. The role of the microprocessor controller in achieving dosimetry, alternating/reverse polarity, pre-programmed, and sensor-based delivery is highlighted. Unique features such as the use of tactile signaling, telemetry control, and pulsatile waveforms in iontophoretic drug delivery are described briefly.

  2. Microprocessor control of photovoltaic systems

    Science.gov (United States)

    Millner, A. R.; Kaufman, D. L.

    1984-01-01

    The present low power CMOS microprocessor controller for photovoltaic power systems possesses three programs, which are respectively intended for (1) conventional battery-charging systems with state-of-charge estimation and sequential shedding of subarrays and loads, (2) maximum power-controlled battery-charging systems, and (3) variable speed dc motor drives. Attention is presently given to the development of this terrestrial equipment for spacecraft use.

  3. Microprocessor-controlled ultrasonic plethysmograph

    Science.gov (United States)

    Bhagat, P. K.; Wu, V. C.

    1981-01-01

    Safe, nonintrusive microprocessor system times ultrasonic pulses to measure limb cross-sectional area. Simple instrument requires no calibration and does not confine leg movement, making tests relating limb volume to activity level possible. Program considers more realistic geometries of human limb than circular cross-sections and monitors changes in area with great accuracy. Errors due to body temperature changes and timing roundoff are insignificant.

  4. Integer roots of quadratic and cubic polynomials with integer coefficients

    CERN Document Server

    Zelator, Konstantine

    2011-01-01

    The subject matter of this work is quadratic and cubic polynomial functions with integer coefficients;and all of whose roots are integers. The material of this work is directed primarily at educators,students,and teachers of mathematics,grades K12 to K20.The results of this work are expressed in Theorems3,4,and5. Of these theorems, Theorem3, is the one that most likely, the general reader of this article will have some familiarity with.In Theorem3, precise coefficient conditions are given;in order that a quadratic trinomial(with integer) have two integer roots or zeros.On the other hand, Theorems4 and5 are largely unfamiliar territory. In Theorem4, precise coefficient conditions are stated; for a monic cubic polynomial to have a double(i.e.of multiplicity 2) integer root, and a single integer root(i.e.of multiplicity 1).The entire family of such cubics can be described in terms of four groups or subfamilies; each such group being a two-integer parameter subfamily. In Theorem5, a one-integer parameter family o...

  5. Integer and Half-Integer Quantization Conditions in Quantum Mechanics

    Institute of Scientific and Technical Information of China (English)

    DUAN Yi-Shi; JIA Duo-Jie

    2001-01-01

    The integer and half-integer quantization conditions are found in quantum mechanics based on the topological structure of symmetry group of the singlet and spinor wavefunction. The internal symmetry of the physical system is shown to be sufficient to determine the topological structure in quantum mechanics without taking int account the dynamical details about the interaction.

  6. Microprocessor based systems for the higher technician

    CERN Document Server

    Vears, RE

    2013-01-01

    Microprocessor Based Systems for the Higher Technician provides coverage of the BTEC level 4 unit in Microprocessor Based Systems (syllabus U80/674). This book is composed of 10 chapters and concentrates on the development of 8-bit microcontrollers specifically constructed around the Z80 microprocessor. The design cycle for the development of such a microprocessor based system and the use of a disk-based development system (MDS) as an aid to design are both described in detail. The book deals with the Control Program Monitor (CP/M) operating system and gives background information on file hand

  7. JOVIAL/Ada Microprocessor Study.

    Science.gov (United States)

    1982-04-01

    Technical Report Kernighan , B., and Mashey, J., "The UNIX Programing Environment", Computer 14:4, April 1981, pp. 12-24. Kildall, G., "A Unified Approach to...UCSD is a trademark of the Regents of the University of California) UNIX An operating system ( UNIX is a trademark of Bell Laboratories) VAX A...version of UNIX . An eight-user system costs about $30,000. 19 JOVIAL/Ada Microprocessor Study Final Technical Report Another Z8000-based system is the

  8. Design of Simulator for VLIW Processor%VLIW架构处理器软件模拟器设计

    Institute of Scientific and Technical Information of China (English)

    黄光红; 王昊

    2014-01-01

    分析VLIW架构处理器特点,设计周期级精确的指令集模拟器。模拟器被按照功能划分为若干具有规范接口的模块。通过修改、替换模块可快速构建新模型,具有较好的可扩展性。采用高效的二进制指令译码算法和JIT-CCS技术提高性能。实践表明,本模拟器在处理器设计过程中起到重要作用。%Analyzing VLIW architecture processor, this paper designs a instruction set simulator with cycle accurate. According function, the simulator is divided to several module which with standard interface. The simulator is flexible and is able to become other processor prototype fast by modification and replacing.Adopting efficient decoding arithmetic for binary instruction and JIT-CCS, the simulator obtains excellent performance. The result demonstrates that the simulator can work effectively for design VLIW processor.

  9. Integer Quadratic Quasi-polyhedra

    Science.gov (United States)

    Letchford, Adam N.

    This paper introduces two fundamental families of 'quasi-polyhedra' - polyhedra with a countably infinite number of facets - that arise in the context of integer quadratic programming. It is shown that any integer quadratic program can be reduced to the minimisation of a linear function over a quasi-polyhedron in the first family. Some fundamental properties of the quasi-polyhedra are derived, along with connections to some other well-studied convex sets. Several classes of facet-inducing inequalities are also derived. Finally, extensions to the mixed-integer case are briefly examined.

  10. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  11. Microprocessors in the Curriculum and the Classroom.

    Science.gov (United States)

    Summers, M. K.

    1978-01-01

    This article, directed at teachers concerned with computer science courses at sixth-form level with no prior knowledge of microprocessors, provides a basic introduction, and describes possible applications of a microprocessor development system as a teaching aid in computer sciences courses in UK secondary school. (Author/RAO)

  12. Microprocessor-Controlled Laser Balancing System

    Science.gov (United States)

    Demuth, R. S.

    1985-01-01

    Material removed by laser action as part tested for balance. Directed by microprocessor, laser fires appropriate amount of pulses in correct locations to remove necessary amount of material. Operator and microprocessor software interact through video screen and keypad; no programing skills or unprompted system-control decisions required. System provides complete and accurate balancing in single load-and-spinup cycle.

  13. PageRank of integers

    CERN Document Server

    Frahm, K M; Shepelyansky, D L

    2012-01-01

    We build up a directed network tracing links from a given integer to its divisors and analyze the properties of the Google matrix of this network. The PageRank vector of this matrix is computed numerically and it is shown that its probability is inversely proportional to the PageRank index thus being similar to the Zipf law and the dependence established for the World Wide Web. The spectrum of the Google matrix of integers is characterized by a large gap and a relatively small number of nonzero eigenvalues. A simple semi-analytical expression for the PageRank of integers is derived that allows to find this vector for matrices of billion size. This network provides a new PageRank order of integers.

  14. Microprocessor controlled portable TLD system

    Science.gov (United States)

    Apathy, I.; Deme, S.; Feher, I.

    1996-01-01

    An up-to-date microprocessor controlled thermoluminescence dosemeter (TLD) system for environmental and space dose measurements has been developed. The earlier version of the portable TLD system, Pille, was successfully used on Soviet orbital stations as well as on the US Space Shuttle, and for environmental monitoring. The new portable TLD system, Pille'95, consists of a reader and TL bulb dosemeters, and each dosemeter is provided with an EEPROM chip for automatic identification. The glow curve data are digitised and analysed by the program of the reader. The measured data and the identification number appear on the LED display of the reader. Up to several thousand measured data together with the glow curves can be stored on a removable flash memory card. The whole system is supplied either from built-in rechargeable batteries or from the mains of the space station.

  15. Ionizing radiation effects on SBP9900 microprocessor

    Science.gov (United States)

    Stanley, A. G.; Mallen, W.; Springer, P.

    1977-01-01

    The radiation resistance of a 16-bit microprocessor based on integrated injection logic technology has been investigated. Cumulative fluences of 10 to the 12th power to 10 to the 14th power e/sq cm were used in the radiation-resistance study. Complete failure of the microprocessor was noted at a fluence level of 1.2 times 10 to the 14th power e/sq cm. Though the radiation resistance of the microprocessor makes it suited for space applications, reductions in the power dissipation of the device are needed.

  16. Image Watermarking Method Using Integer-to-Integer Wavelet Transforms

    Institute of Scientific and Technical Information of China (English)

    陈韬; 王京春

    2002-01-01

    Digital watermarking is an efficient method for copyright protection for text, image, audio, and video data. This paper presents a new image watermarking method based on integer-to-integer wavelet transforms. The watermark is embedded in the significant wavelet coefficients by a simple exclusive OR operation. The method avoids complicated computations and high computer memory requirements that are the main drawbacks of common frequency domain based watermarking algorithms. Simulation results show that the embedded watermark is perceptually invisible and robust to various operations, such as low quality joint picture expert group (JPEG) compression, random and Gaussian noises, and smoothing (mean filtering).

  17. Note on Integer Factoring Methods IV

    OpenAIRE

    Carella, N. A.

    2008-01-01

    This note continues the theoretical development of deterministic integer factorization algorithms based on systems of polynomials equations. The main result establishes a new deterministic time complexity bench mark in integer factorization.

  18. A Euclidean algorithm for integer matrices

    DEFF Research Database (Denmark)

    Lauritzen, Niels; Thomsen, Jesper Funch

    2015-01-01

    We present a Euclidean algorithm for computing a greatest common right divisor of two integer matrices. The algorithm is derived from elementary properties of finitely generated modules over the ring of integers.......We present a Euclidean algorithm for computing a greatest common right divisor of two integer matrices. The algorithm is derived from elementary properties of finitely generated modules over the ring of integers....

  19. Controller Chips Preserve Microprocessor Function

    Science.gov (United States)

    2012-01-01

    Above the Atlantic Ocean, off the coast of Brazil, there is a dip in the Earth s surrounding magnetic field called the South Atlantic Anomaly. Here, space radiation can reach into Earth s upper atmosphere to interfere with the functioning of satellites, aircraft, and even the International Space Station. "The South Atlantic Anomaly is a hot spot of radiation that the space station goes through at a certain point in orbit," Miria Finckenor, a physicist at Marshall Space Flight Center, describes, "If there s going to be a problem with the electronics, 90 percent of that time, it is going to be in that spot." Space radiation can cause physical damage to microchips and can actually change the software commands in computers. When high-energy particles penetrate a satellite or other spacecraft, the electrical components can absorb the energy and temporarily switch off. If the energy is high enough, it can cause the device to enter a hung state, which can only be addressed by restarting the system. When space radiation affects the operational status of microprocessors, the occurrence is called single event functional interrupt (SEFI). SEFI happens not only to the computers onboard spacecraft in Earth orbit, but to the computers on spacecraft throughout the solar system. "One of the Mars rovers had this problem in the radiation environment and was rebooting itself several times a day. On one occasion, it rebooted 40 times in one day," Finckenor says. "It s hard to obtain any data when you have to constantly reboot and start over."

  20. Microprocessor utilization in search and rescue missions

    Science.gov (United States)

    Schwartz, M.; Bashkow, T.

    1978-01-01

    The position of an emergency transmitter may be determined by measuring the Doppler shift of the distress signal as received by an orbiting satellite. This requires the computation of an initial estimate and refinement of this estimate through an iterative, nonlinear, least squares estimation. A version of the algorithm was implemented and tested by locating a transmitter on the premises and obtaining observations from a satellite. The computer used was an IBM 360/95. The position was determined within the desired 10 km radius accuracy. The feasibility of performing the same task in real time using microprocessor technology, was determined. The least squares algorithm was implemented on an Intel 8080 microprocessor. The results indicate that a microprocessor can easily match the IBM implementation in accuracy and be performed inside the time limitations set.

  1. On minimal integer representations of weighted games

    CERN Document Server

    Freixas, Josep

    2011-01-01

    We study minimum integer representations for the weights of weighted games, which is linked with some solution concepts in game theory. Closing some gaps in the existing literature we prove that each weighted game with two types of voters admits a unique minimum integer presentation and give examples for more than two types of voters without a minimum integer representation. We characterize the possible weights in minimum integer representations and give examples for at least four types of voters without minimum integer representations preserving types.

  2. Integer programming theory, applications, and computations

    CERN Document Server

    Taha, Hamdy A

    1975-01-01

    Integer Programming: Theory, Applications, and Computations provides information pertinent to the theory, applications, and computations of integer programming. This book presents the computational advantages of the various techniques of integer programming.Organized into eight chapters, this book begins with an overview of the general categorization of integer applications and explains the three fundamental techniques of integer programming. This text then explores the concept of implicit enumeration, which is general in a sense that it is applicable to any well-defined binary program. Other

  3. A Microprocessor Project for Non-Electrical Engineering Students.

    Science.gov (United States)

    Swingler, D. N.

    1981-01-01

    Offers rationale for and a description of a microprocessor-based control system project for mechanical engineering students. Includes reasons for selecting a Texas Instruments TM990/189 microprocessor system. (SK)

  4. Fast resolution of integer Vandermonde systems

    Directory of Open Access Journals (Sweden)

    Rosa di Salvo

    2014-10-01

    Full Text Available The resolution of polynomial interpolation problems with integer coefficients directly involves the open issue of the integer inversion of a general Vandermonde matrix defined over the field Z/pZ, for p prime number. The purpose of this paper is to demonstrate the possibility to invert a Vandermonde matrix with integer mod p coefficients and exactly compute the integer inverse matrix in the ring Mat(Z/pZ of square matrices over Z/pZ through the new fast algorithm InVanderMOD. The explicit formula derived for the integer inversion of Vandermonde matrices entirely develops inside the field of the integers mod p, with due consideration to the operation of integer division. The inversion procedure InVanderMOD is valid for any prime number p and competitive in terms of computational effort, since its computational cost is less than O(n^3.

  5. Microprocessor system design a practical introduction

    CERN Document Server

    Spinks, Michael J

    2013-01-01

    Microprocessor System Design: A Practical Introduction describes the concepts and techniques incorporated into the design of electronic circuits, particularly microprocessor boards and their peripherals. The book reviews the basic building blocks of the electronic systems composed of digital (logic levels, gate output circuitry) and analog components (resistors, capacitors, diodes, transistors). The text also describes operational amplifiers (op-amp) that use a negative feedback technique to improve the parameters of the op-amp. The design engineer can use programmable array logic (PAL) to rep

  6. Simplified design of microprocessor-supervisory circuits

    CERN Document Server

    Lenk, John

    1998-01-01

    This is the seventh book in the popular Simplified Design series from John Lenk, which teaches engineers, technicians, and students to use and modify off-the-shelf ICs to suit their individual design needs.The first chapter of this book describes the basic operation of microprocessor supervisory circuits and how to use manufacturer data sheets to make your component selections. Later chapters describe the internal operations of various commonly-available ICs and how to select and modify them.The most common microprocessor-supervisory functions include: power-on reset, low-volta

  7. Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

    Science.gov (United States)

    Liu, Yuan-Kwei

    1991-01-01

    The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

  8. MICROPROCESSOR CONTROLLED FOR SMART DISTRI ESSOR ...

    African Journals Online (AJOL)

    eobe

    In this work, analysis and development of a mi deployment in a ... nd development of a microprocessor controlled capacitor bank switchi istribution .... an output which is proportional to the voltage on the ... 2.1.3 The design of the control unit.

  9. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  10. A Microprocessor Architecture for Bibliographic Retrieval System.

    Science.gov (United States)

    Martella, G.; Gobbi, G.

    1981-01-01

    Proposes a microprocessor-based architecture that makes large use of parallelism both in processing and in retrieval operations. The proposed system consists of three functional blocks: the query processor, simple query executers, and the answer composer. Twenty-one references are listed. (FM)

  11. VELA: A Microprocessor-Based Laboratory Instrument.

    Science.gov (United States)

    Lambert, Andrew

    1983-01-01

    Provides a general description of a preprogramed, microprocessor-based laboratory instrument, discussing its use in monitoring: (1) environmental changes; (2) distribution of count rates from a radioactive source, and (3) motion on an air tract. Includes list of the instrument's various capabilities: frequency meter, voltmeter, interval timer, and…

  12. Microprocessor-Based Laboratory Data Acquisition Systems.

    Science.gov (United States)

    Woodard, F. E.; And Others

    1981-01-01

    Focuses on attributes of microcomputer systems which affect their usefulness in a laboratory environment. In addition to presenting general concepts, comments are made regarding the implementation of these concepts using a microprocessor-based data acquisition system developed at the University of North Carolina. (CO)

  13. Functional Anatomy of the Human Microprocessor.

    Science.gov (United States)

    Nguyen, Tuan Anh; Jo, Myung Hyun; Choi, Yeon-Gil; Park, Joha; Kwon, S Chul; Hohng, Sungchul; Kim, V Narry; Woo, Jae-Sung

    2015-06-04

    MicroRNA (miRNA) maturation is initiated by Microprocessor composed of RNase III DROSHA and its cofactor DGCR8, whose fidelity is critical for generation of functional miRNAs. To understand how Microprocessor recognizes pri-miRNAs, we here reconstitute human Microprocessor with purified recombinant proteins. We find that Microprocessor is an ∼364 kDa heterotrimeric complex of one DROSHA and two DGCR8 molecules. Together with a 23-amino acid peptide from DGCR8, DROSHA constitutes a minimal functional core. DROSHA serves as a "ruler" by measuring 11 bp from the basal ssRNA-dsRNA junction. DGCR8 interacts with the stem and apical elements through its dsRNA-binding domains and RNA-binding heme domain, respectively, allowing efficient and accurate processing. DROSHA and DGCR8, respectively, recognize the basal UG and apical UGU motifs, which ensure proper orientation of the complex. These findings clarify controversies over the action mechanism of DROSHA and allow us to build a general model for pri-miRNA processing.

  14. Educational Implications of Microelectronics and Microprocessors.

    Science.gov (United States)

    Harris, N. D. C., Ed.

    This conference report explores microelectronic technology, its effect on educational methods and objectives, and its implications for educator responsibilities. Two main areas were considered: the significance of the likely impact of the large scale introduction of microprocessors and microelectronics on commercial and industrial processes, the…

  15. Could a Neuroscientist Understand a Microprocessor?

    Science.gov (United States)

    Jonas, Eric; Kording, Konrad Paul

    2017-01-01

    There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.

  16. Applied Integer Programming Modeling and Solution

    CERN Document Server

    Chen, Der-San; Dang, Yu

    2011-01-01

    An accessible treatment of the modeling and solution of integer programming problems, featuring modern applications and software In order to fully comprehend the algorithms associated with integer programming, it is important to understand not only how algorithms work, but also why they work. Applied Integer Programming features a unique emphasis on this point, focusing on problem modeling and solution using commercial software. Taking an application-oriented approach, this book addresses the art and science of mathematical modeling related to the mixed integer programming (MIP) framework and

  17. IMPLEMENTATION OF USER INTERFACE FOR MICROPROCESSOR TRAINER

    Directory of Open Access Journals (Sweden)

    TinMarKyi

    2011-07-01

    Full Text Available This paper aims to design and construct the microcontroller - based userinterface system and to study input, computation and output for microprocessor trainer.The other two activities beyond computation :input and output or I/O.This paper also aims to do high quality research in the area of filesystems, as well as develop a good implementation on atleast one computersystem. A computersystem's I/O performance must be commensurate (equal with its CPU performance if the I/O system is not to limit the system's total throughput.When hundreds to thousands of such highperformance micro-processors are closely connected inscalablearray architecture, the enormous CPU performance of the multi-computer requires an I/O system with correspondingly high performance.A wellbalanced computer requires I/O performance commensurate with its CPU performance. High performance computers, access large numbers of disks in parallel to achieve the very appreciable I/O performance.

  18. Simplified microprocessor design for VLSI control applications

    Science.gov (United States)

    Cameron, K.

    1991-01-01

    A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

  19. Design of a Distributed Microprocessor Sensor System

    Science.gov (United States)

    1990-04-01

    implemented through these methods, multiversion software and recovery the use of multiple identical software tasks running on blocks, are intended to... Multiversion software for real-time systems tolerant microprocessor that uses three processing is discussed by Shepherd32, Hitt33, Avizienis’, and...tasks and the there are no data available to determine the cost third is used for noncritical tasks. If a discrepancy effectiveness of multiversion

  20. Hardware math for the 6502 microprocessor

    Science.gov (United States)

    Kissel, R.; Currie, J.

    1985-01-01

    A floating-point arithmetic unit is described which is being used in the Ground Facility of Large Space Structures Control Verification (GF/LSSCV). The experiment uses two complete inertial measurement units and a set of three gimbal torquers in a closed loop to control the structural vibrations in a flexible test article (beam). A 6502 (8-bit) microprocessor controls four AMD 9511A floating-point arithmetic units to do all the computation in 20 milliseconds.

  1. Stochastic Programming with Simple Integer Recourse

    NARCIS (Netherlands)

    Louveaux, François V.; van der Vlerk, Maarten H.

    1993-01-01

    Stochastic integer programs are notoriously difficult. Very few properties are known and solution algorithms are very scarce. In this paper, we introduce the class of stochastic programs with simple integer recourse, a natural extension of the simple recourse case extensively studied in stochastic c

  2. Integer Programming Models for Computational Biology Problems

    Institute of Scientific and Technical Information of China (English)

    Giuseppe Lancia

    2004-01-01

    The recent years have seen an impressive increase in the use of Integer Programming models for the solution of optimization problems originating in Molecular Biology. In this survey, some of the most successful Integer Programming approaches are described, while a broad overview of application areas being is given in modern Computational Molecular Biology.

  3. Formal verification of an avionics microprocessor

    Science.gov (United States)

    Srivas, Mandayam, K.; Miller, Steven P.

    1995-01-01

    Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This report discusses a project undertaken to answer some of these questions, the formal verification of the AAMPS microprocessor. This project consisted of formally specifying in the PVS language a rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show that the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.

  4. NSC 800, 8-bit CMOS microprocessor

    Science.gov (United States)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  5. Effective integer-to-integer transforms for JPEG2000 coder

    Science.gov (United States)

    Przelaskowski, Artur

    2001-12-01

    This paper considers reversible transforms which are used in wavelet compression according to nowadays JPEG2000 standard. Original data decomposition in a form of integer wavelet transformation realized in subband decomposition scheme is optimized by design and selection of the most effective transforms. Lifting scheme is used to construct new biorthogonal symmetric wavelets. Number and distribution of vanishing moments, subband coding gain, associated filter length, computational complexity and number of lifting steps were mainly analyzed in the optimization of designed transforms. Coming from many tests of compression efficiency evaluation in JPEG2000 standardization process, the best selected transforms have been compared to designed ones to conclude the most efficient for compression wavelet bases and their important features. Certain new transforms overcome all other in both phases of lossy-to-lossless compression (e.g. up to 0.5 dB of PSNR for 0.5 bpp in comparison to the state-of-art transforms of JPEG2000 compression, and up to 3dB over 5/3 standard reversible transform). Moreover, the lossy compression efficiency of proposed reversible wavelets is comparable to reference irreversible wavelets potential in several cases. The highest improvement over that reference PSNR values is close to 1.2 dB.

  6. SNOOP module CAMAC interface to the 168/E microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Bernstein, D.; Carroll, J.T.; Mitnick, V.H.; Paffrath, L.; Parker, D.B.

    1979-10-01

    A pair of 168/E microprocessors will be used to meet the realtime computing requirements of the SLAC Hybrid Facility. A SNOOP module and 168/E Interface provide the link between the host computer and the microprocessors. By eavesdropping on normal CAMAC read operations, the SNOOP provides a direct data transfer from CAMAC to microprocessor memory. The host computer controls the processors using standard CAMAC programmed I/O to the SNOOP.

  7. A High-performance Fetch Pipeline Based On the VLIW DSP Architecture%一种基于VLIW DSP架构的高性能取指流水线

    Institute of Scientific and Technical Information of China (English)

    杨惠; 陈书明; 万江华

    2011-01-01

    以超长指令字(VLIW)数字信号处理器(DSP)作为平台,针对现有提高单线程取指流水线效率的方法中存在的弊端,提出了一种高性能的取指流水架构.该架构支持无效取指的检测与作废,从而降低不必要的cacbe访问,减少取指流水停顿周期,该结构还引入专用硬件支持编译调度的循环软流水,有效提高指令并行性,降低代码存储空间,由此释放出的单线程取指流水线的空闲周期约达46.34%.实验结果表明,相比优化前的取指流水而言,代码空同压缩约11.93%,执行周期缩短约8.67%,cache访同次数下降约12.84%,指令cache暂停周期缩短约7.86%,处理器单线程的指令吞吐率平均提高约11.7%.%For the drawbacks existent in single-thread fetch pipeline to improve the efficiency, a high-performance fetch pipeline structure is proposed in tins paper based on the platform of the VIIW digital signal processor ( DSP). It can support the detection and void for the invalid fetch, bypass for die missing fetch, which reduces the unnecessary cache access and fetch pipeline stall. The structure also inducts dedicated hardware which supports the software pipeline of scheduled compilation to improve the parallelism of instruction. It reduces the code memory space) and the idle cycles of released single-threaded pipeline is reached up to about 46.34%. Compared with the fetch pipeline before optimized, experiment results show that the code storage space is reduced about 11.93%, the average execution cycle is shortened about 8.67%, the cache access times is decreased about 12.84%, the suspension period of instruction cache is shortened about 7.86%, and die single-threaded instruction throughput of processor is increased by 11.7%.

  8. Parallel Integer Relation Detection: Techniques and Applications

    OpenAIRE

    Bailey, David H.; Broadhurst, David J.

    1999-01-01

    Let $\\{x_1, x_2, ..., x_n\\}$ be a vector of real numbers. An integer relation algorithm is a computational scheme to find the $n$ integers $a_k$, if they exist, such that $a_1 x_1 + a_2 x_2 + ... + a_n x_n= 0$. In the past few years, integer relation algorithms have been utilized to discover new results in mathematics and physics. Existing programs for this purpose require very large amounts of computer time, due in part to the requirement for multiprecision arithmetic, yet are poorly suited ...

  9. 76 FR 39895 - In the Matter of Certain Microprocessors, Components Thereof, and Products Containing Same...

    Science.gov (United States)

    2011-07-07

    ... COMMISSION In the Matter of Certain Microprocessors, Components Thereof, and Products Containing Same; Notice... importation, and the sale within the United States after importation of certain microprocessors, components... sale within the United States after importation of certain microprocessors, components thereof,...

  10. EnABLing microprocessor for apoptosis.

    Science.gov (United States)

    Tu, Chi-Chiang; Wang, Jean Y J

    The Microprocessor complex consisting of DROSHA (a type III ribonuclease) and DGCR8 (DiGeorge syndrome critical region gene 8-encoded RNA binding protein) recognizes and cleaves the precursor microRNA hairpin (pre-miRNA) from the primary microRNA transcript (pri-miRNA). The Abelson tyrosine kinase 1 (ABL) phosphorylates DGCR8 to stimulate the cleavage of a subset of pro-apoptotic pri-miRNAs, thus expanding the nuclear functions of ABL to include regulation of RNA processing.

  11. Microprocessor architectures RISC, CISC and DSP

    CERN Document Server

    Heath, Steve

    1995-01-01

    'Why are there all these different processor architectures and what do they all mean? Which processor will I use? How should I choose it?' Given the task of selecting an architecture or design approach, both engineers and managers require a knowledge of the whole system and an explanation of the design tradeoffs and their effects. This is information that rarely appears in data sheets or user manuals. This book fills that knowledge gap.Section 1 provides a primer and history of the three basic microprocessor architectures. Section 2 describes the ways in which the architectures react with the

  12. Microprocessor-controlled, programmable ramp voltage generator

    Energy Technology Data Exchange (ETDEWEB)

    Hopwood, J.

    1978-11-01

    A special-purpose voltage generator has been developed for driving the quadrupole mass filter of a residual gas analyzer. The generator is microprocessor-controlled with desired ramping parameters programmed by setting front-panel digital thumb switches. The start voltage, stop voltage, and time of each excursion are selectable. A maximum of five start-stop levels may be pre-selected for each program. The ramp voltage is 0 to 10 volts with sweep times from 0.1 to 999.99 seconds.

  13. Microprocessor controlled proof-mass actuator

    Science.gov (United States)

    Horner, Garnett C.

    1987-01-01

    The objective of the microprocessor controlled proof-mass actuator is to develop the capability to mount a small programmable device on laboratory models. This capability will allow research in the active control of flexible structures. The approach in developing the actuator will be to mount all components as a single unit. All sensors, electronic and control devices will be mounted with the actuator. The goal for the force output capability of the actuator will be one pound force. The programmable force actuator developed has approximately a one pound force capability over the usable frequency range, which is above 2 Hz.

  14. Garbageless reversible implementation of integer linear transformations

    DEFF Research Database (Denmark)

    Burignat, Stéphane; Vermeirsch, Kenneth; De Vos, Alexis;

    2013-01-01

    Discrete linear transformations are important tools in information processing. Many such transforms are injective and therefore prime candidates for a physically reversible implementation into hardware. We present here reversible digital implementations of different integer transformations on fou...

  15. On a correlational clustering of integers

    OpenAIRE

    Aszalós László; Hajdu Lajos (1968-) (matematikus); Pethő Attila (1950-) (matematikus, informatikus)

    2016-01-01

    Correlation clustering is a concept of machine learning. The ultimate goal of such a clustering is to find a partition with minimal conflicts. In this paper we investigate a correlation clustering of integers, based upon the greatest common divisor.

  16. Solving Parity Games on Integer Vectors

    OpenAIRE

    Abdulla, Parosh Aziz; Mayr, Richard; Sangnier, Arnaud; Sproston, Jeremy

    2013-01-01

    We consider parity games on infinite graphs where configurations are represented by control-states and integer vectors. This framework subsumes two classic game problems: parity games on vector addition systems with states (vass) and multidimensional energy parity games. We show that the multidimensional energy parity game problem is inter-reducible with a subclass of single-sided parity games on vass where just one player can modify the integer counters and the opponent can only change contr...

  17. An 8b organic microprocessor on plastic foil

    NARCIS (Netherlands)

    Myny, K.; Veenendaal, E. van; Gelinck, G.H.; Genoe, J.; Dehaene, W.; Heremans, P.

    2011-01-01

    We introduce a microprocessor made by organic thin-film transistors processed directly onto flexible plastic foil. This is a direct realization of a microprocessor by thin-film technology, i.e., without transfer, on plastic. It paves the way to equip mundane supports and objects with low-cost comput

  18. Information Technologies for the 1980's: Lasers and Microprocessors.

    Science.gov (United States)

    Mathews, William D.

    This discussion of the development and application of lasers and microprocessors to information processing stresses laser communication in relation to capacity, reliability, and cost and the advantages of this technology to real-time information access and information storage. The increased capabilities of microprocessors are reviewed, and a…

  19. Microprocessor-based single particle calibration of scintillation counter

    Science.gov (United States)

    Mazumdar, G. K. D.; Pathak, K. M.

    1985-01-01

    A microprocessor-base set-up is fabricated and tested for the single particle calibration of the plastic scintillator. The single particle response of the scintillator is digitized by an A/D converter, and a 8085 A based microprocessor stores the pulse heights. The digitized information is printed. Facilities for CRT display and cassette storing and recalling are also made available.

  20. Slip and Slide Method of Factoring Trinomials with Integer Coefficients over the Integers

    Science.gov (United States)

    Donnell, William A.

    2012-01-01

    In intermediate and college algebra courses there are a number of methods for factoring quadratic trinomials with integer coefficients over the integers. Some of these methods have been given names, such as trial and error, reversing FOIL, AC method, middle term splitting method and slip and slide method. The purpose of this article is to discuss…

  1. Elementary Theory of Factoring Trinomials with Integer Coefficients over the Integers

    Science.gov (United States)

    Donnell, William A.

    2010-01-01

    An important component of intermediate and college algebra courses involves teaching students methods to factor a trinomial with integer coefficients over the integers. The aim of this article is to present a theoretical justification of that which is often taught, but really never explained as to why it works. The theory is presented, and a…

  2. OS friendly microprocessor architecture: Hardware level computer security

    Science.gov (United States)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  3. The MMU Implementation of Unity-1 Microprocessor

    Institute of Scientific and Technical Information of China (English)

    Song Chuanhua(宋传华); Cheng Xu; Zhu Dexin

    2003-01-01

    Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management mechanism between the operating system and user programs. This paper analyzes the tradeoffs considered in the MMU design of Unity-11 CPU of Peking University, and introduces in detail the solution of pure hardware table walking with two-level page table organization. The implementation takes care of required operations and high performances needed by modern operating systems and low costs needed by embedded systems. This solution has been silicon proven, and successfully porting the Linux 2.4.17 kernel, the Xwindow system, GNOME and most application software onto the Unity platform.

  4. Proceedings: DISE Workshop on Microprocessors and Education (Fort Collins, Colorado, August 16-18, 1976).

    Science.gov (United States)

    Pittsburgh Univ., PA. Dept. of Electrical Engineering.

    Papers presented during four sessions of a workshop, which addressed the role of microprocessors in education, are included in this publication. The issues covered involved seven areas: (1) views of the microelectronics industry; (2) microprocessor architecture; (3) microprocessor chip design; (4) microprocessor software; (5) the impact of…

  5. Linear and integer programming made easy

    CERN Document Server

    Hu, T C

    2016-01-01

    Linear and integer programming are fundamental toolkits for data and information science and technology, particularly in the context of today’s megatrends toward statistical optimization, machine learning, and big data analytics. Drawn from over 30 years of classroom teaching and applied research experience, this textbook provides a crisp and practical introduction to the basics of linear and integer programming. The authors’ approach is accessible to students from all fields of engineering, including operations research, statistics, machine learning, control system design, scheduling, formal verification, and computer vision. Readers will learn to cast hard combinatorial problems as mathematical programming optimizations, understand how to achieve formulations where the objective and constraints are linear, choose appropriate solution methods, and interpret results appropriately. •Provides a concise introduction to linear and integer programming, appropriate for undergraduates, graduates, a short cours...

  6. Integer Discontinuity of Density Functional Theory

    CERN Document Server

    Mosquera, Martin A

    2014-01-01

    Density functional approximations to the exchange-correlation energy of Kohn-Sham theory, such as the local density approximation and generalized gradient approximations, lack the well-known integer discontinuity, a feature that is critical to describe molecular dissociation correctly. Moreover, standard approximations to the exchange-correlation energy also fail to yield the correct linear dependence of the ground-state energy on the number of electrons when this is a non-integer number obtained from the grand canonical ensemble statistics. We present a formal framework to restore the integer discontinuity of any density functional approximation. Our formalism derives from a formula for the exact energy functional and a new constrained search functional that recovers the linear dependence of the energy on the number of electrons.

  7. The engineering of microprocessor systems guidelines on system development

    CERN Document Server

    1979-01-01

    The Engineering of Microprocessor Systems: Guidelines on System Development provides economical and technical guidance for use when incorporating microprocessors in products or production processes and assesses the alternatives that are available. This volume is part of Project 0251 undertaken by The Electrical Research Association, which aims to give managers and development engineers advice and comment on the development process and the hardware and software needed to support the engineering of microprocessor systems. The results of Phase 1 of the five-phase project are contained in this fir

  8. Hermitian K-theory of the integers

    OpenAIRE

    Berrick, A. J.; Karoubi, M.

    2005-01-01

    The 2-primary torsion of the higher algebraic K-theory of the integers has been computed by Rognes and Weibel. In this paper we prove analogous results for the Hermitian K-theory of the integers with 2 inverted (denoted by Z'). We also prove in this case the analog of the Lichtenbaum conjecture for the hermitian K-theory of Z' : the homotopy fixed point set of a suitable Z/2 action on the classifying space of the algebraic K-theory of Z' is the hermitian K-theory of Z' after 2-adic completion.

  9. NEW ALGORITHM FOR FAST INTEGER AMBIGUITY RESOLUTION

    Institute of Scientific and Technical Information of China (English)

    HEXiao-feng; HUXiao-ping

    2005-01-01

    Fast integer ambiguity resolution is referred as a key part in precision relative positioning of the GPS carrier phase. A new algorithm for fast integer ambiguity resolution based on LAMBDA and FASF methods is proposed. This algorithm integrates the LAMBDA method and the FASF method, thus improving the efficiency of the ambiguity resolution. Firstly, the ambiguity search space transformation in the LAMBDA method is used,and then the FASF method is used to search ambiguities. Experiments in the relative positioning of about 1 km static baseline demonstrate that the error is less than 1 cm.

  10. A Binomial Integer-Valued ARCH Model.

    Science.gov (United States)

    Ristić, Miroslav M; Weiß, Christian H; Janjić, Ana D

    2016-11-01

    We present an integer-valued ARCH model which can be used for modeling time series of counts with under-, equi-, or overdispersion. The introduced model has a conditional binomial distribution, and it is shown to be strictly stationary and ergodic. The unknown parameters are estimated by three methods: conditional maximum likelihood, conditional least squares and maximum likelihood type penalty function estimation. The asymptotic distributions of the estimators are derived. A real application of the novel model to epidemic surveillance is briefly discussed. Finally, a generalization of the introduced model is considered by introducing an integer-valued GARCH model.

  11. Multiparametric programming based algorithms for pure integer and mixed-integer bilevel programming problems

    KAUST Repository

    Domínguez, Luis F.

    2010-12-01

    This work introduces two algorithms for the solution of pure integer and mixed-integer bilevel programming problems by multiparametric programming techniques. The first algorithm addresses the integer case of the bilevel programming problem where integer variables of the outer optimization problem appear in linear or polynomial form in the inner problem. The algorithm employs global optimization techniques to convexify nonlinear terms generated by a reformulation linearization technique (RLT). A continuous multiparametric programming algorithm is then used to solve the reformulated convex inner problem. The second algorithm addresses the mixed-integer case of the bilevel programming problem where integer and continuous variables of the outer problem appear in linear or polynomial forms in the inner problem. The algorithm relies on the use of global multiparametric mixed-integer programming techniques at the inner optimization level. In both algorithms, the multiparametric solutions obtained are embedded in the outer problem to form a set of single-level (M)(I)(N)LP problems - which are then solved to global optimality using standard fixed-point (global) optimization methods. Numerical examples drawn from the open literature are presented to illustrate the proposed algorithms. © 2010 Elsevier Ltd.

  12. CONDITIONAL FACTORIZATION BASED ON LATTICE THEORY FOR -INTEGERS

    Institute of Scientific and Technical Information of China (English)

    Zheng Yonghui; Zhu Yuefei

    2008-01-01

    In this paper, the integer N = pkq is called a -integer, if p and q are odd primes with almost the same size and k is a positive integer. Such integers were previously proposed for various cryptographic applications. The conditional factorization based on lattice theory for n-bit -integers is considered, and there is an algorithm in time polynomial in n to factor these integers if the least significant |(2k-1)n/(3k-1)(k-1)| bits of p are given.

  13. The Microprocessor controls the activity of mammalian retrotransposons.

    Science.gov (United States)

    Heras, Sara R; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L; Cáceres, Javier F

    2013-10-01

    More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons and a defender of human genome integrity.

  14. State of the art: benchmarking microprocessors for embedded automotive applications

    Directory of Open Access Journals (Sweden)

    Adnan Shaout

    2016-09-01

    Full Text Available Benchmarking microprocessors provides a way for consumers to evaluate the performance of the processors. This is done by using either synthetic or real world applications. There are a number of benchmarks that exist today to assist consumers in evaluating the vast number of microprocessors that are available in the market. In this paper an investigation of the various benchmarks available for evaluating microprocessors for embedded automotive applications will be performed. We will provide an overview of the following benchmarks: Whetstone, Dhrystone, Linpack, standard performance evaluation corporation (SPEC CPU2006, embedded microprocessor benchmark consortium (EEMBC AutoBench and MiBench. A comparison of existing benchmarks will be given based on relevant characteristics of automotive applications which will give the proper recommendation when benchmarking processors for automotive applications.

  15. Analysis of Setups of the Control of Rail Microprocessor Systems

    Directory of Open Access Journals (Sweden)

    Mieczyslaw Kornaszewski

    2008-01-01

    Full Text Available In the article will have been introduced possibilities following from the application of the microprocessor technology in rail systems of the control of traffic will remain for example of modern signalling on railway crossings. Introduction to microcomputer and microprocessor systems of rail devices will permit to eliminate and to replace disusedrelay devices with them and raising safety on railway and increasing reliability of used devices.

  16. The design of a microprocessor-based data logger

    Science.gov (United States)

    Leap, K.J.; Dedini, L.A.

    1982-01-01

    The design of a microprocessor-based data logger, which collects and digitizes analog voltage signals from a continuous-measuring instrumentation system and transmits serial data to a magnetic tape recorder, is discussed. The data logger was assembled from commercially-available components and can be user-programmed for greater flexibility. A description of the data logger hardware and software designs, general operating instructions, the microprocessor program listing, and electrical schematic diagrams are presented.

  17. Quadratic forms representing all odd positive integers

    CERN Document Server

    Rouse, Jeremy

    2011-01-01

    We consider the problem of classifying all positive-definite integer-valued quadratic forms that represent all positive odd integers. Kaplansky considered this problem for ternary forms, giving a list of 23 candidates, and proving that 19 of those represent all positive odds. (Jagy later dealt with a 20th candidate.) Assuming that the remaining three forms represent all positive odds, we prove that an arbitrary, positive-definite quadratic form represents all positive odds if and only if it represents the odd numbers from 1 up to 451. This result is analogous to Bhargava and Hanke's celebrated 290-theorem. In addition, we prove that these three remaining ternaries represent all positive odd integers, assuming the generalized Riemann hypothesis. This result is made possible by a new analytic method for bounding the cusp constants of integer-valued quaternary quadratic forms $Q$ with fundamental discriminant. This method is based on the analytic properties of Rankin-Selberg $L$-functions, and we use it to prove...

  18. Linear and integer programming theory and practice

    CERN Document Server

    Sierksma, Gerard

    2001-01-01

    Linear optimisation; basic concepts; Dantzig's simplex method; duality and optimality; sensitivity analysis; karmarkar's interior path method; integer linear optimisation; linear network models; computational complexity issues; model building, case studies, and advanced techniques; solutions to selected exercises. Appendices: linear algebra; convexity; graph theory; optimisation theory; computer package INTPM.

  19. Sums of Integer Squares: A New Look.

    Science.gov (United States)

    Sastry, K. R. S.; Pranesachar, C. R.; Venkatachala, B. J.

    1998-01-01

    Focuses on the study of the sum of two integer squares, neither of which is zero square. Develops some new interesting and nonstandard ideas that can be put to use in number theory class, mathematics club meetings, or popular lectures. (ASK)

  20. Predecessor queries in dynamic integer sets

    DEFF Research Database (Denmark)

    Brodal, Gerth Stølting

    1997-01-01

    We consider the problem of maintaining a set of n integers in the range 0.2w–1 under the operations of insertion, deletion, predecessor queries, minimum queries and maximum queries on a unit cost RAM with word size w bits. Let f (n) be an arbitrary nondecreasing smooth function satisfying n...

  1. Integer programming techniques for educational timetabling

    DEFF Research Database (Denmark)

    Fonseca, George H.G.; Santos, Haroldo G.; Carrano, Eduardo G.

    2017-01-01

    in recent studies in the field. This work presents new cuts and reformulations for the existing integer programming model for XHSTT. The proposed cuts improved hugely the linear relaxation of the formulation, leading to an average gap reduction of 32%. Applied to XHSTT-2014 instance set, the alternative...

  2. Mixed integer evolution strategies for parameter optimization.

    Science.gov (United States)

    Li, Rui; Emmerich, Michael T M; Eggermont, Jeroen; Bäck, Thomas; Schütz, M; Dijkstra, J; Reiber, J H C

    2013-01-01

    Evolution strategies (ESs) are powerful probabilistic search and optimization algorithms gleaned from biological evolution theory. They have been successfully applied to a wide range of real world applications. The modern ESs are mainly designed for solving continuous parameter optimization problems. Their ability to adapt the parameters of the multivariate normal distribution used for mutation during the optimization run makes them well suited for this domain. In this article we describe and study mixed integer evolution strategies (MIES), which are natural extensions of ES for mixed integer optimization problems. MIES can deal with parameter vectors consisting not only of continuous variables but also with nominal discrete and integer variables. Following the design principles of the canonical evolution strategies, they use specialized mutation operators tailored for the aforementioned mixed parameter classes. For each type of variable, the choice of mutation operators is governed by a natural metric for this variable type, maximal entropy, and symmetry considerations. All distributions used for mutation can be controlled in their shape by means of scaling parameters, allowing self-adaptation to be implemented. After introducing and motivating the conceptual design of the MIES, we study the optimality of the self-adaptation of step sizes and mutation rates on a generalized (weighted) sphere model. Moreover, we prove global convergence of the MIES on a very general class of problems. The remainder of the article is devoted to performance studies on artificial landscapes (barrier functions and mixed integer NK landscapes), and a case study in the optimization of medical image analysis systems. In addition, we show that with proper constraint handling techniques, MIES can also be applied to classical mixed integer nonlinear programming problems.

  3. Integer least-squares theory for the GNSS compass

    NARCIS (Netherlands)

    Teunissen, P.J.G.

    2010-01-01

    Global navigation satellite system (GNSS) carrier phase integer ambiguity resolution is the key to highprecision positioning and attitude determination. In this contribution, we develop new integer least-squares (ILS) theory for the GNSS compass model, together with efficient integer search strategi

  4. On the Delone property of (−β-integers

    Directory of Open Access Journals (Sweden)

    Wolfgang Steiner

    2011-08-01

    Full Text Available The (−β-integers are natural generalisations of the β-integers, and thus of the integers, for negative real bases. They can be described by infinite words which are fixed points of anti-morphisms. We show that they are not necessarily uniformly discrete and relatively dense in the real numbers.

  5. Integer least-squares theory for the GNSS compass

    NARCIS (Netherlands)

    Teunissen, P.J.G.

    2010-01-01

    Global navigation satellite system (GNSS) carrier phase integer ambiguity resolution is the key to highprecision positioning and attitude determination. In this contribution, we develop new integer least-squares (ILS) theory for the GNSS compass model, together with efficient integer search

  6. Logic integer programming models for signaling networks.

    Science.gov (United States)

    Haus, Utz-Uwe; Niermann, Kathrin; Truemper, Klaus; Weismantel, Robert

    2009-05-01

    We propose a static and a dynamic approach to model biological signaling networks, and show how each can be used to answer relevant biological questions. For this, we use the two different mathematical tools of Propositional Logic and Integer Programming. The power of discrete mathematics for handling qualitative as well as quantitative data has so far not been exploited in molecular biology, which is mostly driven by experimental research, relying on first-order or statistical models. The arising logic statements and integer programs are analyzed and can be solved with standard software. For a restricted class of problems the logic models reduce to a polynomial-time solvable satisfiability algorithm. Additionally, a more dynamic model enables enumeration of possible time resolutions in poly-logarithmic time. Computational experiments are included.

  7. PSLQ: An Algorithm to Discover Integer Relations

    Energy Technology Data Exchange (ETDEWEB)

    Bailey, David H.; Borwein, J. M.

    2009-04-03

    Let x = (x{sub 1}, x{sub 2} {hor_ellipsis}, x{sub n}) be a vector of real or complex numbers. x is said to possess an integer relation if there exist integers a{sub i}, not all zero, such that a{sub 1}x{sub 1} + a{sub 2}x{sub 2} + {hor_ellipsis} + a{sub n}x{sub n} = 0. By an integer relation algorithm, we mean a practical computational scheme that can recover the vector of integers ai, if it exists, or can produce bounds within which no integer relation exists. As we will see in the examples below, an integer relation algorithm can be used to recognize a computed constant in terms of a formula involving known constants, or to discover an underlying relation between quantities that can be computed to high precision. At the present time, the most effective algorithm for integer relation detection is the 'PSLQ' algorithm of mathematician-sculptor Helaman Ferguson [10, 4]. Some efficient 'multi-level' implementations of PSLQ, as well as a variant of PSLQ that is well-suited for highly parallel computer systems, are given in [4]. PSLQ constructs a sequence of integer-valued matrices B{sub n} that reduces the vector y = xB{sub n}, until either the relation is found (as one of the columns of B{sub n}), or else precision is exhausted. At the same time, PSLQ generates a steadily growing bound on the size of any possible relation. When a relation is found, the size of smallest entry of the vector y abruptly drops to roughly 'epsilon' (i.e. 10{sup -p}, where p is the number of digits of precision). The size of this drop can be viewed as a 'confidence level' that the relation is real and not merely a numerical artifact - a drop of 20 or more orders of magnitude almost always indicates a real relation. Very high precision arithmetic must be used in PSLQ. If one wishes to recover a relation of length n, with coefficients of maximum size d digits, then the input vector x must be specified to at least nd digits, and one must employ nd

  8. Integer sparse distributed memory: analysis and results.

    Science.gov (United States)

    Snaider, Javier; Franklin, Stan; Strain, Steve; George, E Olusegun

    2013-10-01

    Sparse distributed memory is an auto-associative memory system that stores high dimensional Boolean vectors. Here we present an extension of the original SDM, the Integer SDM that uses modular arithmetic integer vectors rather than binary vectors. This extension preserves many of the desirable properties of the original SDM: auto-associativity, content addressability, distributed storage, and robustness over noisy inputs. In addition, it improves the representation capabilities of the memory and is more robust over normalization. It can also be extended to support forgetting and reliable sequence storage. We performed several simulations that test the noise robustness property and capacity of the memory. Theoretical analyses of the memory's fidelity and capacity are also presented.

  9. Recursion formulas for the evaluation of the parabolic cylinder function with integer and half-integer orders

    NARCIS (Netherlands)

    D. Veestraeten

    2015-01-01

    Sums of the parabolic cylinder function for, in absolute value, growing half-integer and integer orders emerge in numerous fields such as time-series analysis, quantum optics and transmission in wireless channels. This paper derives recursion formulas for the parabolic cylinder function with integer

  10. Solving Integer Programming by Evolutionary Soft Agent

    Institute of Scientific and Technical Information of China (English)

    Yin Jian

    2003-01-01

    Many practical problems in commerce and industry involve finding the best way to allocate scarce resources a mong competing activities. This paper focuses on the problem of integer programming, and describes an evolutionary soft agent model to solve it. In proposed model, agent is composed of three components: goal, environment and behavior. Experirnental shows thne model has the characters of parallel computing and goal driving.

  11. The Microprocessor controls the activity of mammalian retrotransposons

    DEFF Research Database (Denmark)

    Heras, Sara R.; Macias, Sara; Plass, Mireya

    2013-01-01

    More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogen......More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for micro......RNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions...... of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor...

  12. 78 FR 3449 - Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements...

    Science.gov (United States)

    2013-01-16

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements... a limited exclusion order as to subject Intel microprocessors, but that implementation be...

  13. 78 FR 12354 - Certain Microprocessors, Components Thereof, and Products Containing Same; Termination of...

    Science.gov (United States)

    2013-02-22

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Microprocessors, Components Thereof, and Products Containing Same; Termination of... microprocessors, Apple Inc. of Cupertino, California (``Apple''); and Hewlett-Packard Company of Palo...

  14. Microprocessors in Systems Engineering at the U.S. Naval Academy.

    Science.gov (United States)

    Mitchell, Eugene E., Ed.; Lowe, W. M., Ed.

    1982-01-01

    Describes the introduction of microprocessors into the Weapons and Systems Engineering Department at the U.S. Naval Academy, including planning decisions, implementation, procedures, uses of microprocessors in the department, and impact on the Systems Engineering major and curriculum. (SK)

  15. Single event effect testing of the Intel 80386 family and the 80486 microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Moran, A.; LaBel, K.; Gates, M. [NASA/GSFC, Greenbelt, MD (United States); Seidleck, C. [Hughes ST Systems, Greenbelt, MD (United States); McGraw, R. [Jackson and Tull, Greenbelt, MD (United States); Broida, M.; Firer, J. [Daedalian Systems Corp., Greenbelt, MD (United States); Sprehn, S. [Lystad Ltd., Crownsville, MD (United States)

    1996-06-01

    The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored.

  16. Modular, Microprocessor-Controlled Flash Lighting System

    Science.gov (United States)

    Kiefer, Dwayne; Gray, Elizabeth; Skupinski, Robert; Stachowicz, Arthur; Birchenough, William

    2006-01-01

    A microprocessor-controlled lighting system generates brief, precisely timed, high-intensity flashes of light for scientific imaging at frame rates up to about 1 kHz. The system includes an array of light-emitting diodes (LEDs) that are driven in synchronism with an externally generated timing signal (for example, a timing signal generated by a video camera). The light output can be varied in peak intensity, pulse duration, pulse delay, and pulse rate, all depending on the timing signal and associated externally generated control signals. The array of LEDs comprises as many as 16 LED panels that can be attached together. Each LED panel is a module consisting of a rectangular subarray of 10 by 20 LEDs of advanced design on a printed-circuit board in a mounting frame with a power/control connector. The LED panels are controlled by an LED control module that contains an AC-to-DC power supply, a control board, and 8 LED-panel driver boards. In prior LED panels, the LEDs are packaged at less than maximum areal densities in bulky metal housings that reduce effective active areas. In contrast, in the present LED panels, the LEDs are packed at maximum areal density so as to afford 100-percent active area and so that when panels are joined side by side to form the array, there are no visible seams between them and the proportion of active area is still 100 percent. Each panel produces an illuminance of .5 x 10( exp 4) lux at a distance of 5.8 in. (approx.1.6 cm). The LEDs are driven according to a pulse-width-modulation control scheme that makes it safe to drive the LEDs beyond their rated steady-state currents in order to generate additional light during short periods. The drive current and the pulse-width modulation for each LED panel can be controlled independently of those of the other 15 panels. The maximum allowable duration of each pulse of drive current is a function of the amount of overdrive, the total time to be spent in overdrive operation, and the limitations

  17. Cross software for microprocessor program development at CERN

    CERN Document Server

    Von Eicken, H; Montuelle, J; Willers, I

    1981-01-01

    Programs for a variety of microprocessors (including Intel 8080; Motorola 6800, 6809 and 68000; and Texas Instruments 9900) can be prepared on different host computers (such as IBM 370, CDC 6000, and Nord 10) using portable programs developed at CERN. The range of cross software consists of: an assembler for each target microprocessor, a single linkage editor, a single object module librarian, and a variety of pre-loaders which convert object modules from CERN's format (CUFOM) into manufacturers' formats. The programs are written in BCPL and PASCAL, programming languages which are available on a wide range of computers.

  18. RlSC & DSP Advanced Microprocessor System Design; Sample Projects, Fall 1991

    OpenAIRE

    Fredine, John E.; Goeckel, Dennis L.; Meyer, David G.; Sailer, Stuart E.; Schmottlach, Glenn E.

    1992-01-01

    RlSC & DSP Microprocessor System Design (EE 595M) provides students with an overview of reduced instruction set (RISC) microprocessors and digital signal processing (DSP) microprocessors, with emphasis on incorporating these devices in general purpose and embedded system designs, respectively. The first half of the course emphasizes design considerations for RlSC microprocessor based computer systems; a half-semester design project focuses on design principles that could be utilized in a gene...

  19. Radiation hardened microprocessor for small payloads

    Science.gov (United States)

    Shah, Ravi

    1993-01-01

    The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

  20. Decimal Integer Multiplication based on Molecular Beacons

    Directory of Open Access Journals (Sweden)

    Jing Wang

    2013-12-01

    Full Text Available Due to the enhancement of circuit integration level, and the accelerating of working frequency of traditional computer, it requires components dimension must be constantly decreased. So encapsulation, etching and other problems of chip are becoming more and more difficult to solve, which causes its performance also become unstable. In order to overcome this problem, DNA computing as a new kind of molecular computing mode, with its high parallelism, huge amounts of storage capacity, low energy consumption advantages has received extensive attention. Being the same with traditional electronic computer, DNA computer is composed by arithmetic operations such as addition, subtraction, multiplication and dividing and basic logic units such as AND, OR, NON gate. This paper puts forward a new method to realize decimal integer multiplication based on molecular beacons. The algorithm firstly converts decimal integer to binary number, and then resolves the multiplication process into multiplication of current bit and addition of intermediate result after shifting two steps. Molecular beacon is used as multiplying unit, coding sequence is used as multiplier in this method. Based on the working principle of molecular beacon, multiplication operation of two one-bit binary is simulated. And by recording fluorescence status of molecular beacon to observe intermediate result and carry-bit situation, the final result can be obtained through addition after shifting. Examples prove that this method can realize decimal integer multiplication rapidly and accurately. This method is similar to multiplication system in traditional electronic computer, and it provides a simple, easier operation method for DNA computer to realize arithmetic operation.

  1. Microprocessors in U.S. Electrical Engineering Departments, 1974-1975.

    Science.gov (United States)

    Sloan, M. E.

    Drawn from a survey of engineering departments known to be teaching microprocessor courses, this paper shows that the adoption of microprocessors by Electrical Engineering Departments has been rapid compared with their adoption of minicomputers. The types of courses that are being taught can be categorized as: surveys of microprocessors, intensive…

  2. Integer Set Compression and Statistical Modeling

    DEFF Research Database (Denmark)

    Larsson, N. Jesper

    2014-01-01

    Compression of integer sets and sequences has been extensively studied for settings where elements follow a uniform probability distribution. In addition, methods exist that exploit clustering of elements in order to achieve higher compression performance. In this work, we address the case where...... enumeration of elements may be arbitrary or random, but where statistics is kept in order to estimate probabilities of elements. We present a recursive subset-size encoding method that is able to benefit from statistics, explore the effects of permuting the enumeration order based on element probabilities...

  3. Division Unit for Binary Integer Decimals

    DEFF Research Database (Denmark)

    Lang, Tomas; Nannarelli, Alberto

    2009-01-01

    -recurrence algorithm to BID representation and implement the division unit in standard cell technology. The implementation of the proposed BID division unit is compared to that of a BCD based unit implementing the same algorithm. The comparison shows that for normalized operands the BID unit has the same latency......In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm and implements binary encodings (binary integer decimal or BID) for significands. Recent decimal division designs are all based on the binary coded decimal (BCD) encoding. We adapt the radix-10 digit...

  4. Variable-thermoinsulation garments with a microprocessor temperature controller.

    Science.gov (United States)

    Kurczewska, Agnieszka; Leánikowski, Jacek

    2008-01-01

    This paper presents the concept of active variable thermoinsulation clothing for users working in low temperatures. Those garments contain heating inserts regulated by a microprocessor temperature controller. This paper also presents the results of tests carried out on the newly designed garments.

  5. Advanced Electricity. Microprocessors and Robotics. Curriculum Development. Bulletin 1803.

    Science.gov (United States)

    Southeastern Louisiana Univ., Hammond.

    This model instructional unit was developed to aid industrial arts/technology education teachers in Louisiana to teach a course on microprocessors and robotics in grades 11 and 12. It provides guidance on model performance objectives, current technology content, sources, and supplemental materials. Following a course description, rationale, and…

  6. Analysis of inadvertent microprocessor lag time on eddy covariance results

    Science.gov (United States)

    Karl Zeller; Gary Zimmerman; Ted Hehn; Evgeny Donev; Diane Denny; Jeff Welker

    2001-01-01

    Researchers using the eddy covariance approach to measuring trace gas fluxes are often hoping to measure carbon dioxide and energy fluxes for ecosystem intercomparisons. This paper demonstrates a systematic microprocessor- caused lag of 20.1 to 20.2 s in a commercial sonic anemometer-analog-to-digital datapacker system operated at 10 Hz. The result of the inadvertent...

  7. Microprocessor-Based Neural-Pulse-Wave Analyzer

    Science.gov (United States)

    Kojima, G. K.; Bracchi, F.

    1983-01-01

    Microprocessor-based system analyzes amplitudes and rise times of neural waveforms. Displaying histograms of measured parameters helps researchers determine how many nerves contribute to signal and specify waveform characteristics of each. Results are improved noise rejection, full or partial separation of overlapping peaks, and isolation and identification of related peaks in different histograms. 2

  8. Small private key MQPKS on an embedded microprocessor.

    Science.gov (United States)

    Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

    2014-03-19

    Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

  9. Design and implementation of a microprocessor based room ...

    African Journals Online (AJOL)

    Log in or Register to get access to full text downloads. ... At the heart of this system is an Intel 8085 microprocessor which controls all operations of the system. ... efficiency in the use of electrical energy and reduces the cost of electricity.

  10. Horizontal visibility graphs from integer sequences

    Science.gov (United States)

    Lacasa, Lucas

    2016-09-01

    The horizontal visibility graph (HVG) is a graph-theoretical representation of a time series and builds a bridge between dynamical systems and graph theory. In recent years this representation has been used to describe and theoretically compare different types of dynamics and has been applied to characterize empirical signals, by extracting topological features from the associated HVGs which have shown to be informative on the class of dynamics. Among some other measures, it has been shown that the degree distribution of these graphs is a very informative feature that encapsulates nontrivial information of the series's generative dynamics. In particular, the HVG associated to a bi-infinite real-valued series of independent and identically distributed random variables is a universal exponential law P(k)=(1/3){(2/3)}k-2, independent of the series marginal distribution. Most of the current applications have however only addressed real-valued time series, as no exact results are known for the topological properties of HVGs associated to integer-valued series. In this paper we explore this latter situation and address univariate time series where each variable can only take a finite number n of consecutive integer values. We are able to construct an explicit formula for the parametric degree distribution {P}n(k), which we prove to converge to the continuous case for large n and deviates otherwise. A few applications are then considered.

  11. Network interdiction and stochastic integer programming

    CERN Document Server

    2003-01-01

    On March 15, 2002 we held a workshop on network interdiction and the more general problem of stochastic mixed integer programming at the University of California, Davis. Jesús De Loera and I co-chaired the event, which included presentations of on-going research and discussion. At the workshop, we decided to produce a volume of timely work on the topics. This volume is the result. Each chapter represents state-of-the-art research and all of them were refereed by leading investigators in the respective fields. Problems - sociated with protecting and attacking computer, transportation, and social networks gain importance as the world becomes more dep- dent on interconnected systems. Optimization models that address the stochastic nature of these problems are an important part of the research agenda. This work relies on recent efforts to provide methods for - dressing stochastic mixed integer programs. The book is organized with interdiction papers first and the stochastic programming papers in the second part....

  12. An experiment on Lowest Unique Integer Games

    Science.gov (United States)

    Yamada, Takashi; Hanaki, Nobuyuki

    2016-12-01

    We experimentally study Lowest Unique Integer Games (LUIGs) to determine if and how subjects self-organize into different behavioral classes. In a LUIG, N(≥ 3) players submit a positive integer up to M and the player choosing the smallest number not chosen by anyone else wins. LUIGs are simplified versions of real systems such as Lowest/Highest Unique Bid Auctions that have been attracting attention from scholars, yet experimental studies are scarce. Furthermore, LUIGs offer insights into choice patterns that can shed light on the alleviation of congestion problems. Here, we consider four LUIGs with N = { 3 , 4 } and M = { 3 , 4 } . We find that (a) choices made by more than 1/3 of subjects were not significantly different from what a symmetric mixed-strategy Nash equilibrium (MSE) predicts; however, (b) subjects who behaved significantly differently from what the MSE predicts won the game more frequently. What distinguishes subjects was their tendencies to change their choices following losses.

  13. Prime labeling of families of trees with Gaussian integers

    Directory of Open Access Journals (Sweden)

    Steven Klee

    2016-08-01

    Full Text Available A graph on n vertices is said to admit a prime labeling if we can label its vertices with the first n natural numbers such that any two adjacent vertices have relatively prime labels. Here we extend the idea of prime labeling to the Gaussian integers, which are the complex numbers whose real and imaginary parts are both integers. We begin by defining an order on the Gaussian integers that lie in the first quadrant. Using this ordering, we show that several families of trees admit a prime labeling with the Gaussian integers.

  14. On Secure Two-Party Integer Division

    DEFF Research Database (Denmark)

    Dahl, Morten; Ning, Chao; Toft, Tomas

    2012-01-01

    We consider the problem of secure integer division: given two Paillier encryptions of ℓ-bit values n and d, determine an encryption of $\\lfloor \\frac{n}{d}\\rfloor$ without leaking any information about n or d. We propose two new protocols solving this problem. The first requires $\\ensuremath......{\\mathcal{O}}(\\ell)$ arithmetic operations on encrypted values (secure addition and multiplication) in $\\ensuremath{\\mathcal{O}}(1)$ rounds. This is the most efficient constant-rounds solution to date. The second protocol requires only $\\ensuremath{\\mathcal{O}} \\left( (\\log^2 \\ell)(\\kappa + \\operatorname{loglog} \\ell) \\right......)$ arithmetic operations in $\\ensuremath{\\mathcal{O}}(\\log^2 \\ell)$ rounds, where κ is a correctness parameter. Theoretically, this is the most efficient solution to date as all previous solutions have required Ω(ℓ) operations. Indeed, the fact that an o(ℓ) solution is possible at all is highly surprising....

  15. Bivium as a Mixed Integer Programming Problem

    DEFF Research Database (Denmark)

    Borghoff, Julia; Knudsen, Lars Ramkilde; Stolpe, Mathias

    2009-01-01

    Trivium is a stream cipher proposed for the eSTREAM project. Raddum introduced some reduced versions of Trivium, named Bivium A and Bivium B. In this article we present a numerical attack on the Biviums. The main idea is to transform the problem of solving a sparse system of quadratic equations...... over $GF(2)$ into a combinatorial optimization problem. We convert the Boolean equation system into an equation system over $\\mathbb{R}$ and formulate the problem of finding a $0$-$1$-valued solution for the system as a mixed-integer programming problem. This enables us to make use of several...... algorithms in the field of combinatorial optimization in order to find a solution for the problem and recover the initial state of Bivium. In particular this gives us an attack on Bivium B in estimated time complexity of $2^{63.7}$ seconds. But this kind of attack is also applicable to other cryptographic...

  16. Statistical Mechanical Models of Integer Factorization Problem

    Science.gov (United States)

    Nakajima, Chihiro H.; Ohzeki, Masayuki

    2017-01-01

    We formulate the integer factorization problem via a formulation of the searching problem for the ground state of a statistical mechanical Hamiltonian. The first passage time required to find a correct divisor of a composite number signifies the exponential computational hardness. The analysis of the density of states of two macroscopic quantities, i.e., the energy and the Hamming distance from the correct solutions, leads to the conclusion that the ground state (correct solution) is completely isolated from the other low-energy states, with the distance being proportional to the system size. In addition, the profile of the microcanonical entropy of the model has two peculiar features that are each related to two marked changes in the energy region sampled via Monte Carlo simulation or simulated annealing. Hence, we find a peculiar first-order phase transition in our model.

  17. Ensemble segmentation using efficient integer linear programming.

    Science.gov (United States)

    Alush, Amir; Goldberger, Jacob

    2012-10-01

    We present a method for combining several segmentations of an image into a single one that in some sense is the average segmentation in order to achieve a more reliable and accurate segmentation result. The goal is to find a point in the "space of segmentations" which is close to all the individual segmentations. We present an algorithm for segmentation averaging. The image is first oversegmented into superpixels. Next, each segmentation is projected onto the superpixel map. An instance of the EM algorithm combined with integer linear programming is applied on the set of binary merging decisions of neighboring superpixels to obtain the average segmentation. Apart from segmentation averaging, the algorithm also reports the reliability of each segmentation. The performance of the proposed algorithm is demonstrated on manually annotated images from the Berkeley segmentation data set and on the results of automatic segmentation algorithms.

  18. Superposition of two optical vortices with opposite integer or non-integer orbital angular momentum

    Directory of Open Access Journals (Sweden)

    Carlos Fernando Díaz Meza

    2016-04-01

    Full Text Available This work develops a brief proposal to achieve the superposition of two opposite vortex beams, both with integer or non-integer mean value of the orbital angular momentum. The first part is about the generation of this kind of spatial light distributions through a modified Brown and Lohmann’s hologram. The inclusion of a simple mathematical expression into the pixelated grid’s transmittance function, based in Fourier domain properties, shifts the diffraction orders counterclockwise and clockwise to the same point and allows the addition of different modes. The strategy is theoretically and experimentally validated for the case of two opposite rotation helical wavefronts.

  19. Garbage-free reversible constant multipliers for arbitrary integers

    DEFF Research Database (Denmark)

    Mogensen, Torben Ægidius

    2013-01-01

    We present a method for constructing reversible circuitry for multiplying integers by arbitrary integer constants. The method is based on Mealy machines and gives circuits whose size are (in the worst case) linear in the size of the constant. This makes the method unsuitable for large constants......, but gives quite compact circuits for small constants. The circuits use no garbage or ancillary lines....

  20. On the Relationship between Integer Lifting and Rounding Transform

    Directory of Open Access Journals (Sweden)

    R. Vargic

    2007-12-01

    Full Text Available In this paper we analyze the relationship between integer Lifting scheme and Rounding transform as means to compute the wavelet transform in signal processing area. We bring some new results which better describe relationship, reversibility and equivalence of integer lifting scheme and rounding transform concept.

  1. A Paper-and-Pencil gcd Algorithm for Gaussian Integers

    Science.gov (United States)

    Szabo, Sandor

    2005-01-01

    As with natural numbers, a greatest common divisor of two Gaussian (complex) integers "a" and "b" is a Gaussian integer "d" that is a common divisor of both "a" and "b". This article explores an algorithm for such gcds that is easy to do by hand.

  2. Discrete Dirac equation on a finite half-integer lattice

    Science.gov (United States)

    Smalley, L. L.

    1986-01-01

    The formulation of the Dirac equation on a discrete lattice with half-integer spacing and periodic boundary conditions is investigated analytically. The importance of lattice formulations for problems in field theory and quantum mechanics is explained; the concept of half-integer Fourier representation is introduced; the discrete Dirac equation for the two-dimensional case is derived; dispersion relations for the four-dimensional case are developed; and the spinor formulation for the Dirac fields on the half-integer lattice and the discrete time variable for the four-dimensional time-dependent Dirac equation are obtained. It is argued that the half-integer lattice, because it takes the Dirac Lagrangian into account, is more than a mere relabeling of the integer lattice and may have fundamental physical meaning (e.g., for the statistics of fermions). It is noted that the present formulation does not lead to species doubling, except in the continuum limit.

  3. Design and Implementation of O/C relay using Microprocessor

    Directory of Open Access Journals (Sweden)

    Dr.Abdul-Sattar H. Jasim

    2012-03-01

    Full Text Available This work presents the design and implementation of a versatile digital overcurrent (O/C relay using a single microprocessor. The relay is implemented by a combination of a look-up table and a counter. The software development and hardware testing are done using a microcomputer module based on a 8-bit microprocessor. The digital processing of measured currents enables a separate setting of operating values selection of all types of inverse or constant time characteristics overcurrent protection. This protection provides reasonably fast tripping, even at terminal close to the power source were the most serve faults can occur excluding the transient condition. So this method has an excellent compromise between accuracy hardware and speed

  4. Innovative architectures for dense multi-microprocessor computers

    Science.gov (United States)

    Larson, Robert E.

    1989-01-01

    The purpose is to summarize a Phase 1 SBIR project performed for the NASA/Langley Computational Structural Mechanics Group. The project was performed from February to August 1987. The main objectives of the project were to: (1) expand upon previous research into the application of chordal ring architectures to the general problem of designing multi-microcomputer architectures, (2) attempt to identify a family of chordal rings such that each chordal ring can be simply expanded to produce the next member of the family, (3) perform a preliminary, high-level design of an expandable multi-microprocessor computer based upon chordal rings, (4) analyze the potential use of chordal ring based multi-microprocessors for sparse matrix problems and other applications arising in computational structural mechanics.

  5. Algorithms for Temperature-Aware Task Scheduling in Microprocessor Systems

    CERN Document Server

    Chrobak, Marek; Hurand, Mathilde; Robert, Julien

    2008-01-01

    We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems. We focus on s...

  6. Real-time fetal ECG system design using embedded microprocessors

    Science.gov (United States)

    Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

    2016-05-01

    The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

  7. A microprocessor-based multichannel subsensory stochastic resonance electrical stimulator.

    Science.gov (United States)

    Chang, Gwo-Ching

    2013-01-01

    Stochastic resonance electrical stimulation is a novel intervention which provides potential benefits for improving postural control ability in the elderly, those with diabetic neuropathy, and stroke patients. In this paper, a microprocessor-based subsensory white noise electrical stimulator for the applications of stochastic resonance stimulation is developed. The proposed stimulator provides four independent programmable stimulation channels with constant-current output, possesses linear voltage-to-current relationship, and has two types of stimulation modes, pulse amplitude and width modulation.

  8. Achieving High Performance on the i860 Microprocessor

    Science.gov (United States)

    Lee, King; Kutler, Paul (Technical Monitor)

    1998-01-01

    The i860 is a high performance microprocessor used in the Intel Touchstone project. This paper proposes a paradigm for programming the i860 that is modelled on the vector instructions of the Cray computers. Fortran callable assembler subroutines were written that mimic the concurrent vector instructions of the Cray. Cache takes the place of vector registers. Using this paradigm we have achieved twice the performance of compiled code on a traditional solve.

  9. A Microprocessor-Based System for Monitoring Gas Turbines

    Directory of Open Access Journals (Sweden)

    P. K.S. Shrivastava

    1989-04-01

    Full Text Available The development and testing of hardware and software for a microprocessor-based monitoring system for gas turbines is described in this paper. The operators of gas turbines can be trained to monitor running hours, slip between high and low pressure compressor spools and torque on the reduction gear-box under various conditions ofoperation. The system will replace the traditional method of monitoring these parameters which are more time consuming and error prone.

  10. Microprocessor activity controls differential miRNA biogenesis In Vivo.

    Science.gov (United States)

    Conrad, Thomas; Marsico, Annalisa; Gehre, Maja; Orom, Ulf Andersson

    2014-10-23

    In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression.

  11. G-cueing microcontroller (a microprocessor application in simulators)

    Science.gov (United States)

    Horattas, C. G.

    1980-01-01

    A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

  12. Feasibility analysis and design of a fault tolerant computing system: a TMR microprocessor system design of 64-Bit COTS microprocessors

    OpenAIRE

    Eken, Huseyin Baha

    2001-01-01

    The purpose of this thesis is to analyze and determine the feasibility of implementing a fault tolerant computing system that is able to function in the presence of radiation induced Single Event Upsets (SEU) by using the Triple Modular Redundancy (TMR) technique with 64-bit Commercial-Off-The- Shelf (COTS) microprocessors. Due to the radiation environment in space, electronic devices must be designed to tolerate the radiation effects. While there are radiation-hardened devices that can toler...

  13. Integer lattice dynamics for Vlasov-Poisson

    Science.gov (United States)

    Mocz, Philip; Succi, Sauro

    2017-03-01

    We revisit the integer lattice (IL) method to numerically solve the Vlasov-Poisson equations, and show that a slight variant of the method is a very easy, viable, and efficient numerical approach to study the dynamics of self-gravitating, collisionless systems. The distribution function lives in a discretized lattice phase-space, and each time-step in the simulation corresponds to a simple permutation of the lattice sites. Hence, the method is Lagrangian, conservative, and fully time-reversible. IL complements other existing methods, such as N-body/particle mesh (computationally efficient, but affected by Monte Carlo sampling noise and two-body relaxation) and finite volume (FV) direct integration schemes (expensive, accurate but diffusive). We also present improvements to the FV scheme, using a moving-mesh approach inspired by IL, to reduce numerical diffusion and the time-step criterion. Being a direct integration scheme like FV, IL is memory limited (memory requirement for a full 3D problem scales as N6, where N is the resolution per linear phase-space dimension). However, we describe a new technique for achieving N4 scaling. The method offers promise for investigating the full 6D phase-space of collisionless systems of stars and dark matter.

  14. Integer Lattice Dynamics for Vlasov-Poisson

    CERN Document Server

    Mocz, Philip

    2016-01-01

    We revisit the integer lattice (IL) method to numerically solve the Vlasov-Poisson equations, and show that a slight variant of the method is a very easy, viable, and efficient numerical approach to study the dynamics of self-gravitating, collisionless systems. The distribution function lives in a discretized lattice phase-space, and each time-step in the simulation corresponds to a simple permutation of the lattice sites. Hence, the method is Lagrangian, conservative, and fully time-reversible. IL complements other existing methods, such as N-body/particle mesh (computationally efficient, but affected by Monte-Carlo sampling noise and two-body relaxation) and finite volume (FV) direct integration schemes (expensive, accurate but diffusive). We also present improvements to the FV scheme, using a moving mesh approach inspired by IL, to reduce numerical diffusion and the time-step criterion. Being a direct integration scheme like FV, IL is memory limited (memory requirement for a full 3D problem scales as N^6, ...

  15. The integer quantum hall effect revisited

    Energy Technology Data Exchange (ETDEWEB)

    Michalakis, Spyridon [Los Alamos National Laboratory; Hastings, Matthew [Q STATION, CALIFORNIA

    2009-01-01

    For T - L x L a finite subset of Z{sup 2}, let H{sub o} denote a Hamiltonian on T with periodic boundary conditions and finite range, finite strength intetactions and a unique ground state with a nonvanishing spectral gap. For S {element_of} T, let q{sub s} denote the charge at site s and assume that the total charge Q = {Sigma}{sub s {element_of} T} q{sub s} is conserved. Using the local charge operators q{sub s}, we introduce a boundary magnetic flux in the horizontal and vertical direction and allow the ground state to evolve quasiadiabatically around a square of size one magnetic flux, in flux space. At the end of the evolution we obtain a trivial Berry phase, which we compare, via a method reminiscent of Stokes Theorem. to the Berry phase obtained from an evolution around an exponentially small loop near the origin. As a result, we show, without any averaging assumption, that the Hall conductance is quantized in integer multiples of e{sup 2}/h up to exponentially small corrections of order e{sup -L/{zeta}}, where {zeta}, is a correlation length that depends only on the gap and the range and strength of the interactions.

  16. Diversity and non-integer differentiation for system dynamics

    CERN Document Server

    Oustaloup, Alain

    2014-01-01

    Based on a structured approach to diversity, notably inspired by various forms of diversity of natural origins, Diversity and Non-integer Derivation Applied to System Dynamics provides a study framework to the introduction of the non-integer derivative as a modeling tool. Modeling tools that highlight unsuspected dynamical performances (notably damping performances) in an ""integer"" approach of mechanics and automation are also included. Written to enable a two-tier reading, this is an essential resource for scientists, researchers, and industrial engineers interested in this subject area. Ta

  17. Generalization of a few results in Integer Partitions

    CERN Document Server

    Dastidar, Manosij Ghosh

    2011-01-01

    In this paper, we generalize a few important results in Integer Partitions; namely the results known as Stanley's theorem and Elder's theorem, and the congruence results proposed by Ramanujan for the partition function. We generalize the results of Stanley and Elder from a fixed integer to an array of subsequent integers, and propose an analogue of Ramanujan's congruence relations for the `number of parts' function instead of the partition function. We also deduce the generating function for the `number of parts', and relate the technical results with their graphical interpretations through a novel use of the Ferrer's diagrams.

  18. Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

    Science.gov (United States)

    Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

    1994-01-01

    A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

  19. Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor

    Science.gov (United States)

    2015-03-10

    for Public Release; Distribution Unlimited Final Report: Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor The views...Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor Report Title The major objective of the project was to design and demonstrate operation...25, no.3, pp.1-8, June 2015. Technology Transfer Final Report: Design and Demonstration of a 30 GHz 16‐bit Superconductor RSFQ Microprocessor

  20. HARDWARE COMPLEXITY OF MICROPROCESSOR DESIGN ACCORDING TO MOORE’S LAW

    Directory of Open Access Journals (Sweden)

    Haissam El-Aawar

    2014-07-01

    Full Text Available The increasing of the number of transistors on a chip, which plays the main role in improvement in the performance and increasing the speed of a microprocessor, causes rapidly increasing of microprocessor design complexity. Based on Moore’s Law the number of transistors should be doubled every 24 months. The doubling of transistor count affects increasing of microprocessor design complexity, power dissipation, and cost of design effort. This article presents a proposal to discuss the matter of scaling hardware complexity of a microprocessor design related to Moore’s Law. Based on the discussion a hardware complexity measure is presented.

  1. Introduction to 6800/6802 microprocessor systems hardware, software and experimentation

    CERN Document Server

    Simpson, Robert J

    1987-01-01

    Introduction to 6800/6802 Microprocessor Systems: Hardware, Software and Experimentation introduces the reader to the features, characteristics, operation, and applications of the 6800/6802 microprocessor and associated family of devices. Many worked examples are included to illustrate the theoretical and practical aspects of the 6800/6802 microprocessor.Comprised of six chapters, this book begins by presenting several aspects of digital systems before introducing the concepts of fetching and execution of a microprocessor instruction. Details and descriptions of hardware elements (MPU, RAM, RO

  2. Compiler for Fast, Accurate Mathematical Computing on Integer Processors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposers will develop a computer language compiler to enable inexpensive, low-power, integer-only processors to carry our mathematically-intensive comptutations...

  3. Mixed-integer vertex covers on bipartite graphs

    NARCIS (Netherlands)

    Gerards, A.M.H.; Conforti, M.; Zambelli, G.; Fischetti, M.; Williamson, D.P.

    2007-01-01

    Let $A$ be the edge-node incidence matrix of a bipartite graph $G = (U, V ; E)$, $I$ be a subset of the nodes of $G$, and $b$ be a vector such that $2b$ is integral. We consider the following mixed-integer set: $X(G, b, I) = {x : Ax ≥ b, x ≥ 0, x_i$ integer for all $i ∈ I}$

  4. Short Rational Generating Functions For Multiobjective Linear Integer Programming

    CERN Document Server

    Blanco, Victor

    2007-01-01

    This paper presents an algorithm for solving multiobjective integer programming problems. The algorithm uses Barvinok's rational functions of the polytope that defines the feasible region and provides as output the entire set of nondominated solutions for the problem. Theoretical complexity results on the algorithm are provided in the paper and an implementation of the algorithm shows that it is useful for solving multiobjective integer linear programs.

  5. AN ALGORITHM FOR FINDING GLOBAL MINIMUM OF NONLINEAR INTEGER PROGRAMMING

    Institute of Scientific and Technical Information of China (English)

    Wei-wenTian; Lian-shengZhang

    2004-01-01

    A filled function is proposed by R.Ge[2] for finding a global minimizer of a function of several continuous variables. In [4], an approach for finding a global integer minimizer of nonlinear flmction using the above filled function is given. Meanwhile a major obstacle is met: if ρ > 0 is small, and ‖xI- xI* is large, where xI - an integer point, xI* - a current local integer minimizer, then the value of the filled function almost equals zero. Thus it is difficult to recognize the size of the value of the filled flmction and can not to find the global integer minimizer of nonlinear function. In this paper, two new filled functions are proposed for finding global integer minimizer of nonlinear flmction, the new filled function improves some properties of the filled function proposed by R. Ge [2]. Some numerical results are given, which indicate the new filled function (4.1) to find global integer minimizer of nonlinear function is efficient.

  6. Single-chip microprocessor that communicates directly using light.

    Science.gov (United States)

    Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

    2015-12-24

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  7. Designs and performance of microprocessor-controlled knee joints.

    Science.gov (United States)

    Thiele, Julius; Westebbe, Bettina; Bellmann, Malte; Kraft, Marc

    2014-02-01

    In this comparative study, three transfemoral amputee subjects were fitted with four different microprocessor-controlled exoprosthetic knee joints (MPK): C-Leg, Orion, Plié2.0, and Rel-K. In a motion analysis laboratory, objective gait measures were acquired during level walking at different velocities. Subsequent technical analyses, which involved X-ray computed tomography, identified the functional mechanisms of each device and enabled corroboration of the performance in the gait laboratory by the engineering design of the MPK. Gait measures showed that the mean increase of the maximum knee flexion angle at different walking velocities was closest in value to the unaffected contralateral knee (6.2°/m/s) with C-Leg (3.5°/m/s; Rel-K 17.0°/m/s, Orion 18.3°/m/s, and Plié2.0 28.1°/m/s). Technical analyses corroborated that only with Plié2.0 the flexion resistances were not regulated by microprocessor control at different walking velocities. The muscular effort for the initiation of the swing phase, measured by the minimum hip moment, was found to be lowest with C-Leg (-82.1±14.1 Nm; Rel-K -83.59±17.8 Nm, Orion -88.0±16.3 Nm, and Plié2.0 -91.6±16.5 Nm). Reaching the extension stop at the end of swing phase was reliably executed with both Plié2.0 and C-Leg. Abrupt terminal stance phase extension observed with Plié2.0 and Rel-K could be attributed to the absence of microprocessor control of extension resistance.

  8. Single-chip microprocessor that communicates directly using light

    Science.gov (United States)

    Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

    2015-12-01

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  9. Microprocessor Controller in Closed Loop Angular Position Servo System P.

    Directory of Open Access Journals (Sweden)

    P. B. Deshpande

    1989-07-01

    Full Text Available Integrated command, control and copmunication systems are based on the use of computers for digital data processing. The weapon system platforms like missile launchers are given input command for accurate and quick positioning in azimuth and elevation. The technologies of sensors, signal conditioning and associated solid state electronics have moved from analog to digital. Therefore, a position controller has to be designed around a microprocessor in embedded form for usage in such servo control systems. This paper highlights the basic approach for such design and problems which need to be tackled during actual implementation.

  10. On the Floating Point Performance of the i860 Microprocessor

    Science.gov (United States)

    Lee, King; Kutler, Paul (Technical Monitor)

    1997-01-01

    The i860 microprocessor is a pipelined processor that can deliver two double precision floating point results every clock. It is being used in the Touchstone project to develop a teraflop computer by the year 2000. With such high computational capabilities it was expected that memory bandwidth would limit performance on many kernels. Measured performance of three kernels showed performance is less than what memory bandwidth limitations would predict. This paper develops a model that explains the discrepancy in terms of memory latencies and points to some problems involved in moving data from memory to the arithmetic pipelines.

  11. Distributed Micro-Processor Applications to Guidance and Control Systems.

    Science.gov (United States)

    1982-07-01

    Microprocessor Technology have provided helpful discussion, background material, and comments . Mr. Louis J. Urban, USAF, WG 06 Chairman, provided a summary...0.25 &a UJVS1tN P155) I$ addeU* S odrf 16 isdae 16 Ime S eewi~lewd S* Sdeta wedee~. IES dets dd a蚍 m a 0 frsno m no Vol D ova *EMULATES 8085 HAS Z-80...plane of the paper causes a deflection of the cantilever beams proportional to the applied acceleration. A DC voltage output proportional to

  12. Microprocessor implementation of an FFT for ionospheric VLF observations

    Science.gov (United States)

    Elvidge, J.; Kintner, P.; Holzworth, R.

    1984-01-01

    A fast Fourier transform algorithm is implemented on a CMOS microprocessor for application to very low-frequency electric fields (less than 10 kHz) sensed on high-altitude scientific balloons. Two FFT's are calculated simultaneously by associating them with conjugate symmetric and conjugate antisymmetric results. One goal of the system was to detect spectral signatures associated with fast time variations present in natural signals such as whistlers and chorus. Although a full evaluation of the system was not possible for operational reasons, a measure of the system's success has been defined and evaluated.

  13. Microprocessor-controlled laser tracker for atmospheric sensing

    Science.gov (United States)

    Johnson, R. A.; Webster, C. R.; Menzies, R. T.

    1985-01-01

    An optical tracking system comprising a visible HeNe laser, an imaging detector, and a microprocessor-controlled mirror, has been designed to track a moving retroreflector located up to 500 m away from an atmospheric instrument and simultaneously direct spectrally tunable infrared laser radiation to the retroreflector for double-ended, long-path absorption measurements of atmospheric species. The tracker has been tested during the recent flight of a balloon-borne tunable diode laser absorption spectrometer which monitors the concentrations of stratospheric species within a volume defined by a 0.14-m-diameter retroreflector lowered 500 m below the instrument gondola.

  14. Practical design of digital circuits basic logic to microprocessors

    CERN Document Server

    Kampel, Ian

    1983-01-01

    Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

  15. A family of compatible single- and multimicroprocessor systems with 8-bit and 16-bit Microprocessors

    Energy Technology Data Exchange (ETDEWEB)

    Brzezinski, J.; Cellary, W.; Kreglewski, J.

    1984-10-01

    In the paper, a multimicroprocessor system for 8-bit and 16-bit microprocessors is presented. The main assumptions of the project of the presented system are discussed. Different single- and multimicroprocessor structures with 8-bit microprocessors are outlined. A detailed description of two single-board microcomputers and system aspects of different solutions are presented. Finally, an intelligent floppy disk controller is described.

  16. COED Transactions, Vol. IX, No. 6, June 1977. An Introductory Course in Microprocessors and Microcomputers.

    Science.gov (United States)

    Marcovitz, Alan B., Ed.

    This paper describes an introductory course in microprocessors and microcomputers implemented at Grossmont College. The current state-of-the-art in the microprocessor field is discussed, with special emphasis on the 8-bit MOS single-chip processors which are the most commonly used devices. Objectives and guidelines for the course are presented,…

  17. The Stand-Alone Microprocessor System: A Valuable Tool in College Admissions and Recruitment.

    Science.gov (United States)

    Garrett, Larry Neal

    1983-01-01

    The stand-alone microprocessor is seen as one innovative tool that can be used both in the organizational management of decline and in meeting specific organizational needs such as those of the admissions director and staff. The term "microprocessor" is defined. (MLW)

  18. Minimizing the Integer Ambiguity Search Space for RTK

    Institute of Scientific and Technical Information of China (English)

    Yang Yun-chun; R. R. Hatch; R. T. Sharpe

    2003-01-01

    Differential GPS carrier phase measurements have much lower noise and multipath error than that of pseudorange measurements.The result is centimeter accuracy for Real-Time Kinematic (RTK).However, the measurement of the carrier phase has a constant unknown integer ambiguity. Several technical issues are related to solving the integer ambiguity correctly. They are: proper stochastic model, search space definition and initialization, search space reduction, state and standard deviation calculation, validation and rejection criteria for the unique and correct candidate. Search space reduction is critically important. It not only affects the ambiguity resolution speed, but also defines the ambiguity resolution success rate. The smaller the search space, the easier it is to find the unique and correct candidate set. The paper analyzes the integer ambiguity search space in its residual domain.The search space is minimized by: Analyzing the maximum independent integer ambiguity measurement set theoretically; Selecting the best initial measurement set that minimizes the search range of each satellite in the set and reduces the error effects from noise that may cause the wrong integer ambiguity solution for the remaining satellites not contained in the initial measurement set.Since the Residual Sensitive Matrix (S-Matrix) relates the integer ambiguity candidate set directly to post-fix residuals, it is not necessary to compute a fix for each candidate set thus making the integ erambiguity search process much more efficient. Also, minimizing the search space in the residual domain improves the search efficiency significantly and at the same time improves its reliability. Performance issues, such as recursive and weighted search techniques as well as methods for improving reliability, are also discussed in the article.

  19. Framework to Harvest Waste Heat from Microprocessor using MEMS Thermoelectric Generator

    Directory of Open Access Journals (Sweden)

    Tai Zhi Ling

    2014-01-01

    Full Text Available The world primary energy consumption has been growing steadily. Therefore, there is a need to improve the overall energy application. There is a lack of investigation on harvesting waste heat from microprocessor as an alternative energy source. This study focuses on the framework required to harvest the energy from the microprocessor. Thermal profiling of the microprocessor integrated with an MEMS Thermoelectric Generator (TEG using shunt configuration is developed. Additionally, a non-uniform energy model is derived to estimate the amount of energy that can be harvested from the microprocessor in the shunt configuration. MATLAB simulation based on the thermal and energy model is presented with two types of heat spreader material, copper and pyrolytic graphite with ideal and non-ideal contacts. The advantages and their shortfalls with respect to the microprocessor heat dissipation and the effectiveness to generate a temperature gradient at the MEMS TEG are discussed.

  20. Fractal electrodynamics via non-integer dimensional space approach

    Energy Technology Data Exchange (ETDEWEB)

    Tarasov, Vasily E., E-mail: tarasov@theory.sinp.msu.ru

    2015-09-25

    Using the recently suggested vector calculus for non-integer dimensional space, we consider electrodynamics problems in isotropic case. This calculus allows us to describe fractal media in the framework of continuum models with non-integer dimensional space. We consider electric and magnetic fields of fractal media with charges and currents in the framework of continuum models with non-integer dimensional spaces. An application of the fractal Gauss's law, the fractal Ampere's circuital law, the fractal Poisson equation for electric potential, and equation for fractal stream of charges are suggested. Lorentz invariance and speed of light in fractal electrodynamics are discussed. An expression for effective refractive index of non-integer dimensional space is suggested. - Highlights: • Electrodynamics of fractal media is described by non-integer dimensional spaces. • Applications of the fractal Gauss's and Ampere's laws are suggested. • Fractal Poisson equation, equation for fractal stream of charges are considered.

  1. Non-integer expansion embedding techniques for reversible image watermarking

    Science.gov (United States)

    Xiang, Shijun; Wang, Yi

    2015-12-01

    This work aims at reducing the embedding distortion of prediction-error expansion (PE)-based reversible watermarking. In the classical PE embedding method proposed by Thodi and Rodriguez, the predicted value is rounded to integer number for integer prediction-error expansion (IPE) embedding. The rounding operation makes a constraint on a predictor's performance. In this paper, we propose a non-integer PE (NIPE) embedding approach, which can proceed non-integer prediction errors for embedding data into an audio or image file by only expanding integer element of a prediction error while keeping its fractional element unchanged. The advantage of the NIPE embedding technique is that the NIPE technique can really bring a predictor into full play by estimating a sample/pixel in a noncausal way in a single pass since there is no rounding operation. A new noncausal image prediction method to estimate a pixel with four immediate pixels in a single pass is included in the proposed scheme. The proposed noncausal image predictor can provide better performance than Sachnev et al.'s noncausal double-set prediction method (where data prediction in two passes brings a distortion problem due to the fact that half of the pixels were predicted with the watermarked pixels). In comparison with existing several state-of-the-art works, experimental results have shown that the NIPE technique with the new noncausal prediction strategy can reduce the embedding distortion for the same embedding payload.

  2. Multiplicity of Summands in the Random Partitions of an Integer

    Indian Academy of Sciences (India)

    Ghurumuruhan Ganesan

    2013-02-01

    In this paper, we prove a conjecture of Yakubovich regarding limit shapes of `slices’ of two-dimensional (2D) integer partitions and compositions of when the number of summands $m\\sim An^$ for some >0 and $ < \\frac{1}{2}$. We prove that the probability that there is a summand of multiplicity in any randomly chosen partition or composition of an integer goes to zero asymptotically with provided is larger than a critical value. As a corollary, we strengthen a result due to Erdös and Lehner (Duke Math. J. 8(1941) 335–345) that concerns the relation between the number of integer partitions and compositions when $=\\frac{1}{3}$.

  3. Integer Programming and m-irreducibility of numerical semigroups

    CERN Document Server

    Blanco, Víctor

    2011-01-01

    This paper addresses the problem of decomposing a numerical semigroup into m-irreducible numerical semigroups. The problem originally stated in algebraic terms is translated, introducing the so called Kunz-coordinates, to resolve a series of several discrete optimization problems. First, we prove that finding a minimal m-irreducible decomposition is equivalent to solve a multiobjective linear integer problem. Then, we restate that problem as the problem of finding all the optimal solutions of a finite number of single objective integer linear problems plus a set covering problem. Finally, we prove that there is a suitable transformation that reduces the original problem to find an optimal solution of a compact integer linear problem. This result ensures a polynomial time algorithm for each given multiplicity m. We have implemented the different algorithms and have performed some computational experiments to show the efficiency of our methodology.

  4. The lattice of integer flows of a regular matroid

    CERN Document Server

    Su, Yi

    2009-01-01

    For a finite multigraph G, let \\Lambda(G) denote the lattice of integer flows of G -- this is a finitely generated free abelian group with an integer-valued positive definite bilinear form. Bacher, de la Harpe, and Nagnibeda show that if G and H are 2-isomorphic graphs then \\Lambda(G) and \\Lambda(H) are isometric, and remark that they were unable to find a pair of nonisomorphic 3-connected graphs for which the corresponding lattices are isometric. We explain this by examining the lattice \\Lambda(M) of integer flows of any regular matroid M. Let M_\\bullet be the minor of M obtained by contracting all co-loops. We show that \\Lambda(M) and \\Lambda(N) are isometric if and only if M_\\bullet and N_\\bullet are isomorphic.

  5. The Quadratic Graver Cone, Quadratic Integer Minimization, and Extensions

    CERN Document Server

    Lee, Jon; Romanchuk, Lyubov; Weismantel, Robert

    2010-01-01

    We consider the nonlinear integer programming problem of minimizing a quadratic function over the integer points in variable dimension satisfying a system of linear inequalities. We show that when the Graver basis of the matrix defining the system is given, and the quadratic function lies in a suitable {\\em dual Graver cone}, the problem can be solved in polynomial time. We discuss the relation between this cone and the cone of positive semidefinite matrices, and show that none contains the other. So we can minimize in polynomial time some non-convex and some (including all separable) convex quadrics. We conclude by extending our results to efficient integer minimization of multivariate polynomial functions of arbitrary degree lying in suitable cones.

  6. FPGA Implementation of Optimal 3D-Integer DCT Structure for Video Compression.

    Science.gov (United States)

    Jacob, J Augustin; Kumar, N Senthil

    2015-01-01

    A novel optimal structure for implementing 3D-integer discrete cosine transform (DCT) is presented by analyzing various integer approximation methods. The integer set with reduced mean squared error (MSE) and high coding efficiency are considered for implementation in FPGA. The proposed method proves that the least resources are utilized for the integer set that has shorter bit values. Optimal 3D-integer DCT structure is determined by analyzing the MSE, power dissipation, coding efficiency, and hardware complexity of different integer sets. The experimental results reveal that direct method of computing the 3D-integer DCT using the integer set [10, 9, 6, 2, 3, 1, 1] performs better when compared to other integer sets in terms of resource utilization and power dissipation.

  7. Exploiting Symmetry in Integer Convex Optimization using Core Points

    CERN Document Server

    Herr, Katrin; Schürmann, Achill

    2012-01-01

    We consider convex programming problems with integrality constraints that are invariant under a linear symmetry group. We define a core point of such a symmetry group as an integral point for which the convex hull of its orbit does not contain integral points other than the orbit points themselves. These core points allow us to decompose symmetric integer convex programming problems. Especially for symmetric integer linear programs we describe two algorithms based on this decomposition. Using a characterization of core points for direct products of symmetric groups, we show that prototype implementations can compete with state-of-the art commercial solvers and solve an open MIPLIB problem.

  8. Integer Programming Model for Maximum Clique in Graph

    Institute of Scientific and Technical Information of China (English)

    YUAN Xi-bo; YANG You; ZENG Xin-hai

    2005-01-01

    The maximum clique or maximum independent set of graph is a classical problem in graph theory. Combined with Boolean algebra and integer programming, two integer programming models for maximum clique problem,which improve the old results were designed in this paper. Then, the programming model for maximum independent set is a corollary of the main results. These two models can be easily applied to computer algorithm and software, and suitable for graphs of any scale. Finally the models are presented as Lingo algorithms, verified and compared by several examples.

  9. A new heuristic algorithm for general integer linear programming problems

    Institute of Scientific and Technical Information of China (English)

    GAO Pei-wang; CAI Ying

    2006-01-01

    A new heuristic algorithm is proposed for solving general integer linear programming problems.In the algorithm,the objective function hyperplane is used as a cutting plane,and then by introducing a special set of assistant sets,an efficient heuristic search for the solution to the integer linear program is carried out in the sets on the objective function hyperplane.A simple numerical example shows that the algorithm is efficient for some problems,and therefore,of practical interest.

  10. Arithmetic progressions in Salem-type subsets of the integers

    CERN Document Server

    Potgieter, Paul

    2010-01-01

    Given a subset of the integers of zero density, we define the weaker notion of fractional density of such a set. It is shown how this notion corresponds to that of the Hausdorff dimension of a compact subset of the reals. We then show that a version of a theorem of {\\L}aba and Pramanik on 3-term arithmetic progressions in subsets of the unit interval also holds for subsets of the integers with fractional density and satisfying certain Fourier-decay conditions.

  11. Floating-point processor for INTEL 8080A microprocessor systems

    Energy Technology Data Exchange (ETDEWEB)

    Bairstow, R.; Barlow, J.; Jires, M.; Waters, M.

    1982-03-01

    An A.M.D. 9511 Floating Point Processor has been interfaced to the Rutherford Laboratory Bubble Chamber Group's microcomputers. These computers are based on the INTEL 8080A microprocessor. The interface uses a memory mapped I/O technique to ensure rapid transfer of arguments between processors. The A.M.D. 9511 acts as a slave processor to the INTEL 8080A system. The 8080 processor is held in WAIT status until completion of the A.M.D. operation. A software Macro Processor has been written to effectively extend the basic INTEL 8080A instruction set to include the full range of A.M.D. 9511 instructions.

  12. Biosorption of gold from computer microprocessor leachate solutions using chitin.

    Science.gov (United States)

    Côrtes, Letícia N; Tanabe, Eduardo H; Bertuol, Daniel A; Dotto, Guilherme L

    2015-11-01

    The biosorption of gold from discarded computer microprocessor (DCM) leachate solutions was studied using chitin as a biosorbent. The DCM components were leached with thiourea solutions, and two procedures were tested for recovery of gold from the leachates: (1) biosorption and (2) precipitation followed by biosorption. For each procedure, the biosorption was evaluated considering kinetic, equilibrium, and thermodynamic aspects. The general order model was able to represent the kinetic behavior, and the equilibrium was well represented by the BET model. The maximum biosorption capacities were around 35 mg g(-1) for both procedures. The biosorption of gold on chitin was a spontaneous, favorable, and exothermic process. It was found that precipitation followed by biosorption resulted in the best gold recovery, because other species were removed from the leachate solution in the precipitation step. This method enabled about 80% of the gold to be recovered, using 20 g L(-1) of chitin at 298 K for 4 h.

  13. FRISC-E; A 250-MIPS hybrid microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Greub, H.J. (Rensselaer Polytechnic Inst., Troy, NY (USA). Center for Integrated Electronics); McDonald, J.F. (Rensselaer Polytechnic Inst., Troy, NY (USA). Dept. of Electrical, Computer, and Systems Engineering); Creedon, T.G. (Tektronix, Inc., Beaverton, OR (USA))

    1990-05-01

    Implementing the principles of reduced instruction set computers (RISC) with advanced high-speed circuit technology is both attractive and difficult. Advanced bipolar circuit technology, for instance, offers gate delays as low as 55 ps but dissipates considerable power. Therefore, a high-speed microprocessor fabricated with this technology must be partitioned into LSI circuits to increase yield and reduce heat flux. But partitioning requires die-to-die interconnections, which cause signal propagation delays. The authors discuss how the FRISC series of fast reduced instruction set computer designs goes a long way towards solving these problems. For FRISC-E the targeted instruction rate of 250 MIPS led to a seven-stage instruction pipeline. The authors have partitioned the processor into 11 chips.

  14. Microprocessor-controlled colonic peristalsis: dynamic parametric modeling in dogs.

    Science.gov (United States)

    Rashev, Peter Z; Amaris, Manuel; Bowes, Kenneth L; Mintchev, Martin P

    2002-05-01

    The study aimed at completing a model of functional colonic electric stimulation and testing it for artificial recreation of peristalsis in dogs. Dynamic measurements of invoked single contractions obtained from two unconscious dogs as well as previously reported static contraction properties were utilized to suggest the optimal stimulation parameters of: (1) length of the stimulating electrodes, (2) separation between the successive electrode sets, (3) duration, and (4) phase lag between the stimuli sequentially applied to the electrode sets. The derived electrode configuration and stimulation pattern were adjusted for different anatomical dimensions and tested in distended colon full of viscous content. Forward and backward propagating peristaltic waves were invoked in two other unconscious dogs, indicating that the recreation of colonic peristalsis under microprocessor control is feasible.

  15. Transient fault behavior in a microprocessor: A case study

    Science.gov (United States)

    Duba, Patrick

    1989-01-01

    An experimental analysis is described which studies the susceptibility of a microprocessor based jet engine controller to upsets caused by current and voltage transients. A design automation environment which allows the run time injection of transients and the tracing from their impact device to the pin level is described. The resulting error data are categorized by the charge levels of the injected transients by location and by their potential to cause logic upsets, latched errors, and pin errors. The results show a 3 picoCouloumb threshold, below which the transients have little impact. An Arithmetic and Logic Unit transient is most likely to result in logic upsets and pin errors (i.e., impact the external environment). The transients in the countdown unit are potentially serious since they can result in latched errors, thus causing latent faults. Suggestions to protect the processor against these errors, by incorporating internal error detection and transient suppression techniques, are also made.

  16. Microprocessor tester for the treat upgrade reactor trip system

    Energy Technology Data Exchange (ETDEWEB)

    Lenkszus, F.R.; Bucher, R.G.

    1984-01-01

    The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety system is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations.

  17. Fuzzy Concurrent Object Oriented Expert System for Fault Diagnosis in 8085 Microprocessor Based System Board

    Directory of Open Access Journals (Sweden)

    Mr.D. V. Kodavade

    2014-09-01

    Full Text Available With the acceptance of artificial intelligence paradigm, a number of successful artificial intelligence systems were created. Fault diagnosis in microprocessor based boards needs lot of empirical knowledge and expertise and is a true artificial intelligence problem. Research on fault diagnosis in microprocessor based system boards using new fuzzy-object oriented approach is presented in this paper. There are many uncertain situations observed during fault diagnosis. These uncertain situations were handled using fuzzy mathematics properties. Fuzzy inference mechanism is demonstrated using one case study. Some typical faults in 8085 microprocessor board and diagnostic procedures used is presented in this paper.

  18. Report on the formal specification and partial verification of the VIPER microprocessor

    Science.gov (United States)

    Brock, Bishop; Hunt, Warren A., Jr.

    1991-01-01

    The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed.

  19. Quantum recurrence and integer ratios in neutron resonances

    Energy Technology Data Exchange (ETDEWEB)

    Ohkubo, Makio

    1998-03-01

    Quantum recurrence of the compound nucleus in neutron resonance reactions are described for normal modes which are excited on the compound nucleus simultaneously. In the structure of the recurrence time, integer relations among dominant level spacings are derived. The `base modes` are assumed as stable combinations of the normal modes, preferably excited in many nuclei. (author)

  20. Designing fractional factorial split-plot experiments using integer programming

    DEFF Research Database (Denmark)

    Capehart, Shay R.; Keha, Ahmet; Kulahci, Murat

    2011-01-01

    factorial (FF) design, with the restricted randomisation structure to account for the whole plots and subplots. We discuss the formulation of FFSP designs using integer programming (IP) to achieve various design criteria. We specifically look at the maximum number of clear two-factor interactions...

  1. Method for solving a convex integer programming problem

    OpenAIRE

    Stefanov, Stefan M.

    2003-01-01

    We consider a convex integer program which is a nonlinear version of the assignment problem. This problem is reformulated as an equivalent problem. An algorithm for solving the original problem is suggested which is based on solving the simple assignment problem via some of known algorithms.

  2. Solving linear integer programming problems by a novel neural model.

    Science.gov (United States)

    Cavalieri, S

    1999-02-01

    The paper deals with integer linear programming problems. As is well known, these are extremely complex problems, even when the number of integer variables is quite low. Literature provides examples of various methods to solve such problems, some of which are of a heuristic nature. This paper proposes an alternative strategy based on the Hopfield neural network. The advantage of the strategy essentially lies in the fact that hardware implementation of the neural model allows for the time required to obtain a solution so as not depend on the size of the problem to be solved. The paper presents a particular class of integer linear programming problems, including well-known problems such as the Travelling Salesman Problem and the Set Covering Problem. After a brief description of this class of problems, it is demonstrated that the original Hopfield model is incapable of supplying valid solutions. This is attributed to the presence of constant bias currents in the dynamic of the neural model. A demonstration of this is given and then a novel neural model is presented which continues to be based on the same architecture as the Hopfield model, but introduces modifications thanks to which the integer linear programming problems presented can be solved. Some numerical examples and concluding remarks highlight the solving capacity of the novel neural model.

  3. Unique Factorization in Cyclotomic Integers of Degree Seven

    Science.gov (United States)

    Duckworth, W. Ethan

    2008-01-01

    This article provides a survey of some basic results in algebraic number theory and applies this material to prove that the cyclotomic integers generated by a seventh root of unity are a unique factorization domain. Part of the proof uses the computer algebra system Maple to find and verify factorizations. The proofs use a combination of historic…

  4. Leveraging Structure: Logical Necessity in the Context of Integer Arithmetic

    Science.gov (United States)

    Bishop, Jessica Pierson; Lamb, Lisa L.; Philipp, Randolph A.; Whitacre, Ian; Schappelle, Bonnie P.

    2016-01-01

    Looking for, recognizing, and using underlying mathematical structure is an important aspect of mathematical reasoning. We explore the use of mathematical structure in children's integer strategies by developing and exemplifying the construct of logical necessity. Students in our study used logical necessity to approach and use numbers in a…

  5. Limit theorems for bifurcating integer-valued autoregressive processes

    CERN Document Server

    Blandin, Vassili

    2012-01-01

    We study the asymptotic behavior of the weighted least squares estimators of the unknown parameters of bifurcating integer-valued autoregressive processes. Under suitable assumptions on the immigration, we establish the almost sure convergence of our estimators, together with the quadratic strong law and central limit theorems. All our investigation relies on asymptotic results for vector-valued martingales.

  6. Designing fractional factorial split-plot experiments using integer programming

    DEFF Research Database (Denmark)

    Capehart, Shay R.; Keha, Ahmet; Kulahci, Murat

    2011-01-01

    factorial (FF) design, with the restricted randomisation structure to account for the whole plots and subplots. We discuss the formulation of FFSP designs using integer programming (IP) to achieve various design criteria. We specifically look at the maximum number of clear two-factor interactions...

  7. Happy and Sad Thoughts: An Exploration of Children's Integer Reasoning

    Science.gov (United States)

    Whitacre, Ian; Bishop, Jessica Pierson; Lamb, Lisa L. C.; Philipp, Randolph A.; Schappelle, Bonnie P.; Lewis, Melinda L.

    2012-01-01

    The purpose of this study was to investigate elementary children's conceptions that might serve as foundations for integer reasoning. Working from an abstract algebraic perspective and using an opposite-magnitudes context that is relevant to children, we analyzed the reasoning of 33 children in grades K-5. We focus our report on three prominent…

  8. Automorphisms of semigroups of invertible matrices with nonnegative integer elements

    Energy Technology Data Exchange (ETDEWEB)

    Semenov, Pavel P [M. V. Lomonosov Moscow State University, Faculty of Mechanics and Mathematics, Moscow (Russian Federation)

    2012-09-30

    Let G{sub n}(Z) be the subsemigroup of GL{sub n}(Z) consisting of the matrices with nonnegative integer coefficients. In the paper, the automorphisms of this semigroup are described for n{>=}2. Bibliography: 5 titles.

  9. A fast DFT algorithm using complex integer transforms

    Science.gov (United States)

    Reed, I. S.; Truong, T. K.

    1978-01-01

    Winograd's algorithm for computing the discrete Fourier transform is extended considerably for certain large transform lengths. This is accomplished by performing the cyclic convolution, required by Winograd's method, by a fast transform over certain complex integer fields. This algorithm requires fewer multiplications than either the standard fast Fourier transform or Winograd's more conventional algorithms.

  10. Triangular Numbers, Gaussian Integers, and KenKen

    Science.gov (United States)

    Watkins, John J.

    2012-01-01

    Latin squares form the basis for the recreational puzzles sudoku and KenKen. In this article we show how useful several ideas from number theory are in solving a KenKen puzzle. For example, the simple notion of triangular number is surprisingly effective. We also introduce a variation of KenKen that uses the Gaussian integers in order to…

  11. Algorithms and Data Structures for Strings, Points and Integers

    DEFF Research Database (Denmark)

    Vind, Søren Juhl

    This dissertation presents our research in the broad area of algorithms and data structures. More specifically, we show solutions for the following problems related to strings, points and integers. Results hold on the Word RAM and we measure space in w-bit words. Compressed Fingerprints. The Karp...

  12. Negative Integer Understanding: Characterizing First Graders' Mental Models

    Science.gov (United States)

    Bofferding, Laura

    2014-01-01

    This article presents results of a research study. Sixty-one first graders' responses to interview questions about negative integer values and order and directed magnitudes were examined to characterize the students' mental models. The models reveal that initially, students overrelied on various combinations of whole-number principles as…

  13. Happy and Sad Thoughts: An Exploration of Children's Integer Reasoning

    Science.gov (United States)

    Whitacre, Ian; Bishop, Jessica Pierson; Lamb, Lisa L. C.; Philipp, Randolph A.; Schappelle, Bonnie P.; Lewis, Melinda L.

    2012-01-01

    The purpose of this study was to investigate elementary children's conceptions that might serve as foundations for integer reasoning. Working from an abstract algebraic perspective and using an opposite-magnitudes context that is relevant to children, we analyzed the reasoning of 33 children in grades K-5. We focus our report on three prominent…

  14. Currency Arbitrage Detection Using a Binary Integer Programming Model

    Science.gov (United States)

    Soon, Wanmei; Ye, Heng-Qing

    2011-01-01

    In this article, we examine the use of a new binary integer programming (BIP) model to detect arbitrage opportunities in currency exchanges. This model showcases an excellent application of mathematics to the real world. The concepts involved are easily accessible to undergraduate students with basic knowledge in Operations Research. Through this…

  15. Stochastic level-value approximation for quadratic integer convex programming

    Institute of Scientific and Technical Information of China (English)

    PENG Zheng; WU Dong-hua

    2008-01-01

    We propose a stochastic level value approximation method for a quadratic integer convex minimizing problem in this paper. This method applies an importance sampling technique, and make use of the cross-entropy method to update the sample density functions. We also prove the asymptotic convergence of this algorithm, and re-port some numerical results to illuminate its effectiveness.

  16. Solving the Water Jugs Problem by an Integer Sequence Approach

    Science.gov (United States)

    Man, Yiu-Kwong

    2012-01-01

    In this article, we present an integer sequence approach to solve the classic water jugs problem. The solution steps can be obtained easily by additions and subtractions only, which is suitable for manual calculation or programming by computer. This approach can be introduced to secondary and undergraduate students, and also to teachers and…

  17. Simple integer recourse models : convexity and convex approximations

    NARCIS (Netherlands)

    Klein Haneveld, W.K.; Stougie, L.; van der Vlerk, M.H.

    We consider the objective function of a simple recourse problem with fixed technology matrix and integer second-stage variables. Separability due to the simple recourse structure allows to study a one-dimensional version instead. Based on an explicit formula for the objective function, we derive a

  18. Simple Integer Recourse Models : Convexity and Convex Approximations

    NARCIS (Netherlands)

    Klein Haneveld, Willem K.; Stougie, L; van der Vlerk, Maarten H.

    2004-01-01

    We consider the objective function of a simple recourse problem with fixed technology matrix and integer second-stage variables. Separability due to the simple recourse structure allows to study a one-dimensional version instead. Based on an explicit formula for the objective function, we derive a

  19. The role of the microprocessor in onboard image processing for the information adaptive system

    Science.gov (United States)

    Kelly, W. L., IV; Meredith, B. D.

    1980-01-01

    The preliminary design of the Information Adaptive System is presented. The role of the microprocessor in the implementation of the individual processing elements is discussed. Particular emphasis is placed on multispectral image data processing.

  20. A low cost matching motion estimation sensor based on the NIOS II microprocessor

    National Research Council Canada - National Science Library

    González, Diego; Botella, Guillermo; Meyer-Baese, Uwe; García, Carlos; Sanz, Concepción; Prieto-Matías, Manuel; Tirado, Francisco

    2012-01-01

    ...) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology...

  1. Formal proof of the AVM-1 microprocessor using the concept of generic interpreters

    Science.gov (United States)

    Windley, P.; Levitt, K.; Cohen, G. C.

    1991-01-01

    A microprocessor designated AVM-1 was designed to demonstrate the use of generic interpreters in verifying hierarchically decomposed microprocessor specifications. This report is intended to document the high-order language (HOL) code verifying AVM-1. The organization of the proof is discussed and some technical details concerning the execution of the proof scripts in HOL are presented. The proof scripts used to verify AVM-1 are also presented.

  2. Microprocessor based implementation of attitude and shape control of large space structures

    Science.gov (United States)

    Reddy, A. S. S. R.

    1984-01-01

    The feasibility of off the shelf eight bit and 16 bit microprocessors to implement linear state variable feedback control laws and assessing the real time response to spacecraft dynamics is studied. The complexity of the dynamic model is described along with the appropriate software. An experimental setup of a beam, microprocessor system for implementing the control laws and the needed generalized software to implement any state variable feedback control system is included.

  3. MicroShell Minimalist Shell for Xilinx Microprocessors

    Science.gov (United States)

    Werne, Thomas A.

    2011-01-01

    MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is

  4. Post-transcriptional control of DGCR8 expression by the Microprocessor.

    Science.gov (United States)

    Triboulet, Robinson; Chang, Hao-Ming; Lapierre, Robert J; Gregory, Richard I

    2009-06-01

    The Microprocessor, comprising the RNase III Drosha and the double-stranded RNA binding protein DGCR8, is essential for microRNA (miRNA) biogenesis. In the miRNA processing pathway certain hairpin structures within primary miRNA (pri-miRNA) transcripts are specifically cleaved by the Microprocessor to release approximately 60-70-nucleotide precursor miRNA (pre-miRNA) intermediates. Although both Drosha and DGCR8 are required for Microprocessor activity, the mechanisms regulating the expression of these proteins are unknown. Here we report that the Microprocessor negatively regulates DGCR8 expression. Using in vitro reconstitution and in vivo studies, we demonstrate that a hairpin, localized in the 5' untranslated region (5'UTR) of DGCR8 mRNA, is cleaved by the Microprocessor. Accordingly, knockdown of Drosha leads to an increase in DGCR8 mRNA and protein levels in cells. Furthermore, we found that the DGCR8 5'UTR confers Microprocessor-dependent repression of a luciferase reporter gene in vivo. Our results uncover a novel feedback loop that regulates DGCR8 levels.

  5. Efficient Algorithms for gcd and Cubic Residuosity in the Ring of Eisenstein Integers

    DEFF Research Database (Denmark)

    Damgård, Ivan Bjerre; Frandsen, Gudmund Skovbjerg

    2003-01-01

    We present simple and efficient algorithms for computing gcd and cubic residuosity in the ring of Eisenstein integers, bf Z[ ]i.e. the integers extended with , a complex primitive third root of unity. The algorithms are similar and may be seen as generalisations of the binary integer gcd and deri...... primality tests and the implementation of cryptographic protocols....

  6. GNSS integer ambiguity estimation and evaluation: LAMBDA and Ps-LAMBDA

    NARCIS (Netherlands)

    Li, B.; Verhagen, A.A.; Teunissen, P.J.G.

    2013-01-01

    Successful integer carrier-phase ambiguity resolution is crucial for high precision GNSS applications. It includes both integer estimation and evaluation. For integer estimation, the LAMBDA method has been applied in a wide variety of GNSS applications. The method’s popularity stems from its numeric

  7. Evidence for a cytoplasmic microprocessor of pri-miRNAs.

    Science.gov (United States)

    Shapiro, Jillian S; Langlois, Ryan A; Pham, Alissa M; Tenoever, Benjamin R

    2012-07-01

    microRNAs (miRNAs) represent a class of noncoding RNAs that fine-tune gene expression through post-transcriptional silencing. While miRNA biogenesis occurs in a stepwise fashion, initiated by the nuclear microprocessor, rare noncanonical miRNAs have also been identified. Here we characterize the molecular components and unique attributes associated with the processing of virus-derived cytoplasmic primary miRNAs (c-pri-miRNAs). RNA in situ hybridization and inhibition of cellular division demonstrated a complete lack of nuclear involvement in c-pri-miRNA cleavage while genetic studies revealed that maturation still relied on the canonical nuclear RNase III enzyme, Drosha. The involvement of Drosha was mediated by a dramatic relocalization to the cytoplasm following virus infection. Deep sequencing analyses revealed that the cytoplasmic localization of Drosha does not impact the endogenous miRNA landscape during infection, despite allowing for robust synthesis of virus-derived miRNAs in the cytoplasm. Taken together, this research describes a unique function for Drosha in the processing of highly structured cytoplasmic RNAs in the context of virus infection.

  8. Microprocessor-based gait analysis system to retrain Trendelenburg gait.

    Science.gov (United States)

    Petrofsky, J S

    2001-01-01

    A microprocessor-based gait analysis system is described that uses two electromyogram (EMG) amplifiers, two foot switches and an audio feedback device to allow the retraining of one type of improper gait, where the hip abductors (gluteus medius muscles) are weak on one side of the body, causing the opposite hip to drop during the swing phase of gait (Trendelenburg gait). As the abnormality is strictly on one side of the body in most people, the circuitry is minimised, as gait can be analysed by only comparing muscle activity in the affected gluteus medius muscle with that in the unaffected gluteus medius muscle, through the EMG. Two foot contact switches are used to help assess timing of the step cycle. If gait is different on the two sides of the body, an audio cue directs the patient to correct the abnormality by increasing activity on the affected side. The device is tested on five patients. Trendelenburg gait is reduced by an average of 29 degrees through the use of the device. The average stride length at the beginning of the study is 0.32 +/- 0.3 m. By the end of the study, the stride length is increased to 0.45 +/- 0.2 m for the entire group of five subjects. The speed of gait has increased from 1.6 +/- 0.4 kmh(-1) to 3.1 +/- 0.5km h(-1).

  9. GPS/MEMS IMU/Microprocessor Board for Navigation

    Science.gov (United States)

    Gender, Thomas K.; Chow, James; Ott, William E.

    2009-01-01

    A miniaturized instrumentation package comprising a (1) Global Positioning System (GPS) receiver, (2) an inertial measurement unit (IMU) consisting largely of surface-micromachined sensors of the microelectromechanical systems (MEMS) type, and (3) a microprocessor, all residing on a single circuit board, is part of the navigation system of a compact robotic spacecraft intended to be released from a larger spacecraft [e.g., the International Space Station (ISS)] for exterior visual inspection of the larger spacecraft. Variants of the package may also be useful in terrestrial collision-detection and -avoidance applications. The navigation solution obtained by integrating the IMU outputs is fed back to a correlator in the GPS receiver to aid in tracking GPS signals. The raw GPS and IMU data are blended in a Kalman filter to obtain an optimal navigation solution, which can be supplemented by range and velocity data obtained by use of (l) a stereoscopic pair of electronic cameras aboard the robotic spacecraft and/or (2) a laser dynamic range imager aboard the ISS. The novelty of the package lies mostly in those aspects of the design of the MEMS IMU that pertain to controlling mechanical resonances and stabilizing scale factors and biases.

  10. Formal verification of a microcoded VIPER microprocessor using HOL

    Science.gov (United States)

    Levitt, Karl; Arora, Tejkumar; Leung, Tony; Kalvala, Sara; Schubert, E. Thomas; Windley, Philip; Heckman, Mark; Cohen, Gerald C.

    1993-01-01

    The Royal Signals and Radar Establishment (RSRE) and members of the Hardware Verification Group at Cambridge University conducted a joint effort to prove the correspondence between the electronic block model and the top level specification of Viper. Unfortunately, the proof became too complex and unmanageable within the given time and funding constraints, and is thus incomplete as of the date of this report. This report describes an independent attempt to use the HOL (Cambridge Higher Order Logic) mechanical verifier to verify Viper. Deriving from recent results in hardware verification research at UC Davis, the approach has been to redesign the electronic block model to make it microcoded and to structure the proof in a series of decreasingly abstract interpreter levels, the lowest being the electronic block level. The highest level is the RSRE Viper instruction set. Owing to the new approach and some results on the proof of generic interpreters as applied to simple microprocessors, this attempt required an effort approximately an order of magnitude less than the previous one.

  11. Information distribution in distributed microprocessor based flight control systems

    Science.gov (United States)

    Montgomery, R. C.; Lee, P. S.

    1977-01-01

    This paper presents an optimal control theory that accounts for variable time intervals in the information distribution to control effectors in a distributed microprocessor based flight control system. The theory is developed using a linear process model for the aircraft dynamics and the information distribution process is modeled as a variable time increment process where, at the time that information is supplied to the control effectors, the control effectors know the time of the next information update only in a stochastic sense. An optimal control problem is formulated and solved that provides the control law that minimizes the expected value of a quadratic cost function. An example is presented where the theory is applied to the control of the longitudinal motions of the F8-DFBW aircraft. Theoretical and simulation results indicate that, for the example problem, the optimal cost obtained using a variable time increment Markov information update process where the control effectors know only the past information update intervals and the Markov transition mechanism is almost identical to that obtained using a known uniform information update interval.

  12. Design for Testability Features of Godson-3 Multicore Microprocessor

    Institute of Scientific and Technical Information of China (English)

    Zi-Chu Qi; Hui Liu; Xiang-Ku Li; Wei-Wu Hu

    2011-01-01

    This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

  13. Microprocessor control and networking for the amps breadboard

    Science.gov (United States)

    Floyd, Stephen A.

    1987-01-01

    Future space missions will require more sophisticated power systems, implying higher costs and more extensive crew and ground support involvement. To decrease this human involvement, as well as to protect and most efficiently utilize this important resource, NASA has undertaken major efforts to promote progress in the design and development of autonomously managed power systems. Two areas being actively pursued are autonomous power system (APS) breadboards and knowledge-based expert system (KBES) applications. The former are viewed as a requirement for the timely development of the latter. Not only will they serve as final testbeds for the various KBES applications, but will play a major role in the knowledge engineering phase of their development. The current power system breadboard designs are of a distributed microprocessor nature. The distributed nature, plus the need to connect various external computer capabilities (i.e., conventional host computers and symbolic processors), places major emphasis on effective networking. The communications and networking technologies for the first power system breadboard/test facility are described.

  14. Microprocessor-controlled wide-range streak camera

    Science.gov (United States)

    Lewis, Amy E.; Hollabaugh, Craig

    2006-08-01

    Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera's user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.

  15. A Secret Image Sharing Method Using Integer Wavelet Transform

    Directory of Open Access Journals (Sweden)

    Li Ching-Chung

    2007-01-01

    Full Text Available A new image sharing method, based on the reversible integer-to-integer (ITI wavelet transform and Shamir's threshold scheme is presented, that provides highly compact shadows for real-time progressive transmission. This method, working in the wavelet domain, processes the transform coefficients in each subband, divides each of the resulting combination coefficients into shadows, and allows recovery of the complete secret image by using any or more shadows . We take advantages of properties of the wavelet transform multiresolution representation, such as coefficient magnitude decay and excellent energy compaction, to design combination procedures for the transform coefficients and processing sequences in wavelet subbands such that small shadows for real-time progressive transmission are obtained. Experimental results demonstrate that the proposed method yields small shadow images and has the capabilities of real-time progressive transmission and perfect reconstruction of secret images.

  16. Extracting vascular networks under physiological constraints via integer programming.

    Science.gov (United States)

    Rempfler, Markus; Schneider, Matthias; Ielacqua, Giovanna D; Xiao, Xianghui; Stock, Stuart R; Klohs, Jan; Székely, Gábor; Andres, Bjoern; Menze, Bjoern H

    2014-01-01

    We introduce an integer programming-based approach to vessel network extraction that enforces global physiological constraints on the vessel structure and learn this prior from a high-resolution reference network. The method accounts for both image evidence and geometric relationships between vessels by formulating and solving an integer programming problem. Starting from an over-connected network, it is pruning vessel stumps and spurious connections by evaluating bifurcation angle and connectivity of the graph. We utilize a high-resolution micro computed tomography (μCT) dataset of a cerebrovascular corrosion cast to obtain a reference network, perform experiments on micro magnetic resonance angiography (μMRA) images of mouse brains and discuss properties of the networks obtained under different tracking and pruning approaches.

  17. A fuzzy mixed integer programming for marketing planning

    Directory of Open Access Journals (Sweden)

    Abolfazl Danaei

    2014-03-01

    Full Text Available One of the primary concerns to market a product is to find appropriate channel to target customers. The recent advances on information technology have created new products with tremendous opportunities. This paper presents a mixed integer programming technique based on McCarthy's 4PS to locate suitable billboards for marketing newly introduced IPHONE product. The paper considers two types of information including age and income and tries to find the best places such that potential consumers aged 25-35 with high income visit the billboards and the cost of advertisement is minimized. The model is formulated in terms of mixed integer programming and it has been applied for potential customers who live in city of Tabriz, Iran. Using a typical software package, the model detects appropriate places in various parts of the city.

  18. Two dimensional convolute integers for machine vision and image recognition

    Science.gov (United States)

    Edwards, Thomas R.

    1988-01-01

    Machine vision and image recognition require sophisticated image processing prior to the application of Artificial Intelligence. Two Dimensional Convolute Integer Technology is an innovative mathematical approach for addressing machine vision and image recognition. This new technology generates a family of digital operators for addressing optical images and related two dimensional data sets. The operators are regression generated, integer valued, zero phase shifting, convoluting, frequency sensitive, two dimensional low pass, high pass and band pass filters that are mathematically equivalent to surface fitted partial derivatives. These operators are applied non-recursively either as classical convolutions (replacement point values), interstitial point generators (bandwidth broadening or resolution enhancement), or as missing value calculators (compensation for dead array element values). These operators show frequency sensitive feature selection scale invariant properties. Such tasks as boundary/edge enhancement and noise or small size pixel disturbance removal can readily be accomplished. For feature selection tight band pass operators are essential. Results from test cases are given.

  19. Integer-ambiguity resolution in astronomy and geodesy

    CERN Document Server

    Lannes, André

    2013-01-01

    Recent theoretical developments in astronomical aperture synthesis have revealed the existence of integer-ambiguity problems. Those problems, which appear in the self-calibration procedures of radio imaging, have been shown to be similar to the nearest-lattice point (NLP) problems encountered in high-precision geodetic positioning, and in global navigation satellite systems. In this paper, we analyse the theoretical aspects of the matter and propose new methods for solving those NLP problems. The related optimization aspects concern both the preconditioning stage, and the discrete-search stage in which the integer ambiguities are finally fixed. Our algorithms, which are described in an explicit manner, can easily be implemented. They lead to substantial gains in the processing time of both stages. Their efficiency was shown via intensive numerical tests.

  20. Optimization of integer wavelet transforms based on difference correlation structures.

    Science.gov (United States)

    Li, Hongliang; Liu, Guizhong; Zhang, Zhongwei

    2005-11-01

    In this paper, a novel lifting integer wavelet transform based on difference correlation structure (DCCS-LIWT) is proposed. First, we establish a relationship between the performance of a linear predictor and the difference correlations of an image. The obtained results provide a theoretical foundation for the following construction of the optimal lifting filters. Then, the optimal prediction lifting coefficients in the sense of least-square prediction error are derived. DCCS-LIWT puts heavy emphasis on image inherent dependence. A distinct feature of this method is the use of the variance-normalized autocorrelation function of the difference image to construct a linear predictor and adapt the predictor to varying image sources. The proposed scheme also allows respective calculations of the lifting filters for the horizontal and vertical orientations. Experimental evaluation shows that the proposed method produces better results than the other well-known integer transforms for the lossless image compression.

  1. A NOVEL INTEGER FREQUENCY OFFSET ESTIMATOR FOR OFDM

    Institute of Scientific and Technical Information of China (English)

    Cai Xuelian; Li Jiandong; Li Changle; Chen Chen

    2005-01-01

    One of the principal disadvantages of Orthogonal Frequency Division Multiplexing (OFDM) is very sensitive to carrier frequency offset. The integer frequency offset has no effect on the orthogonality among the subcarriers, but it causes a circular shift and phase rotation of the received data symbols sequence, resulting in a Bit Error Rate(BER) of 0.5. In this paper,a novel integer frequency offset estimator for OFDM is derived based on maximum likelihood estimation technique and exploration of the differential relation between two consecutive OFDM data symbol sequences in frequency domain. Its performance is compared with the conventional method by computer simulations for the additive white Gaussian noise channel and a multipath fading channel. Simulation results show that the performance of the proposed estimator is better than the conventional estimator.

  2. Linear Independence of -Logarithms over the Eisenstein Integers

    Directory of Open Access Journals (Sweden)

    Peter Bundschuh

    2010-01-01

    Full Text Available For fixed complex with ||>1, the -logarithm is the meromorphic continuation of the series ∑>0/(−1,||1,≠,2,3,…. In 2004, Tachiya showed that this is true in the Subcase =ℚ, ∈ℤ, =−1, and the present authors extended this result to arbitrary integer from an imaginary quadratic number field , and provided a quantitative version. In this paper, the earlier method, in particular its arithmetical part, is further developed to answer the above question in the affirmative if is the Eisenstein number field √ℚ(−3, an integer from , and a primitive third root of unity. Under these conditions, the linear independence holds also for 1,(,(−1, and both results are quantitative.

  3. Some new thin sets of integers in Harmonic Analysis

    CERN Document Server

    Li, Daniel; Rodriguez-Piazza, Luis

    2009-01-01

    We randomly construct various subsets $\\Lambda$ of the integers which have both smallness and largeness properties. They are small since they are very close, in various meanings, to Sidon sets: the continuous functions with spectrum in $\\Lambda$ have uniformly convergent series, and their Fourier coefficients are in $\\ell_p$ for all $p>1$; moreover, all the Lebesgue spaces $L^q_\\Lambda$ are equal for $q<+\\infty$. On the other hand, they are large in the sense that they are dense in the Bohr group and that the space of the bounded functions with spectrum in $\\Lambda$ is non separable. So these sets are very different from the thin sets of integers previously known.

  4. Low Complexity Integer Transform and Adaptive Quantization Optimization

    Institute of Scientific and Technical Information of China (English)

    Si-Wei Ma; Wen Gao

    2006-01-01

    In this paper, a new low complexity integer transform is proposed, which has been adopted by AVS1-PT. The proposed transform can enable AVS1-P7 to share the same quantization/dequantization table with AVS1-P2. As the bases of the proposed transform coefficients are very close, the transform normalization can be implemented only on the encoder side and the dequantization table size can be reduced compared with the transform used in H.264/MPEG-4 AVC. Along with the feature of the proposed transform, adaptive dead-zone quantization optimization for the proposed transform is studied.Experimental results show that the proposed integer transform has similar coding performance compared with the transform used in H.264/MPEG-4 AVC, and would gain near 0.1dB with the adaptive dead-zone quantization optimization.

  5. Relaxation and decomposition methods for mixed integer nonlinear programming

    CERN Document Server

    Nowak, Ivo; Bank, RE

    2005-01-01

    This book presents a comprehensive description of efficient methods for solving nonconvex mixed integer nonlinear programs, including several numerical and theoretical results, which are presented here for the first time. It contains many illustrations and an up-to-date bibliography. Because on the emphasis on practical methods, as well as the introduction into the basic theory, the book is accessible to a wide audience. It can be used both as a research and as a graduate text.

  6. Consequences of the Continuity of the Monic Integer Transfinite Diameter

    CERN Document Server

    Hilmar, Jan

    2007-01-01

    We consider the problem of determining the monic integer transfinite diameter t_M(I)&=&\\lim_{n\\to\\infty}\\inf_{p_n\\in{\\mathcal M_n}}\\supnorm{p_n}{I}^{1/n} for real intervals of length less than 4. We show the $t_M([0,x])$, as a function in $x>0$, is continuous, therefore disproving two conjectures due to Hare and Smyth. Consequently, for $n>2\\in\

  7. Computing Integer Powers in Floating-Point Arithmetic

    CERN Document Server

    Kornerup, Peter; Muller, Jean-Michel

    2007-01-01

    We introduce two algorithms for accurately evaluating powers to a positive integer in floating-point arithmetic, assuming a fused multiply-add (fma) instruction is available. We show that our log-time algorithm always produce faithfully-rounded results, discuss the possibility of getting correctly rounded results, and show that results correctly rounded in double precision can be obtained if extended-precision is available with the possibility to round into double precision (with a single rounding).

  8. Computing Integer Powers in Floating-Point Arithmetic

    OpenAIRE

    Kornerup, Peter; Lefèvre, Vincent; Muller, Jean-Michel

    2007-01-01

    We introduce two algorithms for accurately evaluating powers to a positive integer in floating-point arithmetic, assuming a fused multiply-add (fma) instruction is available. We show that our log-time algorithm always produce faithfully-rounded results, discuss the possibility of getting correctly rounded results, and show that results correctly rounded in double precision can be obtained if extended-precision is available with the possibility to round into double precision (with a single rou...

  9. THE ALGORITHMS OF AN INTEGER PARTITIONING WITH ITS APPLICATIONS

    Institute of Scientific and Technical Information of China (English)

    曹立明; 周强

    1994-01-01

    In the light of the ideals of Artificial Intelligence(AI) , three algorithms of an integer partitioning have been given in this paper:generate and test algorithm ,and two heuristic algorithms about forward partition and backward partition. PROLOG has been used to describe algorithms, it is reasonable, direct and simple. In the sight of describing algorithms ,it is a new and valid try. At last, some intresting applications of the algorithms mentioned in the paper have been presented.

  10. Optimal source codes for geometrically distributed integer alphabets

    Science.gov (United States)

    Gallager, R. G.; Van Voorhis, D. C.

    1975-01-01

    An approach is shown for using the Huffman algorithm indirectly to prove the optimality of a code for an infinite alphabet if an estimate concerning the nature of the code can be made. Attention is given to nonnegative integers with a geometric probability assignment. The particular distribution considered arises in run-length coding and in encoding protocol information in data networks. Questions of redundancy of the optimal code are also investigated.

  11. Optimizing Marine Corps Personnel Assignments Using an Integer Programming Model

    Science.gov (United States)

    2012-12-01

    would assist the Monitors in the assignment process. Though these studies contain very thorough analyses, they differ from the approach taken in this...thesis in that they do not look into using a low cost, yet very efficient, decision modeling approach of integer programming as a method of...2012 BAH Rates-with Dependents. Defense Travel Mangement Office. (2011, December). 2012 BAH Rates-without Dependents. M ileage C ost 1 Per D iem

  12. On Integers, Primes and UniqueFactorization in Quadratic Fields

    OpenAIRE

    Hedenlund, Alice

    2013-01-01

    Abstract. This thesis will deal with quadratic elds. The prob- lem is to study such elds and their properties including, but not limited to, determining integers, nding primes and deciding which quadratic elds have unique factorization. The goal is to get famil- iar with these concepts and to provide a starting point for students with an interest in algebra to explore eld extensions and inte- gral closures in relation to elementary number theory. The reader will be assumed to have a basic kn...

  13. Application of Integer and Fractional Models in Electrochemical Systems

    Directory of Open Access Journals (Sweden)

    Isabel S. Jesus

    2012-01-01

    Full Text Available This paper describes the use of integer and fractional electrical elements, for modelling two electrochemical systems. A first type of system consists of botanical elements and a second type is implemented by electrolyte processes with fractal electrodes. Experimental results are analyzed in the frequency domain, and the pros and cons of adopting fractional-order electrical components for modelling these systems are compared.

  14. Integers without Large Prime Factors in Short Intervals: Conditional Results

    Indian Academy of Sciences (India)

    Goutam Pal; Satadal Ganguly

    2010-11-01

    Under the Riemann hypothesis and the conjecture that the order of growth of the argument of $(1/2+it)$ is bounded by $(\\log t)^{\\frac{1}{2}+o(1)}$, we show that for any given > 0 the interval $(X, X+\\sqrt{X}(\\log X)^{1/2+o(1)}]$ contains an integer having no prime factor exceeding $X^$ for all sufficiently large.

  15. Integer Sequences of the Form $\\alpha^n \\pm \\beta^n$

    CERN Document Server

    Abdulaziz, Abdulrahman Ali

    2010-01-01

    In this paper, we find all integer sequences of the form a^n + b^n, where a and b are complex numbers and n is a nonnegative integer. We prove that if p and q are integers, then there is a correspondence between the roots of the quadratic equation z^2 - pz - q = 0 and integer sequences of the form a^n + b^n. In addition, we will show that there are no integer sequences of the form a^n - b^n. Finally, we use special values of a and b to obtain a range of formulas involving Lucas and Fibonacci numbers.

  16. Partial Gr\\"obner bases for multiobjective integer programming

    CERN Document Server

    Blanco, Victor

    2007-01-01

    In this paper we present two new methodologies for solving multiobjective integer programming using tools from algebraic geometry. We introduce the concept of partial Gr\\"obner basis for a family of multiobjective programs where the right-hand side varies. This new structure extends the notion of usual Gr\\"obner basis for the single objective case, to the case of multiple objectives, i.e., a partial ordering instead of a total ordering over the feasible vectors. The main property of these bases is that partial reduction of the integer elements in the kernel of the constraint matrix by the different blocks of the basis is zero. It allows us to prove that this new construction is a test family for a family of multiobjective programs. An algorithm '\\`a la Buchberger' is developed to compute partial Gr\\"obner basis. Specifically, with this tool we compute the entire set of efficient solutions of any multiobjective integer linear problem (MOILP). Some examples illustrate the application of the algorithms and compu...

  17. Efficient Big Integer Multiplication and Squaring Algorithms for Cryptographic Applications

    Directory of Open Access Journals (Sweden)

    Shahram Jahani

    2014-01-01

    Full Text Available Public-key cryptosystems are broadly employed to provide security for digital information. Improving the efficiency of public-key cryptosystem through speeding up calculation and using fewer resources are among the main goals of cryptography research. In this paper, we introduce new symbols extracted from binary representation of integers called Big-ones. We present a modified version of the classical multiplication and squaring algorithms based on the Big-ones to improve the efficiency of big integer multiplication and squaring in number theory based cryptosystems. Compared to the adopted classical and Karatsuba multiplication algorithms for squaring, the proposed squaring algorithm is 2 to 3.7 and 7.9 to 2.5 times faster for squaring 32-bit and 8-Kbit numbers, respectively. The proposed multiplication algorithm is also 2.3 to 3.9 and 7 to 2.4 times faster for multiplying 32-bit and 8-Kbit numbers, respectively. The number theory based cryptosystems, which are operating in the range of 1-Kbit to 4-Kbit integers, are directly benefited from the proposed method since multiplication and squaring are the main operations in most of these systems.

  18. Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

    Directory of Open Access Journals (Sweden)

    Lauri Koskinen

    2012-06-01

    Full Text Available This paper presents the first known timing-error detection (TED microprocessor able to operate in subthreshold. Since the minimum energy point (MEP of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV.

  19. Global identification of target recognition and cleavage by the Microprocessor in human ES cells.

    Science.gov (United States)

    Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

    2014-11-10

    The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein-RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3' overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells.

  20. Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems.

    Science.gov (United States)

    Rhee, Minsoung; Burns, Mark A

    2009-11-07

    We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.

  1. Bleimann, Butzer, and Hahn Operators Based on the -Integers

    Directory of Open Access Journals (Sweden)

    Doğru Ogün

    2007-01-01

    Full Text Available We give a new generalization of Bleimann, Butzer, and Hahn operators, which includes -integers. We investigate uniform approximation of these new operators on some subspace of bounded and continuous functions. In Section, we show that the rates of convergence of the new operators in uniform norm are better than the classical ones. We also obtain a pointwise estimation in a general Lipschitz-type maximal function space. Finally, we define a generalization of these new operators and study the uniform convergence of them.

  2. Gaps and the exponent of convergence of an integer sequence

    CERN Document Server

    Grekos, Georges; Sleziak, Martin

    2012-01-01

    Professor Tibor \\v{S}al\\'at, at one of his seminars at Comenius University, Bratislava, asked to study the influence of gaps of an integer sequence A={a_1

  3. Efficient Reversible Watermarking Using Differential Expansible Integer Wavelet Transform

    Directory of Open Access Journals (Sweden)

    Sanjay Patel

    2016-07-01

    Full Text Available Digital watermarking has been utilized widely to claim the ownership and to protect images from alternation. Reversible watermarking is having great importance as it provided original image and the embedded logo without any loss. This paper proposed reversible watermarking algorithm using integer wavelet transform to satisfy the reversibility requirement. Further difference expansion based lifting scheme is used to make algorithm fast. To show the robustness of algorithm, various attacks like noise, rotating/scaling an image and filtering to the watermarked image is employed. The extraction of original image against such attacks is quantified in terms of peak signal to noise ratio (PSNR

  4. Integer Valued Autoregressive Models for Tipping Bucket Rainfall Measurements

    DEFF Research Database (Denmark)

    Thyregod, Peter; Carstensen, Niels Jacob; Madsen, Henrik

    1999-01-01

    A new method for modelling the dynamics of rain sampled by a tipping bucket rain gauge is proposed. The considered models belong to the class of integer valued autoregressive processes. The models take the autocorelation and discrete nature of the data into account. A first order, a second order...... and a threshold model are presented together with methods to estimate the parameters of each model. The models are demonstrated to provide a good description of dt from actual rain events requiring only two to four parameters....

  5. Integer programming for the generalized high school timetabling problem

    DEFF Research Database (Denmark)

    Kristiansen, Simon; Sørensen, Matias; Stidsen, Thomas Riis

    2015-01-01

    Recently, the XHSTT format for high school timetabling was introduced. It provides a uniform way of modeling problem instances and corresponding solutions. The format supports a wide variety of constraints, and currently 38 real-life instances from 11 different countries are available. Thereby......, the XHSTT format serves as a common ground for researchers within this area. This paper describes the first exact method capable of handling an arbitrary instance of the XHSTT format. The method is based on a mixed-integer linear programming (MIP) model, which is solved in two steps with a commercial...

  6. Integer least-squares theory for the GNSS compass

    Science.gov (United States)

    Teunissen, P. J. G.

    2010-07-01

    Global navigation satellite system (GNSS) carrier phase integer ambiguity resolution is the key to high-precision positioning and attitude determination. In this contribution, we develop new integer least-squares (ILS) theory for the GNSS compass model, together with efficient integer search strategies. It extends current unconstrained ILS theory to the nonlinearly constrained case, an extension that is particularly suited for precise attitude determination. As opposed to current practice, our method does proper justice to the a priori given information. The nonlinear baseline constraint is fully integrated into the ambiguity objective function, thereby receiving a proper weighting in its minimization and providing guidance for the integer search. Different search strategies are developed to compute exact and approximate solutions of the nonlinear constrained ILS problem. Their applicability depends on the strength of the GNSS model and on the length of the baseline. Two of the presented search strategies, a global and a local one, are based on the use of an ellipsoidal search space. This has the advantage that standard methods can be applied. The global ellipsoidal search strategy is applicable to GNSS models of sufficient strength, while the local ellipsoidal search strategy is applicable to models for which the baseline lengths are not too small. We also develop search strategies for the most challenging case, namely when the curvature of the non-ellipsoidal ambiguity search space needs to be taken into account. Two such strategies are presented, an approximate one and a rigorous, somewhat more complex, one. The approximate one is applicable when the fixed baseline variance matrix is close to diagonal. Both methods make use of a search and shrink strategy. The rigorous solution is efficiently obtained by means of a search and shrink strategy that uses non-quadratic, but easy-to-evaluate, bounding functions of the ambiguity objective function. The theory

  7. Bayesian integer frequency offset estimator for MIMO-OFDM systems

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Carrier frequency offset (CFO) in MIMO-OFDM systems can be decoupled into two parts: fraction frequency offset (FFO) and integer frequency offset (IFO). The problem of IFO estimation is addressed and a new IFO estimator based on the Bayesian philosophy is proposed. Also, it is shown that the Bayesian IFO estimator is optimal among all the IFO estimators. Furthermore, the Bayesian estimator can take advantage of oversampling so that better performance can be obtained. Finally, numerical results show the optimality of the Bayesian estimator and validate the theoretical analysis.

  8. Using Set Model for Learning Addition of Integers

    Directory of Open Access Journals (Sweden)

    Umi Puji Lestari

    2015-07-01

    Full Text Available This study aims to investigate how set model can help students' understanding of addition of integers in fourth grade. The study has been carried out to 23 students and a teacher of IVC SD Iba Palembang in January 2015. This study is a design research that also promotes PMRI as the underlying design context and activity. Results showed that the use of set models that is packaged in activity of recording of financial transactions in two color chips and card game can help students to understand the concept of zero pair, addition with the same colored chips, and cancellation strategy.

  9. Gaussian free fields at the integer quantum Hall plateau transition

    Energy Technology Data Exchange (ETDEWEB)

    Bondesan, R., E-mail: roberto.bondesan@phys.ox.ac.uk [Rudolf Peierls Centre for Theoretical Physics, 1 Keble Road, Oxford OX1 3NP (United Kingdom); Wieczorek, D.; Zirnbauer, M.R. [Institut für Theoretische Physik, Universität zu Köln, Zülpicher Straße 77, 50937 Köln (Germany)

    2017-05-15

    In this work we put forward an effective Gaussian free field description of critical wavefunctions at the transition between plateaus of the integer quantum Hall effect. To this end, we expound our earlier proposal that powers of critical wave intensities prepared via point contacts behave as pure scaling fields obeying an Abelian operator product expansion. Our arguments employ the framework of conformal field theory and, in particular, lead to a multifractality spectrum which is parabolic. We also derive a number of old and new identities that hold exactly at the lattice level and hinge on the correspondence between the Chalker–Coddington network model and a supersymmetric vertex model.

  10. $W_{\\infty}$ algebra in the integer quantum Hall effects

    OpenAIRE

    Azuma, Hiroo

    1994-01-01

    We investigate the $W_{\\infty}$ algebra in the integer quantum Hall effects. Defining the simplest vacuum, the Dirac sea, we evaluate the central extension for this algebra. A new algebra which contains the central extension is called the $W_{1+\\infty}$ algebra. We show that this $W_{1+\\infty}$ algebra is an origin of the Kac-Moody algebra which determines the behavior of edge states of the system. We discuss the relation between the $W_{1+\\infty}$ algebra and the incompressibility of the int...

  11. COED Transactions, Vol. XI, No. 12, December 1979. Some Alternate Applications of Microprocessor Trainers in Support of Undergraduate Laboratories.

    Science.gov (United States)

    Mitchell, Eugene E., Ed.

    Ways are described for the use of a microprocessor trainer in undergraduate laboratories. Listed are microcomputer applications that have been used as demonstrations and which provide signals for other experiments which are not related to microprocessors. Information and figures are provided for methods to do the following: direct generation of…

  12. Microprocessor-Controlled Pulsed NQR Spectrometer for Automatic Acquisition of Zeeman Perturbed Nuclear Quadrupole Spin Echo Envelope Modulations (ZSEEM )

    Science.gov (United States)

    Reddy, Narsimha; Bhavsar, Arun; Narasimhan, P. T.

    1986-02-01

    A simple microprocessor-controlled pulsed NQR spectrometer system has been developed with the capability to acquire Zeeman perturbed spin echo envelope modulations (ZSEEM). The CPU of the system is based on the Intel Corporation 8085 A microprocessor. The performance of the spectrometer is illustrated with the presentation of ZSEEM spectra of NaClO3 and KClO3.

  13. Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

    Science.gov (United States)

    Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

    2017-04-01

    We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

  14. Optimization of Reciprocals and Square Roots on the i860 Microprocessor

    DEFF Research Database (Denmark)

    Sinclair, Robert

    1996-01-01

    The i860 microprocessor lacks both a divide and a square root instruction. The consequences of this for code involving many reciprocal square roots, such as many-body simulations involving Coulomb-like potentials, are discussed with a particular emphasis on high performance.......The i860 microprocessor lacks both a divide and a square root instruction. The consequences of this for code involving many reciprocal square roots, such as many-body simulations involving Coulomb-like potentials, are discussed with a particular emphasis on high performance....

  15. Distributed Microprocessor Automation Network for Synthesizing Radiotracers Used in Positron Emission Tomography [PET

    Science.gov (United States)

    Russell, J. A. G.; Alexoff, D. L.; Wolf, A. P.

    1984-09-01

    This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. (DT)

  16. Implementation of the Sun Position Calculation in the PDC-1 Control Microprocessor

    Science.gov (United States)

    Stallkamp, J. A.

    1984-01-01

    The several computational approaches to providing the local azimuth and elevation angles of the Sun as a function of local time and then the utilization of the most appropriate method in the PDC-1 microprocessor are presented. The full algorithm, the FORTRAN form, is felt to be very useful in any kind or size of computer. It was used in the PDC-1 unit to generate efficient code for the microprocessor with its floating point arithmetic chip. The balance of the presentation consists of a brief discussion of the tracking requirements for PPDC-1, the planetary motion equations from the first to the final version, and the local azimuth-elevation geometry.

  17. Neutron beam irradiation study of workload dependence of SER in a microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Michalak, Sarah E [Los Alamos National Laboratory; Graves, Todd L [Los Alamos National Laboratory; Hong, Ted [STANFORD; Ackaret, Jerry [IBM; Sonny, Rao [IBM; Subhasish, Mitra [STANFORD; Pia, Sanda [IBM

    2009-01-01

    It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

  18. An Integer Programming-based Local Search for Large-scale Maximal Covering Problems

    Directory of Open Access Journals (Sweden)

    Junha Hwang

    2011-02-01

    Full Text Available Maximal covering problem (MCP is classified as a linear integer optimization problem which can be effectively solved by integer programming technique. However, as the problem size grows, integerprogramming requires excessive time to get an optimal solution. This paper suggests a method for applying integer programming-based local search (IPbLS to solve large-scale maximal covering problems. IPbLS, which is a hybrid technique combining integer programming and local search, is a kind of local search using integer programming for neighbor generation. IPbLS itself is very effective for MCP. In addition, we improve the performance of IPbLS for MCP through problem reduction based on the current solution. Experimental results show that the proposed method considerably outperforms any other local search techniques and integer programming.

  19. BQP_p = PP for integer p > 2

    CERN Document Server

    Bebel, Joseph

    2011-01-01

    There's something really strange about quantum mechanics. It's not just that cats can be dead and alive at the same time, and that entanglement seems to violate the principle of locality; quantum mechanics seems to be what Aaronson calls "an island in theoryspace", because even slight perturbations to the theory of quantum mechanics seem to generate absurdities. In [Aar 04] and [Aar 05], he explores these perturbations and the corresponding absurdities in the context of computation. In particular, he shows that a quantum theory where the measurement probabilities are computed using p-norm instead of the standard 2-norm has the effect of blowing up the class BQP (the class of problems that can be efficiently solved on a quantum computer) to at least PP (the class of problems that can be solved in probabilistic polynomial time). He showed that PP \\subseteq BQP_p \\subseteq PSPACE for all constants p != 2, and that BQP_p = PP for even integers p > 2. Here, we show that this equality holds for all integers p > 2.

  20. Using Integer Programming for Airport Service Planning in Staff Scheduling

    Directory of Open Access Journals (Sweden)

    W.H. Ip

    2010-09-01

    Full Text Available Reliability and safety in flight is extremely necessary and that depend on the adoption of proper maintenance system. Therefore, it is essential for aircraft maintenance companies to perform the manpower scheduling efficiently. One of the objectives of this paper is to provide an Integer Programming approach to determine the optimal solutions to aircraft maintenance planning and scheduling and hence the planning and scheduling processes can become more efficient and effective. Another objective is to develop a set of computational schedules for maintenance manpower to cover all scheduled flights. In this paper, a sequential methodology consisting of 3 stages is proposed. They are initial maintenance demand schedule, the maintenance pairing and the maintenance group(s assignment. Since scheduling would split up into different stages, different mathematical techniques have been adopted to cater for their own problem characteristics. Microsoft Excel would be used. Results from the first stage and second stage would be inputted into integer programming model using Microsoft Excel Solver to find the optimal solution. Also, Microsoft Excel VBA is used for devising a scheduling system in order to reduce the manual process and provide a user friendly interface. For the results, all can be obtained optimal solution and the computation time is reasonable and acceptable. Besides, the comparison of the peak time and non-peak time is discussed.

  1. Integer Representations towards Efficient Counting in the Bit Probe Model

    DEFF Research Database (Denmark)

    Brodal, Gerth Stølting; Greve, Mark; Pandey, Vineet

    2011-01-01

    Abstract We consider the problem of representing numbers in close to optimal space and supporting increment, decrement, addition and subtraction operations efficiently. We study the problem in the bit probe model and analyse the number of bits read and written to perform the operations, both...... in the worst-case and in the average-case. A counter is space-optimal if it represents any number in the range [0,...,2 n  − 1] using exactly n bits. We provide a space-optimal counter which supports increment and decrement operations by reading at most n − 1 bits and writing at most 3 bits in the worst...... of the counter as the ratio between L + 1 and 2 n . We present various representations that achieve different trade-offs between the read and write complexities and the efficiency. We also give another representation of integers that uses n + O(logn ) bits to represent integers in the range [0,...,2 n  − 1...

  2. Optimal power system management via mixed integer dynamic programming

    Energy Technology Data Exchange (ETDEWEB)

    Kwatny, H.G.; Mensah, E. [Drexel Univ., Philadelphia, PA (United States). Dept. of Mechanical Engineering and Mechanics; Niebur, D. [Drexel Univ., Philadelphia, PA (United States). Dept. of Electrical and Computer Engineering; Teolis, C. [Techno-Sciences Inc., Lanham, MD (United States)

    2006-07-01

    Power systems are comprised of continuous and discrete acting components and subsystems. This paper discussed a logical specification that was used to define the transition dynamics of the discrete subsystem. It also presented a computational tool that reduced the logical specification to a set of inequalities as well as the use of the transformed model in a dynamic programming approach to the design of the optimal feedback controls. An example of optimal load shedding within a power system with an aggregate induction motor and constant admittance loads was presented. Specifically, the paper outlined the problem and discussed the modeling of hybrid systems and the control problem. A solution to the optimal control problem was presented. The essential feature of the model was the characterization of the discrete subsystem in terms of a set of mixed-integer formulas. The case example showed how logical constraints involving system real variables, such as case excitation voltage, could be incorporated in the problem via transformation to mixed-integer formulas. 10 refs., 4 figs.

  3. A virtual network mapping algorithm based on integer programming

    Institute of Scientific and Technical Information of China (English)

    Bo LU; Jian-ya CHEN; Hong-yan CUI; Tao HUANG; Yun-jie LIU

    2013-01-01

    The virtual network (VN) embedding/mapping problem is recognized as an essential question of network virtualiza-tion. The VN embedding problem is a major challenge in this field. Its target is to efficiently map the virtual nodes and virtual links onto the substrate network resources. Previous research focused on designing heuristic-based algorithms or attempting two-stage solutions by solving node mapping in the first stage and link mapping in the second stage. In this study, we propose a new VN embedding algorithm based on integer programming. We build a model of an augmented substrate graph, and formulate the VN embedding problem as an integer program with an objective function and some constraints. A factor of topology-awareness is added to the objective function. The VN embedding problem is solved in one stage. Simulation results show that our algorithm greatly enhances the acceptance ratio, and increases the revenue/cost (R/C) ratio and the revenue while decreasing the cost of the VN embedding problem.

  4. Direct comparison of fractional and integer quantized Hall resistance

    Science.gov (United States)

    Ahlers, Franz J.; Götz, Martin; Pierz, Klaus

    2017-08-01

    We present precision measurements of the fractional quantized Hall effect, where the quantized resistance {{R}≤ft[ 1/3 \\right]} in the fractional quantum Hall state at filling factor 1/3 was compared with a quantized resistance {{R}[2]} , represented by an integer quantum Hall state at filling factor 2. A cryogenic current comparator bridge capable of currents down to the nanoampere range was used to directly compare two resistance values of two GaAs-based devices located in two cryostats. A value of 1-(5.3  ±  6.3) 10-8 (95% confidence level) was obtained for the ratio ({{R}≤ft[ 1/3 \\right]}/6{{R}[2]} ). This constitutes the most precise comparison of integer resistance quantization (in terms of h/e 2) in single-particle systems and of fractional quantization in fractionally charged quasi-particle systems. While not relevant for practical metrology, such a test of the validity of the underlying physics is of significance in the context of the upcoming revision of the SI.

  5. Split diversity in constrained conservation prioritization using integer linear programming.

    Science.gov (United States)

    Chernomor, Olga; Minh, Bui Quang; Forest, Félix; Klaere, Steffen; Ingram, Travis; Henzinger, Monika; von Haeseler, Arndt

    2015-01-01

    Phylogenetic diversity (PD) is a measure of biodiversity based on the evolutionary history of species. Here, we discuss several optimization problems related to the use of PD, and the more general measure split diversity (SD), in conservation prioritization.Depending on the conservation goal and the information available about species, one can construct optimization routines that incorporate various conservation constraints. We demonstrate how this information can be used to select sets of species for conservation action. Specifically, we discuss the use of species' geographic distributions, the choice of candidates under economic pressure, and the use of predator-prey interactions between the species in a community to define viability constraints.Despite such optimization problems falling into the area of NP hard problems, it is possible to solve them in a reasonable amount of time using integer programming. We apply integer linear programming to a variety of models for conservation prioritization that incorporate the SD measure.We exemplarily show the results for two data sets: the Cape region of South Africa and a Caribbean coral reef community. Finally, we provide user-friendly software at http://www.cibiv.at/software/pda.

  6. An Approach to Integer Wavelet Transform for Medical Image Compression in PACS

    Institute of Scientific and Technical Information of China (English)

    2000-01-01

    We study an approach to integer wavelet transform for lossless compression of medical image in medical picture archiving and communication system (PACS). By lifting scheme a reversible integer wavelet transform is generated, which has the similar features with the corresponding biorthogonal wavelet transform. Experimental results of the method based on integer wavelet transform are given to show better performance and great applicable potentiality in medical image compression.

  7. An alternative approach to calculate the posterior probability of GNSS integer ambiguity resolution

    Science.gov (United States)

    Yu, Xianwen; Wang, Jinling; Gao, Wang

    2017-03-01

    When precise positioning is carried out via GNSS carrier phases, it is important to make use of the property that every ambiguity should be an integer. With the known float solution, any integer vector, which has the same degree of freedom as the ambiguity vector, is the ambiguity vector in probability. For both integer aperture estimation and integer equivariant estimation, it is of great significance to know the posterior probabilities. However, to calculate the posterior probability, we have to face the thorny problem that the equation involves an infinite number of integer vectors. In this paper, using the float solution of ambiguity and its variance matrix, a new approach to rapidly and accurately calculate the posterior probability is proposed. The proposed approach consists of four steps. First, the ambiguity vector is transformed via decorrelation. Second, the range of the adopted integer of every component is directly obtained via formulas, and a finite number of integer vectors are obtained via combination. Third, using the integer vectors, the principal value of posterior probability and the correction factor are worked out. Finally, the posterior probability of every integer vector and its error upper bound can be obtained. In the paper, the detailed process to calculate the posterior probability and the derivations of the formulas are presented. The theory and numerical examples indicate that the proposed approach has the advantages of small amount of computations, high calculation accuracy and strong adaptability.

  8. An alternative approach to calculate the posterior probability of GNSS integer ambiguity resolution

    Science.gov (United States)

    Yu, Xianwen; Wang, Jinling; Gao, Wang

    2016-10-01

    When precise positioning is carried out via GNSS carrier phases, it is important to make use of the property that every ambiguity should be an integer. With the known float solution, any integer vector, which has the same degree of freedom as the ambiguity vector, is the ambiguity vector in probability. For both integer aperture estimation and integer equivariant estimation, it is of great significance to know the posterior probabilities. However, to calculate the posterior probability, we have to face the thorny problem that the equation involves an infinite number of integer vectors. In this paper, using the float solution of ambiguity and its variance matrix, a new approach to rapidly and accurately calculate the posterior probability is proposed. The proposed approach consists of four steps. First, the ambiguity vector is transformed via decorrelation. Second, the range of the adopted integer of every component is directly obtained via formulas, and a finite number of integer vectors are obtained via combination. Third, using the integer vectors, the principal value of posterior probability and the correction factor are worked out. Finally, the posterior probability of every integer vector and its error upper bound can be obtained. In the paper, the detailed process to calculate the posterior probability and the derivations of the formulas are presented. The theory and numerical examples indicate that the proposed approach has the advantages of small amount of computations, high calculation accuracy and strong adaptability.

  9. Exact Discrete Analogs of Derivatives of Integer Orders: Differences as Infinite Series

    Directory of Open Access Journals (Sweden)

    Vasily E. Tarasov

    2015-01-01

    Full Text Available New differences of integer orders, which are connected with derivatives of integer orders not approximately, are proposed. These differences are represented by infinite series. A characteristic property of the suggested differences is that its Fourier series transforms have a power-law form. We demonstrate that the proposed differences of integer orders n are directly connected with the derivatives ∂n/∂xn. In contrast to the usual finite differences of integer orders, the suggested differences give the usual derivatives without approximation.

  10. Haar Wavelet Based Implementation Method of the Non–integer Order Differentiation and its Application to Signal Enhancement

    Directory of Open Access Journals (Sweden)

    Li Yuanlu

    2015-06-01

    Full Text Available Non–integer order differentiation is changing application of traditional differentiation because it can achieve a continuous interpolation of the integer order differentiation. However, implementation of the non–integer order differentiation is much more complex than that of integer order differentiation. For this purpose, a Haar wavelet-based implementation method of non–integer order differentiation is proposed. The basic idea of the proposed method is to use the operational matrix to compute the non–integer order differentiation of a signal through expanding the signal by the Haar wavelets and constructing Haar wavelet operational matrix of the non–integer order differentiation. The effectiveness of the proposed method was verified by comparison of theoretical results and those obtained by another non–integer order differential filtering method. Finally, non–integer order differentiation was applied to enhance signal.

  11. Microcprocessing Computer Technician, Digital and Microprocessor Technician Program. Post-Graduate 5th Year.

    Science.gov (United States)

    Carangelo, Pasquale R.; Janeczek, Anthony J.

    Materials are provided for a two-semester digital and microprocessor technician postgraduate program. Prerequisites stated for the program include a background in DC and AC theory, solid state devices, basic circuit fundamentals, and basic math. A chronology of major topics and a listing of course objectives appear first. Theory outlines for each…

  12. An Ill-Structured PBL-Based Microprocessor Course without Formal Laboratory

    Science.gov (United States)

    Kim, Jungkuk

    2012-01-01

    This paper introduces a problem-based learning (PBL) microprocessor application course designed according to the following strategies: 1) hands-on training without having a formal laboratory, and 2) intense student-centered cooperative learning through an ill-structured problem. PBL was adopted as the core educational technique of the course to…

  13. Optimalisatie van de sulfaatbepaling met bariumdimethylsulfonazo(III) in een microprocessor gestuurd flowinjectiesysteem

    NARCIS (Netherlands)

    Staden; J.J.van

    1984-01-01

    Uit een aantal methoden voor de bepaling van sulfaat in doorstroomsystemen is een methode geselecteerd om hieruit een flowinjectiesysteem dat met een microprocessor gestuurd kan worden te ontwikkelen. Gekozen werd voor een methode met bariumdimethylsulfonazo(III), omdat deze methode relatief st

  14. A microprocessor based, multi-channel low-temperature monitoring system

    NARCIS (Netherlands)

    Kuiper, B.W.; Dijk, van M.H.H.

    1982-01-01

    A multi-channel low-temperature monitoring system and its design considerations are presented. The system is microprocessor based and specially designed to interface thermoresistive sensors in cryogenic experiments. The system can be easily expanded to accept any type of physical transducer and to p

  15. Cell cycle-dependent regulation of Aurora kinase B mRNA by the Microprocessor complex.

    Science.gov (United States)

    Jung, Eunsun; Seong, Youngmo; Seo, Jae Hong; Kwon, Young-Soo; Song, Hoseok

    2014-03-28

    Aurora kinase B regulates the segregation of chromosomes and the spindle checkpoint during mitosis. In this study, we showed that the Microprocessor complex, which is responsible for the processing of the primary transcripts during the generation of microRNAs, destabilizes the mRNA of Aurora kinase B in human cells. The Microprocessor-mediated cleavage kept Aurora kinase B at a low level and prevented premature entrance into mitosis. The cleavage was reduced during mitosis leading to the accumulation of Aurora kinase B mRNA and protein. In addition to Aurora kinase B mRNA, the processing of other primary transcripts of miRNAs were also decreased during mitosis. We found that the cleavage was dependent on an RNA helicase, DDX5, and the association of DDX5 and DDX17 with the Microprocessor was reduced during mitosis. Thus, we propose a novel mechanism by which the Microprocessor complex regulates stability of Aurora kinase B mRNA and cell cycle progression.

  16. Coed Transactions, Vol. XI, No. 1, January 1979. Microprocessor Course Development Equipment Selection.

    Science.gov (United States)

    Mitchell, Eugene E., Ed.; Leventhal, Lance A.

    Many devices and systems related to microprocessors are available on the marketplace. The author suggests that criteria for selecting and designing workstations and development systems are necessary. Seventeen important factors of designing workstations and six desirable features of a development system are presented. The kinds of places in which…

  17. Establishment of cells to monitor Microprocessor through fusion genes of microRNA and GFP.

    Science.gov (United States)

    Tsutsui, Motomu; Hasegawa, Hitoki; Adachi, Koichi; Miyata, Maiko; Huang, Peng; Ishiguro, Naoki; Hamaguchi, Michinari; Iwamoto, Takashi

    2008-08-08

    Microprocessor, the complex of Drosha and DGCR8, promotes the processing of primary microRNA to precursor microRNA, which is a crucial step for microRNA maturation. So far, no convenient assay systems have been developed for observing this step in vivo. Here we report the establishment of highly sensitive cellular systems where we can visually monitor the function of Microprocessor. During a series of screening of transfectants with fusion genes of the EGFP cDNA and primary microRNA genes, we have obtained certain cell lines where introduction of siRNA against DGCR8 or Drosha strikingly augments GFP signals. In contrast, these cells have not responded to Dicer siRNA; thus they have a unique character that GFP signals should be negatively and specifically correlated to the action of Microprocessor among biogenesis of microRNA. These cell lines can be useful tools for real-time analysis of Microprocessor action in vivo and identifying its novel modulators.

  18. Receipt of Input Signal Amplitudes in Microprocessor Protection of Electrical Installations

    Directory of Open Access Journals (Sweden)

    F. A. Romaniuk

    2006-01-01

    Full Text Available Frequency-independent methods for receipt of input signal amplitudes in microprocessor protection of an electrical installation in the aggregate with earlier analyzed digital filters are considered in the paper. The paper contains comparative analysis and specified characteristics have been obtained.

  19. The design of an asynchronous Tiny RISC TM/TR4101 microprocessor core

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jensen, P.; Korger, P.

    1998-01-01

    This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper repo...

  20. INVESTIGATION OF MICROPROCESSOR TRANSFORMER CURRENT PROTECTION IN SHORT CIRCUIT FAULT MODES

    Directory of Open Access Journals (Sweden)

    M. S. Loman

    2014-01-01

    Full Text Available The paper presents an investigation on transformer current protection with blocking against magnetizing inrush current in short circuit fault modes. It has been shown that the proposed magnetizing in-rush current blocking algorithm can be implemented in microprocessor current protections of transformers.

  1. Quantum Field-Theory in Non-Integer Dimensions.

    Science.gov (United States)

    Eyink, Gregory Lawrence

    In a 1973 paper entitled "Quantum Field-Theory Models in Less Than 4 Dimensions," Kenneth G. Wilson studied field-theories for spacetime dimension d between 2 and 4. With unconventional renormalizations, these models were found to have non-Gaussian ultraviolet renormalization group fixed points. Wilson's method was perturbative "dimensional regularization": the Feynman-graph integrals were analytically continued to non-integer d. His work left open the question of the nonperturbative existence of the models. Since that landmark paper, Yuval Gefen, Amnon Aharony and Benoit B. Mandelbrot have shown that Ising spin models on fractal lattices have critical properties like those predicted for non-integer dimensions by the analytic continuation, or "varepsilon-expansion," method. Our work shows that fractal lattices and continua provide also a nonperturbative definition of field-theories in non-integer dimensions. The fractal point-sets employed are the Sierpinski carpets and their higher-dimensional generalizations. This class of point-sets has a tunable dimension which allows the approach to four from below. Furthermore, the carpets have discrete groups of scale or dilation invariances and infinite order of ramification. A class of scalar field models are defined on these sets which should reduce to the standard models when dnearrow4. The propagator for these models is given by a proper-time or heat-kernel representation. For this propagator, reflection -positivity is established, a general scaling law is conjectured (and established in a special case), and the perturbative renormalizability shown to be governed by the spectral dimensionality. Scalar models with another choice of propagator, the hierarchical propagator, are studied by rigorous renormalization -group methods. Both massless and massive solutions with non-Gaussian ultraviolet fixed points are mathematically constructed. The definition of higher-spin fields, gauge and fermion fields, on fractal spacetimes

  2. New Integer Programming Formulations of the Generalized Travelling Salesman Problem

    Directory of Open Access Journals (Sweden)

    P. C. Pop

    2007-01-01

    Full Text Available The Generalized Travelling Salesman Problem, denoted by GTSP, is a variant of the classical travelling salesman problem (TSP, in which the nodes of an undirected graph are partitioned into node sets (clusters and the salesman has to visit exactly one node from every cluster. In this paper we described six distinct formulations of the GTSP as an integer programming. Apart from the standard formulations all the new formulations that we describe are 'compact' in the sense that the number of constraints and variables is a polynomial function of the number of nodes in the problem. In order to provide compact formulations for the GTSP we used two approaches using auxiliary flow variables beyond the natural binary edge and node variables and the second one by distinguishing between global and local variables. Comparisons of the polytopes corresponding to their linear relaxations are established.

  3. Non-chiral 2d CFT with integer energy levels

    Science.gov (United States)

    Ashrafi, M.; Loran, F.

    2016-09-01

    The partition function of 2d conformal field theory is a modular invariant function. It is known that the partition function of a holomorphic CFT whose central charge is a multiple of 24 is a polynomial in the Klein function. In this paper, by using the medium temperature expansion we show that every modular invariant partition function can be mapped to a holomorphic partition function whose structure can be determined similarly. We use this map to study partition function of CFTs with half-integer left and right conformal weights. We show that the corresponding left and right central charges are necessarily multiples of 4. Furthermore, the degree of degeneracy of high-energy levels can be uniquely determined in terms of the degeneracy in the low energy states.

  4. Non-chiral 2d CFT with integer energy levels

    CERN Document Server

    Ashrafi, M

    2016-01-01

    The partition function of 2d conformal field theory is a modular invariant function. It is known that the partition function of a holomorphic CFT whose central charge is a multiple of 24 is a polynomial in the Klein function. In this paper, by using the medium temperature expansion we show that every modular invariant partition function can be mapped to a holomorphic partition function whose structure can be determined similarly. We use this map to study partition function of CFTs with half-integer left and right conformal weights. We show that the corresponding left and right central charges are necessarily multiples of 4. Furthermore, the degree of degeneracy of high-energy levels can be uniquely determined in terms of the degeneracy in the low energy states.

  5. Analytical estimation of the correlation dimension of integer lattices

    Energy Technology Data Exchange (ETDEWEB)

    Lacasa, Lucas, E-mail: l.lacasa@qmul.ac.uk [School of Mathematical Sciences, Queen Mary University of London, Mile End Road, E14NS London (United Kingdom); Gómez-Gardeñes, Jesús, E-mail: gardenes@gmail.com [Institute for Biocomputation and Physics of Complex System (BIFI), Universidad de Zaragoza, Zaragoza (Spain); Departamento de Fisica de la Materia Condensada, Universidad de Zaragoza, Zaragoza (Spain)

    2014-12-01

    Recently [L. Lacasa and J. Gómez-Gardeñes, Phys. Rev. Lett. 110, 168703 (2013)], a fractal dimension has been proposed to characterize the geometric structure of networks. This measure is an extension to graphs of the so called correlation dimension, originally proposed by Grassberger and Procaccia to describe the geometry of strange attractors in dissipative chaotic systems. The calculation of the correlation dimension of a graph is based on the local information retrieved from a random walker navigating the network. In this contribution, we study such quantity for some limiting synthetic spatial networks and obtain analytical results on agreement with the previously reported numerics. In particular, we show that up to first order, the correlation dimension β of integer lattices ℤ{sup d} coincides with the Haussdorf dimension of their coarsely equivalent Euclidean spaces, β = d.

  6. Integer programming model for optimizing bus timetable using genetic algorithm

    Science.gov (United States)

    Wihartiko, F. D.; Buono, A.; Silalahi, B. P.

    2017-01-01

    Bus timetable gave an information for passengers to ensure the availability of bus services. Timetable optimal condition happened when bus trips frequency could adapt and suit with passenger demand. In the peak time, the number of bus trips would be larger than the off-peak time. If the number of bus trips were more frequent than the optimal condition, it would make a high operating cost for bus operator. Conversely, if the number of trip was less than optimal condition, it would make a bad quality service for passengers. In this paper, the bus timetabling problem would be solved by integer programming model with modified genetic algorithm. Modification was placed in the chromosomes design, initial population recovery technique, chromosomes reconstruction and chromosomes extermination on specific generation. The result of this model gave the optimal solution with accuracy 99.1%.

  7. Parallel Matrix Implementation of an Integer Division Algorithm Using FPGA

    Directory of Open Access Journals (Sweden)

    Eshwararao. Boddepalli

    2011-12-01

    Full Text Available This paper presents a method for fast, parallel matrix implementation of an integer division algorithm inside FPGA that can be used for real-time control systems. An essential improvement over the known matrix structure was made, with all the matrix lines having the same width which leads to equal and reduced propagation time. The alignment was also improved by reducing one algorithm step and eliminating one matrix line. Both fully combinational and pipelined versions of the algorithm were designed and tested until a functional physical implementation was obtained, including a user interface. The paper also presents new way to implement hardware structures inside programmable circuits, using portable schematic design from “Altium Designer” software environment instead textual description with HDL languages

  8. Three-Dimensional Image Compression With Integer Wavelet Transforms

    Science.gov (United States)

    Bilgin, Ali; Zweig, George; Marcellin, Michael W.

    2000-04-01

    A three-dimensional (3-D) image-compression algorithm based on integer wavelet transforms and zerotree coding is presented. The embedded coding of zerotrees of wavelet coefficients (EZW) algorithm is extended to three dimensions, and context-based adaptive arithmetic coding is used to improve its performance. The resultant algorithm, 3-D CB-EZW, efficiently encodes 3-D image data by the exploitation of the dependencies in all dimensions, while enabling lossy and lossless decompression from the same bit stream. Compared with the best available two-dimensional lossless compression techniques, the 3-D CB-EZW algorithm produced averages of 22%, 25%, and 20% decreases in compressed file sizes for computed tomography, magnetic resonance, and Airborne Visible Infrared Imaging Spectrometer images, respectively. The progressive performance of the algorithm is also compared with other lossy progressive-coding algorithms.

  9. An Optimal Decision Procedure for MPNL over the Integers

    Directory of Open Access Journals (Sweden)

    Davide Bresolin

    2011-06-01

    Full Text Available Interval temporal logics provide a natural framework for qualitative and quantitative temporal reason- ing over interval structures, where the truth of formulae is defined over intervals rather than points. In this paper, we study the complexity of the satisfiability problem for Metric Propositional Neigh- borhood Logic (MPNL. MPNL features two modalities to access intervals "to the left" and "to the right" of the current one, respectively, plus an infinite set of length constraints. MPNL, interpreted over the naturals, has been recently shown to be decidable by a doubly exponential procedure. We improve such a result by proving that MPNL is actually EXPSPACE-complete (even when length constraints are encoded in binary, when interpreted over finite structures, the naturals, and the in- tegers, by developing an EXPSPACE decision procedure for MPNL over the integers, which can be easily tailored to finite linear orders and the naturals (EXPSPACE-hardness was already known.

  10. Some locally self-interacting walks on the integers

    CERN Document Server

    Erschler, Anna; Werner, Wendelin

    2010-01-01

    We study certain self-interacting walks on the set of integers, that choose to jump to the right or to the left randomly but influenced by the number of times they have previously jumped along the edges in the finite neighbourhood of their current position (in the present paper, typically, we will discuss the case where one considers the neighbouring edges and the next-to-neighbouring edges). We survey a variety of possible behaviours, including some where the walk is eventually confined to an interval of large length. We also focus on certain "asymmetric" drifts, where we prove that with positive probability, the walks behave deterministically on large scale and move like a constant times the square root of time, or like a constant times the logarithm of time.

  11. $\\sigma$-Set Theory and the Integer Space

    CERN Document Server

    Araus, Ivan Gatica

    2009-01-01

    In this article we develop an alternative theory to the ZF Set Theory called $\\sigma$-Set Theory. The goal of this theory is to build the Integer Space $3^{X}$, that will be the algebraic completion of the Power Set $2^{X}$, i.e., $3^{X}$ contains the inverse element for the union, that in this case we call fusion. We first give an introduction where we explain in a more detailed way the motivations and the objectives of this new theory. Later we present the language of the theory that will be the same as that of the Set Theory. Finally, we present the axioms of the $\\sigma$-Set Theory and their individual analysis.

  12. Developing optimal nurses work schedule using integer programming

    Science.gov (United States)

    Shahidin, Ainon Mardhiyah; Said, Mohd Syazwan Md; Said, Noor Hizwan Mohamad; Sazali, Noor Izatie Amaliena

    2017-08-01

    Time management is the art of arranging, organizing and scheduling one's time for the purpose of generating more effective work and productivity. Scheduling is the process of deciding how to commit resources between varieties of possible tasks. Thus, it is crucial for every organization to have a good work schedule for their staffs. The job of Ward nurses at hospitals runs for 24 hours every day. Therefore, nurses will be working using shift scheduling. This study is aimed to solve the nurse scheduling problem at an emergency ward of a private hospital. A 7-day work schedule for 7 consecutive weeks satisfying all the constraints set by the hospital will be developed using Integer Programming. The work schedule for the nurses obtained gives an optimal solution where all the constraints are being satisfied successfully.

  13. Designing Networks: A Mixed-Integer Linear Optimization Approach

    CERN Document Server

    Gounaris, Chrysanthos E; Kevrekidis, Ioannis G; Floudas, Christodoulos A

    2015-01-01

    Designing networks with specified collective properties is useful in a variety of application areas, enabling the study of how given properties affect the behavior of network models, the downscaling of empirical networks to workable sizes, and the analysis of network evolution. Despite the importance of the task, there currently exists a gap in our ability to systematically generate networks that adhere to theoretical guarantees for the given property specifications. In this paper, we propose the use of Mixed-Integer Linear Optimization modeling and solution methodologies to address this Network Generation Problem. We present a number of useful modeling techniques and apply them to mathematically express and constrain network properties in the context of an optimization formulation. We then develop complete formulations for the generation of networks that attain specified levels of connectivity, spread, assortativity and robustness, and we illustrate these via a number of computational case studies.

  14. Self-Avoiding Random Dynamics on Integer Complex Systems

    CERN Document Server

    Hamze, Firas; de Freitas, Nando

    2011-01-01

    This paper introduces a new specialized algorithm for equilibrium Monte Carlo sampling of binary-valued systems, which allows for large moves in the state space. This is achieved by constructing self-avoiding walks (SAWs) in the state space. As a consequence, many bits are flipped in a single MCMC step. We name the algorithm SARDONICS, an acronym for Self-Avoiding Random Dynamics on Integer Complex Systems. The algorithm has several free parameters, but we show that Bayesian optimization can be used to automatically tune them. SARDONICS performs remarkably well in a broad number of sampling tasks: toroidal ferromagnetic and frustrated Ising models, 3D Ising models, restricted Boltzmann machines and chimera graphs arising in the design of quantum computers.

  15. An Integer Programming Approach to Solving Tantrix on Fixed Boards

    Directory of Open Access Journals (Sweden)

    Yushi Uno

    2012-03-01

    Full Text Available Tantrix (Tantrix R ⃝ is a registered trademark of Colour of Strategy Ltd. in New Zealand, and of TANTRIX JAPAN in Japan, respectively, under the license of M. McManaway, the inventor. is a puzzle to make a loop by connecting lines drawn on hexagonal tiles, and the objective of this research is to solve it by a computer. For this purpose, we first give a problem setting of solving Tantrix as making a loop on a given fixed board. We then formulate it as an integer program by describing the rules of Tantrix as its constraints, and solve it by a mathematical programming solver to have a solution. As a result, we establish a formulation that can solve Tantrix of moderate size, and even when the solutions are invalid only by elementary constraints, we achieved it by introducing additional constraints and re-solve it. By this approach we succeeded to solve Tantrix of size up to 60.

  16. Steganography Based on Integer Wavelet Transform and Bicubic Interpolation

    Directory of Open Access Journals (Sweden)

    N. Ajeeshvali

    2012-11-01

    Full Text Available Steganography is the art and science of hiding information in unremarkable cover media so as not to observe any suspicion. It is an application under information security field, being classified under information security, Steganography will be characterized by having set of measures that rely on strengths and counter attacks that are caused by weaknesses and vulnerabilities. The aim of this paper is to propose a modified high capacity image steganography technique that depends on integer wavelet transform with acceptable levels of imperceptibility and distortion in the cover image as a medium file and high levels of security. Bicubic interpolation causes overshoot, which increases acutance (apparent sharpness. The Bicubic algorithm is frequently used for scaling images and video for display. The algorithm preserves fine details of the image better than the common bilinear algorithm.

  17. An integer linear programming for a comprehensive reverse supply chain

    Directory of Open Access Journals (Sweden)

    Hoda Mahmoudi

    2014-12-01

    Full Text Available Reverse supply chain is a cycle of recovery for the products and materials used by the customers but can be returned to the chain performing some operations. Due to significance of reverse supply chain in the content of environmental and economical aspects, we formulate a mathematical model of reverse multi-layer multi-product supply chain for minimizing the total costs including returning, disassembly, processing, recycling, remanufacturing, and distribution centers. The presented model is an integer linear programming model being solved using Lingo 9 software. Numerical experiments are conducted to gain insight into the proposed model. The solutions provide a decision aid stream strengthening the concept of reverse supply network design and analysis for profit-making organization.

  18. The transport mechanism of the integer quantum Hall effect

    CERN Document Server

    LiMing, W

    2016-01-01

    The integer quantum Hall effect is analysed using a transport mechanism with a semi-classic wave packages of electrons in this paper. A strong magnetic field perpendicular to a slab separates the electron current into two branches with opposite wave vectors $({\\it k})$ and locating at the two edges of the slab, respectively, along the current. In this case back scattering of electrons ($k\\rightarrow -k$) is prohibited by the separation of electron currents. Thus the slab exhibits zero longitudinal resistance and plateaus of Hall resistance. When the Fermi level is scanning over a Landau level when the magnetic field increases, however, the electron waves locate around the central axis of the slab and overlap each other thus back scattering of electrons takes place frequently. Then longitudinal resistance appears and the Hall resistance goes up from one plateau to a new plateau.

  19. Distributing Earthquakes Among California's Faults: A Binary Integer Programming Approach

    Science.gov (United States)

    Geist, E. L.; Parsons, T.

    2016-12-01

    Statement of the problem is simple: given regional seismicity specified by a Gutenber-Richter (G-R) relation, how are earthquakes distributed to match observed fault-slip rates? The objective is to determine the magnitude-frequency relation on individual faults. The California statewide G-R b-value and a-value are estimated from historical seismicity, with the a-value accounting for off-fault seismicity. UCERF3 consensus slip rates are used, based on geologic and geodetic data and include estimates of coupling coefficients. The binary integer programming (BIP) problem is set up such that each earthquake from a synthetic catalog spanning millennia can occur at any location along any fault. The decision vector, therefore, consists of binary variables, with values equal to one indicating the location of each earthquake that results in an optimal match of slip rates, in an L1-norm sense. Rupture area and slip associated with each earthquake are determined from a magnitude-area scaling relation. Uncertainty bounds on the UCERF3 slip rates provide explicit minimum and maximum constraints to the BIP model, with the former more important to feasibility of the problem. There is a maximum magnitude limit associated with each fault, based on fault length, providing an implicit constraint. Solution of integer programming problems with a large number of variables (>105 in this study) has been possible only since the late 1990s. In addition to the classic branch-and-bound technique used for these problems, several other algorithms have been recently developed, including pre-solving, sifting, cutting planes, heuristics, and parallelization. An optimal solution is obtained using a state-of-the-art BIP solver for M≥6 earthquakes and California's faults with slip-rates > 1 mm/yr. Preliminary results indicate a surprising diversity of on-fault magnitude-frequency relations throughout the state.

  20. Mixed Integer Programming and Heuristic Scheduling for Space Communication

    Science.gov (United States)

    Lee, Charles H.; Cheung, Kar-Ming

    2013-01-01

    Optimal planning and scheduling for a communication network was created where the nodes within the network are communicating at the highest possible rates while meeting the mission requirements and operational constraints. The planning and scheduling problem was formulated in the framework of Mixed Integer Programming (MIP) to introduce a special penalty function to convert the MIP problem into a continuous optimization problem, and to solve the constrained optimization problem using heuristic optimization. The communication network consists of space and ground assets with the link dynamics between any two assets varying with respect to time, distance, and telecom configurations. One asset could be communicating with another at very high data rates at one time, and at other times, communication is impossible, as the asset could be inaccessible from the network due to planetary occultation. Based on the network's geometric dynamics and link capabilities, the start time, end time, and link configuration of each view period are selected to maximize the communication efficiency within the network. Mathematical formulations for the constrained mixed integer optimization problem were derived, and efficient analytical and numerical techniques were developed to find the optimal solution. By setting up the problem using MIP, the search space for the optimization problem is reduced significantly, thereby speeding up the solution process. The ratio of the dimension of the traditional method over the proposed formulation is approximately an order N (single) to 2*N (arraying), where N is the number of receiving antennas of a node. By introducing a special penalty function, the MIP problem with non-differentiable cost function and nonlinear constraints can be converted into a continuous variable problem, whose solution is possible.

  1. Item Pool Construction Using Mixed Integer Quadratic Programming (MIQP). GMAC® Research Report RR-14-01

    Science.gov (United States)

    Han, Kyung T.; Rudner, Lawrence M.

    2014-01-01

    This study uses mixed integer quadratic programming (MIQP) to construct multiple highly equivalent item pools simultaneously, and compares the results from mixed integer programming (MIP). Three different MIP/MIQP models were implemented and evaluated using real CAT item pool data with 23 different content areas and a goal of equal information…

  2. Sabrewing: a lightweight architecture for combined floating-point and integer arithmetic

    NARCIS (Netherlands)

    Bruintjes, Tom M.; Walters, Karel H.G.; Gerez, Sabih H.; Molenkamp, Bert; Smit, Gerard J.M.

    2012-01-01

    In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in contemporar

  3. Optimized Waterspace Management and Scheduling Using Mixed-Integer Linear Programming

    Science.gov (United States)

    2016-01-01

    TECHNICAL REPORT NSWC PCD TR 2015-003 OPTIMIZED WATERSPACE MANAGEMENT AND SCHEDULING USING MIXED-INTEGER LINEAR PROGRAMMING...constraints required for the mathematical formulation of the MCM scheduling problem pertaining to the survey constraints and logistics management . The...Floudas, Nonlinear and Mixed-Integer Optimization: Fundamentals and Applications, Oxford University Press, 1995. [10] M. J. Bays, A. Shende, D. J

  4. On the series of the reciprocals lcm's of sequences of positive integers: A curious interpretation

    CERN Document Server

    Farhi, Bakir

    2009-01-01

    In this paper, we prove the following result: {quote} Let $\\A$ be an infinite set of positive integers. For all positive integer $n$, let $\\tau_n$ denote the smallest element of $\\A$ which does not divide $n$. Then we have

  5. Nonlinear feedback synchronisation control between fractional-order and integer-order chaotic systems

    Institute of Scientific and Technical Information of China (English)

    Jia Li-Xin; Dai Hao; Hui Meng

    2010-01-01

    This paper focuses on the synchronisation between fractional-order and integer-order chaotic systems.Based on Lyapunov stability theory and numerical differentiation,a nonlinear feedback controller is obtained to achieve the synchronisation between fractional-order and integer-order chaotic systems.Numerical simulation results are presented to illustrate the effectiveness of this method.

  6. Sabrewing: A lightweight architecture for combined floating-point and integer arithmetic

    NARCIS (Netherlands)

    Bruintjes, Tom; Walters, K.H.G.; Gerez, Sabih H.; Molenkamp, Egbert; Smit, Gerardus Johannes Maria

    In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in

  7. Mixed integer (0-1) fractional programming for decision support in paper production industry

    NARCIS (Netherlands)

    Claassen, G.D.H.

    2014-01-01

    This paper presents an effective and efficient method for solving a special class of mixed integer fractional programming (FP) problems. We take a classical reformulation approach for continuous FP as a starting point and extend it for solving a more general class of mixed integer (0–1) fractional p

  8. Integral-valued polynomials over sets of algebraic integers of bounded degree.

    Science.gov (United States)

    Peruginelli, Giulio

    2014-04-01

    Let K be a number field of degree n with ring of integers [Formula: see text]. By means of a criterion of Gilmer for polynomially dense subsets of the ring of integers of a number field, we show that, if [Formula: see text] maps every element of [Formula: see text] of degree n to an algebraic integer, then [Formula: see text] is integral-valued over [Formula: see text], that is, [Formula: see text]. A similar property holds if we consider the set of all algebraic integers of degree n and a polynomial [Formula: see text]: if [Formula: see text] is integral over [Formula: see text] for every algebraic integer α of degree n, then [Formula: see text] is integral over [Formula: see text] for every algebraic integer β of degree smaller than n. This second result is established by proving that the integral closure of the ring of polynomials in [Formula: see text] which are integer-valued over the set of matrices [Formula: see text] is equal to the ring of integral-valued polynomials over the set of algebraic integers of degree equal to n.

  9. Improving integer ambiguity resolution for GLONASS precise orbit determination

    Science.gov (United States)

    Liu, Yang; Ge, Maorong; Shi, Chuang; Lou, Yidong; Wickert, Jens; Schuh, Harald

    2016-08-01

    The frequency division multiple access adopted in present GLONASS introduces inter-frequency bias (IFB) at the receiver-end both in code and phase observables, which makes GLONASS ambiguity resolution rather difficult or even not available, especially for long baselines up to several thousand kilometers. This is one of the major reasons that GLONASS could hardly reach the orbit precision of GPS, both in terms of consistency among individual International GNSS Service (IGS) analysis centers and discontinuity at the overlapping day boundaries. Based on the fact that the GLONASS phase IFB is similar on L1 and L2 bands in unit of length and is a linear function of the frequency number, several approaches have been developed to estimate and calibrate the IFB for integer ambiguity resolution. However, they are only for short and medium baselines. In this study, a new ambiguity resolution approach is developed for GLONASS global networks. In the approach, the phase ambiguities in the ionosphere-free linear combination are directly transformed with a wavelength of about 5.3 cm, according to the special frequency relationship of GLONASS L1 and L2 signals. After such transformation, the phase IFB rate can be estimated and corrected precisely and then the corresponding double-differenced ambiguities can be directly fixed to integers even for baselines up to several thousand kilometers. To evaluate this approach, experimental validations using one-month data of a global network with 140 IGS stations was carried out for GLONASS precise orbit determination. The results show that the GLONASS double-difference ambiguity resolution for long baselines could be achieved with an average fixing-rate of 91.4 %. Applying the fixed ambiguities as constraints, the GLONASS orbit overlapping RMS at the day boundaries could be reduced by 37.2 % in ideal cases and with an averaged reduction of about 21.4 %, which is comparable with that by the GPS ambiguity resolution. The orbit improvement is

  10. Positive Integer Solutions of the Diophantine Equation $x^2 - L_n xy + (-1)^n y^2 = ± 5^r$

    Indian Academy of Sciences (India)

    Refik Keskin; Zafer Şiar

    2014-08-01

    In this paper, we consider the equation $x^2-L_n xy+(-1)^n y^2=± 5^r$ and determine the values of for which the equation has positive integer solutions and . Moreover, we give all positive integer solutions of the equation $x^2-L_n xy+(-1)^n y^2=± 5^r$ when the equation has positive integer solutions.

  11. Anisotropic fractal media by vector calculus in non-integer dimensional space

    Energy Technology Data Exchange (ETDEWEB)

    Tarasov, Vasily E., E-mail: tarasov@theory.sinp.msu.ru [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow 119991 (Russian Federation)

    2014-08-15

    A review of different approaches to describe anisotropic fractal media is proposed. In this paper, differentiation and integration non-integer dimensional and multi-fractional spaces are considered as tools to describe anisotropic fractal materials and media. We suggest a generalization of vector calculus for non-integer dimensional space by using a product measure method. The product of fractional and non-integer dimensional spaces allows us to take into account the anisotropy of the fractal media in the framework of continuum models. The integration over non-integer-dimensional spaces is considered. In this paper differential operators of first and second orders for fractional space and non-integer dimensional space are suggested. The differential operators are defined as inverse operations to integration in spaces with non-integer dimensions. Non-integer dimensional space that is product of spaces with different dimensions allows us to give continuum models for anisotropic type of the media. The Poisson's equation for fractal medium, the Euler-Bernoulli fractal beam, and the Timoshenko beam equations for fractal material are considered as examples of application of suggested generalization of vector calculus for anisotropic fractal materials and media.

  12. A guide to reliability aspects of microprocessor-based instrument development

    Science.gov (United States)

    Taunton, J. C.

    1982-03-01

    Techniques for assessing the hardware reliability of microprocessor-based products are reviewed. Models for predicting the failure rates of indifferent categories of microelectronic components, failure mechanisms, and degradation processes are examined. The failure rates of several types of microprocessor, memory and peripheral component, obtained from accelerated life testing are given. Software design philosophies, the choice of programming languages and methods of software testing and reliability assessment are discussed. The life characteristics of microelectronic components follow the same curve as those for discrete digital or analog components, and similar models can be used to describe their failure characteristics. Best estimates of system reliability come from the independent assessment of hardware and software reliability. The overall reliability of hardware is expected to be better in LSI systems, although initial failure rates can be higher than for discrete components.

  13. A case study for the real-time experimental evaluation of the VIPER microprocessor

    Science.gov (United States)

    Carreno, Victor A.; Angellatta, Rob K.

    1991-01-01

    An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

  14. A case study for the real-time experimental evaluation of the VIPER microprocessor

    Science.gov (United States)

    Carreno, Victor A.; Angellatta, Rob K.

    1991-09-01

    An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

  15. A microprocessor-based position control system for a telescope secondary mirror

    Science.gov (United States)

    Lorell, K. R.; Barrows, W. F.; Clappier, R. R.; Lee, G. K.

    1983-01-01

    The pointing requirements for the Shuttle IR Telescope Facility (SIRTF), which consists of an 0.85-m cryogenically cooled IR telescope, call for an image stability of 0.25 arcsec. Attention is presently given to a microprocessor-based position control system developed for the control of the SIRTF secondary mirror, employing a special control law (to minimize energy dissipation), a precision capacitive position sensor, and a specially designed power amplifier/actuator combination. The microprocessor generates the command angular position and rate waveforms in order to maintain a 90 percent dwell time/10 percent transition time ratio independently of chop frequency or amplitude. Performance and test results of a prototype system designed for use with a demonstration model of the SIRTF focal plane fine guidance sensor are presented.

  16. In-house servicing of microprocessor-based and digital patient care equipment.

    Science.gov (United States)

    Ben-Zvi, S; Casaregola, D; Weissenberg, G

    1985-01-01

    Servicing of microprocessor-based and digital patient care instrumentation presents a special challenge to the in-house clinical engineering program. The complexity of this instrumentation, the cost of test equipment and support materials, and continuing education needs are pressing concerns. Servicing methods available to clinical engineering include the use of manufacturer diagnostics and board or subassembly swapping. Test equipment, such as digital oscilloscopes, logic analyzers, signature analyzers, and logic probes, can also be used during repair, even to the component level. In some instances, clinical engineering may choose alternative service arrangements, such as fee-for-service, service contracts, or maintenance insurance. Clinical engineering must objectively evaluate its resources and the level of technical expertise within the department; a realistic maintenance program for microprocessor-based and digital patient care equipment can thus be developed and can result in significant cost savings.

  17. Microprocessor based protecting and monitoring system for transformer of electric furnace in nickel smelting process

    Institute of Scientific and Technical Information of China (English)

    廖力清; 曾可; 凌玉华; 杨欣荣; 陈燕辉

    2001-01-01

    In nickel smelting process, the working conditions and surroundings for the transformer of electric furnace are worse than general electric power transformer. It is difficult to meet the requirements on reliability and safety by the conventional centralized control protection. With the development of microcomputer and field-bus technology, it is necessary to design a new type of protection and monitoring system for transformer of electric furnace. A microprocessor-based protection and monitoring system was described, which uses the embedded high performance microprocessor 87C196KC20 as its most important micro-controller unit & the technology of CAN (Controller Area Network) making it a fully distributed microcomputer system not only to perform all sorts of the transformer protection and function of automatic coinciding and communicate with the monitoring host, but also to carry with it the function of protecting, measuring, and fault diagnosis for transformer of electric furnace.

  18. Trieste conference on digital microelectronics and microprocessors in particle physics: Summary and concluding remarks

    Energy Technology Data Exchange (ETDEWEB)

    Nash, T.

    1988-08-01

    This paper is a written version of the Concluding Remarks presented at the International Conference on the Impact of Digital Microelectronics and Microprocessors on Particle Physics. The Conference emphasized on-line data acquisition and triggering problems in high energy physics. Among the participants there was a clearly growing consensus that as these real time systems become larger they require more attention from the beginning to overall system coherence and manageability issues. We consider what this means for SSC/LHC era detectors. Given the interesting results on pixel silicon, neural networks, and parallel microprocessor based computers presented at Trieste, we speculate on some surprisingly simple, though still very radical, ideas on systems solutions for those huge detectors.

  19. IESIP - AN IMPROVED EXPLORATORY SEARCH TECHNIQUE FOR PURE INTEGER LINEAR PROGRAMMING PROBLEMS

    Science.gov (United States)

    Fogle, F. R.

    1994-01-01

    IESIP, an Improved Exploratory Search Technique for Pure Integer Linear Programming Problems, addresses the problem of optimizing an objective function of one or more variables subject to a set of confining functions or constraints by a method called discrete optimization or integer programming. Integer programming is based on a specific form of the general linear programming problem in which all variables in the objective function and all variables in the constraints are integers. While more difficult, integer programming is required for accuracy when modeling systems with small numbers of components such as the distribution of goods, machine scheduling, and production scheduling. IESIP establishes a new methodology for solving pure integer programming problems by utilizing a modified version of the univariate exploratory move developed by Robert Hooke and T.A. Jeeves. IESIP also takes some of its technique from the greedy procedure and the idea of unit neighborhoods. A rounding scheme uses the continuous solution found by traditional methods (simplex or other suitable technique) and creates a feasible integer starting point. The Hook and Jeeves exploratory search is modified to accommodate integers and constraints and is then employed to determine an optimal integer solution from the feasible starting solution. The user-friendly IESIP allows for rapid solution of problems up to 10 variables in size (limited by DOS allocation). Sample problems compare IESIP solutions with the traditional branch-and-bound approach. IESIP is written in Borland's TURBO Pascal for IBM PC series computers and compatibles running DOS. Source code and an executable are provided. The main memory requirement for execution is 25K. This program is available on a 5.25 inch 360K MS DOS format diskette. IESIP was developed in 1990. IBM is a trademark of International Business Machines. TURBO Pascal is registered by Borland International.

  20. Approximating electrical distribution networks via mixed-integer nonlinear programming

    Energy Technology Data Exchange (ETDEWEB)

    Lakhera, Sanyogita [Citibank, New York City, NY (United States); Shanbhag, Uday V. [Department of Industrial and Enterprise Systems Engineering at the University of Illinois at Urbana-Champaign, 117 Transportation Building, 104 S. Mathews Ave., Urbana, IL 61801 (United States); McInerney, Michael K. [Construction Engineering Research Laboratory (CERL) (United States)

    2011-02-15

    Given urban data derived from a geographical information system (GIS), we consider the problem of constructing an estimate of the electrical distribution system of an urban area. We employ the image data to obtain an approximate electrical load distribution over a network of a prespecificed discretization. Together with partial information about existing substations, we determine the optimal placement of electrical substations to sustain such a load that minimizes the cost of capital and losses. This requires solving large-scale quadratic programs with discrete variables for which we present a novel penalization-smoothing scheme. The choice of locations allows one to determine the optimal flows in this network, as required by physical requirements which provide us with an approximation of the distribution network. Furthermore, the scheme allows for approximating systems in the presence of no-go areas, such as lakes and fields. We examine the performance of our algorithm on the solution of a set of location problems and observe that the scheme is capable of solving large-scale instances, well beyond the realm of existing mixed-integer nonlinear programming solvers. We conclude with a case study in which a stage-wise extension of this scheme is developed to reflect the temporal evolution of load. (author)

  1. Sums of the Numbers of Prime Factors of Positive Integers

    Institute of Scientific and Technical Information of China (English)

    王巧林

    1993-01-01

    Denote by ω(n) and Ω(n) the number of distinct prime factors of n and the total number of prime factors of n,respectively.For any positive integer ι,we prove that ∑↑2≤n≤x1/ω(n)=ι↑∑↑κ=0(ι↑∑↑i=κ(-1)i-κCiκF(i-κ)(1)κ!x/(loglogx)i+1+O(x/(loglogx)ι+2) ∑↑2≤n≤xΩ(n)/ω(n)=x+ι↑∑↑κ=0ι↑∑↑i=κ∑↑p1/pκ+2-pκ+1(-1)i-κCiκF(i-κ)(1)κ!)x/(loglogx)i+1+O(x/(loglogx)ι+2) where F(z)=1/г(z)pⅡ(1+z/p-1)(1-1/p)z,and the constant O despends on ι.This improves previous result of R.L.Duncan and Chao Huizhong.

  2. Emergence of integer quantum Hall effect from chaos

    CERN Document Server

    Tian, Chushun; Wang, Jiao

    2015-01-01

    We present an analytic microscopic theory showing that in a large class of spin-$\\frac{1}{2}$ quasiperiodic quantum kicked rotors, a dynamical analog of the integer quantum Hall effect (IQHE) emerges from an intrinsic chaotic structure. Specifically, the inverse of the Planck's quantum ($h_e$) and the rotor's energy growth rate mimic the `filling fraction' and the `longitudinal conductivity' in conventional IQHE, respectively, and a hidden quantum number is found to mimic the `quantized Hall conductivity'. We show that for an infinite discrete set of critical values of $h_e$, the long-time energy growth rate is universal and of order of unity (`metallic' phase), but otherwise vanishes (`insulating' phase). Moreover, the rotor insulating phases are topological, each of which is characterized by a hidden quantum number. This number exhibits universal behavior for small $h_e$, i.e., it jumps by unity whenever $h_e$ decreases, passing through each critical value. This intriguing phenomenon is not triggered by the...

  3. Module detection in complex networks using integer optimisation

    Directory of Open Access Journals (Sweden)

    Tsoka Sophia

    2010-11-01

    Full Text Available Abstract Background The detection of modules or community structure is widely used to reveal the underlying properties of complex networks in biology, as well as physical and social sciences. Since the adoption of modularity as a measure of network topological properties, several methodologies for the discovery of community structure based on modularity maximisation have been developed. However, satisfactory partitions of large graphs with modest computational resources are particularly challenging due to the NP-hard nature of the related optimisation problem. Furthermore, it has been suggested that optimising the modularity metric can reach a resolution limit whereby the algorithm fails to detect smaller communities than a specific size in large networks. Results We present a novel solution approach to identify community structure in large complex networks and address resolution limitations in module detection. The proposed algorithm employs modularity to express network community structure and it is based on mixed integer optimisation models. The solution procedure is extended through an iterative procedure to diminish effects that tend to agglomerate smaller modules (resolution limitations. Conclusions A comprehensive comparative analysis of methodologies for module detection based on modularity maximisation shows that our approach outperforms previously reported methods. Furthermore, in contrast to previous reports, we propose a strategy to handle resolution limitations in modularity maximisation. Overall, we illustrate ways to improve existing methodologies for community structure identification so as to increase its efficiency and applicability.

  4. Integer wavelet transform for embedded lossy to lossless image compression.

    Science.gov (United States)

    Reichel, J; Menegaz, G; Nadenau, M J; Kunt, M

    2001-01-01

    The use of the discrete wavelet transform (DWT) for embedded lossy image compression is now well established. One of the possible implementations of the DWT is the lifting scheme (LS). Because perfect reconstruction is granted by the structure of the LS, nonlinear transforms can be used, allowing efficient lossless compression as well. The integer wavelet transform (IWT) is one of them. This is an interesting alternative to the DWT because its rate-distortion performance is similar and the differences can be predicted. This topic is investigated in a theoretical framework. A model of the degradations caused by the use of the IWT instead of the DWT for lossy compression is presented. The rounding operations are modeled as additive noise. The noise are then propagated through the LS structure to measure their impact on the reconstructed pixels. This methodology is verified using simulations with random noise as input. It predicts accurately the results obtained using images compressed by the well-known EZW algorithm. Experiment are also performed to measure the difference in terms of bit rate and visual quality. This allows to a better understanding of the impact of the IWT when applied to lossy image compression.

  5. AN EFFICIENT HILBERT AND INTEGER WAVELET TRANSFORM BASED VIDEO WATERMARKING

    Directory of Open Access Journals (Sweden)

    AGILANDEESWARI L.

    2016-03-01

    Full Text Available In this paper, an efficient, highly imperceptible, robust, and secure digital video watermarking technique for content authentication based on Hilbert transform in the Integer Wavelet Transform (IWT domain has been introduced. The Hilbert coefficients of gray watermark image are embedded into the cover video frames Hilbert coefficients on the 2-level IWT decomposed selected block on sub-bands using Principal Component Analysis (PCA technique. The authentication is achieved by using the digital signature mechanism. This mechanism is used to generate and embed a digital signature after embedding the watermarks. Since, the embedding process is done in Hilbert transform domain, the imperceptibility and the robustness of the watermark is greatly improved. At the receiver end, prior to the extraction of watermark, the originality of the content is verified through the authentication test. If the generated and received signature matches, it proves that the received content is original and performs the extraction process, otherwise deny the extraction process due to unauthenticated received content. The proposed method avoids typical degradations in the imperceptibility level of watermarked video in terms of Average Peak Signal – to – Noise Ratio (PSNR value of about 48db, while it is still providing better robustness against common video distortions such as frame dropping, averaging, and various image processing attacks such as noise addition, median filtering, contrast adjustment, and geometrical attacks such as, rotation and cropping in terms of Normalized Correlation Coefficient (NCC value of about nearly 1.

  6. A Faster Algorithm for Quasi-convex Integer Polynomial Optimization

    CERN Document Server

    Hildebrand, Robert

    2010-01-01

    We present a faster exponential-time algorithm for integer optimization over quasi-convex polynomials. We study the minimization of a quasi-convex polynomial subject to s quasi-convex polynomial constraints and integrality constraints for all variables. The new algorithm is an improvement upon the best known algorithm due to Heinz (Journal of Complexity, 2005). A lower time complexity is reached through applying a stronger ellipsoid rounding method and applying a recent advancement in the shortest vector problem to give a smaller exponential-time complexity of a Lenstra-type algorithm. For the bounded case, our algorithm attains a time-complexity of s (r l M d)^{O(1)} 2^{2n\\log_2(n) + O(n)} when M is a bound on the number of monomials in each polynomial and r is the binary encoding length of a bound on the feasible region. In the general case, s l^{O(1)} d^{O(n)} 2^{2n\\log_2(n)}. In each we assume d>=2 is a bound on the total degree of the polynomials and l bounds the maximum binary encoding size of the input...

  7. Preconditioning 2D Integer Data for Fast Convex Hull Computations.

    Directory of Open Access Journals (Sweden)

    José Oswaldo Cadenas

    Full Text Available In order to accelerate computing the convex hull on a set of n points, a heuristic procedure is often applied to reduce the number of points to a set of s points, s ≤ n, which also contains the same hull. We present an algorithm to precondition 2D data with integer coordinates bounded by a box of size p × q before building a 2D convex hull, with three distinct advantages. First, we prove that under the condition min(p, q ≤ n the algorithm executes in time within O(n; second, no explicit sorting of data is required; and third, the reduced set of s points forms a simple polygonal chain and thus can be directly pipelined into an O(n time convex hull algorithm. This paper empirically evaluates and quantifies the speed up gained by preconditioning a set of points by a method based on the proposed algorithm before using common convex hull algorithms to build the final hull. A speedup factor of at least four is consistently found from experiments on various datasets when the condition min(p, q ≤ n holds; the smaller the ratio min(p, q/n is in the dataset, the greater the speedup factor achieved.

  8. Deleting Outliers in Robust Regression with Mixed Integer Programming

    Institute of Scientific and Technical Information of China (English)

    Georgios Zioutas; Antonios Avramidis

    2005-01-01

    In robust regression we often have to decide how many are the unusual observations, which should be removed from the sample in order to obtain better fitting for the rest of the observations. Generally, we use the basic principle of LTS, which is to fit the majority of the data, identifying as outliers those points that cause the biggest damage to the robust fit. However, in the LTS regression method the choice of default values for high break down-point affects seriously the efficiency of the estimator. In the proposed approach we introduce penalty cost for discarding an outlier, consequently, the best fit for the majority of the data is obtained by discarding only catastrophic observations. This penalty cost is based on robust design weights and high break down-point residual scale taken from the LTS estimator. The robust estimation is obtained by solving a convex quadratic mixed integer programming problem, where in the objective function the sum of the squared residuals and penalties for discarding observations is minimized. The proposed mathematical programming formula is suitable for small-sample data. Moreover, we conduct a simulation study to compare other robust estimators with our approach in terms of their efficiency and robustness.

  9. Near integer tune for polarization preservation in the AGS

    Energy Technology Data Exchange (ETDEWEB)

    Tsoupas N.; Ahrens, L.; Bai, M.; Brown, K.; Glenn, J.W.; Huang, H.; MacKay, W.W.; Roser, T.; Schoefer, V.; Zeno, K.

    2012-05-20

    The high energy (T = 250 GeV) polarized proton beam experiments performed in RHIC, require high polarization of the beam. In order to preserve the polarization of the proton beam, during the acceleration in the AGS, which is the pre-injector to RHIC, we have installed in AGS two partial helical magnets which minimize the loss of the beam polarization caused by the various intrinsic spin resonances occurring during the proton acceleration. The minimization of the polarization loss during the acceleration cycle, requires that the vertical tune of the AGS is between the values of 8.97 and 8.985 during the acceleration. With the AGS constrained to run at near integer tune {approx}8.980, the perturbations to the beam caused by the partial helical magnets are large and also result in large beta and dispersion waves. To mitigate the adverse effect of the partial helices on the optics of the AGS, we have installed in specified straight sections of the AGS compensation quads and we have also generated a beam bump at the location of the cold partial helix. In this paper we present the beam optics of the AGS which ameliorates the adverse effect of the two partial helices on the beam optics.

  10. An integer programming model for assigning students to elective courses

    Directory of Open Access Journals (Sweden)

    Ivo Beroš

    2015-10-01

    Full Text Available This paper deals with the problem of assigning students to elective courses according to their preferences. This process of assigning students to elective courses according to their preferences often places before academic institutions numerous obstacles, the most typical being a limited number of students who can be assigned to any particular class. Furthermore, due to financial or technical reasons, the maximum number of the elective courses is determined in advance, meaning that the institution decides which courses to conduct. Therefore, the expectation that all the students will be assigned to their first choice of courses is not realistic (perfect satisfaction. This paper presents an integer programming model that maximizes the total student satisfaction in line with a number of different constraints. The measure of student satisfaction is based on a student's order of preference according to the principle: the more a choice is met the higher the satisfaction. Following the basic model, several versions of the models are generated to cover possible real-life situations, while taking into consideration the manner student satisfaction is measured, as well as the preference of academic institution within set technical and financial constraints. The main contribution of the paper is introducing the concept of the minimal student satisfaction level that reduces the number of students dissatised with the courses to which they were assigned.

  11. Cho Decomposition of One-Half Integer Monopoles Solutions

    Science.gov (United States)

    Teh, Rosy; Ng, Ban-Loong; Wong, Khai-Ming

    2013-11-01

    We performed the Cho decomposition of the SU(2) Yang-Mills-Higgs gauge potentials of the finite energy (1) one-half monopole solution and (2) the one and a half monopoles solution into Abelian and non-Abelian components. We found that the semi-infinite string singularity in the gauge potentials is a contribution from the Higgs field of the one-half monopole in both of the solutions. The non-Abelian components of the gauge potentials are able to remove the point singularity of the Abelian components of the 't Hooft-Polyakov monopole but not the string singularity of the one-half monopole which is topological in nature. Hence the total energy of a one monopole is infinite in the Maxwell electromagnetic theory but the total energy of a one-half monopole is finite. By analyzing the magnetic fields and the gauge covariant derivatives of the Higgs field, we are able to conclude that both the one-half integer monopoles solutions are indeed non-BPS even in the limit of vanishing Higgs self-coupling constant.

  12. On Column-restricted and Priority Covering Integer Programs

    CERN Document Server

    Chakrabarty, Deeparnab; Koenemann, Jochen

    2010-01-01

    In a column-restricted covering integer program (CCIP), all the non-zero entries of any column of the constraint matrix are equal. Such programs capture capacitated versions of covering problems. In this paper, we study the approximability of CCIPs, in particular, their relation to the integrality gaps of the underlying 0,1-CIP. If the underlying 0,1-CIP has an integrality gap O(gamma), and assuming that the integrality gap of the priority version of the 0,1-CIP is O(omega), we give a factor O(gamma + omega) approximation algorithm for the CCIP. Priority versions of 0,1-CIPs (PCIPs) naturally capture quality of service type constraints in a covering problem. We investigate priority versions of the line (PLC) and the (rooted) tree cover (PTC) problems. Apart from being natural objects to study, these problems fall in a class of fundamental geometric covering problems. We bound the integrality of certain classes of this PCIP by a constant. Algorithmically, we give a polytime exact algorithm for PLC, show that t...

  13. Constrained spacecraft reorientation using mixed integer convex programming

    Science.gov (United States)

    Tam, Margaret; Glenn Lightsey, E.

    2016-10-01

    A constrained attitude guidance (CAG) system is developed using convex optimization to autonomously achieve spacecraft pointing objectives while meeting the constraints imposed by on-board hardware. These constraints include bounds on the control input and slew rate, as well as pointing constraints imposed by the sensors. The pointing constraints consist of inclusion and exclusion cones that dictate permissible orientations of the spacecraft in order to keep objects in or out of the field of view of the sensors. The optimization scheme drives a body vector towards a target inertial vector along a trajectory that consists solely of permissible orientations in order to achieve the desired attitude for a given mission mode. The non-convex rotational kinematics are handled by discretization, which also ensures that the quaternion stays unity norm. In order to guarantee an admissible path, the pointing constraints are relaxed. Depending on how strict the pointing constraints are, the degree of relaxation is tuneable. The use of binary variables permits the inclusion of logical expressions in the pointing constraints in the case that a set of sensors has redundancies. The resulting mixed integer convex programming (MICP) formulation generates a steering law that can be easily integrated into an attitude determination and control (ADC) system. A sample simulation of the system is performed for the Bevo-2 satellite, including disturbance torques and actuator dynamics which are not modeled by the controller. Simulation results demonstrate the robustness of the system to disturbances while meeting the mission requirements with desirable performance characteristics.

  14. Preconditioning 2D Integer Data for Fast Convex Hull Computations.

    Science.gov (United States)

    Cadenas, José Oswaldo; Megson, Graham M; Luengo Hendriks, Cris L

    2016-01-01

    In order to accelerate computing the convex hull on a set of n points, a heuristic procedure is often applied to reduce the number of points to a set of s points, s ≤ n, which also contains the same hull. We present an algorithm to precondition 2D data with integer coordinates bounded by a box of size p × q before building a 2D convex hull, with three distinct advantages. First, we prove that under the condition min(p, q) ≤ n the algorithm executes in time within O(n); second, no explicit sorting of data is required; and third, the reduced set of s points forms a simple polygonal chain and thus can be directly pipelined into an O(n) time convex hull algorithm. This paper empirically evaluates and quantifies the speed up gained by preconditioning a set of points by a method based on the proposed algorithm before using common convex hull algorithms to build the final hull. A speedup factor of at least four is consistently found from experiments on various datasets when the condition min(p, q) ≤ n holds; the smaller the ratio min(p, q)/n is in the dataset, the greater the speedup factor achieved.

  15. Efficient Interpolant Generation in Satisfiability Modulo Linear Integer Arithmetic

    CERN Document Server

    Griggio, Alberto; Sebastiani, Roberto

    2010-01-01

    The problem of computing Craig interpolants in SAT and SMT has recently received a lot of interest, mainly for its applications in formal verification. Efficient algorithms for interpolant generation have been presented for some theories of interest ---including that of equality and uninterpreted functions, linear arithmetic over the rationals, and their combination--- and they are successfully used within model checking tools. For the theory of linear arithmetic over the integers (LA(Z)), however, the problem of finding an interpolant is more challenging, and the task of developing efficient interpolant generators for the full theory LA(Z) is still the objective of ongoing research. In this paper we try to close this gap. We build on previous work and present a novel interpolation algorithm for SMT(LA(Z)), which exploits the full power of current state-of-the-art SMT(LA(Z)) solvers. We demonstrate the potential of our approach with an extensive experimental evaluation of our implementation of the proposed al...

  16. Mixed integer linear programming for maximum-parsimony phylogeny inference.

    Science.gov (United States)

    Sridhar, Srinath; Lam, Fumei; Blelloch, Guy E; Ravi, R; Schwartz, Russell

    2008-01-01

    Reconstruction of phylogenetic trees is a fundamental problem in computational biology. While excellent heuristic methods are available for many variants of this problem, new advances in phylogeny inference will be required if we are to be able to continue to make effective use of the rapidly growing stores of variation data now being gathered. In this paper, we present two integer linear programming (ILP) formulations to find the most parsimonious phylogenetic tree from a set of binary variation data. One method uses a flow-based formulation that can produce exponential numbers of variables and constraints in the worst case. The method has, however, proven extremely efficient in practice on datasets that are well beyond the reach of the available provably efficient methods, solving several large mtDNA and Y-chromosome instances within a few seconds and giving provably optimal results in times competitive with fast heuristics than cannot guarantee optimality. An alternative formulation establishes that the problem can be solved with a polynomial-sized ILP. We further present a web server developed based on the exponential-sized ILP that performs fast maximum parsimony inferences and serves as a front end to a database of precomputed phylogenies spanning the human genome.

  17. Learning oncogenetic networks by reducing to mixed integer linear programming.

    Science.gov (United States)

    Shahrabi Farahani, Hossein; Lagergren, Jens

    2013-01-01

    Cancer can be a result of accumulation of different types of genetic mutations such as copy number aberrations. The data from tumors are cross-sectional and do not contain the temporal order of the genetic events. Finding the order in which the genetic events have occurred and progression pathways are of vital importance in understanding the disease. In order to model cancer progression, we propose Progression Networks, a special case of Bayesian networks, that are tailored to model disease progression. Progression networks have similarities with Conjunctive Bayesian Networks (CBNs) [1],a variation of Bayesian networks also proposed for modeling disease progression. We also describe a learning algorithm for learning Bayesian networks in general and progression networks in particular. We reduce the hard problem of learning the Bayesian and progression networks to Mixed Integer Linear Programming (MILP). MILP is a Non-deterministic Polynomial-time complete (NP-complete) problem for which very good heuristics exists. We tested our algorithm on synthetic and real cytogenetic data from renal cell carcinoma. We also compared our learned progression networks with the networks proposed in earlier publications. The software is available on the website https://bitbucket.org/farahani/diprog.

  18. Accurate construction of consensus genetic maps via integer linear programming.

    Science.gov (United States)

    Wu, Yonghui; Close, Timothy J; Lonardi, Stefano

    2011-01-01

    We study the problem of merging genetic maps, when the individual genetic maps are given as directed acyclic graphs. The computational problem is to build a consensus map, which is a directed graph that includes and is consistent with all (or, the vast majority of) the markers in the input maps. However, when markers in the individual maps have ordering conflicts, the resulting consensus map will contain cycles. Here, we formulate the problem of resolving cycles in the context of a parsimonious paradigm that takes into account two types of errors that may be present in the input maps, namely, local reshuffles and global displacements. The resulting combinatorial optimization problem is, in turn, expressed as an integer linear program. A fast approximation algorithm is proposed, and an additional speedup heuristic is developed. Our algorithms were implemented in a software tool named MERGEMAP which is freely available for academic use. An extensive set of experiments shows that MERGEMAP consistently outperforms JOINMAP, which is the most popular tool currently available for this task, both in terms of accuracy and running time. MERGEMAP is available for download at http://www.cs.ucr.edu/~yonghui/mgmap.html.

  19. Maximum likelihood pedigree reconstruction using integer linear programming.

    Science.gov (United States)

    Cussens, James; Bartlett, Mark; Jones, Elinor M; Sheehan, Nuala A

    2013-01-01

    Large population biobanks of unrelated individuals have been highly successful in detecting common genetic variants affecting diseases of public health concern. However, they lack the statistical power to detect more modest gene-gene and gene-environment interaction effects or the effects of rare variants for which related individuals are ideally required. In reality, most large population studies will undoubtedly contain sets of undeclared relatives, or pedigrees. Although a crude measure of relatedness might sometimes suffice, having a good estimate of the true pedigree would be much more informative if this could be obtained efficiently. Relatives are more likely to share longer haplotypes around disease susceptibility loci and are hence biologically more informative for rare variants than unrelated cases and controls. Distant relatives are arguably more useful for detecting variants with small effects because they are less likely to share masking environmental effects. Moreover, the identification of relatives enables appropriate adjustments of statistical analyses that typically assume unrelatedness. We propose to exploit an integer linear programming optimisation approach to pedigree learning, which is adapted to find valid pedigrees by imposing appropriate constraints. Our method is not restricted to small pedigrees and is guaranteed to return a maximum likelihood pedigree. With additional constraints, we can also search for multiple high-probability pedigrees and thus account for the inherent uncertainty in any particular pedigree reconstruction. The true pedigree is found very quickly by comparison with other methods when all individuals are observed. Extensions to more complex problems seem feasible.

  20. Development of a microprocessor-based Sun-tracking system for solar collectors

    Science.gov (United States)

    Kohler, S. M.; Wilcoxen, J. L.

    1980-04-01

    The development of a prototype Sun-tracking system and the tests performed on it on an east-west trough solar collector array are described. The system includes a controller built around an RCA1802 microprocessor, a digital shaft encoder, and a heat flux sensor. The heat flux sensor consists of a fine resistance wire wrapped around the receiver tube. The wire is used to correct errors in calculated tracking angles arising from reflector imperfections and misalignments.

  1. Development of a microprocessor-based sun-tracking system for solar collectors

    Energy Technology Data Exchange (ETDEWEB)

    Kohler, S.M.; Wilcoxen, J.L.

    1980-04-01

    The development of a prototype sun-tracking system and the tests performed on it on an east-west trough solar collector array are described. The system includes a controller built around an RCA1802 microprocessor (..mu..P), a digital shaft encoder, and a heat flux sensor. The heat flux sensor consists of a fine resistance wire wrapped around the receiver tube. The wire is used to correct errors in calculated tracking angles arising from reflector imperfections and misalignments.

  2. Test report for single event effects of the 80386DX microprocessor

    Science.gov (United States)

    Watson, R. Kevin; Schwartz, Harvey R.; Nichols, Donald K.

    1993-01-01

    The Jet Propulsion Laboratory Section 514 Single Event Effects (SEE) Testing and Analysis Group has performed a series of SEE tests of certain strategic registers of Intel's 80386DX CHMOS 4 microprocessor. Following a summary of the test techniques and hardware used to gather the data, we present the SEE heavy ion and proton test results. We also describe the registers tested, along with a system impact analysis should these registers experience a single event upset.

  3. INVESTIGATION OF MICROPROCESSOR CURRENT PROTECTION LINES WITH IMPROVED INDICES OF TECHNICAL PERFECTION

    Directory of Open Access Journals (Sweden)

    E. V. Buloichyk

    2014-01-01

    Full Text Available Technical perfection improvement of microprocessor current protection of distribution networks lines is provided by introduction of asymmetrical fault mode determination and fault location functions in the algorithm of its functioning. As a result of computing experiment the basic indices of the technical perfection of current protection have been obtained in the paper. The paper proves high efficiency of the proposed methods that ensure selective and proper operation in the different modes of the controlled line.

  4. API testing program - calibration of microprocessor based flowmeters for integrated metering systems

    Energy Technology Data Exchange (ETDEWEB)

    Elliot, Kenneth D. [Omni Flow Computers, Inc., Stafford, TX (United States)

    2005-07-01

    Microprocessor based flowmeter technologies for liquids, such as Coriolis mass meters, and Ultrasonic flowmeters hold great promise. These technologies offer many advantages, such as no rotating parts, self-diagnostic checks, which can help anticipate and warn of impending failures before they have a major impact on the measurement. These meters are substantially different though than other primary devices due to their heavy reliance on the accompanying secondary electronics. One method to prove that they are accurate would be proving the flowmeter, using a pipe prover or small volume prover (SVP), but these proving methods are designed to count 'real time' pulses from a turbine or PD meter between a known volume, they are not designed to count 'time delayed' 'manufactured pulses' from a microprocessor. There are limitations of the manufactured pulse train and it affects the ability of the flowmeter to be proved using current proving technology. The author of this paper, a chairman of an American Petroleum Institute working group, investigated how the 'microprocessor generated pulses' produced by these types of flowmeters, interacted with the existing measurement technologies in use today. Several microprocessor based flowmeter technologies have been tested, including; Ultrasonic, Coriolis, and Helical Turbine with pulse multiplying preamplifier. Wherever possible, flowmeters of various sizes, and from several vendors have been tested. A significant amount of data has been collected which sheds light into why these types of flowmeters are sometimes difficult to prove. This paper describes the API testing program, and the methodology behind it. It presents results and findings, and offers specific recommendations that may eventually be incorporated into API documents and/or standards in the future. (author)

  5. Microprocessor based interface unit for coupling a picosecond laser oscillator with external laser amplifiers

    Science.gov (United States)

    Navathe, C. P.; Ansari, M. S.; Upadhyaya, J.; Sreedhar, N.; Chandra, R.; Kumbhare, S. R.; Chakera, J. A.; Gupta, P. D.

    1996-07-01

    A microprocessor based interface unit for coupling a commercial picosecond Nd:YLF laser oscillator amplifier to external high power Nd:phosphate glass laser amplifier stages is described. The system generates charging and firing signals required for the picosecond oscillator, and also carries out the charging and firing sequence of external amplifiers for a single shot or a repetitive mode of operation. The electronics developed is simple and modular, with sufficient scope for expansion of the system, and resistant to electromagnetic interference.

  6. A versatile physiological data analysis system using an Intel 8080 microprocessor.

    Science.gov (United States)

    Hyde, D; Nice, E G; Oakley, P J

    1979-08-01

    A microprocessor based physiological data processor has been realised. The system controls the data flow from physiological experiments and performs on-line mean and variance calculations with an output in graphical form. The analyser accepts one data point every 0.5 ms and has a capacity of 128 records each containing 800 data points. Post stimulus histogram and interval histogram analysis programs have also been written and implemented.

  7. An interactive debugging system composed of a minicomputer and a microprocessor

    OpenAIRE

    Okada, Kenichi; 松尾, 泰樹; 北川, 節

    1980-01-01

    This paper describes a debugging system which has been developed on such a combined system of a minicomputer and a microprocessor that is microprogrammable for the user, and aims at an effective debugging of the errors that will be detected during the execution of the program written in a low-level language. The multiprocessor organization, adoption of firmware monitor and special hardwares yield such advantageous features as bilateral tracing, procedure extraction, eight kinds of event monit...

  8. An overview of solution methods for multi-objective mixed integer linear programming programs

    DEFF Research Database (Denmark)

    Andersen, Kim Allan; Stidsen, Thomas Riis

    Multiple objective mixed integer linear programming (MOMIP) problems are notoriously hard to solve to optimality, i.e. finding the complete set of non-dominated solutions. We will give an overview of existing methods. Among those are interactive methods, the two phases method and enumeration...... methods. In particular we will discuss the existing branch and bound approaches for solving multiple objective integer programming problems. Despite the fact that branch and bound methods has been applied successfully to integer programming problems with one criterion only a few attempts has been made...

  9. STUDI PERBANDINGAN PERFORMANCE ALGORITMA HEURISTIK POUR TERHADAP MIXED INTEGER PROGRAMMING DALAM MENYELESAIKAN PENJADWALAN FLOWSHOP

    Directory of Open Access Journals (Sweden)

    Tessa Vanina Soetanto

    2004-01-01

    Full Text Available This paper presents a study about new heuristic algorithm performance compared to Mixed Integer Programming (MIP method in solving flowshop scheduling problem to reach minimum makespan. Performance appraisal is based on Efficiency Index (EI, Relative Error (RE and Elapsed Runtime. Abstract in Bahasa Indonesia : Makalah ini menyajikan penelitian tentang performance algoritma heuristik Pour terhadap metode Mixed Integer Programming (MIP dalam menyelesaikan masalah penjadwalan flowshop dengan tujuan meminimalkan makespan. Penilaian performance dilakukan berdasarkan nilai Efficiency Index (EI, Relative Error (RE dan Elapsed Runtime. Kata kunci: flowshop, makespan, algoritma heuristik Pour, Mixed Integer Programming.

  10. Higher-order semiclassical energy expansions for potentials with non-integer powers

    Indian Academy of Sciences (India)

    Asiri Nanayakkara

    2003-10-01

    In this paper, we present a semiclassical eigenenergy expansion for the potential || when is a positive rational number of the form 2/ ( is a positive integer and is an odd positive integer). Remarkably, this expansion is found to be identical to the WKB expansion obtained for the potential (-even), if 2/ is replaced by . Taking the limit → 2 of the above expansion, we obtain an explicit asymptotic energy expansion of symmetric odd power potentials ||2+1 (-positive integer). We then show how to develop approximate semiclassical expansions for potentials || when is any positive real number.

  11. An Approximate Algorithm for a Class of Nonlinear Bilevel Integer Programming

    Institute of Scientific and Technical Information of China (English)

    LI Lei; TENG Chun-xian; TIAN Guang-yue

    2002-01-01

    The algorithm for a class of nonlinear bilevel integer programming is discussed in this paper. It is based on the theory and algorithm for nonlinear integer programming. The continuity methods for integer programming are studied in this paper. After simulated annealing algorithm is applied to the upper-level programming problem and the thought of filled function method for continuous global optimization is applied to the corresponding lower-level programming, an approximate algorithm is established. The satisfactory algorithm is elaborated in the following example.

  12. An overview of solution methods for multi-objective mixed integer linear programming programs

    DEFF Research Database (Denmark)

    Andersen, Kim Allan; Stidsen, Thomas Riis

    Multiple objective mixed integer linear programming (MOMIP) problems are notoriously hard to solve to optimality, i.e. finding the complete set of non-dominated solutions. We will give an overview of existing methods. Among those are interactive methods, the two phases method and enumeration...... methods. In particular we will discuss the existing branch and bound approaches for solving multiple objective integer programming problems. Despite the fact that branch and bound methods has been applied successfully to integer programming problems with one criterion only a few attempts has been made...

  13. Evaluation of overlap integrals with integer and noninteger n Slater-type orbitals using auxiliary functions.

    Science.gov (United States)

    Guseinov, Israfil; Mamedov, Bahtiyar

    2002-09-01

    The series expansion formulae are derived for the overlap integrals with arbitrary integer n and noninteger n* Slater-type orbitals (ISTOs and NISTOs) in terms of a product of well-known auxiliary functions A(sigma) and B (k). The series becomes an ordinary closed expression when both principal quantum numbers n* and n'* of orbitals are integer n*= n and n'*= n'. These formulae are especially useful for the calculation of overlap integrals for large quantum numbers. Accuracy of the results is satisfactory for values of integer and noninteger quantum numbers up to n= n'=60, n*= n'*orbitals and internuclear distances.

  14. A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

    Science.gov (United States)

    Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

    2011-10-01

    In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

  15. Microprocessor mediates transcriptional termination of long noncoding RNA transcripts hosting microRNAs.

    Science.gov (United States)

    Dhir, Ashish; Dhir, Somdutta; Proudfoot, Nick J; Jopling, Catherine L

    2015-04-01

    MicroRNAs (miRNAs) play a major part in the post-transcriptional regulation of gene expression. Mammalian miRNA biogenesis begins with cotranscriptional cleavage of RNA polymerase II (Pol II) transcripts by the Microprocessor complex. Although most miRNAs are located within introns of protein-coding transcripts, a substantial minority of miRNAs originate from long noncoding (lnc) RNAs, for which transcript processing is largely uncharacterized. We show, by detailed characterization of liver-specific lnc-pri-miR-122 and genome-wide analysis in human cell lines, that most lncRNA transcripts containing miRNAs (lnc-pri-miRNAs) do not use the canonical cleavage-and-polyadenylation pathway but instead use Microprocessor cleavage to terminate transcription. Microprocessor inactivation leads to extensive transcriptional readthrough of lnc-pri-miRNA and transcriptional interference with downstream genes. Consequently we define a new RNase III-mediated, polyadenylation-independent mechanism of Pol II transcription termination in mammalian cells.

  16. Microprocessor Activity Controls Differential miRNA Biogenesis In Vivo

    Directory of Open Access Journals (Sweden)

    Thomas Conrad

    2014-10-01

    Full Text Available In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression.

  17. Microprocessor dynamics and interactions at endogenous imprinted C19MC microRNA genes.

    Science.gov (United States)

    Bellemer, Clément; Bortolin-Cavaillé, Marie-Line; Schmidt, Ute; Jensen, Stig Mølgaard Rask; Kjems, Jørgen; Bertrand, Edouard; Cavaillé, Jérôme

    2012-06-01

    Nuclear primary microRNA (pri-miRNA) processing catalyzed by the DGCR8-Drosha (Microprocessor) complex is highly regulated. Little is known, however, about how microRNA biogenesis is spatially organized within the mammalian nucleus. Here, we image for the first time, in living cells and at the level of a single microRNA cluster, the intranuclear distribution of untagged, endogenously-expressed pri-miRNAs generated at the human imprinted chromosome 19 microRNA cluster (C19MC), from the environment of transcription sites to single molecules of fully released DGCR8-bound pri-miRNAs dispersed throughout the nucleoplasm. We report that a large fraction of Microprocessor concentrates onto unspliced C19MC pri-miRNA deposited in close proximity to their genes. Our live-cell imaging studies provide direct visual evidence that DGCR8 and Drosha are targeted post-transcriptionally to C19MC pri-miRNAs as a preformed complex but dissociate separately. These dynamics support the view that, upon pri-miRNA loading and most probably concomitantly with Drosha-mediated cleavages, Microprocessor undergoes conformational changes that trigger the release of Drosha while DGCR8 remains stably bound to pri-miRNA.

  18. BRCA1 regulates microRNA biogenesis via the DROSHA microprocessor complex.

    Science.gov (United States)

    Kawai, Shinji; Amano, Atsuo

    2012-04-16

    MicroRNAs (miRNAs) are noncoding RNAs that function as key posttranscriptional regulators of gene expression. miRNA maturation is controlled by the DROSHA microprocessor complex. However, the detailed mechanism of miRNA biogenesis remains unclear. We show that the tumor suppressor breast cancer 1 (BRCA1) accelerates the processing of miRNA primary transcripts. BRCA1 increased the expressions of both precursor and mature forms of let-7a-1, miR-16-1, miR-145, and miR-34a. In addition, this tumor suppressor was shown to be directly associated with DROSHA and DDX5 of the DROSHA microprocessor complex, and it interacted with Smad3, p53, and DHX9 RNA helicase. We also found that BRCA1 recognizes the RNA secondary structure and directly binds with primary transcripts of miRNAs via a DNA-binding domain. Together, these results suggest that BRCA1 regulates miRNA biogenesis via the DROSHA microprocessor complex and Smad3/p53/DHX9. Our findings also indicate novel functions of BRCA1 in miRNA biogenesis, which may be linked to its tumor suppressor mechanism and maintenance of genomic stability.

  19. TDP-43 regulates the microprocessor complex activity during in vitro neuronal differentiation.

    Science.gov (United States)

    Di Carlo, Valerio; Grossi, Elena; Laneve, Pietro; Morlando, Mariangela; Dini Modigliani, Stefano; Ballarino, Monica; Bozzoni, Irene; Caffarelli, Elisa

    2013-12-01

    TDP-43 (TAR DNA-binding protein 43) is an RNA-binding protein implicated in RNA metabolism at several levels. Even if ubiquitously expressed, it is considered as a neuronal activity-responsive factor and a major signature for neurological pathologies, making the comprehension of its activity in the nervous system a very challenging issue. TDP-43 has also been described as an accessory component of the Drosha-DGCR8 (DiGeorge syndrome critical region gene 8) microprocessor complex, which is crucially involved in basal and tissue-specific RNA processing events. In the present study, we exploited in vitro neuronal differentiation systems to investigate the TDP-43 demand for the microprocessor function, focusing on both its canonical microRNA biosynthetic activity and its alternative role as a post-transcriptional regulator of gene expression. Our findings reveal a novel role for TDP-43 as an essential factor that controls the stability of Drosha protein during neuronal differentiation, thus globally affecting the production of microRNAs. We also demonstrate that TDP-43 is required for the Drosha-mediated regulation of Neurogenin 2, a master gene orchestrating neurogenesis, whereas post-transcriptional control of Dgcr8, another Drosha target, resulted to be TDP-43-independent. These results implicate a previously uncovered contribution of TDP-43 in regulating the abundance and the substrate specificity of the microprocessor complex and provide new insights into TDP-43 as a key player in neuronal differentiation.

  20. Pure Silica Zeolite Beta Membrane: A Potential Low Dielectric Constant Material For Microprocessor Application

    Science.gov (United States)

    Fong, Yeong Yin; Bhatia, Subhash

    The semiconductor industry needs low dielectric constant (low k-value) materials for more advance microprocessor and chips by reducing the size of the device features. In fabricating these contents, a new material with lower k-value than conventional silica (k = 3.9-4.2) is needed in order to improve the circuit performance. The choice of the inorganic zeolite membrane is an attractive option for low k material and suitable for microprocessor applications. A pure silica zeolite beta membrane was synthesized and coated on non-porous stainless steel support using insitu crystallization in the presence of tetraethylammonium hydroxide, TEA (OH), as structure directing agent, fumed silica, HF and deionized water at pH value of 9. The crystallization was carried out for the duration of 14 days under hydrothermal conditions at 130°C. The membrane was characterized by thermogravimetric analysis (TGA), nitrogen adsorption and Scanning Electron Microscope (SEM). SEM results show a highly crystalline; with a truncated square bipyramidal morphology of pure silica zeolite beta membrane strongly adhered on the non-porous stainless steel support. In the present work, the k-value of the membrane was measured as 2.64 which make it suitable for the microprocessor applications.

  1. Microprocessors help in control and beam observation at the CERN PS booster

    Energy Technology Data Exchange (ETDEWEB)

    Baribaud, G.; Benincasa, G.; Horne, P.; Williams, D.

    1977-06-01

    Many applications requiring either the transfer of large amounts of data for simple processing or the repetition of real time calibration of equipment are not easily or rapidly implemented with the present PS computer system, without restricting other uses of the computer. The availability of MOS microprocessors now allows local data processing in the equipment, supplying final results to the central computer system. The microprocessors (..mu..P) and their peripheral circuits are housed in CAMAC modules to be compatible with the equipment now built in CAMAC technology. The ..mu..P module acts as an auxiliary CAMAC controller. The CAMAC crate is linked to the central computer system through a conventional crate controller. In one application, a microprocessor is used to reduce the amount of data to be collected by the central computer system from some 7000 words to 60 thus enabling the continuous monitoring of the shunt current of 60 pulsed magnet power supplies. In another application, a calibration and linearization system is being designed to improve the operational characteristics (pulse-to-pulse intensity modulation, wide range) of the existing hardware used for the acquisition of the beam intensity in the PSB injection line.

  2. On the Evaluation of Two-Center Overlap Integrals over Integer and Noninteger -Center Overlap Integrals over Integer and Noninteger n-Slater-Type Orbitals

    Institute of Scientific and Technical Information of China (English)

    T. Ozdogan, M. Orbay; S. Gümüs

    2002-01-01

    In this study, two-center overlap integrals over Slater-type orbitals (STOs) with integer and noninteger principal quantum numbers in unaligned coordinate systems have been calculated using formulas for overlap integrals in aligned coordinate systems obtained by the author's previous work (T. Ozdogan and M. Orbay, Int. J. Quant. Chem. 87(2002) 15). The obtained results for integer case have been found to be in excellent agreement with the prior literature.On the other hand, to the best of authors knowledge, because of the scarcity of the literatures on the use of noninteger n-STOs in unaligned coordinate systems, the results for noninteger case have been tested with the limit of integer case,and good agreement has been obtained too.

  3. The Single Event Effect Characteristics of the 486-DX4 Microprocessor

    Science.gov (United States)

    Kouba, Coy; Choi, Gwan

    1996-01-01

    This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of

  4. Presolving and regularization in mixed-integer second-order cone optimization

    DEFF Research Database (Denmark)

    Friberg, Henrik Alsing

    Mixed-integer second-order cone optimization is a powerful mathematical framework capable of representing both logical conditions and nonlinear relationships in mathematical models of industrial optimization problems. What is more, solution methods are already part of many major commercial solvers...... both continuous and mixed-integer conic optimization in general, is discovered and treated. This part of the thesis continues the studies of facial reduction preceding the work of Borwein and Wolkowicz [17] in 1981, when the first algorithmic cure for these kinds of reliability issues were formulated....... An important distinction to make between continuous and mixed-integer optimization, however, is that the reliability issues occurring in mixed-integer optimization cannot be blamed on the practitioner’s formulation of the problem. Specifically, as shown, the causes for these issues may well lie within...

  5. Integer Programming Formulation of the Problem of Generating Milton Babbitt's All-partition Arrays

    DEFF Research Database (Denmark)

    Tanaka, Tsubasa; Bemman, Brian; Meredith, David

    2016-01-01

    integer partition of 12. Integer programming (IP) has proven to be effective for solving such combinatorial prob- lems, however, it has never before been applied to the problem addressed in this paper. We introduce a new way of viewing this problem as one in which restricted overlaps between integer......Milton Babbitt (1916–2011) was a composer of twelve-tone serial music noted for creating the all-partition array. The problem of generating an all-partition array involves finding a rectangular array of pitch-class integers that can be partitioned into regions, each of which represents a distinct...... partition regions are allowed. This permits us to describe the problem using a set of linear constraints necessary for IP. In particular, we show that this problem can be defined as a special case of the well-known problem of set-covering (SCP), modified with additional constraints. Due to the difficulty...

  6. The expected variation of random bounded integer sequences of finite length

    OpenAIRE

    Rudolfo Angeles; Don Rawlings; Lawrence Sze; Mark Tiefenbruck

    2005-01-01

    From the enumerative generating function of an abstract adjacency statistic, we deduce the mean and variance of the variation on random permutations, rearrangements, compositions, and bounded integer sequences of finite length.

  7. A Fast Algorithm for Determining the Existence and Value of Integer Roots of N

    CERN Document Server

    Libby, Vibeke

    2010-01-01

    We show that all perfect odd integer squares not divisible by 3, can be usefully written as sqrt(N) = a + 18p, where the constant a is determined by the basic properties of N. The equation can be solved deterministically by an efficient four step algorithm that is solely based on integer arithmetic. There is no required multiplication or division by multiple digit integers, nor does the algorithm need a seed value. It finds the integer p when N is a perfect square, and certifies N as a non-square when the algorithm terminates without a solution. The number of iterations scales approximately as log(sqrt(N)/2) for square roots. The paper also outlines how one of the methods discussed for squares can be extended to finding an arbitrary root of N. Finally, we present a rule that distinguishes products of twin primes from squares.

  8. Reversible Integer Wavelet Transform for the Joint of Image Encryption and Watermarking

    Directory of Open Access Journals (Sweden)

    Bin Wang

    2015-01-01

    Full Text Available In recent years, signal processing in the encrypted domain has attracted considerable research interest, especially embedding watermarking in encrypted image. In this work, a novel joint of image encryption and watermarking based on reversible integer wavelet transform is proposed. Firstly, the plain-image is encrypted by chaotic maps and reversible integer wavelet transform. Then the lossless watermarking is embedded in the encrypted image by reversible integer wavelet transform and histogram modification. Finally an encrypted image containing watermarking is obtained by the inverse integer wavelet transform. What is more, the original image and watermarking can be completely recovered by inverse process. Numerical experimental results and comparing with previous works show that the proposed scheme possesses higher security and embedding capacity than previous works. It is suitable for protecting the image information.

  9. 7th Conference on Non-Integer Order Calculus and Its Applications

    CERN Document Server

    Dworak, Paweł

    2016-01-01

    This volume is devoted to presentation of new results of research on systems of non-integer order, called also fractional systems. Their analysis and practical implementation have been the object of spontaneous development for a few last decades. The fractional order models can depict a physical plant better than the classical integer order ones. This covers different research fields such as insulator properties, visco-elastic materials, electrodynamic, electrothermal, electrochemical, economic processes modelling etc. On the other hand fractional controllers often outperform their integer order counterparts. This volume contains new ideas and examples of implementation, theoretical and pure practical aspects of using a non-integer order calculus. It is divided into four parts covering: mathematical fundamentals, modeling and approximations, controllability, observability and stability problems and practical applications of fractional control systems. The first part expands the base of tools and methods of th...

  10. The expected variation of random bounded integer sequences of finite length

    Directory of Open Access Journals (Sweden)

    Rudolfo Angeles

    2005-09-01

    Full Text Available From the enumerative generating function of an abstract adjacency statistic, we deduce the mean and variance of the variation on random permutations, rearrangements, compositions, and bounded integer sequences of finite length.

  11. The Number of Representations of an Integer as a Sum of Eight Squares

    Institute of Scientific and Technical Information of China (English)

    林甲富

    2002-01-01

    Two identities are obtained by Jacobi's triple product identity and some basic operators.By applying these identities,Jacobi's theorem for the number of representations of an integer as a sum of eight squares is easily proved.

  12. Edge states and integer quantum Hall effect in topological insulator thin films.

    Science.gov (United States)

    Zhang, Song-Bo; Lu, Hai-Zhou; Shen, Shun-Qing

    2015-08-25

    The integer quantum Hall effect is a topological state of quantum matter in two dimensions, and has recently been observed in three-dimensional topological insulator thin films. Here we study the Landau levels and edge states of surface Dirac fermions in topological insulators under strong magnetic field. We examine the formation of the quantum plateaux of the Hall conductance and find two different patterns, in one pattern the filling number covers all integers while only odd integers in the other. We focus on the quantum plateau closest to zero energy and demonstrate the breakdown of the quantum spin Hall effect resulting from structure inversion asymmetry. The phase diagrams of the quantum Hall states are presented as functions of magnetic field, gate voltage and chemical potential. This work establishes an intuitive picture of the edge states to understand the integer quantum Hall effect for Dirac electrons in topological insulator thin films.

  13. 5th Conference on Non-integer Order Calculus and Its Applications

    CERN Document Server

    Kacprzyk, Janusz; Baranowski, Jerzy

    2013-01-01

    This volume presents various aspects of non-integer order systems, also known as fractional systems, which have recently attracted an increasing attention in the scientific community of systems science, applied mathematics, control theory. Non-integer systems have become relevant for many fields of science and technology exemplified by the modeling of signal transmission, electric noise, dielectric polarization, heat transfer, electrochemical reactions, thermal processes,  acoustics, etc. The content is divided into six parts, every of which considers one of the currently relevant problems. In the first part the Realization problem is discussed, with a special focus on positive systems. The second part considers stability of certain classes of non-integer order systems with and without delays. The third part is focused on such important aspects as controllability, observability and optimization especially in discrete time. The fourth part is focused on distributed systems where non-integer calculus leads to ...

  14. On the Branch and Cut Method for Multidimentional Mixed Integer Knapsack Problem

    OpenAIRE

    Mostafa Khorramizadeh; Zahra Rakhshandehroo

    2014-01-01

    In this paper, we examine the effect of the feasibility pump (FP) method on the branch and cut method for solving the multidimentional mixed integer knapsack problem. The feasibility pump is a heuristic method, trying to compute a feasible solution for mixed integer pro- gramming problems. Moreover, we consider two efficient strategies for using the feasibility pump in a branch and cut method and present some tables of numerical results, concerning the application and comparison of using thes...

  15. Non-integer Quantum Transition, a True Non-perturbation Effect in Laser-Atom Interaction

    Institute of Scientific and Technical Information of China (English)

    ZHANG Qi-Ren

    2007-01-01

    We show that in the quantum transition of an atom interacting with an intense laser of circular frequencyω, the energy difference between the initial and the final states of the atom is not necessarily an integer multiple of the quantum energy (h)ω. This kind of non-integer transition is a true non-perturbation effect in laser-atom interaction.

  16. A One-parameter Filled Function Method for Nonlinear Integer Programming

    Institute of Scientific and Technical Information of China (English)

    2005-01-01

    This paper gives a new definition of the filled function for nonlinear integer programming problem. A filled function satisfying our definition is presented. This function contains only one parameter. The properties of the proposed filled function and the method using this filled function to solve nonlinear integer programming problem are also discussed. Numerical results indicate the efficiency and reliability of the proposed filled function algorithm.

  17. One-parameter quasi-filled function algorithm for nonlinear integer programming

    Institute of Scientific and Technical Information of China (English)

    SHANG You-lin; HAN Bo-shun

    2005-01-01

    A definition of the quasi-filled function for nonlinear integer programming problem is given in this paper. A quasi-filled function satisfying our definition is presented. This function contains only one parameter. The properties of the proposed quasi-filled function and the method using this quasi-filled function to solve nonlinear integer programming problem are also discussed in this paper. Numerical results indicated the efficiency and reliability of the proposed quasi-filled function algorithm.

  18. A universal first order formula defining the ring of integers in a number field

    CERN Document Server

    Park, Jennifer

    2012-01-01

    We show that the complement of the ring of integers in a number field K is Diophantine. This means the set of ring of integers in K can be written as {t in K | for all x_1, ..., x_N in K, f(t,x_1, ..., x_N) is not 0}. We will use global class field theory and generalize the ideas originating from Koenigsmann's recent result giving a universal first order formula for Z in Q.

  19. DESIGN STUDY: INTEGER SUBTRACTION OPERATION TEACHING LEARNING USING MULTIMEDIA IN PRIMARY SCHOOL

    Directory of Open Access Journals (Sweden)

    Rendi Muhammad Aris

    2016-12-01

    Full Text Available This study aims to develop a learning trajectory to help students understand concept of subtraction of integers using multimedia in the fourth grade. This study is thematic integrative learning in Curriculum 2013 PMRI based. The method used is design research consists of three stages; preparing for the experiment, design experiment, retrospective analysis. The studied was conducted on 20 students of grade four SDN 1 Muara Batun, OKI. The activities of students in this study consisted of six learning trajectories. The first activity asks the students to classify heroism and non-heroism acts, summarize, and classify integers and non-integer. The second activity asks the students to answer the questions in the film given. The third activity asks students to count the remaining gravel in the film. The fourth activity asks students to count remaining spent money in the film. The fifth activity invites students to play rubber seeds in the bag. The last activity asks students to answer the questions in the student worksheet. The media used along the learning activities are a ruler, rubber seed, student worksheet, money, gravel, and film. The results indicate that the learning trajectory using multimedia help students understand the concept of integer subtraction integer. Keywords: Subtraction Integer, PMRI, Multimedia DOI: http://dx.doi.org/10.22342/jme.8.1.3233.95-102

  20. Assessment of transfemoral amputees using a passive microprocessor-controlled knee versus an active powered microprocessor-controlled knee for level walking.

    Science.gov (United States)

    Creylman, Veerle; Knippels, Ingrid; Janssen, Paul; Biesbrouck, Evelyne; Lechler, Knut; Peeraer, Louis

    2016-12-19

    In transfemoral (TF) amputees, the forward propulsion of the prosthetic leg in swing has to be mainly carried out by hip muscles. With hip strength being the strongest predictor to ambulation ability, an active powered knee joint could have a positive influence, lowering hip loading and contributing to ambulation mobility. To assess this, gait of four TF amputees was measured for level walking, first while using a passive microprocessor-controlled prosthetic knee (P-MPK), subsequently while using an active powered microprocessor-controlled prosthetic knee (A-MPK). Furthermore, to assess long-term effects of the use of an A-MPK, a 4-weeks follow-up case study was performed. The kinetics and kinematics of the gait of four TF amputees were assessed while walking with subsequently the P-MPK and the A-MPK. For one amputee, a follow-up study was performed: he used the A-MPK for 4 weeks, his gait was measured weekly. The range of motion of the knee was higher on both the prosthetic and the sound leg in the A-MPK compared to the P-MPK. Maximum hip torque (HT) during early stance increased for the prosthetic leg and decreased for the sound leg with the A-MPK compared to the P-MPK. During late stance, the maximum HT decreased for the prosthetic leg. The difference between prosthetic and sound leg for HT disappeared when using the A-MPK. Also, an increase in stance phase duration was observed. The follow-up study showed an increase in confidence with the A-MPK over time. Results suggested that, partially due to an induced knee flexion during stance, HT can be diminished when walking with the A-MPK compared to the P-MPK. The single case follow-up study showed positive trends indicating that an adaptation time is beneficial for the A-MPK.

  1. Pain and Efficacy Rating of a Microprocessor-Controlled Metered Injection System for Local Anaesthesia in Minor Hand Surgery

    Directory of Open Access Journals (Sweden)

    André S. Nimigan

    2011-01-01

    Full Text Available Purpose. Little attention has been given to syringe design and local anaesthetic administration methods. A microprocessor-controlled anaesthetic delivery device has become available that may minimize discomfort during injection. The purpose of this study was to document the pain experience associated with the use of this system and to compare it with use of a conventional syringe. Methods. A prospective, randomized clinical trial was designed. 40 patients undergoing carpal tunnel release were block randomized according to sex into a two groups: a traditional syringe group and a microprocessor-controlled device group. The primary outcome measure was surgical pain and local anaesthetic administration pain. Secondary outcomes included volume of anaesthetic used and injection time. Results. Analysis showed that equivalent anaesthesia was achieved in the microprocessor-controlled group despite using a significantly lower volume of local anaesthetic (P=.0002. This same group, however, has significantly longer injection times (P<.0001. Pain during the injection process or during surgery was not different between the two groups. Conclusions. This RCT comparing traditional and microprocessor controlled methods of administering local anaesthetic showed similar levels of discomfort in both groups. While the microprocessor-controlled group used less volume, the total time for the administration was significantly greater.

  2. Pain and efficacy rating of a microprocessor-controlled metered injection system for local anaesthesia in minor hand surgery.

    Science.gov (United States)

    Nimigan, André S; Gan, Bing Siang

    2011-01-01

    Purpose. Little attention has been given to syringe design and local anaesthetic administration methods. A microprocessor-controlled anaesthetic delivery device has become available that may minimize discomfort during injection. The purpose of this study was to document the pain experience associated with the use of this system and to compare it with use of a conventional syringe. Methods. A prospective, randomized clinical trial was designed. 40 patients undergoing carpal tunnel release were block randomized according to sex into a two groups: a traditional syringe group and a microprocessor-controlled device group. The primary outcome measure was surgical pain and local anaesthetic administration pain. Secondary outcomes included volume of anaesthetic used and injection time. Results. Analysis showed that equivalent anaesthesia was achieved in the microprocessor-controlled group despite using a significantly lower volume of local anaesthetic (P = .0002). This same group, however, has significantly longer injection times (P microprocessor controlled methods of administering local anaesthetic showed similar levels of discomfort in both groups. While the microprocessor-controlled group used less volume, the total time for the administration was significantly greater.

  3. A reversibility-gain model for integer Karhunen-Loève transform design in video coding

    Institute of Scientific and Technical Information of China (English)

    Xing-guo ZHU; Lu YU

    2015-01-01

    Karhunen-Loève transform (KLT) is the optimal transform that minimizes distortion at a given bit allocation for Gaussian source. As a KLT matrix usually contains non-integers, integer-KLT design is a classical problem. In this paper, a joint reversibility-gain (R-G) model is proposed for integer-KLT design in video coding. Specifically, the 'reversibility' is modeled according to distortion analysis in using forward and inverse integer transform without quantization. It not only measures how invertible a transform is, but also bounds the distortion introduced by the non-orthonormal integer transform process. The 'gain' means transform coding gain (TCG), which is a widely used criterion for transform design in video coding. Since KLT maximizes the TCG under some assumptions, here we define the TCG loss ratio (LR) to measure how much coding gain an integer-KLT loses when compared with the original KLT. Thus, the R-G model can be explained as follows: subject to a certain TCG LR, an integer- KLT with the best reversibility is the optimal integer transform for a given non-integer-KLT. Experimental results show that the R-G model can guide the design of integer-KLTs with good performance.

  4. New concepts for a microprocessor oriented long term intelligent monitoring of newborns.

    Science.gov (United States)

    Vasseur, C P; Couvreur, M C; Toulotte, J M; Dubois, O

    1980-07-01

    This paper is based on the utilization of the very elementary principle of linear regression used in a recursive way. This technique tested on electrophysiological signals readily leads to the conception of a monitoring system built on a biprocessor unit. In a clinical context, the use of microprocessors leads then to the design of very compact devices including the capability of distributed processing which embrances the concept of intelligent monitoring. Finally, a proposal is given for the realization of a complete monitoring control desk (MCD) devoted to the survey of eight patients.

  5. Application of Microprocessor-Based Equipment in Nuclear Power Plants - Technical Basis for a Qualification Methodology

    Energy Technology Data Exchange (ETDEWEB)

    Korsah, K.

    2001-08-24

    This document (1) summarizes the most significant findings of the ''Qualification of Advanced Instrumentation and Control (I&C) Systems'' program initiated by the Nuclear Regulatory Commission (NRC); (2) documents a comparative analysis of U.S. and European qualification standards; and (3) provides recommendations for enhancing regulatory guidance for environmental qualification of microprocessor-based safety-related systems. Safety-related I&C system upgrades of present-day nuclear power plants, as well as I&C systems of Advanced Light-Water Reactors (ALWRs), are expected to make increasing use of microprocessor-based technology. The Nuclear Regulatory Commission (NRC) recognized that the use of such technology may pose environmental qualification challenges different from current, analog-based I&C systems. Hence, it initiated the ''Qualification of Advanced Instrumentation and Control Systems'' program. The objectives of this confirmatory research project are to (1) identify any unique environmental-stress-related failure modes posed by digital technologies and their potential impact on the safety systems and (2) develop the technical basis for regulatory guidance using these findings. Previous findings from this study have been documented in several technical reports. This final report in the series documents a comparative analysis of two environmental qualification standards--Institute of Electrical and Electronics Engineers (IEEE) Std 323-1983 and International Electrotechnical Commission (IEC) 60780 (1998)--and provides recommendations for environmental qualification of microprocessor-based systems based on this analysis as well as on the findings documented in the previous reports. The two standards were chosen for this analysis because IEEE 323 is the standard used in the U.S. for the qualification of safety-related equipment in nuclear power plants, and IEC 60780 is its European counterpart. In addition, the IEC

  6. THE BIOLOGICAL MICROPROCESSOR, OR HOW TO BUILD A COMPUTER WITH BIOLOGICAL PARTS

    Directory of Open Access Journals (Sweden)

    Gerd HG Moe-Behrens

    2013-04-01

    Full Text Available Systemics, a revolutionary paradigm shift in scientific thinking, with applications in systems biology, and synthetic biology, have led to the idea of using silicon computers and their engineering principles as a blueprint for the engineering of a similar machine made from biological parts. Here we describe these building blocks and how they can be assembled to a general purpose computer system, a biological microprocessor. Such a system consists of biological parts building an input / output device, an arithmetic logic unit, a control unit, memory, and wires (busses to interconnect these components. A biocomputer can be used to monitor and control a biological system.

  7. A microprocessor-based control system for the Vienna PDS microdensitometer

    Science.gov (United States)

    Jenkner, H.; Stoll, M.; Hron, J.

    1984-01-01

    The Motorola Exorset 30 system, based on a Motorola 6809 microprocessor which serves as control processor for the microdensitometer is presented. User communication and instrument control are implemented in this syatem; data transmission to a host computer is provided via standard interfaces. The Vienna PDS system (VIPS) software was developed in BASIC and M6809 assembler. It provides efficient user interaction via function keys and argument input in a menu oriented environment. All parameters can be stored on, and retrieved from, minifloppy disks, making it possible to set up large scanning tasks. Extensive user information includes continuously updated status and coordinate displays, as well as a real time graphic display during scanning.

  8. A low cost matching motion estimation sensor based on the NIOS II microprocessor.

    Science.gov (United States)

    González, Diego; Botella, Guillermo; Meyer-Baese, Uwe; García, Carlos; Sanz, Concepción; Prieto-Matías, Manuel; Tirado, Francisco

    2012-09-27

    This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system.

  9. Development of a microprocessor controller for stand-alone photovoltaic power systems

    Science.gov (United States)

    Millner, A. R.; Kaufman, D. L.

    1984-01-01

    A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.

  10. MONICA - a programmable microprocessor for track recognition in an e+e- experiment at PETRA

    CERN Document Server

    Schildt, P; Wermes, N

    1981-01-01

    The microprocessor device MONICA is used in the TASSO experiment at PETRA. Its task is to reconstruct events in the cylindrical driftchamber on-line. Used as an event filter MONICA provides a 2 prong trigger without any further requirements. The speed of the processor (event reconstruction times must be in the order of 1 ms) is achieved by a 4*4 bit slice processor in ECL technology, content addressable memories and table look-up. The track finding efficiency is 80%. (6 refs).

  11. Microprocessor, Setx, Xrn2, and Rrp6 co-operate to induce premature termination of transcription by RNAPII.

    Science.gov (United States)

    Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

    2012-09-14

    Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 3'-5' exoribonuclease, Rrp6, to initiate RNAPII pausing and premature termination at the HIV-1 promoter through cleavage of the stem-loop RNA, TAR. Rrp6 further processes the cleavage product, which generates a small RNA that is required to mediate potent transcriptional repression and chromatin remodeling at the HIV-1 promoter. Using chromatin immunoprecipitation coupled to high-throughput sequencing (ChIP-seq), we identified cellular gene targets whose transcription is modulated by microprocessor. Our study reveals RNAPII pausing and premature termination mediated by the co-operative activity of ribonucleases, Drosha/Dgcr8, Xrn2, and Rrp6, as a regulatory mechanism of RNAPII-dependent transcription elongation.

  12. Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

    Directory of Open Access Journals (Sweden)

    Ching-Hwa Cheng

    2013-01-01

    Full Text Available The existence of structural, control, and data hazards presents a major challenge in designing an advanced pipeline/superscalar microprocessor. An efficient memory hierarchy cache-RAM-Disk design greatly enhances the microprocessor's performance. However, there are complex relationships among the memory hierarchy and the functional units in the microprocessor. Most past architectural design simulations focus on the instruction hazard detection/prevention scheme from the viewpoint of function units. This paper emphasizes that additional inboard memory can be well utilized to handle the hazardous conditions. When the instruction meets hazardous issues, the memory latency can be utilized to prevent performance degradation due to the hazard prevention mechanism. By using the proposed technique, a better architectural design can be rapidly validated by an FPGA at the start of the design stage. In this paper, the simulation results prove that our proposed methodology has a better performance and less power consumption compared to the conventional hazard prevention technique.

  13. Using Integer Clocks to Verify the Timing-Sync Sensor Network Protocol

    Science.gov (United States)

    Huang, Xiaowan; Singh, Anu; Smolka, Scott A.

    2010-01-01

    We use the UPPAAL model checker for Timed Automata to verify the Timing-Sync time-synchronization protocol for sensor networks (TPSN). The TPSN protocol seeks to provide network-wide synchronization of the distributed clocks in a sensor network. Clock-synchronization algorithms for sensor networks such as TPSN must be able to perform arithmetic on clock values to calculate clock drift and network propagation delays. They must be able to read the value of a local clock and assign it to another local clock. Such operations are not directly supported by the theory of Timed Automata. To overcome this formal-modeling obstacle, we augment the UPPAAL specification language with the integer clock derived type. Integer clocks, which are essentially integer variables that are periodically incremented by a global pulse generator, greatly facilitate the encoding of the operations required to synchronize clocks as in the TPSN protocol. With this integer-clock-based model of TPSN in hand, we use UPPAAL to verify that the protocol achieves network-wide time synchronization and is devoid of deadlock. We also use the UPPAAL Tracer tool to illustrate how integer clocks can be used to capture clock drift and resynchronization during protocol execution

  14. Mixed integer programming for the resolution of GPS carrier phase ambiguities

    CERN Document Server

    Xu, Peiliang; Lachapelle, Gerard

    2010-01-01

    This arXiv upload is to clarify that the now well-known sorted QR MIMO decoder was first presented in the 1995 IUGG General Assembly. We clearly go much further in the sense that we directly incorporated reduction into this one step, non-exact suboptimal integer solution. Except for these first few lines up to this point, this paper is an unaltered version of the paper presented at the IUGG1995 Assembly in Boulder. Ambiguity resolution of GPS carrier phase observables is crucial in high precision geodetic positioning and navigation applications. It consists of two aspects: estimating the integer ambiguities in the mixed integer observation model and examining whether they are sufficiently accurate to be fixed as known nonrandom integers. We shall discuss the first point in this paper from the point of view of integer programming. A one-step nonexact approach is proposed by employing minimum diagonal pivoting Gaussian decompositions, which may be thought of as an improvement of the simple rounding-off method, ...

  15. A time series model: First-order integer-valued autoregressive (INAR(1))

    Science.gov (United States)

    Simarmata, D. M.; Novkaniza, F.; Widyaningsih, Y.

    2017-07-01

    Nonnegative integer-valued time series arises in many applications. A time series model: first-order Integer-valued AutoRegressive (INAR(1)) is constructed by binomial thinning operator to model nonnegative integer-valued time series. INAR (1) depends on one period from the process before. The parameter of the model can be estimated by Conditional Least Squares (CLS). Specification of INAR(1) is following the specification of (AR(1)). Forecasting in INAR(1) uses median or Bayesian forecasting methodology. Median forecasting methodology obtains integer s, which is cumulative density function (CDF) until s, is more than or equal to 0.5. Bayesian forecasting methodology forecasts h-step-ahead of generating the parameter of the model and parameter of innovation term using Adaptive Rejection Metropolis Sampling within Gibbs sampling (ARMS), then finding the least integer s, where CDF until s is more than or equal to u . u is a value taken from the Uniform(0,1) distribution. INAR(1) is applied on pneumonia case in Penjaringan, Jakarta Utara, January 2008 until April 2016 monthly.

  16. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Science.gov (United States)

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  17. Microprocessors & their operating systems a comprehensive guide to 8, 16 & 32 bit hardware, assembly language & computer architecture

    CERN Document Server

    Holland, R C

    1989-01-01

    Provides a comprehensive guide to all of the major microprocessor families (8, 16 and 32 bit). The hardware aspects and software implications are described, giving the reader an overall understanding of microcomputer architectures. The internal processor operation of each microprocessor device is presented, followed by descriptions of the instruction set and applications for the device. Software considerations are expanded with descriptions and examples of the main high level programming languages (BASIC, Pascal and C). The book also includes detailed descriptions of the three main operatin

  18. Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

    Science.gov (United States)

    Delaat, J. C.; Soeder, J. F.

    1983-01-01

    High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

  19. DGCR8 HITS-CLIP reveals novel functions for the Microprocessor.

    Science.gov (United States)

    Macias, Sara; Plass, Mireya; Stajuda, Agata; Michlewski, Gracjan; Eyras, Eduardo; Cáceres, Javier F

    2012-08-01

    The Drosha-DGCR8 complex (Microprocessor) is required for microRNA (miRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as the endonuclease. Using high-throughput sequencing and cross-linking immunoprecipitation (HITS-CLIP) we identified RNA targets of DGCR8 in human cells. Unexpectedly, miRNAs were not the most abundant targets. DGCR8-bound RNAs also comprised several hundred mRNAs as well as small nucleolar RNAs (snoRNAs) and long noncoding RNAs. We found that the Microprocessor controlled the abundance of several mRNAs as well as of MALAT1. By contrast, DGCR8-mediated cleavage of snoRNAs was independent of Drosha, suggesting the involvement of DGCR8 in cellular complexes with other endonucleases. Binding of DGCR8 to cassette exons is a new mechanism for regulation of the relative abundance of alternatively spliced isoforms. These data provide insights in the complex role of DGCR8 in controlling the fate of several classes of RNAs.

  20. The microprocessor component, DGCR8, is essential for early B-cell development in mice.

    Science.gov (United States)

    Brandl, Andreas; Daum, Patrick; Brenner, Sven; Schulz, Sebastian R; Yap, Desmond Yat-Hin; Bösl, Michael R; Wittmann, Jürgen; Schuh, Wolfgang; Jäck, Hans-Martin

    2016-12-01

    microRNAs (miRNAs) are important posttranscriptional regulators during hematopoietic lineage commitment and lymphocyte development. Mature miRNAs are processed from primary miRNA transcripts in two steps by the microprocessor complex, consisting of Drosha and its partner DiGeorge Critical Region 8 (DGCR8), and the RNAse III enzyme, Dicer. Conditional ablations of Drosha and Dicer have established the importance of both RNAses in B- and T-cell development. Here, we show that a cre-mediated B-cell specific deletion of DGCR8 in mice results in a nearly complete maturation block at the transition from the pro-B to the pre-B cell stage, and a failure to upregulate Ig μ heavy chain expression in pro-B cells. Furthermore, we found that the death of freshly isolated DGCR8-deficient pro-B cells could be partially prevented by enforced Bcl2 expression. We conclude from these findings that the microprocessor component DGCR8 is essential for survival and differentiation of early B-cell progenitors.

  1. Mapping of equipment with a microprocessor controlled X-Y moving stage

    CERN Document Server

    Bermond, M; Guglielmi, L; Jaeger, J J; Szafran, S

    1981-01-01

    Summary form only given, as follows. Mapping is a crucial part of equipment calibration to ensure uniformity of response. Since mechanical movements are involved, automation requires some caution to avoid possible damage. To increase security, the acquisition processor, where the program may be frequently changed by the user, is distinct from the microprocessor which actually controls the mechanics with an noncorruptible program in EPROM. The mapped equipment is kept fixed and vertical while a sensing/exciting probe can be moved in 2 dimensions over 2.50*2.50 m/sup 2/ by the action of two printed circuit motors. The motor speeds are controlled through a DAC interface and the position of the moving stage is measured within 1 mm by optical sensing of two cheap workshop rules. The Motorola 6800 microprocessor also controls various security checks and communicates with the outside world through simple commands on a standard RS 232 C serial interface. This allows connection to a simple TTY/VDU or to any other proc...

  2. Electric protections based in microprocessors in power plants; Protecciones electricas basadas en microprocesadores en centrales generadoras

    Energy Technology Data Exchange (ETDEWEB)

    Libreros, Domitilo; Castanon Jimenez, Jose Ismael [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1987-12-31

    This article is centered around the substitution of the conventional electric protections of a power plant in connection type unit for protections based in microprocessors. A general model of conventional protection of a power plant is described and the number of analogic and digital signals that intervene in that model are quantified. A model is setup for power plant protection with microprocessors, analyzing each one of the modules that would form it. Finally, the algorithms to carry on such protection are presented. [Espanol] Este articulo se centra en torno a la sustitucion de las protecciones electricas convencionales de una central generadora en conexion tipo unidad por protecciones basadas en microprocesadores. Se describe el modelo general de proteccion convencional de una central generadora y se cuantifica el numero de senales analogicas y digitales que interviene en dicho modelo. Se propone un modelo para proteccion de centrales generadoras mediante microprocesadores, analizandose cada uno de los modulos que lo conformarian. Finalmente, se presentan los algoritmos para realizar dicha proteccion.

  3. Design of a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs

    Energy Technology Data Exchange (ETDEWEB)

    Tanaka, M [Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603 (Japan); Kawamoto, T [Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603 (Japan); Yamanashi, Y [Yokohama National University, 79-5 Tokiwa-dai, Hodogaya-ku, Yokohama 240-8501 (Japan); Kamiya, Y [Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603 (Japan); Akimoto, A [Yokohama National University, 79-5 Tokiwa-dai, Hodogaya-ku, Yokohama 240-8501 (Japan); Fujiwara, K [Yokohama National University, 79-5 Tokiwa-dai, Hodogaya-ku, Yokohama 240-8501 (Japan); Fujimaki, A [Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8603 (Japan); Yoshikawa, N [Yokohama National University, 79-5 Tokiwa-dai, Hodogaya-ku, Yokohama 240-8501 (Japan); Terai, H [National Institute of Information and Communications Technology, 588-2 Iwaoka, Nishi-ku, Kobe 651-2492 (Japan); Yorozu, S [International Superconductivity Technology Center/Superconductivity Research Laboratory, 34 Miyukigaoka, Tsukuba 305-8501 (Japan)

    2006-05-15

    We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 {beta}. In the CORE1 {beta}, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 {beta} chip by using the NEC 2.5 kA cm{sup -2} niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.

  4. Design of a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs

    Science.gov (United States)

    Tanaka, M.; Kawamoto, T.; Yamanashi, Y.; Kamiya, Y.; Akimoto, A.; Fujiwara, K.; Fujimaki, A.; Yoshikawa, N.; Terai, H.; Yorozu, S.

    2006-05-01

    We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm-2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.

  5. An extension of the Lovasz Local Lemma, and its applications to integer programming

    Energy Technology Data Exchange (ETDEWEB)

    Srinivasan, A. [National univ. of Singapore (Singapore)

    1996-12-31

    The Lovasz Local Lemma (LLL) is a powerful tool in proving the existence of rare events. We present an extension of this lemma, which works well when the event to be shown to exist is a conjunction of individual events, each of which asserts that a random variable does not deviate much from its mean. We consider three classes of NP-hard integer programs: minimax, packing, and covering integer programs. A key technique, randomized rounding of linear relaxations, was developed by Raghavan & Thompson to derive good approximation algorithms for such problems. We use our extended LLL to prove that randomized rounding produces, with non-zero probability, much better feasible solutions than known be- fore, if the constraint matrices of these integer programs are sparse (e.g., VLSI routing using short paths, problems on hypergraphs with small dimension/degree). We also generalize the method of pessimistic estimators due to Raghavan, to constructivize our packing and covering results.

  6. Exponential distribution-based genetic algorithm for solving mixed-integer bilevel programming problems

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Two classes of mixed-integer nonlinear bilevel programming problems are discussed. One is that the follower's functions are separable with respect to the follower's variables, and the other is that the follower's functions are convex if the follower's variables are not restricted to integers. A genetic algorithm based on an exponential distribution is proposed for the aforementioned problems. First, for each fixed leader's variable x, it is proved that the optimal solution y of the follower's mixed-integer programming can be obtained by solving associated relaxed problems, and according to the convexity of the functions involved, a simplified branch and bound approach is given to solve the follower's programming for the second class of problems. Furthermore, based on an exponential distribution with a parameter A, a new crossover operator is designed in which the best individuals are used to generate better offspring of crossover. The simulation results illustrate that the proposed algorithm is efficient and robust.

  7. ALLOCATING REPAIRABLE SYSTEM'S RELIABILITY SUBJECT TO MINIMAL TOTAL COST - AN INTEGER PROGRAMMING APPROACH

    Institute of Scientific and Technical Information of China (English)

    Ahmad A. Moreb

    2007-01-01

    Reliability allocation problem is commonly treated using a closed-form expression relating the cost to reliability. A recent approach has introduced the use of discrete integer technique for un-repairable systems. This research addresses the allocation problem for repairable systems. It presents an integer formulation for finding the optimum selection of components based on the integer values of their Mean Time to Failure (MTTF) and Mean Time to Repair (MTTR). The objective is to minimize the total cost under a system reliability constraint, in addition to other physical constraints. Although, a closed-form expression relating the cost to reliability may not be a linear; however, in this research, the objective function will always be linear regardless of the shape of the equivalent continuous closed-form function. An example is solved using the proposed method and compared with the solution of the continuous closed-form version. The formulation for all possible system configurations, components and subsystems are also considered.

  8. A Polynomial Time Algorithm for a Special Case of Linear Integer Programming

    CERN Document Server

    Ghasemiesfeh, Golnaz; Tabesh, Yahya

    2011-01-01

    According to the wide use of integer programming in many fields, affords toward finding and solving sub classes of these problems which are solvable in polynomial time seems to be important and useful. Integer linear programming (ILP) problems have the general form: $Min \\{C^{T}x: Ax=b, x\\geq 0, x\\in Z^{n}\\}$ where $Z^{n}$ is the set of n-dimensional integer vectors. Algorithmic solution of ILP is at great interest, in this paper we have presented a polynomial algorithm for a special case of the ILP problems; we have used a graph theoretical formulation of the problem which leads to an $O[mn(m+n)]$ solution where $m$ and $n$ are dimensions of coefficient matrix $X$.

  9. Cubic one-regular graphs of order twice a square-free integer

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    A graph is one-regular if its automorphism group acts regularly on the set of its arcs.Let n be a square-free integer.In this paper,we show that a cubic one-regular graph of order 2n exists if and only if n=3tp1p2…ps≥13,where t≤1,s≥1 and pi’s are distinct primes such that 3|(Pi—1). For such an integer n,there are 2s-1 non-isomorphic cubic one-regular graphs of order 2n,which are all Cayley graphs on the dihedral group of order 2n.As a result,no cubic one-regular graphs of order 4 times an odd square-free integer exist.

  10. Allocating the Fixed Resources and Setting Targets in Integer Data Envelopment Analysis

    Directory of Open Access Journals (Sweden)

    Kobra Gholami

    2013-11-01

    Full Text Available Data envelopment analysis (DEA is a non-parametric approach to evaluate a set of decision making units (DMUs consuming multiple inputs to produce multiple outputs. Formally, DEA use to estimate the efficiency score into the empirical efficient frontier. Also, DEA can be used to allocate resources and set targets for future forecast. The data are continuous in the standard DEA model whereas there are many problems in the real life that data must be integer such as number of employee, machinery, expert and so on. Thus in this paper we propose an approach to allocate fixed resources and set fixed targets with selective integer assumption that is based on an integer data envelopment analysis (IDEA approach for the first time. The major aim in this approach is preserving the efficiency score of DMUs. We use the concept of benchmarking to reach this aim. The numerical example gets to illustrate the applicability of the proposed method.

  11. On 4D, N = 1 Massless Gauge Superfields of Higher Superspin: Integer Case

    CERN Document Server

    Gates,, S James

    2013-01-01

    We present an alternative method of exploring the component structure of an integer super-helicity Y=s (for any integers) irreducible representation of the Super-Poincare group. We use it to derive the component action and the SUSY transformation laws. The effectiveness of this approach is based on the equations of motion and their properties, like Bianchi identities. These equations are generated by the superspace action when it is expressed in terms of prepotentials. For that reason we reproduce the superspace action for integer superspin, using unconstrained superfields. The appropriate, to use, superfields are dictated by the representation theory of the group and the requirement that there is a smooth limit between the massive and massless case.

  12. Property study of integer wavelet transform lossless compression coding based on lifting scheme

    Science.gov (United States)

    Xie, Cheng Jun; Yan, Su; Xiang, Yang

    2006-01-01

    In this paper the algorithms and its improvement of integer wavelet transform combining SPIHT and arithmetic coding in image lossless compression is mainly studied. The experimental result shows that if the order of low-pass filter vanish matrix is fixed, the improvement of compression effect is not evident when invertible integer wavelet transform is satisfied and focusing of energy property monotonic increase with transform scale. For the same wavelet bases, the order of low-pass filter vanish matrix is more important than the order of high-pass filter vanish matrix in improving the property of image compression. Integer wavelet transform lossless compression coding based on lifting scheme has no relation to the entropy of image. The effect of compression is depended on the the focuing of energy property of image transform.

  13. Metamorphic Testing Integer Overflow Faults of Mission Critical Program: A Case Study

    Directory of Open Access Journals (Sweden)

    Zhanwei Hui

    2013-01-01

    Full Text Available For mission critical programs, integer overflow is one of the most dangerous faults. Different testing methods provide several effective ways to detect the defect. However, it is hard to validate the testing outputs, because the oracle of testing is not always available or too expensive to get, unless the program throws an exception obviously. In the present study, the authors conduct a case study, where the authors apply a metamorphic testing (MT method to detect the integer overflow defect and alleviate the oracle problem in testing critical program of Traffic Collision Avoidance System (TCAS. Experimental results show that, in revealing typical integer mutations, compared with traditional safety property testing method, MT with a novel symbolic metamorphic relation is more effective than the traditional method in some cases.

  14. Spin analogs of superconductivity and integer quantum Hall effect in an array of spin chains

    Science.gov (United States)

    Hill, Daniel; Kim, Se Kwon; Tserkovnyak, Yaroslav

    2017-05-01

    Motivated by the successful idea of using weakly coupled quantum electronic wires to realize the quantum Hall effects and the quantum spin Hall effects, we theoretically study two systems composed of weakly coupled quantum spin chains within the mean-field approximations, which can exhibit spin analogs of superconductivity and the integer quantum Hall effect. First, a certain bilayer of two arrays of interacting spin chains is mapped, via the Jordan-Wigner transformation, to an attractive Hubbard model that exhibits fermionic superconductivity, which corresponds to spin superconductivity in the original spin Hamiltonian. Secondly, an array of spin-orbit-coupled spin chains in the presence of a suitable external magnetic field is transformed to an array of quantum wires that exhibits the integer quantum Hall effect, which translates into its spin analog in the spin Hamiltonian. The resultant spin superconductivity and spin integer quantum Hall effect can be characterized by their ability to transport spin without any resistance.

  15. On a problem of Arnold: the average multiplicative order of a given integer

    CERN Document Server

    Kurlberg, Par

    2011-01-01

    For g,n coprime integers, let l_g(n) denote the multiplicative order of g modulo n. Motivated by a conjecture of Arnold, we study the average of l_g(n) as n <= x ranges over integers coprime to g, and x tending to infinity. Assuming the Generalized Riemann Hypothesis, we show that this average is essentially as large as the average of the Carmichael lambda function. We also determine the asymptotics of the average of l_g(p) as p <= x ranges over primes.

  16. Function projective synchronization between integer-order and stochastic fractional-order nonlinear systems.

    Science.gov (United States)

    Geng, Lingling; Yu, Yongguang; Zhang, Shuo

    2016-09-01

    In this paper, the function projective synchronization between integer-order and stochastic fractional-order nonlinear systems is investigated. Firstly, according to the stability theory of fractional-order systems and tracking control, a controller is designed. At the same time, based on the orthogonal polynomial approximation, the method of transforming stochastic error system into an equivalent deterministic system is given. Thus, the stability of the stochastic error system can be analyzed through its equivalent deterministic one. Finally, to demonstrate the effectiveness of the proposed scheme, the function projective synchronization between integer-order Lorenz system and stochastic fractional-order Chen system is studied.

  17. An approach towards the proof of the strong Goldbach's conjecture for sufficiently large even integers

    OpenAIRE

    2016-01-01

    We approach a new proof of the strong Goldbach's conjecture for sufficiently large even integers by applying the Dirichlet's series. Using the Perron formula and the Residue Theorem in complex variable integration, one could show that any large even integer is demonstrated as a sum of two primes. In this paper,the Riemann Hypothesis is assumed to be true in throughout the paper. A novel function is defined on the natural numbers set.This function is a typical sieve function.Then based on this...

  18. Right Propositional Neighborhood Logic over Natural Numbers with Integer Constraints for Interval Lengths

    DEFF Research Database (Denmark)

    Bresolin, Davide; Goranko, Valentin; Montanari, Angelo

    2009-01-01

    Interval temporal logics are based on interval structures over linearly (or partially) ordered domains, where time intervals, rather than time instants, are the primitive ontological entities. In this paper we introduce and study Right Propositional Neighborhood Logic over natural numbers...... with integer constraints for interval lengths, which is a propositional interval temporal logic featuring a modality for the 'right neighborhood' relation between intervals and explicit integer constraints for interval lengths. We prove that it has the bounded model property with respect to ultimately periodic...

  19. Two-parameters quasi-filled function algorithm for nonlinear integer programming

    Institute of Scientific and Technical Information of China (English)

    WANG Wei-xiang; SHANG You-lin; ZHANG Lian-sheng

    2006-01-01

    A quasi-filled function for nonlinear integer programming problem is given in this paper. This function contains two parameters which are easily to be chosen. Theoretical properties of the proposed quasi-filled function are investigated. Moreover,we also propose a new solution algorithm using this quasi-filled function to solve nonlinear integer programming problem in this paper. The examples with 2 to 6 variables are tested and computational results indicated the efficiency and reliability of the proposed quasi-filled function algorithm.

  20. An approach towards the proof of the strong Goldbach's conjecture for sufficiently large even integers

    OpenAIRE

    Sabihi, Ahmad

    2016-01-01

    We approach a new proof of the strong Goldbach's conjecture for sufficiently large even integers by applying the Dirichlet's series. Using the Perron formula and the Residue Theorem in complex variable integration, one could show that any large even integer is demonstrated as a sum of two primes. In this paper,the Riemann Hypothesis is assumed to be true in throughout the paper. A novel function is defined on the natural numbers set.This function is a typical sieve function.Then based on this...

  1. Enumeration of pyramids of one-dimensional pieces of arbitrary fixed integer length

    DEFF Research Database (Denmark)

    Durhuus, Bergfinnur; Eilers, Søren

    We consider pyramids made of one-dimensional pieces of fixed integer length a and which may have pairwise overlaps of integer length from 1 to a. We prove that the number of pyramids of size m, i.e. consisting of m pieces, equals (am-1,m-1) for each a >= 2. This generalises a well known result...... for a = 2. A bijective correspondence between so-called right (or left) pyramids and a-ary trees is pointed out, and it is shown that asymptotically the average width of pyramids is proportional to the square root of the size....

  2. THE PHENOMENON OF HALF-INTEGER SPIN, QUATERNIONS, AND PAULI MATRICES

    Directory of Open Access Journals (Sweden)

    FERNANDO R. GONZÁLEZ DÍAZ

    2017-01-01

    Full Text Available In this paper the phenomenon of half-integer spin exemplification Paul AM Dirac made with a pair of scissors, an elastic cord and chair play. Four examples in which the same phenomenon appears and the algebraic structure of quaternions is related to one of the examples are described. Mathematical proof of the phenomenon using known topological and algebraic results are explained. The basic results of algebraic structures are described quaternions H , and an intrinsic relationship with the phenomenon half-integer spin and the Pauli matrices is established.

  3. Lossless Image Compression Using A Simplified MED Algorithm with Integer Wavelet Transform

    Directory of Open Access Journals (Sweden)

    Mohamed M. Fouad

    2013-11-01

    Full Text Available In this paper, we propose a lossless (LS image compression technique combining a prediction step with the integer wavelet transform. The prediction step proposed in this technique is a simplified version of the median edge detector algorithm used with JPEG-LS. First, the image is transformed using the prediction step and a difference image is obtained. The difference image goes through an integer wavelet transform and the transform coefficients are used in the lossless codeword assignment. The algorithm is simple and test results show that it yields higher compression ratios than competing techniques. Computational cost is also kept close to competing techniques.

  4. [An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

    Science.gov (United States)

    Balashov, A M; Selishchev, S V

    2004-01-01

    An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

  5. Use of electronic microprocessor-based instrumentation by the U.S. geological survey for hydrologic data collection

    Science.gov (United States)

    Shope, William G.; ,

    1991-01-01

    The U.S. Geological Survey is acquiring a new generation of field computers and communications software to support hydrologic data-collection at field locations. The new computer hardware and software mark the beginning of the Survey's transition from the use of electromechanical devices and paper tapes to electronic microprocessor-based instrumentation. Software is being developed for these microprocessors to facilitate the collection, conversion, and entry of data into the Survey's National Water Information System. The new automated data-collection process features several microprocessor-controlled sensors connected to a serial digital multidrop line operated by an electronic data recorder. Data are acquired from the sensors in response to instructions programmed into the data recorder by the user through small portable lap-top or hand-held computers. The portable computers, called personal field computers, also are used to extract data from the electronic recorders for transport by courier to the office computers. The Survey's alternative to manual or courier retrieval is the use of microprocessor-based remote telemetry stations. Plans have been developed to enhance the Survey's use of the Geostationary Operational Environmental Satellite telemetry by replacing the present network of direct-readout ground stations with less expensive units. Plans also provide for computer software that will support other forms of telemetry such as telephone or land-based radio.

  6. 15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

    Science.gov (United States)

    2010-01-01

    ... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer... amendment to the EAR, that a license is required for export or reexport of items described in ECCN 3A991.a.1...

  7. A microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

    Science.gov (United States)

    Agoritsas, V.; Beck, F.; Benincasa, G. P.; Bovigny, J. P.

    1986-06-01

    This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

  8. Microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Agoritsas, V.; Beck, F.; Benincasa, G.P.; Bovigny, J.P.

    1986-06-01

    This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

  9. Identification of microprocessor-dependent cancer cells allows screening for growth-sustaining micro-RNAs.

    Science.gov (United States)

    Peric, D; Chvalova, K; Rousselet, G

    2012-04-19

    Micro-RNAs are deregulated in cancer cells, and some are either tumor suppressive or oncogenic. In addition, a link has been established between decreased expression of micro-RNAs and transformation, and several proteins of the RNA interference pathway have been shown to be haploinsufficient tumor suppressors. Oncogenic micro-RNAs (oncomiRs) could represent new therapeutic targets, and their identification is therefore crucial. However, structural and functional redundancy between micro-RNAs hampers approaches relying on individual micro-RNA inhibition. We reasoned that in cancer cells that depend on oncomiRs, impairing the micro-RNA pathway could lead to growth perturbation rather than increased tumorigenesis. Identifying such cells could allow functional analyses of individual micro-RNAs by complementation of the phenotypes observed upon global micro-RNA inhibition. Therefore, we developed episomal vectors coding for small hairpin RNAs targeting either Drosha or DGCR8, the two components of the microprocessor, the nuclear micro-RNA maturation complex. We identified cancer cell lines in which both vectors induced colony growth arrest. We then screened for individual micro-RNAs complementing this growth arrest, and identified miR-19a, miR-19b, miR-20a and miR-27b as major growth-sustaining micro-RNAs. However, the effect of miR-19a and miR-19b was only transient. In addition, embryonic stem cell-derived micro-RNAs with miR-20a seeds were much less efficient than miR-20a in sustaining cancer cell growth, a finding that contrasted with results obtained in stem cells. Finally, we showed that the tumor suppressor phosphatase and tensin homologue deleted on chromosome 10, a shared target of miR-19 and miR-20, was functionally involved in the growth arrest induced by microprocessor inhibition. We conclude that our approach allowed to identify microprocessor-dependent cancer cells, which could be used to screen for growth-sustaining micro-RNAs. This complementation screen

  10. Euclidean skeletons of 3D data sets in linear time by the integer medial axis transform

    NARCIS (Netherlands)

    Hesselink, Wim H.; Visser, Menno; Roerdink, Jos B.T.M.; Ronse, C; Najman, L; Decenciere, E

    2005-01-01

    A general algorithm for computing Euclidean skeletons of 3D data sets in linear time is presented. These skeletons are defined in terms of a new concept, called the integer medial axis (IMA) transform. The algorithm is based upon the computation of 3D feature transforms, using a modification of an a

  11. On the convex hull of the simple integer recourse objective function

    NARCIS (Netherlands)

    Klein Haneveld, Willem K.; Stougie, L.; van der Vlerk, Maarten H.

    1995-01-01

    We consider the objective function of a simple integer recourse problem with fixed technology matrix. Using properties of the expected value function, we prove a relation between the convex hull of this function and the expected value function of a continuous simple recourse program. We present an

  12. On the expected value function of a simple integer recourse problem with random technology matrix

    NARCIS (Netherlands)

    Klein Haneveld, Willem K.; van der Vlerk, Maarten H.

    1994-01-01

    In this paper we consider the expected value function of a stochastic simple recourse program with random technology matrix and integer variables in the second stage. Due to its separability the analysis is straightforward. Conditions for finiteness, continuity, Lipschitz continuity and

  13. Determining the optimal product-mix using integer programming: An application in audio speaker production

    Science.gov (United States)

    Khan, Sahubar Ali Bin Mohamed Nadhar; Ahmarofi, Ahmad Afif Bin

    2014-12-01

    In manufacturing sector, production planning or scheduling is the most important managerial task in order to achieve profit maximization and cost minimization. With limited resources, the management has to satisfy customer demand and at the same time fulfill company's objective, which is to maximize profit or minimize cost. Hence, planning becomes a significant task for production site in order to determine optimal number of units for each product to be produced. In this study, integer programming technique is used to develop an appropriate product-mix planning to obtain the optimal number of audio speaker products that should be produced in order to maximize profit. Branch-and-bound method is applied to obtain exact integer solutions when non-integer solutions occurred. Three major resource constraints are considered in this problem: raw materials constraint, demand constraint and standard production time constraint. It is found that, the developed integer programming model gives significant increase in profit compared to the existing method used by the company. At the end of the study, sensitivity analysis was performed to evaluate the effects of changes in objective function coefficient and available resources on the developed model. This will enable the management to foresee the effects on the results when some changes happen to the profit of its products or available resources.

  14. Integer charge transfer at the tetrakis(dimethylamino)ethylene/Au interface

    DEFF Research Database (Denmark)

    Lindell, L.; Unge, Mikael; Osikowicz, W.

    2008-01-01

    conditions, where direct overlap of the organic pi system from the metal bands is prevented due to presence of oxides and/or hydrocarbons. We present direct experimental and theoretical evidence showing that the interface energetic for such systems is governed by exchange of an integer amount of electrons....

  15. Integer Programming Formulation of the Problem of Generating Milton Babbitt's All-partition Arrays

    DEFF Research Database (Denmark)

    Tanaka, Tsubasa; Bemman, Brian; Meredith, David

    2016-01-01

    Milton Babbitt (1916–2011) was a composer of twelve-tone serial music noted for creating the all-partition array. The problem of generating an all-partition array involves finding a rectangular array of pitch-class integers that can be partitioned into regions, each of which represents a distinct...

  16. Mixed-Integer-Linear-Programming-Based Energy Management System for Hybrid PV-Wind-Battery Microgrids

    DEFF Research Database (Denmark)

    Hernández, Adriana Carolina Luna; Aldana, Nelson Leonardo Diaz; Graells, Moises

    2017-01-01

    -side strategy, defined as a general mixed-integer linear programming by taking into account two stages for proper charging of the storage units. This model is considered as a deterministic problem that aims to minimize operating costs and promote self-consumption based on 24-hour ahead forecast data...

  17. An algorithm for the construction of convex hulls in simple integer recourse programming

    NARCIS (Netherlands)

    Klein Haneveld, W.K.; Stougie, L.; van der Vlerk, M.H.

    1996-01-01

    We consider the objective function of a simple integer recourse problem with fixed technology matrix and discretely distributed right-hand sides. Exploiting the special structure of this problem, we devise an algorithm that determines the convex hull of this function efficiently. The results are imp

  18. On the convex hull of the simple integer recourse objective function

    NARCIS (Netherlands)

    Klein Haneveld, Willem K.; Stougie, L.; van der Vlerk, Maarten H.

    1995-01-01

    We consider the objective function of a simple integer recourse problem with fixed technology matrix. Using properties of the expected value function, we prove a relation between the convex hull of this function and the expected value function of a continuous simple recourse program. We present an a

  19. Exact Penalty Function and Asymptotic Strong Nonlinear Duality in Integer Programming

    Institute of Scientific and Technical Information of China (English)

    Fu-sheng Bai; Z.Y.Wu; L.S. Zhang

    2004-01-01

    In this paper, a logarithmic-exponential penalty function with two parameters for integer programmingis discussed. We obtain the exact penalty properties and then establish the asymptotic strong nonlinear duality in the corresponding logarithmic-exponential dual formulation by using the obtained exact penalty properties.The discussion is based on the logarithmic-exponential nonlinear dual formulation proposed in [6].

  20. Fast numerical methods for mixed-integer nonlinear model-predictive control

    CERN Document Server

    Kirches, Christian

    2011-01-01

    Christian Kirches develops a fast numerical algorithm of wide applicability that efficiently solves mixed-integer nonlinear optimal control problems. He uses convexification and relaxation techniques to obtain computationally tractable reformulations for which feasibility and optimality certificates can be given even after discretization and rounding.