WorldWideScience

Sample records for transistor terminal voltages

  1. A High-Voltage Level Tolerant Transistor Circuit

    NARCIS (Netherlands)

    Annema, Anne J.; Geelen, Godefridus Johannes Gertrudis Maria

    2001-01-01

    A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1)

  2. A nanoscale piezoelectric transformer for low-voltage transistors.

    Science.gov (United States)

    Agarwal, Sapan; Yablonovitch, Eli

    2014-11-12

    A novel piezoelectric voltage transformer for low-voltage transistors is proposed. Placing a piezoelectric transformer on the gate of a field-effect transistor results in the piezoelectric transformer field-effect transistor that can switch at significantly lower voltages than a conventional transistor. The piezoelectric transformer operates by using one piezoelectric to squeeze another piezoelectric to generate a higher output voltage than the input voltage. Multiple piezoelectrics can be used to squeeze a single piezoelectric layer to generate an even higher voltage amplification. Coupled electrical and mechanical modeling in COMSOL predicts a 12.5× voltage amplification for a six-layer piezoelectric transformer. This would lead to more than a 150× reduction in the power needed for communications.

  3. Shootthrough fault protection system for bipolar transistors in a voltage source transistor inverter

    International Nuclear Information System (INIS)

    Wirth, W.F.

    1982-01-01

    Faulted bipolar transistors in a voltage source transistor inverter are protected against shootthrough fault current, from the filter capacitor of the d-c voltage source which drives the inverter over the d-c bus, by interposing a small choke in series with the filter capacitor to limit the rate of rise of that fault current while at the same time causing the d-c bus voltage to instantly drop to essentially zero volts at the beginning of a shootthrough fault. In this way, the load lines of the faulted transistors are effectively shaped so that they do not enter the second breakdown area, thereby preventing second breakdown destruction of the transistors

  4. Comprehensive study of gate-terminated and source-terminated field-plate 0.13 µm NMOS transistors

    International Nuclear Information System (INIS)

    Chiu, Hsien-Chin; Lin, Shao-Wei; Cheng, Chia-Shih; Wei, Chien-Cheng

    2008-01-01

    This study systematically investigated microwave noise, power and linearity characteristics of field-plate (FP) 0.13 µm CMOS transistors in which the field-plate metal is connected to the gate terminal and the source terminal. The gate-terminated FP NMOS (FP-G NMOS) provided the best noise figure (NF) at 6 GHz compared with standard devices and the source-terminated FP device (FP-S NMOS) as the lowest gate resistance (R g ) was obtained by this structure. By adopting the field-plate metal in NMOS, both FP-S and FP-G devices achieved higher current density at high gate bias voltages. Moreover, these two devices also had higher efficiency under high drain-to-source voltages at the high input power swing. The third-order inter-modulation product (IM3) is −39.4 dBm for FP-S NMOS at P in of −20 dBm; the corresponding values for FP-G and standard devices are −34.9 dBm and −37.3 dBm, respectively. Experimental results indicate that the FP-G architecture is suitable for low noise applications and FP-S is suitable for high power and high linearity operation

  5. Oscillation of Critical Current by Gate Voltage in Cooper Pair Transistor

    International Nuclear Information System (INIS)

    Kim, N.; Cheong, Y.; Song, W.

    2010-01-01

    We measured the critical current of a Cooper pair transistor consisting of two Josephson junctions and a gate electrode. The Cooper pair transistors were fabricated by using electron-beam lithography and double-angle evaporation technique. The Gate voltage dependence of critical current was measured by observing voltage jumps at various gate voltages while sweeping bias current. The observed oscillation was 2e-periodic, which shows the Cooper pair transistor had low level of quasiparticle poisoning.

  6. Circuit and method for controlling the threshold voltage of transistors.

    NARCIS (Netherlands)

    2008-01-01

    A control unit, for controlling a threshold voltage of a circuit unit having transistor devices, includes a reference circuit and a measuring unit. The measuring unit is configured to measure a threshold voltage of at least one sensing transistor of the circuit unit, and to measure a threshold

  7. Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

    Energy Technology Data Exchange (ETDEWEB)

    Erofeev, E. V., E-mail: erofeev@micran.ru [Tomsk State University of Control Systems and Radioelectronics, Research Institute of Electrical-Communication Systems (Russian Federation); Fedin, I. V.; Kutkov, I. V. [Research and Production Company “Micran” (Russian Federation); Yuryev, Yu. N. [National Research Tomsk Polytechnic University, Institute of Physics and Technology (Russian Federation)

    2017-02-15

    High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

  8. Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

    International Nuclear Information System (INIS)

    Erofeev, E. V.; Fedin, I. V.; Kutkov, I. V.; Yuryev, Yu. N.

    2017-01-01

    High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V_t_h = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V_t_h = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

  9. Influence of X and gamma radiation and bias conditions on dropout voltage of voltage regulators serial transistors

    International Nuclear Information System (INIS)

    Vukic, V.; Osmokrovic, P.; Stankovic, S.; Kovacevic, M.

    2005-01-01

    Research topic presented in this paper is degradation of characteristics of low-dropout voltage regulator's serial transistor during exposure of device to the ionizing radiation. Voltage regulators were exposed to X and γ radiation in two modes: without bias conditions, and with bias conditions and load. Tested circuits are representatives of the first and the second generation of low-dropout voltage regulators, with lateral and vertical PNP serial transistor: LM2940 and L4940. Experimental results of output voltage and serial dropout voltage change in function of total ionizing dose, during the medium-dose-rate exposure, were presented. (author) [sr

  10. Liquid–Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

    KAUST Repository

    Zhang, Yu

    2017-10-17

    Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

  11. Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

    Science.gov (United States)

    Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

    2017-11-08

    Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

  12. Research of the voltage and current stabilization processes by using the silicon field-effect transistor

    International Nuclear Information System (INIS)

    Karimov, A.V.; Yodgorova, D.M.; Kamanov, B.M.; Giyasova, F.A.; Yakudov, A.A.

    2012-01-01

    The silicon field-effect transistors were investigated to use in circuits for stabilization of current and voltage. As in gallium arsenide field-effect transistors, in silicon field-effect transistors with p-n-junction a new mechanism of saturation of the drain current is experimentally found out due to both transverse and longitudinal compression of channel by additional resistance between the source and the gate of the transistor. The criteria for evaluating the coefficients of stabilization of transient current suppressors and voltage stabilizator based on the field-effect transistor are considered. (authors)

  13. Characteristics of voltage regulators with serial NPN transistor in the fields of medium and high energy photons

    International Nuclear Information System (INIS)

    Vukic, V.; Osmokrovic, P.

    2007-01-01

    Variation of collector - emitter dropout voltage on serial transistors of voltage regulators LM2990T-5 and LT1086CT5 were used as the parameter for detection of examined devices' radiation hardness in X and ? radiation fields. Biased voltage regulators with serial super-β transistor in the medium dose rate X radiation field had significantly different response from devices with conventional serial NPN transistor. Although unbiased components suffered greater damage in most cases, complete device failure happened only among the biased components with serial super-β transistor in Bremsstrahlung field. Mechanisms of transistors degradation in ionizing radiation fields were analysed [sr

  14. Gold nanoparticle-pentacene memory-transistors

    OpenAIRE

    Novembre , Christophe; Guerin , David; Lmimouni , Kamal; Gamrat , Christian; Vuillaume , Dominique

    2008-01-01

    We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off sta...

  15. Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

    Science.gov (United States)

    Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

    2012-01-01

    Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

  16. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    Energy Technology Data Exchange (ETDEWEB)

    Chao, Jin Yu [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Yuan, Zhi Guo, E-mail: ncityzg@163.com [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China)

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  17. Optical control system for high-voltage terminals

    International Nuclear Information System (INIS)

    Bicek, J.J.

    1978-01-01

    An optical control system for the control of devices in the terminal of an electrostatic accelerator includes a laser that is modulated by a series of preselected codes produced by an encoder. A photodiode receiver is placed in the laser beam at the high-voltage terminal of an electrostatic accelerator. A decoder connected to the photodiode decodes the signals to provide control impulses for a plurality of devices at the high voltage of the terminal

  18. Fabrication of a vertical channel field effect transistor and a study of its electrical performances

    International Nuclear Information System (INIS)

    Bhuiyan, A.S.

    1983-01-01

    A vertical channel field effect transistor on silicon was fabricated by diffusion technique and its electrical characteristics were studied as a function of voltage and temperature. It was found that this transistor has relatively high breakdown voltage of 65 volts for drain source and of 7.5 volts for gate source terminals. (author)

  19. Light-voltage conversion apparatus

    Energy Technology Data Exchange (ETDEWEB)

    Fujioka, Yoshiki

    1987-09-19

    In a light-voltage conversion unit, when input signal is applied, the output signal to the control circuit has quick rise-up time and slow breaking time. In order to improve this, a short-circuit transistor is placed at the diode, and this transistor is forced ON, when an output signal to the control circuit is lowered down to a constant voltage, to short-circuit between the output terminals. This, however, has a demerit of high power consumption by a transistor. In this invention, by connecting a light-emitting element which gets ON at the first transition and a light-emitting element which gets ON at the last transition, placing a light receiving element in front of each light-emitting element, when an input signal is applied; thus a load is driven only with ON signal of each light-emitting element, eliminating the delay in the last transition. All of these give a quick responsive light-voltage conversion without unnecessary power consumption. (5 figs)

  20. Proton conducting sodium alginate electrolyte laterally coupled low-voltage oxide-based transistors

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Yang Hui; Wan, Qing, E-mail: wanqing@nju.edu.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China); Qiang Zhu, Li, E-mail: lqzhu@nimte.ac.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Shi, Yi [School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China)

    2014-03-31

    Solution-processed sodium alginate electrolyte film shows a high proton conductivity of ∼5.5 × 10{sup −3} S/cm and a high lateral electric-double-layer (EDL) capacitance of ∼2.0 μF/cm{sup 2} at room temperature with a relative humidity of 57%. Low-voltage in-plane-gate indium-zinc-oxide-based EDL transistors laterally gated by sodium alginate electrolytes are fabricated on glass substrates. The field-effect mobility, current ON/OFF ratio, and subthreshold swing of such EDL transistors are estimated to be 4.2 cm{sup 2} V{sup −1} s{sup −1}, 2.8 × 10{sup 6}, and 130 mV/decade, respectively. At last, a low-voltage driven resistor-load inverter is also demonstrated. Such in-plane-gate EDL transistors have potential applications in portable electronics and low-cost biosensors.

  1. Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

    Science.gov (United States)

    Lodi, Robert J.

    1976-01-01

    A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

  2. High-Voltage, Low-Power BNC Feedthrough Terminator

    Science.gov (United States)

    Bearden, Douglas

    2012-01-01

    This innovation is a high-voltage, lowpower BNC (Bayonet Neill-Concelman) feedthrough that enables the user to terminate an instrumentation cable properly while connected to a high voltage, without the use of a voltage divider. This feedthrough is low power, which will not load the source, and will properly terminate the instrumentation cable to the instrumentation, even if the cable impedance is not constant. The Space Shuttle Program had a requirement to measure voltage transients on the orbiter bus through the Ground Lightning Measurement System (GLMS). This measurement has a bandwidth requirement of 1 MHz. The GLMS voltage measurement is connected to the orbiter through a DC panel. The DC panel is connected to the bus through a nonuniform cable that is approximately 75 ft (approximately equal to 23 m) long. A 15-ft (approximately equal to 5-m), 50-ohm triaxial cable is connected between the DC panel and the digitizer. Based on calculations and simulations, cable resonances and reflections due to mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. A voltage divider at the DC panel, and terminating the 50-ohm cable properly, would eliminate this issue. Due to implementation issues, an alternative design was needed to terminate the cable properly without the use of a voltage divider. Analysis shows how the cable resonances and reflections due to the mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. After simulating a dampening circuit located at the digitizer, simulations were performed to show how the cable resonances were dampened and the accuracy was improved significantly. Test cables built to verify simulations were accurate. Since the dampening circuit is low power, it can be packaged in a BNC feedthrough.

  3. A novel voltage clamp circuit for the measurement of transistor dynamic on-resistance

    NARCIS (Netherlands)

    Gelagaev, R.; Jacqmaer, P.; Everts, J.; Driesen, Johan

    2012-01-01

    For determining the dynamic on-resistance Rdyn,on of a power transistor, the voltage and current waveforms have to be measured during the switching operation. In measurements of voltage waveforms, using an oscilloscope, the characteristics of an amplifier inside the oscilloscope are distorted when

  4. An analytic current-voltage model for quasi-ballistic III-nitride high electron mobility transistors

    Science.gov (United States)

    Li, Kexin; Rakheja, Shaloo

    2018-05-01

    We present an analytic model to describe the DC current-voltage (I-V) relationship in scaled III-nitride high electron mobility transistors (HEMTs) in which transport within the channel is quasi-ballistic in nature. Following Landauer's transport theory and charge calculation based on two-dimensional electrostatics that incorporates negative momenta states from the drain terminal, an analytic expression for current as a function of terminal voltages is developed. The model interprets the non-linearity of access regions in non-self-aligned HEMTs. Effects of Joule heating with temperature-dependent thermal conductivity are incorporated in the model in a self-consistent manner. With a total of 26 input parameters, the analytic model offers reduced empiricism compared to existing GaN HEMT models. To verify the model, experimental I-V data of InAlN/GaN with InGaN back-barrier HEMTs with channel lengths of 42 and 105 nm are considered. Additionally, the model is validated against numerical I-V data obtained from DC hydrodynamic simulations of an unintentionally doped AlGaN-on-GaN HEMT with 50-nm gate length. The model is also verified against pulsed I-V measurements of a 150-nm T-gate GaN HEMT. Excellent agreement between the model and experimental and numerical results for output current, transconductance, and output conductance is demonstrated over a broad range of bias and temperature conditions.

  5. Interface Engineering for Precise Threshold Voltage Control in Multilayer-Channel Thin Film Transistors

    KAUST Repository

    Park, Jihoon

    2016-11-29

    Multilayer channel structure is used to effectively manipulate the threshold voltage of zinc oxide transistors without degrading its field-effect mobility. Transistors operating in enhancement mode with good mobility are fabricated by optimizing the structure of the multilayer channel. The optimization is attributed to the formation of additional channel and suppression of the diffusion of absorbed water molecules and oxygen vacancies.

  6. Interface Engineering for Precise Threshold Voltage Control in Multilayer-Channel Thin Film Transistors

    KAUST Repository

    Park, Jihoon; Alshammari, Fwzah Hamud; Wang, Zhenwei; Alshareef, Husam N.

    2016-01-01

    Multilayer channel structure is used to effectively manipulate the threshold voltage of zinc oxide transistors without degrading its field-effect mobility. Transistors operating in enhancement mode with good mobility are fabricated by optimizing the structure of the multilayer channel. The optimization is attributed to the formation of additional channel and suppression of the diffusion of absorbed water molecules and oxygen vacancies.

  7. Hysteresis analysis of graphene transistor under repeated test and gate voltage stress

    International Nuclear Information System (INIS)

    Yang Jie; Jia Kunpeng; Su Yajuan; Zhao Chao; Chen Yang

    2014-01-01

    The current transport characteristic is studied systematically based on a back-gate graphene field effect transistor, under repeated test and gate voltage stress. The interface trapped charges caused by the gate voltage sweep process screens the gate electric field, and results in the neutral point voltage shift between the forth and back sweep direction. In the repeated test process, the neutral point voltage keeps increasing with test times in both forth and back sweeps, which indicates the existence of interface trapped electrons residual and accumulation. In gate voltage stress experiment, the relative neutral point voltage significantly decreases with the reducing of stress voltage, especially in −40 V, which illustrates the driven-out phenomenon of trapped electrons under negative voltage stress. (semiconductor devices)

  8. Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

    Science.gov (United States)

    Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

    2017-09-01

    The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

  9. Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

    Science.gov (United States)

    Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

    2017-09-15

    The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

  10. Generic inertia emulation controller for multi-terminal voltage-source-converter high voltage direct current systems

    DEFF Research Database (Denmark)

    Zhu, Jiebei; Guerrero, Josep M.; Hung, William

    2014-01-01

    A generic Inertia Emulation Controller (INEC) scheme for Multi-Terminal Voltage-Source-Converter based HVDC (VSC-MTDC) systems is proposed and presented in this paper. The proposed INEC can be incorporated in any Grid-side Voltage-Source-Converter (GVSC) station, allowing the MTDC terminal...

  11. Low-Voltage Solution-Processed Hybrid Light-Emitting Transistors.

    Science.gov (United States)

    Chaudhry, Mujeeb Ullah; Tetzner, Kornelius; Lin, Yen-Hung; Nam, Sungho; Pearson, Christopher; Groves, Chris; Petty, Michael C; Anthopoulos, Thomas D; Bradley, Donal D C

    2018-05-21

    We report the development of low operating voltages in inorganic-organic hybrid light-emitting transistors (HLETs) based on a solution-processed ZrO x gate dielectric and a hybrid multilayer channel consisting of the heterojunction In 2 O 3 /ZnO and the organic polymer "Super Yellow" acting as n- and p-channel/emissive layers, respectively. Resulting HLETs operate at the lowest voltages reported to-date (<10 V) and combine high electron mobility (22 cm 2 /(V s)) with appreciable current on/off ratios (≈10 3 ) and an external quantum efficiency of 2 × 10 -2 % at 700 cd/m 2 . The charge injection, transport, and recombination mechanisms within this HLET architecture are discussed, and prospects for further performance enhancement are considered.

  12. Flexible low-voltage organic transistors with high thermal stability at 250 °C.

    Science.gov (United States)

    Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Zschieschang, Ute; Klauk, Hagen; Takimiya, Kazuo; Sadamitsu, Yuji; Hamada, Masahiro; Sekitani, Tsuyoshi; Someya, Takao

    2013-07-19

    Low-operating-voltage flexible organic thin-film transistors with high thermal stability using DPh-DNTT and SAM gate dielectrics are reported. The mobility of the transistors are decreased by 23% after heating to 250 °C for 30 min. Furthermore, flexible organic pseudo-CMOS inverter circuits, which are functional after heating to 200 °C, are demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  13. Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

    Science.gov (United States)

    Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

    2014-01-01

    Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

  14. Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

    Science.gov (United States)

    Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

    2015-10-21

    The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

  15. Problems of noise modeling in the presence of total current branching in high electron mobility transistor and field-effect transistor channels

    International Nuclear Information System (INIS)

    Shiktorov, P; Starikov, E; Gružinskis, V; Varani, L; Sabatini, G; Marinchio, H; Reggiani, L

    2009-01-01

    In the framework of analytical and hydrodynamic models for the description of carrier transport and noise in high electron mobility transistor/field-effect transistor channels the main features of the intrinsic noise of transistors are investigated under continuous branching of the current between channel and gate. It is shown that the current-noise and voltage-noise spectra at the transistor terminals contain an excess noise related to thermal excitation of plasma wave modes in the dielectric layer between the channel and gate. It is found that the set of modes of excited plasma waves can be governed by the external embedding circuits, thus violating a universal description of noise in terms of Norton and Thevenin noise generators

  16. Justifying threshold voltage definition for undoped body transistors through 'crossover point' concept

    International Nuclear Information System (INIS)

    Baruah, Ratul Kumar; Mahapatra, Santanu

    2009-01-01

    Two different definitions, one is potential based and the other is charge based, are used in the literatures to define the threshold voltage of undoped body symmetric double gate transistors. This paper, by introducing a novel concept of crossover point, proves that the charge based definition is more accurate than the potential based definition. It is shown that for a given channel length the potential based definition predicts anomalous change in threshold voltage with body thickness variation while the charge based definition results in monotonous change. The threshold voltage is then extracted from drain current versus gate voltage characteristics using linear extrapolation, transconductance and match-point methods. In all the three cases it is found that trend of threshold voltage variation support the charge based definition.

  17. Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...

  18. Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

    Energy Technology Data Exchange (ETDEWEB)

    Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

    2015-08-24

    Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

  19. Threshold voltage roll-off modelling of bilayer graphene field-effect transistors

    International Nuclear Information System (INIS)

    Saeidmanesh, M; Ismail, Razali; Khaledian, M; Karimi, H; Akbari, E

    2013-01-01

    An analytical model is presented for threshold voltage roll-off of double gate bilayer graphene field-effect transistors. To this end, threshold voltage models of short- and long-channel states have been developed. In the short-channel case, front and back gate potential distributions have been modelled and used. In addition, the tunnelling probability is modelled and its effect is taken into consideration in the potential distribution model. To evaluate the accuracy of the potential model, FlexPDE software is employed with proper boundary conditions and a good agreement is observed. Using the proposed models, the effect of several structural parameters on the threshold voltage and its roll-off are studied at room temperature. (paper)

  20. Analysis of collector-emitter offset voltage of InGaP/GaAs composite collector double heterojunction bipolar transistor

    Science.gov (United States)

    Lew, K. L.; Yoon, S. F.

    2002-04-01

    The Ebers-Moll-like terminal current expressions of a composite collector double heterojunction bipolar transistor (DHBT), which takes the recombination effect into account, have been formulated and an expression for collector-emitter offset voltage [VCE(offset)] has been derived. Factors affecting the VCE(offset) of a composite collector DHBT are investigated and good agreement between the calculated and reported experimental results is shown. Analytical results showed that the transmission coefficient of the base-collector (B-C) junction does not have a considerable effect on the VCE(offset), provided that the B-C junction is of good quality. Thus, despite its asymmetric structure, the VCE(offset) of an optimally designed composite collector DHBT could be as low as that of a conventional DHBT. Hence a composite collector DHBT with low saturation voltage and negligible VCE(offset) is possible if the two conditions: (i) good quality B-C junction, (ii) base transport factor, α≈1, are fulfilled.

  1. High-temperature performance of MoS{sub 2} thin-film transistors: Direct current and pulse current-voltage characteristics

    Energy Technology Data Exchange (ETDEWEB)

    Jiang, C.; Samnakay, R.; Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory (NDL), Department of Electrical Engineering, Bourns College of Engineering, University of California—Riverside, Riverside, California 92521 (United States); Phonon Optimized Engineered Materials (POEM) Center, Materials Science and Engineering Program, University of California—Riverside, Riverside, California 92521 (United States); Rumyantsev, S. L. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States); Ioffe Physical-Technical Institute, St. Petersburg 194021 (Russian Federation); Shur, M. S. [Department of Electrical, Computer, and Systems Engineering, Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, New York 12180 (United States)

    2015-02-14

    We report on fabrication of MoS{sub 2} thin-film transistors (TFTs) and experimental investigations of their high-temperature current-voltage characteristics. The measurements show that MoS{sub 2} devices remain functional to temperatures of at least as high as 500 K. The temperature increase results in decreased threshold voltage and mobility. The comparison of the direct current (DC) and pulse measurements shows that the direct current sub-linear and super-linear output characteristics of MoS{sub 2} thin-films devices result from the Joule heating and the interplay of the threshold voltage and mobility temperature dependences. At temperatures above 450 K, a kink in the drain current occurs at zero gate voltage irrespective of the threshold voltage value. This intriguing phenomenon, referred to as a “memory step,” was attributed to the slow relaxation processes in thin films similar to those in graphene and electron glasses. The fabricated MoS{sub 2} thin-film transistors demonstrated stable operation after two months of aging. The obtained results suggest new applications for MoS{sub 2} thin-film transistors in extreme-temperature electronics and sensors.

  2. On-line monitoring of base current and forward emitter current gain of the voltage regulator's serial pnp transistor in a radiation environment

    Directory of Open Access Journals (Sweden)

    Vukić Vladimir Đ.

    2012-01-01

    Full Text Available A method of on-line monitoring of the low-dropout voltage regulator's operation in a radiation environment is developed in this paper. The method had to enable detection of the circuit's degradation during exploitation, without terminating its operation in an ionizing radiation field. Moreover, it had to enable automatic measurement and data collection, as well as the detection of any considerable degradation, well before the monitored voltage regulator's malfunction. The principal parameters of the voltage regulator's operation that were monitored were the serial pnp transistor's base current and the forward emitter current gain. These parameters were procured indirectly, from the data on the voltage regulator's load and quiescent currents. Since the internal consumption current in moderately and heavily loaded devices was used, the quiescent current of a negligibly loaded voltage regulator of the same type served as a reference. Results acquired by on-line monitoring demonstrated marked agreement with the results acquired from examinations of the voltage regulator's maximum output current and minimum dropout voltage in a radiation environment. The results were particularly consistent in tests with heavily loaded devices. Results obtained for moderately loaded voltage regulators and the risks accompanying the application of the presented method, were also analyzed.

  3. Ultra-low Voltage CMOS Cascode Amplifier

    OpenAIRE

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique.

  4. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique......, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique....

  5. Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    2016-01-01

    : off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize...

  6. Adjustable threshold-voltage in all-inkjet-printed organic thin film transistor using double-layer dielectric structures

    International Nuclear Information System (INIS)

    Wu, Wen-Jong; Lee, Chang-Hung; Hsu, Chun-Hao; Yang, Shih-Hsien; Lin, Chih-Ting

    2013-01-01

    An all-inkjet-printed organic thin film transistor (OTFT) with a double-layer dielectric structure is proposed and implemented in this study. By using the double-layer structure with different dielectric materials (i.e., polyvinylphenol with poly(vinylidene fluoride-co-hexafluoropropylene)), the threshold-voltage of OTFT can be adjusted. The threshold-voltage shift can be controlled by changing the composition of dielectric layers. That is, an enhancement-mode OTFT can be converted to a depletion-mode OTFT by selectively printing additional dielectric layers to form a high-k/low-k double-layer structure. The printed OTFT has a carrier mobility of 5.0 × 10 −3 cm 2 /V-s. The threshold-voltages of the OTFTs ranged between − 13 V and 10 V. This study demonstrates an additional design parameter for organic electronics manufactured using inkjet printing technology. - Highlights: • A double-layer dielectric organic thin film transistor, OTFT, is implemented. • The threshold voltage of OTFT can be configured by the double dielectric structure. • The composition of the dielectric determines the threshold voltage shift. • The characteristics of OTFTs can be adjusted by double dielectric structures

  7. Trap Healing for High-Performance Low-Voltage Polymer Transistors and Solution-Based Analog Amplifiers on Foil.

    Science.gov (United States)

    Pecunia, Vincenzo; Nikolka, Mark; Sou, Antony; Nasrallah, Iyad; Amin, Atefeh Y; McCulloch, Iain; Sirringhaus, Henning

    2017-06-01

    Solution-processed semiconductors such as conjugated polymers have great potential in large-area electronics. While extremely appealing due to their low-temperature and high-throughput deposition methods, their integration in high-performance circuits has been difficult. An important remaining challenge is the achievement of low-voltage circuit operation. The present study focuses on state-of-the-art polymer thin-film transistors based on poly(indacenodithiophene-benzothiadiazole) and shows that the general paradigm for low-voltage operation via an enhanced gate-to-channel capacitive coupling is unable to deliver high-performance device behavior. The order-of-magnitude longitudinal-field reduction demanded by low-voltage operation plays a fundamental role, enabling bulk trapping and leading to compromised contact properties. A trap-reduction technique based on small molecule additives, however, is capable of overcoming this effect, allowing low-voltage high-mobility operation. This approach is readily applicable to low-voltage circuit integration, as this work exemplifies by demonstrating high-performance analog differential amplifiers operating at a battery-compatible power supply voltage of 5 V with power dissipation of 11 µW, and attaining a voltage gain above 60 dB at a power supply voltage below 8 V. These findings constitute an important milestone in realizing low-voltage polymer transistors for solution-based analog electronics that meets performance and power-dissipation requirements for a range of battery-powered smart-sensing applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. Poisson simulation for high voltage terminal of test stand for 1MV electrostatic accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sae-Hoon; Kim, Jeong-Tae; Kwon, Hyeok-Jung; Cho, Yong-Sub [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Kim, Yu-Seok [Dongguk Univ.., Gyeongju (Korea, Republic of)

    2014-10-15

    KOMAC provide ion beam to user which energy range need to expand to MeV range and develop 1 MV electrostatic accelerator. The specifications of the electrostatic accelerator are 1MV acceleration voltage, 10 mA peak current and variable gas ion. We are developing test stand before set up 1 MV electrostatic accelerator. The test stand voltage is 300 kV and operating time is 8 hours. The test stand is consist of 300 kV high voltage terminal, DC-AC-DC inverter, power supply device inside terminal, 200MHz RF power, 5 kV extraction power supply, 300 kV accelerating tube and vacuum system.. The beam measurement system and beam dump will be installed next to accelerating tube. Poisson code simulation results of the high voltage terminal are presented in this paper. Poisson code has been used to calculate the electric field for high voltage terminal. The results of simulation were verified with reasonable results. The poisson code structure could be apply to the high voltage terminal of the test stand.

  9. Poisson simulation for high voltage terminal of test stand for 1MV electrostatic accelerator

    International Nuclear Information System (INIS)

    Park, Sae-Hoon; Kim, Jeong-Tae; Kwon, Hyeok-Jung; Cho, Yong-Sub; Kim, Yu-Seok

    2014-01-01

    KOMAC provide ion beam to user which energy range need to expand to MeV range and develop 1 MV electrostatic accelerator. The specifications of the electrostatic accelerator are 1MV acceleration voltage, 10 mA peak current and variable gas ion. We are developing test stand before set up 1 MV electrostatic accelerator. The test stand voltage is 300 kV and operating time is 8 hours. The test stand is consist of 300 kV high voltage terminal, DC-AC-DC inverter, power supply device inside terminal, 200MHz RF power, 5 kV extraction power supply, 300 kV accelerating tube and vacuum system.. The beam measurement system and beam dump will be installed next to accelerating tube. Poisson code simulation results of the high voltage terminal are presented in this paper. Poisson code has been used to calculate the electric field for high voltage terminal. The results of simulation were verified with reasonable results. The poisson code structure could be apply to the high voltage terminal of the test stand

  10. High breakdown voltage quasi-two-dimensional β-Ga2O3 field-effect transistors with a boron nitride field plate

    Science.gov (United States)

    Bae, Jinho; Kim, Hyoung Woo; Kang, In Ho; Yang, Gwangseok; Kim, Jihyun

    2018-03-01

    We have demonstrated a β-Ga2O3 metal-semiconductor field-effect transistor (MESFET) with a high off-state breakdown voltage (344 V), based on a quasi-two-dimensional β-Ga2O3 field-plated with hexagonal boron nitride (h-BN). Both the β-Ga2O3 and h-BN were mechanically exfoliated from their respective crystal substrates, followed by dry-transfer onto a SiO2/Si substrate for integration into a high breakdown voltage quasi-two-dimensional β-Ga2O3 MESFETs. N-type conducting behavior was observed in the fabricated β-Ga2O3 MESFETs, along with a high on/off current ratio (>106) and excellent current saturation. A three-terminal off-state breakdown voltage of 344 V was obtained, with a threshold voltage of -7.3 V and a subthreshold swing of 84.6 mV/dec. The distribution of electric fields in the quasi-two-dimensional β-Ga2O3 MESFETs was simulated to analyze the role of the dielectric h-BN field plate in improving the off-state breakdown voltage. The stability of the field-plated β-Ga2O3 MESFET in air was confirmed after storing the MESFET in ambient air for one month. Our results pave the way for unlocking the full potential of β-Ga2O3 for use in a high-power nano-device with an ultrahigh breakdown voltage.

  11. Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe degradat......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...... degradation of the performance of the circuit and without the need for a repeating programming. In this way the noise originating from any resistance previously used for the definition of the operating point is avoided completely and, moreover, by avoiding the input high-pass filter both the saturation...

  12. Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide

    Science.gov (United States)

    Sangwan, Vinod K.; Lee, Hong-Sub; Bergeron, Hadallia; Balla, Itamar; Beck, Megan E.; Chen, Kan-Sheng; Hersam, Mark C.

    2018-02-01

    Memristors are two-terminal passive circuit elements that have been developed for use in non-volatile resistive random-access memory and may also be useful in neuromorphic computing. Memristors have higher endurance and faster read/write times than flash memory and can provide multi-bit data storage. However, although two-terminal memristors have demonstrated capacity for basic neural functions, synapses in the human brain outnumber neurons by more than a thousandfold, which implies that multi-terminal memristors are needed to perform complex functions such as heterosynaptic plasticity. Previous attempts to move beyond two-terminal memristors, such as the three-terminal Widrow-Hoff memristor and field-effect transistors with nanoionic gates or floating gates, did not achieve memristive switching in the transistor. Here we report the experimental realization of a multi-terminal hybrid memristor and transistor (that is, a memtransistor) using polycrystalline monolayer molybdenum disulfide (MoS2) in a scalable fabrication process. The two-dimensional MoS2 memtransistors show gate tunability in individual resistance states by four orders of magnitude, as well as large switching ratios, high cycling endurance and long-term retention of states. In addition to conventional neural learning behaviour of long-term potentiation/depression, six-terminal MoS2 memtransistors have gate-tunable heterosynaptic functionality, which is not achievable using two-terminal memristors. For example, the conductance between a pair of floating electrodes (pre- and post-synaptic neurons) is varied by a factor of about ten by applying voltage pulses to modulatory terminals. In situ scanning probe microscopy, cryogenic charge transport measurements and device modelling reveal that the bias-induced motion of MoS2 defects drives resistive switching by dynamically varying Schottky barrier heights. Overall, the seamless integration of a memristor and transistor into one multi-terminal device could

  13. Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

    Science.gov (United States)

    Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

    2018-01-01

    An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

  14. Low-voltage polymer/small-molecule blend organic thin-film transistors and circuits fabricated via spray deposition

    Energy Technology Data Exchange (ETDEWEB)

    Hunter, By Simon; Anthopoulos, Thomas D., E-mail: t.anthopoulos@ic.ac.uk [Department of Physics and Centre for Plastic Electronics, Imperial College London, South Kensington SW7 2AZ (United Kingdom); Ward, Jeremy W.; Jurchescu, Oana D. [Department of Physics, Wake Forest University, Winston-Salem, North Carolina 27109 (United States); Payne, Marcia M.; Anthony, John E. [Department of Chemistry, University of Kentucky, Lexington, Kentucky 40506 (United States)

    2015-06-01

    Organic thin-film electronics have long been considered an enticing candidate in achieving high-throughput manufacturing of low-power ubiquitous electronics. However, to achieve this goal, more work is required to reduce operating voltages and develop suitable mass-manufacture techniques. Here, we demonstrate low-voltage spray-cast organic thin-film transistors based on a semiconductor blend of 2,8-difluoro- 5,11-bis (triethylsilylethynyl) anthradithiophene and poly(triarylamine). Both semiconductor and dielectric films are deposited via successive spray deposition in ambient conditions (air with 40%–60% relative humidity) without any special precautions. Despite the simplicity of the deposition method, p-channel transistors with hole mobilities of >1 cm{sup 2}/Vs are realized at −4 V operation, and unipolar inverters operating at −6 V are demonstrated.

  15. Effect of neutron irradiation on the breakdown voltage of power MOSFET's

    International Nuclear Information System (INIS)

    Hasan, S.M.Y.; Kosier, S.L.; Schrimpf, R.D.; Galloway, K.F.

    1994-01-01

    The effect of neutron irradiation on power metal-oxide-semiconductor field effect transistor (power MOSFET) breakdown voltage has been investigated. Transistors with various breakdown voltage ratings were irradiated in a TRIGA nuclear reactor with cumulative fluence levels up to 5 x 10 14 neutrons/cm 2 (1 MeV equivalent). Noticeable increases in the breakdown voltages are observed in n-type MOSFET's after 10 13 neutrons/cm 2 and in p-type MOSFETs after 10 12 neutrons/cm 2 . An increase in breakdown voltage of as much as 30% is observed after 5 x 10 14 neutrons/cm 2 . The increase in breakdown voltage is attributed to the neutron-irradiation-induced defects which decrease the mean free path and trap majority carriers in the space charge region. The effect of positive trapped oxide charge due to concomitant gamma radiation and the effect of the termination structure on the increase in breakdown voltage are considered. An empirical model is presented to predict the value of the breakdown voltage as a function of neutron fluence

  16. Development of a terminal voltage stabilization system for the FOTIA ...

    Indian Academy of Sciences (India)

    Abstract. A terminal voltage stabilization system for the folded tandem ion accelerator (FOTIA) was developed and is in continuous use. The system achieves good voltage stabilization, eliminates ground loops and noise interference. It incorporates a correcting circuit for compensating the mains frequency variations in the ...

  17. Research into the Effect of Supercapacitor Terminal Voltage on Regenerative Suspension Energy-Regeneration and Dynamic Performance

    Directory of Open Access Journals (Sweden)

    Ruochen Wang

    2017-01-01

    Full Text Available To study the effect of supercapacitor initial terminal voltage on the regenerative and semiactive suspension energy-regeneration and dynamic performance, firstly, the relationship between supercapacitor terminal voltage and linear motor electromagnetic damping force and that between supercapacitor terminal voltage and recycled energy by the supercapacitor in one single switching period were both analyzed. The result shows that the linear motor electromagnetic damping force is irrelevant to the supercapacitor terminal voltage, and the recycled energy by the supercapacitor reaches the maximum when initial terminal voltage of the supercapacitor equals output terminal voltage of the linear motor. Then, performances of system dynamics and energy-regeneration were studied as the supercapacitor initial terminal voltage varied in situations of B level and C level road. The result showed that recycled energy by the supercapacitor increased at first and then decreased while the dynamic performance had no obvious change. On the basis of previous study, a mode-switching control strategy of supercapacitor for the regenerative and semiactive suspension system was proposed, and the mode-switching rule was built. According to simulation and experiment results, the system energy-regeneration efficiency can be increased by utilizing the control strategy without influencing suspension dynamic performance, which is highly valuable to practical engineering.

  18. Four-terminal circuit element with photonic core

    Science.gov (United States)

    Sampayan, Stephen

    2017-08-29

    A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated based on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.

  19. Investigation of channel width-dependent threshold voltage variation in a-InGaZnO thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Kuan-Hsien; Chou, Wu-Ching [Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Wu, Ming-Siou; Hung, Yi-Syuan; Sze, Simon M. [Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Hung, Pei-Hua; Chu, Ann-Kuo [Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Hsieh, Tien-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Yeh, Bo-Liang [Advanced Display Technology Research Center, AU Optronics, No. 1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsinchu 30078, Taiwan (China)

    2014-03-31

    This Letter investigates abnormal channel width-dependent threshold voltage variation in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Unlike drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, the wider the channel, the larger the threshold voltage observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider channel devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast IV measurement is utilized to demonstrate the self-heating induced anomalous channel width-dependent threshold voltage variation.

  20. Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

    KAUST Repository

    Petti, Luisa; Pattanasattayavong, Pichaya; Lin, Yen-Hung; Mü nzenrieder, Niko; Cantarella, Giuseppe; Yaacobi-Gross, Nir; Yan, Feng; Trö ster, Gerhard; Anthopoulos, Thomas D.

    2017-01-01

    , depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as −3.5 V. Importantly, discrete CuSCN transistors

  1. Ultra Low Voltage Class AB Switched Current Memory Cells Based on Floating Gate Transistors

    DEFF Research Database (Denmark)

    Mucha, Igor

    1999-01-01

    current memory cells were designed using a CMOS process with threshold voltages V-T0n = \\V-T0p\\ = 0.9 V for the n- and p-channel devices. Both hand calculations and PSPICE simulations showed that the designed example switched current memory cell allowed a maximum signal range better than +/-18 mu......A proposal for a class AB switched current memory cell, suitable for ultra-low-voltage applications is presented. The proposal employs transistors with floating gates, allowing to build analog building blocks for ultralow supply voltage operation also in CMOS processes with high threshold voltages....... This paper presents the theoretical basis for the design of "floating-gate'' switched current memory cells by giving a detailed description and analysis of the most important impacts degrading the performance of the cells. To support the theoretical assumptions circuits based on "floating-gate'' switched...

  2. Application of pentacene thin-film transistors with controlled threshold voltages to enhancement/depletion inverters

    Science.gov (United States)

    Takahashi, Hajime; Hanafusa, Yuki; Kimura, Yoshinari; Kitamura, Masatoshi

    2018-03-01

    Oxygen plasma treatment has been carried out to control the threshold voltage in organic thin-film transistors (TFTs) having a SiO2 gate dielectric prepared by rf sputtering. The threshold voltage linearly changed in the range of -3.7 to 3.1 V with the increase in plasma treatment time. Although the amount of change is smaller than that for organic TFTs having thermally grown SiO2, the tendency of the change was similar to that for thermally grown SiO2. To realize different plasma treatment times on the same substrate, a certain region on the SiO2 surface was selected using a shadow mask, and was treated with oxygen plasma. Using the process, organic TFTs with negative threshold voltages and those with positive threshold voltages were fabricated on the same substrate. As a result, enhancement/depletion inverters consisting of the organic TFTs operated at supply voltages of 5 to 15 V.

  3. Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

    KAUST Repository

    Petti, Luisa

    2017-03-17

    We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V−1 s−1 and 0.013 cm2 V−1 s−1, respectively, current on/off ratio in the range 102–104, and maximum operating voltages between −3.5 and −10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as −3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

  4. Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

    2015-10-15

    Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

  5. Voltage-Controlled Floating Resistor Using DDCC

    Directory of Open Access Journals (Sweden)

    M. Kumngern

    2011-04-01

    Full Text Available This paper presents a new simple configuration to realize the voltage-controlled floating resistor, which is suitable for integrated circuit implementation. The proposed resistor is composed of three main components: MOS transistor operating in the non-saturation region, DDCC, and MOS voltage divider. The MOS transistor operating in the non-saturation region is used to configure a floating linear resistor. The DDCC and the MOS transistor voltage divider are used for canceling the nonlinear component term of MOS transistor in the non-saturation region to obtain a linear current/voltage relationship. The DDCC is employed to provide a simple summer of the circuit. This circuit offers an ease for realizing the voltage divider circuit and the temperature effect that includes in term of threshold voltage can be compensated. The proposed configuration employs only 16 MOS transistors. The performances of the proposed circuit are simulated with PSPICE to confirm the presented theory.

  6. Low-frequency noise in single electron tunneling transistor

    DEFF Research Database (Denmark)

    Tavkhelidze, A.N.; Mygind, Jesper

    1998-01-01

    The noise in current biased aluminium single electron tunneling (SET) transistors has been investigated in the frequency range of 5 mHz ..., we find the same input charge noise, typically QN = 5 × 10–4 e/Hz1/2 at 10 Hz, with and without the HF shielding. At lower frequencies, the noise is due to charge trapping, and the voltage noise pattern superimposed on the V(Vg) curve (voltage across transistor versus gate voltage) strongly depends...... when ramping the junction voltage. Dynamic trapping may limit the high frequency applications of the SET transistor. Also reported on are the effects of rf irradiation and the dependence of the SET transistor noise on bias voltage. ©1998 American Institute of Physics....

  7. High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

    Science.gov (United States)

    Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

    2014-05-21

    We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

  8. Phosphorylation of purified mitochondrial Voltage-Dependent Anion Channel by c-Jun N-terminal Kinase-3 modifies channel voltage-dependence

    Directory of Open Access Journals (Sweden)

    Rajeev Gupta

    2017-06-01

    Full Text Available Voltage-Dependent Anion Channel (VDAC phosphorylated by c-Jun N-terminal Kinase-3 (JNK3 was incorporated into the bilayer lipid membrane. Single-channel electrophysiological properties of the native and the phosphorylated VDAC were compared. The open probability versus voltage curve of the native VDAC displayed symmetry around the voltage axis, whereas that of the phosphorylated VDAC showed asymmetry. This result indicates that phosphorylation by JNK3 modifies voltage-dependence of VDAC.

  9. Phosphorylation of purified mitochondrial Voltage-Dependent Anion Channel by c-Jun N-terminal Kinase-3 modifies channel voltage-dependence.

    Science.gov (United States)

    Gupta, Rajeev; Ghosh, Subhendu

    2017-06-01

    Voltage-Dependent Anion Channel (VDAC) phosphorylated by c-Jun N-terminal Kinase-3 (JNK3) was incorporated into the bilayer lipid membrane. Single-channel electrophysiological properties of the native and the phosphorylated VDAC were compared. The open probability versus voltage curve of the native VDAC displayed symmetry around the voltage axis, whereas that of the phosphorylated VDAC showed asymmetry. This result indicates that phosphorylation by JNK3 modifies voltage-dependence of VDAC.

  10. Neutron generator ion source pulser

    International Nuclear Information System (INIS)

    Peelman, H.E.

    1987-01-01

    This patent describes, for use with a pulsed neutron generator in a logging tool lowered in a borehole, a pulsed high voltage source having an output terminal adapted to be connected to pulse neutron generator. The power supply comprises: (a) high voltage supply means; (b) field effect transistor means comprising at least a pair of field effect transistors serially connected between the high voltage supply means and ground; (c) an output terminal between the two transistors of the field effect transistor means, the output terminal adapted to be connected by a conductor to provide pulsed high voltage to a neutron generator; (d) control pulse forming means connected to the gates of the respective two transistors, the pulse forming means forming control pulses selectively switching the transistors off and on in timed sequence to thereby connect the output terminal to the high voltage supply means, and (e) diode means connected to the gates of the transistors to limit gate voltage for operation of the transistors

  11. Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

    Science.gov (United States)

    Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

    2018-07-01

    We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

  12. Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

    Science.gov (United States)

    Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

    2018-07-20

    We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

  13. Electrically tunable spin polarization in silicene: A multi-terminal spin density matrix approach

    International Nuclear Information System (INIS)

    Chen, Son-Hsien

    2016-01-01

    Recent realized silicene field-effect transistor yields promising electronic applications. Using a multi-terminal spin density matrix approach, this paper presents an analysis of the spin polarizations in a silicene structure of the spin field-effect transistor by considering the intertwined intrinsic and Rashba spin–orbit couplings, gate voltage, Zeeman splitting, as well as disorder. Coexistence of the stagger potential and intrinsic spin–orbit coupling results in spin precession, making any in-plane polarization directions reachable by the gate voltage; specifically, the intrinsic coupling allows one to electrically adjust the in-plane components of the polarizations, while the Rashba coupling to adjust the out-of-plan polarizations. Larger electrically tunable ranges of in-plan polarizations are found in oppositely gated silicene than in the uniformly gated silicene. Polarizations in different phases behave distinguishably in weak disorder regime, while independent of the phases, stronger disorder leads to a saturation value. - Highlights: • Density matrix with spin rotations enables multi-terminal arbitrary spin injections. • Gate-voltage tunable in-plane polarizations require intrinsic SO coupling. • Gate-voltage tunable out-of-plane polarizations require Rashba SO coupling. • Oppositely gated silicene yields a large tunable range of in-plan polarizations. • Polarizations in different phases behave distinguishably only in weak disorder.

  14. Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

    Science.gov (United States)

    Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

    2018-04-01

    In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

  15. Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

    Directory of Open Access Journals (Sweden)

    P. T. Tue

    2013-01-01

    Full Text Available We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT which uses solution-processed indium-tin-oxide (ITO and lead-zirconium-titanate (PZT film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1 a reduction of the charge injection and (2 an increase of effective coercive voltage dropped on the insulator.

  16. CMOS-compatible high-voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Parpia, Z

    1988-01-01

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

  17. Analysis of transistor and snubber turn-off dynamics in high-frequency high-voltage high-power converters

    Science.gov (United States)

    Wilson, P. M.; Wilson, T. G.; Owen, H. A., Jr.

    Dc to dc converters which operate reliably and efficiently at switching frequencies high enough to effect substantial reductions in the size and weight of converter energy storage elements are studied. A two winding current or voltage stepup (buck boost) dc-to-dc converter power stage submodule designed to operate in the 2.5-kW range, with an input voltage range of 110 to 180 V dc, and an output voltage of 250 V dc is emphasized. In order to assess the limitations of present day component and circuit technologies, a design goal switching frequency of 10 kHz was maintained. The converter design requirements represent a unique combination of high frequency, high voltage, and high power operation. The turn off dynamics of the primary circuit power switching transistor and its associated turn off snubber circuitry are investigated.

  18. Investigation of defect-induced abnormal body current in fin field-effect-transistors

    International Nuclear Information System (INIS)

    Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Yang, Ren-Ya; Cheng, Osbert; Huang, Cheng-Tung

    2015-01-01

    This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal

  19. Tungsten oxide proton conducting films for low-voltage transparent oxide-based thin-film transistors

    International Nuclear Information System (INIS)

    Zhang, Hongliang; Wan, Qing; Wan, Changjin; Wu, Guodong; Zhu, Liqiang

    2013-01-01

    Tungsten oxide (WO x ) electrolyte films deposited by reactive magnetron sputtering showed a high room temperature proton conductivity of 1.38 × 10 −4 S/cm with a relative humidity of 60%. Low-voltage transparent W-doped indium-zinc-oxide thin-film transistors gated by WO x -based electrolytes were self-assembled on glass substrates by one mask diffraction method. Enhancement mode operation with a large current on/off ratio of 4.7 × 10 6 , a low subthreshold swing of 108 mV/decade, and a high field-effect mobility 42.6 cm 2 /V s was realized. Our results demonstrated that WO x -based proton conducting films were promising gate dielectric candidates for portable low-voltage oxide-based devices.

  20. On theory of single-molecule transistor

    International Nuclear Information System (INIS)

    Tran Tien Phuc

    2009-01-01

    The results of the study on single-molecule transistor are mainly investigated in this paper. The structure of constructed single-molecule transistor is similar to a conventional MOSFET. The conductive channel of the transistors is a single-molecule of halogenated benzene derivatives. The chemical simulation software CAChe was used to design and implement for the essential parameter of the molecules utilized as the conductive channel. The GUI of Matlab has been built to design its graphical interface, calculate and plot the output I-V characteristic curves for the transistor. The influence of temperature, length and width of the conductive channel, and gate voltage is considered. As a result, the simulated curves are similar to the traditional MOSFET's. The operating temperature range of the transistors is wider compared with silicon semiconductors. The supply voltage for transistors is only about 1 V. The size of transistors in this research is several nanometers.

  1. Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

    International Nuclear Information System (INIS)

    Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

    2015-01-01

    Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  2. Switching Characteristics of Ferroelectric Transistor Inverters

    Science.gov (United States)

    Laws, Crystal; Mitchell, Coey; MacLeod, Todd C.; Ho, Fat D.

    2010-01-01

    This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

  3. Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

    Science.gov (United States)

    Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

    2018-01-03

    Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

  4. High voltage designing of 300.000 Volt

    International Nuclear Information System (INIS)

    Hutapea, Sumihar.

    1978-01-01

    Some methods of designing a.c and d.c high voltage supplies are discussed. A high voltage supply for the Gama Research Centre accelerator is designed using transistor pulse generators. High voltage transformers being made using radio transistor ferrits as a core are also discussed. (author)

  5. Experimental study on the 4H-SiC-based VDMOSFETs with lightly doped P-well field-limiting rings termination

    Science.gov (United States)

    He, Yan Jing; Lv, Hong Liang; Tang, Xiao Yan; Song, Qing Wen; Zhang, Yi Meng; Han, Chao; Zhang, Yi Men; Zhang, Yu Ming

    2017-03-01

    A lightly doped P-well field-limiting rings (FLRs) termination on 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) has been investigated. Based on the simulation, the proposed termination applied to 4H-SiC VDMOSFET could achieve an almost same breakdown voltage (BV) and have the advantage of lower ion-implantation damage comparing with P+ FLRs termination. Meanwhile, this kind of termination also reduces the difficulty and consumption of fabrication process. 4H-SiC VDMOSFETs with lightly doped P-well (FLRs) termination have been fabricated on 10 μm thick epi-layer with nitrogen doping concentration of 6.2 × 1015 cm-3. The maximum breakdown voltage of the 4H-SiC VDMOSFETs has achieved as high as 1610 V at a current of 15 μA, which is very close to the simulated result of 1643 V and about 90% of the plane parallel breakdown voltage of 1780 V. It is considered that P-well FLRs termination is an effective, robust and process-tolerant termination structure suitable for 4H-SiC VDMOSFET.

  6. A New Contribution in Reducing Electric Field Distribution Within/Around Medium Voltage Underground Cable Terminations

    Directory of Open Access Journals (Sweden)

    S. S. Desouky

    2017-10-01

    Full Text Available Ιn medium voltage cables, the stress control layers play an important part in controlling the electric field distribution around the medium voltage underground cable terminations. Underground cable accessories, used in medium voltage cable systems, need a stress control tube in order to maintain and control the insulation level which is designed for long life times. The term “electrical stress control” refers to the cable termination analysis of optimizing the electrical stress in the area of insulation shield cutback to reduce the electrical field concentration at this point in order to reduce breakdown in the cable insulation. This paper presents the effect of some materials of different relative permittivities and geometrical regulation with the curved shape stress relief cones on the electric field distribution of cable termination. The optimization was done by comparing the results of eight materials used. Also, the effect of the change in the thickness of the stress control tube is presented. The modeling design is very important for engineers to find the optimal solution of terminator design of medium voltage cables. This paper also describes the evolution of stress control systems and their benefits. A developed program using Finite Element Method (FEM has calculated a numerical study to the stress control layering electric field distribution.

  7. Proposal for a dual-gate spin field effect transistor: A device with very small switching voltage and a large ON to OFF conductance ratio

    Science.gov (United States)

    Wan, J.; Cahay, M.; Bandyopadhyay, S.

    2008-06-01

    We propose a new dual gate spin field effect transistor (SpinFET) consisting of a quasi one-dimensional semiconductor channel sandwiched between two half-metallic contacts. The gate voltage aligns and de-aligns the incident electron energy with Ramsauer resonance levels in the channel, thereby modulating the source-to-drain conductance. The device can be switched from ON to OFF with a few mV change in the gate voltage, resulting in exceedingly low dynamic power dissipation during switching. The conductance ON/OFF ratio stays fairly large ( ∼60) up to a temperature of 10 K. This conductance ratio is comparable to that achievable with carbon nanotube transistors.

  8. Low-voltage protonic/electronic hybrid indium zinc oxide synaptic transistors on paper substrates

    International Nuclear Information System (INIS)

    Wu, Guodong; Wan, Changjin; Wan, Qing; Zhou, Jumei; Zhu, Liqiang

    2014-01-01

    Low-voltage (1.5 V) indium zinc oxide (IZO)-based electric-double-layer (EDL) thin-film transistors (TFTs) gated by nanogranular proton conducting SiO 2 electrolyte films are fabricated on paper substrates. Both enhancement-mode and depletion-mode operation are obtained by tuning the thickness of the IZO channel layer. Furthermore, such flexible IZO protonic/electronic hybrid EDL TFTs can be used as artificial synapses, and synaptic stimulation response and short-term synaptic plasticity function are demonstrated. The protonic/electronic hybrid EDL TFTs on paper substrates proposed here are promising for low-power flexible paper electronics, artificial synapses and bioelectronics. (paper)

  9. Impurity Deionization Effects on Surface Recombination DC Current-Voltage Characteristics in MOS Transistors

    International Nuclear Information System (INIS)

    Chen Zuhui; Jie Binbin; Sah Chihtang

    2010-01-01

    Impurity deionization on the direct-current current-voltage characteristics from electron-hole recombination (R-DCIV) at SiO 2 /Si interface traps in MOS transistors is analyzed using the steady-state Shockley-Read-Hall recombination kinetics and the Fermi distributions for electrons and holes. Insignificant distortion is observed over 90% of the bell-shaped R-DCIV curves centered at their peaks when impurity deionization is excluded in the theory. This is due to negligible impurity deionization because of the much lower electron and hole concentrations at the interface than the impurity concentration in the 90% range. (invited papers)

  10. Basic matrix algebra and transistor circuits

    CERN Document Server

    Zelinger, G

    1963-01-01

    Basic Matrix Algebra and Transistor Circuits deals with mastering the techniques of matrix algebra for application in transistors. This book attempts to unify fundamental subjects, such as matrix algebra, four-terminal network theory, transistor equivalent circuits, and pertinent design matters. Part I of this book focuses on basic matrix algebra of four-terminal networks, with descriptions of the different systems of matrices. This part also discusses both simple and complex network configurations and their associated transmission. This discussion is followed by the alternative methods of de

  11. Self-assembled monolayer exchange reactions as a tool for channel interface engineering in low-voltage organic thin-film transistors.

    Science.gov (United States)

    Lenz, Thomas; Schmaltz, Thomas; Novak, Michael; Halik, Marcus

    2012-10-02

    In this work, we compared the kinetics of monolayer self-assembly long-chained carboxylic acids and phosphonic acids on thin aluminum oxide surfaces and investigated their dielectric properties in capacitors and low-voltage organic thin-film transistors. Phosphonic acid anchor groups tend to substitute carboxylic acid molecules on aluminum oxide surfaces and thus allow the formation of mixed or fully exchanged monolayers. With different alkyl chain substituents (n-alkyl or fluorinated alkyl chains), the exchange reaction can be monitored as a function of time by static contact angle measurements. The threshold voltage in α,α'-dihexyl-sexithiophene thin-film transistors composed of such mixed layer dielectrics correlates with the exchange progress and can be tuned from negative to positive values or vice versa depending on the dipole moment of the alkyl chain substituents. The change in the dipole moment with increasing exchange time also shifts the capacitance of these devices. The rate constants for exchange reactions determined by the time-dependent shift of static contact angle, threshold voltage, and capacitance exhibit virtually the same value thus proving the exchange kinetics to be highly controllable. In general, the exchange approach is a powerful tool in interface engineering, displaying a great potential for tailoring of device characteristics.

  12. Colour tuneable light-emitting transistor

    Energy Technology Data Exchange (ETDEWEB)

    Feldmeier, Eva J.; Melzer, Christian; Seggern, Heinz von [Electronic Materials Department, Institute of Materials Science, Technische Universitaet Darmstadt (Germany)

    2010-07-01

    In recent years the interest in ambipolar organic light-emitting field-effect transistors has increased steadily as the devices combine switching behaviour of transistors with light emission. Usually, small molecules and polymers with a band gap in the visible spectral range serve as semiconducting materials. Mandatory remain balanced injection and transport properties for both charge carrier types to provide full control of the spatial position of the recombination zone of electrons and holes in the transistor channel via the applied voltages. As will be presented here, the spatial control of the recombination zone opens new possibilities towards light-emitting devices with colour tuneable emission. In our contribution an organic light-emitting field-effect transistors is presented whose emission colour can be changed by the applied voltages. The organic top-contact field-effect transistor is based on a parallel layer stack of acenes serving as organic transport and emission layers. The transistor displays ambipolar characteristics with a narrow recombination zone within the transistor channel. During operation the recombination zone can be moved by a proper change in the drain and gate bias from one organic semiconductor layer to another one inducing a change in the emission colour. In the presented example the emission maxima can be switched from 530 nm to 580 nm.

  13. A built-in current sensor using thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Hatzopoulos, A A [Department of Electrical and Computer Eng., Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Siskos, S [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Dimitriadis, C A [Department of Physics, Microelectronic device characterization and design Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Papadopoulos, N [Department of Electrical and Computer Eng., Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Pappas, I [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Nalpantidis, L [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece)

    2005-01-01

    A simple current mirror using TFTs with input terminals which are capacitively coupled to the TFT gate, is used in this work, to design a built-in current sensor (BICS). The important feature in this application is that the voltage drop across the sensing TFT device can be reduced to almost zero value, while preserving transistor operation in the saturation region. This makes the proposed BICS appropriate for TFT applications without affecting the circuit operation. It also results in adequate linearity for the current monitoring, making the structure applicable to digital as well as to analog and mixed-signal circuit testing.

  14. The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

    International Nuclear Information System (INIS)

    Sah, C.-T.; Jie Binbin

    2009-01-01

    This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

  15. Theoretical and experimental studies of the current–voltage and capacitance–voltage of HEMT structures and field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Tarasova, E. A.; Obolenskaya, E. S., E-mail: obolensk@rf.unn.ru; Hananova, A. V.; Obolensky, S. V. [Lobachevsky State University of Nizhny Novgorod (NNSU) (Russian Federation); Zemliakov, V. E.; Egorkin, V. I. [National Research University of Electronic Technology (MIET) (Russian Federation); Nezhenzev, A. V. [Lobachevsky State University of Nizhny Novgorod (NNSU) (Russian Federation); Saharov, A. V.; Zazul’nokov, A. F.; Lundin, V. V.; Zavarin, E. E. [Russian Academy of Sciences, Ioffe Physical–Technical Institute (Russian Federation); Medvedev, G. V. [JSC RPE Salut (Russian Federation)

    2016-12-15

    The sensitivity of classical n{sup +}/n{sup –} GaAs and AlGaN/GaN structures with a 2D electron gas (HEMT) and field-effect transistors based on these structures to γ-neutron exposure is studied. The levels of their radiation hardness were determined. A method for experimental study of the structures on the basis of a differential analysis of their current–voltage characteristics is developed. This method makes it possible to determine the structure of the layers in which radiation-induced defects accumulate. A procedure taking into account changes in the plate area of the experimentally measured barrier-contact capacitance associated with the emergence of clusters of radiation-induced defects that form dielectric inclusions in the 2D-electron-gas layer is presented for the first time.

  16. Static Characteristics of the Ferroelectric Transistor Inverter

    Science.gov (United States)

    Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

    2010-01-01

    The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

  17. Distributed amplifier using Josephson vortex flow transistors

    International Nuclear Information System (INIS)

    McGinnis, D.P.; Beyer, J.B.; Nordman, J.E.

    1986-01-01

    A wide-band traveling wave amplifier using vortex flow transistors is proposed. A vortex flow transistor is a long Josephson junction used as a current controlled voltage source. The dual nature of this device to the field effect transistor is exploited. A circuit model of this device is proposed and a distributed amplifier utilizing 50 vortex flow transistors is predicted to have useful gain to 100 GHz

  18. The Complete Semiconductor Transistor and Its Incomplete Forms

    International Nuclear Information System (INIS)

    Jie Binbin; Sah, C.-T.

    2009-01-01

    This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

  19. Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

    International Nuclear Information System (INIS)

    Luo Jun; Zhao Sheng-Lei; Mi Min-Han; Zhang Jin-Cheng; Ma Xiao-Hua; Hao Yue; Chen Wei-Wei; Hou Bin

    2016-01-01

    The effects of gate length L G on breakdown voltage V BR are investigated in AlGaN/GaN high-electron-mobility transistors (HEMTs) with L G = 1 μm∼ 20 μm. With the increase of L G , V BR is first increased, and then saturated at L G = 3 μm. For the HEMT with L G = 1 μm, breakdown voltage V BR is 117 V, and it can be enhanced to 148 V for the HEMT with L G = 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage. A similar suppression of the impact ionization exists in the HEMTs with L G > 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with L G = 3 μm∼20 μm, and their breakdown voltages are in a range of 140 V–156 V. (paper)

  20. Enhanced intrinsic voltage gain in artificially stacked bilayer CVD graphene field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Pandey, Himadri; Kataria, Satender [RWTH Aachen University, Chair for Electronic Devices, Aachen (Germany); University of Siegen, School of Science and Technology, Siegen (Germany); Aguirre-Morales, Jorge-Daniel; Fregonese, Sebastien; Zimmer, Thomas [IMS Laboratory, Centre National de la Recherche Scientifique, University of Bordeaux, Talence (France); Passi, Vikram [University of Siegen, School of Science and Technology, Siegen (Germany); AMO GmbH, Advanced Microelectronics Center Aachen (Germany); Iannazzo, Mario; Alarcon, Eduard [Technical University of Catalonia, Department of Electronics Engineering, UPC, Barcelona (Spain); Lemme, Max C. [RWTH Aachen University, Chair for Electronic Devices, Aachen (Germany); University of Siegen, School of Science and Technology, Siegen (Germany); AMO GmbH, Advanced Microelectronics Center Aachen (Germany)

    2017-11-15

    We report on electronic transport in dual-gate, artificially stacked bilayer graphene field effect transistors (BiGFETs) fabricated from large-area chemical vapor deposited (CVD) graphene. The devices show enhanced tendency to current saturation, which leads to reduced minimum output conductance values. This results in improved intrinsic voltage gain of the devices when compared to monolayer graphene FETs. We employ a physics based compact model originally developed for Bernal stacked bilayer graphene FETs (BSBGFETs) to explore the observed phenomenon. The improvement in current saturation may be attributed to increased charge carrier density in the channel and thus reduced saturation velocity due to carrier-carrier scattering. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  1. Schottky barrier diode embedded AlGaN/GaN switching transistor

    International Nuclear Information System (INIS)

    Park, Bong-Ryeol; Lee, Jung-Yeon; Lee, Jae-Gil; Lee, Dong-Myung; Cha, Ho-Young; Kim, Moon-Kyung

    2013-01-01

    We developed a Schottky barrier diode (SBD) embedded AlGaN/GaN switching transistor to allow negative current flow during off-state condition. An SBD was embedded in a recessed normally-off AlGaN/GaN-on-Si metal-oxide-semiconductor heterostructure field-effect transistor (MOSHFET). The fabricated device exhibited normally-off characteristics with a gate threshold voltage of 2.8 V, a diode turn-on voltage of 1.2 V, and a breakdown voltage of 849 V for the anode-to-drain distance of 8 µm. An on-resistance of 2.66 mΩcm 2 was achieved at a gate voltage of 16 V in the forward transistor mode. Eliminating the need for an external diode, the SBD embedded switching transistor has advantages of significant reduction in parasitic inductance and chip area. (paper)

  2. Transistors using crystalline silicon devices on glass

    Science.gov (United States)

    McCarthy, Anthony M.

    1995-01-01

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

  3. Three-terminal superconducting devices

    International Nuclear Information System (INIS)

    Gallagher, W.J.

    1985-01-01

    The transistor has a number of properties that make it so useful. The authors discuss these and the additional properties a transistor would need to have for high performance applications at temperatures where superconductivity could contribute advantages to system-level performance. These properties then serve as criteria by which to evaluate three-terminal devices that have been proposed for applications at superconducting temperatures. FETs can retain their transistor properties at low temperatures, but their power consumption is too large for high-speed, high-density cryogenic applications. They discuss in detail why demonstrated superconducting devices with three terminals -Josephson effect based devices, injection controlled weak links, and stacked tunnel junction devices such as the superconducting transistor proposed by K. Gray and the quiteron -- each fail to have true transistor-like properties. They conclude that the potentially very rewarding search for a transistor compatible with superconductivity in high performance applications must be in new directions

  4. An All-Solid-State pH Sensor Employing Fluorine-Terminated Polycrystalline Boron-Doped Diamond as a pH-Insensitive Solution-Gate Field-Effect Transistor.

    Science.gov (United States)

    Shintani, Yukihiro; Kobayashi, Mikinori; Kawarada, Hiroshi

    2017-05-05

    A fluorine-terminated polycrystalline boron-doped diamond surface is successfully employed as a pH-insensitive SGFET (solution-gate field-effect transistor) for an all-solid-state pH sensor. The fluorinated polycrystalline boron-doped diamond (BDD) channel possesses a pH-insensitivity of less than 3mV/pH compared with a pH-sensitive oxygenated channel. With differential FET (field-effect transistor) sensing, a sensitivity of 27 mv/pH was obtained in the pH range of 2-10; therefore, it demonstrated excellent performance for an all-solid-state pH sensor with a pH-sensitive oxygen-terminated polycrystalline BDD SGFET and a platinum quasi-reference electrode, respectively.

  5. Efficient simulation of power MOS transistors

    NARCIS (Netherlands)

    Ugryumova, M.; Schilders, W.H.A.

    2011-01-01

    In this report we present a few industrial problems related to modeling of MOS transistors. We suggest an efficient algorithm for computing output current at the top ports of power MOS transistors for given voltage excitations. The suggested algorithm exploits the connection between the resistor and

  6. AlN/GaN heterostructures for normally-off transistors

    Energy Technology Data Exchange (ETDEWEB)

    Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.; Tereshenko, O. E. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation); Abgaryan, K. K.; Reviznikov, D. L. [Dorodnicyn Computing Centre of the Russian Academy of Sciences (Russian Federation); Zemlyakov, V. E.; Egorkin, V. I. [National Research University of Electronic Technology (MIET) (Russian Federation); Parnes, Ya. M.; Tikhomirov, V. G. [Joint Stock Company “Svetlana-Electronpribor” (Russian Federation); Prosvirin, I. P. [Russian Academy of Sciences, Boreskov Institute of Catalysis, Siberian Branch (Russian Federation)

    2017-03-15

    The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

  7. Proton migration mechanism for the instability of organic field-effect transistors

    NARCIS (Netherlands)

    Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.

    2009-01-01

    During prolonged application of a gate bias, organic field-effect transistors show an instability involving a gradual shift of the threshold voltage toward the applied gate bias voltage. We propose a model for this instability in p-type transistors with a silicon-dioxide gate dielectric, based on

  8. Controlling charge current through a DNA based molecular transistor

    Energy Technology Data Exchange (ETDEWEB)

    Behnia, S., E-mail: s.behnia@sci.uut.ac.ir; Fathizadeh, S.; Ziaei, J.

    2017-01-05

    Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I–V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive. - Highlights: • Modeling a DNA based molecular transistor and studying its transport properties. • Choosing the appropriate DNA sequence using the quantum chaos tools. • Choosing the functional interval for voltages via the inverse participation ratio tool. • Detecting the rectifier and negative differential resistance behavior of DNA.

  9. Direct observation of contact and channel resistance in pentacene four-terminal thin-film transistor patterned by laser ablation method

    International Nuclear Information System (INIS)

    Yagi, Iwao; Tsukagoshi, Kazuhito; Aoyagi, Yoshinobu

    2004-01-01

    We established a dry-etching patterning process for the channel formation of pentacene thin-film transistor, and fabricated a four-terminal device equipped with a gate electrode. The four-terminal device enabled us to divide two-terminal source-drain resistance into two components of contact resistance and pentacene channel resistance. We obtained direct evidence of a gate-voltagedependent contact resistance change: the gate-induced charge significantly reduced the contact resistance and increased source-drain current. Furthermore, the temperature dependence of the device clearly indicated that the contact resistance was much higher than the channel resistance and was dominated in the two-terminal total resistance of the device below 120 K. An observed activation energy of 80 meV for contact resistance was higher than that of 42 meV for pentacene channel resistance

  10. Low start-up voltage dc–dc converter with negative voltage control for thermoelectric energy harvesting

    Directory of Open Access Journals (Sweden)

    Pui-Sun Lei

    2015-01-01

    Full Text Available This Letter presents a low start-up voltage dc–dc converter for low-power thermoelectric systems which uses a native n-type MOS transistor as the start-up switch. The start-up voltage of the proposed converter is 300 mV and the converter does not need batteries to start up. The negative voltage control is proposed to reduce the leakage current caused by native n-type transistor and increase the efficiency. The proposed converter was designed using standard 0.18 µm CMOS process with chip size of 0.388 mm^2. The peak efficiency is 63% at load current of 1.5 mA. The proposed converter provides output voltage >1 V at maximum load current of 3.2 mA.

  11. IMPROVING BANDWIDTH OF FLIPPED VOLTAGE FOLLOWER USING GATE-BODY DRIVEN TECHNIQUE

    Directory of Open Access Journals (Sweden)

    VANDANA NIRANJAN

    2017-01-01

    Full Text Available In this paper, a new approach to enhance the bandwidth of flipped voltage follower is explored. The proposed approach is based on gate-body driven technique. This technique boosts the transconductance in a MOS transistor as both gate and body/bulk terminals are tied together and used as signal input. This novel technique appears as a good solution to merge the advantages of gate-driven and bulk-driven techniques and suppress their disadvantages. The gate-body driven technique utilizes body effect to enable low voltage low power operation and improves the overall performance of flipped voltage follower, providing it with low output impedance, high input impedance and bandwidth extension ratio of 2.614. The most attractive feature is that bandwidth enhancement has been achieved without use of any passive component or extra circuitry. Simulations in PSpice environment for 180 nm CMOS technology verified the predicted theoretical results. The improved flipped voltage follower is particularly interesting for high frequency low noise signal processing applications.

  12. Theory and application of dual-transistor charge separation analysis

    International Nuclear Information System (INIS)

    Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Sexton, F.W.; Shaneyfelt, M.R.

    1989-01-01

    The authors describe a dual-transistor charge separation method to evaluate the radiation response of MOS transistors. This method requires that n- and p-channel transistors with identically processed oxides be irradiated under identical conditions at the same oxide electric fields. Combining features of single-transistor midgap and mobility methods, the authors show how one may determine threshold voltage shifts due to oxide-trapped and interface-trapped charge from standard threshold voltage and mobility measurements. These measurements can be made at currents 2-5 orders of magnitude higher than those required for midgap, subthreshold slope, and charge-pumping methods. The dual-transistor method contains no adjustable parameters, and includes an internal self-consistency check. The accuracy of the method is verified by comparison to midgap, subthreshold slope, and charge-pumping methods for several MOS processes and technologies

  13. Simultaneous On-State Voltage and Bond-Wire Resistance Monitoring of Silicon Carbide MOSFETs

    Directory of Open Access Journals (Sweden)

    Nick Baker

    2017-03-01

    Full Text Available In fast switching power semiconductors, the use of a fourth terminal to provide the reference potential for the gate signal—known as a kelvin-source terminal—is becoming common. The introduction of this terminal presents opportunities for condition monitoring systems. This article demonstrates how the voltage between the kelvin-source and power-source can be used to specifically monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A Silicon Carbide Metal-Oxide-Semiconductor-Field-Effect Transistors (MOSFETs, it is shown that there are opposing trends in the evolution of the on-state resistances of both the bond-wires and the MOSFET die. In summary, after 50,000 temperature cycles, the resistance of the bond-wires increased by up to 2 mΩ, while the on-state resistance of the MOSFET dies decreased by approximately 1 mΩ. The conventional failure precursor (monitoring a single forward voltage cannot distinguish between semiconductor die or bond-wire degradation. Therefore, the ability to monitor both these parameters due to the presence of an auxiliary-source terminal can provide more detailed information regarding the aging process of a device.

  14. Dynamic range of low-voltage cascode current mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik; Shah, Peter Jivan

    1995-01-01

    Low-voltage cascode current mirrors are reviewed with respect to the design limitations imposed if all transistors in the mirror are required to operate in the saturation region. It is found that both a lower limit and an upper limit exist for the cascode transistor bias voltage. Further, the use....... The proposed configuration has the advantage of simplicity combined with a complete elimination of the need for fixed bias voltages or bias currents in the current mirror. A disadvantage is that it requires a higher input voltage to the current mirror...

  15. Monolithic acoustic graphene transistors based on lithium niobate thin film

    Science.gov (United States)

    Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

    2018-05-01

    This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

  16. Attofarad resolution capacitance-voltage measurement of nanometer scale field effect transistors utilizing ambient noise

    International Nuclear Information System (INIS)

    Gokirmak, Ali; Inaltekin, Hazer; Tiwari, Sandip

    2009-01-01

    A high resolution capacitance-voltage (C-V) characterization technique, enabling direct measurement of electronic properties at the nanoscale in devices such as nanowire field effect transistors (FETs) through the use of random fluctuations, is described. The minimum noise level required for achieving sub-aF (10 -18 F) resolution, the leveraging of stochastic resonance, and the effect of higher levels of noise are illustrated through simulations. The non-linear ΔC gate-source/drain -V gate response of FETs is utilized to determine the inversion layer capacitance (C inv ) and carrier mobility. The technique is demonstrated by extracting the carrier concentration and effective electron mobility in a nanoscale Si FET with C inv = 60 aF.

  17. Laser processing for bevel termination of high voltage pn junction in SiC

    International Nuclear Information System (INIS)

    Kubiak, A; Ruta, Ł; Rosowski, A; French, P

    2016-01-01

    Proper edge termination of the p-n junction in silicon carbide is a key requirement in the fabrication of discrete devices able to withstand high voltages in reverse polarization. Due to the hardness of SiC the creation of the bevel termination remains difficult using mechanical machining. The use of laser beam sources with medium wavelength (532 nm) gives new possibilities in the machining of the silicon carbide. The paper presents the fabrication of the bevel termination structure in SiC using a green DPSS laser equipped with scanner and dedicated rotating sample holder. Characterization of the resulting structures proves the high potential of the proposed approach. (paper)

  18. Improved transmission of electrostatic accelerator in a wide range of terminal voltages by controlling the focal strength of entrance acceleration tube

    Science.gov (United States)

    Lobanov, Nikolai R.; Tunningley, Thomas; Linardakis, Peter

    2018-04-01

    Tandem electrostatic accelerators often require the flexibility to operate at a variety of terminal voltages to accommodate various user requirements. However, the ion beam transmission will only be optimal for a limited range of terminal voltages. This paper describes the operational performance of a novel focusing system that expands the range of terminal voltages for optimal transmission. This is accomplished by controlling the gradient of the entrance of the low-energy tube, providing an additional focusing element. In this specific case it is achieved by applying up to 150 kV to the fifth electrode of the first unit of the accelerator tube. Numerical simulations and beam transmission tests have been performed to confirm the effectiveness of the lens. An analytical expression has been derived describing its focal properties. These tests demonstrate that the entrance lens control eliminates the need to short out sections of the tube for operation at low terminal voltage.

  19. Total dose effects on the matching properties of deep submicron MOS transistors

    International Nuclear Information System (INIS)

    Wang Yuxin; Hu Rongbin; Li Ruzhang; Chen Guangbing; Fu Dongbing; Lu Wu

    2014-01-01

    Based on 0.18 μm MOS transistors, for the first time, the total dose effects on the matching properties of deep submicron MOS transistors are studied. The experimental results show that the total dose radiation magnifies the mismatch among identically designed MOS transistors. In our experiments, as the radiation total dose rises to 200 krad, the threshold voltage and drain current mismatch percentages of NMOS transistors increase from 0.55% and 1.4% before radiation to 17.4% and 13.5% after radiation, respectively. PMOS transistors seem to be resistant to radiation damage. For all the range of radiation total dose, the threshold voltage and drain current mismatch percentages of PMOS transistors keep under 0.5% and 2.72%, respectively. (semiconductor devices)

  20. DC Voltage Control and Power-Sharing of Multi-Terminal DC Grids Based on Optimal DC Power Flow and Flexible Voltage Droop Strategy

    Directory of Open Access Journals (Sweden)

    F. Azma

    2015-06-01

    Full Text Available This paper develops an effective control framework for DC voltage control and power-sharing of multi-terminal DC (MTDC grids based on an optimal power flow (OPF procedure and the voltage-droop control. In the proposed approach, an OPF algorithm is executed at the secondary level to find optimal reference of DC voltages and active powers of all voltage-regulating converters. Then, the voltage droop characteristics of voltage-regulating converters, at the primary level, are tuned based on the OPF results such that the operating point of the MTDC grid lies on the voltage droop characteristics. Consequently, the optimally-tuned voltage droop controller leads to the optimal operation of the MTDC grid. In case of variation in load or generation of the grid, a new stable operating point is achieved based on the voltage droop characteristics. By execution of a new OPF, the voltage droop characteristics are re-tuned for optimal operation of the MTDC grid after the occurrence of the load or generation variations. The results of simulation on a grid inspired by CIGRE B4 DC grid test system demonstrate efficient grid performance under the proposed control strategy.

  1. Gate voltage and drain current stress instabilities in amorphous In–Ga–Zn–O thin-film transistors with an asymmetric graphene electrode

    Directory of Open Access Journals (Sweden)

    Joonwoo Kim

    2015-09-01

    Full Text Available The gate voltage and drain current stress instabilities in amorphous In–Ga–Zn–O thin-film transistors (a-IGZO TFTs having an asymmetric graphene electrode structure are studied. A large positive shift in the threshold voltage, which is well fitted to a stretched-exponential equation, and an increase in the subthreshold slope are observed when drain current stress is applied. This is due to an increase in temperature caused by power dissipation in the graphene/a-IGZO contact region, in addition to the channel region, which is different from the behavior in a-IGZO TFTs with a conventional transparent electrode.

  2. High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

    International Nuclear Information System (INIS)

    Xia, D X; Xu, J B

    2010-01-01

    Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

  3. Thermal transistor utilizing gas-liquid transition

    KAUST Repository

    Komatsu, Teruhisa S.

    2011-01-25

    We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter. © 2011 American Physical Society.

  4. Current-Induced Transistor Sensorics with Electrogenic Cells

    Directory of Open Access Journals (Sweden)

    Peter Fromherz

    2016-04-01

    Full Text Available The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned.

  5. Negative differential resistance of InGaAs dual channel transistors

    International Nuclear Information System (INIS)

    Sugaya, T; Yamane, T; Hori, S; Komori, K; Yonei, K

    2006-01-01

    We demonstrate a new type of velocity modulation transistor (VMT) with an InGaAs dual channel structure fabricated on an InP (001) substrate. The dual channel structure consists of a high mobility 10 nm In 0.53 Ga 0.47 As quantum well, a 2 nm In 0.52 Al 0.48 As barrier layer, and a low mobility 1 nm In 0.26 Ga 0.74 As quantum well. The VMTs have a negative differential resistance (NDR) effect with a low source-drain voltage of 0.38 V. The NDR characteristics can be clearly seen in the temperature range of 50 to 220 K with a gate voltage of 5 V. The NDR mechanism is thought to be the carrier transfer from the high mobility to the low mobility channels. Three-terminal VMTs are favorable for applications to highfrequency, high-speed, and low-power consumption devices

  6. A transparent electrochromic metal-insulator switching device with three-terminal transistor geometry

    Science.gov (United States)

    Katase, Takayoshi; Onozato, Takaki; Hirono, Misako; Mizuno, Taku; Ohta, Hiromichi

    2016-05-01

    Proton and hydroxyl ion play an essential role for tuning functionality of oxides because their electronic state can be controlled by modifying oxygen off-stoichiometry and/or protonation. Tungsten trioxide (WO3), a well-known electrochromic (EC) material for smart window, is a wide bandgap insulator, whereas it becomes a metallic conductor HxWO3 by protonation. Although one can utilize electrochromism together with metal-insulator (MI) switching for one device, such EC-MI switching cannot be utilized in current EC devices because of their two-terminal structure with parallel-plate configuration. Here we demonstrate a transparent EC-MI switchable device with three-terminal TFT-type structure using amorphous (a-) WO3 channel layer, which was fabricated on glass substrate at room temperature. We used water-infiltrated nano-porous glass, CAN (calcium aluminate with nano-pores), as a liquid-leakage-free solid gate insulator. At virgin state, the device was fully transparent in the visible-light region. For positive gate voltage, the active channel became dark blue, and electrical resistivity of the a-WO3 layer drastically decreased with protonation. For negative gate voltage, deprotonation occurred and the active channel returned to transparent insulator. Good cycleability of the present transparent EC-MI switching device would have potential for the development of advanced smart windows.

  7. Three-terminal heterojunction bipolar transistor solar cell for high-efficiency photovoltaic conversion.

    Science.gov (United States)

    Martí, A; Luque, A

    2015-04-22

    Here we propose, for the first time, a solar cell characterized by a semiconductor transistor structure (n/p/n or p/n/p) where the base-emitter junction is made of a high-bandgap semiconductor and the collector is made of a low-bandgap semiconductor. We calculate its detailed-balance efficiency limit and prove that it is the same one than that of a double-junction solar cell. The practical importance of this result relies on the simplicity of the structure that reduces the number of layers that are required to match the limiting efficiency of dual-junction solar cells without using tunnel junctions. The device naturally emerges as a three-terminal solar cell and can also be used as building block of multijunction solar cells with an increased number of junctions.

  8. Automatic voltage imbalance detector

    Science.gov (United States)

    Bobbett, Ronald E.; McCormick, J. Byron; Kerwin, William J.

    1984-01-01

    A device for indicating and preventing damage to voltage cells such as galvanic cells and fuel cells connected in series by detecting sequential voltages and comparing these voltages to adjacent voltage cells. The device is implemented by using operational amplifiers and switching circuitry is provided by transistors. The device can be utilized in battery powered electric vehicles to prevent galvanic cell damage and also in series connected fuel cells to prevent fuel cell damage.

  9. PowerFactory model for multi-terminal HVDC network with DC voltage droop control

    DEFF Research Database (Denmark)

    Korompili, Asimenia; Wu, Qiuwei

    Nowadays, most of the installed HVDC systems are based on line commutated converters (LCC), since this technology offers a series of advantages, mainly low costs and losses. However, voltage source converters (VSCs) have recently drawn more and more attention, due to their high controllability....... Moreover, recent developments have improved efficiency and power quality. For multi-terminal HVDC grids, the advantages of VSCs become so large, that VSC-HVDC systems are the only viable solution. Nevertheless, no VSC-based multi-terminal HVDC grids exist to date. This is the reason for which many research...

  10. Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

    International Nuclear Information System (INIS)

    Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

    2010-01-01

    Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

  11. Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

    Directory of Open Access Journals (Sweden)

    Qi Liu

    2014-08-01

    Full Text Available A novel high-κ organometallic lanthanide complex, Eu(tta3L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine, is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs. The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μFET of 0.17 cm2 V−1 s−1, threshold voltage (Vth of −0.9 V, on/off current ratio of 5 × 103, and subthreshold slope (SS of 1.0 V dec−1, which is much better than that of devices obtained on conventional 300 nm SiO2 substrate (0.13 cm2 V−1 s−1, −7.3 V and 3.1 V dec−1 for μFET, Vth and SS value when operated at −30 V. These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

  12. Demonstration of high current carbon nanotube enabled vertical organic field effect transistors at industrially relevant voltages

    Science.gov (United States)

    McCarthy, Mitchell

    The display market is presently dominated by the active matrix liquid crystal display (LCD). However, the active matrix organic light emitting diode (AMOLED) display is argued to become the successor to the LCD, and is already beginning its way into the market, mainly in small size displays. But, for AMOLED technology to become comparable in market share to LCD, larger size displays must become available at a competitive price with their LCD counterparts. A major issue preventing low-cost large AMOLED displays is the thin-film transistor (TFT) technology. Unlike the voltage driven LCD, the OLEDs in the AMOLED display are current driven. Because of this, the mature amorphous silicon TFT backplane technology used in the LCD must be upgraded to a material possessing a higher mobility. Polycrystalline silicon and transparent oxide TFT technologies are being considered to fill this need. But these technologies bring with them significant manufacturing complexity and cost concerns. Carbon nanotube enabled vertical organic field effect transistors (CN-VFETs) offer a unique solution to this problem (now known as the AMOLED backplane problem). The CN-VFET allows the use of organic semiconductors to be used for the semiconductor layer. Organics are known for their low-cost large area processing compatibility. Although the mobility of the best organics is only comparable to that of amorphous silicon, the CN-VFET makes up for this by orienting the channel vertically, as opposed to horizontally (like in conventional TFTs). This allows the CN-VFET to achieve sub-micron channel lengths without expensive high resolution patterning. Additionally, because the CN-VFET can be easily converted into a light emitting transistor (called the carbon nanotube enabled vertical organic light emitting transistor---CN-VOLET) by essentially stacking an OLED on top of the CN-VFET, more potential benefits can be realized. These potential benefits include, increased aperture ratio, increased OLED

  13. Symmetric voltage-controlled variable resistance

    Science.gov (United States)

    Vanelli, J. C.

    1978-01-01

    Feedback network makes resistance of field-effect transistor (FET) same for current flowing in either direction. It combines control voltage with source and load voltages to give symmetric current/voltage characteristics. Since circuit produces same magnitude output voltage for current flowing in either direction, it introduces no offset in presense of altering polarity signals. It is therefore ideal for sensor and effector circuits in servocontrol systems.

  14. Vertical organic transistors

    International Nuclear Information System (INIS)

    Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

    2015-01-01

    Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted. (topical review)

  15. Vertical organic transistors.

    Science.gov (United States)

    Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

    2015-11-11

    Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

  16. Remarkable reduction in the threshold voltage of pentacene-based thin film transistors with pentacene/CuPc sandwich configuration

    Directory of Open Access Journals (Sweden)

    Yi Li

    2014-06-01

    Full Text Available This study investigates the remarkable reduction in the threshold voltage (VT of pentacene-based thin film transistors with pentacene/copper phthalocyanine (CuPc sandwich configuration. This reduction is accompanied by increased mobility and lowered sub-threshold slope (S. Sandwich devices coated with a 5 nm layer of CuPc layer are compared with conventional top-contact devices, and results indicate that VT decreased significantly from −20.4 V to −0.2 V, that mobility increased from 0.18 cm2/Vs to 0.51 cm2/Vs, and that S was reduced from 4.1 V/dec to 2.9 V/dec. However, the on/off current ratio remains at 105. This enhanced performance could be attributed to the reduction in charge trap density by the incorporated CuPc layer. Results suggest that this method is simple and effectively generates pentacene-based organic thin film transistors with high mobility and low VT.

  17. Novel Voltage limiting concept for avalance breakdown protection

    NARCIS (Netherlands)

    Ruijs, L.C.H.; Bezooijen, van A.; Mahmoudi, R.; Roermund, van A.H.M.

    2006-01-01

    Destructive over-voltage breakdown of cellular phone power transistors is prevented by using a new voltage-limiting concept. The output voltage is detected by an avalanche-based detector, and limited by decreasing the output power when needed. The voltage detector contains a low voltage bipolar NPN

  18. Improving the performance of X-ray proportional counters by using field transistor preamplifiers

    International Nuclear Information System (INIS)

    Kalinina, N.I.; Mel'ttser, L.V.; Pan'kin, V.V.

    1972-01-01

    The possibility of using low-noise field-effect transistors with the n-channel in preamplifiers for x-ray proportional counters constitutes the object of this article. The operation of the preamplifier assembled according to the scheme of the voltage amplifier and charge-sensitive preamplifier has been studied. The use of the field-effect transistor with the n-channel in preamplifiers for proportional counters allows to improve significantly the energy resolution and operation at reduced voltage and at high loads. Notably good results have been obtained when constructing the circuit of the premplifier with the field-effect transistor on the charge-sensitive principle. The use of home-produced field-effect transistors makes it possible to construct detectors of roentgen radiometric instruments to measure light element content with proportional counters at reduced voltage

  19. Design method for a digitally trimmable MOS transistor structure

    DEFF Research Database (Denmark)

    Ning, Feng; Bruun, Erik

    1996-01-01

    A digitally trimmable MOS transistor is a MOS transistor consisting of a drain, a source, and a main gate as well as several subgates. The transconductance of the transistor is tunabledigitally by means of connecting subgates either to the main gate or to the source terminal. In this paper, a sys...

  20. High-performance vertical organic transistors.

    Science.gov (United States)

    Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

    2013-11-11

    Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. High-voltage terminal test of a test stand for a 1-MV electrostatic accelerator

    Science.gov (United States)

    Park, Sae-Hoon; Kim, Yu-Seok

    2015-10-01

    The Korea Multipurpose Accelerator Complex has been developing a 300-kV test stand for a 1-MV electrostatic accelerator ion source. The ion source and accelerating tube will be installed in a high-pressure vessel. The ion source in the high-pressure vessel is required to have a high reliability. The test stand has been proposed and developed to confirm the stable operating conditions of the ion source. The ion source will be tested at the test stand to verify the long-time operating conditions. The test stand comprises a 300-kV high-voltage terminal, a battery for the ion-source power, a 60-Hz inverter, 200-MHz radio-frequency power supply, a 5-kV extraction power supply, a 300-kV accelerating tube, and a vacuum system. The results of the 300-kV high-voltage terminal tests are presented in this paper.

  2. Solution-processable precursor route for fabricating ultrathin silica film for high performance and low voltage organic transistors

    Institute of Scientific and Technical Information of China (English)

    Shujing Guo; Liqiang Li; Zhongwu Wang; Zeyang Xu; Shuguang Wang; Kunjie Wu; Shufeng Chen; Zongbo Zhang; Caihong Xu; Wenfeng Qiu

    2017-01-01

    Silica is one of the most commonly used materials for dielectric layer in organic thin-film transistors due to its excellent stability,excellent electrical properties,mature preparation process,and good compatibility with organic semiconductors.However,most of conventional preparation methods for silica film are generally performed at high temperature and/or high vacuum.In this paper,we introduce a simple solution spin-coating method to fabricate silica thin film from precursor route,which possesses a low leakage current,high capacitance,and low surface roughness.The silica thin film can be produced in the condition of low temperature and atmospheric environment.To meet various demands,the thickness of film can be adjusted by means of preparation conditions such as the speed of spin-coating and the concentration of solution.The p-type and n-type organic field effect transistors fabricated by using this film as gate electrodes exhibit excellent electrical performance including low voltage and high performance.This method shows great potential for industrialization owing to its characteristic of low consumption and energy saving,time-saving and easy to operate.

  3. AC Voltage Control of DC/DC Converters Based on Modular Multilevel Converters in Multi-Terminal High-Voltage Direct Current Transmission Systems

    Directory of Open Access Journals (Sweden)

    Rui Li

    2016-12-01

    Full Text Available The AC voltage control of a DC/DC converter based on the modular multilevel converter (MMC is considered under normal operation and during a local DC fault. By actively setting the AC voltage according to the two DC voltages of the DC/DC converter, the modulation index can be near unity, and the DC voltage is effectively utilized to output higher AC voltage. This significantly decreases submodule (SM capacitance and conduction losses of the DC/DC converter, yielding reduced capital cost, volume, and higher efficiency. Additionally, the AC voltage is limited in the controllable range of both the MMCs in the DC/DC converter; thus, over-modulation and uncontrolled currents are actively avoided. The AC voltage control of the DC/DC converter during local DC faults, i.e., standby operation, is also proposed, where only the MMC connected on the faulty cable is blocked, while the other MMC remains operational with zero AC voltage output. Thus, the capacitor voltages can be regulated at the rated value and the decrease of the SM capacitor voltages after the blocking of the DC/DC converter is avoided. Moreover, the fault can still be isolated as quickly as the conventional approach, where both MMCs are blocked and the DC/DC converter is not exposed to the risk of overcurrent. The proposed AC voltage control strategy is assessed in a three-terminal high-voltage direct current (HVDC system incorporating a DC/DC converter, and the simulation results confirm its feasibility.

  4. Revisiting the role of trap-assisted-tunneling process on current-voltage characteristics in tunnel field-effect transistors

    Science.gov (United States)

    Omura, Yasuhisa; Mori, Yoshiaki; Sato, Shingo; Mallik, Abhijit

    2018-04-01

    This paper discusses the role of trap-assisted-tunneling process in controlling the ON- and OFF-state current levels and its impacts on the current-voltage characteristics of a tunnel field-effect transistor. Significant impacts of high-density traps in the source region are observed that are discussed in detail. With regard to recent studies on isoelectronic traps, it has been discovered that deep level density must be minimized to suppress the OFF-state leakage current, as is well known, whereas shallow levels can be utilized to control the ON-state current level. A possible mechanism is discussed based on simulation results.

  5. Research Update: Molecular electronics: The single-molecule switch and transistor

    Directory of Open Access Journals (Sweden)

    Kai Sotthewes

    2014-01-01

    Full Text Available In order to design and realize single-molecule devices it is essential to have a good understanding of the properties of an individual molecule. For electronic applications, the most important property of a molecule is its conductance. Here we show how a single octanethiol molecule can be connected to macroscopic leads and how the transport properties of the molecule can be measured. Based on this knowledge we have realized two single-molecule devices: a molecular switch and a molecular transistor. The switch can be opened and closed at will by carefully adjusting the separation between the electrical contacts and the voltage drop across the contacts. This single-molecular switch operates in a broad temperature range from cryogenic temperatures all the way up to room temperature. Via mechanical gating, i.e., compressing or stretching of the octanethiol molecule, by varying the contact's interspace, we are able to systematically adjust the conductance of the electrode-octanethiol-electrode junction. This two-terminal single-molecule transistor is very robust, but the amplification factor is rather limited.

  6. Design of a Negative Differential Resistance Circuit Element Using Single-Electron Transistors

    Science.gov (United States)

    Dixon, D. C.; Heij, C. P.; Hadley, P.; Mooij, J. E.

    1998-03-01

    Electronic circuit elements displaying negative differential resistance (NDR), such as tunnel diodes, have a wide variety of device applications, including oscillators, amplifiers, logic, and memory. We present a two-terminal device using two single-electron transistors (SET's) that demonstrates an NDR profile tuneable with gate voltages. If the capacitive coupling between the SET's is sufficiently larger than the junction capacitances, the device exhibits multiply-peaked NDR, allowing its use as a multi-valued digital element. We will also report recent experimental progress in measurements of such a device, fabricated using standard Al tunnel junctions, but with an additional overlap capacitor to allow the required inter-SET coupling.

  7. Towards low-voltage organic thin film transistors (OTFTs with solution-processed high-k dielectric and interface engineering

    Directory of Open Access Journals (Sweden)

    Yaorong Su

    2015-11-01

    Full Text Available Although impressive progress has been made in improving the performance of organic thin film transistors (OTFTs, the high operation voltage resulting from the low gate capacitance density of traditional SiO2 remains a severe limitation that hinders OTFTs'development in practical applications. In this regard, developing new materials with high-k characteristics at low cost is of great scientific and technological importance in the area of both academia and industry. Here, we introduce a simple solution-based technique to fabricate high-k metal oxide dielectric system (ATO at low-temperature, which can be used effectively to realize low-voltage operation of OTFTs. On the other hand, it is well known that the properties of the dielectric/semiconductor and electrode/semiconductor interfaces are crucial in controlling the electrical properties of OTFTs. By optimizing the above two interfaces with octadecylphosphonic acid (ODPA self-assembled monolayer (SAM and properly modified low-cost Cu, obviously improved device performance is attained in our low-voltage OTFTs. Further more, organic electronic devices on flexible substrates have attracted much attention due to their low-cost, rollability, large-area processability, and so on. Basing on the above results, outstanding electrical performance is achieved in flexible devices. Our studies demonstrate an effective way to realize low-voltage, high-performance OTFTs at low-cost.

  8. Pseudo-diode based on protonic/electronic hybrid oxide transistor

    Science.gov (United States)

    Fu, Yang Ming; Liu, Yang Hui; Zhu, Li Qiang; Xiao, Hui; Song, An Ran

    2018-01-01

    Current rectification behavior has been proved to be essential in modern electronics. Here, a pseudo-diode is proposed based on protonic/electronic hybrid indium-gallium-zinc oxide electric-double-layer (EDL) transistor. The oxide EDL transistors are fabricated by using phosphorous silicate glass (PSG) based proton conducting electrolyte as gate dielectric. A diode operation mode is established on the transistor, originating from field configurable proton fluxes within the PSG electrolyte. Current rectification ratios have been modulated to values ranged between ˜4 and ˜50 000 with gate electrode biased at voltages ranged between -0.7 V and 0.1 V. Interestingly, the proposed pseudo-diode also exhibits field reconfigurable threshold voltages. When the gate is biased at -0.5 V and 0.3 V, threshold voltages are set to ˜-1.3 V and -0.55 V, respectively. The proposed pseudo-diode may find potential applications in brain-inspired platforms and low-power portable systems.

  9. Mobility overestimation due to gated contacts in organic field-effect transistors

    Science.gov (United States)

    Bittle, Emily G.; Basham, James I.; Jackson, Thomas N.; Jurchescu, Oana D.; Gundlach, David J.

    2016-01-01

    Parameters used to describe the electrical properties of organic field-effect transistors, such as mobility and threshold voltage, are commonly extracted from measured current–voltage characteristics and interpreted by using the classical metal oxide–semiconductor field-effect transistor model. However, in recent reports of devices with ultra-high mobility (>40 cm2 V−1 s−1), the device characteristics deviate from this idealized model and show an abrupt turn-on in the drain current when measured as a function of gate voltage. In order to investigate this phenomenon, here we report on single crystal rubrene transistors intentionally fabricated to exhibit an abrupt turn-on. We disentangle the channel properties from the contact resistance by using impedance spectroscopy and show that the current in such devices is governed by a gate bias dependence of the contact resistance. As a result, extracted mobility values from d.c. current–voltage characterization are overestimated by one order of magnitude or more. PMID:26961271

  10. Simultaneous On-State Voltage and Bond-Wire Resistance Monitoring of Silicon Carbide MOSFETs

    DEFF Research Database (Denmark)

    Baker, Nick; Luo, Haoze; Iannuzzo, Francesco

    2017-01-01

    the voltage between the kelvin-source and power-source can be used to specifically monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A Silicon Carbide Metal......-Oxide-Semiconductor-Field-Effect Transistors (MOSFETs), it is shown that there are opposing trends in the evolution of the on-state resistances of both the bond-wires and the MOSFET die. In summary, after 50,000 temperature cycles, the resistance of the bond-wires increased by up to 2 mΩ, while the on-state resistance of the MOSFET dies...... decreased by approximately 1 mΩ. The conventional failure precursor (monitoring a single forward voltage) cannot distinguish between semiconductor die or bond-wire degradation. Therefore, the ability to monitor both these parameters due to the presence of an auxiliary-source terminal can provide more...

  11. Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Qi; Li, Yi; Zhang, Yang; Song, You, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Wang, Xizhang, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Hu, Zheng [Key Laboratory of Mesoscopic Chemistry of MOE, Jiangsu Provincial Lab for Nanotechnology, School of Chemistry and Chemical Engineering, Nanjing University, Nanjing 210093, China. High-Tech Research Institute of Nanjing University (Suzhou), Suzhou 215123 (China); Sun, Huabin; Li, Yun, E-mail: wangxzh@nju.edu.cn, E-mail: yli@nju.edu.cn, E-mail: yousong@nju.edu.cn; Shi, Yi [School of Electronic Science and Engineering and Jiangsu Provincial Key Laboratory of Photonic and Electronic Materials, Nanjing University, Nanjing 210093 (China)

    2014-08-15

    A novel high-κ organometallic lanthanide complex, Eu(tta){sub 3}L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine), is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs). The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μ{sub FET}) of 0.17 cm{sup 2} V{sup −1} s{sup −1}, threshold voltage (V{sub th}) of −0.9 V, on/off current ratio of 5 × 10{sup 3}, and subthreshold slope (SS) of 1.0 V dec{sup −1}, which is much better than that of devices obtained on conventional 300 nm SiO{sub 2} substrate (0.13 cm{sup 2} V{sup −1} s{sup −1}, −7.3 V and 3.1 V dec{sup −1} for μ{sub FET}, V{sub th} and SS value when operated at −30 V). These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

  12. Effect of 1MeV electron beam on transistors and circuits

    International Nuclear Information System (INIS)

    Lee, Tae Hoon

    1998-02-01

    It has been known that semiconductor devices operating in a radiation environment exhibited significant alterations of their electrical responses. Since an electron beam bombardment produces lattice damage in Si and charged defects in SiO 2 , several electrical parameters of transistors exhibit significant changes. Those parameters are the current gain of BJT (Bipolar Junction Transistor) and the threshold voltage of MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The degradation of transistors brings about that of circuits. This paper presents the results of experiments and simulations performed to study the effects of 1MeV electron beam irradiation on selected silicon transistors and circuits. For BJTs, the current gains of npn (2N3904) and pnp (2N3906) linearly decreased as the irradiation dose increased, and from this result, the damage constants, Ks were obtained as 13.65 for 2N3904 and 22.52 for 2N3906 in MGy, indicating a more stable operation in the electron radiation environment for pnp than that for npn. The decrease of current gain was due to that of minority-carrier lifetime in the base region. For MOSFETs (CD4007s), the threshold voltages of NMOS and PMOS shifted to the lower values, which was resulted from the accumulation of charge in SiO 2 . The charges could be categorized into fixed oxide charge and interfacial trap charge. From experimental results, the amounts of the induced charges could be quantitatively estimated. These degradations of transistors brought about the decrease in the voltage gain of CE (Common Emitter) amplifier and the shifts in the inverting voltage of inverter. Additionally, PSpice simulations of these circuits were carried out by modeling of irradiated transistors. The comparison of simulation with experiment showed the relatively good agreement of simulation for the degradation of circuits after irradiation

  13. Homogeneous double-layer amorphous Si-doped indium oxide thin-film transistors for control of turn-on voltage

    International Nuclear Information System (INIS)

    Kizu, Takio; Tsukagoshi, Kazuhito; Aikawa, Shinya; Nabatame, Toshihide; Fujiwara, Akihiko; Ito, Kazuhiro; Takahashi, Makoto

    2016-01-01

    We fabricated homogeneous double-layer amorphous Si-doped indium oxide (ISO) thin-film transistors (TFTs) with an insulating ISO cap layer on top of a semiconducting ISO bottom channel layer. The homogeneously stacked ISO TFT exhibited high mobility (19.6 cm"2/V s) and normally-off characteristics after annealing in air. It exhibited normally-off characteristics because the ISO insulator suppressed oxygen desorption, which suppressed the formation of oxygen vacancies (V_O) in the semiconducting ISO. Furthermore, we investigated the recovery of the double-layer ISO TFT, after a large negative shift in turn-on voltage caused by hydrogen annealing, by treating it with annealing in ozone. The recovery in turn-on voltage indicates that the dense V_O in the semiconducting ISO can be partially filled through the insulator ISO. Controlling molecule penetration in the homogeneous double layer is useful for adjusting the properties of TFTs in advanced oxide electronics.

  14. Transient voltage sharing in series-coupled high voltage switches

    Directory of Open Access Journals (Sweden)

    Editorial Office

    1992-07-01

    Full Text Available For switching voltages in excess of the maximum blocking voltage of a switching element (for example, thyristor, MOSFET or bipolar transistor such elements are often coupled in series - and additional circuitry has to be provided to ensure equal voltage sharing. Between each such series element and system ground there is a certain parasitic capacitance that may draw a significant current during high-speed voltage transients. The "open" switch is modelled as a ladder network. Analy­sis reveals an exponential progression in the distribution of the applied voltage across the elements. Overstressing thus oc­curs in some of the elements at levels of the total voltage that are significantly below the design value. This difficulty is overcome by grading the voltage sharing circuitry, coupled in parallel with each element, in a prescribed manner, as set out here.

  15. Voltage-spike analysis for a free-running parallel inverter

    Science.gov (United States)

    Lee, F. C. Y.; Wilson, T. G.

    1974-01-01

    Unwanted and sometimes damaging high-amplitude voltage spikes occur during each half cycle in many transistor saturable-core inverters at the moment when the core saturates and the transistors switch. The analysis shows that spikes are an intrinsic characteristic of certain types of inverters even with negligible leakage inductance and purely resistive load. The small but unavoidable after-saturation inductance of the saturable-core transformer plays an essential role in creating these undesired thigh-voltage spikes. State-plane analysis provides insight into the complex interaction between core and transistors, and shows the circuit parameters upon which the magnitude of these spikes depends.

  16. Top-gate organic depletion and inversion transistors with doped channel and injection contact

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Xuhai; Kasemann, Daniel, E-mail: daniel.kasemann@iapp.de; Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Strasse 1, 01069 Dresden (Germany)

    2015-03-09

    Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

  17. Determination of bulk and interface density of states in metal oxide semiconductor thin-film transistors by using capacitance-voltage characteristics

    Science.gov (United States)

    Wei, Xixiong; Deng, Wanling; Fang, Jielin; Ma, Xiaoyu; Huang, Junkai

    2017-10-01

    A physical-based straightforward extraction technique for interface and bulk density of states in metal oxide semiconductor thin film transistors (TFTs) is proposed by using the capacitance-voltage (C-V) characteristics. The interface trap density distribution with energy has been extracted from the analysis of capacitance-voltage characteristics. Using the obtained interface state distribution, the bulk trap density has been determined. With this method, for the interface trap density, it is found that deep state density nearing the mid-gap is approximately constant and tail states density increases exponentially with energy; for the bulk trap density, it is a superposition of exponential deep states and exponential tail states. The validity of the extraction is verified by comparisons with the measured current-voltage (I-V) characteristics and the simulation results by the technology computer-aided design (TCAD) model. This extraction method uses non-numerical iteration which is simple, fast and accurate. Therefore, it is very useful for TFT device characterization.

  18. Temporal and voltage stress stability of high performance indium-zinc-oxide thin film transistors

    Science.gov (United States)

    Song, Yang; Katsman, Alexander; Butcher, Amy L.; Paine, David C.; Zaslavsky, Alexander

    2017-10-01

    Thin film transistors (TFTs) based on transparent oxide semiconductors, such as indium zinc oxide (IZO), are of interest due to their improved characteristics compared to traditional a-Si TFTs. Previously, we reported on top-gated IZO TFTs with an in-situ formed HfO2 gate insulator and IZO active channel, showing high performance: on/off ratio of ∼107, threshold voltage VT near zero, extracted low-field mobility μ0 = 95 cm2/V·s, and near-perfect subthreshold slope at 62 mV/decade. Since device stability is essential for technological applications, in this paper we report on the temporal and voltage stress stability of IZO TFTs. Our devices exhibit a small negative VT shift as they age, consistent with an increasing carrier density resulting from an increasing oxygen vacancy concentration in the channel. Under gate bias stress, freshly annealed TFTs show a negative VT shift during negative VG gate bias stress, while aged (>1 week) TFTs show a positive VT shift during negative VG stress. This indicates two competing mechanisms, which we identify as the field-enhanced generation of oxygen vacancies and the field-assisted migration of oxygen vacancies, respectively. A simplified kinetic model of the vacancy concentration evolution in the IZO channel under electrical stress is provided.

  19. Analysing organic transistors based on interface approximation

    International Nuclear Information System (INIS)

    Akiyama, Yuto; Mori, Takehiko

    2014-01-01

    Temperature-dependent characteristics of organic transistors are analysed thoroughly using interface approximation. In contrast to amorphous silicon transistors, it is characteristic of organic transistors that the accumulation layer is concentrated on the first monolayer, and it is appropriate to consider interface charge rather than band bending. On the basis of this model, observed characteristics of hexamethylenetetrathiafulvalene (HMTTF) and dibenzotetrathiafulvalene (DBTTF) transistors with various surface treatments are analysed, and the trap distribution is extracted. In turn, starting from a simple exponential distribution, we can reproduce the temperature-dependent transistor characteristics as well as the gate voltage dependence of the activation energy, so we can investigate various aspects of organic transistors self-consistently under the interface approximation. Small deviation from such an ideal transistor operation is discussed assuming the presence of an energetically discrete trap level, which leads to a hump in the transfer characteristics. The contact resistance is estimated by measuring the transfer characteristics up to the linear region

  20. Comparison of MOS capacitor and transistor postirradiation response

    International Nuclear Information System (INIS)

    McWhorter, P.J.; Fleetwood, D.M.; Pastorek, R.A.; Zimmerman, G.T.

    1989-01-01

    The postirradiation response of MOS capacitors and transistors fabricated on the same chip has been examined as a function of dose and anneal bias. A variety of analysis techniques are used to evaluate the postirradiation response of these structures, including low and high frequency capacitance-voltage techniques, subthreshold current-voltage techniques, and charge pumping. Though there are changes in the postirradiation energy spectrum of ΔD it , no clear evidence of defect transformation is observed on transistors or capacitors under any conditions examined. Postirradiation response at 80 degrees C is found to be similar in the two structures for low levels of damage (100 krad). For both structures, interface-trap densities continue to grow following irradiation under these conditions. In contrast, the postirradiation response of capacitors and transistors can differ qualitatively at higher levels of damage (1 Mrad), with interface-traps increasing postirradiation at 80 degrees C for transistors and annealing for capacitors. These results indicate that capacitor structures may not be suitable for hardness assurance studies that involve elevated temperature irradiations or postirradiation anneals

  1. Copper atomic-scale transistors.

    Science.gov (United States)

    Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

    2017-01-01

    We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

  2. Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters

    Directory of Open Access Journals (Sweden)

    Vytautas Bleizgys

    2011-03-01

    Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian

  3. Universal power transistor base drive control unit

    Science.gov (United States)

    Gale, Allan R.; Gritter, David J.

    1988-01-01

    A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

  4. Transistorized PWM inverter-induction motor drive system

    Science.gov (United States)

    Peak, S. C.; Plunkett, A. B.

    1982-01-01

    This paper describes the development of a transistorized PWM inverter-induction motor traction drive system. A vehicle performance analysis was performed to establish the vehicle tractive effort-speed requirements. These requirements were then converted into a set of inverter and motor specifications. The inverter was a transistorized three-phase bridge using General Electric power Darlington transistors. The description of the design and development of this inverter is the principal object of this paper. The high-speed induction motor is a design which is optimized for use with an inverter power source. The primary feedback control is a torque angle control with voltage and torque outer loop controls. A current-controlled PWM technique is used to control the motor voltage. The drive has a constant torque output with PWM operation to base motor speed and a constant horsepower output with square wave operation to maximum speed. The drive system was dynamometer tested and the results are presented.

  5. Capacitance-voltage analysis of electrical properties for WSe2 field effect transistors with high-k encapsulation layer

    Science.gov (United States)

    Ko, Seung-Pil; Shin, Jong Mok; Jang, Ho Kyun; You, Min Youl; Jin, Jun-Eon; Choi, Miri; Cho, Jiung; Kim, Gyu-Tae

    2018-02-01

    Doping effects in devices based on two-dimensional (2D) materials have been widely studied. However, detailed analysis and the mechanism of the doping effect caused by encapsulation layers has not been sufficiently explored. In this work, we present experimental studies on the n-doping effect in WSe2 field effect transistors (FETs) with a high-k encapsulation layer (Al2O3) grown by atomic layer deposition. In addition, we demonstrate the mechanism and origin of the doping effect. After encapsulation of the Al2O3 layer, the threshold voltage of the WSe2 FET negatively shifted with the increase of the on-current. The capacitance-voltage measurements of the metal insulator semiconductor (MIS) structure proved the presence of the positive fixed charges within the Al2O3 layer. The flat-band voltage of the MIS structure of Au/Al2O3/SiO2/Si was shifted toward the negative direction on account of the positive fixed charges in the Al2O3 layer. Our results clearly revealed that the fixed charges in the Al2O3 encapsulation layer modulated the Fermi energy level via the field effect. Moreover, these results possibly provide fundamental ideas and guidelines to design 2D materials FETs with high-performance and reliability.

  6. Exponential dependence of potential barrier height on biased voltages of inorganic/organic static induction transistor

    International Nuclear Information System (INIS)

    Zhang Yong; Yang Jianhong; Cai Xueyuan; Wang Zaixing

    2010-01-01

    The exponential dependence of the potential barrier height φ c on the biased voltages of the inorganic/organic static induction transistor (SIT/OSIT) through a normalized approach in the low-current regime is presented. It shows a more accurate description than the linear expression of the potential barrier height. Through the verification of the numerical calculated and experimental results, the exponential dependence of φ c on the applied biases can be used to derive the I-V characteristics. For both SIT and OSIT, the calculated results, using the presented relationship, are agreeable with the experimental results. Compared to the previous linear relationship, the exponential description of φ c can contribute effectively to reduce the error between the theoretical and experimental results of the I-V characteristics. (semiconductor devices)

  7. Synaptic transistor with a reversible and analog conductance modulation using a Pt/HfOx/n-IGZO memcapacitor

    Science.gov (United States)

    Yang, Paul; Kim, Hyung Jun; Zheng, Hong; Beom, Geon Won; Park, Jong-Sung; Kang, Chi Jung; Yoon, Tae-Sik

    2017-06-01

    A synaptic transistor emulating the biological synaptic motion is demonstrated using the memcapacitance characteristics in a Pt/HfOx/n-indium-gallium-zinc-oxide (IGZO) memcapacitor. First, the metal-oxide-semiconductor (MOS) capacitor with Pt/HfOx/n-IGZO structure exhibits analog, polarity-dependent, and reversible memcapacitance in capacitance-voltage (C-V), capacitance-time (C-t), and voltage-pulse measurements. When a positive voltage is applied repeatedly to the Pt electrode, the accumulation capacitance increases gradually and sequentially. The depletion capacitance also increases consequently. The capacitances are restored by repeatedly applying a negative voltage, confirming the reversible memcapacitance. The analog and reversible memcapacitance emulates the potentiation and depression synaptic motions. The synaptic thin-film transistor (TFT) with this memcapacitor also shows the synaptic motion with gradually increasing drain current by repeatedly applying the positive gate and drain voltages and reversibly decreasing one by applying the negative voltages, representing synaptic weight modulation. The reversible and analog conductance change in the transistor at both the voltage sweep and pulse operations is obtained through the memcapacitance and threshold voltage shift at the same time. These results demonstrate the synaptic transistor operations with a MOS memcapacitor gate stack consisting of Pt/HfOx/n-IGZO.

  8. Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

    International Nuclear Information System (INIS)

    Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

    1990-01-01

    Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

  9. Worst-Case Bias During Total Dose Irradiation of SOI Transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Colladant, T.; Paillet, P.; Leray, J.-L; Musseau, O.; Schwank, James R.; Shaneyfelt, Marty R.; Pelloie, J.L.; Du Port de Poncharra, J.

    2000-01-01

    The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide

  10. Resilient architecture design for voltage variation

    CERN Document Server

    Reddi, Vijay Janapa

    2013-01-01

    Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe

  11. Subthreshold currents in CMOS transistors made on oxygen-implanted silicon

    International Nuclear Information System (INIS)

    Foster, D.J.

    1983-01-01

    Kinks have been observed in subthreshold current plots of mesa-shaped n-channel transistors made on oxygen-implanted silicon substrates. The kinks represent additional current flow and are due to overlapping fields from the gate electrode causing early corner inversion and to a Qsub(ss) side-wall effect. Subthreshold currents in n-channel transistors are dominated by the two effects which, as a consequence, reduce threshold voltages especially in narrow n-channel transistors. The subthreshold characteristics of p-channel transistors were not affected in the same way. (author)

  12. Low-voltage organic field effect transistors with a 2-tridecyl[1]benzothieno[3,2-b][1]benzothiophene semiconductor layer.

    Science.gov (United States)

    Amin, Atefeh Y; Khassanov, Artoem; Reuter, Knud; Meyer-Friedrichsen, Timo; Halik, Marcus

    2012-10-10

    An asymmetric n-alkyl substitution pattern was realized in 2-tridecyl[1]benzothieno[3,2-b][1]benzothiophene (C(13)-BTBT) in order to improve the charge transport properties in organic thin-film transistors. We obtained large hole mobilities up to 17.2 cm(2)/(V·s) in low-voltage operating devices. The large mobility is related to densely packed layers of the BTBT π-systems at the channel interface dedicated to the substitution motif and confirmed by X-ray reflectivity measurements. The devices exhibit promising stability in continuous operation for several hours in ambient air.

  13. Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

    Science.gov (United States)

    Lee, In-Kyu; Lee, Kwan Hyi; Lee, Seok; Cho, Won-Ju

    2014-12-24

    We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

  14. Fabricating an organic complementary inverter by integrating two transistors on a single substrate

    International Nuclear Information System (INIS)

    Wang Jun; Wei Bin; Zhang Jianhua

    2008-01-01

    Organic complementary inverters were fabricated by integrating two transistors of different electric type on a single substrate. One is a p-type organic heterojunction transistor with a depletion–accumulation mode that acts as a load element. The other is an n-type transistor with an accumulation mode that acts as a drive element. Typical inverter characteristics with a voltage gain of 12 were obtained. Compared with conventional devices, our organic complementary inverter used only one-step patterning of an organic semiconductor, and simultaneously suppressed the leakage current between supply voltage and ground. Therefore, current studies provide a simpler path to fabrication of organic complementary circuits

  15. Voltage regulator for generator

    Energy Technology Data Exchange (ETDEWEB)

    Naoi, K

    1989-01-17

    It is an object of this invention to provide a voltage regulator for a generator charging a battery, wherein even if the ambient temperature at the voltage regulator rises abnormally high, possible thermal breakage of the semiconductor elements constituting the voltage regulator can be avoided. A feature of this invention is that the semiconductor elements can be protected from thermal breakage, even at an abnormal ambient temperature rise at the voltage regulator for the battery charging generator, by controlling a maximum conduction ratio of a power transistor in the voltage regulator in accordance with the temperature at the voltage regulator. This is achieved through a switching device connected in series to the field coil of the generator and adapted to be controlled in accordance with an output voltage of the generator and the ambient temperature at the voltage regulator. 6 figs.

  16. A novel high voltage start up circuit for an integrated switched mode power supply

    Energy Technology Data Exchange (ETDEWEB)

    Hu Hao; Chen Xingbi, E-mail: huhao21@uestc.edu.c [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)

    2010-09-15

    A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions. (semiconductor devices)

  17. Organic semiconductors for organic field-effect transistors

    International Nuclear Information System (INIS)

    Yamashita, Yoshiro

    2009-01-01

    The advantages of organic field-effect transistors (OFETs), such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed. (topical review)

  18. Organic semiconductors for organic field-effect transistors

    Directory of Open Access Journals (Sweden)

    Yoshiro Yamashita

    2009-01-01

    Full Text Available The advantages of organic field-effect transistors (OFETs, such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed.

  19. Combined effects of 60Co dose and high frequency interferences on a discrete bipolar transistor

    International Nuclear Information System (INIS)

    Doridant, A.; Raoult, J.; Jarrix, S.; Blain, A.; Dusseau, L.; Hoffmann, P.; Chatry, N.; Calvel, P.

    2012-01-01

    This paper concerns bipolar transistors subject to a double aggression: dose irradiation and high-frequency interference. The electromagnetic interference is injected in a contactless way in the near-field zone around the device. Parameters of the interference are power and frequency, the latter largely out of band of operation of the transistors. The output voltage of the transistor exhibits changes, due to rectification and to some extent to current crowding. The importance of the base bias set-up for the type of change occurring in voltage is displayed. After irradiation with a 60 Co source, the voltage output will change under electromagnetic interference but sometimes in an opposite way as initially measured. The impact of the irradiation with respect to electromagnetic susceptibility is highlighted from a physical point of view. Finally preliminary results of simulation for susceptibility prediction are given and a discussion is given on the limits of the transistor model used. (authors)

  20. Electrical pulse burnout of transistors in intense ionizing radiation

    International Nuclear Information System (INIS)

    Hartman, E.F.; Evans, D.C.

    1975-01-01

    Tests examining possible synergistic effects of electrical pulses and ionizing radiation on transistors were performed and energy/power thresholds for transistor burnout determined. The effect of ionizing radiation on burnout thresholds was found to be minimal, indicating that electrical pulse testing in the absence of radiation produces burnout-threshold results which are applicable to IEMP studies. The conditions of ionized transistor junctions and radiation induced current surges at semiconductor device terminals are inherent in IEMP studies of electrical circuits

  1. DEVELOPMENT OF CONTROLLED RECTIFIERS BASED ON THE BIPOLAR WITH STATIC INDUCTION TRANSISTORS (BSIT

    Directory of Open Access Journals (Sweden)

    F. I. Bukashev

    2016-01-01

    Full Text Available Aim. The aim of this study is to develop one of the most perspective semiconductor device suitable for creation and improvement of controlled rectifiers, bipolar static induction transistor.Methods. Considered are the structural and schematic circuit controlled rectifier based on bipolar static induction transistor (BSIT, and the criterion of effectiveness controlled rectifiers - equivalent to the voltage drop.Results. Presented are the study results of controlled rectifier layout on BSIT KT698I. It sets the layout operation at an input voltage of 2.0 V at a frequency up to 750 kHz. The efficiency of the studied layouts at moderate current densities as high as 90 % .Offered is optimization of technological route microelectronic controlled rectifier manufacturing including BSIT and integrated bipolar elements of the scheme management.Conclusion. It is proved that the most efficient use of the bipolar static induction transistor occurs at the low voltage controlled rectifiers 350-400 kHz, at frequencies in conjunction with a low-voltage control circuit.It is proved that the increase of the functional characteristics of the converters is connected to the expansion of the input voltage and output current ranges

  2. Monolayer field effect transistor as a probe of electronic defects in organic semiconducting layers at organic/inorganic hetero-junction interface

    International Nuclear Information System (INIS)

    Park, Byoungnam

    2016-01-01

    The origin of a large negative threshold voltage observed in monolayer (ML) field effect transistors (FETs) is explored using in-situ electrical measurements through confining the thickness of an active layer to the accumulation layer thickness. Using ML pentacene FETs combined with gated multiple-terminal devices and atomic force microscopy, the effect of electronic and structural evolution of a ML pentacene film on the threshold voltage in an FET, proportional to the density of deep traps, was probed, revealing that a large negative threshold voltage found in ML FETs results from the pentacene/SiO_2 and pentacene/metal interfaces. More importantly, the origin of the threshold voltage difference between ML and thick FETs is addressed through a model in which the effective charge transport layer is transitioned from the pentacene layer interfacing with the SiO_2 gate dielectric to the upper layers with pentacene thickness increasing evidenced by pentacene coverage dependent threshold voltage measurements. - Highlights: • The origin of a large negative threshold voltage in accumulation layer is revealed. • Electronic localized states at the nanometer scale are separately probed from the bulk. • The second monolayer becomes the effective charge transport layer governing threshold voltage.

  3. A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

    Science.gov (United States)

    She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

    2017-02-01

    A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  4. Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process

    International Nuclear Information System (INIS)

    Yu Jun-Ting; Chen Shu-Ming; Chen Jian-Jun; Huang Peng-Cheng; Song Rui-Qiang

    2016-01-01

    Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor (FinFET) technology. However, the studies of charge sharing induced single-event transient (SET) pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design (3DTCAD) mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing (RBB), the circuit with forward body-biasing (FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications. (paper)

  5. Study on ionizing radiation effects of bipolar transistor with BPSG films

    International Nuclear Information System (INIS)

    Lu Man; Zhang Xiaoling; Xie Xuesong; Sun Jiangchao; Wang Pengpeng; Lu Changzhi; Zhang Yanxiu

    2013-01-01

    Background: Because of the damage induced by ionizing radiation, bipolar transistors in integrated voltage regulator could induce the current gain degradation and increase leakage current. This will bring serious problems to electronic system. Purpose: In order to ensure the reliability of the device work in the radiation environments, the device irradiation reinforcement technology is used. Methods: The characteristics of 60 Co γ irradiation and annealing at different temperatures in bipolar transistors and voltage regulators (JW117) with different passive films for SiO 2 +BPSG+SiO 2 and SiO 2 +SiN have been investigated. Results: The devices with BPSG film enhanced radiation tolerance significantly. Because BPSG films have better absorption for Na + in SiO 2 layer, the surface recombination rate of base region in a bipolar transistor and the excess base current have been reduced. It may be the main reason for BJT with BPSG film having a good radiation hardness. And annealing experiments at different temperatures after irradiation ensure the reliability of the devices with BPSG films. Conclusions: A method of improving the ionizing irradiation hardness of bipolar transistors is proposed. As well as the linear integrated circuits which containing bipolar transistors, an experimental basis for the anti-ionizing radiation effects of bipolar transistors is provided. (authors)

  6. A High Voltage Swing 1.9 GHz PA in Standard CMOS

    NARCIS (Netherlands)

    Aartsen, W.A.J.; Annema, Anne J.; Nauta, Bram

    2002-01-01

    A circuit technique for RF power amplifiers that reliably handle voltage peaks well above the nominal supply voltage is presented. To achieve this high-voltage tolerance the circuit implements switched-cascode transistors that yield reliable operation for voltages up to 7V at RF frequencies in a

  7. Optimization design on breakdown voltage of AlGaN/GaN high-electron mobility transistor

    Science.gov (United States)

    Yang, Liu; Changchun, Chai; Chunlei, Shi; Qingyang, Fan; Yuqian, Liu

    2016-12-01

    Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2 × 1016 to 5 × 1019 cm-3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices. Project supported by the National Basic Research Program of China (No. 2014CB339900) and the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology, China Academy of Engineering Physics (No. 2015-0214.XY.K).

  8. Through thick and thin: tuning the threshold voltage in organic field-effect transistors.

    Science.gov (United States)

    Martínez Hardigree, Josué F; Katz, Howard E

    2014-04-15

    Organic semiconductors (OSCs) constitute a class of organic materials containing densely packed, overlapping conjugated molecular moieties that enable charge carrier transport. Their unique optical, electrical, and magnetic properties have been investigated for use in next-generation electronic devices, from roll-up displays and radiofrequency identification (RFID) to biological sensors. The organic field-effect transistor (OFET) is the key active element for many of these applications, but the high values, poor definition, and long-term instability of the threshold voltage (V(T)) in OFETs remain barriers to realization of their full potential because the power and control circuitry necessary to compensate for overvoltages and drifting set points decrease OFET practicality. The drifting phenomenon has been widely observed and generally termed "bias stress." Research on the mechanisms responsible for this poor V(T) control has revealed a strong dependence on the physical order and chemical makeup of the interfaces between OSCs and adjacent materials in the OFET architecture. In this Account, we review the state of the art for tuning OFET performance via chemical designs and physical processes that manipulate V(T). This parameter gets to the heart of OFET operation, as it determines the voltage regimes where OFETs are either ON or OFF, the basis for the logical function of the devices. One obvious way to decrease the magnitude and variability of V(T) is to work with thinner and higher permittivity gate dielectrics. From the perspective of interfacial engineering, we evaluate various methods that we and others have developed, from electrostatic poling of gate dielectrics to molecular design of substituted alkyl chains. Corona charging of dielectric surfaces, a method for charging the surface of an insulating material using a constant high-voltage field, is a brute force means of shifting the effective gate voltage applied to a gate dielectric. A gentler and more

  9. Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers.

    Science.gov (United States)

    Dell' Anna, Francesco; Dong, Tao; Li, Ping; Wen, Yumei; Azadmehr, Mehdi; Casu, Mario; Berg, Yngvar

    2018-04-17

    This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.

  10. Improvement in Brightness Uniformity by Compensating for the Threshold Voltages of Both the Driving Thin-Film Transistor and the Organic Light-Emitting Diode for Active-Matrix Organic Light-Emitting Diode Displays

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2014-01-01

    Full Text Available This paper proposes a novel pixel circuit design and driving method for active-matrix organic light-emitting diode (AM-OLED displays that use low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs as driving element. The automatic integrated circuit modeling simulation program with integrated circuit emphasis (AIM-SPICE simulator was used to verify that the proposed pixel circuit, which comprises five transistors and one capacitor, can supply uniform output current. The voltage programming method of the proposed pixel circuit comprises three periods: reset, compensation with data input, and emission periods. The simulated results reflected excellent performance. For instance, when ΔVTH=±0.33 V, the average error rate of the OLED current variation was low (<0.8%, and when ΔVTH_OLED=+0.33 V, the error rate of the OLED current variation was 4.7%. Moreover, when the I×R (current × resistance drop voltage of a power line was 0.3 V, the error rate of the OLED current variation was 5.8%. The simulated results indicated that the proposed pixel circuit exhibits high immunity to the threshold voltage deviation of both the driving poly-Si TFTs and OLEDs, and simultaneously compensates for the I×R drop voltage of a power line.

  11. Metal nanoparticle film-based room temperature Coulomb transistor.

    Science.gov (United States)

    Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

    2017-07-01

    Single-electron transistors would represent an approach to developing less power-consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations.

  12. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    Energy Technology Data Exchange (ETDEWEB)

    Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

    2016-07-18

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  13. Transistor analogs of emergent iono-neuronal dynamics.

    Science.gov (United States)

    Rachmuth, Guy; Poon, Chi-Sang

    2008-06-01

    Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

  14. Effects of controlling the interface trap densities in InGaZnO thin-film transistors on their threshold voltage shifts

    Energy Technology Data Exchange (ETDEWEB)

    Jeong, S-W.; Lee, J-T.; Roh, Y. [Sungkyunkwan University, Suwon (Korea, Republic of)

    2014-12-15

    In this paper, the threshold voltage stability characteristics of indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFT) are discussed. The IGZO TFTs were found to induce a parallel threshold voltage (V{sub th}) shift with changing field effect mobility (μ{sub FE}) or a sub-threshold gate voltage swing (SS) due to various thermal annealing conditions. The IGZO TFT that was post-annealed in an O{sub 2} ambient was found to be more stable for use in oxide-based TFT devices and to have better performance characteristics, such as the on/off current ratio (I{sub on/off} ), SS, and V{sub th}, than other TFTs did. The mechanism for improving the V{sub th} stability in the post-annealed IGZO TFT is a decrease in the number of trap sites for the electrons and the weak oxygen bonding in the IGZO thin films. The device's performance could be significantly affected by adjusting the annealing conditions. This mechanism is closely related to that of modulation annealing, where the number of localized trapped carriers and defect centers at the interface or in the channel layer are reduced.

  15. Ultra-Low Voltage Class AB Switched Current Memory Cell

    DEFF Research Database (Denmark)

    Igor, Mucha

    1996-01-01

    This paper presents the theoretical basis for the design of class AB switched current memory cells employing floating-gate MOS transistors, suitable for ultra-low-voltage applications. To support the theoretical assumptions circuits based on these cells were designed using a CMOS process with thr......This paper presents the theoretical basis for the design of class AB switched current memory cells employing floating-gate MOS transistors, suitable for ultra-low-voltage applications. To support the theoretical assumptions circuits based on these cells were designed using a CMOS process...... with threshold voltages of 0.9V. Both hand calculations and PSPICE simulations showed that the cells designed allowed a maximum signal range better than +/-13 micoamp, with a supply voltage down to 1V and a quiescent bias current of 1 microamp, resulting in a very high current efficiency and effective power...

  16. Memristive device based on a depletion-type SONOS field effect transistor

    Science.gov (United States)

    Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

    2017-06-01

    State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

  17. Doped organic transistors operating in the inversion and depletion regime

    Science.gov (United States)

    Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

    2013-01-01

    The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

  18. High-voltage, high-current, solid-state closing switch

    Science.gov (United States)

    Focia, Ronald Jeffrey

    2017-08-22

    A high-voltage, high-current, solid-state closing switch uses a field-effect transistor (e.g., a MOSFET) to trigger a high-voltage stack of thyristors. The switch can have a high hold-off voltage, high current carrying capacity, and high time-rate-of-change of current, di/dt. The fast closing switch can be used in pulsed power applications.

  19. Design and implementation of a 3-A source and sink linear regulator for bus terminators

    International Nuclear Information System (INIS)

    Li Yanming; Wen Changbao; Wen Limin; Mao Xiangyu

    2012-01-01

    According to the requirements of the bus terminal regulator, a linear regulator with 3-A source-sink current ability is presented. The use of the NMOS pass transistor and load current feedback technique enhances the system current ability and response speed. The method of adaptive zero compensation realizes loop stability over the whole load range for either source or sink loop. Furthermore, the transconductance matching technique reduces the shoot-through current through the output stage to less than 3 μA. The regulator has been fabricated with a 0.6-μm 30 V BCD process successfully, and the area size is about 1 mm 2 . With a 20 μF output capacitor, the maximum transient output-voltage variation is within 3.5% of the output voltage with load step changes of ±2 A/1 μs. At the load range of ±3 A, the variation of output voltage is less than ±15 mV.

  20. Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current

    OpenAIRE

    Mheen, B.; Song, Y.J.; Theuwissen, J.P.

    2008-01-01

    This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result, using a commercial pixel in a 0.18 ?m CMOS process, the voltage drop due to dark current of the pinned photodiode (PPD) is reduced by 6.1 dB and the well capacity is enhanced by 4.4 dB, which is attri...

  1. Metal nanoparticle film–based room temperature Coulomb transistor

    Science.gov (United States)

    Willing, Svenja; Lehmann, Hauke; Volkmann, Mirjam; Klinke, Christian

    2017-01-01

    Single-electron transistors would represent an approach to developing less power–consuming microelectronic devices if room temperature operation and industry-compatible fabrication were possible. We present a concept based on stripes of small, self-assembled, colloidal, metal nanoparticles on a back-gate device architecture, which leads to well-defined and well-controllable transistor characteristics. This Coulomb transistor has three main advantages. By using the scalable Langmuir-Blodgett method, we combine high-quality chemically synthesized metal nanoparticles with standard lithography techniques. The resulting transistors show on/off ratios above 90%, reliable and sinusoidal Coulomb oscillations, and room temperature operation. Furthermore, this concept allows for versatile tuning of the device properties such as Coulomb energy gap and threshold voltage, as well as period, position, and strength of the oscillations. PMID:28740864

  2. Fundamentals of RF and microwave transistor amplifiers

    CERN Document Server

    Bahl, Inder J

    2009-01-01

    A Comprehensive and Up-to-Date Treatment of RF and Microwave Transistor Amplifiers This book provides state-of-the-art coverage of RF and microwave transistor amplifiers, including low-noise, narrowband, broadband, linear, high-power, high-efficiency, and high-voltage. Topics covered include modeling, analysis, design, packaging, and thermal and fabrication considerations. Through a unique integration of theory and practice, readers will learn to solve amplifier-related design problems ranging from matching networks to biasing and stability. More than 240 problems are included to help read

  3. Fully transparent thin-film transistor devices based on SnO2 nanowires.

    Science.gov (United States)

    Dattoli, Eric N; Wan, Qing; Guo, Wei; Chen, Yanbin; Pan, Xiaoqing; Lu, Wei

    2007-08-01

    We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.

  4. High-Current Gain Two-Dimensional MoS 2 -Base Hot-Electron Transistors

    KAUST Repository

    Torres, Carlos M.

    2015-12-09

    The vertical transport of nonequilibrium charge carriers through semiconductor heterostructures has led to milestones in electronics with the development of the hot-electron transistor. Recently, significant advances have been made with atomically sharp heterostructures implementing various two-dimensional materials. Although graphene-base hot-electron transistors show great promise for electronic switching at high frequencies, they are limited by their low current gain. Here we show that, by choosing MoS2 and HfO2 for the filter barrier interface and using a noncrystalline semiconductor such as ITO for the collector, we can achieve an unprecedentedly high-current gain (α ∼ 0.95) in our hot-electron transistors operating at room temperature. Furthermore, the current gain can be tuned over 2 orders of magnitude with the collector-base voltage albeit this feature currently presents a drawback in the transistor performance metrics such as poor output resistance and poor intrinsic voltage gain. We anticipate our transistors will pave the way toward the realization of novel flexible 2D material-based high-density, low-energy, and high-frequency hot-carrier electronic applications. © 2015 American Chemical Society.

  5. High-Current Gain Two-Dimensional MoS 2 -Base Hot-Electron Transistors

    KAUST Repository

    Torres, Carlos M.; Lan, Yann Wen; Zeng, Caifu; Chen, Jyun Hong; Kou, Xufeng; Navabi, Aryan; Tang, Jianshi; Montazeri, Mohammad; Adleman, James R.; Lerner, Mitchell B.; Zhong, Yuan Liang; Li, Lain-Jong; Chen, Chii Dong; Wang, Kang L.

    2015-01-01

    The vertical transport of nonequilibrium charge carriers through semiconductor heterostructures has led to milestones in electronics with the development of the hot-electron transistor. Recently, significant advances have been made with atomically sharp heterostructures implementing various two-dimensional materials. Although graphene-base hot-electron transistors show great promise for electronic switching at high frequencies, they are limited by their low current gain. Here we show that, by choosing MoS2 and HfO2 for the filter barrier interface and using a noncrystalline semiconductor such as ITO for the collector, we can achieve an unprecedentedly high-current gain (α ∼ 0.95) in our hot-electron transistors operating at room temperature. Furthermore, the current gain can be tuned over 2 orders of magnitude with the collector-base voltage albeit this feature currently presents a drawback in the transistor performance metrics such as poor output resistance and poor intrinsic voltage gain. We anticipate our transistors will pave the way toward the realization of novel flexible 2D material-based high-density, low-energy, and high-frequency hot-carrier electronic applications. © 2015 American Chemical Society.

  6. Flexible Graphene Transistor Architecture for Optical Sensor Technology

    Science.gov (United States)

    Ordonez, Richard Christopher

    The unique electrical and optoelectronic properties of graphene allow tunable conductivity and broadband electromagnetic absorption that spans the ultraviolet and infrared regimes. However, in the current state-of-art graphene sensor architectures, junction resistance and doping concentration are predominant factors that affect signal strength and sensitivity. Unfortunately, graphene produces high contact resistances with standard electrode materials ( few kilo-ohms), therefore, signal is weak and large carrier concentrations are required to probe sensitivity. Moreover, the atomic thickness of graphene enables the potential for flexible electronics, but there has not been a successful graphene sensor architecture that demonstrates stable operation on flexible substrates and with minimal fabrication cost. In this study, the author explores a novel 3-terminal transistor architecture that integrates twodimensional graphene, liquid metal, and electrolytic gate dielectrics (LM-GFETs: Liquid Metal and Graphene Field-Effect Transistors ). The goal is to deliver a sensitive, flexible, and lightweight transistor architecture that will improve sensor technology and maneuverability. The reported high thermal conductivity of graphene provides potential for room-temperature thermal management without the need of thermal-electric and gas cooling systems that are standard in sensor platforms. Liquid metals provide a unique opportunity for conformal electrodes that maximize surface area contact, therefore, enable flexibility, lower contact resistance, and reduce damage to the graphene materials involved. Lastly, electrolytic gate dielectrics provide conformability and high capacitances needed for high on/off rations and electrostatic gating. Results demonstrated that with minimal fabrication steps the proposed flexible graphene transistor architecture demonstrated ambipolar current-voltage transfer characteristics that are comparable to the current state-of-the-art. An additional

  7. Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers

    Directory of Open Access Journals (Sweden)

    Francesco Dell’ Anna

    2018-04-01

    Full Text Available This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.

  8. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  9. Band-to-band tunneling field effect transistor for low power logic and memory applications: Design, fabrication and characterization

    Science.gov (United States)

    Mookerjea, Saurabh A.

    Over the past decade the microprocessor clock frequency has hit a plateau. The main reason for this has been the inability to follow constant electric field scaling, which requires the transistor supply voltage to be scaled down as the transistor dimensions are reduced. Scaling the supply voltage down reduces the dynamic power quadratically but increases the static leakage power exponentially due to non-scalability of threshold voltage of the transistor, which is required to maintain the same ON state performance. This limitation in supply voltage scaling is directly related to MOSFET's (Metal Oxide Semiconductor Field Effect Transistor) sub-threshold slope (SS) limitation of 60 mV/dec at room temperature. Thus novel device design/materials are required that would allow the transistor to switch with sub-threshold slopes steeper than 60 mV/dec at room temperature, thus facilitating supply voltage scaling. Recently, a new class of devices known as super-steep slope (SSswitching behavior of TFET is studied through mixed-mode numerical simulations. The significance of correct benchmarking methodology to estimate the effective drive current and capacitance in TFET is highlighted and compared with MOSFET. This is followed by the fabrication details of homo-junction TFET. Analysis of the electrical characteristics of homo-junction TFET gives key insight into its device operation and identifies the critical factors that impact its performance. In order to boost the ON current, the design and fabrication of hetero-junction TFET is also presented.

  10. Physisorption of functionalized gold nanoparticles on AlGaN/GaN high electron mobility transistors for sensing applications.

    Science.gov (United States)

    Makowski, M S; Kim, S; Gaillard, M; Janes, D; Manfra, M J; Bryan, I; Sitar, Z; Arellano, C; Xie, J; Collazo, R; Ivanisevic, A

    2013-02-18

    AlGaN/GaN high electron mobility transistors (HEMTs) were used to measure electrical characteristics of physisorbed gold nanoparticles (Au NPs) functionalized with alkanethiols with a terminal methyl, amine, or carboxyl functional group. Additional alkanethiol was physisorbed onto the NP treated devices to distinguish between the effects of the Au NPs and alkanethiols on HEMT operation. Scanning Kelvin probe microscopy and electrical measurements were used to characterize the treatment effects. The HEMTs were operated near threshold voltage due to the greatest sensitivity in this region. The Au NP/HEMT system electrically detected functional group differences on adsorbed NPs which is pertinent to biosensor applications.

  11. Total dose induced latch in short channel NMOS/SOI transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

    1998-01-01

    A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

  12. Monolayer field effect transistor as a probe of electronic defects in organic semiconducting layers at organic/inorganic hetero-junction interface

    Energy Technology Data Exchange (ETDEWEB)

    Park, Byoungnam, E-mail: metalpbn@hongik.ac.kr

    2016-01-01

    The origin of a large negative threshold voltage observed in monolayer (ML) field effect transistors (FETs) is explored using in-situ electrical measurements through confining the thickness of an active layer to the accumulation layer thickness. Using ML pentacene FETs combined with gated multiple-terminal devices and atomic force microscopy, the effect of electronic and structural evolution of a ML pentacene film on the threshold voltage in an FET, proportional to the density of deep traps, was probed, revealing that a large negative threshold voltage found in ML FETs results from the pentacene/SiO{sub 2} and pentacene/metal interfaces. More importantly, the origin of the threshold voltage difference between ML and thick FETs is addressed through a model in which the effective charge transport layer is transitioned from the pentacene layer interfacing with the SiO{sub 2} gate dielectric to the upper layers with pentacene thickness increasing evidenced by pentacene coverage dependent threshold voltage measurements. - Highlights: • The origin of a large negative threshold voltage in accumulation layer is revealed. • Electronic localized states at the nanometer scale are separately probed from the bulk. • The second monolayer becomes the effective charge transport layer governing threshold voltage.

  13. EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

    Science.gov (United States)

    Demming, Anna

    2012-09-01

    Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor

  14. Guidelines on the Switch Transistors Sizing Using the Symbolic Description for the Cross-Coupled Charge Pump

    Directory of Open Access Journals (Sweden)

    J. Marek

    2017-09-01

    Full Text Available This paper presents a symbolic description of the design process of the switch transistors for the cross- coupled charge pump applications. Discrete-time analog circuits are usually designed by the numerical algorithms in the professional simulator software which can be an extremely time-consuming process in contrast to described analytical procedure. The significant part of the pumping losses is caused by the reverse current through the switch transistors due to continuous-time voltage change on the main capacitors. Design process is based on the analytical expression of the time response characteristics of the pump stage as an analog system with using BSIM model equations. The main benefit of the article is the analytical transistors sizing formula, so that the maximum voltage gain is achieved. The diode transistor is dimensioned for the pump requirements, as the maximal pump output ripple voltage, current, etc. The characteristics of the proposed circuit has been verified by simulation in ELDO Spice. Results are valid for N-stage charge pump and also applicable for other model equations as PSP, EKV.

  15. Voltage Stabilizer Based on SPWM technique Using Microcontroller

    OpenAIRE

    K. N. Tarchanidis; J. N. Lygouras; P. Botsaris

    2013-01-01

    This paper presents an application of the well known SPWM technique on a voltage stabilizer, using a microcontroller. The stabilizer is AC/DC/AC type. So, the system rectifies the input AC voltage to a suitable DC level and the intelligent control of an embedded microcontroller regulates the pulse width of the output voltage in order to produce through a filter a perfect sinusoidal AC voltage. The control program on the microcontroller has the ability to change the FET transistor ...

  16. Improvement in interfacial characteristics of low-voltage carbon nanotube thin-film transistors with solution-processed boron nitride thin films

    Energy Technology Data Exchange (ETDEWEB)

    Jeon, Jun-Young; Ha, Tae-Jun, E-mail: taejunha0604@gmail.com

    2017-08-15

    Highlights: • We demonstrate the potential of solution-processed boron nitride (BN) thin films for nanoelectronics. • Improved interfacial characteristics reduced the leakage current by three orders of magnitude. • The BN encapsulation improves all the device key metrics of low-voltage SWCNT-TFTs. • Such improvements were achieved by reduced interaction of interfacial localized states. - Abstract: In this article, we demonstrate the potential of solution-processed boron nitride (BN) thin films for high performance single-walled carbon nanotube thin-film transistors (SWCNT-TFTs) with low-voltage operation. The use of BN thin films between solution-processed high-k dielectric layers improved the interfacial characteristics of metal-insulator-metal devices, thereby reducing the current density by three orders of magnitude. We also investigated the origin of improved device performance in SWCNT-TFTs by employing solution-processed BN thin films as an encapsulation layer. The BN encapsulation layer improves the electrical characteristics of SWCNT-TFTs, which includes the device key metrics of linear field-effect mobility, sub-threshold swing, and threshold voltage as well as the long-term stability against the aging effect in air. Such improvements can be achieved by reduced interaction of interfacial localized states with charge carriers. We believe that this work can open up a promising route to demonstrate the potential of solution-processed BN thin films on nanoelectronics.

  17. Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current

    NARCIS (Netherlands)

    Mheen, B.; Song, Y.J.; Theuwissen, J.P.

    2008-01-01

    This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result,

  18. The measurement of vacuum at high voltage terminal of the FOTIA facility at BARC

    International Nuclear Information System (INIS)

    Kansara, M.J.; Sapna, P.; Subrahmanyam, N.B.V.; Bhatt, J.P.; Gupta, S.K.; Singh, P.

    2003-01-01

    Full text: In FOTIA, the ion beams accelerated by the low energy tube are injected into the high-energy accelerating tube using the 180 deg folding magnet. In order to have maximum transmission through the magnet chamber the vacuum in this section should be in the range of 10 -8 Torr. The chamber is very narrow (14 mm x 24 mm) and offers low conductance to the vacuum system. For maintaining the required UHV inside this chamber and associated beam lines inside the high voltage terminal at 6 MV, a sputter ion pump (120 litres/sec) is used. However, the control of the ion pump and measurement of the vacuum in the chamber has to be done from the control consol located at ground potential. This has been accomplished through a fibre optic data telemetry system, which offers electrical isolation of 6 MV. This fibre optic system is integrated to the main control system of the FOTIA. For controlling and monitoring the ion pump DOUT and ADC modules of the CAMAC system are used to provide interfacing signals to the fibre optic system. For the measurement of the vacuum, the gauge output provided by the ion pump is converted to a suitable light signal (1 kHz to 10 kHz) and is transmitted to the fibre optic link box (located at ground). At ground level this light signal is converted back to a voltage signal and transmitted to ADC module of the CAMAC system. This voltage signal is calibrated against the vacuum measured in the terminal, which is available in the control room via computer connected to the CAMAC system. In this paper, details of the above system will be presented

  19. Three-terminal ferroelectric synapse device with concurrent learning function for artificial neural networks

    International Nuclear Information System (INIS)

    Nishitani, Y.; Kaneko, Y.; Ueda, M.; Fujii, E.; Morie, T.

    2012-01-01

    Spike-timing-dependent synaptic plasticity (STDP) is demonstrated in a synapse device based on a ferroelectric-gate field-effect transistor (FeFET). STDP is a key of the learning functions observed in human brains, where the synaptic weight changes only depending on the spike timing of the pre- and post-neurons. The FeFET is composed of the stacked oxide materials with ZnO/Pr(Zr,Ti)O 3 (PZT)/SrRuO 3 . In the FeFET, the channel conductance can be altered depending on the density of electrons induced by the polarization of PZT film, which can be controlled by applying the gate voltage in a non-volatile manner. Applying a pulse gate voltage enables the multi-valued modulation of the conductance, which is expected to be caused by a change in PZT polarization. This variation depends on the height and the duration of the pulse gate voltage. Utilizing these characteristics, symmetric and asymmetric STDP learning functions are successfully implemented in the FeFET-based synapse device by applying the non-linear pulse gate voltage generated from a set of two pulses in a sampling circuit, in which the two pulses correspond to the spikes from the pre- and post-neurons. The three-terminal structure of the synapse device enables the concurrent learning, in which the weight update can be performed without canceling signal transmission among neurons, while the neural networks using the previously reported two-terminal synapse devices need to stop signal transmission for learning.

  20. Transistor-based filter for inhibiting load noise from entering a power supply

    Science.gov (United States)

    Taubman, Matthew S

    2013-07-02

    A transistor-based filter for inhibiting load noise from entering a power supply is disclosed. The filter includes a first transistor having an emitter coupled to a power supply, a collector coupled to a load, and a base. The filter also includes a first capacitor coupled between the base of the first transistor and a ground terminal. The filter further includes an impedance coupled between the base and a node between the collector and the load, or a second transistor and second capacitor. The impedance can be a resistor or an inductor.

  1. High reliability EPI-base radiation hardened power transistor

    International Nuclear Information System (INIS)

    Clark, L.E.; Saltich, J.L.

    1978-01-01

    A high-voltage power transistor is described which is able to withstand fluences as high as 3 x 10 14 neutrons per square centimeter and still be able to operate satisfactorily. The collector may be made essentially half as thick and twice as heavily doped as normally and its base is made in two regions which together are essentially four times as thick as the normal power transistor base region. The base region has a heavily doped upper region and a lower region intermediate the upper heavily doped region and the collector. The doping in the intermediate region is as close to intrinsic as possible, in any event less than about 3 x 10 15 impurities per cubic centimeter. The second base region has small width in comparison to the first base region, the ratio of the first to the second being at least about 5 to 1. The base region having the upper heavily doped region and the intermediate or lower low doped region contributes to the higher breakdown voltage which the transistor is able to withstand. The high doping of the collector region essentially lowers that portion of the breakdown voltage achieved by the collector region. Accordingly, it is necessary to transfer certain of this breakdown capability to the base region and this is achieved by using the upper region of heavily doped and an intermediate or lower region of low doping

  2. A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under positive gate bias stress

    Energy Technology Data Exchange (ETDEWEB)

    Niang, K. M.; Flewitt, A. J., E-mail: ajf@eng.cam.ac.uk [Electrical Engineering Division, Cambridge University, J J Thomson Avenue, Cambridge CB3 0FA (United Kingdom); Barquinha, P. M. C.; Martins, R. F. P. [i3N/CENIMAT, Department of Materials Science, Faculty of Science and Technology, Universidade NOVA de Lisboa and CEMOP/UNINOVA, Campus de Caparica, 2829-516 Caparica (Portugal); Cobb, B. [Holst Centre/TNO, High Tech Campus 31, 5656AE Eindhoven (Netherlands); Powell, M. J. [252, Valley Drive, Kendal LA9 7SL (United Kingdom)

    2016-02-29

    Thin film transistors (TFTs) employing an amorphous indium gallium zinc oxide (a-IGZO) channel layer exhibit a positive shift in the threshold voltage under the application of positive gate bias stress (PBS). The time and temperature dependence of the threshold voltage shift was measured and analysed using the thermalization energy concept. The peak energy barrier to defect conversion is extracted to be 0.75 eV and the attempt-to-escape frequency is extracted to be 10{sup 7} s{sup −1}. These values are in remarkable agreement with measurements in a-IGZO TFTs under negative gate bias illumination stress (NBIS) reported recently (Flewitt and Powell, J. Appl. Phys. 115, 134501 (2014)). This suggests that the same physical process is responsible for both PBS and NBIS, and supports the oxygen vacancy defect migration model that the authors have previously proposed.

  3. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    Energy Technology Data Exchange (ETDEWEB)

    Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

    2014-08-11

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  4. Vertical architecture for enhancement mode power transistors based on GaN nanowires

    Science.gov (United States)

    Yu, F.; Rümmler, D.; Hartmann, J.; Caccamo, L.; Schimpke, T.; Strassburg, M.; Gad, A. E.; Bakin, A.; Wehmann, H.-H.; Witzigmann, B.; Wasisto, H. S.; Waag, A.

    2016-05-01

    The demonstration of vertical GaN wrap-around gated field-effect transistors using GaN nanowires is reported. The nanowires with smooth a-plane sidewalls have hexagonal geometry made by top-down etching. A 7-nanowire transistor exhibits enhancement mode operation with threshold voltage of 1.2 V, on/off current ratio as high as 108, and subthreshold slope as small as 68 mV/dec. Although there is space charge limited current behavior at small source-drain voltages (Vds), the drain current (Id) and transconductance (gm) reach up to 314 mA/mm and 125 mS/mm, respectively, when normalized with hexagonal nanowire circumference. The measured breakdown voltage is around 140 V. This vertical approach provides a way to next-generation GaN-based power devices.

  5. Total dose behavior of partially depleted SOI dynamic threshold voltage MOS (DTMOS) for very low supply voltage applications (0.6 - 1 V)

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Musseau, O.; Leray, J.L.; Faynot, O.; Raynaud, C.; Pelloie, J.L.

    1999-01-01

    In this paper, we presented two DTMOS architectures processed with a partially depleted SOI technology. The first architecture, DTMOS without limiting transistor, is dedicated to ultra-low voltage applications, at 0.6 V. For 1V applications, the second architecture, DTMOS with limiting transistor, needs an additional transistor to limit the body-source diode current. The total dose irradiation of both DTMOS architectures induces no change of the drain current, but an increase of the body-source diode current. Total dose induced trapped charge in the buried oxide increases the body potential of the DTMOS transistor. It induces an increase of the current flow at the back interface of the silicon film. Irradiation of complex circuits using DTMOS transistors would lead to a degradation of the stand-by consumption. (authors)

  6. A 10-kW series resonant converter design, transistor characterization, and base-drive optimization

    Science.gov (United States)

    Robson, R. R.; Hancock, D. J.

    1982-01-01

    The development, components, and performance of a transistor-based 10 kW series resonant converter for use in resonant circuits in space applications is described. The transistors serve to switch on the converter current, which has a half-sinusoid waveform when the transistor is in saturation. The goal of the program was to handle an input-output voltage range of 230-270 Vdc, an output voltage range of 200-500 Vdc, and a current limit range of 0-20 A. Testing procedures for the D60T and D7ST transistors are outlined and base drive waveforms are presented. The total device dissipation was minimized and found to be independent of the regenerative feedback ratio at lower current levels. Dissipation was set at within 10% and rise times were found to be acceptable. The finished unit displayed a 91% efficiency at full power levels of 500 V and 20 A and 93.7% at 500 V and 10 A.

  7. Solvothermal synthesis of gallium-indium-zinc-oxide nanoparticles for electrolyte-gated transistors.

    Science.gov (United States)

    Santos, Lídia; Nunes, Daniela; Calmeiro, Tomás; Branquinho, Rita; Salgueiro, Daniela; Barquinha, Pedro; Pereira, Luís; Martins, Rodrigo; Fortunato, Elvira

    2015-01-14

    Solution-processed field-effect transistors are strategic building blocks when considering low-cost sustainable flexible electronics. Nevertheless, some challenges (e.g., processing temperature, reliability, reproducibility in large areas, and cost effectiveness) are requirements that must be surpassed in order to achieve high-performance transistors. The present work reports electrolyte-gated transistors using as channel layer gallium-indium-zinc-oxide nanoparticles produced by solvothermal synthesis combined with a solid-state electrolyte based on aqueous dispersions of vinyl acetate stabilized with cellulose derivatives, acrylic acid ester in styrene and lithium perchlorate. The devices fabricated using this approach display a ION/IOFF up to 1 × 10(6), threshold voltage (VTh) of 0.3-1.9 V, and mobility up to 1 cm(2)/(V s), as a function of gallium-indium-zinc-oxide ink formulation and two different annealing temperatures. These results validates the usage of electrolyte-gated transistors as a viable and promising alternative for nanoparticle based semiconductor devices as the electrolyte improves the interface and promotes a more efficient step coverage of the channel layer, reducing the operating voltage when compared with conventional dielectrics gating. Moreover, it is shown that by controlling the applied gate potential, the operation mechanism of the electrolyte-gated transistors can be modified from electric double layer to electrochemical doping.

  8. Significance of the double-layer capacitor effect in polar rubbery dielectrics and exceptionally stable low-voltage high transconductance organic transistors.

    Science.gov (United States)

    Wang, Chao; Lee, Wen-Ya; Kong, Desheng; Pfattner, Raphael; Schweicher, Guillaume; Nakajima, Reina; Lu, Chien; Mei, Jianguo; Lee, Tae Hoon; Wu, Hung-Chin; Lopez, Jeffery; Diao, Ying; Gu, Xiaodan; Himmelberger, Scott; Niu, Weijun; Matthews, James R; He, Mingqian; Salleo, Alberto; Nishi, Yoshio; Bao, Zhenan

    2015-12-14

    Both high gain and transconductance at low operating voltages are essential for practical applications of organic field-effect transistors (OFETs). Here, we describe the significance of the double-layer capacitance effect in polar rubbery dielectrics, even when present in a very low ion concentration and conductivity. We observed that this effect can greatly enhance the OFET transconductance when driven at low voltages. Specifically, when the polar elastomer poly(vinylidene fluoride-co-hexafluoropropylene) (e-PVDF-HFP) was used as the dielectric layer, despite a thickness of several micrometers, we obtained a transconductance per channel width 30 times higher than that measured for the same organic semiconductors fabricated on a semicrystalline PVDF-HFP with a similar thickness. After a series of detailed experimental investigations, we attribute the above observation to the double-layer capacitance effect, even though the ionic conductivity is as low as 10(-10) S/cm. Different from previously reported OFETs with double-layer capacitance effects, our devices showed unprecedented high bias-stress stability in air and even in water.

  9. Significance of the double-layer capacitor effect in polar rubbery dielectrics and exceptionally stable low-voltage high transconductance organic transistors

    Science.gov (United States)

    Wang, Chao; Lee, Wen-Ya; Kong, Desheng; Pfattner, Raphael; Schweicher, Guillaume; Nakajima, Reina; Lu, Chien; Mei, Jianguo; Lee, Tae Hoon; Wu, Hung-Chin; Lopez, Jeffery; Diao, Ying; Gu, Xiaodan; Himmelberger, Scott; Niu, Weijun; Matthews, James R.; He, Mingqian; Salleo, Alberto; Nishi, Yoshio; Bao, Zhenan

    2015-01-01

    Both high gain and transconductance at low operating voltages are essential for practical applications of organic field-effect transistors (OFETs). Here, we describe the significance of the double-layer capacitance effect in polar rubbery dielectrics, even when present in a very low ion concentration and conductivity. We observed that this effect can greatly enhance the OFET transconductance when driven at low voltages. Specifically, when the polar elastomer poly(vinylidene fluoride-co-hexafluoropropylene) (e-PVDF-HFP) was used as the dielectric layer, despite a thickness of several micrometers, we obtained a transconductance per channel width 30 times higher than that measured for the same organic semiconductors fabricated on a semicrystalline PVDF-HFP with a similar thickness. After a series of detailed experimental investigations, we attribute the above observation to the double-layer capacitance effect, even though the ionic conductivity is as low as 10–10 S/cm. Different from previously reported OFETs with double-layer capacitance effects, our devices showed unprecedented high bias-stress stability in air and even in water. PMID:26658331

  10. Dosimetric properties of MOS transistors

    International Nuclear Information System (INIS)

    Frank, H.; Petr, I.

    1977-01-01

    The structure of MOS transistors is described and their characteristics given. The experiments performed and data in the literature show the following dosimetric properties of MOS transistors: while for low gamma doses the transistor response to exposure is linear, it shows saturation for higher doses (exceeding 10 3 Gy in tissue). The response is independent of the energy of radiation and of the dose rate (within 10 -2 to 10 5 Gy/s). The spontaneous reduction with time of the spatial charge captured by the oxide layer (fading) is small and acceptable from the point of view of dosimetry. Curves are given of isochronous annealing of the transistors following irradiation with 137 Cs and 18 MeV electrons for different voltages during irradiation. The curves show that in MOS transistors irradiated with high-energy electrons the effect of annealing is less than in transistors irradiated with 137 Cs. In view of the requirement of using higher temperatures (approx. 400 degC) for the complete ''erasing'' of the captured charge, unsealed systems must be used for dosimetric purposes. The effect was also studied of neutron radiation, proton radiation and electron radiation on the MOS transistor structure. For MOS transistor irradiation with 14 MeV neutrons from a neutron generator the response was 4% of that for gamma radiation at the same dose equivalent. The effect of proton radiation was studied as related to the changes in MOS transistor structure during space flights. The response curve shapes are similar to those of gamma radiation curves. The effect of electron radiation on the MOS structure was studied by many authors. The experiments show that for each thickness of the SiO 2 layer an electron energy exists at which the size of the charge captured in SiO 2 is the greatest. All data show that MOS transistors are promising for radiation dosimetry. The main advantage of MOS transistors as gamma dosemeters is the ease and speed of evaluation, low sensitivity to neutron

  11. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

    KAUST Repository

    Smith, Casey; Qaisi, Ramy M.; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

    2013-01-01

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

  12. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

    KAUST Repository

    Smith, Casey

    2013-07-23

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

  13. Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

    Science.gov (United States)

    Xu, Meili; Xiang, Lanyi; Xu, Ting; Wang, Wei; Xie, Wenfa; Zhou, Dayu

    2017-10-01

    Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V-1 s-1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

  14. Reevaluating the worst-case radiation response of MOS transistors

    Science.gov (United States)

    Fleetwood, D. M.

    Predicting worst-case response of a semiconductor device to ionizing radiation is a formidable challenge. As processes change and MOS gate insulators become thinner in advanced VLSI and VHSIC technologies, failure mechanisms must be constantly re-examined. Results are presented of a recent study in which more than 100 MOS transistors were monitored for up to 300 days after Co-60 exposure. Based on these results, a reevaluation of worst-case n-channel transistor response (most positive threshold voltage shift) in low-dose-rate and postirradiation environments is required in many cases. It is shown for Sandia hardened n-channel transistors with a 32 nm gate oxide, that switching from zero-volt bias, held during the entire radiation period, to positive bias during anneal clearly leads to a more positive threshold voltage shift (and thus the slowest circuit response) after Co-60 exposure than the standard case of maintaining positive bias during irradiation and anneal. It is concluded that irradiating these kinds of transistors with zero-volt bias, and annealing with positive bias, leads to worst-case postirradiation response. For commercial devices (with few interface states at doses of interest), on the other hand, device response only improves postirradiation, and worst-case response (in terms of device leakage) is for devices irradiated under positive bias and annealed with zero-volts bias.

  15. An AMOLED AC-Biased Pixel Design Compensating the Threshold Voltage and I-R Drop

    Directory of Open Access Journals (Sweden)

    Ching-Lin Fan

    2011-01-01

    Full Text Available We propose a novel pixel design and an AC bias driving method for active-matrix organic light-emitting diode (AM-OLED displays using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs. The proposed threshold voltage and I-R drop compensation circuit, which comprised three transistors and one capacitor, have been verified to supply uniform output current by simulation work using the Automatic Integrated Circuit Modeling Simulation Program with Integrated Circuit Emphasis (AIM-SPICE simulator. The simulated results demonstrate excellent properties such as low error rate of OLED anode voltage variation (<0.7% and low voltage drop of VDD power line. The proposed pixel circuit effectively enables threshold-voltage-deviation correction of driving TFT and compensates for the voltage drop of VDD power line using AC bias on OLED cathode.

  16. Sensitivity of the threshold voltage of organic thin-film transistors to light and water

    Energy Technology Data Exchange (ETDEWEB)

    Feng, Cong; Marinov, Ognian; Deen, M. Jamal; Selvaganapathy, Ponnambalam Ravi [McMaster University, 1280 Main Street West, Hamilton, Ontario L8S 4K1 (Canada); Wu, Yiliang [Xerox Research Centre, 2660 Speakman Dr., Mississauga, Ontario L5K 2L1 (Canada)

    2015-05-14

    Analyses of extensive experiments with organic thin-film transistors (OTFTs) indicate that the threshold voltage V{sub T} of an OTFT has a temporal differential sensitivity. In particular, V{sub T} changes initially by changing the light illumination intensity or making/removing a contact of water with the organic semiconductor. Keeping the conditions stationary, then the initial shift of V{sub T} diminishes, since the time dependence of V{sub T} gradually recovers the OTFT to the state before applying the change in the environmental conditions. While still causing a differential and time-variant shift of V{sub T}, the deionized water does not have a dramatic impact on OTFTs that use the polymer DKPP-βT (diketopyrrolopyrrole β-unsubstituted quaterthiophene) as the active semiconductor material. Observations for the impact of water are made from experiments with an OTFT that has a microfluidic channel on the top the electrical channel, with the water in the microfluidic channel in direct contact with the electrical channel of the OTFT. This arrangement of electrical and microfluidic channels is a novel structure of the microfluidic OTFT, suitable for sensing applications of liquid analytes by means of organic electronics.

  17. Effects of irradiation on device characteristics of transistor structures based on AlGaN/GaN

    International Nuclear Information System (INIS)

    Kargin, N.I.; Gromov, D.V.; Kuznetsov, A.L.; Grekhov, M.M.

    2014-01-01

    A technologic scheme was developed, and transistor structures, based on hetero-structures AlGaN/GaN, were made. Current-voltage characteristics of the transistor structures and current-amplification and power-amplification cutoff frequencies have been presented in the paper [ru

  18. High voltage short plus generation based on avalanche circuit

    International Nuclear Information System (INIS)

    Hu Yuanfeng; Yu Xiaoqi

    2006-01-01

    Simulate the avalanche circuit in series with PSPICE module, design the high voltage short plus generation circuit by avalanche transistor in series for the sweep deflection circuit of streak camera. The output voltage ranges 1.2 KV into 50 ohm load. The rise time of the circuit is less than 3 ns. (authors)

  19. In-situ study of pn-heterojunction interface states in organic thin film transistors

    International Nuclear Information System (INIS)

    Ye, Rongbin; Ohta, Koji; Baba, Mamoru

    2014-01-01

    In this paper, we have investigated the density of pn-heterojunction interface states by evaluating the threshold voltage shift with in-situ measurement of electrical characteristics of a sandwich fluorinated copper phthalocyanine/pentacene thin film transistor with various thicknesses of pentacene thin films. A threshold voltage (V T ) undergoes a significant shift from + 20.6 to + 0.53 V with increasing the thickness of pentacene. When the thickness of pentacene is more than a critical thickness of 15 nm, V T undergoes hardly any shift. On the other hand, the value of mobility is lightly decreased with increasing the thickness of pentacene due to the effect of the bulk current. Thus the V T shift is attributed to the increase of drain current in the sandwich device. In order to explain the V T shift, a model was assumed in the linear region of thin film transistor operation and the V T shift agrees with a tan −1 function of film thickness. The total charge density (Q 0 ) of 1.53 × 10 −7 C/cm 2 (9.56 × 10 11 electrons or holes/cm 2 ) was obtained. Furthermore, the V T shift and Q 0 could be adjusted by selecting a p-type semiconductor. - Highlights: • A threshold voltage was in-situ measured in an organic sandwich thin film transistor. • Density of pn-heterojunction interface states by evaluating the threshold voltage shift. • The threshold voltage shift attributes to the increase of drain current. • In order to explain the threshold voltage shift, a model was assumed

  20. High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

    Science.gov (United States)

    Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

    2016-02-01

    The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

  1. Effects on focused ion beam irradiation on MOS transistors

    International Nuclear Information System (INIS)

    Campbell, A.N.; Peterson, K.A.; Fleetwood, D.M.; Soden, J.M.

    1997-01-01

    The effects of irradiation from a focused ion beam (FIB) system on MOS transistors are reported systematically for the first time. Three MOS transistor technologies, with 0.5, 1, and 3 μm minimum feature sizes and with gate oxide thicknesses ranging from 11 to 50 nm, were analyzed. Significant shifts in transistor parameters (such as threshold voltage, transconductance, and mobility) were observed following irradiation with a 30 keV Ga + focused ion beam with ion doses varying by over 5 orders of magnitude. The apparent damage mechanism (which involved the creation of interface traps, oxide trapped charge, or both) and extent of damage were different for each of the three technologies investigated

  2. An analytical model for the vertical electric field distribution and optimization of high voltage REBULF LDMOS

    International Nuclear Information System (INIS)

    Hu Xia-Rong; Lü Rui

    2014-01-01

    In this paper, an analytical model for the vertical electric field distribution and optimization of a high voltage-reduced bulk field (REBULF) lateral double-diffused metal—oxide-semiconductor (LDMOS) transistor is presented. The dependences of the breakdown voltage on the buried n-layer depth, thickness, and doping concentration are discussed in detail. The REBULF criterion and the optimal vertical electric field distribution condition are derived on the basis of the optimization of the electric field distribution. The breakdown voltage of the REBULF LDMOS transistor is always higher than that of a single reduced surface field (RESURF) LDMOS transistor, and both analytical and numerical results show that it is better to make a thick n-layer buried deep into the p-substrate. (interdisciplinary physics and related areas of science and technology)

  3. High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

    Science.gov (United States)

    Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

    2017-08-01

    In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

  4. Low-voltage bendable pentacene thin-film transistor with stainless steel substrate and polystyrene-coated hafnium silicate dielectric.

    Science.gov (United States)

    Yun, Dong-Jin; Lee, Seunghyup; Yong, Kijung; Rhee, Shi-Woo

    2012-04-01

    The hafnium silicate and aluminum oxide high-k dielectrics were deposited on stainless steel substrate using atomic layer deposition process and octadecyltrichlorosilane (OTS) and polystyrene (PS) were treated improve crystallinity of pentacene grown on them. Besides, the effects of the pentacene deposition condition on the morphologies, crystallinities and electrical properties of pentacene were characterized. Therefore, the surface treatment condition on dielectric and pentacene deposition conditions were optimized. The pentacene grown on polystyrene coated high-k dielectric at low deposition rate and temperature (0.2-0.3 Å/s and R.T.) showed the largest grain size (0.8-1.0 μm) and highest crystallinity among pentacenes deposited various deposition conditions, and the pentacene TFT with polystyrene coated high-k dielectric showed excellent device-performance. To decrease threshold voltage of pentacene TFT, the polystyrene-thickness on high-k dielectric was controlled using different concentration of polystyrene solution. As the polystyrene-thickness on hafnium silicate decreases, the dielectric constant of polystyrene/hafnium silicate increases, while the crystallinity of pentacene grown on polystyrene/hafnium silicate did not change. Using low-thickness polystyrene coated hafnium silicate dielectric, the high-performance and low voltage operating (pentacene thin film transistor (μ: ~2 cm(2)/(V s), on/off ratio, >1 × 10(4)) and complementary inverter (DC gains, ~20) could be fabricated.

  5. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO2 nanogranular films

    International Nuclear Information System (INIS)

    Zhu, Li Qiang; Chao, Jin Yu; Xiao, Hui

    2014-01-01

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO 2 nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics

  6. 1/f noise in pentacene and poly-thienylene vinylene thin film transistors

    NARCIS (Netherlands)

    Vandamme, L.K.J.; Feyaerts, R.; Trefan, G.; Detcheverry, C.

    2002-01-01

    We investigate low frequency conductivity noise in the drain-source channel of organic material field-effect transistors by measuring the spectra of current fluctuations for several values of the gate voltage Vgs and drain voltage Vds and find that it is 1/f. The samples are biased in the ohmic

  7. Charge-density depinning at metal contacts of graphene field-effect transistors

    OpenAIRE

    Nouchi, Ryo; Tanigaki, Katsumi

    2010-01-01

    An anomalous distortion is often observed in the transfer characteristics of graphene field-effect transistors. We fabricate graphene transistors with ferromagnetic metal electrodes, which reproducibly display distorted transfer characteristics, and show that the distortion is caused by metal-graphene contacts with no charge-density pinning effect. The pinning effect, where the gate voltage cannot tune the charge density of graphene at the metal electrodes, has been experimentally observed; h...

  8. Micromolar-Affinity Benzodiazepine Receptors Regulate Voltage-Sensitive Calcium Channels in Nerve Terminal Preparations

    Science.gov (United States)

    Taft, William C.; Delorenzo, Robert J.

    1984-05-01

    Benzodiazepines in micromolar concentrations significantly inhibit depolarization-sensitive Ca2+ uptake in intact nerve-terminal preparations. Benzodiazepine inhibition of Ca2+ uptake is concentration dependent and stereospecific. Micromolar-affinity benzodiazepine receptors have been identified and characterized in brain membrane and shown to be distinct from nanomolar-affinity benzodiazepine receptors. Evidence is presented that micromolar, and not nanomolar, benzodiazepine binding sites mediate benzodiazepine inhibition of Ca2+ uptake. Irreversible binding to micromolar benzodiazepine binding sites also irreversibly blocked depolarization-dependent Ca2+ uptake in synaptosomes, indicating that these compounds may represent a useful marker for identifying the molecular components of Ca2+ channels in brain. Characterization of benzodiazepine inhibition of Ca2+ uptake demonstrates that these drugs function as Ca2+ channel antagonists, because benzodiazepines effectively blocked voltage-sensitive Ca2+ uptake inhibited by Mn2+, Co2+, verapamil, nitrendipine, and nimodipine. These results indicate that micromolar benzodiazepine binding sites regulate voltage-sensitive Ca2+ channels in brain membrane and suggest that some of the neuronal stabilizing effects of micromolar benzodiazepine receptors may be mediated by the regulation of Ca2+ conductance.

  9. Nanogap Electrodes towards Solid State Single-Molecule Transistors.

    Science.gov (United States)

    Cui, Ajuan; Dong, Huanli; Hu, Wenping

    2015-12-01

    With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  10. Field-effect transistors as electrically controllable nonlinear rectifiers for the characterization of terahertz pulses

    Science.gov (United States)

    Lisauskas, Alvydas; Ikamas, Kestutis; Massabeau, Sylvain; Bauer, Maris; ČibiraitÄ--, DovilÄ--; Matukas, Jonas; Mangeney, Juliette; Mittendorff, Martin; Winnerl, Stephan; Krozer, Viktor; Roskos, Hartmut G.

    2018-05-01

    We propose to exploit rectification in field-effect transistors as an electrically controllable higher-order nonlinear phenomenon for the convenient monitoring of the temporal characteristics of THz pulses, for example, by autocorrelation measurements. This option arises because of the existence of a gate-bias-controlled super-linear response at sub-threshold operation conditions when the devices are subjected to THz radiation. We present measurements for different antenna-coupled transistor-based THz detectors (TeraFETs) employing (i) AlGaN/GaN high-electron-mobility and (ii) silicon CMOS field-effect transistors and show that the super-linear behavior in the sub-threshold bias regime is a universal phenomenon to be expected if the amplitude of the high-frequency voltage oscillations exceeds the thermal voltage. The effect is also employed as a tool for the direct determination of the speed of the intrinsic TeraFET response which allows us to avoid limitations set by the read-out circuitry. In particular, we show that the build-up time of the intrinsic rectification signal of a patch-antenna-coupled CMOS detector changes from 20 ps in the deep sub-threshold voltage regime to below 12 ps in the vicinity of the threshold voltage.

  11. Bias stress effect and recovery in organic field effect transistors : proton migration mechanism

    NARCIS (Netherlands)

    Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.; Bao, Z.; McCulloch, I.

    2010-01-01

    Organic field-effect transistors exhibit operational instabilities when a gate bias is applied. For a constant gate bias the threshold voltage shifts towards the applied gate bias voltage, an effect known as the bias-stress effect. We have performed a detailed experimental and theoretical study of

  12. Effect of initial material on the electrolytic parameters of field-effect transistors

    International Nuclear Information System (INIS)

    Antonov, A.V.; Sinitsyn, V.N.; Fursov, V.V.

    1978-01-01

    The effect of initial material parameters upon the main electric characteristics of field transistors at room and optimum (170 deg C) temperatures is studied. For that purpose, the values of parasitic resistances rsub(s), specific resistances rho and steepness S of field transistors, depending on temperature and electrical conditions were measured. The output volt-ampere characteristics of the transistors at room and optimum temperatures are given. An analysis of the results obtained permits to conclude that there is an unambiguous relationship between rho and rsub(s). Impact ionization is shown to occur for field transistors with lower rho at lower drain voltage. When manufacturing field transistors designed for operation at low temperatures, one should remember that a minimum rho may restrict maximum possible steepness. When designing field transistors with optimum noise characteristics, one should variate not only such material parameters as mobility and carrier density, but also select optimum geometry

  13. Low dielectric constant-based organic field-effect transistors and metal-insulator-semiconductor capacitors

    Science.gov (United States)

    Ukah, Ndubuisi Benjamin

    This thesis describes a study of PFB and pentacene-based organic field-effect transistors (OFET) and metal-insulator-semiconductor (MIS) capacitors with low dielectric constant (k) poly(methyl methacrylate) (PMMA), poly(4-vinyl phenol) (PVP) and cross-linked PVP (c-PVP) gate dielectrics. A physical method -- matrix assisted pulsed laser evaporation (MAPLE) -- of fabricating all-polymer field-effect transistors and MIS capacitors that circumvents inherent polymer dissolution and solvent-selectivity problems, is demonstrated. Pentacene-based OFETs incorporating PMMA and PVP gate dielectrics usually have high operating voltages related to the thickness of the dielectric layer. Reduced PMMA layer thickness (≤ 70 nm) was obtained by dissolving the PMMA in propylene carbonate (PC). The resulting pentacene-based transistors exhibited very low operating voltage (below -3 V), minimal hysteresis in their transfer characteristics, and decent electrical performance. Also low voltage (within -2 V) operation using thin (≤ 80 nm) low-k and hydrophilic PVP and c-PVP dielectric layers obtained via dissolution in high dipole moment and high-k solvents -- PC and dimethyl sulfoxide (DMSO), is demonstrated to be a robust means of achieving improved electrical characteristics and high operational stability in OFETs incorporating PVP and c-PVP dielectrics.

  14. Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

    Science.gov (United States)

    Liu, Huixuan; Xun, Damao

    2018-04-01

    We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

  15. In-situ study of pn-heterojunction interface states in organic thin film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Ye, Rongbin, E-mail: ye@iwate-u.ac.jp; Ohta, Koji; Baba, Mamoru

    2014-03-03

    In this paper, we have investigated the density of pn-heterojunction interface states by evaluating the threshold voltage shift with in-situ measurement of electrical characteristics of a sandwich fluorinated copper phthalocyanine/pentacene thin film transistor with various thicknesses of pentacene thin films. A threshold voltage (V{sub T}) undergoes a significant shift from + 20.6 to + 0.53 V with increasing the thickness of pentacene. When the thickness of pentacene is more than a critical thickness of 15 nm, V{sub T} undergoes hardly any shift. On the other hand, the value of mobility is lightly decreased with increasing the thickness of pentacene due to the effect of the bulk current. Thus the V{sub T} shift is attributed to the increase of drain current in the sandwich device. In order to explain the V{sub T} shift, a model was assumed in the linear region of thin film transistor operation and the V{sub T} shift agrees with a tan{sup −1} function of film thickness. The total charge density (Q{sub 0}) of 1.53 × 10{sup −7} C/cm{sup 2} (9.56 × 10{sup 11} electrons or holes/cm{sup 2}) was obtained. Furthermore, the V{sub T} shift and Q{sub 0} could be adjusted by selecting a p-type semiconductor. - Highlights: • A threshold voltage was in-situ measured in an organic sandwich thin film transistor. • Density of pn-heterojunction interface states by evaluating the threshold voltage shift. • The threshold voltage shift attributes to the increase of drain current. • In order to explain the threshold voltage shift, a model was assumed.

  16. Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

    Science.gov (United States)

    Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

    2017-12-28

    Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

  17. Lateral protonic/electronic hybrid oxide thin-film transistor gated by SiO{sub 2} nanogranular films

    Energy Technology Data Exchange (ETDEWEB)

    Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Chao, Jin Yu; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China)

    2014-12-15

    Ionic/electronic interaction offers an additional dimension in the recent advancements of condensed materials. Here, lateral gate control of conductivities of indium-zinc-oxide (IZO) films is reported. An electric-double-layer (EDL) transistor configuration was utilized with a phosphorous-doped SiO{sub 2} nanogranular film to provide a strong lateral electric field. Due to the strong lateral protonic/electronic interfacial coupling effect, the IZO EDL transistor could operate at a low-voltage of 1 V. A resistor-loaded inverter is built, showing a high voltage gain of ∼8 at a low supply voltage of 1 V. The lateral ionic/electronic coupling effects are interesting for bioelectronics and portable electronics.

  18. Intrinsic hydrogen-terminated diamond as ion-sensitive field effect transistor

    Czech Academy of Sciences Publication Activity Database

    Rezek, Bohuslav; Shin, D.; Watanabe, H.; Nebel, C.E.

    2007-01-01

    Roč. 122, - (2007), s. 596-599 ISSN 0925-4005 Institutional research plan: CEZ:AV0Z10100521 Keywords : diamond film * surface electronic properties * field effect transistor * pH sensor * semiconductor-electrolyte interface Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 2.934, year: 2007

  19. Avalanche transistor pulser for fast-gated operation of micro-channel plate image-intensifiers

    International Nuclear Information System (INIS)

    Lundy, A.; Parker, J.R.; Lunsford, J.S.; Martin, A.D.

    1977-01-01

    Transistors operated in the avalanche mode are employed to generate a 1000 volt 10 to 30 nsec wide pulse with less than 4 nsec rise and fall times. This pulse is resistively attenuated to approximately equal to 270 volts and drives the image intensifier tube which is a load of approximately equal to 200 pf. To reduce stray inductance and capacitance, transistor chips were assembled on a thick-film hybrid substrate. Circuit parameters, operating conditions, and coupling to the microchannel plate image-intensifier (MCPI 2 ) tube are described. To provide dc operating voltages and control of transient voltages on the MCPI 2 tube a resistance-capacitance network has been developed which (a) places the MCPI 2 output phosphor at ground, (b) provides programmable gains in ''f-stop'' steps, and (c) minimizes voltage transients on the MCPI 2 tube

  20. Low operating voltage InGaZnO thin-film transistors based on Al2O3 high-k dielectrics fabricated using pulsed laser deposition

    International Nuclear Information System (INIS)

    Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K.; Lee, W. J.; Shin, B. C.; Cho, C. R.

    2014-01-01

    Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al 2 O 3 dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al 2 O 3 and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al 2 O 3 gate dielectric exhibits a very low leakage current density of 1.3 x 10 -8 A/cm 2 at 5 V and a high capacitance density of 60.9 nF/cm 2 . The IGZO TFT with a structure of Ni/IGZO/Al 2 O 3 /Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm 2 V -1 s -1 , an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10 7 .

  1. C-terminal modulatory domain controls coupling of voltage-sensing to pore opening in Cav1.3 L-type Ca(2+) channels.

    Science.gov (United States)

    Lieb, Andreas; Ortner, Nadine; Striessnig, Jörg

    2014-04-01

    Activity of voltage-gated Cav1.3 L-type Ca(2+) channels is required for proper hearing as well as sinoatrial node and brain function. This critically depends on their negative activation voltage range, which is further fine-tuned by alternative splicing. Shorter variants miss a C-terminal regulatory domain (CTM), which allows them to activate at even more negative potentials than C-terminally long-splice variants. It is at present unclear whether this is due to an increased voltage sensitivity of the Cav1.3 voltage-sensing domain, or an enhanced coupling of voltage-sensor conformational changes to the subsequent opening of the activation gate. We studied the voltage-dependence of voltage-sensor charge movement (QON-V) and of current activation (ICa-V) of the long (Cav1.3L) and a short Cav1.3 splice variant (Cav1.342A) expressed in tsA-201 cells using whole cell patch-clamp. Charge movement (QON) of Cav1.3L displayed a much steeper voltage-dependence and a more negative half-maximal activation voltage than Cav1.2 and Cav3.1. However, a significantly higher fraction of the total charge had to move for activation of Cav1.3 half-maximal conductance (Cav1.3: 68%; Cav1.2: 52%; Cav3.1: 22%). This indicated a weaker coupling of Cav1.3 voltage-sensor charge movement to pore opening. However, the coupling efficiency was strengthened in the absence of the CTM in Cav1.342A, thereby shifting ICa-V by 7.2 mV to potentials that were more negative without changing QON-V. We independently show that the presence of intracellular organic cations (such as n-methyl-D-glucamine) induces a pronounced negative shift of QON-V and a more negative activation of ICa-V of all three channels. These findings illustrate that the voltage sensors of Cav1.3 channels respond more sensitively to depolarization than those of Cav1.2 or Cav3.1. Weak coupling of voltage sensing to pore opening is enhanced in the absence of the CTM, allowing short Cav1.342A splice variants to activate at lower voltages

  2. Junctionless Cooper pair transistor

    Energy Technology Data Exchange (ETDEWEB)

    Arutyunov, K. Yu., E-mail: konstantin.yu.arutyunov@jyu.fi [National Research University Higher School of Economics , Moscow Institute of Electronics and Mathematics, 101000 Moscow (Russian Federation); P.L. Kapitza Institute for Physical Problems RAS , Moscow 119334 (Russian Federation); Lehtinen, J.S. [VTT Technical Research Centre of Finland Ltd., Centre for Metrology MIKES, P.O. Box 1000, FI-02044 VTT (Finland)

    2017-02-15

    Highlights: • Junctionless Cooper pair box. • Quantum phase slips. • Coulomb blockade and gate modulation of the Coulomb gap. - Abstract: Quantum phase slip (QPS) is the topological singularity of the complex order parameter of a quasi-one-dimensional superconductor: momentary zeroing of the modulus and simultaneous 'slip' of the phase by ±2π. The QPS event(s) are the dynamic equivalent of tunneling through a conventional Josephson junction containing static in space and time weak link(s). Here we demonstrate the operation of a superconducting single electron transistor (Cooper pair transistor) without any tunnel junctions. Instead a pair of thin superconducting titanium wires in QPS regime was used. The current–voltage characteristics demonstrate the clear Coulomb blockade with magnitude of the Coulomb gap modulated by the gate potential. The Coulomb blockade disappears above the critical temperature, and at low temperatures can be suppressed by strong magnetic field.

  3. Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

    Science.gov (United States)

    Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

    2014-05-07

    Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

  4. Voltage-sensing domain mode shift is coupled to the activation gate by the N-terminal tail of hERG channels.

    Science.gov (United States)

    Tan, Peter S; Perry, Matthew D; Ng, Chai Ann; Vandenberg, Jamie I; Hill, Adam P

    2012-09-01

    Human ether-a-go-go-related gene (hERG) potassium channels exhibit unique gating kinetics characterized by unusually slow activation and deactivation. The N terminus of the channel, which contains an amphipathic helix and an unstructured tail, has been shown to be involved in regulation of this slow deactivation. However, the mechanism of how this occurs and the connection between voltage-sensing domain (VSD) return and closing of the gate are unclear. To examine this relationship, we have used voltage-clamp fluorometry to simultaneously measure VSD motion and gate closure in N-terminally truncated constructs. We report that mode shifting of the hERG VSD results in a corresponding shift in the voltage-dependent equilibrium of channel closing and that at negative potentials, coupling of the mode-shifted VSD to the gate defines the rate of channel closure. Deletion of the first 25 aa from the N terminus of hERG does not alter mode shifting of the VSD but uncouples the shift from closure of the cytoplasmic gate. Based on these observations, we propose the N-terminal tail as an adaptor that couples voltage sensor return to gate closure to define slow deactivation gating in hERG channels. Furthermore, because the mode shift occurs on a time scale relevant to the cardiac action potential, we suggest a physiological role for this phenomenon in maximizing current flow through hERG channels during repolarization.

  5. A radio-frequency single-electron transistor based on an InAs/InP heterostructure nanowire

    DEFF Research Database (Denmark)

    Nilsson, Henrik A.; Duty, Tim; Abay, Simon

    2008-01-01

    We demonstrate radio frequency single-electron transistors fabricated from epitaxially grown InAs/InP heterostructure nanowires. Two sets of double-barrier wires with different barrier thicknesses were grown. The wires were suspended 15 nm above a metal gate electrode. Electrical measurements...... on a high-resistance nanowire showed regularly spaced Coulomb oscillations at a gate voltage from −0.5 to at least 1.8 V. The charge sensitivity was measured to 32 µerms Hz−1/2 at 1.5 K. A low-resistance single-electron transistor showed regularly spaced oscillations only in a small gate-voltage region just...

  6. DC power flow control for radial offshore multi-terminal HVDC transmission system by considering steady-state DC voltage operation range

    DEFF Research Database (Denmark)

    Irnawan, Roni; Silva, Filipe Miguel Faria da; Bak, Claus Leth

    2017-01-01

    This paper deals with a radial offshore multi-terminal HVDC (MTDC) transmission system which is formed by interconnection several existing offshore wind farm (OWF) HVDC links with a shore-to-shore (StS) HVDC link. A challenge arises when deciding the steady-state DC voltage operating level...

  7. Characteristics of thin-film transistors based on silicon nitride passivation by excimer laser direct patterning

    International Nuclear Information System (INIS)

    Chen, Chao-Nan; Huang, Jung-Jie

    2013-01-01

    This study explored the removal of silicon nitride using KrF laser ablation technology with a high threshold fluence of 990 mJ/cm 2 . This technology was used for contact hole patterning to fabricate SiN x -passivation-based amorphous-silicon thin films in a transistor device. Compared to the photolithography process, laser direct patterning using KrF laser ablation technology can reduce the number of process steps by at least three. Experimental results showed that the mobility and threshold voltages of thin film transistors patterned using the laser process were 0.16 cm 2 /V-sec and 0.2 V, respectively. The device performance and the test results of gate voltage stress reliability demonstrated that laser direct patterning is a promising alternative to photolithography in the panel manufacturing of thin-film transistors for liquid crystal displays. - Highlights: ► KrF laser ablation technology is used to remove silicon nitride. ► A simple method for direct patterning contact-hole in thin-film-transistor device. ► Laser technology reduced processing by at least three steps

  8. Influence of the semiconductor oxidation potential on the operational stability of organic field-effect transistors

    NARCIS (Netherlands)

    Sharma, A.; Mathijssen, S.G.J.; Bobbert, P.A.; Leeuw, de D.M.

    2011-01-01

    During prolonged application of a gate bias, organic field-effect transistors show a gradual shift of the threshold voltage towards the applied gate bias voltage. The shift follows a stretched-exponential time dependence governed by a relaxation time. Here, we show that a thermodynamic analysis

  9. Gate Tunable Transport in Graphene/MoS2/(Cr/Au Vertical Field-Effect Transistors

    Directory of Open Access Journals (Sweden)

    Ghazanfar Nazir

    2017-12-01

    Full Text Available Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS2/(Cr/Au vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr, the electrical transport in our Gr/MoS2/(Cr/Au vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS2 can be modified by back-gate voltage and the current bias. Vertical resistance (Rvert of a Gr/MoS2/(Cr/Au transistor is compared with planar resistance (Rplanar of a conventional lateral MoS2 field-effect transistor. We have also studied electrical properties for various thicknesses of MoS2 channels in both vertical and lateral transistors. As the thickness of MoS2 increases, Rvert increases, but Rplanar decreases. The increase of Rvert in the thicker MoS2 film is attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

  10. High voltage performance of BARC-TIFR Pelletron Accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Surendran, P.; Ansari, Q.N.; Nair, J.P., E-mail: surendra@tifr.res.in [Nuclear Physics Division, Bhabha Atomic Research Centre, Mumbai (India); and others

    2014-07-01

    The 14 UD Pelletron Accelerator at TIFR, Mumbai is operational since its inception in 1988. It was decided to impart enough time for high voltage conditioning to achieve higher operational voltage. Prior to this, comprehensive works such as replacing all the sputter ion pumps and Titanium sublimation pumps across the accelerator tube with new or refurbished ones and replacement of Alumina balls in the SF{sub 6} drier with fresh balls were carried out. High voltage conditioning of each module was done. Further conditioning of two modules at a time in overlapping mode improved the terminal voltage. As a result of this rigorous conditioning Terminal voltage of 12.6 MV was achieved and beam has been delivered to users at 12 MV terminal. Details of this effort will be presented in this paper. (author)

  11. High voltage performance of BARC-TIFR Pelletron Accelerator

    International Nuclear Information System (INIS)

    Surendran, P.; Ansari, Q.N.; Nair, J.P.

    2014-01-01

    The 14 UD Pelletron Accelerator at TIFR, Mumbai is operational since its inception in 1988. It was decided to impart enough time for high voltage conditioning to achieve higher operational voltage. Prior to this, comprehensive works such as replacing all the sputter ion pumps and Titanium sublimation pumps across the accelerator tube with new or refurbished ones and replacement of Alumina balls in the SF_6 drier with fresh balls were carried out. High voltage conditioning of each module was done. Further conditioning of two modules at a time in overlapping mode improved the terminal voltage. As a result of this rigorous conditioning Terminal voltage of 12.6 MV was achieved and beam has been delivered to users at 12 MV terminal. Details of this effort will be presented in this paper. (author)

  12. Control of the threshold voltage by using the oxygen partial pressure in sputter-deposited InGaZnO4 thin-film transistors

    International Nuclear Information System (INIS)

    Ahn, Jeung Sun; Lee, Kwang Bae

    2012-01-01

    We investigate the controllability of the threshold voltage (V th ) by varying the O 2 partial pressure in sputter-deposited of InGaZnO 4 thin-film transistors (IGZO TFTs). We showed that the V th values could be linearly controlled from a depletion-type of V th ∼ -6 V to an enhancement-type of V th ∼ 2 V, without any abrupt change in μ sat , I on/off , and S, by only changing the O 2 partial pressure in a fixed region of the Ar partial pressure. Such V th controllability is thought to be due to the proper reduction of defect states and, in turn, to the preservation of high-performance TFT behavior.

  13. Gamma radiation effects on hydrogen-terminated nanocrystalline diamond bio-transistors

    Czech Academy of Sciences Publication Activity Database

    Krátká, Marie; Babchenko, Oleg; Ukraintsev, Egor; Vachelová, Jana; Davídková, Marie; Vandrovcová, Marta; Kromka, Alexander; Rezek, Bohuslav

    2016-01-01

    Roč. 63, Mar (2016), 186-191 ISSN 0925-9635 R&D Projects: GA ČR(CZ) GBP108/12/G108 Institutional support: RVO:68378271 ; RVO:61389005 ; RVO:67985823 Keywords : diamond thin films * field effect transistors * proteins * cells * gamma irradiation * atomic force microscope * biosensors Subject RIV: BO - Biophysics Impact factor: 2.561, year: 2016

  14. Scaling properties of ballistic nano-transistors

    Directory of Open Access Journals (Sweden)

    Wulf Ulrich

    2011-01-01

    Full Text Available Abstract Recently, we have suggested a scale-invariant model for a nano-transistor. In agreement with experiments a close-to-linear thresh-old trace was found in the calculated I D - V D-traces separating the regimes of classically allowed transport and tunneling transport. In this conference contribution, the relevant physical quantities in our model and its range of applicability are discussed in more detail. Extending the temperature range of our studies it is shown that a close-to-linear thresh-old trace results at room temperatures as well. In qualitative agreement with the experiments the I D - V G-traces for small drain voltages show thermally activated transport below the threshold gate voltage. In contrast, at large drain voltages the gate-voltage dependence is weaker. As can be expected in our relatively simple model, the theoretical drain current is larger than the experimental one by a little less than a decade.

  15. Tandem Terminal Ion Source

    International Nuclear Information System (INIS)

    Harper, G.C.; Lindner, C.E.; Myers, A.W.; Wechel, T.D. van

    2000-01-01

    OAK-B135 Tandem Terminal Ion Source. The terminal ion source (TIS) was used in several experiments during this reporting period, all for the 7 Be(γ) 8 B experiment. Most of the runs used 1 H + at terminal voltages from 0.3 MV to 1.5 MV. One of the runs used 2 H + at terminal voltage of 1.4 MV. The other run used 4 He + at a terminal voltage of 1.37 MV. The list of experiments run with the TIS to date is given in table 1 below. The tank was opened four times for unscheduled source repairs. On one occasion the tank was opened to replace the einzel lens power supply which had failed. The 10 kV unit was replaced with a 15 kV unit. The second time the tank was opened to repair the extractor supply which was damaged by a tank spark. On the next occasion the tank was opened to replace a source canal which had sputtered away. Finally, the tank was opened to replace the discharge bottle which had been coated with aluminum sputtered from the exit canal

  16. Tandem Terminal Ion Source

    International Nuclear Information System (INIS)

    None

    2000-01-01

    OAK-B135 Tandem Terminal Ion Source. The terminal ion source (TIS) was used in several experiments during this reporting period, all for the(sup 7)Be((gamma))(sup 8)B experiment. Most of the runs used(sup 1)H(sup+) at terminal voltages from 0.3 MV to 1.5 MV. One of the runs used(sup 2)H(sup+) at terminal voltage of 1.4 MV. The other run used(sup 4)He(sup+) at a terminal voltage of 1.37 MV. The list of experiments run with the TIS to date is given in table 1 below. The tank was opened four times for unscheduled source repairs. On one occasion the tank was opened to replace the einzel lens power supply which had failed. The 10 kV unit was replaced with a 15 kV unit. The second time the tank was opened to repair the extractor supply which was damaged by a tank spark. On the next occasion the tank was opened to replace a source canal which had sputtered away. Finally, the tank was opened to replace the discharge bottle which had been coated with aluminum sputtered from the exit canal

  17. Systems and methods for switched-inductor integrated voltage regulators

    Science.gov (United States)

    Shepard, Kenneth L.; Sturcken, Noah Andrew

    2017-12-12

    Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage using the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided.

  18. Interface engineering in high-performance low-voltage organic thin-film transistors based on 2,7-dialkyl-[1]benzothieno[3,2-b][1]benzothiophenes.

    Science.gov (United States)

    Amin, Atefeh Y; Reuter, Knud; Meyer-Friedrichsen, Timo; Halik, Marcus

    2011-12-20

    We investigated two different (2,7-dialkyl-[1]benzothieno[3,2-b][1]benzothiophenes; C(n)-BTBT-C(n), where n = 12 or 13) semiconductors in low-voltage operating thin-film transistors. By choosing functional molecules in nanoscaled hybrid dielectric layers, we were able to tune the surface energy and improve device characteristics, such as leakage current and hysteresis. The dipolar nature of the self-assembled molecules led to a shift in the threshold voltage. All devices exhibited high charge carrier mobilities of 0.6-7.0 cm(2) V(-1) s(-1). The thin-film morphology of BTBT was studied by means of atomic force microscopy (AFM), presented a dependency upon the surface energy of the self-assembled monolayer (SAM) hybrid dielectrics but not upon the device performance. The use of C(13)-BTBT-C(13) on hybrid dielectrics of AlO(x) and a F(15)C(18)-phosphonic acid monolayer led to devices with a hole mobility of 1.9 cm(2) V(-1) s(-1) at 3 V, on/off ratio of 10(5), small device-device variation of mobility, and a threshold voltage of only -0.9 V, thus providing excellent characteristics for further integration. © 2011 American Chemical Society

  19. Magnon transistor for all-magnon data processing.

    Science.gov (United States)

    Chumak, Andrii V; Serga, Alexander A; Hillebrands, Burkard

    2014-08-21

    An attractive direction in next-generation information processing is the development of systems employing particles or quasiparticles other than electrons--ideally with low dissipation--as information carriers. One such candidate is the magnon: the quasiparticle associated with the eigen-excitations of magnetic materials known as spin waves. The realization of single-chip all-magnon information systems demands the development of circuits in which magnon currents can be manipulated by magnons themselves. Using a magnonic crystal--an artificial magnetic material--to enhance nonlinear magnon-magnon interactions, we have succeeded in the realization of magnon-by-magnon control, and the development of a magnon transistor. We present a proof of concept three-terminal device fabricated from an electrically insulating magnetic material. We demonstrate that the density of magnons flowing from the transistor's source to its drain can be decreased three orders of magnitude by the injection of magnons into the transistor's gate.

  20. Reduced Voltage Scaling in Clock Distribution Networks

    Directory of Open Access Journals (Sweden)

    Khader Mohammad

    2009-01-01

    Full Text Available We propose a novel circuit technique to generate a reduced voltage swing (RVS signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV devices and the programmability of the low voltage value.

  1. High current transistor pulse generator

    International Nuclear Information System (INIS)

    Nesterov, V.; Cassel, R.

    1991-05-01

    A solid state pulse generator capable of delivering high current trapezoidally shaped pulses into an inductive load has been developed at SLAC. Energy stored in the capacitor bank of the pulse generator is switched to the load through a pair of Darlington transistors. A combination of diodes and Darlington transistors is used to obtain trapezoidal or triangular shaped current pulses into an inductive load and to recover the remaining energy in the same capacitor bank without reversing capacitor voltage. The transistors work in the switch mode, and the power losses are low. The rack mounted pulse generators presently used at SLAC contain a 660 microfarad storage capacitor bank and can deliver 400 amps at 800 volts into inductive loads up to 3 mH. The pulse generators are used in several different power systems, including pulse to pulse bipolar power supplies and in application with current pulses distributed into different inductive loads. The current amplitude and discharge time are controlled by the central computer system through a specially developed multichannel controller. Several years of operation with the pulse generators have proven their consistent performance and reliability. 8 figs

  2. Radio frequency and linearity performance of transistors using high-purity semiconducting carbon nanotubes.

    Science.gov (United States)

    Wang, Chuan; Badmaev, Alexander; Jooyaie, Alborz; Bao, Mingqiang; Wang, Kang L; Galatsis, Kosmas; Zhou, Chongwu

    2011-05-24

    This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (f(t)) of 5 GHz and with maximum oscillation frequency (f(max)) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.

  3. Fiber Optic Telemetry System for LLL High-Voltage Test Stand

    International Nuclear Information System (INIS)

    Richter, J.P.

    1977-01-01

    This paper describes the Fiber Optic Telemetry System designed to operate in the hostile particle and electromagnetic radiation environment of the High Voltage Test Stand. It discusses system criteria, components, packaging, and performance. In all tests to date, the system exceeds its design goals with very comfortable margins. It is well advanced into the fabrication stages with all crucial components tested and only straightforward TTL (Transistor Transistor Logic) circuitry to be completed

  4. Characterization of a Common-Source Amplifier Using Ferroelectric Transistors

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; MacLeond, Todd C.; Ho, Pat D.

    2010-01-01

    This paper presents empirical data that was collected through experiments using a FeFET in the established common-source amplifier circuit. The unique behavior of the FeFET lends itself to interesting and useful operation in this widely used common-source amplifier. The paper examines the effect of using a ferroelectric transistor for the amplifier. It also examines the effects of varying load resistance, biasing, and input voltages on the output signal and gives several examples of the output of the amplifier for a given input. The difference between a commonsource amplifier using a ferroelectric transistor and that using a MOSFET is addressed.

  5. SnTe field effect transistors and the anomalous electrical response of structural phase transition

    International Nuclear Information System (INIS)

    Li, Haitao; Zhu, Hao; Yuan, Hui; Li, Qiliang; You, Lin; Kopanski, Joseph J.; Richter, Curt A.; Zhao, Erhai

    2014-01-01

    SnTe is a conventional thermoelectric material and has been newly found to be a topological crystalline insulator. In this work, back-gate SnTe field-effect transistors have been fabricated and fully characterized. The devices exhibit n-type transistor behaviors with excellent current-voltage characteristics and large on/off ratio (>10 6 ). The device threshold voltage, conductance, mobility, and subthreshold swing have been studied and compared at different temperatures. It is found that the subthreshold swings as a function of temperature have an apparent response to the SnTe phase transition between cubic and rhombohedral structures at 110 K. The abnormal and rapid increase in subthreshold swing around the phase transition temperature may be due to the soft phonon/structure change which causes the large increase in SnTe dielectric constant. Such an interesting and remarkable electrical response to phase transition at different temperatures makes the small SnTe transistor attractive for various electronic devices.

  6. Air-stable complementary-like circuits based on organic ambipolar transistors

    NARCIS (Netherlands)

    Anthopoulos, Thomas D.; Setayesh, Sepas; Smits, Edsger; Cantatore, Eugenio; Boer ,de Bert; Blom, Paul W. M.; de Leeuw, Dago M.; Cölle, Michael

    2006-01-01

    Air stable complementary-like circuits, such as voltage inverters (see figure) and ring oscillators, are fabricated using ambipolar organic transistors based on a nickel dithiolene derivative. In addition to the complementary-like character of the circuits, the technology is very simple and fully

  7. Subthreshold characteristics of pentacene field-effect transistors influenced by grain boundaries.

    OpenAIRE

    Park, J.; Jeong, Y-S.; Park, K-S.; Do, L-M.; Bae, J-H.; Choi, J.S.; Pearson, C.; Petty, M.C.

    2012-01-01

    Grain boundaries in polycrystalline pentacene films significantly affect the electrical characteristics of pentacene field-effect transistors (FETs). Upon reversal of the gate voltage sweep direction, pentacene FETs exhibited hysteretic behaviours in the subthreshold region, which was more pronounced for the FET having smaller pentacene grains. No shift in the flat-band voltage of the metal-insulator-semiconductor capacitor elucidates that the observed hysteresis was mainly caused by the infl...

  8. Siloxane-Terminated Solubilizing Side Chains: Bringing Conjugated Polymer Backbones Closer and Boosting Hole Mobilities in Thin-Film Transistors

    KAUST Repository

    Mei, Jianguo

    2011-12-21

    We introduce a novel siloxane-terminated solubilizing group and demonstrate its effectiveness as a side chain in an isoindigo-based conjugated polymer. An average hole mobility of 2.00 cm 2 V -1 s -1 (with a maximum mobility of 2.48 cm 2 V -1 s -1), was obtained from solution-processed thin-film transistors, one of the highest mobilities reported to date. In contrast, the reference polymer with a branched alkyl side chain gave an average hole mobility of 0.30 cm 2 V -1 s -1 and a maximum mobility of 0.57 cm 2 V -1 s -1. This is largely explained by the polymer packing: our new polymer exhibited a π-π stacking distance of 3.58 Å, while the reference polymer showed a distance of 3.76 Å. © 2011 American Chemical Society.

  9. Dynamics of charge carrier trapping in NO 2 sensors based on ZnO field-effect transistors

    NARCIS (Netherlands)

    Andringa, A.-M.; Vlietstra, N.; Smits, E.C.P.; Spijkman, M.-J.; Gomes, H.L.; Klootwijk, J.H.; Blom, P.W.M.; Leeuw, D.M. de

    2012-01-01

    Nitrogen dioxide (NO 2) detection with ZnO field-effect transistors is based on charge carrier trapping. Here we investigate the dynamics of charge trapping and recovery as a function of temperature by monitoring the threshold voltage shift. The threshold voltage shifts follow a

  10. Infrared-transmittance tunable metal-insulator conversion device with thin-film-transistor-type structure on a glass substrate

    Directory of Open Access Journals (Sweden)

    Takayoshi Katase

    2017-05-01

    Full Text Available Infrared (IR transmittance tunable metal-insulator conversion was demonstrated on a glass substrate by using thermochromic vanadium dioxide (VO2 as the active layer in a three-terminal thin-film-transistor-type device with water-infiltrated glass as the gate insulator. Alternative positive/negative gate-voltage applications induce the reversible protonation/deprotonation of a VO2 channel, and two-orders of magnitude modulation of sheet-resistance and 49% modulation of IR-transmittance were simultaneously demonstrated at room temperature by the metal-insulator phase conversion of VO2 in a non-volatile manner. The present device is operable by the room-temperature protonation in an all-solid-state structure, and thus it will provide a new gateway to future energy-saving technology as an advanced smart window.

  11. Tuning the hysteresis voltage in 2D multilayer MoS{sub 2} FETs

    Energy Technology Data Exchange (ETDEWEB)

    Jiang, Jie, E-mail: jiangjie@csu.edu.cn; Zheng, Zhouming; Guo, Junjie

    2016-10-01

    The hysteresis tuning is of great significance before the two-dimensional (2D) molybdenum disulfide (MoS{sub 2}) field-effect transistors (FETs) can be practically used in the next-generation nanoelectronic devices. In this paper, a simple and effective annealing method was developed to tune the hysteresis voltage in 2D MoS{sub 2} transistors. It was found that high temperature (175 °C) annealing in air could increase the hysteresis voltage from 8.0 V (original device) to 28.4 V, while a next vacuum annealing would reduce the hysteresis voltage to be only 2.0 V. An energyband diagram model based on electron trapping/detrapping due to oxygen adsorption is proposed to understand the hysteresis mechanism in multilayer MoS{sub 2} FET. This simple method for tuning the hysteresis voltage of MoS{sub 2} FET can make a significant step toward 2D nanoelectronic device applications.

  12. Performance Enhancement of Power Transistors and Radiation effect

    International Nuclear Information System (INIS)

    Hassn, Th.A.A.

    2012-01-01

    The main objective of this scientific research is studying the characteristic of bipolar junction transistor device and its performance under radiation fields and temperature effect as a control element in many power circuits. In this work we present the results of experimental measurements and analytical simulation of gamma – radiation effects on the electrical characteristics and operation of power transistor types 2N3773, 2N3055(as complementary silicon power transistor are designed for general-purpose switching and amplifier applications), three samples of each type were irradiated by gamma radiation with doses, 1 K rad, 5 K rad, 10 K rad, 30 K rad, and 10 Mrad, the experimental data are utilized to establish an analytical relation between the total absorbed dose of gamma irradiation and corresponding to effective density of generated charge in the internal structure of transistor, the electrical parameters which can be measured to estimate the generated defects in the power transistor are current gain, collector current and collected emitter leakage current , these changes cause the circuit to case proper functioning. Collector current and transconductance of each device are calibrated as a function of irradiated dose. Also the threshold voltage and transistor gain can be affected and also calibrated as a function of dose. A silicon NPN power transistor type 2N3773 intended for general purpose applications, were used in this work. It was designed for medium current and high power circuits. Performance and characteristic were discusses under temperature and gamma radiation doses. Also the internal junction thermal system of the transistor represented in terms of a junction thermal resistance (Rjth). The thermal resistance changed by ΔRjth, due to the external intended, also due to the gamma doses intended. The final result from the model analysis reveals that the emitter-bias configuration is quite stable by resistance ratio RB/RE. Also the current

  13. Combinatorial study of zinc tin oxide thin-film transistors

    Science.gov (United States)

    McDowell, M. G.; Sanderson, R. J.; Hill, I. G.

    2008-01-01

    Groups of thin-film transistors using a zinc tin oxide semiconductor layer have been fabricated via a combinatorial rf sputtering technique. The ZnO :SnO2 ratio of the film varies as a function of position on the sample, from pure ZnO to SnO2, allowing for a study of zinc tin oxide transistor performance as a function of channel stoichiometry. The devices were found to have mobilities ranging from 2to12cm2/Vs, with two peaks in mobility in devices at ZnO fractions of 0.80±0.03 and 0.25±0.05, and on/off ratios as high as 107. Transistors composed predominantly of SnO2 were found to exhibit light sensitivity which affected both the on/off ratios and threshold voltages of these devices.

  14. The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

    Science.gov (United States)

    Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

    2004-06-01

    The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

  15. Low Temperature Noise and Electrical Characterization of the Company Heterojunction Field-Effect Transistor

    Science.gov (United States)

    Cunningham, Thomas J.; Gee, Russell C.; Fossum, Eric R.; Baier, Steven M.

    1993-01-01

    This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.

  16. Stable organic thin-film transistors

    Science.gov (United States)

    Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; Park, Youngrak; Kippelen, Bernard

    2018-01-01

    Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperature over time periods up to 5.9 × 105 s do not vary monotonically and remain below 0.2 V in microcrystalline OTFTs (μc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies. PMID:29340301

  17. Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

    Science.gov (United States)

    Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

    2005-04-01

    We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

  18. Ion sensors based on novel fiber organic electrochemical transistors for lead ion detection.

    Science.gov (United States)

    Wang, Yuedan; Zhou, Zhou; Qing, Xing; Zhong, Weibing; Liu, Qiongzhen; Wang, Wenwen; Li, Mufang; Liu, Ke; Wang, Dong

    2016-08-01

    Fiber organic electrochemical transistors (FECTs) based on polypyrrole and nanofibers have been prepared for the first time. FECTs exhibited excellent electrical performances, on/off ratios up to 10(4) and low applied voltages below 2 V. The ion sensitivity behavior of the fiber organic electrochemical transistors was investigated. It exhibited that the transfer curve of FECTs shifted to lower gate voltage with increasing cations concentration, the sensitivity reached to 446 μA/dec in the 10(-5)-10(-2) M Pb(2+) concentration range. The ion selective properties of the FECTs have also been systematically studied for the detection of potassium, calcium, aluminum, and lead ions. The devices with different cations showed great difference in response curves. It was suitable for selectively monitoring Pb(2+) with respect to other cations. The results indicated FECTs were very effective for electrochemical sensing of lead ion, which opened a promising perspective for wearable electronics in healthcare and biological application. Graphical Abstract The schematic diagram of fiber organic electrochemical transistors based on polypyrrole and nanofibers for ion sensing.

  19. Organic thin film transistors using a liquid crystalline palladium phthalocyanine as active layer

    Science.gov (United States)

    Jiménez Tejada, Juan A.; Lopez-Varo, Pilar; Chaure, Nandu B.; Chambrier, Isabelle; Cammidge, Andrew N.; Cook, Michael J.; Jafari-Fini, Ali; Ray, Asim K.

    2018-03-01

    70 nm thick solution-processed films of a palladium phthalocyanine (PdPc6) derivative bearing eight hexyl (-C6H13) chains at non-peripheral positions have been employed as active layers in the fabrication of bottom-gate bottom-contact organic thin film transistors (OTFTs) deposited on highly doped p-type Si (110) substrates with SiO2 gate dielectric. The dependence of the transistor electrical performance upon the mesophase behavior of the PdPc6 films has been investigated by measuring the output and transfer characteristics of the OTFT having its active layer ex situ vacuum annealed at temperatures between 500 °C and 200 °C. A clear correlation between the annealing temperature and the threshold voltage and carrier mobility of the transistors, and the transition temperatures extracted from the differential scanning calorimetric curves for bulk materials has been established. This direct relation has been obtained by means of a compact electrical model in which the contact effects are taken into account. The precise determination of the contact-voltage drain-current curves allows for obtaining such a relation.

  20. Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

    Science.gov (United States)

    Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

    2016-06-15

    Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

  1. Fermilab main accelerator quadrupole transistorized regulators for improved tune stability

    International Nuclear Information System (INIS)

    Yarema, R.J.; Pfeffer, H.

    1977-01-01

    During early operation of the Fermilab Main Accelerator, tune fluctuations, caused by the SCR-controlled power supplies in the quad bus, limited the beam aperature at low energies. To correct this problem, two transistorized power supplies were built in 1975 to regulate and filter the main ring quad magnet current during injection and beam acceleration through the rf transistion region. There is one power supply in series with each quad bus. Each supply uses 320 parallel power transistors and is rated at 300A, 120V. Since the voltage and current capabilities of the transistorized supplies are limited, the supplies are turned-off at about 25GeV. A real-time computer system initiates turn-on of the SCR-controlled power supplies and regulation takeover by the SCR-controlled supplies, at the appropriate times

  2. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  3. Radiation effects on JFETS, MOSFETS, and bipolar transistors, as related to SSC circuit design

    Energy Technology Data Exchange (ETDEWEB)

    Kennedy, E J; Gray, B; Wu, A [Dept. of Electrical and Computer Engineering, Univ. of Tennessee, Knoxville, TN (United States); Alley, G T; Britton, Jr, C L [Oak Ridge National Lab., TN (United States); Skubic, P L [Univ. of Oklahoma, Dept. of Physics and Astronomy, Norman, OK (United States)

    1991-10-01

    Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular at currents {<=} 1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier. (orig.).

  4. High-frequency high-voltage high-power DC-to-DC converters

    Science.gov (United States)

    Wilson, T. G.; Owen, H. A.; Wilson, P. M.

    1982-09-01

    A simple analysis of the current and voltage waveshapes associated with the power transistor and the power diode in an example current-or-voltage step-up (buck-boost) converter is presented. The purpose of the analysis is to provide an overview of the problems and design trade-offs which must be addressed as high-power high-voltage converters are operated at switching frequencies in the range of 100 kHz and beyond. Although the analysis focuses on the current-or-voltage step-up converter as the vehicle for discussion, the basic principles presented are applicable to other converter topologies as well.

  5. Radiation resistance of wide-bandgap semiconductor power transistors

    Energy Technology Data Exchange (ETDEWEB)

    Hazdra, Pavel; Popelka, Stanislav [Department of Microelectronics, Czech Technical University in Prague (Czech Republic)

    2017-04-15

    Radiation resistance of state-of-the-art commercial wide-bandgap power transistors, 1700 V 4H-SiC power MOSFETs and 200 V GaN HEMTs, to the total ionization dose was investigated. Transistors were irradiated with 4.5 MeV electrons with doses up to 2000 kGy. Electrical characteristics and introduced defects were characterized by current-voltage (I-V), capacitance-voltage (C-V), and deep level transient spectroscopy (DLTS) measurements. Results show that already low doses of 4.5 MeV electrons (>1 kGy) cause a significant decrease in threshold voltage of SiC MOSFETs due to embedding of the positive charge into the gate oxide. On the other hand, other parameters like the ON-state resistance are nearly unchanged up to the dose of 20 kGy. At 200 kGy, the threshold voltage returns back close to its original value, however, the ON-state resistance increases and transconductance is lowered. This effect is caused by radiation defects introduced into the low-doped drift region which decrease electron concentration and mobility. GaN HEMTs exhibit significantly higher radiation resistance. They keep within the datasheet specification up to doses of 2000 kGy. Absence of dielectric layer beneath the gate and high concentration of carriers in the two dimensional electron gas channel are the reasons of higher radiation resistance of GaN HEMTs. Their degradation then occurs at much higher doses due to electron mobility degradation. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  6. Doping kinetics of organic semiconductors investigated by field-effect transistors

    NARCIS (Netherlands)

    Maddalena, F.; Meijer, E.J.; Asadi, K.; Leeuw, D.M. de; Blom, P.W.M.

    2010-01-01

    The kinetics of acid doping of the semiconductor regioregular poly-3-hexylthiophene with vaporized chlorosilane have been investigated using field-effect transistors. The dopant density has been derived as a function of temperature and exposure time from the shift in the pinch-off voltage, being the

  7. Coulomb Blockade and Multiple Andreev Reflection in a Superconducting Single-Electron Transistor

    Science.gov (United States)

    Lorenz, Thomas; Sprenger, Susanne; Scheer, Elke

    2018-06-01

    In superconducting quantum point contacts, multiple Andreev reflection (MAR), which describes the coherent transport of m quasiparticles each carrying an electron charge with m≥3, sets in at voltage thresholds eV = 2Δ /m. In single-electron transistors, Coulomb blockade, however, suppresses the current at low voltage. The required voltage for charge transport increases with the square of the effective charge eV∝ ( me) ^2. Thus, studying the charge transport in all-superconducting single-electron transistors (SSETs) sets these two phenomena into competition. In this article, we present the fabrication as well as a measurement scheme and transport data for a SSET with one junction in which the transmission and thereby the MAR contributions can be continuously tuned. All regimes from weak to strong coupling are addressed. We extend the Orthodox theory by incorporating MAR processes to describe the observed data qualitatively. We detect a new transport process the nature of which is unclear at present. Furthermore, we observe a renormalization of the charging energy when approaching the strong coupling regime.

  8. Transparent Thin-Film Transistors Based on Sputtered Electric Double Layer.

    Science.gov (United States)

    Cai, Wensi; Ma, Xiaochen; Zhang, Jiawei; Song, Aimin

    2017-04-20

    Electric-double-layer (EDL) thin-film transistors (TFTs) have attracted much attention due to their low operation voltages. Recently, EDL TFTs gated with radio frequency (RF) magnetron sputtered SiO₂ have been developed which is compatible to large-area electronics fabrication. In this work, fully transparent Indium-Gallium-Zinc-Oxide-based EDL TFTs on glass substrates have been fabricated at room temperature for the first time. A maximum transmittance of about 80% has been achieved in the visible light range. The transparent TFTs show a low operation voltage of 1.5 V due to the large EDL capacitance (0.3 µF/cm² at 20 Hz). The devices exhibit a good performance with a low subthreshold swing of 130 mV/dec and a high on-off ratio > 10⁵. Several tests have also been done to investigate the influences of light irradiation and bias stress. Our results suggest that such transistors might have potential applications in battery-powered transparent electron devices.

  9. Probing organic field effect transistors in situ during operation using SFG.

    Science.gov (United States)

    Ye, Hongke; Abu-Akeel, Ashraf; Huang, Jia; Katz, Howard E; Gracias, David H

    2006-05-24

    In this communication, we report results obtained using surface-sensitive IR+Visible Sum Frequency Generation (SFG) nonlinear optical spectroscopy on interfaces of organic field effect transistors during operation. We observe remarkable correlations between trends in the surface vibrational spectra and electrical properties of the transistor, with changes in gate voltage (VG). These results suggest that field effects on electronic conduction in thin film organic semiconductor devices are correlated to interfacial nonlinear optical characteristics and point to the possibility of using SFG spectroscopy to monitor electronic properties of OFETs.

  10. Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

    Energy Technology Data Exchange (ETDEWEB)

    Dib, E., E-mail: elias.dib@for.unipi.it [Dipartimento di Ingegneria dell' Informazione, Università di Pisa, 56122 Pisa (Italy); Carrillo-Nuñez, H. [Integrated Systems Laboratory ETH Zürich, Gloriastrasse 35, 8092 Zürich (Switzerland); Cavassilas, N.; Bescond, M. [IM2NP, UMR CNRS 6242, Bât. IRPHE, Technopôle de Château-Gombert, 13384 Marseille Cedex 13 (France)

    2016-01-28

    Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

  11. Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

    International Nuclear Information System (INIS)

    Dib, E.; Carrillo-Nuñez, H.; Cavassilas, N.; Bescond, M.

    2016-01-01

    Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations

  12. FPGA Based Compensation Method for Correcting Distortion in Voltage Inverters

    National Research Council Canada - National Science Library

    Williamson, Kenya D

    2007-01-01

    ...) voltage source inverters. Blanking time distortion is caused by the delay inserted to prevent the short circuit that would occur if the two transistors in the same inverter leg are both on at the same time...

  13. Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

    Science.gov (United States)

    Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

    2015-12-01

    In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

  14. Breakdown voltage at the electric terminals of GCFR-core flow test loop fuel rod simulators in helium and air

    International Nuclear Information System (INIS)

    Huntley, W.R.; Conley, T.B.

    1979-12-01

    Tests were performed to determine the ac and dc breakdown voltage at the terminal ends of a fuel rod simulator (FRS) in helium and air atmospheres. The tests were performed at low pressures (1 to 2 atm) and at temperatures from 20 to 350 0 C (68 to 660 0 F). The area of concern was the 0.64-mm (0.025-in.) gap between the coaxial conductor of the FRS and the sheaths of the four internal thermocouples as they exit the FRS. The tests were prformed to ensure a sufficient safety margin during Core Flow Test Loop (CFTL) operations that require potentials up to 350 V ac at the FRS terminals. The primary conclusion from the test results is that the CFTL cannot be operated safely if the terminal ends of the FRSs are surrounded by a helium atmosphere but can be operated safely in air

  15. Number-to-voltage converter on commutated condensers

    International Nuclear Information System (INIS)

    Grekhov, Yu.N.

    1975-01-01

    A code-voltage converter using precision voltage dividers based on commutated capacitors [1] is described which is distinguished by the absence of precision elements. Each digit includes eight field-effect transistors in two 1KT682 microcircuit assemblies and three microcapacitors with a conventional unstable capacitance 6200 pF +- 50%. The converter has a speed of response that is not inferior to that of converters based on R-2R matrices, while in time stability of the characteristics, low interference level, and low output impedance it is superior to such converters

  16. Transistor collector breakdown in the presence of conducted EMP and gamma radiation

    International Nuclear Information System (INIS)

    Rice, D.H.

    1975-01-01

    In this paper we develop expressions which describe breakdown, negative resistance and latch characteristics for a common emitter transistor when exposed to simultaneous conducted EMP and ionizing radiation. These expressions are derived from a modified Ebers-Moll model and show that common emitter breakdown voltage is reduced, latch (or sustaining voltage) remains unchanged, and that the negative resistance characteristics are changed. Using the modified Ebers-Moll model good agreement between predicted and observed circuit response is demonstrated when the circuits are exposed to a rising collector voltage (due to EMP) and simultaneous ionizing (gamma) radiation

  17. Modeling of charge transport in ion bipolar junction transistors.

    Science.gov (United States)

    Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

    2014-06-17

    Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

  18. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    International Nuclear Information System (INIS)

    Che, Yongli; Zhang, Yating; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan; Cao, Xiaolong; Dai, Haitao; Yang, Junbo

    2016-01-01

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV th  ∼ 15 V) and a long retention time (>10 5  s). The magnitude of ΔV th depended on both P/E voltages and the bias voltage (V DS ): ΔV th was a cubic function to V P/E and linearly depended on V DS . Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  19. MIS field effect transistor with barium titanate thin film as a gate insulator

    Energy Technology Data Exchange (ETDEWEB)

    Firek, P., E-mail: pfirek@elka.pw.edu.p [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Werbowy, A.; Szmidt, J. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland)

    2009-11-25

    The properties of barium titanate (BaTiO{sub 3}, BT) like, e.g. high dielectric constant and resistivity, allow it to find numerous applications in field of microelectronics. In this work silicon metal insulator semiconductor field effect transistor (MISFET) structures with BaTiO{sub 3} (containing La{sub 2}O{sub 3} admixture) thin films in a role of gate insulator were investigated. The films were produced by means of radio frequency plasma sputtering (RF PS) of sintered BaTiO{sub 3} + La{sub 2}O{sub 3} (2 wt.%) target. In the paper transfer and output current-voltage (I-V), transconductance and output conductance characteristics of obtained transistors are presented and discussed. Basic parameters of these devices like, e.g. threshold voltage (V{sub TH}), are determined and discussed.

  20. Influence of non-adherent yeast cells on electrical characteristics of diamond-based field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Procházka, Václav, E-mail: prochazkav@fzu.cz [Faculty of Electrical Engineering, Czech Technical University in Prague, Technická 2, 16627 Prague (Czech Republic); Institute of Physics, The Czech Academy of Sciences, Cukrovarnická 10/112, 162 00 Prague (Czech Republic); Cifra, Michal [Institute of Photonics and Electronics, The Czech Academy of Sciences, Chaberská 57, 182 51 Prague (Czech Republic); Kulha, Pavel [Faculty of Electrical Engineering, Czech Technical University in Prague, Technická 2, 16627 Prague (Czech Republic); Institute of Physics, The Czech Academy of Sciences, Cukrovarnická 10/112, 162 00 Prague (Czech Republic); Ižák, Tibor [Institute of Physics, The Czech Academy of Sciences, Cukrovarnická 10/112, 162 00 Prague (Czech Republic); Rezek, Bohuslav [Faculty of Electrical Engineering, Czech Technical University in Prague, Technická 2, 16627 Prague (Czech Republic); Institute of Physics, The Czech Academy of Sciences, Cukrovarnická 10/112, 162 00 Prague (Czech Republic); Kromka, Alexander [Institute of Physics, The Czech Academy of Sciences, Cukrovarnická 10/112, 162 00 Prague (Czech Republic); Faculty of Civil Engineering, Czech Technical University in Prague, Thákurova 7, 16629 Prague (Czech Republic)

    2017-02-15

    Highlights: • Interaction of non-adherent yeast cells with H-terminated diamond described. • Effect of cell culture solutions on H-diamond SGFET (positive potential shifts). • H-diamond sensitive to metabolic activity of yeast cells (negative potential shift). - Abstract: Diamond thin films provide unique features as substrates for cell cultures and as bio-electronic sensors. Here we employ solution-gated field effect transistors (SGFET) based on nanocrystalline diamond thin films with H-terminated surface which exhibits the sub-surface p-type conductive channel. We study an influence of yeast cells (Saccharomyces cerevisiae) on electrical characteristics of the diamond SGFETs. Two different cell culture solutions (sucrose and yeast peptone dextrose–YPD) are used, with and without the cells. We have found that transfer characteristics of the SGFETs exhibit a negative shift of the gate voltage by −26 mV and −42 mV for sucrose and YPD with cells in comparison to blank solutions without the cells. This effect is attributed to a local pH change in close vicinity of the H-terminated diamond surface due to metabolic processes of the yeast cells. The pH sensitivity of the diamond-based SGFETs, the role of cell and protein adhesion on the gate surface and the role of negative surface charge of yeast cells on the SGFETs electrical characteristics are discussed as well.

  1. Influence of non-adherent yeast cells on electrical characteristics of diamond-based field-effect transistors

    International Nuclear Information System (INIS)

    Procházka, Václav; Cifra, Michal; Kulha, Pavel; Ižák, Tibor; Rezek, Bohuslav; Kromka, Alexander

    2017-01-01

    Highlights: • Interaction of non-adherent yeast cells with H-terminated diamond described. • Effect of cell culture solutions on H-diamond SGFET (positive potential shifts). • H-diamond sensitive to metabolic activity of yeast cells (negative potential shift). - Abstract: Diamond thin films provide unique features as substrates for cell cultures and as bio-electronic sensors. Here we employ solution-gated field effect transistors (SGFET) based on nanocrystalline diamond thin films with H-terminated surface which exhibits the sub-surface p-type conductive channel. We study an influence of yeast cells (Saccharomyces cerevisiae) on electrical characteristics of the diamond SGFETs. Two different cell culture solutions (sucrose and yeast peptone dextrose–YPD) are used, with and without the cells. We have found that transfer characteristics of the SGFETs exhibit a negative shift of the gate voltage by −26 mV and −42 mV for sucrose and YPD with cells in comparison to blank solutions without the cells. This effect is attributed to a local pH change in close vicinity of the H-terminated diamond surface due to metabolic processes of the yeast cells. The pH sensitivity of the diamond-based SGFETs, the role of cell and protein adhesion on the gate surface and the role of negative surface charge of yeast cells on the SGFETs electrical characteristics are discussed as well.

  2. Analytical Model of Subthreshold Drain Current Characteristics of Ballistic Silicon Nanowire Transistors

    Directory of Open Access Journals (Sweden)

    Wanjie Xu

    2015-01-01

    Full Text Available A physically based subthreshold current model for silicon nanowire transistors working in the ballistic regime is developed. Based on the electric potential distribution obtained from a 2D Poisson equation and by performing some perturbation approximations for subband energy levels, an analytical model for the subthreshold drain current is obtained. The model is further used for predicting the subthreshold slopes and threshold voltages of the transistors. Our results agree well with TCAD simulation with different geometries and under different biasing conditions.

  3. AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with reduced leakage current and enhanced breakdown voltage using aluminum ion implantation

    Energy Technology Data Exchange (ETDEWEB)

    Sun, Shichuang [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China); Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou 215123 (China); Fu, Kai, E-mail: kfu2009@sinano.ac.cn, E-mail: cqchen@mail.hust.edu.cn; Yu, Guohao; Zhang, Zhili; Song, Liang; Deng, Xuguang; Li, Shuiming; Sun, Qian; Cai, Yong; Zhang, Baoshun [Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS, Suzhou 215123 (China); Qi, Zhiqiang; Dai, Jiangnan; Chen, Changqing, E-mail: kfu2009@sinano.ac.cn, E-mail: cqchen@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan 430074 (China)

    2016-01-04

    This letter has studied the performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors on silicon substrate with GaN buffer treated by aluminum ion implantation for insulating followed by a channel regrown by metal–organic chemical vapor deposition. For samples with Al ion implantation of multiple energies of 140 keV (dose: 1.4 × 10{sup 14} cm{sup −2}) and 90 keV (dose: 1 × 10{sup 14} cm{sup −2}), the OFF-state leakage current is decreased by more than 3 orders and the breakdown voltage is enhanced by nearly 6 times compared to the samples without Al ion implantation. Besides, little degradation of electrical properties of the 2D electron gas channel is observed where the maximum drain current I{sub DSmax} at a gate voltage of 3 V was 701 mA/mm and the maximum transconductance g{sub mmax} was 83 mS/mm.

  4. Low-voltage self-assembled monolayer field-effect transistors on flexible substrates.

    Science.gov (United States)

    Schmaltz, Thomas; Amin, Atefeh Y; Khassanov, Artoem; Meyer-Friedrichsen, Timo; Steinrück, Hans-Georg; Magerl, Andreas; Segura, Juan José; Voitchovsky, Kislon; Stellacci, Francesco; Halik, Marcus

    2013-08-27

    Self-assembled monolayer field-effect transistors (SAMFETs) of BTBT functionalized phosphonic acids are fabricated. The molecular design enables device operation with charge carrier mobilities up to 10(-2) cm(2) V(-1) s(-1) and for the first time SAMFETs which operate on rough, flexible PEN substrates even under mechanical substrate bending. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Bipolar Transistors Can Detect Charge in Electrostatic Experiments

    Science.gov (United States)

    Dvorak, L.

    2012-01-01

    A simple charge indicator with bipolar transistors is described that can be used in various electrostatic experiments. Its behaviour enables us to elucidate links between 'static electricity' and electric currents. In addition it allows us to relate the sign of static charges to the sign of the terminals of an ordinary battery. (Contains 7 figures…

  6. A study of s new power semiconductor insulated gate bipolar transistor (IGBT) characteristics and its application to automotive ignition

    International Nuclear Information System (INIS)

    Rabah, K.V.O.

    1995-05-01

    Assessment has been made of the problem of the on-resistance and temperature effects in the three power transistor combinations, such as Darlington-types or IGBT. The IGBT is a device in which the drain of the MOSFET feeds the bipolar base in monolithic (IC and Power on the same chip) to give it both the MOS and bipolar advantages. The high temperature operating characteristics of the device are discussed and compared to that of power bipolar transistor. Unlike the power bipolar transistor whose operating current density shows current crowding at above forward collector current of 4Amps and forward voltage drop above 0.4V, the IGBT is found to maintain its high current density above forward collector of current 1Amp (or a forward voltage drop above 1.2V). The results also indicate that these devices (IGBTs) can be interdigited (paralleled) without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.2V, and this makes it the best candidate for automotive ignition power switches. (author). 20 refs, 10 figs, 1 tab

  7. P-type Cu2O/SnO bilayer thin film transistors processed at low temperatures

    KAUST Repository

    Al-Jawhari, Hala A.

    2013-10-09

    P-type Cu2O/SnO bilayer thin film transistors (TFTs) with tunable performance were fabricated using room temperature sputtered copper and tin oxides. Using Cu2O film as capping layer on top of a SnO film to control its stoichiometry, we have optimized the performance of the resulting bilayer transistor. A transistor with 10 nm/15 nm Cu2O to SnO thickness ratio (25 nm total thickness) showed the best performance using a maximum process temperature of 170 C. The bilayer transistor exhibited p-type behavior with field-effect mobility, on-to-off current ratio, and threshold voltage of 0.66 cm2 V-1 s-1, 1.5×10 2, and -5.2 V, respectively. The advantages of the bilayer structure relative to single layer transistor are discussed. © 2013 American Chemical Society.

  8. Low operating voltage InGaZnO thin-film transistors based on Al{sub 2}O{sub 3} high-k dielectrics fabricated using pulsed laser deposition

    Energy Technology Data Exchange (ETDEWEB)

    Geng, G. Z.; Liu, G. X.; Zhang, Q.; Shan, F. K. [Qingdao University, Qingdao (China); DongEui University, Busan (Korea, Republic of); Lee, W. J.; Shin, B. C. [DongEui University, Busan (Korea, Republic of); Cho, C. R. [Pusan National University, Busan (Korea, Republic of)

    2014-05-15

    Low-voltage-driven amorphous indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) with an Al{sub 2}O{sub 3} dielectric were fabricated on a Si substrate by using pulsed laser deposition. Both Al{sub 2}O{sub 3} and IGZO thin films are amorphous, and the thin films have very smooth surfaces. The Al{sub 2}O{sub 3} gate dielectric exhibits a very low leakage current density of 1.3 x 10{sup -8} A/cm{sup 2} at 5 V and a high capacitance density of 60.9 nF/cm{sup 2}. The IGZO TFT with a structure of Ni/IGZO/Al{sub 2}O{sub 3}/Si exhibits high performance with a low threshold voltage of 1.18 V, a high field effect mobility of 20.25 cm{sup 2}V{sup -1}s{sup -1}, an ultra small subthreshold swing of 87 mV/decade, and a high on/off current ratio of 3 x 10{sup 7}.

  9. Steep Turn On/Off Green Tunnel Transistors

    Science.gov (United States)

    2010-12-17

    band tunneling ( BTBT ), in which electrons tunnel across the energy gap of a semiconductor (i.e., valance to conduction band). Subsequent chapters will...discuss the simulation and experimental results of several transistor designs utilizing BTBT as an active “source” and enabler for ultra low voltage...operation. A thorough understanding of the BTBT models is invaluable for future discussions. In this chapter the derivation of the local or constant

  10. Transistor Effect in Improperly Connected Transistors.

    Science.gov (United States)

    Luzader, Stephen; Sanchez-Velasco, Eduardo

    1996-01-01

    Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

  11. Si/SiC heterojunction optically controlled transistor with charge compensation layer

    Directory of Open Access Journals (Sweden)

    Pu Hongbin

    2016-01-01

    Full Text Available A novel n-SiC/p-Si/n-Si optically controlled transistor with charge compensation layer has been studied in the paper. The performance of the device is simulated using Silvaco Atlas tools, which indicates excellent performances of the device in both blocking state and conducting state. The device also has a good switching characteristic with 0.54μs as rising time and 0.66μs as falling time. With the charge compensation layer, the breakdown voltage and the spectral response intensity of the device are improved by 90V and 33A/W respectively. Compared with optically controlled transistor without charge compensation layer, the n-SiC/p-Si/n-Si optically controlled transistor with charge compensation layer has a better performance.

  12. High-current and low acceleration voltage arsenic ion implanted polysilicon-gate and source-drain electrode Si mos transistor

    International Nuclear Information System (INIS)

    Saito, Yasuyuki; Sugimura, Yoshiro; Sugihara, Michiyuki

    1993-01-01

    The fabrication process of high current arsenic (As) ion implanted polysilicon (Si) gate and source drain (SD) electrode Si n-channel metal oxide-semiconductor field effect transistor (MOSFET) was examined. Poly Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose As implanted poly Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique, the n-channel Poly Si gate (ρs = ≅100Ω/□) enhancement MQSFETs(ρs source drain = ≅50Ω/□, SiO 2 gate=380 angstrom) with off-leak-less were obtained on 3 inch Czochralski grown 2Ωcm boron doped p type wafers (Osaka titanium). By the same process, a 8 bit single chip μ-processor with 26MHz full operation was performed

  13. Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

    KAUST Repository

    Hanna, Amir Nabil

    2017-11-13

    A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor\\'s width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

  14. High-voltage transistor converter for pulsed x-ray sources

    International Nuclear Information System (INIS)

    Krasil'nikov, S.B.; Kristalinskii, A.L.; Lozovoi, L.N.; Markov, S.N.; Sindalovskii, E.I.

    1986-01-01

    A 24-V/12-kV converter for MIRA-2D and NORA pulsed x-ray sources is described. When the low-voltage supply varies within 20-26 V, the frequency stability of the x-ray pulses is higher by a factor of 3 ≅ 3 than when the PRIMA converter is used. For 14-24 V, the average output power of the converter is independent of the load impedance and increases linearly with an increase in supply voltage. The efficiency of the converter reaches 60%. The converter operates in the temperature range of -40 to +60 0 C

  15. Comment on "Performance of a spin based insulated gate field effect transistor" [cond-mat/0603260] [cond-mat/0603260

    OpenAIRE

    Bandyopadhyay, S.; Cahay, M.

    2006-01-01

    In a recent e-print [cond-mat/0603260] Hall and Flatte claim that a particular spin based field effect transistor (SPINFET), which they have analyzed, will have a lower threshold voltage, lower switching energy and lower leakage current than a comparable metal oxide semiconductor field effect transistor (MOSFET). Here, we show that all three claims of HF are invalid.

  16. Micro-irradiation experiments in MOS transistors using synchrotron radiation

    International Nuclear Information System (INIS)

    Autran, J.L.; Masson, P.; Raynaud, C.; Freud, N.; Riekel, C.

    1999-01-01

    Spatially-resolved total-dose degradation has been performed in MOS transistors by focusing x-ray synchrotron radiation on the gate electrode with micrometer resolution. The influence of the resulting permanent degradation on device electrical properties has been analyzed using current-voltage and charge pumping measurements, in concert with optical characterization (hot-carrier luminescence) and one-dimensional device simulation. (authors)

  17. Non-linear effects and thermoelectric efficiency of quantum dot-based single-electron transistors.

    Science.gov (United States)

    Talbo, Vincent; Saint-Martin, Jérôme; Retailleau, Sylvie; Dollfus, Philippe

    2017-11-01

    By means of advanced numerical simulation, the thermoelectric properties of a Si-quantum dot-based single-electron transistor operating in sequential tunneling regime are investigated in terms of figure of merit, efficiency and power. By taking into account the phonon-induced collisional broadening of energy levels in the quantum dot, both heat and electrical currents are computed in a voltage range beyond the linear response. Using our homemade code consisting in a 3D Poisson-Schrödinger solver and the resolution of the Master equation, the Seebeck coefficient at low bias voltage appears to be material independent and nearly independent on the level broadening, which makes this device promising for metrology applications as a nanoscale standard of Seebeck coefficient. Besides, at higher voltage bias, the non-linear characteristics of the heat current are shown to be related to the multi-level effects. Finally, when considering only the electronic contribution to the thermal conductance, the single-electron transistor operating in generator regime is shown to exhibit very good efficiency at maximum power.

  18. Telemetry component tests in the FN tandem terminal

    International Nuclear Information System (INIS)

    Bicek, J.J.; Billquis, P.J.; Yntema, J.L.

    1977-01-01

    When an electrostatic tandem accelerator is used primarily for heavy ion acceleration, numerous communication channels with the high voltage terminal are desirable. The ANL FN tandem operates at a tank pressure of 100 psi SF 6 at terminal voltages up to 9.5 MeV. A low powered He-Ne laser with 15 percent modulation has been successfully tested in the terminal under normal operating conditions. Such a system allows the transmission of information without the use of light guides. Multistranded light guides did not withstand voltage gradients as low as 0.4 MV/m. Single core light guides with a diameter of 0.5 mm have been successfully operated at voltage gradients in excess of 1.7 MV/m. In addition to the laser a microprocessor has also been tested in the tandem terminal. With suitable protection, an 8080 microprocessor and a programmable ROM operated successfully for several weeks under normal operating conditions

  19. Hole-transporting transistors and circuits based on the transparent inorganic semiconductor copper(I) thiocyanate (CuSCN) processed from solution at room temperature

    KAUST Repository

    Pattanasattayavong, Pichaya; Yaacobi-Gross, Nir; Zhao, Kui; Ndjawa, Guy Olivier Ngongang; Li, Jinhua; Yan, Feng; O'Regan, Brian C.; Amassian, Aram; Anthopoulos, Thomas D.

    2012-01-01

    ferroelectric polymeric dielectric P(VDF-TrFE-CFE), we demonstrate low-voltage transistors with hole mobilities on the order of 0.1 cm2 V-1 s-1. By integrating two CuSCN transistors, unipolar logic NOT gates are also demonstrated. Copyright © 2013 WILEY

  20. SOI Transistor measurement techniques using body contacted transistors

    International Nuclear Information System (INIS)

    Worley, E.R.; Williams, R.

    1989-01-01

    Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

  1. Microwave-induced co-tunneling in single electron tunneling transistors

    DEFF Research Database (Denmark)

    Ejrnaes, M.; Savolainen, M.; Manscher, M.

    2002-01-01

    on rubber bellows. Cross-talk was minimized by using individual coaxial lines between the sample and the room temperature electronics: The co-tunneling experiments were performed at zero DC bias current by measuring the voltage response to a very small amplitude 2 Hz current modulation with the gate voltage......The influence of microwaves on the co-tunneling in single electron tunneling transistors has been investigated as function of frequency and power in the temperature range from 150 to 500 mK. All 20 low frequency connections and the RF line were filtered, and the whole cryostat was suspended...

  2. Subthreshold Schottky-barrier thin-film transistors with ultralow power and high intrinsic gain

    Science.gov (United States)

    Lee, Sungsik; Nathan, Arokia

    2016-10-01

    The quest for low power becomes highly compelling in newly emerging application areas related to wearable devices in the Internet of Things. Here, we report on a Schottky-barrier indium-gallium-zinc-oxide thin-film transistor operating in the deep subthreshold regime (i.e., near the OFF state) at low supply voltages (400) that was both bias and geometry independent. The transistor reported here is useful for sensor interface circuits in wearable devices where high current sensitivity and ultralow power are vital for battery-less operation.

  3. Transistor data book

    International Nuclear Information System (INIS)

    1988-03-01

    It introduces how to use this book. It lists transistor data and index, which are Type No, Cross index, Germanium PNP low power transistors, silicon NPN low power transistors, Germanium PNP high power transistors, Switching transistors, transistor arrays, Miscellaneous transistors, types with U.S military specifications, direct replacement transistors, suggested replacement transistors, schematic drawings, outline drawings, device number keys and manufacturer's logos.

  4. Investigations on field-effect transistors based on two-dimensional materials

    Energy Technology Data Exchange (ETDEWEB)

    Finge, T.; Riederer, F.; Grap, T.; Knoch, J. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Mueller, M.R. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Infineon Technologies, Villach (Austria); Kallis, K. [Intelligent Microsystems Chair, TU Dortmund University (Germany)

    2017-11-15

    In the present article, experimental and theoretical investigations regarding field-effect transistors based on two-dimensional (2D) materials are presented. First, the properties of contacts between a metal and 2D material are discussed. To this end, metal-to-graphene contacts as well to transition metal dichalcogenides (TMD) are studied. Whereas metal-graphene contacts can be tuned with an appropriate back-gate, metal-TMD contacts exhibit strong Fermi level pinning showing substantially limited maximum possible drive current. Next, tungsten diselenide (WSe{sub 2}) field-effect transistors are presented. Employing buried-triple-gate substrates allows tuning source, channel and drain by applying appropriate gate voltages so that the device can be reconfigured to work as n-type, p-type and as so-called band-to-band tunnel field-effect transistor on the same WSe{sub 2} flake. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  5. Fabrication of high-performance InGaZnOx thin film transistors based on control of oxidation using a low-temperature plasma

    Science.gov (United States)

    Takenaka, Kosuke; Endo, Masashi; Uchida, Giichiro; Setsuhara, Yuichi

    2018-04-01

    This work demonstrated the low-temperature control of the oxidation of Amorphous InGaZnOx (a-IGZO) films using inductively coupled plasma as a means of precisely tuning the properties of thin film transistors (TFTs) and as an alternative to post-deposition annealing at high temperatures. The effects of the plasma treatment of the as-deposited a-IGZO films were investigated by assessing the electrical properties of TFTs incorporating these films. A TFT fabricated using an a-IGZO film exposed to an Ar-H2-O2 plasma at substrate temperatures as low as 300 °C exhibited the best performance, with a field effect mobility as high as 42.2 cm2 V-1 s-1, a subthreshold gate voltage swing of 1.2 V decade-1, and a threshold voltage of 2.8 V. The improved transfer characteristics of TFTs fabricated with a-IGZO thin films treated using an Ar-H2-O2 plasma are attributed to the termination of oxygen vacancies around Ga and Zn atoms by OH radicals in the gas phase.

  6. dc analysis and design of zero-voltage-switched multi-resonant converters

    Science.gov (United States)

    Tabisz, Wojciech A.; Lee, Fred C.

    Recently introduced multiresonant converters (MRCs) provide zero-voltage switching (ZVS) of both active and passive switches and offer a substantial reduction of transistor voltage stress and an increase of load range, compared to their quasi-resonant converter counterparts. Using the resonant switch concept, a simple, generalized analysis of ZVS MRCs is presented. The conversion ratio and voltage stress characteristics are derived for basic ZVS MRCs, including buck, boost, and buck/boost converters. Based on the analysis, a design procedure that optimizes the selection of resonant elements for maximum conversion efficiency is proposed.

  7. Overcharge Protection And Cell Voltage Monitoring For Lithium-Ion Batteries

    Science.gov (United States)

    Altemose, George; Salim, Abbas

    2011-10-01

    This paper describes a new Battery Interface and Electronics (BIE) assembly used to monitor battery and cell voltages, as well as provide overvoltage (overcharge) protection for Lithium Ion batteries with up to 8-cells in series. The BIE performs accurate measurement of the individual cell voltages, the total battery voltage, and the individual cell temperatures. In addition, the BIE provides an independent over-charge protection (OCP) circuit that terminates the charging process by isolating the battery from the charging source in the event that the voltage of any cell exceeds a preset limit of +4.500V. The OCP circuit utilizes dual redundancy, and is immune to single-point failures in the sense that no single-point failure can cause the battery to become isolated inadvertently. A typical application of the BIE in a spacecraft electrical power subsystem is shown in Figure 1. The BIE circuits have been designed with Chip On Board (COB) technology. Using this technology, integrated circuit die, Field Effect Transistors (FETs) and diodes are mounted and wired directly on a multi-layer printed wiring board (PWB). For those applications where long term reliability can be achieved without hermeticity, COB technology provides many benefits such as size and weight reduction while lowering production costs. The BIE was designed, fabricated and tested to meet the specifications provided by Orbital Sciences Corporation (OSC) for use with Lithium-Ion batteries in the Commercial Orbital Transportation System (COTS). COTS will be used to deliver cargo to the International Space Station at low earth orbit (LEO). Aeroflex has completed the electrical and mechanical design of the BIE and fabricated and tested the Engineering Model (EM), as well as the Engineering Qualification Model (EQM). Flight units have also been fabricated, tested and delivered to OSC.

  8. Analyzing Single-Event Gate Ruptures In Power MOSFET's

    Science.gov (United States)

    Zoutendyk, John A.

    1993-01-01

    Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

  9. Reliability of planar silicon transistors exposed to 60Co γ rays

    International Nuclear Information System (INIS)

    Blin, A.; Le Ber, J.

    1966-01-01

    This report gives an account of results obtained during investigations on the reliability of silicon Planar Transistors, irradiated by the 60 Co γ rays. We consider in a first part the variation of the average values of the parameters of the lots under test. Then, a more complete statistical study is carried out (distribution of the values of the parameters within the lots; research of correlations, etc. ). It is clearly stated and shown that evaluation of the degradation of the gain of transistors depends on: the conditions of measurement (voltage, current), after irradiation; the polarisation of the elements during irradiation; the origin of manufacture of the lots under test (4 manufacturers). We show then the difficulties met to predict the behaviour of the transistors under radiation stress, and attempt is made to define practical rules for design engineers. (author) [fr

  10. Design and Implementation of a High-Voltage Generator with Output Voltage Control for Vehicle ER Shock-Absorber Applications

    Directory of Open Access Journals (Sweden)

    Chih-Lung Shen

    2013-01-01

    Full Text Available A self-oscillating high-voltage generator is proposed to supply voltage for a suspension system in order to control the damping force of an electrorheological (ER fluid shock absorber. By controlling the output voltage level of the generator, the damping force in the ER fluid shock absorber can be adjusted immediately. The shock absorber is part of the suspension system. The high-voltage generator drives a power transistor based on self-excited oscillation, which converts dc to ac. A high-frequency transformer with high turns ratio is used to increase the voltage. In addition, the system uses the car battery as dc power supply. By regulating the duty cycle of the main switch in the buck converter, the output voltage of the buck converter can be linearly adjusted so as to obtain a specific high voltage for ER. The driving system is self-excited; that is, no additional external driving circuit is required. Thus, it reduces cost and simplifies system structure. A prototype version of the actual product is studied to measure and evaluate the key waveforms. The feasibility of the proposed system is verified based on experimental results.

  11. Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

    Directory of Open Access Journals (Sweden)

    Xiaojun Cheng

    2014-05-01

    Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

  12. Modeling of strain effects on the device behaviors of ferroelectric memory field-effect transistors

    International Nuclear Information System (INIS)

    Yang, Feng; Hu, Guangda; Wu, Weibing; Yang, Changhong; Wu, Haitao; Tang, Minghua

    2013-01-01

    The influence of strains on the channel current–gate voltage behaviors and memory windows of ferroelectric memory field-effect transistors (FeMFETs) were studied using an improved model based on the Landau–Devonshire theory. ‘Channel potential–gate voltage’ ferroelectric polarization and silicon surface potential diagrams were constructed for strained single-domain BaTiO 3 FeMFETs. The compressive strains can increase (or decrease) the amplitude of transistor currents and enlarge memory windows. However, tensile strains only decrease the maximum value of transistor currents and compress memory windows. Mismatch strains were found to have a significant influence on the electrical behaviors of the devices, therefore, they must be considered in FeMFET device designing. (fast track communication)

  13. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    Energy Technology Data Exchange (ETDEWEB)

    Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); Cao, Xiaolong [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); College of Mechanical and Electronic Engineering, Shandong University of Science and Technology, Qingdao 266590 (China); Dai, Haitao [Tianjin Key Laboratory of Low Dimensional Materials Physics and Preparing Technology, School of Science, Tianjin University, Tianjin 300072 (China); Yang, Junbo [Center of Material Science, National University of Defense Technology, Changsha 410073 (China)

    2016-07-04

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th} was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  14. Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

    International Nuclear Information System (INIS)

    Ma Da; Luo Xiao-Rong; Wei Jie; Tan Qiao; Zhou Kun; Wu Jun-Feng

    2016-01-01

    A new ultra-low specific on-resistance (R on,sp ) vertical double diffusion metal–oxide–semiconductor field-effect transistor (VDMOS) with continuous electron accumulation (CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the R on,sp but also makes the R on,sp almost independent of the n-pillar doping concentration (N n ). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the N n , and further reduces the R on,sp . Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the R on,sp by 80% compared with the conventional super-junction VDMOS (CSJ-VDMOS) at the same high breakdown voltage (BV). (paper)

  15. Long-term stability assessment of AlGaN/GaN field effect transistors modified with peptides: Device characteristics vs. surface properties

    Energy Technology Data Exchange (ETDEWEB)

    Rohrbaugh, Nathaniel; Bryan, Isaac; Bryan, Zachary; Collazo, Ramon; Ivanisevic, Albena, E-mail: ivanisevic@ncsu.edu [Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695 (United States)

    2015-09-15

    AlGaN/GaN Field Effect Transistors (FETs) are promising biosensing devices. Functionalization of these devices is explored in this study using an in situ approach with phosphoric acid etchant and a phosphonic acid derivative. Devices are terminated on peptides and soaked in water for up to 168 hrs to examine FETs for both device responses and surface chemistry changes. Measurements demonstrated threshold voltage shifting after the functionalization and soaking processes, but demonstrated stable FET behavior throughout. X-ray photoelectron spectroscopy and atomic force microscopy confirmed peptides attachment to device surfaces before and after water soaking. Results of this work point to the stability of peptide coated functionalized AlGaN/GaN devices in solution and support further research of these devices as disposable, long term, in situ biosensors.

  16. Transparent and Flexible Zinc Tin Oxide Thin Film Transistors and Inverters using Low-pressure Oxygen Annealing Process

    Science.gov (United States)

    Lee, Kimoon; Kim, Yong-Hoon; Kim, Jiwan; Oh, Min Suk

    2018-05-01

    We report on the transparent and flexible enhancement-load inverters which consist of zinc tin oxide (ZTO) thin film transistors (TFTs) fabricated at low process temperature. To control the electrical characteristics of oxide TFTs by oxygen vacancies, we applied low-pressure oxygen rapid thermal annealing (RTA) process to our devices. When we annealed the ZTO TFTs in oxygen ambient of 2 Torr, they showed better electrical characteristics than those of the devices annealed in the air ambient of 760 Torr. To realize oxide thin film transistor and simple inverter circuits on flexible substrate, we annealed the devices in O2 of 2 Torr at 150° C and could achieve the decent electrical properties. When we used transparent conductive oxide electrodes such as indium zinc oxide (IZO) and indium tin oxide (ITO), our transparent and flexible inverter showed the total transmittance of 68% in the visible range and the voltage gain of 5. And the transition voltage in voltage transfer curve was located well within the range of operation voltage.

  17. High performance printed oxide field-effect transistors processed using photonic curing

    Science.gov (United States)

    Garlapati, Suresh Kumar; Cadilha Marques, Gabriel; Gebauer, Julia Susanne; Dehm, Simone; Bruns, Michael; Winterer, Markus; Baradaran Tahoori, Mehdi; Aghassi-Hagmann, Jasmin; Hahn, Horst; Dasgupta, Subho

    2018-06-01

    Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV–visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.

  18. Microwave Enhanced Cotunneling in SET Transistors

    DEFF Research Database (Denmark)

    Manscher, Martin; Savolainen, M.; Mygind, Jesper

    2003-01-01

    Cotunneling in single electron tunneling (SET) devices is an error process which may severely limit their electronic and metrologic applications. Here is presented an experimental investigation of the theory for adiabatic enhancement of cotunneling by coherent microwaves. Cotunneling in SET...... transistors has been measured as function of temperature, gate voltage, frequency, and applied microwave power. At low temperatures and applied power levels, including also sequential tunneling, the results can be made consistent with theory using the unknown damping in the microwave line as the only free...

  19. Micro-irradiation experiments in MOS transistors using synchrotron radiation; Experiences de micro-irradiation de transistors MOS a l'aide d'un rayonnement synchrotron

    Energy Technology Data Exchange (ETDEWEB)

    Autran, J.L.; Masson, P.; Raynaud, C. [Institut National des Sciences Appliquees (INSA), 69 - Villeurbanne (France). Lab. de Physique de la Matiere; Masson, P. [Ecole Nationale Superieure d' Electronique et de Radio-Electricite, ENSERG/LPCS, 38 - Grenoble (France); Freud, N. [Institut National des Sciences Appliquees (INSA), CNDRI, 69 - Villeurbanne (France); Riekel, C. [European Synchrotron Radiation Facility ESRF, 38 - Grenoble (France)

    1999-07-01

    Spatially-resolved total-dose degradation has been performed in MOS transistors by focusing x-ray synchrotron radiation on the gate electrode with micrometer resolution. The influence of the resulting permanent degradation on device electrical properties has been analyzed using current-voltage and charge pumping measurements, in concert with optical characterization (hot-carrier luminescence) and one-dimensional device simulation. (authors)

  20. Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

    Science.gov (United States)

    Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

    2012-06-01

    High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

  1. Mapping of trap densities and hotspots in pentacene thin-film transistors by frequency-resolved scanning photoresponse microscopy.

    Science.gov (United States)

    Westermeier, Christian; Fiebig, Matthias; Nickel, Bert

    2013-10-25

    Frequency-resolved scanning photoresponse microscopy of pentacene thin-film transistors is reported. The photoresponse pattern maps the in-plane distribution of trap states which is superimposed by the level of trap filling adjusted by the gate voltage of the transistor. Local hotspots in the photoresponse map thus indicate areas of high trap densities within the pentacene thin film. © 2013 WILEY-VCH Verlag GmbH 8 Co. KGaA, Weinheim.

  2. Inkjet-Printed In-Ga-Zn Oxide Thin-Film Transistors with Laser Spike Annealing

    Science.gov (United States)

    Huang, Hang; Hu, Hailong; Zhu, Jingguang; Guo, Tailiang

    2017-07-01

    Inkjet-printed In-Ga-Zn oxide (IGZO) thin-film transistors (TFTs) have been fabricated at low temperature using laser spike annealing (LSA) treatment. Coffee-ring effects during the printing process were eliminated to form uniform IGZO films by simply increasing the concentration of solute in the ink. The impact of LSA on the TFT performance was studied. The field-effect mobility, threshold voltage, and on/off current ratio were greatly influenced by the LSA treatment. With laser scanning at 1 mm/s for 40 times, the 30-nm-thick IGZO TFT baked at 200°C showed mobility of 1.5 cm2/V s, threshold voltage of -8.5 V, and on/off current ratio >106. Our findings demonstrate the feasibility of rapid LSA treatment of low-temperature inkjet-printed oxide semiconductor transistors, being comparable to those obtained by conventional high-temperature annealing.

  3. Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

    Science.gov (United States)

    Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

    2017-05-23

    Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

  4. Phase transition transistors based on strongly-correlated materials

    Science.gov (United States)

    Nakano, Masaki

    2013-03-01

    The field-effect transistor (FET) provides electrical switching functions through linear control of the number of charges at a channel surface by external voltage. Controlling electronic phases of condensed matters in a FET geometry has long been a central issue of physical science. In particular, FET based on a strongly correlated material, namely ``Mott transistor,'' has attracted considerable interest, because it potentially provides gigantic and diverse electronic responses due to a strong interplay between charge, spin, orbital and lattice. We have investigated electric-field effects on such materials aiming at novel physical phenomena and electronic functions originating from strong correlation effects. Here we demonstrate electrical switching of bulk state of matter over the first-order metal-insulator transition. We fabricated FETs based on VO2 with use of a recently developed electric-double-layer transistor technique, and found that the electrostatically induced carriers at a channel surface drive all preexisting localized carriers of 1022 cm-3 even inside a bulk to motion, leading to bulk carrier delocalization beyond the electrostatic screening length. This non-local switching of bulk phases is achieved with just around 1 V, and moreover, a novel non-volatile memory like character emerges in a voltage-sweep measurement. These observations are apparently distinct from those of conventional FETs based on band insulators, capturing the essential feature of collective interactions in strongly correlated materials. This work was done in collaboration with K. Shibuya, D. Okuyama, T. Hatano, S. Ono, M. Kawasaki, Y. Iwasa, and Y. Tokura. This work was supported by the Japan Society for the Promotion of Science (JSAP) through its ``Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program).''

  5. Recent Advances of Solution-Processed Metal Oxide Thin-Film Transistors.

    Science.gov (United States)

    Xu, Wangying; Li, Hao; Xu, Jian-Bin; Wang, Lei

    2018-03-06

    Solution-processed metal oxide thin-film transistors (TFTs) are considered as one of the most promising transistor technologies for future large-area flexible electronics. This review surveys the recent advances in solution-based oxide TFTs, including n-type oxide semiconductors, oxide dielectrics and p-type oxide semiconductors. Firstly, we provide an introduction on oxide TFTs and the TFT configurations and operating principles. Secondly, we present the recent progress in solution-processed n-type transistors, with a special focus on low-temperature and large-area solution processed approaches as well as novel non-display applications. Thirdly, we give a detailed analysis of the state-of-the-art solution-processed oxide dielectrics for low-voltage electronics. Fourthly, we discuss the recent progress in solution-based p-type oxide semiconductors, which will enable the highly desirable future low-cost large-area complementary circuits. Finally, we draw the conclusions and outline the perspectives over the research field.

  6. Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

    Science.gov (United States)

    Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

    2018-04-01

    In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

  7. Photovoltaic Cells Improvised With Used Bipolar Junction Transistors

    International Nuclear Information System (INIS)

    Akintayo, J. A

    2002-01-01

    The understanding of the underlying principle that the solar cell consists of a p-n junction is exploited to adapt the basic NPN or PNP Bipolar Junction Transistors (BJT) to serve as solar cells. In this mode the in improvised solar cell have employed just the emitter and the base sections with an intact emitter/base junction as the active PN area. The improvised devices tested screened and sorted are wired up in strings, blocks and modules. The photovoltaic modules realised tested as close replica of solar cells with output voltage following insolation level. Further work need be done on the modules to make them generate usable levels of output voltage and current

  8. An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

    International Nuclear Information System (INIS)

    Gao Peijun; Min Hao; Oh, N J

    2009-01-01

    A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative g m -cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 μm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply. (semiconductor integrated circuits)

  9. A pattern recognition approach to transistor array parameter variance

    Science.gov (United States)

    da F. Costa, Luciano; Silva, Filipi N.; Comin, Cesar H.

    2018-06-01

    The properties of semiconductor devices, including bipolar junction transistors (BJTs), are known to vary substantially in terms of their parameters. In this work, an experimental approach, including pattern recognition concepts and methods such as principal component analysis (PCA) and linear discriminant analysis (LDA), was used to experimentally investigate the variation among BJTs belonging to integrated circuits known as transistor arrays. It was shown that a good deal of the devices variance can be captured using only two PCA axes. It was also verified that, though substantially small variation of parameters is observed for BJT from the same array, larger variation arises between BJTs from distinct arrays, suggesting the consideration of device characteristics in more critical analog designs. As a consequence of its supervised nature, LDA was able to provide a substantial separation of the BJT into clusters, corresponding to each transistor array. In addition, the LDA mapping into two dimensions revealed a clear relationship between the considered measurements. Interestingly, a specific mapping suggested by the PCA, involving the total harmonic distortion variation expressed in terms of the average voltage gain, yielded an even better separation between the transistor array clusters. All in all, this work yielded interesting results from both semiconductor engineering and pattern recognition perspectives.

  10. Unified physical DC model of staggered amorphous InGaZnO transistors

    NARCIS (Netherlands)

    Ghittorelli, M.; Torricelli, F.; Garripoli, C.; van der Steen, J.L.; Gelinck, G.H.; Cantatore, E.; Colalongo, L.; Kovács-Vajna, Z.M.

    In this paper, we propose a unified physical model of InGaZnO [amorphous indium-gallium-zinc-oxide (a-IGZO)] thin-film transistors (TFTs) accounting for both charge injection at the contact and charge transport within the channel. We extract the current-voltage characteristics of the injecting

  11. A New Method for Negative Bias Temperature Instability Assessment in P-Channel Metal Oxide Semiconductor Transistors

    Science.gov (United States)

    Djezzar, Boualem; Tahi, Hakim; Benabdelmoumene, Abdelmadjid; Chenouf, Amel; Kribes, Youcef

    2012-11-01

    In this paper, we present a new method, named on the fly oxide trap (OTFOT), to extract the bias temperature instability (BTI) in MOS transistors. The OTFOT method is based on charge pumping technique (CP) at low and high frequencies. We emphasize on the theoretical-based concept, giving a clear insight on the easy-use of the OTFOT methodology and demonstrating its viability to characterize the negative BTI (NBTI). Using alternatively high and low frequencies, OTFOT method separates the interface-traps (ΔNit) and border-trap (ΔNbt) (switching oxide-trap) densities independently and also their contributions to the threshold voltage shift (ΔVth), without needing additional methods. The experimental results, from two experimental scenarios, showing the extraction of NBTI-induced shifts caused by interface- and oxide-trap increases are also presented. In the first scenario, all stresses are performed on the same transistor. It exhibits an artifact value of exponent n. In the second scenario, each voltage stress is applied only on one transistor. Its results show an average n of 0.16, 0.05, and 0.11 for NBTI-induced ΔNit, ΔNbt, ΔVth, respectively. Therefore, OTFOT method can contribute to further understand the behavior of the NBTI degradation, especially through the threshold voltage shift components such as ΔVit and ΔVot caused by interface-trap and border-trap, respectively.

  12. Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

    Science.gov (United States)

    Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

    1994-01-01

    Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

  13. Enhanced plasma wave detection of terahertz radiation using multiple high electron-mobility transistors connected in series

    KAUST Repository

    Elkhatib, Tamer A.; Kachorovskiǐ, Valentin Yu; Stillman, William J.; Veksler, Dmitry B.; Salama, Khaled N.; Zhang, Xicheng; Shur, Michael S.

    2010-01-01

    We report on enhanced room-temperature detection of terahertz radiation by several connected field-effect transistors. For this enhanced nonresonant detection, we have designed, fabricated, and tested plasmonic structures consisting of multiple InGaAs/GaAs pseudomorphic high electron-mobility transistors connected in series. Results show a 1.63-THz response that is directly proportional to the number of detecting transistors biased by a direct drain current at the same gate-to-source bias voltages. The responsivity in the saturation regime was found to be 170 V/W with the noise equivalent power in the range of 10-7 W/Hz0.5. The experimental data are in agreement with the detection mechanism based on the rectification of overdamped plasma waves excited by terahertz radiation in the transistor channel. © 2010 IEEE.

  14. Enhanced plasma wave detection of terahertz radiation using multiple high electron-mobility transistors connected in series

    KAUST Repository

    Elkhatib, Tamer A.

    2010-02-01

    We report on enhanced room-temperature detection of terahertz radiation by several connected field-effect transistors. For this enhanced nonresonant detection, we have designed, fabricated, and tested plasmonic structures consisting of multiple InGaAs/GaAs pseudomorphic high electron-mobility transistors connected in series. Results show a 1.63-THz response that is directly proportional to the number of detecting transistors biased by a direct drain current at the same gate-to-source bias voltages. The responsivity in the saturation regime was found to be 170 V/W with the noise equivalent power in the range of 10-7 W/Hz0.5. The experimental data are in agreement with the detection mechanism based on the rectification of overdamped plasma waves excited by terahertz radiation in the transistor channel. © 2010 IEEE.

  15. The Transistor as Low Level Switch

    Energy Technology Data Exchange (ETDEWEB)

    Lyden, Anders

    1963-10-15

    The common collector transistor switch has in the on state with open emitter a certain offset voltage U{sub EK} {approx_equal} -kT/qB{sub N}. This expression is derived in a new, more physical way. It is further shown at which emitter current the current amplification factor B{sub N} should be measured to get a correct value for the above expression. The collector current I at zero collector voltage I{sub K} = I{sub 0}(exp(qU{sub E}/kT) - 1) extremely well. Substitution of I{sub EBO} and I{sub KBO} by I{sub 0} in Eber's and Moll's relations consequently improves these equations and the characteristics of the transistor switch can be better determined. At switching on and off transients appear across the switch. The influence of the 'spike' at switching off can be described by an current I{sub SPIKE} which is easy to calculate. I{sub SPIKE} is approximately dependent only on the base - emitter depletion layer capacitance and the chopper frequency f{sub 0}. Some compensated switches have lower drift than the drift in U{sub EK}. They may, for example, have a temperature drift < 0.2 {mu}V/deg C and a long time drift < 2 {mu}V/week. Some compensated switches also have I{sub SPIKE} < 10{sup -12} f{sub 0}A. The static offset current in the off state can easily be made < 10{sup -12} A.

  16. Digitally Programmable High-Q Voltage Mode Universal Filter

    Directory of Open Access Journals (Sweden)

    D. Singh

    2013-12-01

    Full Text Available A new low-voltage low-power CMOS current feedback amplifier (CFA is presented in this paper. This is used to realize a novel digitally programmable CFA (DPCFA using transistor arrays and MOS switches. The proposed realizations nearly allow rail-to-rail swing capability at all the ports. Class-AB output stage ensures low power dissipation and high current drive capability. The proposed CFA/ DPCFA operates at supply voltage of ±0.75 V and exhibits bandwidth better than 95 MHz. An application of the DPCFA to realize a novel voltage mode high-Q digitally programmable universal filter (UF is given. Performances of all the proposed circuits are verified by PSPICE simulation using TSMC 0.25μm technology parameters.

  17. Electronic system for data acquisition to study radiation effects on operating MOSFET transistors

    International Nuclear Information System (INIS)

    Alves de Oliveira, Juliano; Assis de Melo, Marco Antônio; Guazzelli da Silveira, Marcilei A.; Medina, Nilberto H.

    2014-01-01

    In this work we present the development of an acquisition system for characterizing transistors under X-ray radiation. The system is able to carry out the acquisition and to storage characteristic transistor curves. To test the acquisition system we have submitted polarized P channel MOS transistors under continuous 10-keV X-ray doses up to 1500 krad. The characterization system can operate in the saturation region or in the linear region in order to observe the behavior of the currents or voltages involved during the irradiation process. Initial tests consisted of placing the device under test (DUT) in front of the X-ray beam direction, while its drain current was constantly monitored through the prototype generated in this work, the data are stored continuously and system behavior was monitored during the test. In order to observe the behavior of the DUT during the radiation tests, we used an acquisition system that consists of an ultra-low consumption16-bit Texas Instruments MSP430 microprocessor. Preliminary results indicate linear behavior of the voltage as a function of the exposure time and fast recovery. These features may be favorable to use this device as a radiation dosimeter to monitor low rate X-ray

  18. Direct coupled amplifiers using field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Fowler, E P [Control and Instrumentation Division, Atomic Energy Establishment, Winfrith, Dorchester, Dorset (United Kingdom)

    1964-03-15

    The concept of the uni-polar field effect transistor (P.E.T.) was known before the invention of the bi-polar transistor but it is only recently that they have been made commercially. Being produced as yet only in small quantities, their price imposes a restriction on use to circuits where their peculiar properties can be exploited to the full. One such application is described here where the combination of low voltage drift and relatively low input leakage current are necessarily used together. One of the instruments used to control nuclear reactors has a logarithmic response to the mean output current from a polarised ionisation chamber. The logarithmic signal is then differentiated electrically, the result being displayed on a meter calibrated to show the reactor divergence or doubling time. If displayed in doubling time the scale is calibrated reciprocally. Because of the wide range obtained in the logarithmic section and the limited supply voltage, an output of 1 volt per decade change in ionisation current is used. Differentiating this gives a current of 1.5 x 10{sup -8} A for p.s.D. (20 sec. doubling time) in the differentiating amplifier. To overcome some of the problems of noise due to statistical variations in input current, the circuit design necessitates a resistive path to ground at the amplifier input of 20 M.ohms. A schematic diagram is shown. 1. It is evident that a zero drift of 1% can be caused by a leakage current of 1.5 x 10{sup -10} A or an offset voltage of 3 mV at the amplifier input. Although the presently used electrometer valve is satisfactory from the point of view of grid current, there have been sudden changes in grid to grid voltage (the valve is a double triode) of up to 10 m.V. It has been found that a pair of F.E.T's. can be used to replace the electrometer valve so long as care is taken in correct balance of the two devices. An investigation has been made into the characteristics of some fourteen devices to see whether those with

  19. Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

    Science.gov (United States)

    Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

    2018-01-01

    Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

    International Nuclear Information System (INIS)

    Tsai, Ming-Yen; Chang, Ting-Chang; Chu, Ann-Kuo; Hsieh, Tien-Yu; Lin, Kun-Yao; Wu, Yi-Chun; Huang, Shih-Feng; Chiang, Cheng-Lung; Chen, Po-Lin; Lai, Tzu-Chieh; Lo, Chang-Cheng; Lien, Alan

    2014-01-01

    This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device. - Highlights: • There is abnormal V T shift induced by illuminated gate bias stress in a-Si:H thin film transistors. • Electron–hole pair is generated via trap-assisted photoexcitation. • Abnormal transconductance hump is induced by the leakage current from back channel. • Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate

  1. In-situ SiN{sub x}/InN structures for InN field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Zervos, Ch., E-mail: hzervos@physics.uoc.gr; Georgakilas, A. [Microelectronics Research Group (MRG), Institute of Electronic Structure and Laser (IESL), Foundation for Research and Technology-Hellas - FORTH, P.O. Box 1385, GR-70013 Heraklion, Crete (Greece); Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete (Greece); Adikimenakis, A.; Kostopoulos, A.; Kayambaki, M.; Tsagaraki, K.; Konstantinidis, G. [Microelectronics Research Group (MRG), Institute of Electronic Structure and Laser (IESL), Foundation for Research and Technology-Hellas - FORTH, P.O. Box 1385, GR-70013 Heraklion, Crete (Greece); Beleniotis, P. [Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete (Greece)

    2016-04-04

    Critical aspects of InN channel field-effect transistors (FETs) have been investigated. SiN{sub x} dielectric layers were deposited in-situ, in the molecular beam epitaxy system, on the surface of 2 nm InN layers grown on GaN (0001) buffer layers. Metal-insulator-semiconductor Ni/SiN{sub x}/InN capacitors were analyzed by capacitance-voltage (C-V) and current-voltage measurements and were used as gates in InN FET transistors (MISFETs). Comparison of the experimental C-V results with self-consistent Schrödinger-Poisson calculations indicates the presence of a positive charge at the SiN{sub x}/InN interface of Q{sub if} ≈ 4.4 – 4.8 × 10{sup 13 }cm{sup −2}, assuming complete InN strain relaxation. Operation of InN MISFETs was demonstrated, but their performance was limited by a catastrophic breakdown at drain-source voltages above 2.5–3.0 V, the low electron mobility, and high series resistances of the structures.

  2. Terminal load response law of coaxial cable to continuous wave electromagnetic irradiation

    International Nuclear Information System (INIS)

    Pan Xiaodong; Wei Guanghui; Li Xinfeng; Lu Xinfu

    2012-01-01

    In order to study the coupling response law of continuous wave electromagnetic irradiation to coaxial cable, the typical RF coaxial cable is selected as the object under test. The equipment or subsystem connected by coaxial cable is equivalent to a lumped load. Continuous wave irradiation effect experiments under different conditions are carried out to analyze the terminal load response law of coaxial cable. The results indicate that the coaxial cable has a frequency selecting characteristic under electromagnetic irradiation, and the terminal load response voltage peak appears at a series of discrete frequency points where the test cable's relative lengths equal to semi-integers. When the coaxial cable is irradiated by continuous wave, the induced sheath current converts to the differential-mode induced voltage between inner conductor and shielding layer through transfer impedance, and the internal resistance of induced voltage source is the characteristic impedance of the coaxial cable. The change in terminal load value has no influence on the response curve. The voltages on the terminal load and the internal resistance of equivalent induced voltage source obey the principle of voltage division. Moreover, when the sheath current on the coaxial cable is in resonance, the distributed induced voltage between adjacent current nodes is in the same polarity, which can be equivalent to a single induced voltage source. The induced voltage source which is adjacent to the terminal load plays the leading role in the irradiation response process. (authors)

  3. Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

    Science.gov (United States)

    Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

    2018-05-01

    We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

  4. Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

    Science.gov (United States)

    Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

    2017-09-01

    Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

  5. Carbon nanotube transistors scaled to a 40-nanometer footprint.

    Science.gov (United States)

    Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

    2017-06-30

    The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

  6. Anomalous high photoconductivity in short channel indium-zinc-oxide photo-transistors

    International Nuclear Information System (INIS)

    Choi, Hyun-Sik; Jeon, Sanghun

    2015-01-01

    Upon light exposure, an indium-zinc-oxide (IZO) thin-film transistor (TFT) presents higher photoconductivity by several orders of magnitude at the negative gate bias region. Among various device geometrical factors, scaling down the channel length of the photo-transistor results in an anomalous increase in photoconductivity. To probe the origin of this high photoconductivity in short-channel device, we measured transient current, current–voltage, and capacitance–voltage characteristics of IZO–TFTs with various channel lengths and widths before and after illumination. Under the illumination, the equilibrium potential region which lies far from front interface exists only in short-channel devices, forming the un-depleted conducting back channel. This region plays an important role in carrier transport under the illumination, leading to high photoconductivity in short-channel devices. Photon exposure coupled with gate-modulated band bending for short-channel devices leads to the accumulation of V o ++ at the front channel and screening negative gate bias, thereby generating high current flow in the un-depleted back-channel region

  7. Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

    Science.gov (United States)

    Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

    2012-01-15

    Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

  8. The effect of random dopant fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

    International Nuclear Information System (INIS)

    Rezapour, Arash; Rezapour, Pegah

    2015-01-01

    We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation (10000 randomizations). With this simulation, we could study the effects of varying the dimensions (length and width), and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region (off) and overthreshold (on). It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion (compared with that of the subthreshold). These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel. (paper)

  9. Raman imaging of carrier distribution in the channel of an ionic liquid-gated transistor fabricated with regioregular poly(3-hexylthiophene)

    Science.gov (United States)

    Wada, Y.; Enokida, I.; Yamamoto, J.; Furukawa, Y.

    2018-05-01

    Raman images of carriers (positive polarons) at the channel of an ionic liquid-gated transistor (ILGT) fabricated with regioregular poly(3-hexylthiophene) (P3HT) have been measured with excitation at 785 nm. The observed spectra indicate that carriers generated are positive polarons. The intensities of the 1415 cm-1 band attributed to polarons in the P3HT channel were plotted as Raman images; they showed the carrier density distribution. When the source-drain voltage VD is lower than the source-gate voltage VG (linear region), the carrier density was uniform. When VD is nearly equal to VG (saturation region), a negative carrier density gradient from the source electrode towards the drain electrode was observed. This carrier density distribution is associated with the observed current-voltage characteristics, which is not consistent with the "pinch-off" theory of inorganic semiconductor transistors.

  10. A Droop Line Tracking Control for Multi-terminal VSC-HVDC Transmission System

    DEFF Research Database (Denmark)

    Irnawan, Roni; Silva, Filipe Miguel Faria da; Bak, Claus Leth

    2018-01-01

    Generally, a voltage-sourced converter (VSC) within a multi-terminal HVDC (MTDC) system can be operated either in constant DC voltage, constant flow (AC active power or DC current) or DC voltage droop control. These control modes can be easily represented as the droop characteristic line with dif......Generally, a voltage-sourced converter (VSC) within a multi-terminal HVDC (MTDC) system can be operated either in constant DC voltage, constant flow (AC active power or DC current) or DC voltage droop control. These control modes can be easily represented as the droop characteristic line...

  11. The effects of gamma irradiation on neutron displacement sensitivity of lateral PNP bipolar transistors

    International Nuclear Information System (INIS)

    Wang, Chenhui; Chen, Wei; Liu, Yan; Jin, Xiaoming; Yang, Shanchao; Qi, Chao

    2016-01-01

    The effects of gamma irradiation on neutron displacement sensitivity of four types of lateral PNP bipolar transistors (LPNPs) with different neutral base widths, emitter widths and the doping concentrations of the epitaxial base region are studied. The physical mechanisms of the effects are explored by defect analysis using deep level transient spectroscopy (DLTS) techniques and numerical simulations of recombination process in the base region of the lateral PNP bipolar transistors, and are verified by the experiments on gate-controlled lateral PNP bipolar transistors (GCLPNPs) manufactured in the identical commercial bipolar process with different gate bias voltage. The results indicate that gamma irradiation increases neutron displacement damage sensitivity of lateral PNP bipolar transistors and the mechanism of this phenomenon is that positive charge induced by gamma irradiation enhances the recombination process in the defects induced by neutrons in the base region, leading to larger recombination component of base current and greater gain degradation.

  12. The effects of gamma irradiation on neutron displacement sensitivity of lateral PNP bipolar transistors

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Chenhui, E-mail: wangchenhui@nint.ac.cn; Chen, Wei; Liu, Yan; Jin, Xiaoming; Yang, Shanchao; Qi, Chao

    2016-09-21

    The effects of gamma irradiation on neutron displacement sensitivity of four types of lateral PNP bipolar transistors (LPNPs) with different neutral base widths, emitter widths and the doping concentrations of the epitaxial base region are studied. The physical mechanisms of the effects are explored by defect analysis using deep level transient spectroscopy (DLTS) techniques and numerical simulations of recombination process in the base region of the lateral PNP bipolar transistors, and are verified by the experiments on gate-controlled lateral PNP bipolar transistors (GCLPNPs) manufactured in the identical commercial bipolar process with different gate bias voltage. The results indicate that gamma irradiation increases neutron displacement damage sensitivity of lateral PNP bipolar transistors and the mechanism of this phenomenon is that positive charge induced by gamma irradiation enhances the recombination process in the defects induced by neutrons in the base region, leading to larger recombination component of base current and greater gain degradation.

  13. Optimum voltage of auxiliary systems for thermal and nuclear power plants

    International Nuclear Information System (INIS)

    Tokumitsu, Iwao; Segawa, Motomichi

    1979-01-01

    In the power plants in Japan, their unit power output has been greatly enhanced since the introduction of new powerful thermal power plants from 1950's to 1960's. In both thermal and nuclear power plants, 1,000 MW machines have been already in operation. The increase of unit power output results in the increase of in-plant load capacity. Of these the voltage adopted for in-plant low voltage systems is now mainly 440 V at load terminals, and the voltage for in-plant high voltage systems has been changing to 6 kV level via 3 kV and 4 kV levels. As plant capacity increases, the load of low voltage systems significantly increases, and it is required to raise the voltage of 400 V level. By the way, the low voltage in AC is specified to be not higher than 600 V. This makes the change within the above range comparatively easy. Considering these conditions, it is recommended to change the voltage for low voltage systems to 575 V at power source terminals and 550 V at load terminals. Some merits in constructing power systems and in economy by raising the voltage were examined. Though demerits are also found, they are only about 15% of total merits. The most advantageous point in raising the voltage is to be capable of increasing the supplying range to low voltage system loads. (Wakatsuki, Y.)

  14. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    Science.gov (United States)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  15. Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

    Energy Technology Data Exchange (ETDEWEB)

    Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)

    2013-12-23

    Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

  16. Performance enhancement of a heterojunction bipolar transistor (HBT) by two-step passivation

    International Nuclear Information System (INIS)

    Fu, S.-I.; Lai, P.-H.; Tsai, Y.-Y.; Hung, C.-W.; Yen, C.-H.; Cheng, S.-Y.; Liu, W.-C.

    2006-01-01

    An interesting two-step passivation (with ledge structure and sulphide based chemical treatment) on base surface, for the first time, is demonstrated to study the temperature-dependent DC characteristics and noise performance of an InGaP/GaAs heterojunction bipolar transistor (HBT). Improved transistor behaviors on maximum current gain β max , offset voltage ΔV CE , and emitter size effect are obtained by using the two-step passivation. Moreover, the device with the two-step passivation exhibits relatively temperature-independent and improved thermal stable performances as the temperature is increased. Therefore, the two-step passivationed device can be used for high-temperature and low-power electronics applications

  17. Modeling and simulation of 4H-SiC field effect transistor

    Science.gov (United States)

    Pedryc, A.; Martychowiec, A.; Kociubiński, A.

    2017-08-01

    This paper presents the technological issue of silicon carbide MOSFET design. Through the use of simulations of silicon carbide transistor, the influence of the different the technological parameters are described and discussed. MOSFET transistor was performed in Silvaco TCAD using technology elaborated at Lublin University of Technology. The most important parameters related to ion implantation, which was used in p-i-n photodiode technology. The electrical simulations were performed, transfer and output characteristics for different values of technological parameters were generated - influence of gate oxide thickness on threshold voltage and influence of channel length modulation were checked. The results of simulations as well as transfer and output characteristics allowed to select optimal parameters between expected device working and available technology - gate oxide thickness and transistor channel length were established. This work was in fact carried out to increase our understanding of the device characteristics so as to allow the design of new SiC circuits which could meet the stressful requirements of ultraviolet detector systems.

  18. Carbon nanotube transistors with graphene oxide films as gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

  19. Enhanced low dose rate sensitivity (ELDRS) in a voltage comparator which only utilizes complementary vertical NPN and PNP transistors

    International Nuclear Information System (INIS)

    Krieg, J.F.; Titus, J.L.; Emily, D.; Gehlhausen, M.; Swonger, J.; Platteter, D.

    1999-01-01

    For the first time, enhanced low dose rate sensitivity (ELDRS) is reported in a vertical bipolar process. A radiation hardness assurance (RHA) test method was successfully demonstrated on a linear circuit, the HS139RH quad comparator, and its discrete transistor elements. This circuit only uses vertical NPN and PNP transistors. Radiation tests on the HS139RH were performed at 25 C using dose rates of 50 rd(Si)/s, 100 mrd(Si)/s and 10 mrd(Si)/s, and at 100 C using a dose rate of 10 rd(Si)/s. Tests at dose rates of 50 rd(Si)/s at 25 C and 10 rd(Si)/s at 100 C were performed on discrete vertical NPN and PNP transistor elements which comprise the HS139RH. Transistor and circuit responses were evaluated. The die's passivation overcoat layers were varied to examine the effect of removing a nitride layer and thinning a deposited SiO 2 (silox) layer

  20. AlN metal-semiconductor field-effect transistors using Si-ion implantation

    Science.gov (United States)

    Okumura, Hironori; Suihkonen, Sami; Lemettinen, Jori; Uedono, Akira; Zhang, Yuhao; Piedra, Daniel; Palacios, Tomás

    2018-04-01

    We report on the electrical characterization of Si-ion implanted AlN layers and the first demonstration of metal-semiconductor field-effect transistors (MESFETs) with an ion-implanted AlN channel. The ion-implanted AlN layers with Si dose of 5 × 1014 cm-2 exhibit n-type characteristics after thermal annealing at 1230 °C. The ion-implanted AlN MESFETs provide good drain current saturation and stable pinch-off operation even at 250 °C. The off-state breakdown voltage is 2370 V for drain-to-gate spacing of 25 µm. These results show the great potential of AlN-channel transistors for high-temperature and high-power applications.

  1. Lateral and Vertical Organic Transistors

    Science.gov (United States)

    Al-Shadeedi, Akram

    An extensive study has been performed to provide a better understanding of the operation principles of doped organic field-effect transistors (OFETs), organic p-i-n diodes, Schottky diodes, and organic permeable base transistors (OPBTs). This has been accomplished by a combination of electrical and structural characterization of these devices. The discussion of doped OFETs focuses on the shift of the threshold voltage due to increased doping concentrations and the generation and transport of minority charge carriers. Doping of pentacene OFETs is achieved by co-evaporation of pentacene with the n-dopant W2(hpp)4. It is found that pentacene thin film are efficiently doped and that a conductivity in the range of 2.6 x 10-6 S cm-1 for 1 wt% to 2.5 x 10-4 S cm-1 for 16 wt% is reached. It is shown that n-doped OFET consisting of an n-doped channel and n-doped contacts are ambipolar. This behavior is surprising, as n-doping the contacts should suppress direct injection of minority charge carriers (holes). It was proposed that minority charge carrier injection and hence the ambipolar characteristic of n-doped OFETs can be explained by Zener tunneling inside the intrinsic pentacene layer underneath the drain electrode. It is shown that the electric field in this layer is indeed in the range of the breakdown field of pentacene based p-i-n Zener homodiodes. Doping the channel has a profound influence on the onset voltage of minority (hole) conduction. The onset voltage can be shifted by lightly n-doping the channel. The shift of onset voltage can be explained by two mechanisms: first, due to a larger voltage that has to be applied to the gate in order to fully deplete the n-doped layer. Second, it can be attributed to an increase in hole trapping by inactive dopants. Moreover, it has been shown that the threshold voltage of majority (electron) conduction is shifted by an increase in the doping concentration, and that the ambipolar OFETs can be turned into unipolar OFETs at

  2. A disorder induced field effect transistor in bilayer and trilayer graphene

    International Nuclear Information System (INIS)

    Xu Dongwei; Liu Haiwen; Sacksteder IV, Vincent; Sun Qingfeng; Song Juntao; Jiang Hua; Xie, X C

    2013-01-01

    We propose using disorder to produce a field effect transistor (FET) in biased bilayer and trilayer graphene. Modulation of the bias voltage can produce large variations in the conductance when the effects of disorder are confined to only one of the graphene layers. This effect is based on the ability of the bias voltage to select which of the graphene layers carries current, and is not tied to the presence of a gap in the density of states. In particular, we demonstrate this effect in models of gapless ABA-stacked trilayer graphene, gapped ABC-stacked trilayer graphene and gapped bilayer graphene. (paper)

  3. Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

    Science.gov (United States)

    Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

    2014-10-08

    Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

  4. Photo-excited charge collection spectroscopy probing the traps in field-effect transistors

    CERN Document Server

    Im, Seongil; Kim, Jae Hoon

    2013-01-01

    Solid state field-effect devices such as organic and inorganic-channel thin-film transistors (TFTs) have been expected to promote advances in display and sensor electronics. The operational stabilities of such TFTs are thus important, strongly depending on the nature and density of charge traps present at the channel/dielectric interface or in the thin-film channel itself. This book contains how to characterize these traps, starting from the device physics of field-effect transistor (FET). Unlike conventional analysis techniques which are away from well-resolving spectral results, newly-introduced photo-excited charge-collection spectroscopy (PECCS) utilizes the photo-induced threshold voltage response from any type of working transistor devices with organic-, inorganic-, and even nano-channels, directly probing on the traps. So, our technique PECCS has been discussed through more than ten refereed-journal papers in the fields of device electronics, applied physics, applied chemistry, nano-devices and materia...

  5. Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

    Science.gov (United States)

    Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

    2014-01-01

    Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

  6. Frequency Response of Graphene Electrolyte-Gated Field-Effect Transistors

    Directory of Open Access Journals (Sweden)

    Charles Mackin

    2018-02-01

    Full Text Available This work develops the first frequency-dependent small-signal model for graphene electrolyte-gated field-effect transistors (EGFETs. Graphene EGFETs are microfabricated to measure intrinsic voltage gain, frequency response, and to develop a frequency-dependent small-signal model. The transfer function of the graphene EGFET small-signal model is found to contain a unique pole due to a resistive element, which stems from electrolyte gating. Intrinsic voltage gain, cutoff frequency, and transition frequency for the microfabricated graphene EGFETs are approximately 3.1 V/V, 1.9 kHz, and 6.9 kHz, respectively. This work marks a critical step in the development of high-speed chemical and biological sensors using graphene EGFETs.

  7. Correlation between the thermal performance and the microstructure of the material used in medium and high voltage transformer terminals

    Science.gov (United States)

    Salas, Y. J.; Vera-Monroy, S. P.; Mejia-Camacho, A.; Rivera, W.

    2017-12-01

    In Colombia, energy companies neglect the distribution that represents the main and most valuable process, presenting shortcomings in prevention and forecasting programs, using contractors who perform corrective maintenance of the components without guaranteeing the quality and performance of the materials. Within the process, the terminals determine the effective connection between the voltage line and the transformer, which have faults that are evidenced by the thermal deterioration of the material. In this work, a diagnosis of the thermal performance of these components was carried out and it was correlated with the microstructure, observing variations of the working temperature, with a thermography camera, for three types of terminals, which were classified by X-ray fluorescence in brass Z20, Z40 and Z60, and for two types of connection, copper and aluminium. The microstructure results showed that copper is the conductor that degrades the terminals faster, evidencing cracking of the material; on the other hand, the Z40 brass was the most stable with the lowest temperature variation regardless of the conductor diameter; however, in all cases the behaviour of higher temperature to lower calibre is satisfied.

  8. Quantum ballistic transistor and low noise HEMT for cryo-electronics lower than 4.2 K; Transistor balistique quantique et HEMT bas-bruit pour la cryoelectronique inferieure a 4.2 K

    Energy Technology Data Exchange (ETDEWEB)

    Gremion, E

    2008-01-15

    Next generations of cryo-detectors, widely used in physics of particles and physics of universe, will need in the future high-performance cryo-electronics less noisy and closer to the detector. Within this context, this work investigates properties of two dimensional electron gas GaAlAs/GaAs by studying two components, quantum point contact (QPC) and high electron mobility transistor (HEMT). Thanks to quantized conductance steps in QPC, we have realized a quantum ballistic transistor (voltage gain higher than 1), a new component useful for cryo-electronics thanks to its operating temperature and weak power consumption (about 1 nW). Moreover, the very low capacity of this component leads to promising performances for multiplexing low temperature bolometer dedicated to millimetric astronomy. The second study focused on HEMT with very high quality 2DEG. At 4.2 K, a voltage gain higher than 20 can be obtained with a very low power dissipation of less than 100 {mu}W. Under the above experimental conditions, an equivalent input voltage noise of 1.2 nV/{radical}(Hz) at 1 kHz and 0.12 nV/{radical}(Hz) at 100 kHz has been reached. According to the Hooge formula, these noise performances are get by increasing gate capacity estimated to 60 pF. (author)

  9. Flexible Textile-Based Organic Transistors Using Graphene/Ag Nanoparticle Electrode

    Science.gov (United States)

    Kim, Youn; Kwon, Yeon Ju; Lee, Kang Eun; Oh, Youngseok; Um, Moon-Kwang; Seong, Dong Gi; Lee, Jea Uk

    2016-01-01

    Highly flexible and electrically-conductive multifunctional textiles are desirable for use in wearable electronic applications. In this study, we fabricated multifunctional textile composites by vacuum filtration and wet-transfer of graphene oxide films on a flexible polyethylene terephthalate (PET) textile in association with embedding Ag nanoparticles (AgNPs) to improve the electrical conductivity. A flexible organic transistor can be developed by direct transfer of a dielectric/semiconducting double layer on the graphene/AgNP textile composite, where the textile composite was used as both flexible substrate and conductive gate electrode. The thermal treatment of a textile-based transistor enhanced the electrical performance (mobility = 7.2 cm2·V−1·s−1, on/off current ratio = 4 × 105, and threshold voltage = −1.1 V) due to the improvement of interfacial properties between the conductive textile electrode and the ion-gel dielectric layer. Furthermore, the textile transistors exhibited highly stable device performance under extended bending conditions (with a bending radius down to 3 mm and repeated tests over 1000 cycles). We believe that our simple methods for the fabrication of graphene/AgNP textile composite for use in textile-type transistors can potentially be applied to the development of flexible large-area electronic clothes. PMID:28335276

  10. Resonant Full-Bridge Synchronous Rectifier Utilizing 15 V GaN Transistors for Wireless Power Transfer Applications Following AirFuel Standard Operating at 6.78 MHz

    DEFF Research Database (Denmark)

    Jensen, Christopher Have Kiaerskou; Spliid, Frederik Monrad; Hertel, Jens Christian

    2018-01-01

    , this work uses low voltage GaN transistors on the receiver (Rx) side to allow synchronous rectification and soft switching, thereby achieving high efficiency. After analyzing adequate Class-DE rectifier topologies, a ClassDE full-bridge 5 W rectifier using 15 V GaN transistors are designed and implemented...

  11. On the Bipolar DC Flow Field-Effect-Transistor for Multifunctional Sample Handing in Microfluidics: A Theoretical Analysis under the Debye–Huckel Limit

    Directory of Open Access Journals (Sweden)

    Weiyu Liu

    2018-02-01

    Full Text Available We present herein a novel method of bipolar field-effect control on DC electroosmosis (DCEO from a physical point of view, in the context of an intelligent and robust operation tool for stratified laminar streams in microscale systems. In this unique design of the DC flow field-effect-transistor (DC-FFET, a pair of face-to-face external gate terminals are imposed with opposite gate-voltage polarities. Diffuse-charge dynamics induces heteropolar Debye screening charge within the diffuse double layer adjacent to the face-to-face oppositely-polarized gates, respectively. A background electric field is applied across the source-drain terminal and forces the face-to-face counterionic charge of reversed polarities into induced-charge electroosmotic (ICEO vortex flow in the lateral direction. The chaotic turbulence of the transverse ICEO whirlpool interacts actively with the conventional plug flow of DCEO, giving rise to twisted streamlines for simultaneous DCEO pumping and ICEO mixing of fluid samples along the channel length direction. A mathematical model in thin-layer approximation and the low-voltage limit is subsequently established to test the feasibility of the bipolar DC-FFET configuration in electrokinetic manipulation of fluids at the micrometer dimension. According to our simulation analysis, an integrated device design with two sets of side-by-side, but upside-down gate electrode pair exhibits outstanding performance in electroconvective pumping and mixing even without any externally-applied pressure difference. Moreover, a paradigm of a microdevice for fully electrokinetics-driven analyte treatment is established with an array of reversed bipolar gate-terminal pairs arranged on top of the dielectric membrane along the channel length direction, from which we can obtain almost a perfect liquid mixture by using a smaller magnitude of gate voltages for causing less detrimental effects at a small Dukhin number. Sustained by theoretical

  12. Demonstration of InAlN/AlGaN high electron mobility transistors with an enhanced breakdown voltage by pulsed metal organic chemical vapor deposition

    Energy Technology Data Exchange (ETDEWEB)

    Xue, JunShuai, E-mail: junshuaixue@hotmail.com; Zhang, JinCheng; Hao, Yue [Key Laboratory of Wide Band Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2016-01-04

    In this work, InAlN/AlGaN heterostructures employing wider bandgap AlGaN instead of conventional GaN channel were grown on sapphire substrate by pulsed metal organic chemical vapor deposition, where the nominal Al composition in InAlN barrier and AlGaN channel were chosen to be 83% and 5%, respectively, to achieve close lattice-matched condition. An electron mobility of 511 cm{sup 2}/V s along with a sheet carrier density of 1.88 × 10{sup 13 }cm{sup −2} were revealed in the prepared heterostructures, both of which were lower compared with lattice-matched InAlN/GaN due to increased intrinsic alloy disorder scattering resulting from AlGaN channel and compressively piezoelectric polarization in barrier, respectively. While the high electron mobility transistor (HEMT) processed on these structures not only exhibited a sufficiently high drain output current density of 854 mA/mm but also demonstrated a significantly enhanced breakdown voltage of 87 V, which is twice higher than that of reported InAlN/GaN HEMT with the same device dimension, potential characteristics for high-voltage operation of GaN-based electronic devices.

  13. Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Soochow University, Suzhou, Jiangsu 215123 (China)

    2016-07-11

    High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

  14. Two-stage unified stretched-exponential model for time-dependence of threshold voltage shift under positive-bias-stresses in amorphous indium-gallium-zinc oxide thin-film transistors

    Science.gov (United States)

    Jeong, Chan-Yong; Kim, Hee-Joong; Hong, Sae-Young; Song, Sang-Hun; Kwon, Hyuck-In

    2017-08-01

    In this study, we show that the two-stage unified stretched-exponential model can more exactly describe the time-dependence of threshold voltage shift (ΔV TH) under long-term positive-bias-stresses compared to the traditional stretched-exponential model in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). ΔV TH is mainly dominated by electron trapping at short stress times, and the contribution of trap state generation becomes significant with an increase in the stress time. The two-stage unified stretched-exponential model can provide useful information not only for evaluating the long-term electrical stability and lifetime of the a-IGZO TFT but also for understanding the stress-induced degradation mechanism in a-IGZO TFTs.

  15. Fabrication of enhancement-mode AlGaN/GaN high electron mobility transistors using double plasma treatment

    Energy Technology Data Exchange (ETDEWEB)

    Lim, Jong-Won, E-mail: jwlim@etri.re.kr [Photonic/Wireless Convergence Components Dept., IT Materials and Components Lab., Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Ahn, Ho-Kyun; Kim, Seong-il; Kang, Dong-Min; Lee, Jong-Min; Min, Byoung-Gue; Lee, Sang-Heung; Yoon, Hyung-Sup; Ju, Chull-Won; Kim, Haecheon; Mun, Jae-Kyoung; Nam, Eun-Soo [Photonic/Wireless Convergence Components Dept., IT Materials and Components Lab., Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Park, Hyung-Moo [Photonic/Wireless Convergence Components Dept., IT Materials and Components Lab., Electronics and Telecommunications Research Institute, Daejeon 305-700 (Korea, Republic of); Division of Electronics and Electrical Engineering, Dongguk University, Seoul (Korea, Republic of)

    2013-11-29

    We report the fabrication and DC and microwave characteristics of 0.5 μm AlGaN/GaN high electron mobility transistors using double plasma treatment process. Silicon nitride layers 700 and 150 Å thick were deposited by plasma-enhanced chemical vapor deposition at 260 °C to protect the device and to define the gate footprint. The double plasma process was carried out by two different etching techniques to obtain enhancement-mode AlGaN/GaN high electron mobility transistors with 0.5 μm gate lengths. The enhancement-mode AlGaN/GaN high electron mobility transistor was prepared in parallel to the depletion-mode AlGaN/GaN high electron mobility transistor device on one wafer. Completed double plasma treated 0.5 μm AlGaN/GaN high electron mobility transistor devices fabricated by dry etching exhibited a peak transconductance, gm, of 330 mS/mm, a breakdown voltage of 115 V, a current-gain cutoff frequency (f{sub T}) of 18 GHz, and a maximum oscillation frequency (f{sub max}) of 66 GHz. - Highlights: • The double plasma process was carried out by two different etching techniques. • Double plasma treated device exhibited a transconductance of 330 mS/mm. • Completed 0.5 μm gate device exhibited a current-gain cutoff frequency of 18 GHz. • The off-state breakdown voltage of 115 V for 0.5 μm gate device was obtained. • Continuous-wave output power density of 4.3 W/mm was obtained at 2.4 GHz.

  16. Fabrication of enhancement-mode AlGaN/GaN high electron mobility transistors using double plasma treatment

    International Nuclear Information System (INIS)

    Lim, Jong-Won; Ahn, Ho-Kyun; Kim, Seong-il; Kang, Dong-Min; Lee, Jong-Min; Min, Byoung-Gue; Lee, Sang-Heung; Yoon, Hyung-Sup; Ju, Chull-Won; Kim, Haecheon; Mun, Jae-Kyoung; Nam, Eun-Soo; Park, Hyung-Moo

    2013-01-01

    We report the fabrication and DC and microwave characteristics of 0.5 μm AlGaN/GaN high electron mobility transistors using double plasma treatment process. Silicon nitride layers 700 and 150 Å thick were deposited by plasma-enhanced chemical vapor deposition at 260 °C to protect the device and to define the gate footprint. The double plasma process was carried out by two different etching techniques to obtain enhancement-mode AlGaN/GaN high electron mobility transistors with 0.5 μm gate lengths. The enhancement-mode AlGaN/GaN high electron mobility transistor was prepared in parallel to the depletion-mode AlGaN/GaN high electron mobility transistor device on one wafer. Completed double plasma treated 0.5 μm AlGaN/GaN high electron mobility transistor devices fabricated by dry etching exhibited a peak transconductance, gm, of 330 mS/mm, a breakdown voltage of 115 V, a current-gain cutoff frequency (f T ) of 18 GHz, and a maximum oscillation frequency (f max ) of 66 GHz. - Highlights: • The double plasma process was carried out by two different etching techniques. • Double plasma treated device exhibited a transconductance of 330 mS/mm. • Completed 0.5 μm gate device exhibited a current-gain cutoff frequency of 18 GHz. • The off-state breakdown voltage of 115 V for 0.5 μm gate device was obtained. • Continuous-wave output power density of 4.3 W/mm was obtained at 2.4 GHz

  17. A generic inertia emulation controller for multi-terminal VSC-HVDC systems

    DEFF Research Database (Denmark)

    Zhu, Jiebei; Guerrero, Josep M.; Booth, Campbell

    2013-01-01

    A generic Inertia Emulation Controller (INEC) for Multi-Terminal Voltage-source-converter based HVDC (VSC-MTDC) is proposed in this paper. The proposed INEC can be incorporated in any grid-side-voltage-source-converter (GVSC) station, allowing the MTDC terminal to contribute an inertial response...

  18. Novel organic semiconductors and dielectric materials for high performance and low-voltage organic thin-film transistors

    Science.gov (United States)

    Yoon, Myung-Han

    Two novel classes of organic semiconductors based on perfluoroarene/arene-modified oligothiophenes and perfluoroacyl/acyl-derivatized quaterthiophens are developed. The frontier molecular orbital energies of these compounds are studied by optical spectroscopy and electrochemistry while solid-state/film properties are investigated by thermal analysis, x-ray diffraction, and scanning electron microscopy. Organic thin film transistors (OTFTs) performance parameters are discussed in terms of the interplay between semiconductor molecular energetics and film morphologies/microstructures. For perfluoroarene-thiophene oligomer systems, majority charge carrier type and mobility exhibit a strong correlation with the regiochemistry of perfluoroarene incorporation. In quaterthiophene-based semiconductors, carbonyl-functionalization allows tuning of the majority carrier type from p-type to ambipolar and to n-type. In situ conversion of a p-type semiconducting film to n-type film is also demonstrated. Very thin self-assembled or spin-on organic dielectric films have been integrated into OTFTs to achieve 1 - 2 V operating voltages. These new dielectrics are deposited either by layer-by-layer solution phase deposition of molecular precursors or by spin-coating a mixture of polymer and crosslinker, resulting in smooth and virtually pinhole-free thin films having exceptionally large capacitances (300--700 nF/cm2) and low leakage currents (10 -9 - 10-7 A/cm2). These organic dielectrics are compatible with various vapor- or solution-deposited p- and n-channel organic semiconductors. Furthermore, it is demonstrated that spin-on crosslinked-polymer-blend dielectrics can be employed for large-area/patterned electronics, and complementary inverters. A general approach for probing semiconductor-dielectric interface effects on OTFT performance parameters using bilayer gate dielectrics is presented. Organic semiconductors having p-, n-type, or ambipolar majority charge carriers are grown on

  19. Ferroelectric transistors with monolayer molybdenum disulfide and ultra-thin aluminum-doped hafnium oxide

    Science.gov (United States)

    Yap, Wui Chung; Jiang, Hao; Liu, Jialun; Xia, Qiangfei; Zhu, Wenjuan

    2017-07-01

    In this letter, we demonstrate ferroelectric memory devices with monolayer molybdenum disulfide (MoS2) as the channel material and aluminum (Al)-doped hafnium oxide (HfO2) as the ferroelectric gate dielectric. Metal-ferroelectric-metal capacitors with 16 nm thick Al-doped HfO2 are fabricated, and a remnant polarization of 3 μC/cm2 under a program/erase voltage of 5 V is observed. The capability of potential 10 years data retention was estimated using extrapolation of the experimental data. Ferroelectric transistors based on embedded ferroelectric HfO2 and MoS2 grown by chemical vapor deposition are fabricated. Clockwise hysteresis is observed at low program/erase voltages due to slow bulk traps located near the 2D/dielectric interface, while counterclockwise hysteresis is observed at high program/erase voltages due to ferroelectric polarization. In addition, the endurances of the devices are tested, and the effects associated with ferroelectric materials, such as the wake-up effect and polarization fatigue, are observed. Reliable writing/reading in MoS2/Al-doped HfO2 ferroelectric transistors over 2 × 104 cycles is achieved. This research can potentially lead to advances of two-dimensional (2D) materials in low-power logic and memory applications.

  20. In situ preparation, electrical and surface analytical characterization of pentacene thin film transistors

    Science.gov (United States)

    Lassnig, R.; Striedinger, B.; Hollerer, M.; Fian, A.; Stadlober, B.; Winkler, A.

    2015-01-01

    The fabrication of organic thin film transistors with highly reproducible characteristics presents a very challenging task. We have prepared and analyzed model pentacene thin film transistors under ultra-high vacuum conditions, employing surface analytical tools and methods. Intentionally contaminating the gold contacts and SiO2 channel area with carbon through repeated adsorption, dissociation, and desorption of pentacene proved to be very advantageous in the creation of devices with stable and reproducible parameters. We mainly focused on the device properties, such as mobility and threshold voltage, as a function of film morphology and preparation temperature. At 300 K, pentacene displays Stranski-Krastanov growth, whereas at 200 K fine-grained, layer-like film growth takes place, which predominantly influences the threshold voltage. Temperature dependent mobility measurements demonstrate good agreement with the established multiple trapping and release model, which in turn indicates a predominant concentration of shallow traps in the crystal grains and at the oxide-semiconductor interface. Mobility and threshold voltage measurements as a function of coverage reveal that up to four full monolayers contribute to the overall charge transport. A significant influence on the effective mobility also stems from the access resistance at the gold contact-semiconductor interface, which is again strongly influenced by the temperature dependent, characteristic film growth mode. PMID:25814770

  1. Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

    KAUST Repository

    Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon S.; Hussain, Muhammad Mustafa

    2017-01-01

    A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

  2. Novel field-effect schottky barrier transistors based on graphene-MoS 2 heterojunctions

    KAUST Repository

    Tian, He

    2014-08-11

    Recently, two-dimensional materials such as molybdenum disulphide (MoS 2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5-20 cm2/V.s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V.s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics.

  3. Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS2 Heterojunctions

    Science.gov (United States)

    Tian, He; Tan, Zhen; Wu, Can; Wang, Xiaomu; Mohammad, Mohammad Ali; Xie, Dan; Yang, Yi; Wang, Jing; Li, Lain-Jong; Xu, Jun; Ren, Tian-Ling

    2014-01-01

    Recently, two-dimensional materials such as molybdenum disulphide (MoS2) have been demonstrated to realize field effect transistors (FET) with a large current on-off ratio. However, the carrier mobility in backgate MoS2 FET is rather low (typically 0.5–20 cm2/V·s). Here, we report a novel field-effect Schottky barrier transistors (FESBT) based on graphene-MoS2 heterojunction (GMH), where the characteristics of high mobility from graphene and high on-off ratio from MoS2 are properly balanced in the novel transistors. Large modulation on the device current (on/off ratio of 105) is achieved by adjusting the backgate (through 300 nm SiO2) voltage to modulate the graphene-MoS2 Schottky barrier. Moreover, the field effective mobility of the FESBT is up to 58.7 cm2/V·s. Our theoretical analysis shows that if the thickness of oxide is further reduced, a subthreshold swing (SS) of 40 mV/decade can be maintained within three orders of drain current at room temperature. This provides an opportunity to overcome the limitation of 60 mV/decade for conventional CMOS devices. The FESBT implemented with a high on-off ratio, a relatively high mobility and a low subthreshold promises low-voltage and low-power applications for future electronics. PMID:25109609

  4. Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors

    KAUST Repository

    Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; LI, LIANG; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I.; Alshareef, Husam N.; Zhang, Yafei; Zhang, Xixiang

    2014-01-01

    Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. This journal is © the Partner Organisations 2014.

  5. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  6. Experimental realization of a silicon spin field-effect transistor

    OpenAIRE

    Huang, Biqin; Monsma, Douwe J.; Appelbaum, Ian

    2007-01-01

    A longitudinal electric field is used to control the transit time (through an undoped silicon vertical channel) of spin-polarized electrons precessing in a perpendicular magnetic field. Since an applied voltage determines the final spin direction at the spin detector and hence the output collector current, this comprises a spin field-effect transistor. An improved hot-electron spin injector providing ~115% magnetocurrent, corresponding to at least ~38% electron current spin polarization after...

  7. Area and energy efficient high-performance ZnO wavy channel thin-film transistor

    KAUST Repository

    Hanna, Amir

    2014-09-01

    Increased output current while maintaining low power consumption in thin-film transistors (TFTs) is essential for future generation large-area high-resolution displays. Here, we show wavy channel (WC) architecture in TFT that allows the expansion of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased performance while maintaining the real estate integrity. The experimental WCTFTs show a linear increase in output current as a function of number of fins per device resulting in (3.5×) increase in output current when compared with planar counterparts that consume the same chip area. The new architecture also allows tuning the threshold voltage as a function of the number of fin features included in the device, as threshold voltage linearly decreased from 6.8 V for planar device to 2.6 V for WC devices with 32 fins. This makes the new architecture more power efficient as lower operation voltages could be used for WC devices compared with planar counterparts. It was also found that field effect mobility linearly increases with the number of fins included in the device, showing almost \\\\(1.8×) enhancements in the field effect mobility than that of the planar counterparts. This can be attributed to higher electric field in the channel due to the fin architecture and threshold voltage shift. © 2014 IEEE.

  8. GaN transistors on Si for switching and high-frequency applications

    Science.gov (United States)

    Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

    2014-10-01

    In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

  9. Modelling transport in single electron transistor

    International Nuclear Information System (INIS)

    Dinh Sy Hien; Huynh Lam Thu Thao; Le Hoang Minh

    2009-01-01

    We introduce a model of single electron transistor (SET). Simulation programme of SET is used as the exploratory tool in order to gain better understanding of process and device physics. This simulator includes a graphic user interface (GUI) in Matlab. The SET was simulated using GUI in Matlab to get current-voltage (I-V) characteristics. In addition, effects of device capacitance, bias, temperature on the I-V characteristics were obtained. In this work, we review the capabilities of the simulator of the SET. Typical simulations of the obtained I-V characteristics of the SET are presented.

  10. Highly tunable local gate controlled complementary graphene device performing as inverter and voltage controlled resistor.

    Science.gov (United States)

    Kim, Wonjae; Riikonen, Juha; Li, Changfeng; Chen, Ya; Lipsanen, Harri

    2013-10-04

    Using single-layer CVD graphene, a complementary field effect transistor (FET) device is fabricated on the top of separated back-gates. The local back-gate control of the transistors, which operate with low bias at room temperature, enables highly tunable device characteristics due to separate control over electrostatic doping of the channels. Local back-gating allows control of the doping level independently of the supply voltage, which enables device operation with very low VDD. Controllable characteristics also allow the compensation of variation in the unintentional doping typically observed in CVD graphene. Moreover, both p-n and n-p configurations of FETs can be achieved by electrostatic doping using the local back-gate. Therefore, the device operation can also be switched from inverter to voltage controlled resistor, opening new possibilities in using graphene in logic circuitry.

  11. High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

    NARCIS (Netherlands)

    Houin, G.J.R.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

    2016-01-01

    The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance

  12. Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

    Science.gov (United States)

    Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

    2015-01-01

    We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

  13. InGaP/InGaAsN/GaAs NpN double-heterojunction bipolar transistor

    International Nuclear Information System (INIS)

    Chang, P. C.; Baca, A. G.; Li, N. Y.; Xie, X. M.; Hou, H. Q.; Armour, E.

    2000-01-01

    We have demonstrated a functional NpN double-heterojunction bipolar transistor (DHBT) using InGaAsN for the base layer. The InGaP/In 0.03 Ga 0.97 As 0.99 N 0.01 /GaAs DHBT has a low V ON of 0.81 V, which is 0.13 V lower than in a InGaP/GaAs heterojunction bipolar transistor (HBT). The lower turn-on voltage is attributed to the smaller band gap (1.20 eV) of metalorganic chemical vapor deposition-grown In 0.03 Ga 0.97 As 0.99 N 0.01 base layer. GaAs is used for the collector; thus the breakdown voltage (BV CEO ) is 10 V, consistent with the BV CEO of InGaP/GaAs HBTs of comparable collector thickness and doping level. To alleviate the current blocking phenomenon caused by the larger conduction band discontinuity between InGaAsN and GaAs, a graded InGaAs layer with δ doping is inserted at the base-collector junction. The improved device has a peak current gain of seven with ideal current-voltage characteristics. (c) 2000 American Institute of Physics

  14. Effect of TMAH Etching Duration on the Formation of Silicon Nano wire Transistor Patterned by AFM Nano lithography

    International Nuclear Information System (INIS)

    Hutagalung, S.D.; Lew, K.C.

    2012-01-01

    Atomic force microscopy (AFM) lithography was applied to produce nano scale pattern for silicon nano wire transistor fabrication. This technique takes advantage of imaging facility of AFM and the ability of probe movement controlling over the sample surface to create nano patterns. A conductive AFM tip was used to grow the silicon oxide nano patterns on silicon on insulator (SOI) wafer. The applied tip-sample voltage and writing speed were well controlled in order to form pre-designed silicon oxide nano wire transistor structures. The effect of tetra methyl ammonium hydroxide (TMAH) etching duration on the oxide covered silicon nano wire transistor structure has been investigated. A completed silicon nano wire transistor was obtained by removing the oxide layer via hydrofluoric acid etching process. The fabricated silicon nano wire transistor consists of a silicon nano wire that acts as a channel with source and drain pads. A lateral gate pad with a nano wire head was fabricated very close to the channel in the formation of transistor structures. (author)

  15. Review of recent developments in amorphous oxide semiconductor thin-film transistor devices

    International Nuclear Information System (INIS)

    Park, Joon Seok; Maeng, Wan-Joo; Kim, Hyun-Suk; Park, Jin-Seong

    2012-01-01

    The present article is a review of the recent progress and major trends in the field of thin-film transistor (TFT) research involving the use of amorphous oxide semiconductors (AOS). First, an overview is provided on how electrical performance may be enhanced by the adoption of specific device structures and process schemes, the combination of various oxide semiconductor materials, and the appropriate selection of gate dielectrics and electrode metals in contact with the semiconductor. As metal oxide TFT devices are excellent candidates for switching or driving transistors in next generation active matrix liquid crystal displays (AMLCD) or active matrix organic light emitting diode (AMOLED) displays, the major parameters of interest in the electrical characteristics involve the field effect mobility (μ FE ), threshold voltage (V th ), and subthreshold swing (SS). A study of the stability of amorphous oxide TFT devices is presented next. Switching or driving transistors in AMLCD or AMOLED displays inevitably involves voltage bias or constant current stress upon prolonged operation, and in this regard many research groups have examined and proposed device degradation mechanisms under various stress conditions. The most recent studies involve stress experiments in the presence of visible light irradiating the semiconductor, and different degradation mechanisms have been proposed with respect to photon radiation. The last part of this review consists of a description of methods other than conventional vacuum deposition techniques regarding the formation of oxide semiconductor films, along with some potential application fields including flexible displays and information storage.

  16. Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

    International Nuclear Information System (INIS)

    Lee, Youngmin; Lee, Sejoon; Im, Hyunsik; Hiramoto, Toshiro

    2015-01-01

    We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions

  17. Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik [Department of Semiconductor Science, Dongguk University-Seoul, Seoul 100-715 (Korea, Republic of); Hiramoto, Toshiro [Institute of Industrial Science, University of Tokyo, Tokyo 153-8505 (Japan)

    2015-02-14

    We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

  18. The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

    Science.gov (United States)

    Hsu, Yu-Jen

    Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by

  19. Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

    International Nuclear Information System (INIS)

    Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu

    2014-01-01

    We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4 ′ -pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm 2 /Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V D ) and gate (V G ) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V D and V G . The best voltage combination was V D = −0.2 V and V G = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors

  20. A Voltage Gain-Controlled Modified CFOA And Its Application in Electronically Tunable Four-Mode All-Pass Filter Design

    Directory of Open Access Journals (Sweden)

    Norbert Herencsar

    2012-07-01

    Full Text Available This paper presents a new active building block (ABB called voltage gain-controlled modified current feedback amplifier (VGC-MCFOA based on bipolar junction transistor technology. The versatility of the new ABB is demonstrated in new first-order all-pass filter structure design employing single VGC-MCFOA, single grounded capacitor, and three resistors. Introduced circuit provides all four possible transfer functions at the same configuration, namely current-mode, transimpedance-mode, transadmittance-mode, and voltage-mode. The pole frequency of the circuit can be easily tuned by means of DC bias currents. The theoretical results are verified by SPICE simulations based on bipolar transistor arrays AT&T ALA400-CBIC-R process parameters.

  1. Hole-transporting transistors and circuits based on the transparent inorganic semiconductor copper(I) thiocyanate (CuSCN) processed from solution at room temperature

    KAUST Repository

    Pattanasattayavong, Pichaya

    2012-12-27

    The wide bandgap and highly transparent inorganic compound copper(I) thiocyanate (CuSCN) is used for the first time to fabricate p-type thin-film transistors processed from solution at room temperature. By combining CuSCN with the high-k relaxor ferroelectric polymeric dielectric P(VDF-TrFE-CFE), we demonstrate low-voltage transistors with hole mobilities on the order of 0.1 cm2 V-1 s-1. By integrating two CuSCN transistors, unipolar logic NOT gates are also demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  2. Multi-Objective Scheduling Optimization Based on a Modified Non-Dominated Sorting Genetic Algorithm-II in Voltage Source Converter−Multi-Terminal High Voltage DC Grid-Connected Offshore Wind Farms with Battery Energy Storage Systems

    Directory of Open Access Journals (Sweden)

    Ho-Young Kim

    2017-07-01

    Full Text Available Improving the performance of power systems has become a challenging task for system operators in an open access environment. This paper presents an optimization approach for solving the multi-objective scheduling problem using a modified non-dominated sorting genetic algorithm in a hybrid network of meshed alternating current (AC/wind farm grids. This approach considers voltage and power control modes based on multi-terminal voltage source converter high-voltage direct current (MTDC and battery energy storage systems (BESS. To enhance the hybrid network station performance, we implement an optimal process based on the battery energy storage system operational strategy for multi-objective scheduling over a 24 h demand profile. Furthermore, the proposed approach is formulated as a master problem and a set of sub-problems associated with the hybrid network station to improve the overall computational efficiency using Benders’ decomposition. Based on the results of the simulations conducted on modified institute of electrical and electronics engineers (IEEE-14 bus and IEEE-118 bus test systems, we demonstrate and confirm the applicability, effectiveness and validity of the proposed approach.

  3. A 5 V-to-3.3 V CMOS Linear Regulator with Three-Output Temperature-Independent Reference Voltages

    Directory of Open Access Journals (Sweden)

    San-Fu Wang

    2016-01-01

    Full Text Available This paper presents a 5 V-to-3.3 V linear regulator circuit, which uses 3.3 V CMOS transistors to replace the 5 V CMOS transistors. Thus, the complexity of the manufacturing semiconductor process can be improved. The proposed linear regulator is implemented by cascode architecture, which requires three different reference voltages as the bias voltages of its circuit. Thus, the three-output temperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously. The three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed temperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable for low cost, small size, and highly integrated system-on-chip (SoC applications. Moreover, the proposed linear regulator uses the cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear regulator has a good performance in reference voltage to output voltage isolation. The voltage variation of the linear regulator is less than 2.153% in the temperature range of −40°C–120°C, and the power supply rejection ratio (PSRR is less than −42.8 dB at 60 Hz. The regulator can support 0~200 mA output current. The core area is less than 0.16 mm2.

  4. Voltage and Thermally Driven Roll-to-Roll Organic Printed Transistor Made in Ambient Air Conditions

    DEFF Research Database (Denmark)

    Pastorelli, Francesco

    of the organic semiconductor poly3hexylthiophene and the dielectric material polyvinylphenol before the gate was applied by screen printing. All the processing was realized in ambient air on a PET flexible substrate. We explore the footprint and the practically accessible geometry of such devices with a special......Resume: Organic thin film transistors offer great potential for use in flexible electronics. Much of this potential lies in the solution processability of the organic polymers enabling both roll coating and printing on flexible substrates and thus greatly reducing the material and fabrication costs....... We present flexible organic power transistors prepared by fast (20 m min−1) roll-to-roll flexographic printing of the drain and source electrode structures, with an interspace below 50 um, directly on polyester foil[1]. The devices have top gate architecture and were completed by slotdie coating...

  5. Electrooptic Methods for Measurement of Small DC Currents at High Voltage Level

    DEFF Research Database (Denmark)

    Tønnesen, Ole; Beatty, Neville; Skilbreid, Asbjørn Ottar

    1989-01-01

    collectors are connected via resistors RA and RB to the protective side of the voltage to be measured and the emitters to the negative side. The currents flowing in to the bases of the transistors are independently controlled by the light levels following on the two photodiodes PDA, PDB....

  6. Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

    Science.gov (United States)

    Farhadi, Rozita; Farhadi, Bita

    2014-01-01

    Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

  7. Effects of microwave pulse-width damage on a bipolar transistor

    International Nuclear Information System (INIS)

    Ma Zhen-Yang; Chai Chang-Chun; Ren Xing-Rong; Yang Yin-Tang; Chen Bin; Zhao Ying-Bo

    2012-01-01

    This paper presents a theoretical study of the pulse-width effects on the damage process of a typical bipolar transistor caused by high power microwaves (HPMs) through the injection approach. The dependences of the microwave damage power, P, and the absorbed energy, E, required to cause the device failure on the pulse width τ are obtained in the nanosecond region by utilizing the curve fitting method. A comparison of the microwave pulse damage data and the existing dc pulse damage data for the same transistor is carried out. By means of a two-dimensional simulator, ISE-TCAD, the internal damage processes of the device caused by microwave voltage signals and dc pulse voltage signals are analyzed comparatively. The simulation results suggest that the temperature-rising positions of the device induced by the microwaves in the negative and positive half periods are different, while only one hot spot exists under the injection of dc pulses. The results demonstrate that the microwave damage power threshold and the absorbed energy must exceed the dc pulse power threshold and the absorbed energy, respectively. The dc pulse damage data may be useful as a lower bound for microwave pulse damage data. (interdisciplinary physics and related areas of science and technology)

  8. Saddle-fin cell transistors with oxide etch rate control by using tilted ion implantation (TIS-fin) for sub-50-nm DRAMs

    International Nuclear Information System (INIS)

    Yoo, Min Soo; Choi, Kang Sik; Sun, Woo Kyung

    2010-01-01

    As DRAM cell pitch size decreases, the need for a high performance transistor is increasing. Though saddle-fin (S-fin) transistors have superior characteristics, S-fin transistors are well known to be more sensitive to process variation. To make uniform S-fin transistors, for the first time, we developed a new fin formation method using tilted ion implantation along the wordline direction after a recess gate etch. Due to the increased etch rate of the oxide film by ion implantation damage, fins are made at the bottom channel of the recess gate after wet etching. The resulting tilt implanted saddle-fin (TIS-fin) transistor has remarkably improved characteristics, such as ∼8% subthreshold swing (SS) and a 40% drain induced barrier lowering (DIBL) decrease. Especially, the TIS-fin with a neutral dopant has a reduced threshold voltage (Vth) variation within a wafer (<100 mV), which is comparable with that of a mass-produced sphere-shaped recessed channel array transistor (SRCAT).

  9. Design and simulation of a novel GaN based resonant tunneling high electron mobility transistor on a silicon substrate

    International Nuclear Information System (INIS)

    Chowdhury, Subhra; Biswas, Dhrubes; Chattaraj, Swarnabha

    2015-01-01

    For the first time, we have introduced a novel GaN based resonant tunneling high electron mobility transistor (RTHEMT) on a silicon substrate. A monolithically integrated GaN based inverted high electron mobility transistor (HEMT) and a resonant tunneling diode (RTD) are designed and simulated using the ATLAS simulator and MATLAB in this study. The 10% Al composition in the barrier layer of the GaN based RTD structure provides a peak-to-valley current ratio of 2.66 which controls the GaN based HEMT performance. Thus the results indicate an improvement in the current–voltage characteristics of the RTHEMT by controlling the gate voltage in this structure. The introduction of silicon as a substrate is a unique step taken by us for this type of RTHEMT structure. (paper)

  10. Kinase detection with gallium nitride based high electron mobility transistors.

    Science.gov (United States)

    Makowski, Matthew S; Bryan, Isaac; Sitar, Zlatko; Arellano, Consuelo; Xie, Jinqiao; Collazo, Ramon; Ivanisevic, Albena

    2013-07-01

    A label-free kinase detection system was fabricated by the adsorption of gold nanoparticles functionalized with kinase inhibitor onto AlGaN/GaN high electron mobility transistors (HEMTs). The HEMTs were operated near threshold voltage due to the greatest sensitivity in this operational region. The Au NP/HEMT biosensor system electrically detected 1 pM SRC kinase in ionic solutions. These results are pertinent to drug development applications associated with kinase sensing.

  11. Doped Organic Transistors.

    Science.gov (United States)

    Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

    2016-11-23

    Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

  12. The design of a new spiking neuron using dual work function silicon nanowire transistors

    International Nuclear Information System (INIS)

    Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

    2007-01-01

    A new spike neuron cell is designed using vertically grown, undoped silicon nanowire transistors. This study presents an entire design cycle from designing and optimizing vertical nanowire transistors for minimal power dissipation to realizing a neuron cell and measuring its dynamic power consumption, performance and layout area. The design cycle starts with determining individual metal gate work functions for NMOS and PMOS transistors as a function of wire radius to produce a 300 mV threshold voltage. The wire radius and effective channel length are subsequently varied to find a common body geometry for both transistors that yields smaller than 1 pA OFF current while producing maximum drive currents. A spike neuron cell is subsequently built using these transistors to measure its transient performance, power dissipation and layout area. Post-layout simulation results indicate that the neuron consumes 0.397 μW to generate a +1 V and 1.12 μW to generate a -1 V output pulse for a fan-out of five synapses at 500 MHz; the power dissipation increases by approximately 3 nW for each additional synapse at the output for generating either pulse. The neuron circuit occupies approximately 0.27 μm 2

  13. Performance improvement of organic thin film transistors by using active layer with sandwich structure

    Science.gov (United States)

    Ni, Yao; Zhou, Jianlin; Kuang, Peng; Lin, Hui; Gan, Ping; Hu, Shengdong; Lin, Zhi

    2017-08-01

    We report organic thin film transistors (OTFTs) with pentacene/fluorinated copper phthalo-cyanine (F16CuPc)/pentacene (PFP) sandwich configuration as active layers. The sandwich devices not only show hole mobility enhancement but also present a well control about threshold voltage and off-state current. By investigating various characteristics, including current-voltage hysteresis, organic film morphology, capacitance-voltage curve and resistance variation of active layers carefully, it has been found the performance improvement is mainly attributed to the low carrier traps and the higher conductivity of the sandwich active layer due to the additional induced carriers in F16CuPc/pentacene. Therefore, using proper multiple active layer is an effective way to gain high performance OTFTs.

  14. Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon

    KAUST Repository

    Lin, Che-Yu

    2017-10-04

    High-frequency operation with ultra-thin, lightweight and extremely flexible semiconducting electronics are highly desirable for the development of mobile devices, wearable electronic systems and defense technologies. In this work, the first experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density and flexible electronics.

  15. Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon

    KAUST Repository

    Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Li, Ming-Yang; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L.; Lan, Yann-Wen

    2017-01-01

    High-frequency operation with ultra-thin, lightweight and extremely flexible semiconducting electronics are highly desirable for the development of mobile devices, wearable electronic systems and defense technologies. In this work, the first experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density and flexible electronics.

  16. Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

    Science.gov (United States)

    Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

    2017-11-28

    High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

  17. Solution-Processed Organic and Halide Perovskite Transistors on Hydrophobic Surfaces.

    Science.gov (United States)

    Ward, Jeremy W; Smith, Hannah L; Zeidell, Andrew; Diemer, Peter J; Baker, Stephen R; Lee, Hyunsu; Payne, Marcia M; Anthony, John E; Guthold, Martin; Jurchescu, Oana D

    2017-05-31

    Solution-processable electronic devices are highly desirable due to their low cost and compatibility with flexible substrates. However, they are often challenging to fabricate due to the hydrophobic nature of the surfaces of the constituent layers. Here, we use a protein solution to modify the surface properties and to improve the wettability of the fluoropolymer dielectric Cytop. The engineered hydrophilic surface is successfully incorporated in bottom-gate solution-deposited organic field-effect transistors (OFETs) and hybrid organic-inorganic trihalide perovskite field-effect transistors (HTP-FETs) fabricated on flexible substrates. Our analysis of the density of trapping states at the semiconductor-dielectric interface suggests that the increase in the trap density as a result of the chemical treatment is minimal. As a result, the devices exhibit good charge carrier mobilities, near-zero threshold voltages, and low electrical hysteresis.

  18. Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

    Science.gov (United States)

    Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

    2017-04-01

    We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

  19. Analysis of the two dimensional Datta-Das Spin Field Effect Transistor

    OpenAIRE

    Bandyopadhyay, S.

    2010-01-01

    An analytical expression is derived for the conductance modulation of a ballistic two dimensional Datta-Das Spin Field Effect Transistor (SPINFET) as a function of gate voltage. Using this expression, we show that the recently observed conductance modulation in a two-dimensional SPINFET structure does not match the theoretically expected result very well. This calls into question the claimed demonstration of the SPINFET and underscores the need for further careful investigation.

  20. Analysis of the two-dimensional Datta-Das spin field effect transistor

    Science.gov (United States)

    Agnihotri, P.; Bandyopadhyay, S.

    2010-03-01

    An analytical expression is derived for the conductance modulation of a ballistic two-dimensional Datta-das spin field effect transistor (SPINFET) as a function of gate voltage. Using this expression, we show that the recently observed conductance modulation in a two-dimensional SPINFET structure does not match the theoretically expected result very well. This calls into question the claimed demonstration of the SPINFET and underscores the need for further careful investigation.

  1. High-performance zno transistors processed via an aqueous carbon-free metal oxide precursor route at temperatures between 80-180 °c

    KAUST Repository

    Lin, Yenhung

    2013-06-25

    An aqueous and carbon-free metal-oxide precursor route is used in combination with a UV irradiation-assisted low-temperature conversion method to fabricate low-voltage ZnO transistors with electron mobilities exceeding 10 cm2/Vs at temperatures <180°C. Because of its low temperature requirements the method allows processing of high-performance transistors onto temperature sensitive substrates such as plastic. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  2. Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors

    KAUST Repository

    Hanna, Amir

    2016-11-01

    This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V. This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation

  3. Probing spin-polarized tunneling at high bias and temperature with a magnetic tunnel transistor

    NARCIS (Netherlands)

    Park, B.G.; Banerjee, T.; Min, B.C.; Sanderink, Johannes G.M.; Lodder, J.C.; Jansen, R.

    2005-01-01

    The magnetic tunnel transistor (MTT) is a three terminal hybrid device that consists of a tunnel emitter, a ferromagnetic (FM) base, and a semiconductor collector. In the MTT with a FM emitter and a single FM base, spin-polarized hot electrons are injected into the base by tunneling. After

  4. Quantum ballistic transistor and low noise HEMT for cryo-electronics lower than 4.2 K

    International Nuclear Information System (INIS)

    Gremion, E.

    2008-01-01

    Next generations of cryo-detectors, widely used in physics of particles and physics of universe, will need in the future high-performance cryo-electronics less noisy and closer to the detector. Within this context, this work investigates properties of two dimensional electron gas GaAlAs/GaAs by studying two components, quantum point contact (QPC) and high electron mobility transistor (HEMT). Thanks to quantized conductance steps in QPC, we have realized a quantum ballistic transistor (voltage gain higher than 1), a new component useful for cryo-electronics thanks to its operating temperature and weak power consumption (about 1 nW). Moreover, the very low capacity of this component leads to promising performances for multiplexing low temperature bolometer dedicated to millimetric astronomy. The second study focused on HEMT with very high quality 2DEG. At 4.2 K, a voltage gain higher than 20 can be obtained with a very low power dissipation of less than 100 μW. Under the above experimental conditions, an equivalent input voltage noise of 1.2 nV/√(Hz) at 1 kHz and 0.12 nV/√(Hz) at 100 kHz has been reached. According to the Hooge formula, these noise performances are get by increasing gate capacity estimated to 60 pF. (author)

  5. Atypical transistor-based chaotic oscillators: Design, realization, and diversity

    Science.gov (United States)

    Minati, Ludovico; Frasca, Mattia; OświÈ©cimka, Paweł; Faes, Luca; DroŻdŻ, Stanisław

    2017-07-01

    In this paper, we show that novel autonomous chaotic oscillators based on one or two bipolar junction transistors and a limited number of passive components can be obtained via random search with suitable heuristics. Chaos is a pervasive occurrence in these circuits, particularly after manual adjustment of a variable resistor placed in series with the supply voltage source. Following this approach, 49 unique circuits generating chaotic signals when physically realized were designed, representing the largest collection of circuits of this kind to date. These circuits are atypical as they do not trivially map onto known topologies or variations thereof. They feature diverse spectra and predominantly anti-persistent monofractal dynamics. Notably, we recurrently found a circuit comprising one resistor, one transistor, two inductors, and one capacitor, which generates a range of attractors depending on the parameter values. We also found a circuit yielding an irregular quantized spike-train resembling some aspects of neural discharge and another one generating a double-scroll attractor, which represent the smallest known transistor-based embodiments of these behaviors. Through three representative examples, we additionally show that diffusive coupling of heterogeneous oscillators of this kind may give rise to complex entrainment, such as lag synchronization with directed information transfer and generalized synchronization. The replicability and reproducibility of the experimental findings are good.

  6. Investigation on pseudomorphic InGaAs/InAlAs/InP High Electron Mobility Transistors with regard to cryogenic applications

    International Nuclear Information System (INIS)

    Toennesmann, A.

    2003-03-01

    A wide variety of new data communication applications demand ever-increasing transmission capacities. The InGaAs/InAlAs/InP layer stack based high electron mobility transistor (HEMT) is currently regarded as the most promising active device in communication systems as it has the highest cut-off frequencies of all transistor types. Due to reduced phonon scattering of the charge carriers, the HEMT is expected to exhibit even better noise and high frequency characteristics for operations at cryogenic temperatures, for instance in mixers or oscillators located in satellites or ground based systems with appropriate cooling equipment. This work focuses on the reduction of access resistances and the fabrication of very short gate lengths as the biggest technological challenges realizing highest cut-off frequencies at any temperature. In addition, the reproducibility and robustness of the implemented gate technologies are fundamental criteria for applications. In comparison to other transistor designs, the InAlAs/InGaAs HEMTs are stronger affected by undesirable, partly material dependent, short channel effects like early breakdown, high gate currents, impact ionization, the kink effect, and a shift in the threshold voltage. Measurements at liquid nitrogen temperature on transistors produced in this work provide further insight into the poorly understood interrelationship between these effects. At liquid nitrogen temperature, the cut-off frequency of 180 GHz and the maximum oscillation frequency of 300 GHz of short channel transistors at room temperature increase by 20% and 30%, respectively, while the breakdown voltage remains at high values above 8 V. (orig.)

  7. Modulation linearization of a frequency-modulated voltage controlled oscillator, part 3

    Science.gov (United States)

    Honnell, M. A.

    1975-01-01

    An analysis is presented for the voltage versus frequency characteristics of a varactor modulated VHF voltage controlled oscillator in which the frequency deviation is linearized by using the nonlinear characteristics of a field effect transistor as a signal amplifier. The equations developed are used to calculate the oscillator output frequency in terms of pertinent circuit parameters. It is shown that the nonlinearity exponent of the FET has a pronounced influence on frequency deviation linearity, whereas the junction exponent of the varactor controls total frequency deviation for a given input signal. A design example for a 250 MHz frequency modulated oscillator is presented.

  8. Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

    Science.gov (United States)

    Choi, Woo Young; Lee, Hyun Kook

    2016-01-01

    The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

  9. Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

    Science.gov (United States)

    Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

    2016-08-10

    Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

  10. Development of a fast voltage control method for electrostatic accelerators

    International Nuclear Information System (INIS)

    Lobanov, Nikolai R.; Linardakis, Peter; Tsifakis, Dimitrios

    2014-01-01

    The concept of a novel fast voltage control loop for tandem electrostatic accelerators is described. This control loop utilises high-frequency components of the ion beam current intercepted by the image slits to generate a correction voltage that is applied to the first few gaps of the low- and high-energy acceleration tubes adjoining the high voltage terminal. New techniques for the direct measurement of the transfer function of an ultra-high impedance structure, such as an electrostatic accelerator, have been developed. For the first time, the transfer function for the fast feedback loop has been measured directly. Slow voltage variations are stabilised with common corona control loop and the relationship between transfer functions for the slow and new fast control loops required for optimum operation is discussed. The main source of terminal voltage instabilities, which are due to variation of the charging current caused by mechanical oscillations of charging chains, has been analysed

  11. Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

    International Nuclear Information System (INIS)

    Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

    2009-01-01

    Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

  12. Unijunction transistors

    International Nuclear Information System (INIS)

    1981-01-01

    The electrical characteristics of unijunction transistors can be modified by irradiation with electron beams in excess of 400 KeV and at a dose rate of 10 13 to 10 16 e/cm 2 . Examples are given of the effect of exposing the emitter-base junctions of transistors to such lattice defect causing radiation for a time sufficient to change the valley current of the transistor. (U.K.)

  13. Influence of channel length and layout on TID for 0.18 μm NMOS transistors

    International Nuclear Information System (INIS)

    Wu Xue; Wang Xin; Xi Shanbin; Lu Wu; Guo Qi; He Chengfa; Li Yudong; Sun Jing; Wen Lin

    2013-01-01

    Different channel lengths and layouts on 0.18 μm NMOS transistors are designed for investigating the dependence of short channel effects (SCEs) on the width of shallow trench isolation (STI) devices and designing in radiation hardness. Results show that, prior to irradiation, the devices exhibited near-ideal I-V characteristics, with no significant SCEs. Following irradiation, no noticeable shift of threshold voltage is observed, radiation-induced edge-leakage current, however, exhibits significant sensitivity on TID. Moreover, radiation-enhanced drain induced barrier lowering (DIBL) and channel length modulation (CLM) effects are observed on short-channel NMOS transistors. Comparing to stripe-gate layout, enclosed-gate layout has excellent radiation tolerance. (authors)

  14. Simulation model for electron irradiated IGZO thin film transistors

    Science.gov (United States)

    Dayananda, G. K.; Shantharama Rai, C.; Jayarama, A.; Kim, Hyun Jae

    2018-02-01

    An efficient drain current simulation model for the electron irradiation effect on the electrical parameters of amorphous In-Ga-Zn-O (IGZO) thin-film transistors is developed. The model is developed based on the specifications such as gate capacitance, channel length, channel width, flat band voltage etc. Electrical parameters of un-irradiated IGZO samples were simulated and compared with the experimental parameters and 1 kGy electron irradiated parameters. The effect of electron irradiation on the IGZO sample was analysed by developing a mathematical model.

  15. Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

    2011-01-01

    In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

  16. Current-Induced Joule Heating and Electrical Field Effects in Low Temperature Measurements on TIPS Pentacene Thin Film Transistors

    NARCIS (Netherlands)

    Nikiforov, G.O.; Venkateshvaran, D.; Mooser, S.; Meneau, A.; Strobel, T.; Kronemeijer, A.; Jiang, L.; Lee, M.J.; Sirringhaus, H.

    2016-01-01

    The channel temperature (Tch) of solution-processed 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS pentacene) thin film transistors (TFTs) is closely monitored in real time during current–voltage (I–V) measurements carried out in a He exchange gas cryostat at various base temperatures (Tb)

  17. Electrical characteristics of silicon percolating nanonet-based field effect transistors in the presence of dispersion

    Science.gov (United States)

    Cazimajou, T.; Legallais, M.; Mouis, M.; Ternon, C.; Salem, B.; Ghibaudo, G.

    2018-05-01

    We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in back-gated transistor mode, for future use as gas or biosensors. These devices featured P-type field-effect characteristics. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as apparent low field mobility, threshold voltage and subthreshold slope ideality factor. Their variation with channel length and nanowire density was related to the change of conduction regime from direct source/drain connection by parallel nanowires to percolating channels. Experimental results could be related in part to an influence of the threshold voltage dispersion of individual nanowires.

  18. Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

    Science.gov (United States)

    Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

    2017-05-10

    We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

  19. Observation of Van Hove Singularities and Temperature Dependence of Electrical Characteristics in Suspended Carbon Nanotube Schottky Barrier Transistors

    Science.gov (United States)

    Zhang, Jian; Liu, Siyu; Nshimiyimana, Jean Pierre; Deng, Ya; Hu, Xiao; Chi, Xiannian; Wu, Pei; Liu, Jia; Chu, Weiguo; Sun, Lianfeng

    2018-06-01

    A Van Hove singularity (VHS) is a singularity in the phonon or electronic density of states of a crystalline solid. When the Fermi energy is close to the VHS, instabilities will occur, which can give rise to new phases of matter with desirable properties. However, the position of the VHS in the band structure cannot be changed in most materials. In this work, we demonstrate that the carrier densities required to approach the VHS are reached by gating in a suspended carbon nanotube Schottky barrier transistor. Critical saddle points were observed in regions of both positive and negative gate voltage, and the conductance flattened out when the gate voltage exceeded the critical value. These novel physical phenomena were evident when the temperature is below 100 K. Further, the temperature dependence of the electrical characteristics was also investigated in this type of Schottky barrier transistor.

  20. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Energy Technology Data Exchange (ETDEWEB)

    Wang Chunhua; Ma Minglin; Sun Jingru; Du Sichun; Guo Xiaorong; He Haizhen, E-mail: wch1227164@sina.com [School of Information Science and Technology, Hunan University, Changsha 410082 (China)

    2011-02-15

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (G{sub m}-LNA) and a differential current-mode down converted mixer. The single terminal of the G{sub m}-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, C{sub x1} and C{sub x2}, can not only reduce the effects of gate-source C{sub gs} on resonance frequency and input-matching impedance, but they also enable the gate inductance L{sub g1,2} to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 {mu}m CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

  1. Top-gate hybrid complementary inverters using pentacene and amorphous InGaZnO thin-film transistors with high operational stability

    Directory of Open Access Journals (Sweden)

    J. B. Kim

    2012-03-01

    Full Text Available We report on the operational stability of low-voltage hybrid organic-inorganic complementary inverters with a top-gate bottom source-drain geometry. The inverters are comprised of p-channel pentacene and n-channel amorphous InGaZnO thin-film transistors (TFTs with bi-layer gate dielectrics formed from an amorphous layer of a fluoropolymer (CYTOP and a high-k layer of Al2O3. The p- and n- channel TFTs show saturation mobility values of 0.1 ± 0.01 and 5.0 ± 0.5 cm2/Vs, respectively. The individual transistors show high electrical stability with less than 6% drain-to-source current variations after 1 h direct current (DC bias stress. Complementary inverters yield hysteresis-free voltage transfer characteristics for forward and reverse input biases with static DC gain values larger than 45 V/V at 8 V before and after being subjected to different conditions of electrical stress. Small and reversible variations of the switching threshold voltage of the inverters during these stress tests are compatible with the observed stability of the individual TFTs.

  2. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    Directory of Open Access Journals (Sweden)

    Mohammad Reza Shokrani

    2014-01-01

    Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  3. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  4. Stability of DC Voltage Droop Controllers in VSC HVDC Systems

    DEFF Research Database (Denmark)

    Thams, Florian; Suul, Jon Are; D’Arco, Salvatore

    2015-01-01

    Future multi-terminal HVDC systems are expected to utilize dc voltage droop controllers and several control implementations have been proposed in literature. This paper first classifies possible dc droop implementations in a simple framework. Then, the small-signal stability of a VSC-based conver......Future multi-terminal HVDC systems are expected to utilize dc voltage droop controllers and several control implementations have been proposed in literature. This paper first classifies possible dc droop implementations in a simple framework. Then, the small-signal stability of a VSC...

  5. Gallium nitride based transistors for high-efficiency microwave switch-mode amplifiers

    Energy Technology Data Exchange (ETDEWEB)

    Maroldt, Stephan

    2012-07-01

    circuit efficiency of >80% were achieved for an operation at 0.45 GHz when adjusting the transistor size for lower operation frequencies. A further decisive improvement of speed and circuit complexity was found by the implementation of enhancement-mode GaN transistors based on a high-transconductance gate-recess technology. Transistors with a threshold voltage of +1 V were demonstrated with a high current drive capability and a maximum transconductance of up to 600 mS/mm. Their reduced input voltage swing tremendously increases the compatibility of digital power amplifier circuits based on GaN and external digital driver and modulator circuits based on silicon technology. Moreover, an innovative development, the series-diode GaN transistor, replaces an off-chip hybrid diode in the class-S amplifier with an integrated solution. It reduces parasitic switching losses and improves the total amplifier properties in terms of operation frequency, efficiency, and circuit complexity. A differential switch-mode core chip featuring series-diode transistors and additional onchip filter elements enabled our partner EADS to realize the first class-S amplifier at 2 GHz worldwide in a module.

  6. Transistorized ignition system for internal combustion engines, in particular for vehicles

    Energy Technology Data Exchange (ETDEWEB)

    Mieras, L F; Skay, F

    1977-05-12

    The invention concerns an ignition system for motor vehicles with solid state control of the power transistor switching the primary current of the ignition coil. A pulse generator driven by the engine is used for this, whose voltage pulses control the switching on of the power transistor and increase in a certain ratio to the engine speed. This ensures that the closing angle, i.e. the mechanical angle of rotation which the machine passes through while loading the ignition coil with mechanical energy, is automatically changed so that for low speeds it is just sufficient for certain ignition, but increases with increasing speed, so that the required ignition energy is always available. At low speeds one avoids charging current flowing through the primary winding of the ignition coil for longer than necessary and thus wasting electrical energy.

  7. Nanoscale structural and chemical analysis of F-implanted enhancement-mode InAlN/GaN heterostructure field effect transistors

    Science.gov (United States)

    Tang, Fengzai; Lee, Kean B.; Guiney, Ivor; Frentrup, Martin; Barnard, Jonathan S.; Divitini, Giorgio; Zaidi, Zaffar H.; Martin, Tomas L.; Bagot, Paul A.; Moody, Michael P.; Humphreys, Colin J.; Houston, Peter A.; Oliver, Rachel A.; Wallis, David J.

    2018-01-01

    We investigate the impact of a fluorine plasma treatment used to obtain enhancement-mode operation on the structure and chemistry at the nanometer and atomic scales of an InAlN/GaN field effect transistor. The fluorine plasma treatment is successful in that enhancement mode operation is achieved with a +2.8 V threshold voltage. However, the InAlN barrier layers are observed to have been damaged by the fluorine treatment with their thickness being reduced by up to 50%. The treatment also led to oxygen incorporation within the InAlN barrier layers. Furthermore, even in the as-grown structure, Ga was unintentionally incorporated during the growth of the InAlN barrier. The impact of both the reduced barrier thickness and the incorporated Ga within the barrier on the transistor properties has been evaluated theoretically and compared to the experimentally determined two-dimensional electron gas density and threshold voltage of the transistor. For devices without fluorine treatment, the two-dimensional electron gas density is better predicted if the quaternary nature of the barrier is taken into account. For the fluorine treated device, not only the changes to the barrier layer thickness and composition, but also the fluorine doping needs to be considered to predict device performance. These studies reveal the factors influencing the performance of these specific transistor structures and highlight the strengths of the applied nanoscale characterisation techniques in revealing information relevant to device performance.

  8. Revealing Buried Interfaces to Understand the Origins of Threshold Voltage Shifts in Organic Field-Effect Transistors

    NARCIS (Netherlands)

    Mathijssen, Simon G. J.; Spijkman, Mark-Jan; Andringa, Anne-Marije; van Hal, Paul A.; McCulloch, Iain; Kemerink, Martijn; Janssen, Rene A. J.; de Leeuw, Dago M.

    2010-01-01

    The semiconductor of an organic field-effect transistor is stripped with adhesive tape, yielding an exposed gate dielectric, accessible for various characterization techniques. By using scanning Kelvin probe microscopy we reveal that trapped charges after gate bias stress are located at the gate

  9. Voltage Quality Improvement in Islanded Microgrids Supplying Nonlinear Loads

    DEFF Research Database (Denmark)

    T. Dehghani, Mohammad; Vahedi, Abolfazl; Savaghebi, Mehdi

    2012-01-01

    The aim of this paper is to improve voltage quality at the terminals of distributed generators (DGs) in an islanded microgrid. To achieve this goal, it is proposed to include separate voltage and current control loops for the fundamental and harmonics frequencies. This way, it is not necessary...

  10. Voltage Recovery of Grid-Connected Wind Turbines with DFIG After a Short-Circuit Fault

    DEFF Research Database (Denmark)

    Sun, Tao; Chen, Zhe; Blaabjerg, Frede

    2004-01-01

    The fast development of wind power generation brings new requirements for wind turbine integration to the network. After clearance of an external short-circuit fault, the voltage at the wind turbine terminal should be re-established with minimized power losses. This paper concentrates on voltage......-establish the wind turbine terminal voltage after the clearance of an external short-circuit fault, and the restore the normal operation of the variable speed wind turbine with DFIG, which has been demonstrated by simulation results....

  11. I-V Characteristics of a Static Random Access Memory Cell Utilizing Ferroelectric Transistors

    Science.gov (United States)

    Laws, Crystal; Mitchell, Cody; Hunt, Mitchell; Ho, Fat D.; MacLeod, Todd C.

    2012-01-01

    I-V characteristics for FeFET different than that of MOSFET Ferroelectric layer features hysteresis trend whereas MOSFET behaves same for both increasing and decreasing VGS FeFET I-V characteristics doesn't show dependence on VDS A Transistor with different channel length and width as well as various resistance and input voltages give different results As resistance values increased, the magnitude of the drain current decreased.

  12. A new high-voltage level-shifting circuit for half-bridge power ICs

    International Nuclear Information System (INIS)

    Kong Moufu; Chen Xingbi

    2013-01-01

    In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well. (semiconductor integrated circuits)

  13. Bi-directional power control system for voltage converter

    Science.gov (United States)

    Garrigan, Neil Richard; King, Robert Dean; Schwartz, James Edward

    1999-01-01

    A control system for a voltage converter includes: a power comparator for comparing a power signal on input terminals of the converter with a commanded power signal and producing a power comparison signal; a power regulator for transforming the power comparison signal to a commanded current signal; a current comparator for comparing the commanded current signal with a measured current signal on output terminals of the converter and producing a current comparison signal; a current regulator for transforming the current comparison signal to a pulse width modulator (PWM) duty cycle command signal; and a PWM for using the PWM duty cycle command signal to control electrical switches of the converter. The control system may further include: a command multiplier for converting a voltage signal across the output terminals of the converter to a gain signal having a value between zero (0) and unity (1), and a power multiplier for multiplying the commanded power signal by the gain signal to provide a limited commanded power signal, wherein power comparator compares the limited commanded power signal with the power signal on the input terminals.

  14. Lowered operation voltage in Pt/SBi2Ta2O9/HfO2/Si ferroelectric-gate field-effect transistors by oxynitriding Si

    International Nuclear Information System (INIS)

    Horiuchi, Takeshi; Takahashi, Mitsue; Li, Qiu-Hong; Wang, Shouyu; Sakai, Shigeki

    2010-01-01

    Oxynitrided Si (SiON) surfaces show smaller subthreshold swings than do directly nitrided Si (SiN) surfaces when used in ferroelectric-gate field-effect transistors (FeFETs) having the following stacked-gate structure: Pt/SrBi 2 Ta 2 O 9 (SBT)/HfO 2 /Si. SiON/Si substrates for FeFETs were prepared by rapid thermal oxidation (RTO) in O 2 at 1000 °C and subsequent rapid thermal nitridation (RTN) in NH 3 at various temperatures in the range 950–1150 °C. The electrical properties of the Pt/SBT/HfO 2 /SiON/Si FeFET were compared with those of reference FETs, i.e. Pt/SBT/HfO 2 gate stacks formed on Si substrates subjected to various treatments: SiN x /Si formed by RTN, SiO 2 /Si formed by RTO and untreated Si. The Pt/SBT/HfO 2 /SiON/Si FeFET had a larger memory window than all the other reference FeFETs, particularly at low operation voltages when the RTN temperature was 1050 °C

  15. Voltage regulation and power losses reduction in a wind farm integrated MV distribution network

    Science.gov (United States)

    Fandi, Ghaeth; Igbinovia, Famous Omar; Tlusty, Josef; Mahmoud, Rateb

    2018-01-01

    A medium-voltage (MV) wind production system is proposed in this paper. The system applies a medium-voltage permanent magnet synchronous generator (PMSG) as well as MV interconnection and distribution networks. The simulation scheme of an existing commercial electric-power system (Case A) and a proposed wind farm with a gearless PMSG insulated gate bipolar transistor (IGBT) power electronics converter scheme (Case B) is compared. The analyses carried out in MATLAB/Simulink environment shows an enhanced voltage profile and reduced power losses, thus, efficiency in installed IGBT power electronics devices in the wind farm. The resulting wind energy transformation scheme is a simple and controllable medium voltage application since it is not restrained by the IGBT power electronics voltage source converter (VSC) arrangement. Active and reactive power control is made possible with the aid of the gearless PMSG IGBT power converters.

  16. Mechanism of improving forward and reverse blocking voltages in AlGaN/GaN HEMTs by using Schottky drain

    International Nuclear Information System (INIS)

    Zhao Sheng-Lei; Mi Min-Han; Luo Jun; Wang Yi; Dai Yang; Zhang Jin-Cheng; Ma Xiao-Hua; Hao Yue; Hou Bin

    2014-01-01

    In this paper, we demonstrate that a Schottky drain can improve the forward and reverse blocking voltages (BVs) simultaneously in AlGaN/GaN high-electron mobility transistors (HEMTs). The mechanism of improving the two BVs is investigated by analysing the leakage current components and by software simulation. The forward BV increases from 72 V to 149 V due to the good Schottky contact morphology. During the reverse bias, the buffer leakage in the Ohmicdrain HEMT increases significantly with the increase of the negative drain bias. For the Schottky-drain HEMT, the buffer leakage is suppressed effectively by the formation of the depletion region at the drain terminal. As a result, the reverse BV is enhanced from −5 V to −49 V by using a Schottky drain. Experiments and the simulation indicate that a Schottky drain is desirable for power electronic applications. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  17. Improved organic thin-film transistor performance using novel self-assembled monolayers

    Science.gov (United States)

    McDowell, M.; Hill, I. G.; McDermott, J. E.; Bernasek, S. L.; Schwartz, J.

    2006-02-01

    Pentacene-based organic thin-film transistors have been fabricated using a phosphonate-linked anthracene self-assembled monolayer as a buffer between the silicon dioxide gate dielectric and the active pentacene channel region. Vast improvements in the subthreshold slope and threshold voltage are observed compared to control devices fabricated without the buffer. Both observations are consistent with a greatly reduced density of charge trapping states at the semiconductor-dielectric interface effected by introduction of the self-assembled monolayer.

  18. Modelling, development and optimization of integrated power LDMOS transistor. Performance limits in terms of energy; Modelisation, conception et optimisation de composant de puissance lateral DMOS integre. Etude des limites de performance en energie

    Energy Technology Data Exchange (ETDEWEB)

    Farenc, D.

    1997-12-16

    Technologies for Smart Power Integrated Circuits combine into a single chip Bipolar and CMOS transistors, plus power with lateral or vertical DMOS transistors. Complexity which has been increasing dramatically since the mid-80`s has allowed to integrate, into a single monolithic solution, entire systems. This thesis deals with the modelling, conception and test of the power integrated LDMOS transistor. The power LDMOS transistor is used as a switching device. It is characterized by two parameters which are the Specific On-resistance R{sub sp} and the breakdown voltage BV{sub DSS}. The LDMOS transistor developed for the new Smart Power technology exhibits a Specific On-resistance of 200 m{Omega}{sup *}mm{sup 2} and a breakdown voltage of 60 V. This device is dedicated to automotive applications. A reduction of the power device which is achieved with a low Specific On-resistance puts forward new issues such as the maximum Energy capability. When the power device is switched-off on an inductive load, a certain amount of energy is dissipated; if it is beyond a certain limit, the device is destroyed. Our goal is to determine the energy limits which are associated with our new Power integrated LDMOS transistor. (author) 28 refs.

  19. Optimization of Contact Force and Pull-in Voltage for Series based MEMS Switch

    Directory of Open Access Journals (Sweden)

    Abhijeet KSHIRSAGAR

    2010-04-01

    Full Text Available Cantilever based metal-to-metal contact type MEMS series switch has many applications namely in RF MEMS, Power MEMS etc. A typical MEMS switch consists of a cantilever as actuating element to make the contact between the two metal terminals of the switch. The cantilever is pulled down by applying a pull-in voltage to the control electrode that is located below the middle portion of the cantilever while only the tip portion of the cantilever makes contact between the two terminals. Detailed analysis of bending of the cantilever for different pull-in voltages reveals some interesting facts. At low pull-in voltage the cantilever tip barely touches the two terminals, thus resulting in very less contact area. To increase contact area a very high pull-in voltage is applied, but it lifts the tip from the free end due to concave curving of the cantilever in the middle region of the cantilever where the electrode is located. Again it results in less contact area. Furthermore, the high pull-in voltage produces large stress at the base of the cantilever close to the anchor. Therefore, an optimum, pull-in voltage must exist at which the concave curving is eliminated and contact area is maximum. In this paper authors report the finding of optimum contact force and pull-in voltage.

  20. New series half-bridge converters with the balance input split capacitor voltages

    Science.gov (United States)

    Lin, Bor-Ren; Chiang, Huann-Keng; Wang, Shang-Lun

    2016-03-01

    This article presents a new dc/dc converter to perform the main functions of zero voltage switching (ZWS), low converter size, high switching frequency and low-voltage stress. Metal-oxide-semiconductor field-effect transistors (MOSFETs) with high switching frequency are used to reduce the converter size and increase circuit efficiency. To overcome low-voltage stress and high turn-on resistance of MOSFETs, the series half-bridge topology is adopted in the proposed converter. Hence, the low-voltage stress MOSFETs can be used for medium-input voltage applications. The asymmetric pulse-width modulation is used to generate the gating signals and achieve the ZWS. On the secondary side, the parallel connection of two diode rectifiers is adopted to reduce the current rating of passive components. On the primary side, the series connection of two transformers is used to balance two output inductor currents. Two flying capacitors are used to automatically balance the input split capacitor voltages. Finally, experiments with 1000 W rated power are performed to verify the theoretical analysis and the effectiveness of proposed converter.