A graphene Zener-Klein transistor cooled by a hyperbolic substrate

Science.gov (United States)

Yang, Wei; Berthou, Simon; Lu, Xiaobo; Wilmart, Quentin; Denis, Anne; Rosticher, Michael; Taniguchi, Takashi; Watanabe, Kenji; Fève, Gwendal; Berroir, Jean-Marc; Zhang, Guangyu; Voisin, Christophe; Baudin, Emmanuel; Plaçais, Bernard

2018-01-01

The engineering of cooling mechanisms is a bottleneck in nanoelectronics. Thermal exchanges in diffusive graphene are mostly driven by defect-assisted acoustic phonon scattering, but the case of high-mobility graphene on hexagonal boron nitride (hBN) is radically different, with a prominent contribution of remote phonons from the substrate. Bilayer graphene on a hBN transistor with a local gate is driven in a regime where almost perfect current saturation is achieved by compensation of the decrease in the carrier density and Zener-Klein tunnelling (ZKT) at high bias. Using noise thermometry, we show that the ZKT triggers a new cooling pathway due to the emission of hyperbolic phonon polaritons in hBN by out-of-equilibrium electron-hole pairs beyond the super-Planckian regime. The combination of ZKT transport and hyperbolic phonon polariton cooling renders graphene on BN transistors a valuable nanotechnology for power devices and RF electronics.

High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

NARCIS (Netherlands)

Houin, G.J.R.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

2016-01-01

The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance

Suppression of self-heating effect in AlGaN/GaN high electron mobility transistors by substrate-transfer technology using h-BN

International Nuclear Information System (INIS)

Hiroki, Masanobu; Kumakura, Kazuhide; Kobayashi, Yasuyuki; Akasaka, Tetsuya; Makimoto, Toshiki; Yamamoto, Hideki

2014-01-01

We fabricated AlGaN/GaN high electron mobility transistors (HEMTs) on h-BN/sapphire substrates and transferred them from the host substrates to copper plates using h-BN as a release layer. In current–voltage characteristics, the saturation drain current decreased by about 30% under a high-bias condition before release by self-heating effect. In contrast, after transfer, the current decrement was as small as 8% owing to improved heat dissipation: the device temperature increased to 50 °C in the as-prepared HEMT, but only by several degrees in the transferred HEMT. An effective way to improve AlGaN/GaN HEMT performance by a suppression of self-heating effect has been demonstrated

Suppression of self-heating effect in AlGaN/GaN high electron mobility transistors by substrate-transfer technology using h-BN

Energy Technology Data Exchange (ETDEWEB)

Hiroki, Masanobu, E-mail: hiroki.masanobu@lab.ntt.co.jp; Kumakura, Kazuhide; Kobayashi, Yasuyuki; Akasaka, Tetsuya; Makimoto, Toshiki; Yamamoto, Hideki [NTT Basic Research Laboratories, NTT Corporation 3-1 Morinosato Wakamiya, Atsugi-shi 243-0198 (Japan)

2014-11-10

We fabricated AlGaN/GaN high electron mobility transistors (HEMTs) on h-BN/sapphire substrates and transferred them from the host substrates to copper plates using h-BN as a release layer. In current–voltage characteristics, the saturation drain current decreased by about 30% under a high-bias condition before release by self-heating effect. In contrast, after transfer, the current decrement was as small as 8% owing to improved heat dissipation: the device temperature increased to 50 °C in the as-prepared HEMT, but only by several degrees in the transferred HEMT. An effective way to improve AlGaN/GaN HEMT performance by a suppression of self-heating effect has been demonstrated.

Low-voltage protonic/electronic hybrid indium zinc oxide synaptic transistors on paper substrates

International Nuclear Information System (INIS)

Wu, Guodong; Wan, Changjin; Wan, Qing; Zhou, Jumei; Zhu, Liqiang

2014-01-01

Low-voltage (1.5 V) indium zinc oxide (IZO)-based electric-double-layer (EDL) thin-film transistors (TFTs) gated by nanogranular proton conducting SiO 2 electrolyte films are fabricated on paper substrates. Both enhancement-mode and depletion-mode operation are obtained by tuning the thickness of the IZO channel layer. Furthermore, such flexible IZO protonic/electronic hybrid EDL TFTs can be used as artificial synapses, and synaptic stimulation response and short-term synaptic plasticity function are demonstrated. The protonic/electronic hybrid EDL TFTs on paper substrates proposed here are promising for low-power flexible paper electronics, artificial synapses and bioelectronics. (paper)

Impact of substrate on performance of band gap engineered graphene field effect transistor

Science.gov (United States)

Tiwari, Durgesh Laxman; Sivasankaran, K.

2018-01-01

In this paper, we investigate the graphene field effect transistor (G-FET) to enhance the drain current saturation and to minimize the drain conductance (gd) using numerical simulation. This work focus on suppressing the drain conductance using silicon substrate. We studied the impact of different substrate on the performance of band gap engineered G-FET device. We used a non-equilibrium green function with mode space (NEGF_MS) to model the transport behavior of carriers for 10 nm channel length G-FET device. We compared the drain current saturation of G-FET at higher drain voltage regime on silicon, SiC, and the SiO2 substrate. This paper clearly demonstrates the effect of substrate on an electric field near drain region of G-FET device. It is shown that the substrate of G-FET is not only creating a band gap in graphene, which is important for current saturation and gd minimization, but also selection of suitable substrate can suppress generation of carrier concentration near drain region is also important.

Substrate-free ultra-flexible organic field-effect transistors and five-stage ring oscillators.

Science.gov (United States)

Zhang, Lei; Wang, Hanlin; Zhao, Yan; Guo, Yunlong; Hu, Wenping; Yu, Gui; Liu, Yunqi

2013-10-11

Freestanding, substrate-free organic field-effect transistors and organic circuits with a nominal thickness of 320 nm are demonstrated by using a simple water-floatation method. The devices work well in freestanding status, attached on banknotes, or bent over the blade of a knife. The ultralight devices with extreme bending stability indicate a bright future for organic electronics. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Alumina nanoparticle/polymer nanocomposite dielectric for flexible amorphous indium-gallium-zinc oxide thin film transistors on plastic substrate with superior stability

Energy Technology Data Exchange (ETDEWEB)

Lai, Hsin-Cheng [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Pei, Zingway, E-mail: zingway@dragon.nchu.edu.tw [Department of Electrical Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China); Center of Nanoscience and Nanotechnology, National Chung Hsing University, Taichung 40227, Taiwan (China); Jian, Jyun-Ruri; Tzeng, Bo-Jie [Graduate Institute of Optoelectronic Engineering, National Chung Hsing University, Taichung 40227, Taiwan (China)

2014-07-21

In this study, the Al{sub 2}O{sub 3} nanoparticles were incorporated into polymer as a nono-composite dielectric for used in a flexible amorphous Indium-Gallium-Zinc Oxide (a-IGZO) thin-film transistor (TFT) on a polyethylene naphthalate substrate by solution process. The process temperature was well below 100 °C. The a-IGZO TFT exhibit a mobility of 5.13 cm{sup 2}/V s on the flexible substrate. After bending at a radius of 4 mm (strain = 1.56%) for more than 100 times, the performance of this a-IGZO TFT was nearly unchanged. In addition, the electrical characteristics are less altered after positive gate bias stress at 10 V for 1500 s. Thus, this technology is suitable for use in flexible displays.

Laser-Printed Organic Thin-Film Transistors

KAUST Repository

Diemer, Peter J.

2017-09-20

Solution deposition of organic optoelectronic materials enables fast roll-to-roll manufacturing of photonic and electronic devices on any type of substrate and at low cost. But controlling the film microstructure when it crystallizes from solution can be challenging. This represents a major limitation of this technology, since the microstructure, in turn, governs the charge transport properties of the material. Further, the solvents typically used are hazardous, which precludes their incorporation in large-scale manufacturing processes. Here, the first ever organic thin-film transistor fabricated with an electrophotographic laser printing process using a standard office laser printer is reported. This completely solvent-free additive manufacturing method allows for simultaneous deposition, purification, and patterning of the organic semiconductor layer. Laser-printed transistors using triisopropylsilylethynyl pentacene as the semiconductor layer are realized on flexible substrates and characterized, making this a successful first demonstration of the potential of laser printing of organic semiconductors.

High performance organic transistor active-matrix driver developed on paper substrate

Science.gov (United States)

Peng, Boyu; Ren, Xiaochen; Wang, Zongrong; Wang, Xinyu; Roberts, Robert C.; Chan, Paddy K. L.

2014-09-01

The fabrication of electronic circuits on unconventional substrates largely broadens their application areas. For example, green electronics achieved through utilization of biodegradable or recyclable substrates, can mitigate the solid waste problems that arise at the end of their lifespan. Here, we combine screen-printing, high precision laser drilling and thermal evaporation, to fabricate organic field effect transistor (OFET) active-matrix (AM) arrays onto standard printer paper. The devices show a mobility and on/off ratio as high as 0.56 cm2V-1s-1 and 109 respectively. Small electrode overlap gives rise to a cut-off frequency of 39 kHz, which supports that our AM array is suitable for novel practical applications. We demonstrate an 8 × 8 AM light emitting diode (LED) driver with programmable scanning and information display functions. The AM array structure has excellent potential for scaling up.

Report on the results of research and development under a consignment from NEDO on deca-nano quantum integrating transistor substrate technologies; 1997 nendo sangyo kagaku gijutsu kenkyu kaihatsu jigyo Shin energy Sangyo Gijutsu Sogo Kaihatsu Kiko itaku. Deca-nano ryoshi shusekika soshi kiban gijutsu no kenkyu kaihatsu seika hokokusho

Energy Technology Data Exchange (ETDEWEB)

NONE

1998-03-01

Researches have been conducted on deca-nano quantum integrating transistor substrate technologies, and developments were made on a three-dimensional device simulator which can be used in deca-nano domains, and a circuit simulator to have quantifying function transistors coexist with silicon semiconductor integrated circuits. The researches were intended to develop a simulator capable of analyzing properties of very small silicon and compound semiconductor devices in deca-nano domains. The researches discussed the applicability of conventional simulators, calculated quantum levels in a three-dimensional hetero structure, and resulted in development of an electron wave propagation simulator in optional two-dimensional shapes, a quantum Monte Carlo simulator, and a three-dimensional semiconductor device simulator with quantum correction. On the other hand, in order to estimate characteristics of a hybrid circuit in which single electron transistors coexist with conventional transistors such as CMOS transistors, a single electron hybrid circuit simulator was developed. The development indicated that a CMOS-SET fused memory is promising as a future LSI memory. 22 refs., 116 figs., 3 tabs.

Infrared-transmittance tunable metal-insulator conversion device with thin-film-transistor-type structure on a glass substrate

Directory of Open Access Journals (Sweden)

Takayoshi Katase

2017-05-01

Full Text Available Infrared (IR transmittance tunable metal-insulator conversion was demonstrated on a glass substrate by using thermochromic vanadium dioxide (VO2 as the active layer in a three-terminal thin-film-transistor-type device with water-infiltrated glass as the gate insulator. Alternative positive/negative gate-voltage applications induce the reversible protonation/deprotonation of a VO2 channel, and two-orders of magnitude modulation of sheet-resistance and 49% modulation of IR-transmittance were simultaneously demonstrated at room temperature by the metal-insulator phase conversion of VO2 in a non-volatile manner. The present device is operable by the room-temperature protonation in an all-solid-state structure, and thus it will provide a new gateway to future energy-saving technology as an advanced smart window.

Design and simulation of a novel GaN based resonant tunneling high electron mobility transistor on a silicon substrate

International Nuclear Information System (INIS)

Chowdhury, Subhra; Biswas, Dhrubes; Chattaraj, Swarnabha

2015-01-01

For the first time, we have introduced a novel GaN based resonant tunneling high electron mobility transistor (RTHEMT) on a silicon substrate. A monolithically integrated GaN based inverted high electron mobility transistor (HEMT) and a resonant tunneling diode (RTD) are designed and simulated using the ATLAS simulator and MATLAB in this study. The 10% Al composition in the barrier layer of the GaN based RTD structure provides a peak-to-valley current ratio of 2.66 which controls the GaN based HEMT performance. Thus the results indicate an improvement in the current–voltage characteristics of the RTHEMT by controlling the gate voltage in this structure. The introduction of silicon as a substrate is a unique step taken by us for this type of RTHEMT structure. (paper)

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

Science.gov (United States)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Impact of barrier thickness on transistor performance in AlN/GaN high electron mobility transistors grown on free-standing GaN substrates

International Nuclear Information System (INIS)

Deen, David A.; Storm, David F.; Meyer, David J.; Bass, Robert; Binari, Steven C.; Gougousi, Theodosia; Evans, Keith R.

2014-01-01

A series of six ultrathin AlN/GaN heterostructures with varied AlN thicknesses from 1.5–6 nm have been grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. High electron mobility transistors (HEMTs) were fabricated from the set in order to assess the impact of barrier thickness and homo-epitaxial growth on transistor performance. Room temperature Hall characteristics revealed mobility of 1700 cm 2 /V s and sheet resistance of 130 Ω/□ for a 3 nm thick barrier, ranking amongst the lowest room-temperature sheet resistance values reported for a polarization-doped single heterostructure in the III-Nitride family. DC and small signal HEMT electrical characteristics from submicron gate length HEMTs further elucidated the effect of the AlN barrier thickness on device performance.

Impact of barrier thickness on transistor performance in AlN/GaN high electron mobility transistors grown on free-standing GaN substrates

Energy Technology Data Exchange (ETDEWEB)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Meyer, David J.; Bass, Robert; Binari, Steven C. [Electronics Science and Technology Division, Naval Research Laboratory, Washington, DC 20375-5347 (United States); Gougousi, Theodosia [Physics Department, University of Maryland Baltimore County, Baltimore, Maryland 21250 (United States); Evans, Keith R. [Kyma Technologies, Raleigh, North Carolina 27617 (United States)

2014-09-01

A series of six ultrathin AlN/GaN heterostructures with varied AlN thicknesses from 1.5–6 nm have been grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. High electron mobility transistors (HEMTs) were fabricated from the set in order to assess the impact of barrier thickness and homo-epitaxial growth on transistor performance. Room temperature Hall characteristics revealed mobility of 1700 cm{sup 2}/V s and sheet resistance of 130 Ω/□ for a 3 nm thick barrier, ranking amongst the lowest room-temperature sheet resistance values reported for a polarization-doped single heterostructure in the III-Nitride family. DC and small signal HEMT electrical characteristics from submicron gate length HEMTs further elucidated the effect of the AlN barrier thickness on device performance.

X-ray imager using solution processed organic transistor arrays and bulk heterojunction photodiodes on thin, flexible plastic substrate

NARCIS (Netherlands)

Gelinck, G.H.; Kumar, A.; Moet, D.; Steen, J.L. van der; Shafique, U.; Malinowski, P.E.; Myny, K.; Rand, B.P.; Simon, M.; Rütten, W.; Douglas, A.; Jorritsma, J.; Heremans, P.L.; Andriessen, H.A.J.M.

2013-01-01

We describe the fabrication and characterization of large-area active-matrix X-ray/photodetector array of high quality using organic photodiodes and organic transistors. All layers with the exception of the electrodes are solution processed. Because it is processed on a very thin plastic substrate

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

Science.gov (United States)

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Transistors using crystalline silicon devices on glass

Science.gov (United States)

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Total dose effects on elementary transistors of a comparator in bipolar technology

International Nuclear Information System (INIS)

Sarrabayrouse, G.; Guerre, F.X.

1995-01-01

In the present work we investigate elementary transistors behaviour of an Integrated Circuit using junction isolation bipolar technology. Polarization conditions and dose rate effects on the main elementary transistor types are analysed. Furthermore, the IC electronic function degradations are studied. Finally, a comparison between the function degradations and the elementary component ones is attempted. (author)

Direct-current substrate bias effects on amorphous silicon sputter-deposited films for thin film transistor fabrication

International Nuclear Information System (INIS)

Jun, Seung-Ik; Rack, Philip D.; McKnight, Timothy E.; Melechko, Anatoli V.; Simpson, Michael L.

2005-01-01

The effect that direct current (dc) substrate bias has on radio frequency-sputter-deposited amorphous silicon (a-Si) films has been investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFTs) that were completely sputter deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film

Organic field-effect transistors with surface modification by using a PVK buffer layer on flexible substrates

Energy Technology Data Exchange (ETDEWEB)

Hyung, Gun Woo; Lee, Dong Hyung; Koo, Ja Ryong; Kim, Young Kwan [Hongik University, Seoul (Korea, Republic of); Park, Jae Hoon [Electronics and Telecommunications Research Institute, Daejeon (Korea, Republic of)

2012-11-15

We have fabricated pentacene thin-film transistors (TFTs) with a gate dielectric such as crosslinked poly(vinyl alcohol) (c-PVA), with poly(9-vinylcarbazole) (PVK) buffer layer on a polyethersulfone (PES) flexible substrate, and with substrate heating at a temperature below 120 .deg. C, and we demonstrated the possibility of using an organic gate dielectric layer as a potential pentacene TFT with a PVK buffer layer for low-voltage operation on a plastic substrate. We report the excellent electrical properties of organic TFTs with a PVK buffer layer. The PVK buffer layer improves the performance of the devices and reduces the operating voltage of the devices. Our pentacene TFTs can be fabricated with mobilities > 2.54 cm{sup 2}/Vs and on/off current ratios > 7.5E5 and with flexible organic dielectrics and substrates.

Free-Standing Organic Transistors and Circuits with Sub-Micron Thicknesses

Science.gov (United States)

Fukuda, Kenjiro; Sekine, Tomohito; Shiwaku, Rei; Morimoto, Takuya; Kumaki, Daisuke; Tokito, Shizuo

2016-01-01

The realization of wearable electronic devices with extremely thin and flexible form factors has been a major technological challenge. While substrates typically limit the thickness of thin-film electronic devices, they are usually necessary for their fabrication and functionality. Here we report on ultra-thin organic transistors and integrated circuits using device components whose substrates that have been removed. The fabricated organic circuits with total device thicknesses down to 350 nm have electrical performance levels close to those fabricated on conventional flexible substrates. Moreover, they exhibit excellent mechanical robustness, whereby their static and dynamic electrical characteristics do not change even under 50% compressive strain. Tests using systematically applied compressive strains reveal that these free-standing organic transistors possess anisotropic mechanical stability, and a strain model for a multilayer stack can be used to describe the strain in this sort of ultra-thin device. These results show the feasibility of ultimate-thin organic electronic devices using free-standing constructions. PMID:27278828

Charge collection mechanisms in MOS/SOI transistors irradiated by energetic heavy ions

International Nuclear Information System (INIS)

Musseau, O.; Leray, J.L.; Ferlet, V.; Umbert, A.; Coic, Y.M.; Hesto, P.

1991-01-01

We have investigated with both experimental and numerical methods (Monte Carlo and drift-diffusion models) various charge collection mechanisms in NMOS/SOI transistors irradiated by single energetic heavy ions. Our physical interpretations of data emphasize the influence of various parasitic structures of the device. Two charge collection mechanisms are detailed: substrate funneling in buried MOS capacitor and latching of the parasitic bipolar transistor. Based on carrier transport and charge collection, the sensitivity of future scaled down CMOS/SOI technologies is finally discussed

Strain-effect transistors: Theoretical study on the effects of external strain on III-nitride high-electron-mobility transistors on flexible substrates

Energy Technology Data Exchange (ETDEWEB)

Shervin, Shahab; Asadirad, Mojtaba [Department of Mechanical Engineering, University of Houston, Houston, Texas 77204-4006 (United States); Materials Science and Engineering Program, University of Houston, Houston, Texas 77204 (United States); Kim, Seung-Hwan; Ravipati, Srikanth; Lee, Keon-Hwa [Department of Mechanical Engineering, University of Houston, Houston, Texas 77204-4006 (United States); Bulashevich, Kirill [STR Group, Inc., Engels av. 27, P.O. Box 89, 194156, St. Petersburg (Russian Federation); Ryou, Jae-Hyun, E-mail: jryou@uh.edu [Department of Mechanical Engineering, University of Houston, Houston, Texas 77204-4006 (United States); Materials Science and Engineering Program, University of Houston, Houston, Texas 77204 (United States); Texas Center for Superconductivity at the University of Houston (TcSUH), University of Houston, Houston, Texas 77204 (United States)

2015-11-09

This paper presents strain-effect transistors (SETs) based on flexible III-nitride high-electron-mobility transistors (HEMTs) through theoretical calculations. We show that the electronic band structures of InAlGaN/GaN thin-film heterostructures on flexible substrates can be modified by external bending with a high degree of freedom using polarization properties of the polar semiconductor materials. Transfer characteristics of the HEMT devices, including threshold voltage and transconductance, are controlled by varied external strain. Equilibrium 2-dimensional electron gas (2DEG) is enhanced with applied tensile strain by bending the flexible structure with the concave-side down (bend-down condition). 2DEG density is reduced and eventually depleted with increasing compressive strain in bend-up conditions. The operation mode of different HEMT structures changes from depletion- to enchantment-mode or vice versa depending on the type and magnitude of external strain. The results suggest that the operation modes and transfer characteristics of HEMTs can be engineered with an optimum external bending strain applied in the device structure, which is expected to be beneficial for both radio frequency and switching applications. In addition, we show that drain currents of transistors based on flexible InAlGaN/GaN can be modulated only by external strain without applying electric field in the gate. The channel conductivity modulation that is obtained by only external strain proposes an extended functional device, gate-free SETs, which can be used in electro-mechanical applications.

1/f Noise Characterization in CMOS Transistors in 0.13μm Technology

DEFF Research Database (Denmark)

Citakovic, J.; Stenberg, L J; Andreani, Pietro

2006-01-01

Low-frequency noise has been studied on a set of n- and p-channel CMOS transistors fabricated in a 0.13μm technology. Noise measurements have been performed on transistors with different gate lengths operating under wide bias conditions, ranging from weak to strong inversion. Noise origin has been...

Doped Organic Transistors.

Science.gov (United States)

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates.

Science.gov (United States)

Tetzner, Kornelius; Bose, Indranil R; Bock, Karlheinz

2014-10-29

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

Array of organic thin film transistors integrated with organic light emitting diodes on a plastic substrate

International Nuclear Information System (INIS)

Ryu, Gi-Seong; Choe, Ki-Beom; Song, Chung-Kun

2006-01-01

In order to demonstrate the possible application of an organic thin film transistor (OTFT) to a flexible active matrix organic light emitting diode (OLED) an array of 64 x 64 pixels was fabricated on a 4-in. size poly-ethylene-terephehalate substrate. Each pixel was composed of one OTFT integrated with one OLED. OTFTs successfully drove OLEDs by varying current in a wide range and some images were displayed on the array by emitting green light. The OTFTs used poly(4-vinylphenol) for the gate and pentacene for the semiconductor taking account compatibility with the PET substrate. The average mobility in the array was 0.2 cm 2 /V.s, which was reduced from 1.0 cm 2 /V.s in a single OTFT, and its variation over the entire substrate was 10%

Electrolyte-Sensing Transistor Decals Enabled by Ultrathin Microbial Nanocellulose

Science.gov (United States)

Yuen, Jonathan D.; Walper, Scott A.; Melde, Brian J.; Daniele, Michael A.; Stenger, David A.

2017-01-01

We report an ultra-thin electronic decal that can simultaneously collect, transmit and interrogate a bio-fluid. The described technology effectively integrates a thin-film organic electrochemical transistor (sensing component) with an ultrathin microbial nanocellulose wicking membrane (sample handling component). As far as we are aware, OECTs have not been integrated in thin, permeable membrane substrates for epidermal electronics. The design of the biocompatible decal allows for the physical isolation of the electronics from the human body while enabling efficient bio-fluid delivery to the transistor via vertical wicking. High currents and ON-OFF ratios were achieved, with sensitivity as low as 1 mg·L-1.

Biosensors based on enzyme field-effect transistors for determination of some substrates and inhibitors.

Science.gov (United States)

Dzyadevych, Sergei V; Soldatkin, Alexey P; Korpan, Yaroslav I; Arkhypova, Valentyna N; El'skaya, Anna V; Chovelon, Jean-Marc; Martelet, Claude; Jaffrezic-Renault, Nicole

2003-10-01

This paper is a review of the authors' publications concerning the development of biosensors based on enzyme field-effect transistors (ENFETs) for direct substrates or inhibitors analysis. Such biosensors were designed by using immobilised enzymes and ion-selective field-effect transistors (ISFETs). Highly specific, sensitive, simple, fast and cheap determination of different substances renders them as promising tools in medicine, biotechnology, environmental control, agriculture and the food industry. The biosensors based on ENFETs and direct enzyme analysis for determination of concentrations of different substrates (glucose, urea, penicillin, formaldehyde, creatinine, etc.) have been developed and their laboratory prototypes were fabricated. Improvement of the analytical characteristics of such biosensors may be achieved by using a differential mode of measurement, working solutions with different buffer concentrations and specific agents, negatively or positively charged additional membranes, or genetically modified enzymes. These approaches allow one to decrease the effect of the buffer capacity influence on the sensor response in an aim to increase the sensitivity of the biosensors and to extend their dynamic ranges. Biosensors for the determination of concentrations of different toxic substances (organophosphorous pesticides, heavy metal ions, hypochlorite, glycoalkaloids, etc.) were designed on the basis of reversible and/or irreversible enzyme inhibition effect(s). The conception of an enzymatic multibiosensor for the determination of different toxic substances based on the enzyme inhibition effect is also described. We will discuss the respective advantages and disadvantages of biosensors based on the ENFETs developed and also demonstrate their practical application.

Monolithic acoustic graphene transistors based on lithium niobate thin film

Science.gov (United States)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates

Directory of Open Access Journals (Sweden)

Kornelius Tetzner

2014-10-01

Full Text Available In this work, the insulating properties of poly(4-vinylphenol (PVP and SU-8 (MicroChem, Westborough, MA, USA dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics on Flexible Substrates

Science.gov (United States)

Tetzner, Kornelius; Bose, Indranil R.; Bock, Karlheinz

2014-01-01

In this work, the insulating properties of poly(4-vinylphenol) (PVP) and SU-8 (MicroChem, Westborough, MA, USA) dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP) using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor. PMID:28788243

Characteristics of Schottky-barrier source/drain metal-oxide-polycrystalline thin-film transistors on glass substrates

International Nuclear Information System (INIS)

Jung, Seung-Min; Cho, Won-Ju; Jung, Jong-Wan

2012-01-01

Polycrystalline-silicon (poly-Si) Schottky-barrier thin-film transistors (SB-TFTs) with Pt-silicided source /drain junctions were fabricated on glass substrates, and the electrical characteristics were examined. The amorphous silicon films on glass substrates were converted into high-quality poly-Si by using excimer laser annealing (ELA) and solid phase crystallization (SPC) methods. The crystallinity of poly-Si was analyzed by using scanning electron microscopy, transmission electron microscopy, and X-ray diffraction analysis. The silicidation process was optimized by measuring the electrical characteristics of the Pt-silicided Schottky diodes. The performances of Pt-silicided SB-TFTs using poly-Si films on glass substrates and crystallized by using ELA and SPC were demonstrated. The SB-TFTs using the ELA poly-Si film demonstrated better electrical performances such as higher mobility (22.4 cm 2 /Vs) and on/off current ratio (3 x 10 6 ) and lower subthreshold swing value (120 mV/dec) than the SPC poly-Si films.

Fabrication of air-stable n-type carbon nanotube thin-film transistors on flexible substrates using bilayer dielectrics.

Science.gov (United States)

Li, Guanhong; Li, Qunqing; Jin, Yuanhao; Zhao, Yudan; Xiao, Xiaoyang; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2015-11-14

Single-walled carbon nanotube (SWNT) thin-film transistors hold great potential for flexible electronics. However, fabrication of air-stable n-type devices by methods compatible with standard photolithography on flexible substrates is challenging. Here, we demonstrated that by using a bilayer dielectric structure of MgO and atomic layer deposited (ALD) Al2O3 or HfO2, air-stable n-type devices can be obtained. The mechanism for conduction type conversion was elucidated and attributed to the hole depletion in SWNT, the decrease of the trap state density by MgO assimilating adsorbed water molecules in the vicinity of SWNT, and the energy band bending because of the positive fixed charges in the ALD layer. The key advantage of the method is the relatively low temperature (120 or 90 °C) required here for the ALD process because we need not employ this step to totally remove the absorbates on the SWNTs. This advantage facilitates the integration of both p-type and n-type transistors through a simple lift off process and compact CMOS inverters were demonstrated. We also demonstrated that the doping of SWNTs in the channel plays a more important role than the Schottky barriers at the metal contacts in carbon nanotube thin-film transistors, unlike the situation in individual SWNT-based transistors.

Patterning of metallic electrodes on flexible substrates for organic thin-film transistors using a laser thermal printing method

International Nuclear Information System (INIS)

Chen, Kun-Tso; Lin, Yu-Hsuan; Ho, Jeng-Rong; Chen, Chih-Kant; Liu, Sung-Ho; Liao, Jin-Long; Cheng, Hua-Chi

2011-01-01

We report on a laser thermal printing method for transferring patterned metallic thin films on flexible plastic substrates using a pulsed CO 2 laser. Aluminium and silver line patterns, with micrometre scale resolution on poly(ethylene terephthalate) substrates, are shown. The printed electrodes demonstrate good conductivity and fulfil the properties for bottom-contact organic thin-film transistors. In addition to providing the energy for transferring the film, the absorption of laser light results in a rise in the temperature of the film and the substrate. This also further anneals the film and softens the plastic substrate. Consequently, it is possible to obtain a film with better surface morphology and with its film thickness implanted in part into the plastic surface. This implantation reveals excellent characteristics in adhesion and flexure resistance. Being feasible to various substrates and executable at ambient temperatures renders this approach a potential alternative for patterning metallic electrodes.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

Science.gov (United States)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

The application of orthogonal photolithography to micro-scale organic field effect transistors and complementary inverters on flexible substrate

International Nuclear Information System (INIS)

Jang, Jingon; Song, Younggul; Yoo, Daekyoung; Kim, Dongku; Lee, Hyungwoo; Hong, Seunghun; Lee, Takhee; Oh, Hyuntaek; Lee, Jin-Kyun

2014-01-01

Micro-scale pentacene organic field effect transistors (OFETs) were fabricated on a flexible poly(ethylene terephthalate) (PET) substrate. By applying a highly fluorinated developing solvents and its compatible photoresist materials, it has become possible to make the micro-scale patterning for organic devices using standard photolithography without damaging the underlying polymer layers. The flexible pentacene OFETs with 3 μm-sized channel length exhibited stable electrical characteristics under bent configurations and under a large number of repetitive bending cycles. Furthermore, we demonstrated micro-scale organic complementary inverters on a flexible PET substrate using p-type pentacene and n-type copper hexadecafluorophthalocyanine materials

The application of orthogonal photolithography to micro-scale organic field effect transistors and complementary inverters on flexible substrate

Energy Technology Data Exchange (ETDEWEB)

Jang, Jingon; Song, Younggul; Yoo, Daekyoung; Kim, Dongku; Lee, Hyungwoo; Hong, Seunghun; Lee, Takhee, E-mail: tlee@snu.ac.kr [Department of Physics and Astronomy, and Institute of Applied Physics, Seoul National University, Seoul 151-747 (Korea, Republic of); Oh, Hyuntaek; Lee, Jin-Kyun, E-mail: jkl36@inha.ac.kr [Department of Polymer Science and Engineering, Inha University, Incheon 402-751 (Korea, Republic of)

2014-02-03

Micro-scale pentacene organic field effect transistors (OFETs) were fabricated on a flexible poly(ethylene terephthalate) (PET) substrate. By applying a highly fluorinated developing solvents and its compatible photoresist materials, it has become possible to make the micro-scale patterning for organic devices using standard photolithography without damaging the underlying polymer layers. The flexible pentacene OFETs with 3 μm-sized channel length exhibited stable electrical characteristics under bent configurations and under a large number of repetitive bending cycles. Furthermore, we demonstrated micro-scale organic complementary inverters on a flexible PET substrate using p-type pentacene and n-type copper hexadecafluorophthalocyanine materials.

Development of transparent thin film transistors on PES polymer substrates

International Nuclear Information System (INIS)

Yun, Eui-Jung; Jung, Jin-Woo; Ko, Kyung-Nam; Song, Young-Wook; Nam, Hyoung; Cho, Nam-Ihn

2010-01-01

In this study, we demonstrate ZnO-based transparent thin film transistors (TTFT's) implemented on polyethersulfone (PES) polymer substrates. For the developed TTFT's, radio-frequency magnetron sputter techniques were used to deposit Al-doped ZnO (AZO) at zero oxygen partial pressures for the source, the drain, and the gate-contact electrodes, undoped ZnO at low oxygen partial pressures for the active p-type layer, and SiO 2 for the gate dielectric. The TTFT's were processed at room temperature (RT), except for a 100 .deg. C sputtering step to deposit the AZO source, drain, and gate-contact electrodes. The devices have bottom-gate structures with top contacts, are optically transparent, and operate in an enhancement mode with a threshold voltage of +13 V, a mobility of 0.1 cm 2 /Vs, an on-off ratio of about 0.5 x 10 3 and, a sub-threshold slope of 4.1 V/decade.

Silicon nanowire transistors

CERN Document Server

Bindal, Ahmet

2016-01-01

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

Improving Breakdown Behavior by Substrate Bias in a Novel Double Epi-layer Lateral Double Diffused MOS Transistor

International Nuclear Information System (INIS)

Li Qi; Wang Wei-Dong; Liu Yun; Wei Xue-Ming

2012-01-01

A new lateral double diffused MOS (LDMOS) transistor with a double epitaxial layer formed by an n-type substrate and a p-type epitaxial layer is reported (DEL LDMOS). The mechanism of the improved breakdown characteristic is that the high electric field around the drain is reduced by substrate reverse bias, which causes the redistribution of the bulk electric field in the drift region, and the vertical blocking voltage is shared by the drain side and the source side. The numerical results indicate that the trade-off between breakdown voltage and on-resistance of the proposed device is improved greatly in comparison to that of the conventional LDMOS. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

Science.gov (United States)

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

A comparative study of graphene and graphite-based field effect transistor on flexible substrate

Science.gov (United States)

Bhatt, Kapil; Rani, Cheenu; Vaid, Monika; Kapoor, Ankit; Kumar, Pramod; Kumar, Sandeep; Shriwastawa, Shilpi; Sharma, Sandeep; Singh, Randhir; Tripathi, C. C.

2018-06-01

In the present era, there has been a great demand of cost-effective, biodegradable, flexible and wearable electronics which may open the gate to many applications like flexible displays, RFID tags, health monitoring devices, etc. Due to the versatile nature of plastic substrates, they have been extensively used in packaging, printing, etc. However, the fabrication of electronic devices requires specially prepared substrates with high quality surfaces, chemical compositions and solutions to the related fabrication issues along with its non-biodegradable nature. Therefore, in this report, a cost-effective, biodegradable cellulose paper as an alternative dielectric substrate material for the fabrication of flexible field effect transistor (FET) is presented. The graphite and liquid phase exfoliated graphene have been used as the material for the realisation of source, drain and channel on cellulose paper substrate for its comparative analysis. The mobility of fabricated FETs was calculated to be 83 cm2/V s (holes) and 33 cm2/V s (electrons) for graphite FET and 100 cm2/V s (holes) and 52 cm2/V s (electrons) for graphene FET, respectively. The output characteristic of the device demonstrates the linear behaviour and a comprehensive increase in conductance as a function of gate voltages. The fabricated FETs may be used for strain sensing, health care monitoring devices, human motion detection, etc.

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

Science.gov (United States)

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

Transfer of Graphene Layers Grown on SiC Wafers to Other Substrates and Their Integration into Field Effect Transistors

Science.gov (United States)

Unarunotai, Sakulsuk; Murata, Yuya; Chialvo, Cesar; Kim, Hoon-Sik; MacLaren, Scott; Mason, Nadya; Petrov, Ivan; Rogers, John

2010-03-01

An approach to produce graphene films by epitaxial growth on silicon carbide substrate is promising, but its current implementation requires the use of SiC as the device substrate. We present a simple method for transferring epitaxial sheets of graphene on SiC to other substrates. The graphene was grown on the (0001) face of 6H-SiC by thermal annealing in a hydrogen atmosphere. Transfer was accomplished using a peeling process with a bilayer film of Gold/polyimide, to yield graphene with square millimeters of coverage on the target substrate. Back gated field-effect transistors fabricated on oxidized silicon substrates with Cr/Au as source-drain electrodes exhibited ambipolar characteristics with hole mobilities of ˜100 cm^2/V-s, and negligible influence of resistance at the contacts. This work was supported by the U.S. DOE, under Award No. DE-FG02-07ER46471, through the Frederick Seitz Materials Research Laboratory at the University of Illinois at Urbana-Champaign.

Tunneling field effect transistor technology

CERN Document Server

Chan, Mansun

2016-01-01

This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs.

Mechanics of silicon nitride thin-film stressors on a transistor-like geometry

Directory of Open Access Journals (Sweden)

S. Reboh

2013-10-01

Full Text Available To understand the behavior of silicon nitride capping etch stopping layer stressors in nanoscale microelectronics devices, a simplified structure mimicking typical transistor geometries was studied. Elastic strains in the silicon substrate were mapped using dark-field electron holography. The results were interpreted with the aid of finite element method modeling. We show, in a counterintuitive sense, that the stresses developed by the film in the vertical sections around the transistor gate can reach much higher values than the full sheet reference. This is an important insight for advanced technology nodes where the vertical contribution of such liners is predominant over the horizontal part.

Improvements in or relating to transistor circuits

International Nuclear Information System (INIS)

Richards, R.F.; Williamson, P.W.

1978-01-01

This invention relates to transistor circuits and in particular to integrated transistor circuits formed on a substrate of semi-conductor material such as silicon. The invention is concerned with providing integrated circuits in which malfunctions caused by the effects of ionising, e.g. nuclear, radiations are reduced. (author)

Advanced organics for electronic substrates and packages

CERN Document Server

Fletcher, Andrew E

1992-01-01

Advanced Organics for Electronic Substrates and Packages provides information on packaging, which is one of the most technologically intensive activities in the electronics industry. The electronics packaging community has realized that while semiconductor devices continue to be improved upon for performance, cost, and reliability, it is the interconnection or packaging of these devices that will limit the performance of the systems. Technology must develop packaging for transistor chips, with high levels of performance and integration providing cooling, power, and interconnection, and yet pre

Process Simulation and Characterization of Substrate Engineered Silicon Thin Film Transistor for Display Sensors and Large Area Electronics

International Nuclear Information System (INIS)

Hashmi, S M; Ahmed, S

2013-01-01

Design, simulation, fabrication and post-process qualification of substrate-engineered Thin Film Transistors (TFTs) are carried out to suggest an alternate manufacturing process step focused on display sensors and large area electronics applications. Damage created by ion implantation of Helium and Silicon ions into single-crystalline n-type silicon substrate provides an alternate route to create an amorphized region responsible for the fabrication of TFT structures with controllable and application-specific output parameters. The post-process qualification of starting material and full-cycle devices using Rutherford Backscattering Spectrometry (RBS) and Proton or Particle induced X-ray Emission (PIXE) techniques also provide an insight to optimize the process protocols as well as their applicability in the manufacturing cycle

InAlAs/InGaAs Pseudomorphic High Eelectron Mobility Transistors Grown by Molecular Beam Epitaxy on the InP Substrate

International Nuclear Information System (INIS)

Huang Jie; Guo Tian-Yi; Zhang Hai-Ying; Xu Jing-Bo; Fu Xiao-Jun; Yang Hao; Niu Jie-Bin

2010-01-01

A novel PMMA/PMGI/ZEP520 trilayer resist electron beam lithograph (EBL) technology is successfully developed and used to fabricate the 150 nm gate-length In 0.7 Ga 0.3 As/In 0.52 Al 0.48 As Pseudomorphic HEMT on an InP substrate, of which the material structure is successfully designed and optimized. A perfect profile of T-gate is successfully obtained. These fabricated devices demonstrate excellent dc and rf characteristics: the transconductance G m , maximum saturation drain-to-source current I DSS , threshold voltage V T , maximum current gain frequency f T derived from h 21 , maximum frequency of oscillation derived from maximum available power gain/maximum stable gain and from unilateral power-gain of metamorphic InGaAs/InAlAs high electron mobility transistors (HEMTs) are 470 mS/mm, 560 mA/mm, −1.0 V, 76 GHz, 135 GHz and 436 GHz, respectively. The excellent high frequency performances promise the possibility of metamorphic HEMTs for millimeter-wave applications. (cross-disciplinary physics and related areas of science and technology)

Electrothermal evaluation of thick GaN epitaxial layers and AlGaN/GaN high-electron-mobility transistors on large-area engineered substrates

Science.gov (United States)

Anderson, Travis J.; Koehler, Andrew D.; Tadjer, Marko J.; Hite, Jennifer K.; Nath, Anindya; Mahadik, Nadeemullah A.; Aktas, Ozgur; Odnoblyudov, Vladimir; Basceri, Cem; Hobart, Karl D.; Kub, Francis J.

2017-12-01

AlGaN/GaN high-electron-mobility transistor (HEMT) device layers were grown by metal organic chemical vapor deposition (MOCVD) on commercial engineered QST™ substrates to demonstrate a path to scalable, cost-effective foundry processing while supporting the thick epitaxial layers required for power HEMT structures. HEMT structures on 150 mm Si substrates were also evaluated. The HEMTs on engineered substrates exhibited material quality, DC performance, and forward blocking performance superior to those of the HEMT on Si. GaN device layers up to 15 µm were demonstrated with a wafer bow of 1 µm, representing the thickest films grown on 150-mm-diameter substrates with low bow to date.

Carbon Based Transistors and Nanoelectronic Devices

Science.gov (United States)

Rouhi, Nima

effect of nanotube network density was explained in detail. On the other hand, graphene transfer technology was explored here as well. Annealing techniques were utilized to deposit clean graphene on arbitrary substrates. Raman spectroscopy and Raman data analysis was used to confirm the clean process. Furthermore, suspended graphene membrane was fabricated using single and multi-layer graphene films. This can make a major impact on graphene based transistors and bio-nano sensors technology.

Vertical organic transistors

International Nuclear Information System (INIS)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-01-01

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted. (topical review)

Vertical organic transistors.

Science.gov (United States)

Lüssem, Björn; Günther, Alrun; Fischer, Axel; Kasemann, Daniel; Leo, Karl

2015-11-11

Organic switching devices such as field effect transistors (OFETs) are a key element of future flexible electronic devices. So far, however, a commercial breakthrough has not been achieved because these devices usually lack in switching speed (e.g. for logic applications) and current density (e.g. for display pixel driving). The limited performance is caused by a combination of comparatively low charge carrier mobilities and the large channel length caused by the need for low-cost structuring. Vertical Organic Transistors are a novel technology that has the potential to overcome these limitations of OFETs. Vertical Organic Transistors allow to scale the channel length of organic transistors into the 100 nm regime without cost intensive structuring techniques. Several different approaches have been proposed in literature, which show high output currents, low operation voltages, and comparatively high speed even without sub-μm structuring technologies. In this review, these different approaches are compared and recent progress is highlighted.

Industrial and scientific technology research and development project in fiscal 1997 commissioned by the New Energy and Industrial Technology Development Organization. Research and development of superconducting materials and transistors (report on overall investigation of superconductive devices); 1997 nendo sangyo kagaku gijutsu kenkyu kaihatsu jigyo Shin energy Sangyo Gijutsu Sogo Kaihatsu Kiko itaku. Chodendo zairyo chodendo soshi no kenkyu kaihatsu (chodendo soshika gijutsu kaihatsu seika hokokusho)

Energy Technology Data Exchange (ETDEWEB)

NONE

1998-03-01

This paper describes development of superconducting new function transistors. Fiscal 1997 as the final year of the project advanced improvement in such transistor-using processes as formation and micro-processing of superconducting thin films to show enhancement in characteristics of high-temperature superconducting transistors and possibility of their application utilizing their high speed motions. Furthermore, fundamental technologies were studied with an aim on junction transistors to be applied as circuits. For field effect transistors, evaluation was performed on critical current distribution of step-type particle boundary junction to make it possible to evaluate characteristics of hundreds of transistors. At the same time, a magnetic flux quantum parametron gate with three-layer structure was fabricated to identify its operation. In superconducting-base transistors, strong reflection was recognized on temperature dependence of permittivity of an Nb-doped strontium titanate substrate used for collectors, by which barrier height was reduced. In the junction transistor and circuit technology, isotropic ramp-edge junctions were fabricated, and so was a frequency divider circuit with single magnetic flux quantum mode operation for evaluating high-speed response characteristics. High time resolution current was observed successfully by using a high-temperature superconducting sampler system. 148 refs., 127 figs., 4 tabs.

Benzocyclobutene (BCB) Polymer as Amphibious Buffer Layer for Graphene Field-Effect Transistor.

Science.gov (United States)

Wu, Yun; Zou, Jianjun; Huo, Shuai; Lu, Haiyan; Kong, Yuecan; Chen, Tangshen; Wu, Wei; Xu, Jingxia

2015-08-01

Owing to the scattering and trapping effects, the interfaces of dielectric/graphene or substrate/graphene can tailor the performance of field-effect transistor (FET). In this letter, the polymer of benzocyclobutene (BCB) was used as an amphibious buffer layer and located at between the layers of substrate and graphene and between the layers of dielectric and graphene. Interestingly, with the help of nonpolar and hydrophobic BCB buffer layer, the large-scale top-gated, chemical vapor deposited (CVD) graphene transistors was prepared on Si/SiO2 substrate, its cutoff frequency (fT) and the maximum cutoff frequency (fmax) of the graphene field-effect transistor (GFET) can be reached at 12 GHz and 11 GHz, respectively.

Significant Improvement of Organic Thin-Film Transistor Mobility Utilizing an Organic Heterojunction Buffer Layer

International Nuclear Information System (INIS)

Pan Feng; Qian Xian-Rui; Huang Li-Zhen; Wang Hai-Bo; Yan Dong-Hang

2011-01-01

High-mobility vanadyl phthalocyanine (VOPc)/5,5‴-bis(4-fluorophenyl)-2,2':5',2″:5″,2‴-quaterthiophene (F2-P4T) thin-film transistors are demonstrated by employing a copper hexadecafluorophthalocyanine (F 16 CuPc)/copper phthalocyanine (CuPc) heterojunction unit, which are fabricated at different substrate temperatures, as a buffer layer. The highest mobility of 4.08cm 2 /Vs is achieved using a F 16 CuPc/CuPc organic heterojunction buffer layer fabricated at high substrate temperature. Compared with the random small grain-like morphology of the room-temperature buffer layer, the high-temperature organic heterojunction presents a large-sized fiber-like film morphology, resulting in an enhanced conductivity. Thus the contact resistance of the transistor is significantly reduced and an obvious improvement in device mobility is obtained. (cross-disciplinary physics and related areas of science and technology)

Graphene-based flexible and stretchable thin film transistors.

Science.gov (United States)

Yan, Chao; Cho, Jeong Ho; Ahn, Jong-Hyun

2012-08-21

Graphene has been attracting wide attention owing to its superb electronic, thermal and mechanical properties. These properties allow great applications in the next generation of optoelectronics, where flexibility and stretchability are essential. In this context, the recent development of graphene growth/transfer and its applications in field-effect transistors are involved. In particular, we provide a detailed review on the state-of-the-art of graphene-based flexible and stretchable thin film transistors. We address the principles of fabricating high-speed graphene analog transistors and the key issues of producing an array of graphene-based transistors on flexible and stretchable substrates. It provides a platform for future work to focus on understanding and realizing high-performance graphene-based transistors.

Stable organic thin-film transistors

Science.gov (United States)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; Park, Youngrak; Kippelen, Bernard

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperature over time periods up to 5.9 × 105 s do not vary monotonically and remain below 0.2 V in microcrystalline OTFTs (μc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies. PMID:29340301

Design and characterization of integrated front-end transistors in a micro-strip detector technology

International Nuclear Information System (INIS)

Simi, G.; Angelini, C.; Batignani, G.; Bettarini, S.; Bondioli, M.; Boscardin, M.; Bosisio, L.; Dalla Betta, G.-F.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Morganti, M.; U. Pignatel, G.; Ratti, L.; Re, V.; Rizzo, G.; Speziali, V.; Zorzi, N.

2002-01-01

We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

High-Performance Vertical Organic Electrochemical Transistors.

Science.gov (United States)

Donahue, Mary J; Williamson, Adam; Strakosas, Xenofon; Friedlein, Jacob T; McLeod, Robert R; Gleskova, Helena; Malliaras, George G

2018-02-01

Organic electrochemical transistors (OECTs) are promising transducers for biointerfacing due to their high transconductance, biocompatibility, and availability in a variety of form factors. Most OECTs reported to date, however, utilize rather large channels, limiting the transistor performance and resulting in a low transistor density. This is typically a consequence of limitations associated with traditional fabrication methods and with 2D substrates. Here, the fabrication and characterization of OECTs with vertically stacked contacts, which overcome these limitations, is reported. The resulting vertical transistors exhibit a reduced footprint, increased intrinsic transconductance of up to 57 mS, and a geometry-normalized transconductance of 814 S m -1 . The fabrication process is straightforward and compatible with sensitive organic materials, and allows exceptional control over the transistor channel length. This novel 3D fabrication method is particularly suited for applications where high density is needed, such as in implantable devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Introduction to thin film transistors physics and technology of TFTs

CERN Document Server

Brotherton, S D

2013-01-01

Introduction to Thin Film Transistors reviews the operation, application, and technology of the main classes of thin film transistor (TFT) of current interest for large area electronics. The TFT materials covered include hydrogenated amorphous silicon (a-Si:H), poly-crystalline silicon (poly-Si), transparent amorphous oxide semiconductors (AOS), and organic semiconductors. The large scale manufacturing of a-Si:H TFTs forms the basis of the active matrix flat panel display industry. Poly-Si TFTs facilitate the integration of electronic circuits into portable active matrix liquid crystal displays, and are increasingly used in active matrix organic light emitting diode (AMOLED) displays for smart phones. The recently developed AOS TFTs are seen as an alternative option to poly-Si and a-Si:H for AMOLED TV and large AMLCD TV applications, respectively. The organic TFTs are regarded as a cost effective route into flexible electronics. As well as treating the highly divergent preparation and properties of these mat...

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

Science.gov (United States)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers

Science.gov (United States)

Daugherty, Robin

This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10-100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.

Subthreshold currents in CMOS transistors made on oxygen-implanted silicon

International Nuclear Information System (INIS)

Foster, D.J.

1983-01-01

Kinks have been observed in subthreshold current plots of mesa-shaped n-channel transistors made on oxygen-implanted silicon substrates. The kinks represent additional current flow and are due to overlapping fields from the gate electrode causing early corner inversion and to a Qsub(ss) side-wall effect. Subthreshold currents in n-channel transistors are dominated by the two effects which, as a consequence, reduce threshold voltages especially in narrow n-channel transistors. The subthreshold characteristics of p-channel transistors were not affected in the same way. (author)

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

Science.gov (United States)

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

High-frequency self-aligned graphene transistors with transferred gate stacks

Science.gov (United States)

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Chemical-free n-type and p-type multilayer-graphene transistors

Energy Technology Data Exchange (ETDEWEB)

Dissanayake, D. M. N. M., E-mail: nandithad@voxtel-inc.com [Voxtel Inc, Lockey Laboratories, University of Oregon, Eugene Oregon 97402 (United States); Eisaman, M. D. [Sustainable Energy Technologies Department, Brookhaven National Laboratory, Upton, New York 11973 (United States); Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, New York 11794 (United States); Department of Physics and Astronomy, Stony Brook University, Stony Brook, New York 11794 (United States)

2016-08-01

A single-step doping method to fabricate n- and p-type multilayer graphene (MG) top-gate field effect transistors (GFETs) is demonstrated. The transistors are fabricated on soda-lime glass substrates, with the n-type doping of MG caused by the sodium in the substrate without the addition of external chemicals. Placing a hydrogen silsesquioxane (HSQ) barrier layer between the MG and the substrate blocks the n-doping, resulting in p-type doping of the MG above regions patterned with HSQ. The HSQ is deposited in a single fabrication step using electron beam lithography, allowing the patterning of arbitrary sub-micron spatial patterns of n- and p-type doping. When a MG channel is deposited partially on the barrier and partially on the glass substrate, a p-type and n-type doping profile is created, which is used for fabricating complementary transistors pairs. Unlike chemically doped GFETs in which the external dopants are typically introduced from the top, these substrate doped GFETs allow for a top gate which gives a stronger electrostatic coupling to the channel, reducing the operating gate bias. Overall, this method enables scalable fabrication of n- and p-type complementary top-gated GFETs with high spatial resolution for graphene microelectronic applications.

Sensor Technologies on Flexible Substrates

Science.gov (United States)

Koehne, Jessica

2016-01-01

NASA Ames has developed sensor technologies on flexible substrates integrated into textiles for personalized environment monitoring and human performance evaluation. Current technologies include chemical sensing for gas leak and event monitoring and biological sensors for human health and performance monitoring. Targeted integration include next generation EVA suits and flexible habitats.

Current-Induced Transistor Sensorics with Electrogenic Cells

Directory of Open Access Journals (Sweden)

Peter Fromherz

2016-04-01

Full Text Available The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned.

High-power microwave LDMOS transistors for wireless data transmission technologies (Review)

International Nuclear Information System (INIS)

Kuznetsov, E. V.; Shemyakin, A. V.

2010-01-01

The fields of the application, structure, fabrication, and packaging technology of high-power microwave LDMOS transistors and the main advantages of these devices were analyzed. Basic physical parameters and some technology factors were matched for optimum device operation. Solid-state microwave electronics has been actively developed for the last 10-15 years. Simultaneously with improvement of old devices, new devices and structures are actively being adopted and developed and new semiconductor materials are being commercialized. Microwave LDMOS technology is in demand in such fields as avionics, civil and military radars, repeaters, base stations of cellular communication systems, television and broadcasting transmitters, and transceivers for high-speed wireless computer networks (promising Wi-Fi and Wi-Max standards).

Polarization sensitive detection of 100 GHz radiation by high mobility field-effect transistors

International Nuclear Information System (INIS)

Sakowicz, M.; Lusakowski, J.; Karpierz, K.; Grynberg, M.; Knap, W.; Gwarek, W.

2008-01-01

Detection of 100 GHz electromagnetic radiation by a GaAs/AlGaAs high electron mobility field-effect transistor was investigated at 300 K as a function of the angle α between the direction of linear polarization of the radiation and the symmetry axis of the transistor. The angular dependence of the detected signal was found to be A 0 cos 2 (α-α 0 )+C with A 0 , α 0 , and C dependent on the electrical polarization of the transistor gate. This dependence is interpreted as due to excitation of two crossed phase-shifted oscillators. A response of the transistor chip (including bonding wires and the substrate) to 100 GHz radiation was numerically simulated. Results of calculations confirmed experimentally observed dependencies and showed that the two oscillators result from an interplay of 100 GHz currents defined by the transistor impedance together with bonding wires and substrate related modes

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

Science.gov (United States)

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

Ultra-high gain diffusion-driven organic transistor

Science.gov (United States)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

Science.gov (United States)

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

Science.gov (United States)

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

GaN transistors for efficient power conversion

CERN Document Server

Lidow, Alex; de Rooij, Michael; Reusch, David

2014-01-01

The first edition of GaN Transistors for Efficient Power Conversion was self-published by EPC in 2012, and is currently the only other book to discuss GaN transistor technology and specific applications for the technology. More than 1,200 copies of the first edition have been sold through Amazon or distributed to selected university professors, students and potential customers, and a simplified Chinese translation is also available. The second edition has expanded emphasis on applications for GaN transistors and design considerations. This textbook provides technical and application-focused i

Vertically aligned carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi

2012-10-01

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been developed using pure semiconducting carbon nanotubes. The source and drain were vertically stacked, separated by a dielectric, and the carbon nanotubes were placed on the sidewall of the stack to bridge the source and drain. Both the effective gate dielectric and gate electrode were normal to the substrate surface. The channel length is determined by the dielectric thickness between source and drain electrodes, making it easier to fabricate sub-micrometer transistors without using time-consuming electron beam lithography. The transistor area is much smaller than the planar CNTFET due to the vertical arrangement of source and drain and the reduced channel area. © 2012 Elsevier Ltd. All rights reserved.

Effect of surface passivation by SiN/SiO2 of AlGaN/GaN high-electron mobility transistors on Si substrate by deep level transient spectroscopy method

International Nuclear Information System (INIS)

Gassoumi, Malek; Mosbahi, Hana; Zaidi, Mohamed Ali; Gaquiere, Christophe; Maaref, Hassen

2013-01-01

Device performance and defects in AlGaN/GaN high-electron mobility transistors have been correlated. The effect of SiN/SiO 2 passivation of the surface of AlGaN/GaN high-electron mobility transistors on Si substrates is reported on DC characteristics. Deep level transient spectroscopy (DLTS) measurements were performed on the device after the passivation by a (50/100 nm) SiN/SiO 2 film. The DLTS spectra from these measurements showed the existence of the same electron trap on the surface of the device

Large scale integration of flexible non-volatile, re-addressable memories using P(VDF-TrFE) and amorphous oxide transistors

International Nuclear Information System (INIS)

Gelinck, Gerwin H; Cobb, Brian; Van Breemen, Albert J J M; Myny, Kris

2015-01-01

Ferroelectric polymers and amorphous metal oxide semiconductors have emerged as important materials for re-programmable non-volatile memories and high-performance, flexible thin-film transistors, respectively. However, realizing sophisticated transistor memory arrays has proven to be a challenge, and demonstrating reliable writing to and reading from such a large scale memory has thus far not been demonstrated. Here, we report an integration of ferroelectric, P(VDF-TrFE), transistor memory arrays with thin-film circuitry that can address each individual memory element in that array. n-type indium gallium zinc oxide is used as the active channel material in both the memory and logic thin-film transistors. The maximum process temperature is 200 °C, allowing plastic films to be used as substrate material. The technology was scaled up to 150 mm wafer size, and offers good reproducibility, high device yield and low device variation. This forms the basis for successful demonstration of memory arrays, read and write circuitry, and the integration of these. (paper)

3.4-Inch Quarter High Definition Flexible Active Matrix Organic Light Emitting Display with Oxide Thin Film Transistor

Science.gov (United States)

Hatano, Kaoru; Chida, Akihiro; Okano, Tatsuya; Sugisawa, Nozomu; Inoue, Tatsunori; Seo, Satoshi; Suzuki, Kunihiko; Oikawa, Yoshiaki; Miyake, Hiroyuki; Koyama, Jun; Yamazaki, Shunpei; Eguchi, Shingo; Katayama, Masahiro; Sakakura, Masayuki

2011-03-01

In this paper, we report a 3.4-in. flexible active matrix organic light emitting display (AMOLED) display with remarkably high definition (quarter high definition: QHD) in which oxide thin film transistors (TFTs) are used. We have developed a transfer technology in which a TFT array formed on a glass substrate is separated from the substrate by physical force and then attached to a flexible plastic substrate. Unlike a normal process in which a TFT array is directly fabricated on a thin plastic substrate, our transfer technology permits a high integration of high performance TFTs, such as low-temperature polycrystalline silicon TFTs (LTPS TFTs) and oxide TFTs, on a plastic substrate, because a flat, rigid, and thermally-stable glass substrate can be used in the TFT fabrication process in our transfer technology. As a result, this technology realized an oxide TFT array for an AMOLED on a plastic substrate. Furthermore, in order to achieve a high-definition AMOLED, color filters were incorporated in the TFT array and a white organic light-emitting diode (OLED) was combined. One of the features of this device is that the whole body of the device can be bent freely because a source driver and a gate driver can be integrated on the substrate due to the high mobility of an oxide TFT. This feature means “true” flexibility.

Reliability improvement of a-Si:H thin film transistors on plastic substrate with saturation in deep state after multiple bending cycles

International Nuclear Information System (INIS)

Lee, M.H.; Chen, P.-G.; Hsu, C.-C.

2013-01-01

For flexible electronic applications, the disordered bonds of a-Si:H may generate a redistribution of trapped states with mechanical strain. During mechanical strain, the deep states are redistributed in a Gaussian distribution and are dissimilar to ordinary acceptor-like deep states, which manifest with exponential distributions. The redistributed deep states may saturate with multiple mechanical bending cycles, and it would improve the reliability with drain current stress of a-Si:H TFTs (thin film transistors) on flexible substrates. We conclude that it is possible to produce low-cost and highly uniform active-matrix organic light emitting diodes systems for use in flexible display applications using a-Si:H TFTs array backplanes. - Highlights: • The stress stability of a-Si:H TFTs (thin-film transistors) was improved after bending cycles. • The saturated deep states after bending were confirmed. • The simulation and extracted gap state density of a-Si:H TFT under strain was calculated

Growth-substrate induced performance degradation in chemically synthesized monolayer MoS{sub 2} field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Amani, Matin; Chin, Matthew L.; Mazzoni, Alexander L.; Burke, Robert A.; Dubey, Madan, E-mail: madan.dubey.civ@mail.mil [Sensors and Electron Devices Directorate, US Army Research Laboratory, Adelphi, Maryland 20723 (United States); Najmaei, Sina; Ajayan, Pulickel M.; Lou, Jun [Department of Materials Science and Nanoengineering, Rice University, Houston, Texas 77005 (United States)

2014-05-19

We report on the electronic transport properties of single-layer thick chemical vapor deposition (CVD) grown molybdenum disulfide (MoS{sub 2}) field-effect transistors (FETs) on Si/SiO{sub 2} substrates. MoS{sub 2} has been extensively investigated for the past two years as a potential semiconductor analogue to graphene. To date, MoS{sub 2} samples prepared via mechanical exfoliation have demonstrated field-effect mobility values which are significantly higher than that of CVD-grown MoS{sub 2}. In this study, we will show that the intrinsic electronic performance of CVD-grown MoS{sub 2} is equal or superior to that of exfoliated material and has been possibly masked by a combination of interfacial contamination on the growth substrate and residual tensile strain resulting from the high-temperature growth process. We are able to quantify this strain in the as-grown material using pre- and post-transfer metrology and microscopy of the same crystals. Moreover, temperature-dependent electrical measurements made on as-grown and transferred MoS{sub 2} devices following an identical fabrication process demonstrate the improvement in field-effect mobility.

Strain on field effect transistors with single–walled–carbon nanotube network on flexible substrate

Energy Technology Data Exchange (ETDEWEB)

Kim, T. G. [Samsung Advanced Institute of Technology, Research center for Time-domain Nano-functional Device, Giheung, Yong-In, Gyeonggi 446-712 (Korea, Republic of); Department of Electrical Engineering, Korea University, Anam-dong, Seongbuk-gu, Seoul 136-713 (Korea, Republic of); Kim, U. J.; Lee, E. H. [Samsung Advanced Institute of Technology, Frontier Research Laboratory, Giheung, Yong-In, Gyeonggi 446-712 (Korea, Republic of); Hwang, J. S. [School of Advanced Materials Science and Engineering, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon, Gyeonggi 440-746 (Korea, Republic of); Hwang, S. W., E-mail: swnano.hwang@samsung.com, E-mail: sangsig@korea.ac.kr [Samsung Advanced Institute of Technology, Research center for Time-domain Nano-functional Device, Giheung, Yong-In, Gyeonggi 446-712 (Korea, Republic of); Samsung Advanced Institute of Technology, Frontier Research Laboratory, Giheung, Yong-In, Gyeonggi 446-712 (Korea, Republic of); Kim, S., E-mail: swnano.hwang@samsung.com, E-mail: sangsig@korea.ac.kr [Department of Electrical Engineering, Korea University, Anam-dong, Seongbuk-gu, Seoul 136-713 (Korea, Republic of)

2013-12-07

We have systematically analyzed the effect of strain on the electrical properties of flexible field effect transistors with a single-walled carbon nanotube (SWCNT) network on a polyethersulfone substrate. The strain was applied and estimated at the microscopic scale (<1 μm) by using scanning electron microscope (SEM) equipped with indigenously designed special bending jig. Interestingly, the strain estimated at the microscopic scale was found to be significantly different from the strain calculated at the macroscopic scale (centimeter-scale), by a factor of up to 4. Further in-depth analysis using SEM indicated that the significant difference in strain, obtained from two different measurement scales (microscale and macroscale), could be attributed to the formation of cracks and tears in the SWCNT network, or at the junction of SWCNT network and electrode during the strain process. Due to this irreversible morphological change, the electrical properties, such as on current level and field effect mobility, lowered by 14.3% and 4.6%, respectively.

Photo-Induced Room-Temperature Gas Sensing with a-IGZO Based Thin-Film Transistors Fabricated on Flexible Plastic Foil.

Science.gov (United States)

Knobelspies, Stefan; Bierer, Benedikt; Daus, Alwin; Takabayashi, Alain; Salvatore, Giovanni Antonio; Cantarella, Giuseppe; Ortiz Perez, Alvaro; Wöllenstein, Jürgen; Palzer, Stefan; Tröster, Gerhard

2018-01-26

We present a gas sensitive thin-film transistor (TFT) based on an amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) semiconductor as the sensing layer, which is fabricated on a free-standing flexible polyimide foil. The photo-induced sensor response to NO₂ gas at room temperature and the cross-sensitivity to humidity are investigated. We combine the advantages of a transistor based sensor with flexible electronics technology to demonstrate the first flexible a-IGZO based gas sensitive TFT. Since flexible plastic substrates prohibit the use of high operating temperatures, the charge generation is promoted with the help of UV-light absorption, which ultimately triggers the reversible chemical reaction with the trace gas. Furthermore, the device fabrication process flow can be directly implemented in standard TFT technology, allowing for the parallel integration of the sensor and analog or logical circuits.

Photo-Induced Room-Temperature Gas Sensing with a-IGZO Based Thin-Film Transistors Fabricated on Flexible Plastic Foil

Directory of Open Access Journals (Sweden)

Stefan Knobelspies

2018-01-01

Full Text Available We present a gas sensitive thin-film transistor (TFT based on an amorphous Indium–Gallium–Zinc–Oxide (a-IGZO semiconductor as the sensing layer, which is fabricated on a free-standing flexible polyimide foil. The photo-induced sensor response to NO2 gas at room temperature and the cross-sensitivity to humidity are investigated. We combine the advantages of a transistor based sensor with flexible electronics technology to demonstrate the first flexible a-IGZO based gas sensitive TFT. Since flexible plastic substrates prohibit the use of high operating temperatures, the charge generation is promoted with the help of UV-light absorption, which ultimately triggers the reversible chemical reaction with the trace gas. Furthermore, the device fabrication process flow can be directly implemented in standard TFT technology, allowing for the parallel integration of the sensor and analog or logical circuits.

Doped organic transistors operating in the inversion and depletion regime

Science.gov (United States)

Lüssem, Björn; Tietze, Max L.; Kleemann, Hans; Hoßbach, Christoph; Bartha, Johann W.; Zakhidov, Alexander; Leo, Karl

2013-01-01

The inversion field-effect transistor is the basic device of modern microelectronics and is nowadays used more than a billion times on every state-of-the-art computer chip. In the future, this rigid technology will be complemented by flexible electronics produced at extremely low cost. Organic field-effect transistors have the potential to be the basic device for flexible electronics, but still need much improvement. In particular, despite more than 20 years of research, organic inversion mode transistors have not been reported so far. Here we discuss the first realization of organic inversion transistors and the optimization of organic depletion transistors by our organic doping technology. We show that the transistor parameters—in particular, the threshold voltage and the ON/OFF ratio—can be controlled by the doping concentration and the thickness of the transistor channel. Injection of minority carriers into the doped transistor channel is achieved by doped contacts, which allows forming an inversion layer. PMID:24225722

Fully transparent thin-film transistor devices based on SnO2 nanowires.

Science.gov (United States)

Dattoli, Eric N; Wan, Qing; Guo, Wei; Chen, Yanbin; Pan, Xiaoqing; Lu, Wei

2007-08-01

We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.

High mobility and quantum well transistors design and TCAD simulation

CERN Document Server

Hellings, Geert

2013-01-01

For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Qu...

Impact of contact and access resistances in graphene field-effect transistors on quartz substrates for radio frequency applications

International Nuclear Information System (INIS)

Ramón, Michael E.; Movva, Hema C. P.; Fahad Chowdhury, Sk.; Parrish, Kristen N.; Rai, Amritesh; Akinwande, Deji; Banerjee, Sanjay K.; Magnuson, Carl W.; Ruoff, Rodney S.

2014-01-01

High-frequency performance of graphene field-effect transistors (GFETs) has been limited largely by parasitic resistances, including contact resistance (R C ) and access resistance (R A ). Measurement of short-channel (500 nm) GFETs with short (200 nm) spin-on-doped source/drain access regions reveals negligible change in transit frequency (f T ) after doping, as compared to ∼23% f T improvement for similarly sized undoped GFETs measured at low temperature, underscoring the impact of R C on high-frequency performance. DC measurements of undoped/doped short and long-channel GFETs highlight the increasing impact of R A for larger GFETs. Additionally, parasitic capacitances were minimized by device fabrication using graphene transferred onto low-capacitance quartz substrates

Charge movement in a GaN-based hetero-structure field effect transistor structure with carbon doped buffer under applied substrate bias

International Nuclear Information System (INIS)

Pooth, Alexander; Uren, Michael J.; Cäsar, Markus; Kuball, Martin; Martin, Trevor

2015-01-01

Charge trapping and transport in the carbon doped GaN buffer of a GaN-based hetero-structure field effect transistor (HFET) has been investigated under both positive and negative substrate bias. Clear evidence of redistribution of charges in the carbon doped region by thermally generated holes is seen, with electron injection and capture observed during positive bias. Excellent agreement is found with simulations. It is shown that these effects are intrinsic to the carbon doped GaN and need to be controlled to provide reliable and efficient GaN-based power HFETs

Transport Mechanisms in Organic Thin-Film Transistors

Science.gov (United States)

Fung, A. W. P.

1996-03-01

Recent success in fabricating field-effect transistors with polycrystalline α-sexithiophene (α-6T) has allowed us to study charge transport in this organic semiconductor. The appealing structural property that the oligomer chains are seated almost perpendicular to the substrate provides a model π-conjugated system which we find exhibits band transport at low temperatures. We observe a behavioral transition around 50K which is consistent with the metal-insulator transition in Holstein's small-polaron theory. The fact that we can observe intrinsic behavior means that the ambient-temperature mobility obtained in these transistors is optimal for α-6T. Agreement with the Holstein theory provides us with a prescription for rational design of materials for organic transistor applications. Work done in collaboration with L. Torsi, A. Dodabalapur, L. J. Rothberg and H. E. Katz.

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2006-01-01

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits

Investigation of (111 wafers and comparison with (100 substrates

Directory of Open Access Journals (Sweden)

A Bahari

2012-06-01

Full Text Available  In the last decade, Si(100 has been used as a suitable substrate in field effect transistors. Some issues such as leakage current and tunneling current through the ultrathin films have been increased with shrinking the electronic devices – particularly, field effect transistors – to nanoscale, which is threatening more use of Si(100. We have thus demonstrated a series of experiments to grow ultrathin films on both Si(100 and Si(111 substrates and studied their nanostructural properties to see the possibility of replacing Si(100 with Si(111. The obtained results indicate that Si(111 substrate with silicon nitride film on top is desirable.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

Science.gov (United States)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor

Area and energy efficient high-performance ZnO wavy channel thin-film transistor

KAUST Repository

Hanna, Amir; Ghoneim, Mohamed T.; Bahabry, Rabab R.; Hussain, Aftab M.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

2014-01-01

of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased

Impact of contact and access resistances in graphene field-effect transistors on quartz substrates for radio frequency applications

Energy Technology Data Exchange (ETDEWEB)

Ramón, Michael E., E-mail: michael.ramon@utexas.edu, E-mail: hemacp@utexas.edu; Movva, Hema C. P., E-mail: michael.ramon@utexas.edu, E-mail: hemacp@utexas.edu; Fahad Chowdhury, Sk.; Parrish, Kristen N.; Rai, Amritesh; Akinwande, Deji; Banerjee, Sanjay K. [Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas 78758 (United States); Magnuson, Carl W.; Ruoff, Rodney S. [Department of Mechanical Engineering and the Materials Science and Engineering Program, The University of Texas at Austin, Austin, Texas 78712 (United States)

2014-02-17

High-frequency performance of graphene field-effect transistors (GFETs) has been limited largely by parasitic resistances, including contact resistance (R{sub C}) and access resistance (R{sub A}). Measurement of short-channel (500 nm) GFETs with short (200 nm) spin-on-doped source/drain access regions reveals negligible change in transit frequency (f{sub T}) after doping, as compared to ∼23% f{sub T} improvement for similarly sized undoped GFETs measured at low temperature, underscoring the impact of R{sub C} on high-frequency performance. DC measurements of undoped/doped short and long-channel GFETs highlight the increasing impact of R{sub A} for larger GFETs. Additionally, parasitic capacitances were minimized by device fabrication using graphene transferred onto low-capacitance quartz substrates.

The dual role of multiple-transistor charge sharing collection in single-event transients

International Nuclear Information System (INIS)

Guo Yang; Chen Jian-Jun; He Yi-Bai; Liang Bin; Liu Bi-Wei

2013-01-01

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients (SETs) due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal—oxide semiconductor field-effect transistor (PMOS FET), but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies. (condensed matter: structural, mechanical, and thermal properties)

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Science.gov (United States)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

Science.gov (United States)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.

Science.gov (United States)

Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2017-10-25

Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2  area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.

Control of droplet morphology for inkjet-printed TIPS-pentacene transistors

Science.gov (United States)

Lee, Myung Won; Ryu, Gi Seong; Lee, Young Uk; Pearson, Christopher; Petty, Michael C.; Song, Chung Kun

2012-01-01

We report on methods to control the morphology of droplets of 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS-PEN), which are then used in the fabrication of organic thin film transistors (OTFTs). The grain size and distribution of the TIPS-PEN were found to depend on the temperature of the droplets during drying. The performance of the OTFTs could be improved by heating the substrate and also by changing the relative positions of the inkjet-printed droplets. In our experiments, the optimum substrate temperature was 46 °C in air. Transistors with the TIPS-PEN grain boundaries parallel to the current flow between the source and drain electrodes exhibited charge carrier mobilities of 0.44 ± 0.08 cm2/V s.

Field emission current from a junction field-effect transistor

International Nuclear Information System (INIS)

Monshipouri, Mahta; Abdi, Yaser

2015-01-01

Fabrication of a titanium dioxide/carbon nanotube (TiO 2 /CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO 2 nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO 2 /CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO 2 /CNT hetero-structure is also investigated, and well modeled

Application of the Johnson criteria to graphene transistors

International Nuclear Information System (INIS)

Kelly, M J

2013-01-01

For 60 years, the Johnson criteria have guided the development of materials and the materials choices for field-effect and bipolar transistor technology. Intrinsic graphene is a semi-metal, precluding transistor applications, but only under lateral bias is a gap opened and transistor action possible. This first application of the Johnson criteria to biased graphene suggests that this material will struggle to ever achieve competitive commercial applications. (fast track communication)

Graphene Field Effect Transistor-Based Detectors for Detection of Ionizing Radiation

International Nuclear Information System (INIS)

Jovanovic, Igor; Cazalas, Edward; Childres, I.; Patil, A.; Koybasi, O.; Chen, Y-P.

2013-06-01

We present the results of our recent efforts to develop novel ionizing radiation sensors based on the nano-material graphene. Graphene used in the field effect transistor architecture could be employed to detect the radiation-induced charge carriers produced in undoped semiconductor absorber substrates, even without the need for charge collection. The detection principle is based on the high sensitivity of graphene to ionization-induced local electric field perturbations in the electrically biased substrate. We experimentally demonstrated promising performance of graphene field effect transistors for detection of visible light, X-rays, gamma-rays, and alpha particles. We propose improved detector architectures which could result in a significant improvement of speed necessary for pulsed mode operation. (authors)

Fabrication and characteristics of magnetic field sensors based on nano-polysilicon thin-film transistors

International Nuclear Information System (INIS)

Zhao Xiaofeng; Wen Dianzhong; Zhuang Cuicui; Cao Jingya; Wang Zhiqiang

2013-01-01

A magnetic field sensor based on nano-polysilicon thin films transistors (TFTs) with Hall probes is proposed. The magnetic field sensors are fabricated on 〈100〉 orientation high resistivity (ρ > 500 Ω·cm) silicon substrates by using CMOS technology, which adopt nano-polysilicon thin films with thicknesses of 90 nm and heterojunction interfaces between the nano-polysilicon thin films and the high resistivity silicon substrates as the sensing layers. The experimental results show that when V DS = 5.0 V, the magnetic sensitivities of magnetic field sensors based on nano-polysilicon TFTs with length—width ratios of 160 μm/80 μm, 320 μm/80 μm and 480 μm/80 μm are 78 mV/T, 55 mV/T and 34 mV/T, respectively. Under the same conditions, the magnetic sensitivity of the obtained magnetic field sensor is significantly improved in comparison with a Hall magnetic field sensor adopting silicon as the sensing layers. (semiconductor technology)

On the 50th Anniversary of the Transistor

DEFF Research Database (Denmark)

Stassen, Flemming

1997-01-01

This paper celebrates the 50th anniversary of the invention of the bipolar transistor in 1947. Combined with the inventions of integration and planar technology, the invention of the transistor marks the beginning of a period of unprecedented growth, the industrialization of electronics....

Thin-film transistors with a channel composed of semiconducting metal oxide nanoparticles deposited from the gas phase

International Nuclear Information System (INIS)

Busch, C.; Schierning, G.; Theissmann, R.; Nedic, A.; Kruis, F. E.; Schmechel, R.

2012-01-01

The fabrication of semiconducting functional layers using low-temperature processes is of high interest for flexible printable electronics applications. Here, the one-step deposition of semiconducting nanoparticles from the gas phase for an active layer within a thin-film transistor is described. Layers of semiconducting nanoparticles with a particle size between 10 and 25 nm were prepared by the use of a simple aerosol deposition system, excluding potentially unwanted technological procedures like substrate heating or the use of solvents. The nanoparticles were deposited directly onto standard thin-film transistor test devices, using thermally grown silicon oxide as gate dielectric. Proof-of-principle experiments were done deploying two different wide-band gap semiconducting oxides, tin oxide, SnO x , and indium oxide, In 2 O 3 . The tin oxide spots prepared from the gas phase were too conducting to be used as channel material in thin-film transistors, most probably due to a high concentration of oxygen defects. Using indium oxide nanoparticles, thin-film transistor devices with significant field effect were obtained. Even though the electron mobility of the investigated devices was only in the range of 10 −6 cm 2V−1s−1 , the operability of this method for the fabrication of transistors was demonstrated. With respect to the possibilities to control the particle size and layer morphology in situ during deposition, improvements are expected.

Fabrication and characterization on reduced graphene oxide field effect transistor (RGOFET) based biosensor

Energy Technology Data Exchange (ETDEWEB)

Rashid, A. Diyana [School of Microelectronic Engineering, Universiti Malaysia Perlis (UniMAP), Pauh, Perlis (Malaysia); Ruslinda, A. Rahim, E-mail: ruslinda@unimap.edu.my; Fatin, M. F. [Institute of Nano Electronic Engineering, Universiti Malaysia Perlis (UniMAP), 01000 Kangar, Perlis (Malaysia); Hashim, U.; Arshad, M. K. [School of Microelectronic Engineering, Universiti Malaysia Perlis (UniMAP), Pauh, Perlis (Malaysia); Institute of Nano Electronic Engineering, Universiti Malaysia Perlis (UniMAP), 01000 Kangar, Perlis (Malaysia)

2016-07-06

The fabrication and characterization on reduced graphene oxide field effect transistor (RGO-FET) were demonstrated using a spray deposition method for biological sensing device purpose. A spray method is a fast, low-cost and simple technique to deposit graphene and the most promising technology due to ideal coating on variety of substrates and high production speed. The fabrication method was demonstrated for developing a label free aptamer reduced graphene oxide field effect transistor biosensor. Reduced graphene oxide (RGO) was obtained by heating on hot plate fixed at various temperatures of 100, 200 and 300°C, respectively. The surface morphology of RGO were examined via atomic force microscopy to observed the temperature effect of produced RGO. The electrical measurement verify the performance of electrical conducting RGO-FET at temperature 300°C is better as compared to other temperature due to the removal of oxygen groups in GO. Thus, reduced graphene oxide was a promising material for biosensor application.

Organic electrochemical transistors

Science.gov (United States)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Organic electrochemical transistors

KAUST Repository

Rivnay, Jonathan

2018-01-16

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Graphene Field Effect Transistor for Radiation Detection

Science.gov (United States)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

International Nuclear Information System (INIS)

Ai-Fang, Yu; Qiong, Qi; Peng, Jiang; Chao, Jiang

2009-01-01

Carrier mobility enhancement from 0.09 to 0.59 cm 2 /Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO 2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO 2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO 2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski–Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility. (cross-disciplinary physics and related areas of science and technology)

Field emission current from a junction field-effect transistor

Energy Technology Data Exchange (ETDEWEB)

Monshipouri, Mahta; Abdi, Yaser, E-mail: y.abdi@ut.ac.ir [University of Tehran, Nano-Physics Research Laboratory, Department of Physics (Iran, Islamic Republic of)

2015-04-15

Fabrication of a titanium dioxide/carbon nanotube (TiO{sub 2}/CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO{sub 2} nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO{sub 2}/CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO{sub 2}/CNT hetero-structure is also investigated, and well modeled.

Transistor Effect in Improperly Connected Transistors.

Science.gov (United States)

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

International Nuclear Information System (INIS)

Nedic, Stanko; Welland, Mark; Tea Chun, Young; Chu, Daping; Hong, Woong-Ki

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10 5 , a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10 4 s

Photosensitive graphene transistors.

Science.gov (United States)

Li, Jinhua; Niu, Liyong; Zheng, Zijian; Yan, Feng

2014-08-20

High performance photodetectors play important roles in the development of innovative technologies in many fields, including medicine, display and imaging, military, optical communication, environment monitoring, security check, scientific research and industrial processing control. Graphene, the most fascinating two-dimensional material, has demonstrated promising applications in various types of photodetectors from terahertz to ultraviolet, due to its ultrahigh carrier mobility and light absorption in broad wavelength range. Graphene field effect transistors are recognized as a type of excellent transducers for photodetection thanks to the inherent amplification function of the transistors, the feasibility of miniaturization and the unique properties of graphene. In this review, we will introduce the applications of graphene transistors as photodetectors in different wavelength ranges including terahertz, infrared, visible, and ultraviolet, focusing on the device design, physics and photosensitive performance. Since the device properties are closely related to the quality of graphene, the devices based on graphene prepared with different methods will be addressed separately with a view to demonstrating more clearly their advantages and shortcomings in practical applications. It is expected that highly sensitive photodetectors based on graphene transistors will find important applications in many emerging areas especially flexible, wearable, printable or transparent electronics and high frequency communications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Inverter circuits on freestanding flexible substrate using ZnO nanoparticles for cost-efficient electronics

Science.gov (United States)

Vidor, Fábio F.; Meyers, Thorsten; Müller, Kathrin; Wirth, Gilson I.; Hilleringmann, Ulrich

2017-11-01

Driven by the Internet of Things (IoT), flexible and transparent smart systems have been intensively researched by the scientific community and by several companies. This technology is already available for consumers in a wide range of innovative products, e.g., flexible displays, radio-frequency identification tags and wearable electronic skins which, for instance, collect and analyze data for medical applications. For these systems, thin-film transistors (TFTs) are the key elements responsible for the driving currents. Solution-based materials such as nanoparticle dispersions avail the fabrication on large-area substrates with high throughput processes. In this study, we discuss the integration of ZnO nanoparticle thin-film transistors and inverter circuits on freestanding polymeric substrates enclosing the main issues concerning the transfer of the integration process from a rigid substrate to a flexible one. The TFTs depict VON between -0.2 and 1 V, ION/IOFF > 104 and field-effect mobility >0.5 cm2 V-1 s-1. Additionally, in order to enhance the transistors and inverters performance, an adaptation on the device configuration, from an inverted coplanar to an inverted staggered setup, was conducted and analyzed. By employing the inverted staggered setup a considerable increase in the contact quality between the semiconductor and the drain and source electrodes was observed. As the integrated devices depict electrical characteristics which enable the fabrication of electronic circuits for the low-cost sector, inverters were fabricated and characterized, evaluating the circuit's gain as function of the applied supply voltage and circuit's geometric ratio.

Lateral n-p-n bipolar transistors by ion implantation into semi-insulating GaAs

International Nuclear Information System (INIS)

Canfield, P.; Forbes, L.

1988-01-01

GaAs bipolar transistors have not seen the major development effort that GaAs MESFETs have due primarily to the short minority carrier lifetimes in GaAs. The short minority carrier lifetimes require that the base region be very thin which, if done by implantation, requires that the doping be high to obtain a well defined base profile. These requirements are very difficult to achieve in GaAs and typically, if high current gain and high speed are desired for a bipolar technology, then heterostructure bipolars are the appropriate technology, although the cost of heterostructure devices will be prohibitive for some time to come. For applications requiring low current gain, more modest fabrication rules can be followed. Lateral bipolars are particularly attractive since they would be easier to fabricate than a planar bipolar or a heterojunction bipolar. Lateral bipolars do not require steps or deep contacts to make contact with the subcollector or highly doped very thin epilayers for the base region and they can draw upon the semi-insulating properties of the GaAs substrates for device isolation. Bipolar transistors are described and shown to work successfully. (author)

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa; Fahad, Hossain M.; Smith, Casey E.; Rojas, Jhonathan Prieto

2015-01-01

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa

2015-12-29

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

A G-band terahertz monolithic integrated amplifier in 0.5-μm InP double heterojunction bipolar transistor technology

International Nuclear Information System (INIS)

Li Ou-Peng; Zhang Yong; Xu Rui-Min; Cheng Wei; Wang Yuan; Niu Bing; Lu Hai-Yan

2016-01-01

Design and characterization of a G-band (140–220 GHz) terahertz monolithic integrated circuit (TMIC) amplifier in eight-stage common-emitter topology are performed based on the 0.5-μm InGaAs/InP double heterojunction bipolar transistor (DHBT). An inverted microstrip line is implemented to avoid a parasitic mode between the ground plane and the InP substrate. The on-wafer measurement results show that peak gains are 20 dB at 140 GHz and more than 15-dB gain at 140–190 GHz respectively. The saturation output powers are −2.688 dBm at 210 GHz and −2.88 dBm at 220 GHz, respectively. It is the first report on an amplifier operating at the G-band based on 0.5-μm InP DHBT technology. Compared with the hybrid integrated circuit of vacuum electronic devices, the monolithic integrated circuit has the advantage of reliability and consistency. This TMIC demonstrates the feasibility of the 0.5-μm InGaAs/InP DHBT amplifier in G-band frequencies applications. (paper)

Radiation effect of doping and bias conditions on NPN bipolar junction transistors

International Nuclear Information System (INIS)

Xi Shanbin; Wang Yiyuan; Xu Fayue; Zhou Dong; Li Ming; Wang Fei; Wang Zhikuan; Yang Yonghui; Lu Wu

2011-01-01

In this paper,we investigate 60 Co γ-ray irradiation effects and annealing behaviors of NPN bipolar junction transistors of the same manufacturing technology but different doping concentrations. The transistors of different doping concentrations differ in responses of the radiation effect. More degradation was observed with the transistors of low concentration-doped NPN transistors than the high concentration-doped NPN transistors. The results also demonstrate that reverse-biased transistors are more sensitive to radiation than the forward-biased ones. Mechanisms of the radiation responses are analyzed. (authors)

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Science.gov (United States)

Sengupta, Sarmista; Pandit, Soumya

2015-06-01

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

SOI Transistor measurement techniques using body contacted transistors

International Nuclear Information System (INIS)

Worley, E.R.; Williams, R.

1989-01-01

Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

Transistor data book

International Nuclear Information System (INIS)

1988-03-01

It introduces how to use this book. It lists transistor data and index, which are Type No, Cross index, Germanium PNP low power transistors, silicon NPN low power transistors, Germanium PNP high power transistors, Switching transistors, transistor arrays, Miscellaneous transistors, types with U.S military specifications, direct replacement transistors, suggested replacement transistors, schematic drawings, outline drawings, device number keys and manufacturer's logos.

Quantum engineering of transistors based on 2D materials heterostructures

Science.gov (United States)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Quantum engineering of transistors based on 2D materials heterostructures.

Science.gov (United States)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Reliability of AlGaN/GaN high electron mobility transistors on low dislocation density bulk GaN substrate: Implications of surface step edges

Energy Technology Data Exchange (ETDEWEB)

Killat, N., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk; Montes Bajo, M.; Kuball, M., E-mail: Nicole.Killat@bristol.ac.uk, E-mail: Martin.Kuball@bristol.ac.uk [Center for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Paskova, T. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Materials Science and Engineering Department, North Carolina State University, Raleigh, North Carolina 27695 (United States); Evans, K. R. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Leach, J. [Kyma Technologies, Inc., Raleigh, North Carolina 27617 (United States); Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Li, X.; Özgür, Ü.; Morkoç, H. [Electrical and Computer Engineering Department, Virginia Commonwealth University, Richmond, Virginia 23284 (United States); Chabak, K. D.; Crespo, A.; Gillespie, J. K.; Fitch, R.; Kossler, M.; Walker, D. E.; Trejo, M.; Via, G. D.; Blevins, J. D. [Air Force Research Laboratory, Wright-Patterson Air Force Base, Dayton, Ohio 45433 (United States)

2013-11-04

To enable gaining insight into degradation mechanisms of AlGaN/GaN high electron mobility transistors, devices grown on a low-dislocation-density bulk-GaN substrate were studied. Gate leakage current and electroluminescence (EL) monitoring revealed a progressive appearance of EL spots during off-state stress which signify the generation of gate current leakage paths. Atomic force microscopy evidenced the formation of semiconductor surface pits at the failure location, which corresponds to the interaction region of the gate contact edge and the edges of surface steps.

Effects on focused ion beam irradiation on MOS transistors

International Nuclear Information System (INIS)

Campbell, A.N.; Peterson, K.A.; Fleetwood, D.M.; Soden, J.M.

1997-01-01

The effects of irradiation from a focused ion beam (FIB) system on MOS transistors are reported systematically for the first time. Three MOS transistor technologies, with 0.5, 1, and 3 μm minimum feature sizes and with gate oxide thicknesses ranging from 11 to 50 nm, were analyzed. Significant shifts in transistor parameters (such as threshold voltage, transconductance, and mobility) were observed following irradiation with a 30 keV Ga + focused ion beam with ion doses varying by over 5 orders of magnitude. The apparent damage mechanism (which involved the creation of interface traps, oxide trapped charge, or both) and extent of damage were different for each of the three technologies investigated

Ion implantation methods for semiconductor substrates

International Nuclear Information System (INIS)

Matsushita, T.; Mamine, T.; Hayashi, H.; Nishiyama, K.

1980-01-01

A method of ion implantation for controlling the life time of minority carriers in a semiconductor substrate and hence to reduce the temperature dependency of the life time, comprises implanting iron ions into an N type semiconductor substrate with a dosage of 10 10 to 10 15 ions cm -2 , and then heat-treating the implanted substrate at 850 0 to 1250 0 C. The method is applicable to the production of diodes, transistors, Si controlled rectifiers and gate controlled switching devices. (author)

Solution-Processed Organic and Halide Perovskite Transistors on Hydrophobic Surfaces.

Science.gov (United States)

Ward, Jeremy W; Smith, Hannah L; Zeidell, Andrew; Diemer, Peter J; Baker, Stephen R; Lee, Hyunsu; Payne, Marcia M; Anthony, John E; Guthold, Martin; Jurchescu, Oana D

2017-05-31

Solution-processable electronic devices are highly desirable due to their low cost and compatibility with flexible substrates. However, they are often challenging to fabricate due to the hydrophobic nature of the surfaces of the constituent layers. Here, we use a protein solution to modify the surface properties and to improve the wettability of the fluoropolymer dielectric Cytop. The engineered hydrophilic surface is successfully incorporated in bottom-gate solution-deposited organic field-effect transistors (OFETs) and hybrid organic-inorganic trihalide perovskite field-effect transistors (HTP-FETs) fabricated on flexible substrates. Our analysis of the density of trapping states at the semiconductor-dielectric interface suggests that the increase in the trap density as a result of the chemical treatment is minimal. As a result, the devices exhibit good charge carrier mobilities, near-zero threshold voltages, and low electrical hysteresis.

Modeling and simulation of 4H-SiC field effect transistor

Science.gov (United States)

Pedryc, A.; Martychowiec, A.; Kociubiński, A.

2017-08-01

This paper presents the technological issue of silicon carbide MOSFET design. Through the use of simulations of silicon carbide transistor, the influence of the different the technological parameters are described and discussed. MOSFET transistor was performed in Silvaco TCAD using technology elaborated at Lublin University of Technology. The most important parameters related to ion implantation, which was used in p-i-n photodiode technology. The electrical simulations were performed, transfer and output characteristics for different values of technological parameters were generated - influence of gate oxide thickness on threshold voltage and influence of channel length modulation were checked. The results of simulations as well as transfer and output characteristics allowed to select optimal parameters between expected device working and available technology - gate oxide thickness and transistor channel length were established. This work was in fact carried out to increase our understanding of the device characteristics so as to allow the design of new SiC circuits which could meet the stressful requirements of ultraviolet detector systems.

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Electronic technology

International Nuclear Information System (INIS)

Kim, Jin Su

2010-07-01

This book is composed of five chapters, which introduces electronic technology about understanding of electronic, electronic component, radio, electronic application, communication technology, semiconductor on its basic, free electron and hole, intrinsic semiconductor and semiconductor element, Diode such as PN junction diode, characteristic of junction diode, rectifier circuit and smoothing circuit, transistor on structure of transistor, characteristic of transistor and common emitter circuit, electronic application about electronic equipment, communication technology and education, robot technology and high electronic technology.

N-polar GaN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor formed on sapphire substrate with minimal step bunching

Science.gov (United States)

Prasertsuk, Kiattiwut; Tanikawa, Tomoyuki; Kimura, Takeshi; Kuboya, Shigeyuki; Suemitsu, Tetsuya; Matsuoka, Takashi

2018-01-01

The metal-insulator-semiconductor (MIS) gate N-polar GaN/AlGaN/GaN high-electron-mobility transistor (HEMT) on a (0001) sapphire substrate, which can be expected to operate with lower on-resistance and more easily work on the pinch-off operation than an N-polar AlGaN/GaN HEMT, was fabricated. For suppressing the step bunching and hillocks peculiar in the N-polar growth, a sapphire substrate with an off-cut angle as small as 0.8° was introduced and an N-polar GaN/AlGaN/GaN HEMT without the step bunching was firstly obtained by optimizing the growth conditions. The previously reported anisotropy of transconductance related to the step was eliminated. The pinch-off operation was also realized. These results indicate that this device is promising.

High-conductance low-voltage organic thin film transistor with locally rearranged poly(3-hexylthiophene) domain by current annealing on plastic substrate

Science.gov (United States)

Pei, Zingway; Tsai, Hsing-Wang; Lai, Hsin-Cheng

2016-02-01

The organic material based thin film transistors (TFTs) are attractive for flexible optoelectronics applications due to the ability of lager area fabrication by solution and low temperature process on plastic substrate. Recently, the research of organic TFT focus on low operation voltage and high output current to achieve a low power organic logic circuit for optoelectronic device,such as e-paper or OLED displayer. To obtain low voltage and high output current, high gate capacitance and high channel mobility are key factors. The well-arranged polymer chain by a high temperature postannealing, leading enhancement conductivity of polymer film was a general method. However, the thermal annealing applying heat for all device on the substrate and may not applicable to plastic substrate. Therefore, in this work, the low operation voltage and high output current of polymer TFTs was demonstrated by locally electrical bias annealing. The poly(styrene-comethyl methacrylate) (PS-r-PMMA) with ultra-thin thickness is used as gate dielectric that the thickness is controlled by thermal treatment after spin coated on organic electrode. In electrical bias-annealing process, the PS-r- PMMA is acted a heating layer. After electrical bias-annealing, the polymer TFTs obtain high channel mobility at low voltage that lead high output current by a locally annealing of P3HT film. In the future, the locally electrical biasannealing method could be applied on plastic substrate for flexible optoelectronic application.

Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors

Directory of Open Access Journals (Sweden)

Fábio F. Vidor

2015-07-01

Full Text Available Flexible and transparent electronics have been studied intensively during the last few decades. The technique establishes the possibility of fabricating innovative products, from flexible displays to radio-frequency identification tags. Typically, large-area polymeric substrates such as polypropylene (PP or polyethylene terephthalate (PET are used, which produces new requirements for the integration processes. A key element for flexible and transparent electronics is the thin-film transistor (TFT, as it is responsible for the driving current in memory cells, digital circuits or organic light-emitting devices (OLEDs. In this paper, we discuss some fundamental concepts of TFT technology. Additionally, we present a comparison between the use of the semiconducting organic small-molecule pentacene and inorganic nanoparticle semiconductors in order to integrate TFTs suitable for flexible electronics. Moreover, a technique for integration with a submicron resolution suitable for glass and foil substrates is presented.

SOI MESFETs on high-resistivity, trap-rich substrates

Science.gov (United States)

Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

2018-04-01

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

Investigation of AlGaN/GaN high electron mobility transistor structures on 200-mm silicon (111) substrates employing different buffer layer configurations.

Science.gov (United States)

Lee, H-P; Perozek, J; Rosario, L D; Bayram, C

2016-11-21

AlGaN/GaN high electron mobility transistor (HEMT) structures are grown on 200-mm diameter Si(111) substrates by using three different buffer layer configurations: (a) Thick-GaN/3 × {Al x Ga 1-x N}/AlN, (b) Thin-GaN/3 × {Al x Ga 1-x N}/AlN, and (c) Thin-GaN/AlN, so as to have crack-free and low-bow (GaN HEMT structures. The effects of buffer layer stacks (i.e. thickness and content) on defectivity, stress, and two-dimensional electron gas (2DEG) mobility and 2DEG concentration are reported. It is shown that 2DEG characteristics are heavily affected by the employed buffer layers between AlGaN/GaN HEMT structures and Si(111) substrates. Particularly, we report that in-plane stress in the GaN layer affects the 2DEG mobility and 2DEG carrier concentration significantly. Buffer layer engineering is shown to be essential for achieving high 2DEG mobility (>1800 cm 2 /V∙s) and 2DEG carrier concentration (>1.0 × 10 13  cm -2 ) on Si(111) substrates.

Carbon Nanotube Thin Film Transistors for Flat Panel Display Application.

Science.gov (United States)

Liang, Xuelei; Xia, Jiye; Dong, Guodong; Tian, Boyuan; Peng, Lianmao

2016-12-01

Carbon nanotubes (CNTs) are promising materials for both high performance transistors for high speed computing and thin film transistors for macroelectronics, which can provide more functions at low cost. Among macroelectronics applications, carbon nanotube thin film transistors (CNT-TFT) are expected to be used soon for backplanes in flat panel displays (FPDs) due to their superior performance. In this paper, we review the challenges of CNT-TFT technology for FPD applications. The device performance of state-of-the-art CNT-TFTs are compared with the requirements of TFTs for FPDs. Compatibility of the fabrication processes of CNT-TFTs and current TFT technologies are critically examined. Though CNT-TFT technology is not yet ready for backplane production line of FPDs, the challenges can be overcome by close collaboration between research institutes and FPD manufacturers in the short term.

Implementation of Self-Bias Transistor on Voting Logic

International Nuclear Information System (INIS)

Harzawardi Hasim; Syirrazie Che Soh

2014-01-01

Study in the eld of digital integrated circuit (IC) already become common to the modern industrial. Day by day we have been introduced with new gadget that was developed based on transistor. This paper will study the implementation of self-bias transistor on voting logic. The self-bias transistor will connected both on pull-up network and pull-down network. On previous research, study on comparison of total number of transistors, time propagation delay, and frequency between NAND and NOR gate of voting logic. It's show, with the same number of transistor, NAND gate achieve high frequency and low time propagation delay compare to NOR gate. We extend this analysis by comparing the total number of transistor, time propagation delay, frequency and power dissipation between common NAND gate with self-bias NAND gate. Extensive LTSpice simulations were performed using IBM 90 nm CMOS(Complementary Metal Oxide Semiconductor) process technology. The result show self-bias voting NAND gate consumes 54 % less power dissipation, 43% slow frequency and 43 % high time propagation delay compare to common voting NAND gate. (author)

AlGaAs/InGaAs/AlGaAs double pulse doped pseudomorphic high electron mobility transistor structures on InGaAs substrates

Science.gov (United States)

Hoke, W. E.; Lyman, P. S.; Mosca, J. J.; McTaggart, R. A.; Lemonias, P. J.; Beaudoin, R. M.; Torabi, A.; Bonner, W. A.; Lent, B.; Chou, L.-J.; Hsieh, K. C.

1997-10-01

Double pulse doped AlGaAs/InGaAs/AlGaAs pseudomorphic high electron mobility transistor (PHEMT) structures have been grown on InxGa1-xAs (x=0.025-0.07) substrates using molecular beam epitaxy. A strain compensated, AlGaInAs/GaAs superlattice was used for improved resistivity and breakdown. Excellent electrical and optical properties were obtained for 110-Å-thick InGaAs channel layers with indium concentrations up to 31%. A room temperature mobility of 6860 cm2/V s with 77 K sheet density of 4.0×1012cm-2 was achieved. The InGaAs channel photoluminescence intensity was equivalent to an analogous structure on a GaAs substrate. To reduce strain PHEMT structures with a composite InGaP/AlGaAs Schottky layer were also grown. The structures also exhibited excellent electrical and optical properties. Transmission electron micrographs showed planar channel interfaces for highly strained In0.30Ga0.70As channel layers.

Total dose induced latch in short channel NMOS/SOI transistors

International Nuclear Information System (INIS)

Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

1998-01-01

A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

Influence of the substrate platform on the opto-electronic properties of multi-layer organic light-emitting field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Generali, Gianluca; Capelli, Raffaella; Toffanin, Stefano; Muccini, Michele [Consiglio Nazionale delle Ricerche (CNR), Istituto per lo Studio dei Materiali Nanostrutturati (ISMN), via P. Gobetti 101, I-40129 Bologna (Italy); Dinelli, Franco, E-mail: g.generali@bo.ismn.cnr.it, E-mail: m.muccini@bo.ismn.cnr.it [Consiglio Nazionale delle Ricerche (CNR), INO U.O.S. ' A. Gozzini' Area della Ricerca di Pisa - S. Cataldo, via Moruzzi 1, I-56124 Pisa (Italy)

2011-06-08

In this paper, we present a study of the effects of the influence of the substrate platform on the properties of a three-layer vertical hetero-junction made of thin films of {alpha}, {omega}-diperfluorohexyl-4T (DHF4T), a blend of tris(8-hydroxyquinoline)aluminium (Alq3) and 4-(dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)-4H-pyran (DCM) and {alpha}, {omega}-dihexyl-quaterthiophene (DH4T). The hetero-junction represents the active component of an organic light-emitting transistor (OLET). The substrate platforms investigated in this study are glass/indium-tin-oxide/poly(methyl-methacrylate) (PMMA) and Si{sup ++}/silicon oxide (SiO{sub 2})/PMMA. The first platform is almost completely transparent to light and therefore is very promising for use in OLET applications. The second one has been chosen for comparison as it employs standard microelectronic materials, i.e. Si{sup ++}/SiO{sub 2}. We show how different gate materials and structure can affect the relevant field-effect electrical characteristics, such as the charge mobility and threshold voltage. By means of an atomic force microscopy analysis, a systematic study has been made in order to correlate the morphology of the active layers with the electrical properties of the devices.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

Science.gov (United States)

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

High-mobility pyrene-based semiconductor for organic thin-film transistors.

Science.gov (United States)

Cho, Hyunduck; Lee, Sunyoung; Cho, Nam Sung; Jabbour, Ghassan E; Kwak, Jeonghun; Hwang, Do-Hoon; Lee, Changhee

2013-05-01

Numerous conjugated oligoacenes and polythiophenes are being heavily studied in the search for high-mobility organic semiconductors. Although many researchers have designed fused aromatic compounds as organic semiconductors for organic thin-film transistors (OTFTs), pyrene-based organic semiconductors with high mobilities and on-off current ratios have not yet been reported. Here, we introduce a new pyrene-based p-type organic semiconductor showing liquid crystal behavior. The thin film characteristics of this material are investigated by varying the substrate temperature during the deposition and the gate dielectric condition using the surface modification with a self-assembled monolayer, and systematically studied in correlation with the performances of transistor devices with this compound. OTFT fabricated under the optimum deposition conditions of this compound, namely, 1,6-bis(5'-octyl-2,2'-bithiophen-5-yl)pyrene (BOBTP) shows a high-performance transistor behavior with a field-effect mobility of 2.1 cm(2) V(-1) s(-1) and an on-off current ratio of 7.6 × 10(6) and enhanced long-term stability compared to the pentacene thin-film transistor.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil

2017-11-13

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor\\'s width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Theory and application of dual-transistor charge separation analysis

International Nuclear Information System (INIS)

Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Sexton, F.W.; Shaneyfelt, M.R.

1989-01-01

The authors describe a dual-transistor charge separation method to evaluate the radiation response of MOS transistors. This method requires that n- and p-channel transistors with identically processed oxides be irradiated under identical conditions at the same oxide electric fields. Combining features of single-transistor midgap and mobility methods, the authors show how one may determine threshold voltage shifts due to oxide-trapped and interface-trapped charge from standard threshold voltage and mobility measurements. These measurements can be made at currents 2-5 orders of magnitude higher than those required for midgap, subthreshold slope, and charge-pumping methods. The dual-transistor method contains no adjustable parameters, and includes an internal self-consistency check. The accuracy of the method is verified by comparison to midgap, subthreshold slope, and charge-pumping methods for several MOS processes and technologies

Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors

KAUST Repository

Hanna, Amir

2016-01-01

This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving

Gallium nitride vertical power devices on foreign substrates: a review and outlook

Science.gov (United States)

Zhang, Yuhao; Dadgar, Armin; Palacios, Tomás

2018-07-01

Vertical gallium nitride (GaN) power devices have attracted increased attention due to their superior high-voltage and high-current capacity as well as easier thermal management than lateral GaN high electron mobility transistors. Vertical GaN devices are promising candidates for next-generation power electronics in electric vehicles, data centers, smart grids and renewable energy process. The use of low-cost foreign substrates such as silicon (Si) substrates, instead of the expensive free-standing GaN substrates, could greatly trim material cost and enable large-diameter wafer processing while maintaining high device performance. This review illustrates recent progress in material epitaxy, device design, device physics and processing technologies for the development of vertical GaN power devices on low-cost foreign substrates. Although the device technologies are still at the early stage of development, state-of-the-art vertical GaN-on-Si power diodes have already shown superior Baliga’s figure of merit than commercial SiC and Si power devices at the voltage classes beyond 600 V. Furthermore, we unveil the design space of vertical GaN power devices on native and different foreign substrates, from the analysis of the impact of dislocation and defects on device performance. We conclude by identifying the application space, current challenges and exciting research opportunities in this very dynamic research field.

AlN/GaN heterostructures for normally-off transistors

Energy Technology Data Exchange (ETDEWEB)

Zhuravlev, K. S., E-mail: zhur@isp.nsc.ru; Malin, T. V.; Mansurov, V. G.; Tereshenko, O. E. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation); Abgaryan, K. K.; Reviznikov, D. L. [Dorodnicyn Computing Centre of the Russian Academy of Sciences (Russian Federation); Zemlyakov, V. E.; Egorkin, V. I. [National Research University of Electronic Technology (MIET) (Russian Federation); Parnes, Ya. M.; Tikhomirov, V. G. [Joint Stock Company “Svetlana-Electronpribor” (Russian Federation); Prosvirin, I. P. [Russian Academy of Sciences, Boreskov Institute of Catalysis, Siberian Branch (Russian Federation)

2017-03-15

The structure of AlN/GaN heterostructures with an ultrathin AlN barrier is calculated for normally-off transistors. The molecular-beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with a two-dimensional electron gas is developed. Normally-off transistors with a maximum current density of ~1 A/mm, a saturation voltage of 1 V, a transconductance of 350 mS/mm, and a breakdown voltage of more than 60 V are demonstrated. Gate lag and drain lag effects are almost lacking in these transistors.

Patterning solution-processed organic single-crystal transistors with high device performance

Directory of Open Access Journals (Sweden)

Yun Li

2011-06-01

Full Text Available We report on the patterning of organic single-crystal transistors with high device performance fabricated via a solution process under ambient conditions. The semiconductor was patterned on substrates via surface selective deposition. Subsequently, solvent-vapor annealing was performed to reorganize the semiconductor into single crystals. The transistors exhibited field-effect mobility (μFET of up to 3.5 cm2/V s. Good reliability under bias-stress conditions indicates low density of intrinsic defects in crystals and low density of traps at the active interfaces. Furthermore, the Y function method clearly suggests that the variation of μFET of organic crystal transistors was caused by contact resistance. Further improvement of the device with higher μFET with smaller variation can be expected when lower and more uniform contact resistance is achieved.

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

Science.gov (United States)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

High Mobility Flexible Amorphous IGZO Thin-Film Transistors with a Low Thermal Budget Ultra-Violet Pulsed Light Process.

Science.gov (United States)

Benwadih, M; Coppard, R; Bonrad, K; Klyszcz, A; Vuillaume, D

2016-12-21

Amorphous, sol-gel processed, indium gallium zinc oxide (IGZO) transistors on plastic substrate with a printable gate dielectric and an electron mobility of 4.5 cm 2 /(V s), as well as a mobility of 7 cm 2 /(V s) on solid substrate (Si/SiO 2 ) are reported. These performances are obtained using a low temperature pulsed light annealing technique. Ultraviolet (UV) pulsed light system is an innovative technique compared to conventional (furnace or hot-plate) annealing process that we successfully implemented on sol-gel IGZO thin film transistors (TFTs) made on plastic substrate. The photonic annealing treatment has been optimized to obtain IGZO TFTs with significant electrical properties. Organic gate dielectric layers deposited on this pulsed UV light annealed films have also been optimized. This technique is very promising for the development of amorphous IGZO TFTs on plastic substrates.

Solution-processed 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene thin-film transistors with a polymer dielectric on a flexible substrate

International Nuclear Information System (INIS)

Shin, Sang-Il; Kwon, Jae-Hong; Ju, Byeong-Kwon; Kang, Hochul

2008-01-01

The authors report the fabrication of solution-processed 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene thin-film transistors with a cross-linked poly-4-vinylphenol (PVP) dielectric on a polyethersulphone (PES) substrate. The device exhibited useful electrical characteristics, including a saturation field effect mobility of 2.08 × 10 −2 cm 2 V −1 s −1 , a current on/off ratio of 10 5 , a threshold voltage of −2 V and an excellent subthreshold slope of 0.86 V/dec. It was demonstrated that the significant improvement in the subthreshold slope of TIPS-pentacene TFTs could be attributed to a decreased carrier trap density at the PVP/TIPS-pentacene film interface. Furthermore, a 1,2,3,4-tetrahydronaphthalene (Tetralin) solvent used in this study had a high boiling point, which had a positive effect on the morphology and the molecular ordering of the TIPS-pentacene film

Microstructure-mobility correlation in self-organised, conjugated polymer field-effect transistors

DEFF Research Database (Denmark)

Sirringhaus, H.; Brown, P.J.; Friend, R.H.

2000-01-01

We have investigated the correlation between polymer microstructure and charge carrier mobility in high-mobility, self-organised field-effect transistors of poly-3-hexyl-thiophene (P3HT). Two different preferential orientations of the microcrystalline P3HT domains with respect to the substrate have...

Investigations on field-effect transistors based on two-dimensional materials

Energy Technology Data Exchange (ETDEWEB)

Finge, T.; Riederer, F.; Grap, T.; Knoch, J. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Mueller, M.R. [Institute of Semiconductor Electronics, RWTH Aachen University (Germany); Infineon Technologies, Villach (Austria); Kallis, K. [Intelligent Microsystems Chair, TU Dortmund University (Germany)

2017-11-15

In the present article, experimental and theoretical investigations regarding field-effect transistors based on two-dimensional (2D) materials are presented. First, the properties of contacts between a metal and 2D material are discussed. To this end, metal-to-graphene contacts as well to transition metal dichalcogenides (TMD) are studied. Whereas metal-graphene contacts can be tuned with an appropriate back-gate, metal-TMD contacts exhibit strong Fermi level pinning showing substantially limited maximum possible drive current. Next, tungsten diselenide (WSe{sub 2}) field-effect transistors are presented. Employing buried-triple-gate substrates allows tuning source, channel and drain by applying appropriate gate voltages so that the device can be reconfigured to work as n-type, p-type and as so-called band-to-band tunnel field-effect transistor on the same WSe{sub 2} flake. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

The next generation CdTe technology- Substrate foil based solar cells

Energy Technology Data Exchange (ETDEWEB)

Ferekides, Chris [Univ. of South Florida, Tampa, FL (United States)

2017-03-22

The main objective of this project was the development of one of the most promising Photovoltaic (PV) materials CdTe into a versatile, cost effective, and high throughput technology, by demonstrating substrate devices on foil substrates using high throughput fabrication conditions. The typical CdTe cell is of the superstrate configuration where the solar cell is fabricated on a glass superstrate by the sequential deposition of a TCO, n-type heterojunction partner, p-CdTe absorber, and back contact. Large glass modules are heavy and present significant challenges during manufacturing (uniform heating, etc.). If a substrate CdTe cell could be developed (the main goal of this project) a roll-to-toll high throughput technology could be developed.

Roll-to-roll UV imprint for bottom-up transistor fabrication

NARCIS (Netherlands)

Maury, P.; Turkenburg, D.H.; Stroeks, N.; Giesen, P.; Wijnen, M.; Tacken, R.; Meinders, E.R.; Werf, R. van der

2011-01-01

We propose a design to fabricate transistors on flexible substrates in a bottom-up fashion using R2R UV-imprint lithography. The design consists of a template composed of multilevel as well as gray level features, the later used to facilitate device interconnection. A hard mold is fabricated by LBR

Operating method of amorphous thin film semiconductor element

Energy Technology Data Exchange (ETDEWEB)

Mori, Koshiro; Ono, Masaharu; Hanabusa, Akira; Osawa, Michio; Arita, Takashi

1988-05-31

The existing technologies concerning amorphous thin film semiconductor elements are the technologies concerning the formation of either a thin film transistor or an amorphous Si solar cell on a substrate. In order to drive a thin film transistor for electronic equipment control by the output power of an amorphous Si solar cell, it has been obliged to drive the transistor weth an amorphous solar cell which was formed on a substrate different from that for the transistor. Accordingly, the space for the amorphous solar cell, which was formed on the different substrate, was additionally needed on the substrate for the thin film transistor. In order to solve the above problem, this invention proposes an operating method of an amorphous thin film semiconductor element that after forming an amorphous Si solar cell through lamination on the insulation coating film which covers the thin film transistor formed on the substrate, the thin film transistor is driven by the output power of this solar cell. The invention eliminates the above superfluous space and reduces the size of the amorphous thin film semiconductor element including the electric source. (3 figs)

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

Science.gov (United States)

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Investigations of Tunneling for Field Effect Transistors

OpenAIRE

Matheu, Peter

2012-01-01

Over 40 years of scaling dimensions for new and continuing product cycles has introduced new challenges for transistor design. As the end of the technology roadmap for semiconductors approaches, new device structures are being investigated as possible replacements for traditional metal-oxide-semiconductor field effect transistors (MOSFETs). Band-to-band tunneling (BTBT) in semiconductors, often viewed as an adverse effect of short channel lengths in MOSFETs, has been discussed as a promising ...

Characteristics of thin-film transistors based on silicon nitride passivation by excimer laser direct patterning

International Nuclear Information System (INIS)

Chen, Chao-Nan; Huang, Jung-Jie

2013-01-01

This study explored the removal of silicon nitride using KrF laser ablation technology with a high threshold fluence of 990 mJ/cm 2 . This technology was used for contact hole patterning to fabricate SiN x -passivation-based amorphous-silicon thin films in a transistor device. Compared to the photolithography process, laser direct patterning using KrF laser ablation technology can reduce the number of process steps by at least three. Experimental results showed that the mobility and threshold voltages of thin film transistors patterned using the laser process were 0.16 cm 2 /V-sec and 0.2 V, respectively. The device performance and the test results of gate voltage stress reliability demonstrated that laser direct patterning is a promising alternative to photolithography in the panel manufacturing of thin-film transistors for liquid crystal displays. - Highlights: ► KrF laser ablation technology is used to remove silicon nitride. ► A simple method for direct patterning contact-hole in thin-film-transistor device. ► Laser technology reduced processing by at least three steps

Planar transistors and impatt diodes with ion implantation

International Nuclear Information System (INIS)

Dorendorf, H.; Glawischnig, H.; Grasser, L.; Hammerschmitt, J.

1975-03-01

Low frequency planar npn and pnp transistors have been developed in which the base and emitter have been fabricated using ion implantation of boron and phosphorus by a drive-in diffusion. Electrical parameters of the transistors are comparable with conventionally produced transistors; the noise figure was improved and production tolerances were significantly reduced. Silicon-impatt diodes for the microwave range were also fabricated with implanted pn junctions and tested for their high frequency characteristics. These diodes, made in an improved upside down technology, delivered output power up to 40 mW (burn out power) at 30 GHz. Reverse leakage current and current carrying capability of these diodes were comparable to diffused structures. (orig.) 891 ORU 892 MB [de

Instrument employing a charge flow transistor

International Nuclear Information System (INIS)

1981-01-01

The invention concerns instruments employing charge-flow transistors that operate to sense a property in the surrounding environment. It is based on a particular sensor principle, thin-film conduction. The instruments described include a charge-flow transistor with semiconductor substrate, a source region, a drain region, a gate insulator, and a gapped electrode structure with a thin-film sensor material in the gap. The sensor material has an electrical conductance that is sensitive to a property of the ambient environment and has a surface conductance that differs substantially from its bulk conductance. The main object is to provide a low-cost instrument for early-warning fire-detection devices: in this case the property detected would be the products of combustion. Other properties that can be sensed include gases or vapors, free radicals, vapor electromagnetic radiation, subatomic particles, atomic or molecular beams, changes in ambient pressure or temperature, the chemical composition and the electrochemical potential of a solution. (U.K.)

Instrument employing a charge flow transistor

Energy Technology Data Exchange (ETDEWEB)

1981-03-11

The invention concerns instruments employing charge-flow transistors that operate to sense a property in the surrounding environment. It is based on a particular sensor principle, thin-film conduction. The instruments described include a charge-flow transistor with semiconductor substrate, a source region, a drain region, a gate insulator, and a gapped electrode structure with a thin-film sensor material in the gap. The sensor material has an electrical conductance that is sensitive to a property of the ambient environment and has a surface conductance that differs substantially from its bulk conductance. The main object is to provide a low-cost instrument for early-warning fire-detection devices: in this case the property detected would be the products of combustion. Other properties that can be sensed include gases or vapors, free radicals, vapor electromagnetic radiation, subatomic particles, atomic or molecular beams, changes in ambient pressure or temperature, the chemical composition and the electrochemical potential of a solution.

Si and Mg pair-doped interlayers for improving performance of AlGaN/GaN heterostructure field effect transistors grown on Si substrate

Science.gov (United States)

Ni, Yi-Qiang; He, Zhi-Yuan; Yao, Yao; Yang, Fan; Zhou, De-Qiu; Zhou, Gui-Lin; Shen, Zhen; Zhong, Jian; Zheng, Yue; Zhang, Bai-Jun; Liu, Yang

2015-05-01

We report a novel structure of AlGaN/GaN heterostructure field effect transistors (HFETs) with a Si and Mg pair-doped interlayer grown on Si substrate. By optimizing the doping concentrations of the pair-doped interlayers, the mobility of 2DEG increases by twice for the conventional structure under 5 K due to the improved crystalline quality of the conduction channel. The proposed HFET shows a four orders lower off-state leakage current, resulting in a much higher on/off ratio (˜ 109). Further temperature-dependent performance of Schottky diodes revealed that the inhibition of shallow surface traps in proposed HFETs should be the main reason for the suppression of leakage current. Project supported by the National Natural Science Foundation of China (Grant Nos. 51177175 and 61274039), the National Basic Research Project of China (Grant Nos. 2010CB923200 and 2011CB301903), the Ph.D. Program Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Sci. & Tech. Collaboration Program of China (Grant No. 2012DFG52260), the National High-tech R&D Program of China (Grant No. 2014AA032606), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics (Grant No. IOSKL2014KF17).

A Robust Highly Aligned DNA Nanowire Array-Enabled Lithography for Graphene Nanoribbon Transistors.

Science.gov (United States)

Kang, Seok Hee; Hwang, Wan Sik; Lin, Zhiqun; Kwon, Se Hun; Hong, Suck Won

2015-12-09

Because of its excellent charge carrier mobility at the Dirac point, graphene possesses exceptional properties for high-performance devices. Of particular interest is the potential use of graphene nanoribbons or graphene nanomesh for field-effect transistors. Herein, highly aligned DNA nanowire arrays were crafted by flow-assisted self-assembly of a drop of DNA aqueous solution on a flat polymer substrate. Subsequently, they were exploited as "ink" and transfer-printed on chemical vapor deposited (CVD)-grown graphene substrate. The oriented DNA nanowires served as the lithographic resist for selective removal of graphene, forming highly aligned graphene nanoribbons. Intriguingly, these graphene nanoribbons can be readily produced over a large area (i.e., millimeter scale) with a high degree of feature-size controllability and a low level of defects, rendering the fabrication of flexible two terminal devices and field-effect transistors.

Nanoscale conductive pattern of the homoepitaxial AlGaN/GaN transistor.

Science.gov (United States)

Pérez-Tomás, A; Catalàn, G; Fontserè, A; Iglesias, V; Chen, H; Gammon, P M; Jennings, M R; Thomas, M; Fisher, C A; Sharma, Y K; Placidi, M; Chmielowska, M; Chenot, S; Porti, M; Nafría, M; Cordier, Y

2015-03-20

The gallium nitride (GaN)-based buffer/barrier mode of growth and morphology, the transistor electrical response (25-310 °C) and the nanoscale pattern of a homoepitaxial AlGaN/GaN high electron mobility transistor (HEMT) have been investigated at the micro and nanoscale. The low channel sheet resistance and the enhanced heat dissipation allow a highly conductive HEMT transistor (Ids > 1 A mm(-1)) to be defined (0.5 A mm(-1) at 300 °C). The vertical breakdown voltage has been determined to be ∼850 V with the vertical drain-bulk (or gate-bulk) current following the hopping mechanism, with an activation energy of 350 meV. The conductive atomic force microscopy nanoscale current pattern does not unequivocally follow the molecular beam epitaxy AlGaN/GaN morphology but it suggests that the FS-GaN substrate presents a series of preferential conductive spots (conductive patches). Both the estimated patches density and the apparent random distribution appear to correlate with the edge-pit dislocations observed via cathodoluminescence. The sub-surface edge-pit dislocations originating in the FS-GaN substrate result in barrier height inhomogeneity within the HEMT Schottky gate producing a subthreshold current.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

Nanowire transistors physics of devices and materials in one dimension

CERN Document Server

Colinge, Jean-Pierre

2016-01-01

From quantum mechanical concepts to practical circuit applications, this book presents a self-contained and up-to-date account of the physics and technology of nanowire semiconductor devices. It includes a unified account of the critical ideas central to low-dimensional physics and transistor physics which equips readers with a common framework and language to accelerate scientific and technological developments across the two fields. Detailed descriptions of novel quantum mechanical effects such as quantum current oscillations, the metal-to-semiconductor transition and the transition from classical transistor to single-electron transistor operation are described in detail, in addition to real-world applications in the fields of nanoelectronics, biomedical sensing techniques, and advanced semiconductor research. Including numerous illustrations to help readers understand these phenomena, this is an essential resource for researchers and professional engineers working on semiconductor devices and materials in ...

Roll-to-roll compatible organic thin film transistor manufacturing technique by printing, lamination, and laser ablation

International Nuclear Information System (INIS)

Hassinen, Tomi; Ruotsalainen, Teemu; Laakso, Petri; Penttilä, Raimo; Sandberg, Henrik G.O.

2014-01-01

We present roll-to-roll printing compatible techniques for manufacturing organic thin film transistors using two separately processed foils that are laminated together. The introduction of heat-assisted lamination opens up possibilities for material and processing combinations. The lamination of two separately processed substrates together will allow usage of pre-patterned electrodes on both substrates and materials with non-compatible solvents. Also, the surface microstructure is formed differently when laminating dry films together compared to film formation from liquid phase. Demonstrator transistors, inverters and ring oscillators were produced using lamination techniques. Finally, a roll-to-roll compatible lamination concept is proposed where also the source and drain electrodes are patterned by laser ablation. The demonstrator transistors have shown very good lifetime in air, which is contributed partly to the good material combination and partly to the enhanced interface formation in heat-assisted lamination process. - Highlights: • A roll-to-roll compatible lamination technique for printed electronics is proposed. • Laser ablation allows highly defined metal top and bottom electrodes. • Method opens up processing possibilities for incompatible materials and solvents. • Shearing forces may enhance molecular orientation and packing. • An air stable polymer transistor is demonstrated with a lifetime of years

Enhanced transconductance in a double-gate graphene field-effect transistor

Science.gov (United States)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Effect of ion-beam gettering on the GaAs transistor structure parameters under neutron irradiation

International Nuclear Information System (INIS)

Obolenskij, S.V.; Skupov, V.D.

2000-01-01

It is established that the neutron irradiation negative effect on the parameters of the field transistors with the Schottky shut-off on the basis of the epitaxial gallium arsenide is essentially reduced when the argon ions are preliminary implanted into structure on the substrate side. The above effect is explained through remotely controlled gettering by ion irradiation of admixtures and defects in the transistor active areas related with origination of deep levels under the neutron fluence [ru

Micro-structure-mobility correlation in self-organised, conjugated polymer field-effect transistors

NARCIS (Netherlands)

Sirringhaus, H.; Brown, P.J.; Friend, R.H.; Nielsen, M.M.; Bechgaard, K.; Langeveld-Voss, B.M.W.; Spiering, A.J.H.; Janssen, R.A.J.; Meijer, E.W.

2000-01-01

We have investigated the correlation between polymer microstructure and charge carrier mobility in high-mobility, self-organised field-effect transistors of poly-3-hexyl-thiophene (P3HT). Two different preferential orientations of the microcrystalline P3HT domains with respect to the substrate have

SOI Fully complementary BI-JFET-MOS technology for analog-digital applications with vertical BJT's

International Nuclear Information System (INIS)

Delevoye, E.; Blanc, J.P.; Bonaime, J.; Pontcharra, J. de; Gautier, J.; Martin, F.; Truche, R.

1993-01-01

A silicon-on-insulator, fully complementary, Bi-JFET-MOS technology has been developed for realizing multi-megarad hardened mixed analog-digital circuits. The six different active components plus resistors and capacitors have been successfully integrated in a 25-mask process using SIMOX substrate and 1 μm thick epitaxial layer. Different constraints such as device compatibility, complexity not higher than BiCMOS technology and breakdown voltages suitable for analog applications have been considered. Several process splits have been realized and all the characteristics presented here have been measured on the same split. P + gate is used for PMOS transistor to get N and PMOST symmetrical characteristics. Both NPN and PNP vertical bipolar transistors with poly-emitters show f T > 5 GHz. 2-separated gate JFET's need no additional mask. (authors). 9 figs., 1 tab

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations

Science.gov (United States)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-01

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

Selective Dirac voltage engineering of individual graphene field-effect transistors for digital inverter and frequency multiplier integrations.

Science.gov (United States)

Sul, Onejae; Kim, Kyumin; Jung, Yungwoo; Choi, Eunsuk; Lee, Seung-Beck

2017-09-15

The ambipolar band structure of graphene presents unique opportunities for novel electronic device applications. A cycle of gate voltage sweep in a conventional graphene transistor produces a frequency-doubled output current. To increase the frequency further, we used various graphene doping control techniques to produce Dirac voltage engineered graphene channels. The various surface treatments and substrate conditions produced differently doped graphene channels that were integrated on a single substrate and multiple Dirac voltages were observed by applying a single gate voltage sweep. We applied the Dirac voltage engineering techniques to graphene field-effect transistors on a single chip for the fabrication of a frequency multiplier and a logic inverter demonstrating analog and digital circuit application possibilities.

High mobility n-type organic thin-film transistors deposited at room temperature by supersonic molecular beam deposition

Energy Technology Data Exchange (ETDEWEB)

Chiarella, F., E-mail: fabio.chiarella@spin.cnr.it; Barra, M.; Ciccullo, F.; Cassinese, A. [CNR-SPIN and Physics Department, University of Naples, Piazzale Tecchio 80, I-80125 Naples (Italy); Toccoli, T.; Aversa, L.; Tatti, R.; Verucchi, R. [IMEM-CNR-FBK Division of Trento, Via alla Cascata 56/C, I-38123 Povo (Italy); Iannotta, S. [IMEM-CNR, Parco Area delle Scienze 37/A, I-43124 Parma (Italy)

2014-04-07

In this paper, we report on the fabrication of N,N′-1H,1H-perfluorobutil dicyanoperylenediimide (PDIF-CN{sub 2}) organic thin-film transistors by Supersonic Molecular Beam Deposition. The devices exhibit mobility up to 0.2 cm{sup 2}/V s even if the substrate is kept at room temperature during the organic film growth, exceeding by three orders of magnitude the electrical performance of those grown at the same temperature by conventional Organic Molecular Beam Deposition. The possibility to get high-mobility n-type transistors avoiding thermal treatments during or after the deposition could significantly extend the number of substrates suitable to the fabrication of flexible high-performance complementary circuits by using this compound.

Molecular thermal transistor: Dimension analysis and mechanism

Science.gov (United States)

Behnia, S.; Panahinia, R.

2018-04-01

Recently, large challenge has been spent to realize high efficient thermal transistors. Outstanding properties of DNA make it as an excellent nano material in future technologies. In this paper, we introduced a high efficient DNA based thermal transistor. The thermal transistor operates when the system shows an increase in the thermal flux despite of decreasing temperature gradient. This is what called as negative differential thermal resistance (NDTR). Based on multifractal analysis, we could distinguish regions with NDTR state from non-NDTR state. Moreover, Based on dimension spectrum of the system, it is detected that NDTR state is accompanied by ballistic transport regime. The generalized correlation sum (analogous to specific heat) shows that an irregular decrease in the specific heat induces an increase in the mean free path (mfp) of phonons. This leads to the occurrence of NDTR.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

KAUST Repository

Petti, Luisa

2017-03-17

We report on low operating voltage thin-film transistors (TFTs) and integrated inverters based on copper(I) thiocyanate (CuSCN) layers processed from solution at low temperature on free-standing plastic foils. As-fabricated coplanar bottom-gate and staggered top-gate TFTs exhibit hole-transporting characteristics with average mobility values of 0.0016 cm2 V−1 s−1 and 0.013 cm2 V−1 s−1, respectively, current on/off ratio in the range 102–104, and maximum operating voltages between −3.5 and −10 V, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as −3.5 V. Importantly, discrete CuSCN transistors and integrated logic inverters remain fully functional even when mechanically bent to a tensile radius of 4 mm, demonstrating the potential of the technology for flexible electronics.

Wet etching rates of InGaZnO for the fabrication of transparent thin-film transistors on plastic substrates

International Nuclear Information System (INIS)

Lee, Chi-Yuan; Chang, Chienliu; Shih, Wen-Pin; Dai, Ching-Liang

2010-01-01

The wet etch process for amorphous indium gallium zinc oxide (a-IGZO or a-InGaZnO) by using various etchants is reported. The etch rates of a-IGZO, compared to another indium-based oxides including indium gallium oxide (IGO), indium zinc oxide (IZO), and indium tin oxide (ITO), are measured by using acetic acid, citric acid, hydrochloric acid, perchloric acid, and aqua ammonia as etchants, respectively. In our experimental results, the etch rate of the transparent oxide semiconductor (TOS) films by using acid solutions ranked accordingly from high to low are IZO, IGZO, IGO and ITO. Comparatively, the etch rate of the TOS films by using alkaline ammonia solution ranked from high to low are IGZO, IZO, IGO and ITO, in that order. Using the proposed wet etching process with high etch selectivity, bottom-gate-type thin-film transistors (TFTs) based on a-IGZO channels and Y 2 O 3 gate-insulators were fabricated by radio-frequency sputtering on plastic substrates. The wet etch processed TFT with 30 μm gate length and 120 μm gate width exhibits a saturation mobility of 46.25 cm 2 V -1 s -1 , a threshold voltage of 1.3 V, a drain current on-off ratio > 10 6 , and subthreshold gate voltage swing of 0.29 V decade -1 . The performance of the TFTs ensures the applicability of the wet etching process for IGZO to electronic devices on organic polymer substrates.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

Science.gov (United States)

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Directory of Open Access Journals (Sweden)

Gammon P.M.

2017-01-01

Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

Fabrication de transistors monoelectroniques pour la detection de charge

Science.gov (United States)

Richard, Jean-Philippe

Le transistor monoelectro'nique (SET) est un candidat que l'on croyait avoir la capacite de remplacer le transistor des circuits integres actuel (MOSFET). Pour des raisons de faible gain en voltage, d'impedance de sortie elevee et de sensibilite aux fluctuations de charges, il est considere aujourd'hui qu'un hybride tirant profit des deux technologies est plus avantageux. En exploitant sa lacune d'etre sensible aux variations de charge, le SET est davantage utilise dans des applications ou la detection de charge s'avere indispensable, notamment dans les domaines de la bio-detection et de l'informatique quantique. Ce memoire presente une etude du transistor monoelectronique utilise en tant que detecteur de charge. La methode de fabrication est basee sur le procede nanodamascene developpe par Dubuc et al. [11] permettant au transistor monoelectronique de fonctionner a temperature ambiante. La temperature d'operation etant intimement liee a la geometrie du SET, la cle du procede nanodamascene reside dans le polissage chimico-mecanique (CMP) permettant de reduire l'epaisseur des SET jusqu'a des valeurs de quelques nanametres. Dans ce projet de maitrise, nous avons cependant opte pour que le SET soit opere a temperature cryogenique. Une faible temperature d'operation permet le relachement des contraintes de dimensions des dispositifs. En considerant les variations de procedes normales pouvant survenir lors de la fabrication, la temperature d'operation maximale calculee en conception s'etend de 27 K a 90 K, soit une energie de charge de 78 meV a 23 meV. Le gain du detecteur de charge etant dependant de la distance de couplage, les resultats de simulations demontrent que cette distance doit etre de 200 nm pour que la detection de charge soit optimale. Les designs concus sont ensuite fabriques sur substrat d'oxyde de silicium. Les resultats de fabrication de SET temoignent de la robustesse du procede nanodamascene. En effet, les dimensions atteintes experimentalement s

Flexible Textile-Based Organic Transistors Using Graphene/Ag Nanoparticle Electrode

Science.gov (United States)

Kim, Youn; Kwon, Yeon Ju; Lee, Kang Eun; Oh, Youngseok; Um, Moon-Kwang; Seong, Dong Gi; Lee, Jea Uk

2016-01-01

Highly flexible and electrically-conductive multifunctional textiles are desirable for use in wearable electronic applications. In this study, we fabricated multifunctional textile composites by vacuum filtration and wet-transfer of graphene oxide films on a flexible polyethylene terephthalate (PET) textile in association with embedding Ag nanoparticles (AgNPs) to improve the electrical conductivity. A flexible organic transistor can be developed by direct transfer of a dielectric/semiconducting double layer on the graphene/AgNP textile composite, where the textile composite was used as both flexible substrate and conductive gate electrode. The thermal treatment of a textile-based transistor enhanced the electrical performance (mobility = 7.2 cm2·V−1·s−1, on/off current ratio = 4 × 105, and threshold voltage = −1.1 V) due to the improvement of interfacial properties between the conductive textile electrode and the ion-gel dielectric layer. Furthermore, the textile transistors exhibited highly stable device performance under extended bending conditions (with a bending radius down to 3 mm and repeated tests over 1000 cycles). We believe that our simple methods for the fabrication of graphene/AgNP textile composite for use in textile-type transistors can potentially be applied to the development of flexible large-area electronic clothes. PMID:28335276

BUSFET - A Novel Radiation-Hardened SOI Transistor

International Nuclear Information System (INIS)

Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

1999-01-01

A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors.

Science.gov (United States)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-12-11

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption.

Flexible Sensory Platform Based on Oxide-based Neuromorphic Transistors

Science.gov (United States)

Liu, Ning; Zhu, Li Qiang; Feng, Ping; Wan, Chang Jin; Liu, Yang Hui; Shi, Yi; Wan, Qing

2015-01-01

Inspired by the dendritic integration and spiking operation of a biological neuron, flexible oxide-based neuromorphic transistors with multiple input gates are fabricated on flexible plastic substrates for pH sensor applications. When such device is operated in a quasi-static dual-gate synergic sensing mode, it shows a high pH sensitivity of ~105 mV/pH. Our results also demonstrate that single-spike dynamic mode can remarkably improve pH sensitivity and reduce response/recover time and power consumption. Moreover, we find that an appropriate negative bias applied on the sensing gate electrode can further enhance the pH sensitivity and reduce the power consumption. Our flexible neuromorphic transistors provide a new-concept sensory platform for biochemical detection with high sensitivity, rapid response and ultralow power consumption. PMID:26656113

Unijunction transistors

International Nuclear Information System (INIS)

1981-01-01

The electrical characteristics of unijunction transistors can be modified by irradiation with electron beams in excess of 400 KeV and at a dose rate of 10 13 to 10 16 e/cm 2 . Examples are given of the effect of exposing the emitter-base junctions of transistors to such lattice defect causing radiation for a time sufficient to change the valley current of the transistor. (U.K.)

320-nm Flexible Solution-Processed 2,7-dioctyl[1] benzothieno[3,2-b]benzothiophene Transistors

OpenAIRE

Ren, Hang; Tang, Qingxin; Tong, Yanhong; Liu, Yichun

2017-01-01

Flexible organic thin-film transistors (OTFTs) have received extensive attention due to their outstanding advantages such as light weight, low cost, flexibility, large-area fabrication, and compatibility with solution-processed techniques. However, compared with a rigid substrate, it still remains a challenge to obtain good device performance by directly depositing solution-processed organic semiconductors onto an ultrathin plastic substrate. In this work, ultrathin flexible OTFTs are success...

GaN transistors on Si for switching and high-frequency applications

Science.gov (United States)

Ueda, Tetsuzo; Ishida, Masahiro; Tanaka, Tsuyoshi; Ueda, Daisuke

2014-10-01

In this paper, recent advances of GaN transistors on Si for switching and high-frequency applications are reviewed. Novel epitaxial structures including superlattice interlayers grown by metal organic chemical vapor deposition (MOCVD) relieve the strain and eliminate the cracks in the GaN over large-diameter Si substrates up to 8 in. As a new device structure for high-power switching application, Gate Injection Transistors (GITs) with a p-AlGaN gate over an AlGaN/GaN heterostructure successfully achieve normally-off operations maintaining high drain currents and low on-state resistances. Note that the GITs on Si are free from current collapse up to 600 V, by which the drain current would be markedly reduced after the application of high drain voltages. Highly efficient operations of an inverter and DC-DC converters are presented as promising applications of GITs for power switching. The high efficiencies in an inverter, a resonant LLC converter, and a point-of-load (POL) converter demonstrate the superior potential of the GaN transistors on Si. As for high-frequency transistors, AlGaN/GaN heterojuction field-effect transistors (HFETs) on Si designed specifically for microwave and millimeter-wave frequencies demonstrate a sufficiently high output power at these frequencies. Output powers of 203 W at 2.5 GHz and 10.7 W at 26.5 GHz are achieved by the fabricated GaN transistors. These devices for switching and high-frequency applications are very promising as future energy-efficient electronics because of their inherent low fabrication cost and superior device performance.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Proton conducting sodium alginate electrolyte laterally coupled low-voltage oxide-based transistors

Energy Technology Data Exchange (ETDEWEB)

Liu, Yang Hui; Wan, Qing, E-mail: wanqing@nju.edu.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China); Qiang Zhu, Li, E-mail: lqzhu@nimte.ac.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Shi, Yi [School of Electronic Science and Engineering, Nanjing University, Nanjing 210093 (China)

2014-03-31

Solution-processed sodium alginate electrolyte film shows a high proton conductivity of ∼5.5 × 10{sup −3} S/cm and a high lateral electric-double-layer (EDL) capacitance of ∼2.0 μF/cm{sup 2} at room temperature with a relative humidity of 57%. Low-voltage in-plane-gate indium-zinc-oxide-based EDL transistors laterally gated by sodium alginate electrolytes are fabricated on glass substrates. The field-effect mobility, current ON/OFF ratio, and subthreshold swing of such EDL transistors are estimated to be 4.2 cm{sup 2} V{sup −1} s{sup −1}, 2.8 × 10{sup 6}, and 130 mV/decade, respectively. At last, a low-voltage driven resistor-load inverter is also demonstrated. Such in-plane-gate EDL transistors have potential applications in portable electronics and low-cost biosensors.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

Impact of the substrate on the efficiency of thin film thermoelectric technology

International Nuclear Information System (INIS)

Alvarez-Quintana, J.

2015-01-01

Thermoelectricity is one of the simplest technologies for thermal energy conversion. Moreover, because of their relatively low efficiency, bulk thermoelectric materials are generally used in environments where their solid state nature outweighs their poor efficiency. Nevertheless, low dimensional thermoelectric materials shed a light in order to achieve higher thermoelectric performance than their bulk counterparts via quantum and spatial confinement of energy carriers. The Thermoelectric figure of merit ZT is the basic criterion for estimating the performance of thermoelectric materials. In this work, by way of an extension of the Harman method to thin films onto substrate to evaluate ZT it is shown that the solely presence of a substrate affects significantly the intrinsic value of the ZT independently of the electrical and thermal nature of the substrate. Furthermore, the model unveils that as the thickness ratio between substrate and thin film increases, the parameter ZT sharply tends to zero; this effect opens a serious problem to overcome by the thin film thermoelectric technology, especially at nanoscale. In this sense, challenges in order to engineering planar thermoelectric devices at micro/nanoscale are properly identified. - Highlights: • Extended Harman method to evaluate ZT of thin films onto substrate is presented. • ZT of thermoelectric thin films is strongly affected by substrate's nature. • Thin dielectric substrates are desirable to hold ZT in in-plane configuration. • Film/substrate thickness ratio play important role on the device performance. • Challenges to engineering planar thermoelectric devices are properly identified

Fabrication of double-dot single-electron transistor in silicon nanowire

International Nuclear Information System (INIS)

Jo, Mingyu; Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Ono, Yukinori; Inokawa, Hiroshi; Choi, Jung-Bum; Takahashi, Yasuo

2010-01-01

We propose a simple method for fabricating Si single-electron transistors (SET) with coupled dots by means of a pattern-dependent-oxidation (PADOX) method. The PADOX method is known to convert a small one-dimensional Si wire formed on a silicon-on-insulator (SOI) substrate into a SET automatically. We fabricated a double-dot Si SET when we oxidized specially designed Si nanowires formed on SOI substrates. We analyzed the measured electrical characteristics by fitting the measurement and simulation results and confirmed the double-dot formation and the position of the two dots in the Si wire.

BUSFET -- A radiation-hardened SOI transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

Operational Stability of Organic Field‐Effect Transistors

NARCIS (Netherlands)

Bobbert, P.A.; Sharma, A.; Matthijssen, S.J.G.; Kemerink, M.; de Leeuw, D.M.

2012-01-01

Organic field-effect transistors (OFETs) are considered in technological applications for which low cost or mechanical flexibility are crucial factors. The environmental stability of the organic semiconductors used in OFETs has improved to a level that is now sufficient for commercialization.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon S.; Hussain, Muhammad Mustafa

2017-01-01

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Carbon nanotube transistors scaled to a 40-nanometer footprint.

Science.gov (United States)

Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

2017-06-30

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Stable Low-Voltage Operation Top-Gate Organic Field-Effect Transistors on Cellulose Nanocrystal Substrates

Science.gov (United States)

Cheng-Yin Wang; Canek Fuentes-Hernandez; Jen-Chieh Liu; Amir Dindar; Sangmoo Choi; Jeffrey P. Youngblood; Robert J. Moon; Bernard Kippelen

2015-01-01

We report on the performance and the characterization of top-gate organic field-effect transistors (OFETs), comprising a bilayer gate dielectric of CYTOP/ Al2O3 and a solution-processed semiconductor layer made of a blend of TIPS-pentacene:PTAA, fabricated on recyclable cellulose nanocrystal−glycerol (CNC/glycerol...

Controlling charge current through a DNA based molecular transistor

Energy Technology Data Exchange (ETDEWEB)

Behnia, S., E-mail: s.behnia@sci.uut.ac.ir; Fathizadeh, S.; Ziaei, J.

2017-01-05

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I–V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive. - Highlights: • Modeling a DNA based molecular transistor and studying its transport properties. • Choosing the appropriate DNA sequence using the quantum chaos tools. • Choosing the functional interval for voltages via the inverse participation ratio tool. • Detecting the rectifier and negative differential resistance behavior of DNA.

Voltage and Thermally Driven Roll-to-Roll Organic Printed Transistor Made in Ambient Air Conditions

DEFF Research Database (Denmark)

Pastorelli, Francesco

of the organic semiconductor poly3hexylthiophene and the dielectric material polyvinylphenol before the gate was applied by screen printing. All the processing was realized in ambient air on a PET flexible substrate. We explore the footprint and the practically accessible geometry of such devices with a special......Resume: Organic thin film transistors offer great potential for use in flexible electronics. Much of this potential lies in the solution processability of the organic polymers enabling both roll coating and printing on flexible substrates and thus greatly reducing the material and fabrication costs....... We present flexible organic power transistors prepared by fast (20 m min−1) roll-to-roll flexographic printing of the drain and source electrode structures, with an interspace below 50 um, directly on polyester foil[1]. The devices have top gate architecture and were completed by slotdie coating...

ZnO-channel thin-film transistors: Channel mobility

International Nuclear Information System (INIS)

Hoffman, R.L.

2004-01-01

ZnO-channel thin-film transistor (TFT) test structures are fabricated using a bottom-gate structure on thermally oxidized Si; ZnO is deposited via RF sputtering from an oxide target, with an unheated substrate. Electrical characteristics are evaluated, with particular attention given to the extraction and interpretation of transistor channel mobility. ZnO-channel TFT mobility exhibits severe deviation from that assumed by ideal TFT models; mobility extraction methodology must accordingly be recast so as to provide useful insight into device operation. Two mobility metrics, μ avg and μ inc , are developed and proposed as relevant tools in the characterization of nonideal TFTs. These mobility metrics are employed to characterize the ZnO-channel TFTs reported herein; values for μ inc as high as 25 cm2/V s are measured, comprising a substantial increase in ZnO-channel TFT mobility as compared to previously reported performance for such devices

Study of materials and technology of ancient floor mosaics' substrate

Directory of Open Access Journals (Sweden)

Vincenzo Starinieri

2008-01-01

Full Text Available A floor mosaic's substrate is composed of a variety of preparatory layers of mortar built on natural levelled ground or on top of a previous pavement. Mosaics' substrates differ one from the other in number, thickness and nature of the mortar layers. In this sense, it has been considered relevant to state how these differences are related with historical period, geographical position, function of the pavements within the building, technology of the substrates. A number of floor mosaics' substrates of Hellenistic and Roman period from archaeological sites in Greece and Italy are under study. The stratigraphy of substrates is recorded in situ, and samples from each mortar layer are analysed in the laboratory by means of different techniques. Results obtained so far indicate that characteristics of the Roman substrates mortar layers are clearly dependant on their position in the substrate stratigraphy, whereas in the case of the Hellenistic substrates, characteristics of the mortar layers are less varying with the stratigraphic position. Furthermore results show that floor mosaics' substrates are different according to the function of the pavement in the building.

Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

International Nuclear Information System (INIS)

Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang; Zhao, Juan; Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S.

2015-01-01

Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10 4 and a field-effect mobility of 5 cm 2 V −1 s −1 under elongation and demonstrate invariant performance over 1000 stretching cycles

Parametrization of the radiation induced leakage current increase of NMOS transistors

CERN Document Server

Backhaus, Malte

2017-01-13

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to si...

BUSFET - A Novel Radiation-Hardened SOI Transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

Review of flexible and transparent thin-film transistors based on zinc oxide and related materials

International Nuclear Information System (INIS)

Zhang Yong-Hui; Mei Zeng-Xia; Liang Hui-Li; Du Xiao-Long

2017-01-01

Flexible and transparent electronics enters into a new era of electronic technologies. Ubiquitous applications involve wearable electronics, biosensors, flexible transparent displays, radio-frequency identifications (RFIDs), etc. Zinc oxide (ZnO) and relevant materials are the most commonly used inorganic semiconductors in flexible and transparent devices, owing to their high electrical performances, together with low processing temperatures and good optical transparencies. In this paper, we review recent advances in flexible and transparent thin-film transistors (TFTs) based on ZnO and relevant materials. After a brief introduction, the main progress of the preparation of each component (substrate, electrodes, channel and dielectrics) is summarized and discussed. Then, the effect of mechanical bending on electrical performance is highlighted. Finally, we suggest the challenges and opportunities in future investigations. (paper)

Application of accelerated simulation method on NPN bipolar transistors of different technology

International Nuclear Information System (INIS)

Fei Wuxiong; Zheng Yuzhan; Wang Yiyuan; Chen Rui; Li Maoshun; Lan Bo; Cui Jiangwei; Zhao Yun; Lu Wu; Ren Diyuan; Wang Zhikuan; Yang Yonghui

2010-01-01

With different radiation methods, ionizing radiation response of NPN bipolar transistors of six different processes was investigated. The results show that the enhanced low dose rate sensitivity obviously exists in NPN bipolar transistors of the six kinds of processes. According to the experiment, the damage of decreasing temperature in step during irradiation is obviously greater than the result of irradiated at high dose rate. This irradiation method can perfectly simulate and conservatively evaluate low dose rate damage, which is of great significance to radiation effects research of bipolar devices. Finally, the mechanisms of the experimental phenomena were analyzed. (authors)

Investigations on Substrate Temperature-Induced Growth Modes of Organic Semiconductors at Dielectric/semiconductor Interface and Their Correlation with Threshold Voltage Stability in Organic Field-Effect Transistors.

Science.gov (United States)

Padma, Narayanan; Maheshwari, Priya; Bhattacharya, Debarati; Tokas, Raj B; Sen, Shashwati; Honda, Yoshihide; Basu, Saibal; Pujari, Pradeep Kumar; Rao, T V Chandrasekhar

2016-02-10

Influence of substrate temperature on growth modes of copper phthalocyanine (CuPc) thin films at the dielectric/semiconductor interface in organic field effect transistors (OFETs) is investigated. Atomic force microscopy (AFM) imaging at the interface reveals a change from 'layer+island' to "island" growth mode with increasing substrate temperatures, further confirmed by probing the buried interfaces using X-ray reflectivity (XRR) and positron annihilation spectroscopic (PAS) techniques. PAS depth profiling provides insight into the details of molecular ordering while positron lifetime measurements reveal the difference in packing modes of CuPc molecules at the interface. XRR measurements show systematic increase in interface width and electron density correlating well with the change from layer + island to coalesced huge 3D islands at higher substrate temperatures. Study demonstrates the usefulness of XRR and PAS techniques to study growth modes at buried interfaces and reveals the influence of growth modes of semiconductor at the interface on hole and electron trap concentrations individually, thereby affecting hysteresis and threshold voltage stability. Minimum hole trapping is correlated to near layer by layer formation close to the interface at 100 °C and maximum to the island formation with large voids between the grains at 225 °C.

Recent advances in understanding total-dose effects in bipolar transistors

International Nuclear Information System (INIS)

Schrimpf, R.D.

1996-01-01

Gain degradation in irradiated bipolar transistors can be a significant problem, particularly in linear integrated circuits. In many bipolar technologies, the degradation is greater for irradiation at low dose rates than it is for typical laboratory dose rates. Ionizing radiation causes the base current in bipolar transistors to increase, due to the presence of net positive charge in the oxides covering sensitive device areas and increases in surface recombination velocity. Understanding the mechanisms responsible for radiation-induced gain degradation in bipolar transistors is important in developing appropriate hardness assurance methods. This paper reviews recent modeling and experimental work, with the emphasis on low-dose-rate effects. A promising hardness assurance method based on irradiation at elevated temperatures is described

Parametrization of the radiation induced leakage current increase of NMOS transistors

International Nuclear Information System (INIS)

Backhaus, M.

2017-01-01

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current results as a function of the exposure time to ionizing radiation. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; LI, LIANG; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I.; Alshareef, Husam N.; Zhang, Yafei; Zhang, Xixiang

2014-01-01

Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. This journal is © the Partner Organisations 2014.

O3 Layers via Spray Pyrolysis at Low Temperatures and Their Application in High Electron Mobility Transistors

KAUST Repository

Isakov, Ivan

2017-04-06

The growth mechanism of indium oxide (InO) layers processed via spray pyrolysis of an aqueous precursor solution in the temperature range of 100-300 °C and the impact on their electron transporting properties are studied. Analysis of the droplet impingement sites on the substrate\\'s surface as a function of its temperature reveals that Leidenfrost effect dominated boiling plays a crucial role in the growth of smooth, continuous, and highly crystalline InO layers via a vapor phase-like process. By careful optimization of the precursor formulation, deposition conditions, and choice of substrate, this effect is exploited and ultrathin and exceptionally smooth layers of InO are grown over large area substrates at temperatures as low as 252 °C. Thin-film transistors (TFTs) fabricated using these optimized InO layers exhibit superior electron transport characteristics with the electron mobility reaching up to 40 cm V s, a value amongst the highest reported to date for solution-processed InO TFTs. The present work contributes enormously to the basic understanding of spray pyrolysis and highlights its tremendous potential for large-volume manufacturing of high-performance metal oxide thin-film transistor electronics.

Binary codes storage and data encryption in substrates with single proton beam writing technology

International Nuclear Information System (INIS)

Zhang Jun; Zhan Furu; Hu Zhiwen; Chen Lianyun; Yu Zengliang

2006-01-01

It has been demonstrated that characters can be written by proton beams in various materials. In contributing to the rapid development of proton beam writing technology, we introduce a new method for binary code storage and data encryption by writing binary codes of characters (BCC) in substrates with single proton beam writing technology. In this study, two kinds of BCC (ASCII BCC and long bit encrypted BCC) were written in CR-39 by a 2.6 MeV single proton beam. Our results show that in comparison to directly writing character shapes, writing ASCII BCC turned out to be about six times faster and required about one fourth the area in substrates. The approach of writing long bit encrypted BCC by single proton beams supports preserving confidential information in substrates. Additionally, binary codes fabricated by MeV single proton beams in substrates are more robust than those formed by lasers, since MeV single proton beams can make much deeper pits in the substrates

Efficient Substrate Noise Coupling Verification and Failure Analysis Methodology for Smart Power ICs in Automotive Applications

OpenAIRE

Moursy , Yasser; Zou , Hao; Khalil , Raouf; Iskander , Ramy; Tisserand , Pierre; Ton , Dieu-My; Pasetti , Giuseppe; Louërat , Marie-Minerve

2016-01-01

International audience; This paper presents a methodology to analyze the substrate noise coupling and reduce their effects in smart power integrated circuits. This methodology considers the propagation of minority carriers in the substrate. Hence, it models the lateral bipolar junction transistors that are layout dependent and are not modeled in conventional substrate extraction tools. It allows the designer to simulate substrate currents and check their effects on circuits functionality. The...

Effects of irradiation on device characteristics of transistor structures based on AlGaN/GaN

International Nuclear Information System (INIS)

Kargin, N.I.; Gromov, D.V.; Kuznetsov, A.L.; Grekhov, M.M.

2014-01-01

A technologic scheme was developed, and transistor structures, based on hetero-structures AlGaN/GaN, were made. Current-voltage characteristics of the transistor structures and current-amplification and power-amplification cutoff frequencies have been presented in the paper [ru

High performance tunnel field-effect transistor by gate and source engineering.

Science.gov (United States)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

Energy Technology Data Exchange (ETDEWEB)

Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang [Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Zhao, Juan [School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China); Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S., E-mail: michael.arnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States)

2015-08-03

Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10{sup 4} and a field-effect mobility of 5 cm{sup 2} V{sup −1} s{sup −1} under elongation and demonstrate invariant performance over 1000 stretching cycles.

Group IV nanotube transistors for next generation ubiquitous computing

KAUST Repository

Fahad, Hossain M.; Hussain, Aftab M.; Sevilla, Galo T.; Banerjee, Sanjay K.; Hussain, Muhammad Mustafa

2014-01-01

Evolution in transistor technology from increasingly large power consuming single gate planar devices to energy efficient multiple gate non-planar ultra-narrow (< 20 nm) fins has enhanced the scaling trend to facilitate doubling performance. However

Characterization of 6,13-bis(triisopropylsilylethynyl) pentacene organic thin film transistors fabricated using pattern-induced confined structure

International Nuclear Information System (INIS)

Kim, Kyohyeok; Kwon, Namyong; Chung, Ilsub

2014-01-01

Bottom gate organic thin film transistors (OTFTs) were fabricated on polyethersulphone substrate using an ink jet printing method. 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene and poly-4-vinylphenol (PVP) were used as an active material and as a gate insulator, respectively. In an attempt to reduce the coffee stain effect, TIPS pentacene active layer was printed onto the pattern-induced confined structure (PICS) which had been obtained by orthogonally printing Ag electrodes on the pre-printed PVP layer. The resolution of Ag patterns was obtained by modifying the surface energy using UV irradiation and substrate temperature. The channel lengths of the aforementioned PICS OTFTs were in the range of 10 μm to 50 μm. The average mobility and on/off ratio of PICS OTFTs were 0.034 cm 2 /Vs and 10 3 , respectively. - Highlights: • Ink-jet printed bottom gate organic thin film transistor on plastic substrate • Ag lines orthogonally printed on pre-printed poly-4-vinylphenol lines • Pattern-induced confined structures obtained • UV irradiation affects the surface energy and the resolution of the Ag patterns

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing

Science.gov (United States)

Chang, Yi-Kuei; Hong, Franklin Chau-Nan

2009-05-01

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min-1), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 105, a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm2 V-1 s-1. The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing

International Nuclear Information System (INIS)

Chang, Y-K; Hong, Franklin Chau-Nan

2009-01-01

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min -1 ), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 10 5 , a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm 2 V -1 s -1 . The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

The fabrication of ZnO nanowire field-effect transistors by roll-transfer printing

Energy Technology Data Exchange (ETDEWEB)

Chang, Y-K; Hong, Franklin Chau-Nan [Department of Chemical Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China)], E-mail: hong@mail.ncku.edu.tw

2009-05-13

A method with the potential to fabricate large-area nanowire field-effect transistors (NW-FETs) was demonstrated in this study. Using a high-speed roller (20-80 cm min{sup -1}), transfer printing was successfully employed to transfer vertically aligned zinc oxide (ZnO) nanowires grown on a donor substrate to a polydimethylsiloxane (PDMS) stamp and then print the ordered ZnO nanowire arrays on the received substrate for the fabrication of NW-FETs. ZnO NW-FETs fabricated by this method exhibit high performances with a threshold voltage of around 0.25 V, a current on/off ratio as high as 10{sup 5}, a subthreshold slope of 360 mV/dec, and a field-effect mobility of around 90 cm{sup 2} V{sup -1} s{sup -1}. The excellent device characteristics suggest that the roll-transfer printing technique, which is compatible with the roll-to-roll (R2R) process and operated in atmosphere, has a good potential for the high-speed fabrication of large-area nanowire transistors for flexible devices and flat panel displays.

Mapping brain activity with flexible graphene micro-transistors

Science.gov (United States)

Blaschke, Benno M.; Tort-Colet, Núria; Guimerà-Brunet, Anton; Weinert, Julia; Rousseau, Lionel; Heimann, Axel; Drieschner, Simon; Kempski, Oliver; Villa, Rosa; Sanchez-Vives, Maria V.; Garrido, Jose A.

2017-06-01

Establishing a reliable communication interface between the brain and electronic devices is of paramount importance for exploiting the full potential of neural prostheses. Current microelectrode technologies for recording electrical activity, however, evidence important shortcomings, e.g. challenging high density integration. Solution-gated field-effect transistors (SGFETs), on the other hand, could overcome these shortcomings if a suitable transistor material were available. Graphene is particularly attractive due to its biocompatibility, chemical stability, flexibility, low intrinsic electronic noise and high charge carrier mobilities. Here, we report on the use of an array of flexible graphene SGFETs for recording spontaneous slow waves, as well as visually evoked and also pre-epileptic activity in vivo in rats. The flexible array of graphene SGFETs allows mapping brain electrical activity with excellent signal-to-noise ratio (SNR), suggesting that this technology could lay the foundation for a future generation of in vivo recording implants.

Generation of uniaxial tensile strain of over 1% on a Ge substrate for short-channel strained Ge n-type Metal–Insulator–Semiconductor Field-Effect Transistors with SiGe stressors

International Nuclear Information System (INIS)

Moriyama, Yoshihiko; Kamimuta, Yuuichi; Ikeda, Keiji; Tezuka, Tsutomu

2012-01-01

Tensile strain of over 1% in Ge stripes sandwiched between a pair of SiGe source-drain stressors was demonstrated. The Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET)-like structures were fabricated on a (001)-Ge substrate having SiO 2 dummy-gate stripes with widths down to 26 nm. Recess-regions adjacent to the dummy-gate stripes were formed by an anisotropic wet etching technique. A damage-free and well-controlled anisotropic wet etching process is developed in order to avoid plasma-induced damage during a conventional Reactive-ion Etching process. The SiGe stressors were epitaxially grown on the recesses to simulate strained Ge n-channel Metal–Insulator–Semiconductor Field-Effect Transistors (MISFETs) having high electron mobility. A micro-Raman spectroscopy measurement revealed tensile strain in the narrow Ge regions which became higher for narrower regions. Tensile strain of up to 1.2% was evaluated from the measurement under an assumption of uniaxial strain configuration. These results strongly suggest that higher electron mobility than the upper limit for a Si-MOSFET is obtainable in short-channel strained Ge-nMISFETs with the embedded SiGe stressors.

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Copper atomic-scale transistors.

Science.gov (United States)

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Highly Conductive Graphene/Ag Hybrid Fibers for Flexible Fiber-Type Transistors.

Science.gov (United States)

Yoon, Sang Su; Lee, Kang Eun; Cha, Hwa-Jin; Seong, Dong Gi; Um, Moon-Kwang; Byun, Joon-Hyung; Oh, Youngseok; Oh, Joon Hak; Lee, Wonoh; Lee, Jea Uk

2015-11-09

Mechanically robust, flexible, and electrically conductive textiles are highly suitable for use in wearable electronic applications. In this study, highly conductive and flexible graphene/Ag hybrid fibers were prepared and used as electrodes for planar and fiber-type transistors. The graphene/Ag hybrid fibers were fabricated by the wet-spinning/drawing of giant graphene oxide and subsequent functionalization with Ag nanoparticles. The graphene/Ag hybrid fibers exhibited record-high electrical conductivity of up to 15,800 S cm(-1). As the graphene/Ag hybrid fibers can be easily cut and placed onto flexible substrates by simply gluing or stitching, ion gel-gated planar transistors were fabricated by using the hybrid fibers as source, drain, and gate electrodes. Finally, fiber-type transistors were constructed by embedding the graphene/Ag hybrid fiber electrodes onto conventional polyurethane monofilaments, which exhibited excellent flexibility (highly bendable and rollable properties), high electrical performance (μh = 15.6 cm(2) V(-1) s(-1), Ion/Ioff > 10(4)), and outstanding device performance stability (stable after 1,000 cycles of bending tests and being exposed for 30 days to ambient conditions). We believe that our simple methods for the fabrication of graphene/Ag hybrid fiber electrodes for use in fiber-type transistors can potentially be applied to the development all-organic wearable devices.

Study on ionizing radiation effects of bipolar transistor with BPSG films

International Nuclear Information System (INIS)

Lu Man; Zhang Xiaoling; Xie Xuesong; Sun Jiangchao; Wang Pengpeng; Lu Changzhi; Zhang Yanxiu

2013-01-01

Background: Because of the damage induced by ionizing radiation, bipolar transistors in integrated voltage regulator could induce the current gain degradation and increase leakage current. This will bring serious problems to electronic system. Purpose: In order to ensure the reliability of the device work in the radiation environments, the device irradiation reinforcement technology is used. Methods: The characteristics of 60 Co γ irradiation and annealing at different temperatures in bipolar transistors and voltage regulators (JW117) with different passive films for SiO 2 +BPSG+SiO 2 and SiO 2 +SiN have been investigated. Results: The devices with BPSG film enhanced radiation tolerance significantly. Because BPSG films have better absorption for Na + in SiO 2 layer, the surface recombination rate of base region in a bipolar transistor and the excess base current have been reduced. It may be the main reason for BJT with BPSG film having a good radiation hardness. And annealing experiments at different temperatures after irradiation ensure the reliability of the devices with BPSG films. Conclusions: A method of improving the ionizing irradiation hardness of bipolar transistors is proposed. As well as the linear integrated circuits which containing bipolar transistors, an experimental basis for the anti-ionizing radiation effects of bipolar transistors is provided. (authors)

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

Science.gov (United States)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Flexible, transparent single-walled carbon nanotube transistors with graphene electrodes

International Nuclear Information System (INIS)

Jang, Sukjae; Jang, Houk; Lee, Youngbin; Suh, Daewoo; Baik, Seunghyun; Hong, Byung Hee; Ahn, Jong-Hyun

2010-01-01

This paper reports a mechanically flexible, transparent thin film transistor that uses graphene as a conducting electrode and single-walled carbon nanotubes (SWNTs) as a semiconducting channel. These SWNTs and graphene films were printed on flexible plastic substrates using a printing method. The resulting devices exhibited a mobility of ∼ 2 cm 2 V -1 s -1 , On/Off ratio of ∼ 10 2 , transmittance of ∼ 81% and excellent mechanical bendability.

Three-Dimensional Printed Poly(vinyl alcohol) Substrate with Controlled On-Demand Degradation for Transient Electronics.

Science.gov (United States)

Yoon, Jinsu; Han, Jungmin; Choi, Bongsik; Lee, Yongwoo; Kim, Yeamin; Park, Jinhee; Lim, Meehyun; Kang, Min-Ho; Kim, Dae Hwan; Kim, Dong Myong; Kim, Sungho; Choi, Sung-Jin

2018-05-25

Electronics that degrade after stable operation for a desired operating time, called transient electronics, are of great interest in many fields, including biomedical implants, secure memory devices, and environmental sensors. Thus, the development of transient materials is critical for the advancement of transient electronics and their applications. However, previous reports have mostly relied on achieving transience in aqueous solutions, where the transience time is largely predetermined based on the materials initially selected at the beginning of the fabrication. Therefore, accurate control of the transience time is difficult, thereby limiting their application. In this work, we demonstrate transient electronics based on a water-soluble poly(vinyl alcohol) (PVA) substrate on which carbon nanotube (CNT)-based field-effect transistors were fabricated. We regulated the structural parameters of the PVA substrate using a three-dimensional (3D) printer to accurately control and program the transience time of the PVA substrate in water. The 3D printing technology can produce complex objects directly, thus enabling the efficient fabrication of a transient substrate with a prescribed and controlled transience time. In addition, the 3D printer was used to develop a facile method for the selective and partial destruction of electronics.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

Science.gov (United States)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high

Electrical performance of multilayer MoS2 transistors on high-κ Al2O3 coated Si substrates

Directory of Open Access Journals (Sweden)

Tao Li

2015-05-01

Full Text Available The electrical performance of MoS2 can be engineered by introducing high-κ dielectrics, while the interactions between high-κ dielectrics and MoS2 need to be studied. In this study, multilayer MoS2 field-effect transistors (FETs with a back-gated configuration were fabricated on high-κ Al2O3 coated Si substrates. Compared with MoS2 FETs on SiO2, the field-effect mobility (μFE and subthreshold swing (SS were remarkably improved in MoS2/Al2O3/Si. The improved μFE was thought to result from the dielectric screening effect from high-κ Al2O3. When a HfO2 passivation layer was introduced on the top of MoS2/Al2O3/Si, the field-effect mobility was further enhanced, which was thought to be concerned with the decreased contact resistance between the metal and MoS2. Meanwhile, the interface trap density increased from 2.4×1012 eV−1cm−2 to 6.3×1012 eV−1cm−2. The increase of the off-state current and the negative shift of the threshold voltage may be related to the increase of interface traps.

Low-voltage bendable pentacene thin-film transistor with stainless steel substrate and polystyrene-coated hafnium silicate dielectric.

Science.gov (United States)

Yun, Dong-Jin; Lee, Seunghyup; Yong, Kijung; Rhee, Shi-Woo

2012-04-01

The hafnium silicate and aluminum oxide high-k dielectrics were deposited on stainless steel substrate using atomic layer deposition process and octadecyltrichlorosilane (OTS) and polystyrene (PS) were treated improve crystallinity of pentacene grown on them. Besides, the effects of the pentacene deposition condition on the morphologies, crystallinities and electrical properties of pentacene were characterized. Therefore, the surface treatment condition on dielectric and pentacene deposition conditions were optimized. The pentacene grown on polystyrene coated high-k dielectric at low deposition rate and temperature (0.2-0.3 Å/s and R.T.) showed the largest grain size (0.8-1.0 μm) and highest crystallinity among pentacenes deposited various deposition conditions, and the pentacene TFT with polystyrene coated high-k dielectric showed excellent device-performance. To decrease threshold voltage of pentacene TFT, the polystyrene-thickness on high-k dielectric was controlled using different concentration of polystyrene solution. As the polystyrene-thickness on hafnium silicate decreases, the dielectric constant of polystyrene/hafnium silicate increases, while the crystallinity of pentacene grown on polystyrene/hafnium silicate did not change. Using low-thickness polystyrene coated hafnium silicate dielectric, the high-performance and low voltage operating (pentacene thin film transistor (μ: ~2 cm(2)/(V s), on/off ratio, >1 × 10(4)) and complementary inverter (DC gains, ~20) could be fabricated.

Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances

International Nuclear Information System (INIS)

Suat, J.P.; Borel, J.

1976-01-01

The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr

Evolution of the MOS transistor - From conception to VLSI

International Nuclear Information System (INIS)

Sah, C.T.

1988-01-01

Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

Synthesis and Field-effect Transistor Behavior of New Oligo-selenophene Derivatives

Institute of Scientific and Technical Information of China (English)

Jiwon; Hong; In-Hwan; Jung; Hong-ku; Shim

2007-01-01

1 Results In recent years,interests in organic semiconductor have increased due to the applications in optoelectronic devices such as organic light-emitting diodes (OLEDs)[1],field-effect transistors (FETs)[2],and photovoltaic devices[3]. These organic electronics have several advantages over conventional inorganic electronics including facile processability,chemical tunability,compatibility with plastic substrates,and low cost to fabricate. Selenophene-based molecules show good π-conjugating electron o...

High-performance zno transistors processed via an aqueous carbon-free metal oxide precursor route at temperatures between 80-180 °c

KAUST Repository

Lin, Yenhung

2013-06-25

An aqueous and carbon-free metal-oxide precursor route is used in combination with a UV irradiation-assisted low-temperature conversion method to fabricate low-voltage ZnO transistors with electron mobilities exceeding 10 cm2/Vs at temperatures <180°C. Because of its low temperature requirements the method allows processing of high-performance transistors onto temperature sensitive substrates such as plastic. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Superconducting transistor

International Nuclear Information System (INIS)

Gray, K.E.

1978-01-01

A three film superconducting tunneling device, analogous to a semiconductor transistor, is presented, including a theoretical description and experimental results showing a current gain of four. Much larger current gains are shown to be feasible. Such a development is particularly interesting because of its novelty and the striking analogies with the semiconductor junction transistor

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

A Mixed Analog-Digital Radiation Hard Technology for High Energy Physics Electronics: DMILL~(Durci~Mixte~sur~Isolant~Logico-Lineaire)

CERN Multimedia

Lugiez, F; Leray, J; Rouger, M; Fourches, N T; Musseau, O; Potheau, R

2002-01-01

%RD29 %title\\\\ \\\\Physics experiments under preparation with the future LHC require a fast, low noise, very rad-hard (>10 Mrad and >10$^{14}$ neutron/cm$^{2}$), mixed analog-digital microelectronics VLSI technology.\\\\ \\\\The DMILL microelectronics technology (RD29) was developed between 1990 and 1995 by a Consortium gathering the CEA and the firm Thomson-TCS, with the collaboration of IN2P3. The goal of the DMILL program, which is now completed, was to provide the High Energy Physics community, space industry, nuclear industry, and other applications, with an industrial very rad-hard mixed analog-digital microelectronics technology.\\\\ \\\\DMILL integrates mixed analog-digital very rad-hard (>10 Mrad and >10$^{14}$ neutron/cm$^{2}$) vertical bipolar, 0.8 $\\mu$m CMOS and 1.2 $\\mu$m PJFET transistors. Its SOI substrate and its dielectric trenches strongly reduce SEU sensitivity and completely eliminate any possibility of latch-up. Its four transistors are optimized to obtain low-noise features. DMILL also integrates...

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

Science.gov (United States)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

Science.gov (United States)

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Accelerating the life of transistors

International Nuclear Information System (INIS)

Qi Haochun; Lü Changzhi; Zhang Xiaoling; Xie Xuesong

2013-01-01

Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object, the test of accelerating life is conducted in constant temperature and humidity, and then the data are statistically analyzed with software developed by ourselves. According to degradations of such sensitive parameters as the reverse leakage current of transistors, the lifetime order of transistors is about more than 10 4 at 100 °C and 100% relative humidity (RH) conditions. By corrosion fracture of transistor outer leads and other failure modes, with the failure truncated testing, the average lifetime rank of transistors in different distributions is extrapolated about 10 3 . Failure mechanism analyses of degradation of electrical parameters, outer lead fracture and other reasons that affect transistor lifetime are conducted. The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation. (semiconductor devices)

Flexible, transparent single-walled carbon nanotube transistors with graphene electrodes

Energy Technology Data Exchange (ETDEWEB)

Jang, Sukjae; Jang, Houk; Lee, Youngbin; Suh, Daewoo; Baik, Seunghyun; Hong, Byung Hee; Ahn, Jong-Hyun, E-mail: ahnj@skku.edu, E-mail: byunghee@skku.edu [SKKU Advanced Institute of Nanotechnology (SAINT) and Center for Human Interface Nano Technology (HINT), Sungkyunkwan University, Suwon 440-746 (Korea, Republic of)

2010-10-22

This paper reports a mechanically flexible, transparent thin film transistor that uses graphene as a conducting electrode and single-walled carbon nanotubes (SWNTs) as a semiconducting channel. These SWNTs and graphene films were printed on flexible plastic substrates using a printing method. The resulting devices exhibited a mobility of {approx} 2 cm{sup 2} V{sup -1} s{sup -1}, On/Off ratio of {approx} 10{sup 2}, transmittance of {approx} 81% and excellent mechanical bendability.

Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with - and channel orientations

International Nuclear Information System (INIS)

Habicht, Stefan; Feste, Sebastian; Zhao, Qing-Tai; Buca, Dan; Mantl, Siegfried

2012-01-01

Nanowire-array metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated along and crystal directions on (001) un-/strained silicon-on-insulator substrates. Lateral strain relaxation through patterning was employed to transform biaxial tensile strain into uniaxial tensile strain along the nanowire. Devices feature ideal subthreshold swings and maximum on-current/off-current ratios of 10 11 for n and p-type transistors on both substrates. Electron and hole mobilities were extracted by split C–V method. For p-MOSFETs an increased mobility is observed for channel direction devices compared to devices. The n-MOSFETs showed a 45% increased electron mobility compared to devices. The comparison of strained and unstrained n-MOSFETs along and clearly demonstrates improved electron mobilities for strained channels of both channel orientations.

Gallium nitride based transistors for high-efficiency microwave switch-mode amplifiers

Energy Technology Data Exchange (ETDEWEB)

Maroldt, Stephan

2012-07-01

Highly-efficient switch-mode power amplifiers form key elements in future fully-digital base stations for mobile communication. This novel digital base station concept reduces system energy consumption, complexity, size and costs, while the flexibility in terms of multi-band operation and signal modulation improves. In this work, innovative core circuits for digital high-efficiency class-D and class-S power amplifiers based on gallium nitride (GaN) technology were developed for the application in digital base stations. A combination of optimized GaN devices and improvements in circuit design allow a highly-efficient switch-mode operation at mobile communication frequencies between 0.45 GHz and 2 GHz. Transistor device modeling for switch-mode operation, the simulation environment, and a broadband measurement system were established for the design and evaluation of digital switchmode power amplifiers. The design of broadband core circuits for switch-mode amplifier concepts was analyzed for dual-stage amplifier circuits, using an initial GaN technology with a gate length of 0.25 {mu}m. A speed-enhanced driver stage improved the circuit switching speed sufficiently above 1 GHz. Speed and efficiency of the amplifier core circuits were studied related to transistor parameters like cut-off frequency or gate capacitance. A reduced gate length was found to improve the switching speed, while a lower on-resistance allows the reduction of the inherent static losses of the GaN-based switches. Apart from this, the restriction of a 50 Ohm environment was found to be a major output power and switching speed limitation, due to a poor switching drive capability of the input capacitance of the GaN circuit. Finally, the optimized transistor and circuit design with an output gate width of 1.2 mm were effectively implemented in the given environment for an operation up to 2 GHz with a high drain efficiency of >65% and a digital output power of 5 W. A maximum output power of 9.7 W and a

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

International Nuclear Information System (INIS)

Cortés, I; Toulon, G; Morancho, F; Hugonnard-Bruyere, E; Villard, B; Toren, W J

2011-01-01

This paper focuses on the design and optimization of different power P-channel LDMOS transistors (V BR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (R on-sp /V BR trade-off) and dynamic (R on × Q g ) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor R on-sp /V BR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance

Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

Science.gov (United States)

Moon, Kyeong-Ju; Lee, Tae-Il; Lee, Sang-Hoon; Han, Young-Uk; Ham, Moon-Ho; Myoung, Jae-Min

2012-07-25

A design platform for a zero drive load logic inverter consisting of p-channel Si nanowire based transistors, which controlled their operating mode through an implantation into a gate dielectric layer was demonstrated. As a result, a nanowire based class D inverter having a 4.6 gain value at V(DD) of -20 V was successfully fabricated on a substrate.

Graphene-on-diamond devices with increased current-carrying capacity: carbon sp2-on-sp3 technology.

Science.gov (United States)

Yu, Jie; Liu, Guanxiong; Sumant, Anirudha V; Goyal, Vivek; Balandin, Alexander A

2012-03-14

Graphene demonstrated potential for practical applications owing to its excellent electronic and thermal properties. Typical graphene field-effect transistors and interconnects built on conventional SiO(2)/Si substrates reveal the breakdown current density on the order of 1 μA/nm(2) (i.e., 10(8) A/cm(2)), which is ~100× larger than the fundamental limit for the metals but still smaller than the maximum achieved in carbon nanotubes. We show that by replacing SiO(2) with synthetic diamond, one can substantially increase the current-carrying capacity of graphene to as high as ~18 μA/nm(2) even at ambient conditions. Our results indicate that graphene's current-induced breakdown is thermally activated. We also found that the current carrying capacity of graphene can be improved not only on the single-crystal diamond substrates but also on an inexpensive ultrananocrystalline diamond, which can be produced in a process compatible with a conventional Si technology. The latter was attributed to the decreased thermal resistance of the ultrananocrystalline diamond layer at elevated temperatures. The obtained results are important for graphene's applications in high-frequency transistors, interconnects, and transparent electrodes and can lead to the new planar sp(2)-on-sp(3) carbon-on-carbon technology. © 2012 American Chemical Society

Ultrasensitive label-free detection of DNA hybridization by sapphire-based graphene field-effect transistor biosensor

Science.gov (United States)

Xu, Shicai; Jiang, Shouzhen; Zhang, Chao; Yue, Weiwei; Zou, Yan; Wang, Guiying; Liu, Huilan; Zhang, Xiumei; Li, Mingzhen; Zhu, Zhanshou; Wang, Jihua

2018-01-01

Graphene has attracted much attention in biosensing applications for its unique properties. Because of one-atom layer structure, every atom of graphene is exposed to the environment, making the electronic properties of graphene are very sensitive to charged analytes. Therefore, graphene is an ideal material for transistors in high-performance sensors. Chemical vapor deposition (CVD) method has been demonstrated the most successful method for fabricating large area graphene. However, the conventional CVD methods can only grow graphene on metallic substrate and the graphene has to be transferred to the insulating substrate for further device fabrication. The transfer process creates wrinkles, cracks, or tears on the graphene, which severely degrade electrical properties of graphene. These factors severely degrade the sensing performance of graphene. Here, we directly fabricated graphene on sapphire substrate by high temperature CVD without the use of metal catalysts. The sapphire-based graphene was patterned and make into a DNA biosensor in the configuration of field-effect transistor. The sensors show high performance and achieve the DNA detection sensitivity as low as 100 fM (10-13 M), which is at least 10 times lower than prior transferred CVD G-FET DNA sensors. The use of the sapphire-based G-FETs suggests a promising future for biosensing applications.

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

Science.gov (United States)

Zhang, Zhili; Song, Liang; Li, Weiyi; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Fan, Yaming; Deng, Xuguang; Li, Shuiming; Sun, Shichuang; Li, Xiajun; Yuan, Jie; Sun, Qian; Dong, Zhihua; Cai, Yong; Zhang, Baoshun

2017-08-01

In this paper, we systematically investigated the leakage mechanism of the ion-implantation isolated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si substrate. By means of combined DC tests at different temperatures and electric field dependence, we demonstrated the following original results: (1) It is proved that gate leakage is the main contribution to OFF-state leakage of ion-implantation isolated AlGaN/GaN MIS-HEMTs, and the gate leakage path is a series connection of the gate dielectric Si3N4 and Si3N4-GaN interface. (2) The dominant mechanisms of the leakage current through LPCVD-Si3N4 gate dielectric and Si3N4-GaN interface are identified to be Frenkel-Poole emission and two-dimensional variable range hopping (2D-VRH), respectively. (3) A certain temperature annealing could reduce the density of the interface state that produced by ion implantation, and consequently suppress the interface leakage transport, which results in a decrease in OFF-state leakage current of ion-implantation isolated AlGaN/GaN MIS-HEMTs.

Organic thin film transistors using a liquid crystalline palladium phthalocyanine as active layer

Science.gov (United States)

Jiménez Tejada, Juan A.; Lopez-Varo, Pilar; Chaure, Nandu B.; Chambrier, Isabelle; Cammidge, Andrew N.; Cook, Michael J.; Jafari-Fini, Ali; Ray, Asim K.

2018-03-01

70 nm thick solution-processed films of a palladium phthalocyanine (PdPc6) derivative bearing eight hexyl (-C6H13) chains at non-peripheral positions have been employed as active layers in the fabrication of bottom-gate bottom-contact organic thin film transistors (OTFTs) deposited on highly doped p-type Si (110) substrates with SiO2 gate dielectric. The dependence of the transistor electrical performance upon the mesophase behavior of the PdPc6 films has been investigated by measuring the output and transfer characteristics of the OTFT having its active layer ex situ vacuum annealed at temperatures between 500 °C and 200 °C. A clear correlation between the annealing temperature and the threshold voltage and carrier mobility of the transistors, and the transition temperatures extracted from the differential scanning calorimetric curves for bulk materials has been established. This direct relation has been obtained by means of a compact electrical model in which the contact effects are taken into account. The precise determination of the contact-voltage drain-current curves allows for obtaining such a relation.

High-performance vertical organic transistors.

Science.gov (United States)

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effect of substrate and temperature on the electronic properties of monolayer molybdenum disulfide field-effect transistors

Science.gov (United States)

Yang, Qizhi; Fang, Jiajia; Zhang, Guangru; Wang, Quan

2018-03-01

The use of two-dimensional nanostructured molybdenum disulfide (MoS2) films in field-effect transistors (FETs) in place of graphene was investigated. Monolayer MoS2 films were fabricated by chemical vapor deposition. The output and transfer curves of supported and suspended MoS2 FETs were measured. The mobility of the suspended device reached 364.2 cm2 V-1 s-1 at 150 °C. The hysteresis of the supported device in transfer curves was much larger than that of the suspended device, and it increased at higher temperatures. These results indicate that the device mobility was limited by Coulomb scattering at ambient temperature, and surface/interface phonon scattering at 150 °C, and the injection of electrons, via quantum tunneling through the Schottky barrier at the contact, was enhanced at higher temperatures and led to the increase of the hysteresis. The suspended MoS2 films show potential for application as a channel material in electronic devices, and further understanding the causes of hysteresis in a material is important for its use in technologies, such as memory devices and sensing cells.

Characterization of 6,13-bis(triisopropylsilylethynyl) pentacene organic thin film transistors fabricated using pattern-induced confined structure

Energy Technology Data Exchange (ETDEWEB)

Kim, Kyohyeok; Kwon, Namyong [Sungkyunkwan University Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); Chung, Ilsub, E-mail: ichung@skku.ac.kr [Sungkyunkwan University Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of); College of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746 (Korea, Republic of)

2014-01-01

Bottom gate organic thin film transistors (OTFTs) were fabricated on polyethersulphone substrate using an ink jet printing method. 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene and poly-4-vinylphenol (PVP) were used as an active material and as a gate insulator, respectively. In an attempt to reduce the coffee stain effect, TIPS pentacene active layer was printed onto the pattern-induced confined structure (PICS) which had been obtained by orthogonally printing Ag electrodes on the pre-printed PVP layer. The resolution of Ag patterns was obtained by modifying the surface energy using UV irradiation and substrate temperature. The channel lengths of the aforementioned PICS OTFTs were in the range of 10 μm to 50 μm. The average mobility and on/off ratio of PICS OTFTs were 0.034 cm{sup 2}/Vs and 10{sup 3}, respectively. - Highlights: • Ink-jet printed bottom gate organic thin film transistor on plastic substrate • Ag lines orthogonally printed on pre-printed poly-4-vinylphenol lines • Pattern-induced confined structures obtained • UV irradiation affects the surface energy and the resolution of the Ag patterns.

O3 Layers via Spray Pyrolysis at Low Temperatures and Their Application in High Electron Mobility Transistors

KAUST Repository

Isakov, Ivan; Faber, Hendrik; Grell, Max; Wyatt-Moon, Gwenhivir; Pliatsikas, Nikos; Kehagias, Thomas; Dimitrakopulos, George P.; Patsalas, Panos P.; Li, Ruipeng; Anthopoulos, Thomas D.

2017-01-01

The growth mechanism of indium oxide (InO) layers processed via spray pyrolysis of an aqueous precursor solution in the temperature range of 100-300 °C and the impact on their electron transporting properties are studied. Analysis of the droplet impingement sites on the substrate's surface as a function of its temperature reveals that Leidenfrost effect dominated boiling plays a crucial role in the growth of smooth, continuous, and highly crystalline InO layers via a vapor phase-like process. By careful optimization of the precursor formulation, deposition conditions, and choice of substrate, this effect is exploited and ultrathin and exceptionally smooth layers of InO are grown over large area substrates at temperatures as low as 252 °C. Thin-film transistors (TFTs) fabricated using these optimized InO layers exhibit superior electron transport characteristics with the electron mobility reaching up to 40 cm V s, a value amongst the highest reported to date for solution-processed InO TFTs. The present work contributes enormously to the basic understanding of spray pyrolysis and highlights its tremendous potential for large-volume manufacturing of high-performance metal oxide thin-film transistor electronics.

A Single-Transistor Active Pixel CMOS Image Sensor Architecture

International Nuclear Information System (INIS)

Zhang Guo-An; He Jin; Zhang Dong-Wei; Su Yan-Mei; Wang Cheng; Chen Qin; Liang Hai-Lang; Ye Yun

2012-01-01

A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution.

Science.gov (United States)

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A; Anthopoulos, Thomas D

2017-03-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In 2 O 3 /ZnO heterojunction. We find that In 2 O 3 /ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In 2 O 3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In 2 O 3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution

KAUST Repository

Faber, Hendrik

2017-04-28

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In2O3/ZnO heterojunction. We find that In2O3/ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In2O3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In2O3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications.

Gate-modulated conductance of few-layer WSe2 field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

International Nuclear Information System (INIS)

Wang, Junjie; Feng, Simin; Rhodes, Daniel; Balicas, Luis; Nguyen, Minh An T.; Watanabe, K.; Taniguchi, T.; Mallouk, Thomas E.; Terrones, Mauricio; Zhu, J.

2015-01-01

Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe 2 field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10 13 /cm 2 /eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices

Overview of recent developments in organic thin-film transistor sensor technology

International Nuclear Information System (INIS)

Tanese, M.C.; Marinelli, F.; Angione, D.; Torsi, L.

2008-01-01

Bio and chemical sensing represents one of the most attractive applications of organic electronics and of Organic Thin Film Transistors(OTFTs) in particular. The implementation of miniaturized portable systems for the detection of chemical analytes as well as of biological species, is still a challenge for the sensor' community. In this respect OTFTs appear as a new class of sensors able, in principle, to overcome some of the commercial sensors drawbacks. As far as volatile analytes are concerned, commercially available sensing systems, such as metal oxide based chemi-resistors, offer great stability but rather poor selectivity. In spite of the improved selectivity offered by organic chemi-resistors the reliability of such devices is not yet satisfactory proven. On the other hand, complex odors recognition, but also explosives or pathogen bacteria detection are currently being addressed by sensor array systems, called e-noses, that try to mimic the mammalian olfactory system. Even though potentially very effective, this technology has not yet reached the performance level required by the market mostly because miniaturization and cost effective production issues. OTFT sensors can offer the advantage of room temperature operation and deliver high repeatable responses. Beside, they show very good selectivity properties. In fact, they implement organic active layers, which behave as sensing layers as well. This improves OTFTs sensitivity towards different chemical and biological analytes as organic materials can be properly chemically tailored to achieve differential detection and potentially even discrimination of biological species. In addiction to this, OTFTs are also able to offer the unique advantages of multi-parametric response and a gate bias enhanced sensitivity. Recently thin dielectric low-voltage OTFTs have also been demonstrated. Their implementation in low power consumption devices has attracted the attention of the organic electronic community. But such

Logarithmic current-measuring transistor circuits

DEFF Research Database (Denmark)

Højberg, Kristian Søe

1967-01-01

Describes two transistorized circuits for the logarithmic measurement of small currents suitable for nuclear reactor instrumentation. The logarithmic element is applied in the feedback path of an amplifier, and only one dual transistor is used as logarithmic diode and temperature compensating...... transistor. A simple one-amplifier circuit is compared with a two-amplifier system. The circuits presented have been developed in connexion with an amplifier using a dual m.o.s. transistor input stage with diode-protected gates....

Charge based DC compact modeling of bulk FinFET transistor

Science.gov (United States)

Cerdeira, A.; Garduño, I.; Tinoco, J.; Ritzenthaler, R.; Franco, J.; Togo, M.; Chiarella, T.; Claeys, C.

2013-09-01

Multiple-gate MOSFETs became an industrial reality in the last years. Due to a pragmatic trade-off between CMOS process baselines compatibility, improved performance compared to planar bulk architecture, and cost, bulk FinFETs emerged as the technological solution to provide downscaling for the 14/22 nm technological nodes. In this work, a charge based DC compact model based on the SDDG Model is demonstrated for this new generation of FinFET transistors and describes continuously the transistor characteristics in all operating regions. Validating the model against two bulk FinFET baselines (NMOS, PMOS, various gate lengths and EOT), an excellent agreement is found for transfer and output characteristics (linear and saturation regimes), transconductance/output conductance, and gm/IDS characteristics. Temperature dependence is also taken into account and validated (T range from 25 °C up to 175 °C).

Shootthrough fault protection system for bipolar transistors in a voltage source transistor inverter

International Nuclear Information System (INIS)

Wirth, W.F.

1982-01-01

Faulted bipolar transistors in a voltage source transistor inverter are protected against shootthrough fault current, from the filter capacitor of the d-c voltage source which drives the inverter over the d-c bus, by interposing a small choke in series with the filter capacitor to limit the rate of rise of that fault current while at the same time causing the d-c bus voltage to instantly drop to essentially zero volts at the beginning of a shootthrough fault. In this way, the load lines of the faulted transistors are effectively shaped so that they do not enter the second breakdown area, thereby preventing second breakdown destruction of the transistors

Transparent Thin-Film Transistors Based on Sputtered Electric Double Layer.

Science.gov (United States)

Cai, Wensi; Ma, Xiaochen; Zhang, Jiawei; Song, Aimin

2017-04-20

Electric-double-layer (EDL) thin-film transistors (TFTs) have attracted much attention due to their low operation voltages. Recently, EDL TFTs gated with radio frequency (RF) magnetron sputtered SiO₂ have been developed which is compatible to large-area electronics fabrication. In this work, fully transparent Indium-Gallium-Zinc-Oxide-based EDL TFTs on glass substrates have been fabricated at room temperature for the first time. A maximum transmittance of about 80% has been achieved in the visible light range. The transparent TFTs show a low operation voltage of 1.5 V due to the large EDL capacitance (0.3 µF/cm² at 20 Hz). The devices exhibit a good performance with a low subthreshold swing of 130 mV/dec and a high on-off ratio > 10⁵. Several tests have also been done to investigate the influences of light irradiation and bias stress. Our results suggest that such transistors might have potential applications in battery-powered transparent electron devices.

High performance tunnel field-effect transistor by gate and source engineering

International Nuclear Information System (INIS)

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-01-01

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I ON /I OFF ratio (∼10 7 ) at V DS  = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high I ON /I OFF ratio of ∼10 8 and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec −1 was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching. (paper)

InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

Science.gov (United States)

Radisic, Vesna; Sawdai, Donald; Scott, Dennis; Deal, William; Dang, Linh; Li, Danny; Cavus, Abdullah; To, Richard; Lai, Richard

2009-01-01

Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

A High-Voltage Level Tolerant Transistor Circuit

NARCIS (Netherlands)

Annema, Anne J.; Geelen, Godefridus Johannes Gertrudis Maria

2001-01-01

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1)

Diode, transistor & fet circuits manual

CERN Document Server

Marston, R M

2013-01-01

Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

Ferroelectric-gate field effect transistor memories device physics and applications

CERN Document Server

Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

2016-01-01

This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

Science.gov (United States)

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

Science.gov (United States)

Hsu, Yu-Jen

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by

Low temperature high-mobility InZnO thin-film transistors fabricated by excimer laser annealing

NARCIS (Netherlands)

Fujii, M.; Ishikawa, Y.; Ishihara, R.; Van der Cingel, J.; Mofrad, M.R.T.; Horita, M.; Uraoka, Y.

2013-01-01

In this study, we successfully achieved a relatively high field-effect mobility of 37.7?cm2/Vs in an InZnO thin-film transistor (TFT) fabricated by excimer layer annealing (ELA). The ELA process allowed us to fabricate such a high-performance InZnO TFT at the substrate temperature less than 50?°C

Screen printing as a scalable and low-cost approach for rigid and flexible thin-film transistors using separated carbon nanotubes.

Science.gov (United States)

Cao, Xuan; Chen, Haitian; Gu, Xiaofei; Liu, Bilu; Wang, Wenli; Cao, Yu; Wu, Fanqi; Zhou, Chongwu

2014-12-23

Semiconducting single-wall carbon nanotubes are very promising materials in printed electronics due to their excellent mechanical and electrical property, outstanding printability, and great potential for flexible electronics. Nonetheless, developing scalable and low-cost approaches for manufacturing fully printed high-performance single-wall carbon nanotube thin-film transistors remains a major challenge. Here we report that screen printing, which is a simple, scalable, and cost-effective technique, can be used to produce both rigid and flexible thin-film transistors using separated single-wall carbon nanotubes. Our fully printed top-gated nanotube thin-film transistors on rigid and flexible substrates exhibit decent performance, with mobility up to 7.67 cm2 V(-1) s(-1), on/off ratio of 10(4)∼10(5), minimal hysteresis, and low operation voltage (transistors (bent with radius of curvature down to 3 mm) and driving capability for organic light-emitting diode have been demonstrated. Given the high performance of the fully screen-printed single-wall carbon nanotube thin-film transistors, we believe screen printing stands as a low-cost, scalable, and reliable approach to manufacture high-performance nanotube thin-film transistors for application in display electronics. Moreover, this technique may be used to fabricate thin-film transistors based on other materials for large-area flexible macroelectronics, and low-cost display electronics.

On theory of single-molecule transistor

International Nuclear Information System (INIS)

Tran Tien Phuc

2009-01-01

The results of the study on single-molecule transistor are mainly investigated in this paper. The structure of constructed single-molecule transistor is similar to a conventional MOSFET. The conductive channel of the transistors is a single-molecule of halogenated benzene derivatives. The chemical simulation software CAChe was used to design and implement for the essential parameter of the molecules utilized as the conductive channel. The GUI of Matlab has been built to design its graphical interface, calculate and plot the output I-V characteristic curves for the transistor. The influence of temperature, length and width of the conductive channel, and gate voltage is considered. As a result, the simulated curves are similar to the traditional MOSFET's. The operating temperature range of the transistors is wider compared with silicon semiconductors. The supply voltage for transistors is only about 1 V. The size of transistors in this research is several nanometers.

Carbon nanotube transistor based high-frequency electronics

Science.gov (United States)

Schroter, Michael

At the nanoscale carbon nanotubes (CNTs) have higher carrier mobility and carrier velocity than most incumbent semiconductors. Thus CNT based field-effect transistors (FETs) are being considered as strong candidates for replacing existing MOSFETs in digital applications. In addition, the predicted high intrinsic transit frequency and the more recent finding of ways to achieve highly linear transfer characteristics have inspired investigations on analog high-frequency (HF) applications. High linearity is extremely valuable for an energy efficient usage of the frequency spectrum, particularly in mobile communications. Compared to digital applications, the much more relaxed constraints for CNT placement and lithography combined with already achieved operating frequencies of at least 10 GHz for fabricated devices make an early entry in the low GHz HF market more feasible than in large-scale digital circuits. Such a market entry would be extremely beneficial for funding the development of production CNTFET based process technology. This talk will provide an overview on the present status and feasibility of HF CNTFET technology will be given from an engineering point of view, including device modeling, experimental results, and existing roadblocks. Carbon nanotube transistor based high-frequency electronics.

On-Chip Chemical Self-Assembly of Semiconducting Single-Walled Carbon Nanotubes (SWNTs) : Toward Robust and Scale Invariant SWNTs Transistors

NARCIS (Netherlands)

Derenskyi, Vladimir; Gomulya, Widianta; Talsma, Wytse; Salazar-Rios, Jorge Mario; Fritsch, Martin; Nirmalraj, Peter; Riel, Heike; Allard, Sybille; Scherf, Ullrich; Loi, Maria A.

2017-01-01

In this paper, the fabrication of carbon nanotubes field effect transistors by chemical self-assembly of semiconducting single walled carbon nanotubes (s-SWNTs) on prepatterned substrates is demonstrated. Polyfluorenes derivatives have been demonstrated to be effective in selecting s-SWNTs from raw

Gate-modulated conductance of few-layer WSe{sub 2} field-effect transistors in the subgap regime: Schottky barrier transistor and subgap impurity states

Energy Technology Data Exchange (ETDEWEB)

Wang, Junjie; Feng, Simin [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Rhodes, Daniel; Balicas, Luis [National High Magnetic Field Lab, Florida State University, Tallahassee, Florida 32310 (United States); Nguyen, Minh An T. [Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Watanabe, K.; Taniguchi, T. [National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044 (Japan); Mallouk, Thomas E. [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Biochemistry and Molecular Biology, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Terrones, Mauricio [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Zhu, J., E-mail: jzhu@phys.psu.edu [Department of Physics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States); Center for 2-Dimensional and Layered Materials, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States)

2015-04-13

Two key subjects stand out in the pursuit of semiconductor research: material quality and contact technology. The fledging field of atomically thin transition metal dichalcogenides (TMDCs) faces a number of challenges in both efforts. This work attempts to establish a connection between the two by examining the gate-dependent conductance of few-layer (1-5L) WSe{sub 2} field effect devices. Measurements and modeling of the subgap regime reveal Schottky barrier transistor behavior. We show that transmission through the contact barrier is dominated by thermionic field emission (TFE) at room temperature, despite the lack of intentional doping. The TFE process arises due to a large number of subgap impurity states, the presence of which also leads to high mobility edge carrier densities. The density of states of such impurity states is self-consistently determined to be approximately 1–2 × 10{sup 13}/cm{sup 2}/eV in our devices. We demonstrate that substrate is unlikely to be a major source of the impurity states and suspect that lattice defects within the material itself are primarily responsible. Our experiments provide key information to advance the quality and understanding of TMDC materials and electrical devices.

Dosimetric properties of MOS transistors

International Nuclear Information System (INIS)

Frank, H.; Petr, I.

1977-01-01

The structure of MOS transistors is described and their characteristics given. The experiments performed and data in the literature show the following dosimetric properties of MOS transistors: while for low gamma doses the transistor response to exposure is linear, it shows saturation for higher doses (exceeding 10 3 Gy in tissue). The response is independent of the energy of radiation and of the dose rate (within 10 -2 to 10 5 Gy/s). The spontaneous reduction with time of the spatial charge captured by the oxide layer (fading) is small and acceptable from the point of view of dosimetry. Curves are given of isochronous annealing of the transistors following irradiation with 137 Cs and 18 MeV electrons for different voltages during irradiation. The curves show that in MOS transistors irradiated with high-energy electrons the effect of annealing is less than in transistors irradiated with 137 Cs. In view of the requirement of using higher temperatures (approx. 400 degC) for the complete ''erasing'' of the captured charge, unsealed systems must be used for dosimetric purposes. The effect was also studied of neutron radiation, proton radiation and electron radiation on the MOS transistor structure. For MOS transistor irradiation with 14 MeV neutrons from a neutron generator the response was 4% of that for gamma radiation at the same dose equivalent. The effect of proton radiation was studied as related to the changes in MOS transistor structure during space flights. The response curve shapes are similar to those of gamma radiation curves. The effect of electron radiation on the MOS structure was studied by many authors. The experiments show that for each thickness of the SiO 2 layer an electron energy exists at which the size of the charge captured in SiO 2 is the greatest. All data show that MOS transistors are promising for radiation dosimetry. The main advantage of MOS transistors as gamma dosemeters is the ease and speed of evaluation, low sensitivity to neutron

Influence of halo doping profiles on MOS transistor mismatch

NARCIS (Netherlands)

Andricciola, P.; Tuinhout, H.

2009-01-01

Halo implants are used in modern CMOS technology to reduce the short channel effect. However, the lateral non-uniformity of the channel doping has been proven to degenerate the mismatch performance. With this paper we want to discuss the influence of the halo profile on MOS transistor mismatch. The

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

Air-stable complementary-like circuits based on organic ambipolar transistors

NARCIS (Netherlands)

Anthopoulos, Thomas D.; Setayesh, Sepas; Smits, Edsger; Cantatore, Eugenio; Boer ,de Bert; Blom, Paul W. M.; de Leeuw, Dago M.; Cölle, Michael

2006-01-01

Air stable complementary-like circuits, such as voltage inverters (see figure) and ring oscillators, are fabricated using ambipolar organic transistors based on a nickel dithiolene derivative. In addition to the complementary-like character of the circuits, the technology is very simple and fully

Colour tuneable light-emitting transistor

Energy Technology Data Exchange (ETDEWEB)

Feldmeier, Eva J.; Melzer, Christian; Seggern, Heinz von [Electronic Materials Department, Institute of Materials Science, Technische Universitaet Darmstadt (Germany)

2010-07-01

In recent years the interest in ambipolar organic light-emitting field-effect transistors has increased steadily as the devices combine switching behaviour of transistors with light emission. Usually, small molecules and polymers with a band gap in the visible spectral range serve as semiconducting materials. Mandatory remain balanced injection and transport properties for both charge carrier types to provide full control of the spatial position of the recombination zone of electrons and holes in the transistor channel via the applied voltages. As will be presented here, the spatial control of the recombination zone opens new possibilities towards light-emitting devices with colour tuneable emission. In our contribution an organic light-emitting field-effect transistors is presented whose emission colour can be changed by the applied voltages. The organic top-contact field-effect transistor is based on a parallel layer stack of acenes serving as organic transport and emission layers. The transistor displays ambipolar characteristics with a narrow recombination zone within the transistor channel. During operation the recombination zone can be moved by a proper change in the drain and gate bias from one organic semiconductor layer to another one inducing a change in the emission colour. In the presented example the emission maxima can be switched from 530 nm to 580 nm.

FY 1991 Research and development project for large-scale industrial technologies. Report on results of R and D of superhigh technological machining systems; 1991 nendo chosentan kako system no kenkyu kaihatsu seika hokokusho. Chosentan kako system no kenkyu kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

1992-03-01

Described herein are the FY 1991 results of the R and D project aimed at establishment of superprecision machining technologies for developing machining technologies and nano-technologies aided by excited beams. The researches on the superprecision machining technologies involve design and development, on a trial basis, of the totally static pressure type positioning device, for which automatically controlling drawing is adopted to improve its rigidity. The researches on the surface modification technologies aided by ion beams involve scanning the ion beams onto the metallic plate to be provided around the glass substrate. The results indicate that the secondary electrons generated can be used to control charge-up. In addition, part of a 30cm square glass substrate is modified by implantation of the spot type ions of high current density, and the modified portion is used to produce a thin-film silicon transistor. The researches on superhigh-technological machining standard measurement involve improvement of precision of the system aided by a dye laser, which attains a precision of 0 to 30nm in a 0.1m measurement range. (NEDO)

Passivated graphene transistors fabricated on a millimeter-sized single-crystal graphene film prepared with chemical vapor deposition

International Nuclear Information System (INIS)

Lin, Meng-Yu; Lee, Si-Chen; Lin, Shih-Yen; Wang, Cheng-Hung; Chang, Shu-Wei

2015-01-01

In this work, we first investigate the effects of partial pressures and flow rates of precursors on the single-crystal graphene growth using chemical vapor depositions on copper foils. These factors are shown to be critical to the growth rate, seeding density and size of graphene single crystals. The prepared graphene films in millimeter sizes are then bubbling transferred to silicon-dioxide/silicon substrates for high-mobility graphene transistor fabrications. After high-temperature annealing and hexamethyldisilazane passivation, the water attachment is removed from the graphene channel. The elimination of uncontrolled doping and enhancement of carrier mobility accompanied by these procedures indicate that they are promising for fabrications of graphene transistors. (paper)

Dosimetric properties of MOS transistors

International Nuclear Information System (INIS)

Peter, I.; Frank, G.

1977-01-01

The performance of MOS transistors as gamma detectors has been tested. The dosimeter sensitivity has proved to be independent on the doses ranging from 10 3 to 10 6 R, and gamma energy of 137 Cs, 60 Co - sources and 5 - 18 MeV electrons. Fading of the space charge trapped by the SiO 2 layer of the transistor has appeared to be neglegible at room temperature after 400 hrs. The isochronous annealing in the temperature range of 40-260 deg C had a more substantial effect on the space charge of the transistor irradiated with 18 MeV electrons than on the 137 Cs gamma-irradiated transistors. This proved a repeated use of γ-dosemeters. MOS transistors are concluded to be promising for gamma dosimetry [ru

Transistor-based particle detection systems and methods

Science.gov (United States)

Jain, Ankit; Nair, Pradeep R.; Alam, Muhammad Ashraful

2015-06-09

Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.

Recent Advances of Solution-Processed Metal Oxide Thin-Film Transistors.

Science.gov (United States)

Xu, Wangying; Li, Hao; Xu, Jian-Bin; Wang, Lei

2018-03-06

Solution-processed metal oxide thin-film transistors (TFTs) are considered as one of the most promising transistor technologies for future large-area flexible electronics. This review surveys the recent advances in solution-based oxide TFTs, including n-type oxide semiconductors, oxide dielectrics and p-type oxide semiconductors. Firstly, we provide an introduction on oxide TFTs and the TFT configurations and operating principles. Secondly, we present the recent progress in solution-processed n-type transistors, with a special focus on low-temperature and large-area solution processed approaches as well as novel non-display applications. Thirdly, we give a detailed analysis of the state-of-the-art solution-processed oxide dielectrics for low-voltage electronics. Fourthly, we discuss the recent progress in solution-based p-type oxide semiconductors, which will enable the highly desirable future low-cost large-area complementary circuits. Finally, we draw the conclusions and outline the perspectives over the research field.

Electron irradiation of power transistors

International Nuclear Information System (INIS)

Hower, P.L.; Fiedor, R.J.

1982-01-01

A method for reducing storage time and gain parameters in a semiconductor transistor includes the step of subjecting the transistor to electron irradiation of a dosage determined from measurements of the parameters of a test batch of transistors. Reduction of carrier lifetime by proton bombardment and gold doping is mentioned as an alternative to electron irradiation. (author)

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

Science.gov (United States)

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Synthesis and characterization of copper, polyimide and TIPS-pentacene layers for the development of a solution processed fibrous transistor

Directory of Open Access Journals (Sweden)

B. Van Genabet

2011-12-01

Full Text Available A study was performed for the development of a flexible organic field effect transistor starting from a polyester fibre as substrate material. Focus of subsequent layer deposition was on low temperature soluble processes to allow upscaling. Gate layer consists out of a pyrrole polymerization and copper coating step. Polyimide dielectric layer was deposited using dipcoating. Gold electrodes were vacuum evaporated and patterned via mask fibre shadowing. The active layer consisted of a soluble p-type TIPS-pentacene organic semiconductor. Different deposition techniques have been examined. Considerable progress in development of a transistor has been made.

Liquid–Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing

KAUST Repository

Zhang, Yu

2017-10-17

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid–liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the “sensing channel” can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

Science.gov (United States)

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Understanding noise suppression in heterojunction field-effect transistors

International Nuclear Information System (INIS)

Green, F.

1996-01-01

Full text: The enhanced transport properties displayed by quantum-well-confined, two-dimensional, electron systems underpin the success of heterojunction, field-effect transistors. At cryogenic temperatures, these devices exhibit impressive mobilities and, as a result, high signal gain and low noise. Conventional wisdom has it that the same favourable conditions also hold for normal room-temperature operation. In that case, however, high mobilities are precluded by abundant electron-phonon scattering. Our recent study of nonequilibrium current noise shows that quantum confinement, not high mobility, is the principal source of noise in these devices; this opens up new and exciting opportunities in low-noise transistor design. As trends in millimetre-wave technology push frequencies beyond 100 GHz, it is essential to develop a genuine understanding of noise processes in heterojunction devices

Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

KAUST Repository

Li, Jingqi

2014-07-01

A vertical carbon nanotube field-effect transistor (CNTFET) based on silicon (Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube (SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage (Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

KAUST Repository

Li, Jingqi; Yue, Weisheng; Guo, Zaibing; Yang, Yang; Wang, Xianbin; Syed, Ahad A.; Zhang, Yafei

2014-01-01

A vertical carbon nanotube field-effect transistor (CNTFET) based on silicon (Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube (SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage (Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

Solution-processed p-type copper(I) thiocyanate (CuSCN) for low-voltage flexible thin-film transistors and integrated inverter circuits

KAUST Repository

Petti, Luisa; Pattanasattayavong, Pichaya; Lin, Yen-Hung; Mü nzenrieder, Niko; Cantarella, Giuseppe; Yaacobi-Gross, Nir; Yan, Feng; Trö ster, Gerhard; Anthopoulos, Thomas D.

2017-01-01

, depending on the gate dielectric employed. The promising TFT characteristics enable fabrication of unipolar NOT gates on flexible free-standing plastic substrates with voltage gain of 3.4 at voltages as low as −3.5 V. Importantly, discrete CuSCN transistors

Reevaluating the worst-case radiation response of MOS transistors

Science.gov (United States)

Fleetwood, D. M.

Predicting worst-case response of a semiconductor device to ionizing radiation is a formidable challenge. As processes change and MOS gate insulators become thinner in advanced VLSI and VHSIC technologies, failure mechanisms must be constantly re-examined. Results are presented of a recent study in which more than 100 MOS transistors were monitored for up to 300 days after Co-60 exposure. Based on these results, a reevaluation of worst-case n-channel transistor response (most positive threshold voltage shift) in low-dose-rate and postirradiation environments is required in many cases. It is shown for Sandia hardened n-channel transistors with a 32 nm gate oxide, that switching from zero-volt bias, held during the entire radiation period, to positive bias during anneal clearly leads to a more positive threshold voltage shift (and thus the slowest circuit response) after Co-60 exposure than the standard case of maintaining positive bias during irradiation and anneal. It is concluded that irradiating these kinds of transistors with zero-volt bias, and annealing with positive bias, leads to worst-case postirradiation response. For commercial devices (with few interface states at doses of interest), on the other hand, device response only improves postirradiation, and worst-case response (in terms of device leakage) is for devices irradiated under positive bias and annealed with zero-volts bias.

High-Mobility 6,13-Bis(triisopropylsilylethynyl) Pentacene Transistors Using Solution-Processed Polysilsesquioxane Gate Dielectric Layers.

Science.gov (United States)

Matsuda, Yu; Nakahara, Yoshio; Michiura, Daisuke; Uno, Kazuyuki; Tanaka, Ichiro

2016-04-01

Polysilsesquioxane (PSQ) is a low-temperature curable polymer that is compatible with low-cost plastic substrates. We cured PSQ gate dielectric layers by irradiation with ultraviolet light at ~60 °C, and used them for 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) thin film transistors (TFTs). The fabricated TFTs have shown the maximum and average hole mobility of 1.3 and 0.78 ± 0.3 cm2V-1s-1, which are comparable to those of the previously reported transistors using single-crystalline TIPS-pentacene micro-ribbons for their active layers and thermally oxidized SiO2 for their gate dielectric layers. Itis therefore demonstrated that PSQ is a promising polymer gate dielectric material for low-cost organic TFTs.

The point of practical use for the transistor circuit

International Nuclear Information System (INIS)

1996-01-01

This is comprised of eight chapters and goes as follows; what is transistor? the first step for use of transistor such as connection between power and signal source, static characteristic of transistor and equivalent circuit of transistor, design of easy small-signal amplifier circuit, design for amplification of electric power and countermeasure for prevention of trouble, transistor concerned interface, transistor circuit around micro computer, transistor in active use of FET and power circuit and transistor. It has an appendix on transistor and design of bias of FET circuits like small signal transistor circuit and FET circuit.

Physical limits of silicon transistors and circuits

International Nuclear Information System (INIS)

Keyes, Robert W

2005-01-01

A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented

Avalanche transistor pulser for fast-gated operation of micro-channel plate image-intensifiers

International Nuclear Information System (INIS)

Lundy, A.; Parker, J.R.; Lunsford, J.S.; Martin, A.D.

1977-01-01

Transistors operated in the avalanche mode are employed to generate a 1000 volt 10 to 30 nsec wide pulse with less than 4 nsec rise and fall times. This pulse is resistively attenuated to approximately equal to 270 volts and drives the image intensifier tube which is a load of approximately equal to 200 pf. To reduce stray inductance and capacitance, transistor chips were assembled on a thick-film hybrid substrate. Circuit parameters, operating conditions, and coupling to the microchannel plate image-intensifier (MCPI 2 ) tube are described. To provide dc operating voltages and control of transient voltages on the MCPI 2 tube a resistance-capacitance network has been developed which (a) places the MCPI 2 output phosphor at ground, (b) provides programmable gains in ''f-stop'' steps, and (c) minimizes voltage transients on the MCPI 2 tube

Ultrathin regioregular poly(3-hexyl thiophene) field-effect transistors

DEFF Research Database (Denmark)

Sandberg, H.G.O.; Frey, G.L.; Shkunov, M.N.

2002-01-01

Ultrathin films of regioregular poly(3-hexyl thiophene) (RR-P3HT) were deposited through a dip-coating technique and utilized as the semiconducting film in field-effect transistors (FETs). Proper selection of the substrate and solution concentration enabled the growth of a monolayer-thick RR-P3HT...... film. Atomic force microscopy (AFM), U-V-vis absorption spectroscopy, X-ray reflectivity, and grazing incidence diffraction were used to study the growth mechanism, thickness and orientation of self-organized monolayer thick RR-P3HT films on SiO2 surfaces. Films were found to adopt a Stranski......-Krastanov-type growth mode with formation of a very stable first monolayer. X-ray measurements show that the direction of pi-stacking in the films (the (010) direction) is parallel to the substrate, which is the preferred orientation for high field-effect carrier mobilities. The field-effect mobilities in all ultrathin...

Research on high-efficiency polishing technology of photomask substrate

Science.gov (United States)

Zhao, Shijie; Xie, Ruiqing; Zhou, Lian; Liao, Defeng; Chen, Xianhua; Wang, Jian

2018-03-01

A method of photomask substrate fabrication is demonstrated ,that the surface figure and roughness of fused silica will converge to target precision rapidly with the full aperture polishing. Surface figure of optical flats in full aperture polishing processes is primarily dependent on the surface profile of polishing pad, therefor, a improved function of polishing mechanism was put forward based on two axis lapping machine and technology experience, and the pad testing based on displacement sensor and the active conditioning method of the pad is applied in this research. Moreover , the clamping deformation of the thin glass is solved by the new pitch dispensing method. The experimental results show that the surface figure of the 152mm×152mm×6.35mm optical glass is 0.25λ(λ=633nm) and the roughness is 0.32nm ,which has meet the requirements of mask substrate for 90 45nm nodes.

High performance, transparent a-IGZO TFTs on a flexible thin glass substrate

International Nuclear Information System (INIS)

Lee, Gwang Jun; Jang, Jae Eun; Kim, Joonwoo; Kim, Jung-Hye; Jeong, Soon Moon; Jeong, Jaewook

2014-01-01

We investigated electrical properties of transparent amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with amorphous indium zinc oxide (a-IZO) transparent electrodes on a flexble thin glass substrate. The TFTs show a high field-effect mobility, a good subthreshold slope and a high on/off ratio owing to the high temperature thermal annealing process which cannot be applied to typical transparent polymer-based flexible substrates. Bias stress instability tests applying tensile stress concurrently with the bending radius of up to 40 mm indicated that mechanically and electrically stable a-IGZO TFTs can be fabricated on the transparent thin glass substrate. (paper)

Titanyl phthalocyanine ambipolar thin film transistors making use of carbon nanotube electrodes

Science.gov (United States)

Coppedè, Nicola; Valitova, Irina; Mahvash, Farzaneh; Tarabella, Giuseppe; Ranzieri, Paolo; Iannotta, Salvatore; Santato, Clara; Martel, Richard; Cicoira, Fabio

2014-12-01

The capability of efficiently injecting charge carriers into organic films and finely tuning their morphology and structure is crucial to improve the performance of organic thin film transistors (OTFTs). In this work, we investigate OTFTs employing carbon nanotubes (CNTs) as the source-drain electrodes and, as the organic semiconductor, thin films of titanyl phthalocyanine (TiOPc) grown by supersonic molecular beam deposition (SuMBD). While CNT electrodes have shown an unprecedented ability to improve charge injection in OTFTs, SuMBD is an effective technique to tune film morphology and structure. Varying the substrate temperature during deposition, we were able to grow both amorphous (low substrate temperature) and polycrystalline (high substrate temperature) films of TiOPc. Regardless of the film morphology and structure, CNT electrodes led to superior charge injection and transport performance with respect to benchmark Au electrodes. Vacuum annealing of polycrystalline TiOPc films with CNT electrodes yielded ambipolar OTFTs.

High Charge Carrier Mobility Polymers for Organic Transistors

OpenAIRE

Erdmann, Tim

2017-01-01

I) Introduction p-Conjugated polymers inherently combine electronic properties of inorganic semiconductor crystals and material characteristics of organic plastics due to their special molecular design. This unique combination has led to developing new unconventional optoelectronic technologies and, further, resulted in the evolution of semiconducting polymers (SCPs) as fundamental components for novel electronic devices, such as organic field-effect transistors (OFETs), organic light-emit...

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

Directory of Open Access Journals (Sweden)

Gaspar Casados-Cruz

2010-11-01

Full Text Available Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors

Science.gov (United States)

Marrs, Michael

A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

Science.gov (United States)

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Growth of a single-wall carbon nanotube film and its patterning as an n-type field effect transistor device using an integrated circuit compatible process

Energy Technology Data Exchange (ETDEWEB)

Shiau, S H; Gau, C [Institute of Aeronautics and Astronautics, and Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan, Taiwan (China); Liu, C W; Dai, B T [National Nano Device Laboratories, No. 27, Nanke 3rd Road, Science-based Industrial Park, Hsin-shi, Tainan, Taiwan (China)], E-mail: gauc@mail.ncku.edu.tw

2008-03-12

This study presents the synthesis of a dense single-wall carbon nanotube (SWNT) network on a silicon substrate using alcohol as the source gas. The nanosize catalysts required are made by the reduction of metal compounds in ethanol. The key point in spreading the nanoparticles on the substrate, so that the SWNT network can be grown over the entire wafer, is making the substrate surface hydrophilic. This SWNT network is so dense that it can be treated like a thin film. Methods of patterning this SWNT film with integrated circuit compatible processes are presented and discussed for the first time in the literature. Finally, fabrication and characteristic measurements of a field effect transistor (FET) using this SWNT film are also demonstrated. This FET is shown to have better electronic properties than any other kind of thin film transistor. This thin film with good electronic properties can be readily applied in the processing of many other SWNT electronic devices.

Neuromorphic transistor achieved by redox reaction of WO3 thin film

Science.gov (United States)

Tsuchiya, Takashi; Jayabalan, Manikandan; Kawamura, Kinya; Takayanagi, Makoto; Higuchi, Tohru; Jayavel, Ramasamy; Terabe, Kazuya

2018-04-01

An all-solid-state neuromorphic transistor composed of a WO3 thin film and a proton-conducting electrolyte was fabricated for application to next-generation information and communication technology including artificial neural networks. The drain current exhibited a 4-order-of-magnitude increment by redox reaction of the WO3 thin film owing to proton migration. Learning and forgetting characteristics were well tuned by the gate control of WO3 redox reactions owing to the separation of the current reading path and pulse application path in the transistor structure. This technique should lead to the development of versatile and low-power-consumption neuromorphic devices.

A mixed analog-digital radiation hard technology for high energy physics electronics DMILL (Durci Mixte sur Isolant Logico-Linéaire)

CERN Document Server

Beuville, E; Borgeaud, P; Fourches, N T; Rouger, M; Blanc, J P; Bruel, M; Delevoye-Orsier, E; Gautier, J; Du Port de Pontcharra, J; Truche, R; Dupont-Nivet, E; Flament, O; Leray, J L; Martin, J L; Montaron, J; Borel, G; Brice, J M; Chatagnon, P; Terrier, C; Aubert, Jean-Jacques; Delpierre, P A; Habrard, M C; Potheau, R; CERN. Geneva. Detector Research and Development Committee

1992-01-01

The high radiation level expected in the inner regions of the high luminosity LHC detectors (gamma and neutron) will require radiation hardened electronics. A consortium between the CEA (Commissariat a l'Energie Atomique) and Thomson TMS (Thomson Composants Militaires et Spatiaux) has been created to push for the development and the industrialization of a nascent technology which looks particularly adapted to the needs of HEP electronics. This technology, currently under development at the LETI(CEA), uses a SIMOX substrate with an epitaxial silicon film. It includes CMOS, JFETs and vertical bipolar transistors with a potential multi-megarad hardness. The CMOS and bipolar transistors constitute a rad-hard BiCMOS which will be useful to design analog and digital high-speed architectures. JFETs, which have intrinsically high hardness behaviour and low noise performances even at low temperature will enable very rad-hard, low noise front end electronics to be designed. Present results, together with the improvemen...

Power transistor module for high current applications

International Nuclear Information System (INIS)

Cilyo, F.F.

1975-01-01

One of the parts needed for the control system of the 400-GeV accelerator at Fermilab was a power transistor with a safe operating area of 1800A at 50V, dc current gain of 100,000 and 20 kHz bandwidth. Since the commercially available discrete devices and power hybrid packages did not meet these requirements, a power transistor module was developed which performed satisfactorily. By connecting 13 power transistors in parallel, with due consideration for network and heat dissipation problems, and by driving these 13 with another power transistor, a super power transistor is made, having an equivalent current, power, and safe operating area capability of 13 transistors. For higher capabilities, additional modules can be conveniently added. (auth)

Impact of regioregularity on thin-film transistor and photovoltaic cell performances of pentacene-containing polymers

KAUST Repository

Jiang, Ying

2012-01-01

Regioregular pentacene-containing polymers were synthesized with alkylated bithiophene (BT) and cyclopentadithiophene (CPDT) as comonomers. Among them, 2,9-conjugated polymers PnBT-2,9 and PnCPDT-2,9 achieved the best performance in transistor and photovoltaic devices respectively. The former achieved the most highly ordered structures in thin films, yielding ambipolar transistor behavior with hole and electron mobilities up to 0.03 and 0.02 cm 2 V -1 s -1 on octadecylsilane-treated substrates. The latter achieved photovoltaic power conversion efficiencies up to 0.33%. The impact of regioregularity and direction of conjugation-extension (2,9 vs. 2,10), on thin-film order and device performance has been demonstrated for the pentacene-containing polymers for the first time, providing insight towards future functional material design. © 2012 The Royal Society of Chemistry.

Analysing organic transistors based on interface approximation

International Nuclear Information System (INIS)

Akiyama, Yuto; Mori, Takehiko

2014-01-01

Temperature-dependent characteristics of organic transistors are analysed thoroughly using interface approximation. In contrast to amorphous silicon transistors, it is characteristic of organic transistors that the accumulation layer is concentrated on the first monolayer, and it is appropriate to consider interface charge rather than band bending. On the basis of this model, observed characteristics of hexamethylenetetrathiafulvalene (HMTTF) and dibenzotetrathiafulvalene (DBTTF) transistors with various surface treatments are analysed, and the trap distribution is extracted. In turn, starting from a simple exponential distribution, we can reproduce the temperature-dependent transistor characteristics as well as the gate voltage dependence of the activation energy, so we can investigate various aspects of organic transistors self-consistently under the interface approximation. Small deviation from such an ideal transistor operation is discussed assuming the presence of an energetically discrete trap level, which leads to a hump in the transfer characteristics. The contact resistance is estimated by measuring the transfer characteristics up to the linear region

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

KAUST Repository

Gutiérrez-Heredia, Gerardo

2010-10-04

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/ parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 μA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 μA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O 3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas \\'parylene only\\' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented. © 2010 IOP Publishing Ltd.

Highly Sensitive Flexible Pressure Sensors Based on Printed Organic Transistors with Centro-Apically Self-Organized Organic Semiconductor Microstructures.

Science.gov (United States)

Yeo, So Young; Park, Sangsik; Yi, Yeon Jin; Kim, Do Hwan; Lim, Jung Ah

2017-12-13

A highly sensitive pressure sensor based on printed organic transistors with three-dimensionally self-organized organic semiconductor microstructures (3D OSCs) was demonstrated. A unique organic transistor with semiconductor channels positioned at the highest summit of printed cylindrical microstructures was achieved simply by printing an organic semiconductor and polymer blend on the plastic substrate without the use of additional etching or replication processes. A combination of the printed organic semiconductor microstructure and an elastomeric top-gate dielectric resulted in a highly sensitive organic field-effect transistor (FET) pressure sensor with a high pressure sensitivity of 1.07 kPa -1 and a rapid response time of <20 ms with a high reliability over 1000 cycles. The flexibility and high performance of the 3D OSC FET pressure sensor were exploited in the successful application of our sensors to real-time monitoring of the radial artery pulse, which is useful for healthcare monitoring, and to touch sensing in the e-skin of a realistic prosthetic hand.

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

KAUST Repository

Gutié rrez-Heredia, Gerardo; Gonzá lez, Luis A.; Alshareef, Husam N.; Gnade, Bruce E.; Quevedo-Ló pez, Manuel Angel Quevedo

2010-01-01

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/ parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 μA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 μA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O 3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas 'parylene only' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented. © 2010 IOP Publishing Ltd.

Recent Progress in the Development of Printed Thin-Film Transistors and Circuits with High-Resolution Printing Technology.

Science.gov (United States)

Fukuda, Kenjiro; Someya, Takao

2017-07-01

Printed electronics enable the fabrication of large-scale, low-cost electronic devices and systems, and thus offer significant possibilities in terms of developing new electronics/optics applications in various fields. Almost all electronic applications require information processing using logic circuits. Hence, realizing the high-speed operation of logic circuits is also important for printed devices. This report summarizes recent progress in the development of printed thin-film transistors (TFTs) and integrated circuits in terms of materials, printing technologies, and applications. The first part of this report gives an overview of the development of functional inks such as semiconductors, electrodes, and dielectrics. The second part discusses high-resolution printing technologies and strategies to enable high-resolution patterning. The main focus of this report is on obtaining printed electrodes with high-resolution patterning and the electrical performance of printed TFTs using such printed electrodes. In the final part, some applications of printed electronics are introduced to exemplify their potential. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Titanyl phthalocyanine ambipolar thin film transistors making use of carbon nanotube electrodes

International Nuclear Information System (INIS)

Coppedè, Nicola; Tarabella, Giuseppe; Ranzieri, Paolo; Iannotta, Salvatore; Valitova, Irina; Cicoira, Fabio; Mahvash, Farzaneh; Santato, Clara; Martel, Richard

2014-01-01

The capability of efficiently injecting charge carriers into organic films and finely tuning their morphology and structure is crucial to improve the performance of organic thin film transistors (OTFTs). In this work, we investigate OTFTs employing carbon nanotubes (CNTs) as the source-drain electrodes and, as the organic semiconductor, thin films of titanyl phthalocyanine (TiOPc) grown by supersonic molecular beam deposition (SuMBD). While CNT electrodes have shown an unprecedented ability to improve charge injection in OTFTs, SuMBD is an effective technique to tune film morphology and structure. Varying the substrate temperature during deposition, we were able to grow both amorphous (low substrate temperature) and polycrystalline (high substrate temperature) films of TiOPc. Regardless of the film morphology and structure, CNT electrodes led to superior charge injection and transport performance with respect to benchmark Au electrodes. Vacuum annealing of polycrystalline TiOPc films with CNT electrodes yielded ambipolar OTFTs. (paper)

Distributed amplifier using Josephson vortex flow transistors

International Nuclear Information System (INIS)

McGinnis, D.P.; Beyer, J.B.; Nordman, J.E.

1986-01-01

A wide-band traveling wave amplifier using vortex flow transistors is proposed. A vortex flow transistor is a long Josephson junction used as a current controlled voltage source. The dual nature of this device to the field effect transistor is exploited. A circuit model of this device is proposed and a distributed amplifier utilizing 50 vortex flow transistors is predicted to have useful gain to 100 GHz

Growth of Horizonatal ZnO Nanowire Arrays on Any Substrate

KAUST Repository

Qin, Yong

2008-12-04

A general method is presented for growing laterally aligned and patterned ZnO nanowire (NW) arrays on any substrate as long as it is flat. The orientation control is achieved using the combined effect from ZnO seed layer and the catalytically inactive Cr (or Sn) layer for NW growth. The growth temperature (< 100 °C) is so low that the method can be applied to a wide range of substrates that can be inorganic, organic, single crystal, polycrystal, or amorphous. The laterally aligned ZnO NW arrays can be employed for various applications, such as gas sensor, field effect transistor, nanogenerator, and flexible electronics. © 2008 American Chemical Society.

Gold nanoparticle-pentacene memory-transistors

OpenAIRE

Novembre , Christophe; Guerin , David; Lmimouni , Kamal; Gamrat , Christian; Vuillaume , Dominique

2008-01-01

We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off sta...

Temperature dependent microwave performance of AlGaN/GaN high-electron-mobility transistors on high-resistivity silicon substrate

International Nuclear Information System (INIS)

Arulkumaran, S.; Liu, Z.H.; Ng, G.I.; Cheong, W.C.; Zeng, R.; Bu, J.; Wang, H.; Radhakrishnan, K.; Tan, C.L.

2007-01-01

The influence of temperature (- 50 deg. C to + 200 deg. C) was studied on the DC and microwave characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) on high resistivity Si substrate for the first time. The AlGaN/GaN HEMTs exhibited a current-gain cut-off frequency (f T ) of 11.8 GHz and maximum frequency of oscillation (f max ) of 27.5 GHz. When compared to room temperature values, about 4% and 10% increase in f T and f max and 23% and 39.5% decrease in f T and f max were observed when measured at - 50 deg. C and 200 deg. C, respectively. The improvement of I D , g m f T , and f max at - 50 deg. C is due to the enhancement of 2DEG mobility and effective electron velocity. The anomalous drain current reduction in the I-V curves were observed at low voltage region at the temperature ≤ 10 deg. C but disappeared when the temperature reached ≥ 25 deg. C. A positive threshold voltage (V th ) shift was observed from - 50 deg. C to 200 deg. C. The positive shift of V th is due to the occurrence of trapping effects in the devices. The drain leakage current decreases with activation energies of 0.028 eV and 0.068 eV. This decrease of leakage current with the increase of temperature is due to the shallow acceptor initiated impact ionization

Organic-inorganic field effect transistor with SnI-based perovskite channel layer using vapor phase deposition technique

Science.gov (United States)

Matsushima, Toshinori; Yasuda, Takeshi; Fujita, Katsuhiko; Tsutsui, Tetsuo

2003-11-01

High field-effect hole mobility of (formula available in paper)and threshold voltage is -3.2 V) in organic-inorganic layered perovskite film (formula available in paper)prepared by a vapor phase deposition technique have been demonstrated through the octadecyltrichlorosilane treatment of substrate. Previously, the (formula available in paper)films prepared on the octadecyltrichlorosilane-covered substrates using a vapor evaporation showed not only intense exciton absorption and photoluminescence in the optical spectroscopy but also excellent crystallinity and large grain structure in X-ray and atomic force microscopic studies. Especially, the (formula available in paper)structure in the region below few nm closed to the surface of octadecyltrichlorosilane monolayer was drastically improved in comparison with that on the non-covered substrate. Though our initial (formula available in paper)films via a same sequence of preparation of (formula available in paper)and octadecyltrichlorosilane monolayer did not show the field-effect properties because of a lack of spectral, structural, and morphological features. The unformation of favorable (formula available in paper)structure in the very thin region, that is very important for the field-effect transistors to transport electrons or holes, closed to the surface of non-covered (formula available in paper)dielectric layer was also one of the problems for no observation of them. By adding further optimization and development, such as deposition rate of perovskite, substrate heating during deposition, and tuning device architecture, with hydrophobic treatment, the vacuum-deposited (formula available in paper)have achieved above-described high performance in organic-inorganic hybrid transistors.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

Science.gov (United States)

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

The Complete Semiconductor Transistor and Its Incomplete Forms

International Nuclear Information System (INIS)

Jie Binbin; Sah, C.-T.

2009-01-01

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

A Fast Dynamic 64-bit Comparator with Small Transistor Count

Directory of Open Access Journals (Sweden)

Chua-Chin Wang

2002-01-01

Full Text Available In this paper, we propose a 64-bit fast dynamic CMOS comparator with small transistor count. Major features of the proposed comparator are the rearrangement and re-ordering of transistors in the evaluation block of a dynamic cell, and the insertion of a weak n feedback inverter, which helps the pull-down operation to ground. The simulation results given by pre-layout tools, e.g. HSPICE, and post-layout tools, e.g. TimeMill, reveal that the delay is around 2.5 ns while the operating clock rate reaches 100 MHz. A physical chip is fabricated to verify the correctness of our design by using UMC (United Microelectronics Company 0.5 μm (2P2M technology.

Enhanced lateral heat dissipation packaging structure for GaN HEMTs on Si substrate

International Nuclear Information System (INIS)

Cheng, Stone; Chou, Po-Chien; Chieng, Wei-Hua; Chang, E.Y.

2013-01-01

This work presents a technology for packaging AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate. The GaN HEMTs are attached to a V-groove copper base and mounted on a TO-3P leadframe. The various thermal paths from the GaN gate junction to the case are carried out for heat dissipation by spreading to protective coating; transferring through the bond wires; spreading in the lateral device structure through the adhesive layer, and vertical heat spreading of silicon chip bottom. Thermal characterization showed a thermal resistance of 13.72 °C/W from the device to the TO-3P package. Experimental tests of a 30 mm gate-periphery single chip packaged in a 5 × 3 mm V-groove Cu base with a 100 V drain bias showed power dissipation of 22 W. -- Highlights: ► An enhanced packaging structure designed for AlGaN/GaN HEMTs on an Si substrate. ► The V-groove copper base is designed on the device periphery surface heat conduction for enhancing Si substrate thermal dissipation. ► The proposed device shows a lower thermal resistance and upgrade in thermal conductivity capability. ► This work provides useful thermal IR imagery information to aid in designing high efficiency package for GaN HEMTs on Si

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

Science.gov (United States)

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array.

Science.gov (United States)

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B-H; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable-like human skin-would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array

Science.gov (United States)

Wang, Sihong; Xu, Jie; Wang, Weichen; Wang, Ging-Ji Nathan; Rastak, Reza; Molina-Lopez, Francisco; Chung, Jong Won; Niu, Simiao; Feig, Vivian R.; Lopez, Jeffery; Lei, Ting; Kwon, Soon-Ki; Kim, Yeongin; Foudeh, Amir M.; Ehrlich, Anatol; Gasperini, Andrea; Yun, Youngjun; Murmann, Boris; Tok, Jeffery B.-H.; Bao, Zhenan

2018-03-01

Skin-like electronics that can adhere seamlessly to human skin or within the body are highly desirable for applications such as health monitoring, medical treatment, medical implants and biological studies, and for technologies that include human-machine interfaces, soft robotics and augmented reality. Rendering such electronics soft and stretchable—like human skin—would make them more comfortable to wear, and, through increased contact area, would greatly enhance the fidelity of signals acquired from the skin. Structural engineering of rigid inorganic and organic devices has enabled circuit-level stretchability, but this requires sophisticated fabrication techniques and usually suffers from reduced densities of devices within an array. We reasoned that the desired parameters, such as higher mechanical deformability and robustness, improved skin compatibility and higher device density, could be provided by using intrinsically stretchable polymer materials instead. However, the production of intrinsically stretchable materials and devices is still largely in its infancy: such materials have been reported, but functional, intrinsically stretchable electronics have yet to be demonstrated owing to the lack of a scalable fabrication technology. Here we describe a fabrication process that enables high yield and uniformity from a variety of intrinsically stretchable electronic polymers. We demonstrate an intrinsically stretchable polymer transistor array with an unprecedented device density of 347 transistors per square centimetre. The transistors have an average charge-carrier mobility comparable to that of amorphous silicon, varying only slightly (within one order of magnitude) when subjected to 100 per cent strain for 1,000 cycles, without current-voltage hysteresis. Our transistor arrays thus constitute intrinsically stretchable skin electronics, and include an active matrix for sensory arrays, as well as analogue and digital circuit elements. Our process offers a

State-of-the-art technologies of gallium oxide power devices

Science.gov (United States)

Higashiwaki, Masataka; Kuramata, Akito; Murakami, Hisashi; Kumagai, Yoshinao

2017-08-01

Gallium oxide (Ga2 O3 ) has gained increased attention for power devices due to its superior material properties and the availability of economical device-quality native substrates. This review illustrates recent advances in Ga2 O3 device technologies, beginning with an overview of the social circumstances that motivate the development of new-generation switching devices. Following an introduction to the material properties of Ga2 O3 from the viewpoint of power electronics, growth technologies of Ga2 O3 bulk single crystals and epitaxial thin films are discussed. The fabrication and performance of state-of-the-art Ga2 O3 transistors and diodes are then described. We conclude by identifying the directions and challenges of Ga2 O3 power device development in the near future.

Heterogeneous Integration Technology

Science.gov (United States)

2017-05-19

integrated CMOS imaging system for high frame rate applications [171]. .................... 68 Figure 83: CPU-DRAM Memory Landscape . [127... film transistors (TFT) were integrated with GaN HEMTs on the same wafer at AFRL. The thin film transistor fabrication using metal-oxide...second layer. Layer transfer produces the best quality devices compared to other additive technologies such as re-crystallization of thin films [148

Wafer-scale laser pantography: Fabrication of n-metal-oxide-semiconductor transistors and small-scale integrated circuits by direct-write laser-induced pyrolytic reactions

International Nuclear Information System (INIS)

McWilliams, B.M.; Herman, I.P.; Mitlitsky, F.; Hyde, R.A.; Wood, L.L.

1983-01-01

A complete set of processes sufficient for manufacture of n-metal-oxide-semiconductor (n-MOS) transistors by a laser-induced direct-write process has been demonstrated separately, and integrated to yield functional transistors. Gates and interconnects were fabricated of various combinations of n-doped and intrinsic polysilicon, tungsten, and tungsten silicide compounds. Both 0.1-μm and 1-μm-thick gate oxides were micromachined with and without etchant gas, and the exposed p-Si [100] substrate was cleaned and, at times, etched. Diffusion regions were doped by laser-induced pyrolytic decomposition of phosphine followed by laser annealing. Along with the successful manufacture of working n-MOS transistors and a set of elementary digital logic gates, this letter reports the successful use of several laser-induced surface reactions that have not been reported previously

Improved Performance of Fluorinated Copper Phthalocyanine Thin Film Transistors Using Para-hexaphenyl as the Inducing Layer

International Nuclear Information System (INIS)

Ma Feng; Wang Shi-Rong; Li Xiang-Gao; Yan Dong-Hang

2011-01-01

We demonstrate n-type organic thin film transistors (OTFTs) employing copper hexadecafluorophthalocyanine (CuPcF 16 ) as the active layer and para-hexaphenyl (p-6p) as the inducing layer. Compared with the CuPcF 16 -based OTFTs without the p-6p inducing layer, the performance of the CuPcF 16 /p-6p OTFTs is greatly improved. The charge carrier field-effect mobility μ, on-off current ratio I on /I off and threshold voltage V T of the CuPcF 16 /p-6p OTFTs are 0.07 cm 2 /V·s, 1.61 × 10 5 and 6.28 V, respectively, approaching the level of a single crystal device. The improved performance is attributed to the introduction of p-6p to form a highly oriented and continuous film of CuPcF 16 with the molecular π-π stack direction parallel to the substrate. (cross-disciplinary physics and related areas of science and technology)

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

Science.gov (United States)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

MOVPE and characterization of GaN-based structures on alternative substrates

Energy Technology Data Exchange (ETDEWEB)

Dikme, Y.

2006-06-20

This study involves growth experiments of GaN-based layer structures on silicon (Si), lithium aluminate (LiAlO{sub 2}) and the composite substrate SiCOI. Substrate specific preparation and growth procedures were developed. Because of the different lattice constants and thermal expansion coefficients between GaN and the substrate materials and because of the high depositions temperatures (>1000 C) complex interlayers are required to create a crossover from the substrate to the GaN layer and to prevent substrate/layer bowing and cracks developing in the epitaxial layers. Crystallographic, thermal and electronic properties of these materials were investigated and the developed layers were used as buffer layers for electronic and opto electronic devices. On Si AlN/GaN distributed Bragg reflectors (DBR), InGaN/GaN multiple quantum well (MQW) and AlGaN/GaN HEMT (high electron mobility transistor) were demonstrated. The transistor structures showed high power densities, which were comparable to industrially fabricated devices. As well as the reflection of a certain wavelength region, the DBR layers additionally showed positive influence on succeeding GaN top layer optical properties. For the first time laser emission of an optically pumped InGaN/GaN MQW on Si was demonstrated with low excitation density and a high operating temperature. GaN-based structures were deposited on LiAlO2 in the m-plane crystal orientation; that do not exhibit polarization mechanisms in growth direction. For the deposition of coalesced GaN films a seal-coating of the LiAlO{sub 2} surface was developed and finally LED structures were grown on these substrates. For the first time electroluminescence of LED structures on LiAlO{sub 2} was achieved. The growth on the composite substrate SiCOI was initiated with an HT AlN layer and it was demonstrated that SiCOI is comparable to a bulk SiC substrate for the GaN-based epitaxy. The developed and investigated layer structure served as buffer for the

Biomolecular detection using a metal semiconductor field effect transistor

Science.gov (United States)

Estephan, Elias; Saab, Marie-Belle; Buzatu, Petre; Aulombard, Roger; Cuisinier, Frédéric J. G.; Gergely, Csilla; Cloitre, Thierry

2010-04-01

In this work, our attention was drawn towards developing affinity-based electrical biosensors, using a MESFET (Metal Semiconductor Field Effect Transistor). Semiconductor (SC) surfaces must be prepared before the incubations with biomolecules. The peptides route was adapted to exceed and bypass the limits revealed by other types of surface modification due to the unwanted unspecific interactions. As these peptides reveal specific recognition of materials, then controlled functionalization can be achieved. Peptides were produced by phage display technology using a library of M13 bacteriophage. After several rounds of bio-panning, the phages presenting affinities for GaAs SC were isolated; the DNA of these specific phages were sequenced, and the peptide with the highest affinity was synthesized and biotinylated. To explore the possibility of electrical detection, the MESFET fabricated with the GaAs SC were used to detect the streptavidin via the biotinylated peptide in the presence of the bovine Serum Albumin. After each surface modification step, the IDS (current between the drain and the source) of the transistor was measured and a decrease in the intensity was detected. Furthermore, fluorescent microscopy was used in order to prove the specificity of this peptide and the specific localisation of biomolecules. In conclusion, the feasibility of producing an electrical biosensor using a MESFET has been demonstrated. Controlled placement, specific localization and detection of biomolecules on a MESFET transistor were achieved without covering the drain and the source. This method of functionalization and detection can be of great utility for biosensing application opening a new way for developing bioFETs (Biomolecular Field-Effect Transistor).

Using white noise to gate organic transistors for dynamic monitoring of cultured cell layers.

Science.gov (United States)

Rivnay, Jonathan; Leleux, Pierre; Hama, Adel; Ramuz, Marc; Huerta, Miriam; Malliaras, George G; Owens, Roisin M

2015-06-26

Impedance sensing of biological systems allows for monitoring of cell and tissue properties, including cell-substrate attachment, layer confluence, and the "tightness" of an epithelial tissue. These properties are critical for electrical detection of tissue health and viability in applications such as toxicological screening. Organic transistors based on conducting polymers offer a promising route to efficiently transduce ionic currents to attain high quality impedance spectra, but collection of complete impedance spectra can be time consuming (minutes). By applying uniform white noise at the gate of an organic electrochemical transistor (OECT), and measuring the resulting current noise, we are able to dynamically monitor the impedance and thus integrity of cultured epithelial monolayers. We show that noise sourcing can be used to track rapid monolayer disruption due to compounds which interfere with dynamic polymerization events crucial for maintaining cytoskeletal integrity, and to resolve sub-second alterations to the monolayer integrity.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene-graphene composite layers for flexible thin film transistors with a polymer gate dielectric.

Science.gov (United States)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-02-28

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene-graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene-graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm(2) V(-1) s(-1) and a threshold voltage of -0.7 V at V(gs) = -40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm(2) V(-1) s(-1) and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies.

Laser printed organic semiconductor PQT-12 for bottom-gate organic thin-film transistors: Fabrication and characterization

Energy Technology Data Exchange (ETDEWEB)

Makrygianni, M. [National Technical University of Athens, Physics Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); National Technical University of Athens, Electrical and Computer Engineering Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); Ainsebaa, A. [Ecole Nationale Supérieure des Mines de Saint-Etienne, Department of Flexible Electronics, CMP-EMSE, MOC, 13541 Gardanne (France); Nagel, M. [EMPA Swiss Federal Lab. for Materials Science and Technology, Laboratory for Functional Polymers, Überlandstrasse 129, 8600 Dubendorf (Switzerland); Sanaur, S. [Ecole Nationale Supérieure des Mines de Saint-Etienne, Department of Flexible Electronics, CMP-EMSE, MOC, 13541 Gardanne (France); Raptis, Y.S. [National Technical University of Athens, Physics Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); Zergioti, I., E-mail: zergioti@central.ntua.gr [National Technical University of Athens, Physics Department, Iroon Polytehneiou 9, 15780 Zografou (Greece); Tsamakis, D. [National Technical University of Athens, Electrical and Computer Engineering Department, Iroon Polytehneiou 9, 15780 Zografou (Greece)

2016-12-30

Highlights: • Smooth printing of semiconducting π-conjugated polymer patterns for BG-BC OTFTs. • Well-ordering of PQT-12 when diluted in a high-boiling-point solvent yielding good interface properties. • No significant change in polymer chain orientation observed between LIFT printed patterns. • Reliable solid phase printing technique for thin, organic large area electronics applications, in a well-defined manner. - Abstract: In this work, we report on the effect of laser printed Poly (3,3‴-didodecyl quarter thiophene) on its optical, structural and electrical properties for bottom-gate/bottom-contact organic thin-film transistors applications. This semiconducting π-conjugated polymer was solution-deposited (spin-coated) on a donor substrate and transferred by means of solid phase laser-induced forward transfer (LIFT) technique on SiO{sub 2}/Si receiver substrates to form the active material. This article presents a detailed study of the electrical properties of the fabricated transistors by measuring the parasitic resistances for gold (Au) and platinum (Pt) as source-drain electrodes, for optimizing OTFTs in terms of contacts. In addition, X-ray diffraction patterns revealed that it is possible to control the polymer microstructure through the choice of solvent. Also, no significant change in polymer chain orientation was observed between two printed patterns at 90 and 130 mJ/cm{sup 2} as confirmed by Raman spectra. The results demonstrate hole mobility values of (2.6 ± 1.3) × 10{sup −2} cm{sup 2}/Vs, and lower parasitic resistance for dielectric surface roughness around 1.2 nm and Pt electrodes. Higher performances are correlated to i) the well-ordering of PQT-12 surface when a high-boiling-point solvent is used and ii) the less limitating Pt source/drain electrodes. This analytical study proves that solid phase LIFT printing is a reliable technology for the fabrication of thin, organic large area electronics in a well-defined manner.

Laser printed organic semiconductor PQT-12 for bottom-gate organic thin-film transistors: Fabrication and characterization

International Nuclear Information System (INIS)

Makrygianni, M.; Ainsebaa, A.; Nagel, M.; Sanaur, S.; Raptis, Y.S.; Zergioti, I.; Tsamakis, D.

2016-01-01

Highlights: • Smooth printing of semiconducting π-conjugated polymer patterns for BG-BC OTFTs. • Well-ordering of PQT-12 when diluted in a high-boiling-point solvent yielding good interface properties. • No significant change in polymer chain orientation observed between LIFT printed patterns. • Reliable solid phase printing technique for thin, organic large area electronics applications, in a well-defined manner. - Abstract: In this work, we report on the effect of laser printed Poly (3,3‴-didodecyl quarter thiophene) on its optical, structural and electrical properties for bottom-gate/bottom-contact organic thin-film transistors applications. This semiconducting π-conjugated polymer was solution-deposited (spin-coated) on a donor substrate and transferred by means of solid phase laser-induced forward transfer (LIFT) technique on SiO_2/Si receiver substrates to form the active material. This article presents a detailed study of the electrical properties of the fabricated transistors by measuring the parasitic resistances for gold (Au) and platinum (Pt) as source-drain electrodes, for optimizing OTFTs in terms of contacts. In addition, X-ray diffraction patterns revealed that it is possible to control the polymer microstructure through the choice of solvent. Also, no significant change in polymer chain orientation was observed between two printed patterns at 90 and 130 mJ/cm"2 as confirmed by Raman spectra. The results demonstrate hole mobility values of (2.6 ± 1.3) × 10"−"2 cm"2/Vs, and lower parasitic resistance for dielectric surface roughness around 1.2 nm and Pt electrodes. Higher performances are correlated to i) the well-ordering of PQT-12 surface when a high-boiling-point solvent is used and ii) the less limitating Pt source/drain electrodes. This analytical study proves that solid phase LIFT printing is a reliable technology for the fabrication of thin, organic large area electronics in a well-defined manner.

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-07-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications.

High transconductance organic electrochemical transistors

Science.gov (United States)

Khodagholy, Dion; Rivnay, Jonathan; Sessolo, Michele; Gurfinkel, Moshe; Leleux, Pierre; Jimison, Leslie H.; Stavrinidou, Eleni; Herve, Thierry; Sanaur, Sébastien; Owens, Róisín M.; Malliaras, George G.

2013-01-01

The development of transistors with high gain is essential for applications ranging from switching elements and drivers to transducers for chemical and biological sensing. Organic transistors have become well-established based on their distinct advantages, including ease of fabrication, synthetic freedom for chemical functionalization, and the ability to take on unique form factors. These devices, however, are largely viewed as belonging to the low-end of the performance spectrum. Here we present organic electrochemical transistors with a transconductance in the mS range, outperforming transistors from both traditional and emerging semiconductors. The transconductance of these devices remains fairly constant from DC up to a frequency of the order of 1 kHz, a value determined by the process of ion transport between the electrolyte and the channel. These devices, which continue to work even after being crumpled, are predicted to be highly relevant as transducers in biosensing applications. PMID:23851620

Recent progress in photoactive organic field-effect transistors.

Science.gov (United States)

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-04-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts.

Recent progress in photoactive organic field-effect transistors

International Nuclear Information System (INIS)

Wakayama, Yutaka; Hayakawa, Ryoma; Seo, Hoon-Seok

2014-01-01

Recent progress in photoactive organic field-effect transistors (OFETs) is reviewed. Photoactive OFETs are divided into light-emitting (LE) and light-receiving (LR) OFETs. In the first part, LE-OFETs are reviewed from the viewpoint of the evolution of device structures. Device performances have improved in the last decade with the evolution of device structures from single-layer unipolar to multi-layer ambipolar transistors. In the second part, various kinds of LR-OFETs are featured. These are categorized according to their functionalities: phototransistors, non-volatile optical memories, and photochromism-based transistors. For both, various device configurations are introduced: thin-film based transistors for practical applications, single-crystalline transistors to investigate fundamental physics, nanowires, multi-layers, and vertical transistors based on new concepts. (review)

All-inkjet-printed flexible electronics fabrication on a polymer substrate by low-temperature high-resolution selective laser sintering of metal nanoparticles

International Nuclear Information System (INIS)

Ko, Seung H; Pan Heng; Grigoropoulos, Costas P; Luscombe, Christine K; Frechet, Jean M J; Poulikakos, Dimos

2007-01-01

All-printed electronics is the key technology to ultra-low-cost, large-area electronics. As a critical step in this direction, we demonstrate that laser sintering of inkjet-printed metal nanoparticles enables low-temperature metal deposition as well as high-resolution patterning to overcome the resolution limitation of the current inkjet direct writing processes. To demonstrate this process combined with the implementation of air-stable carboxylate-functionalized polythiophenes, high-resolution organic transistors were fabricated in ambient pressure and room temperature without utilizing any photolithographic steps or requiring a vacuum deposition process. Local thermal control of the laser sintering process could minimize the heat-affected zone and the thermal damage to the substrate and further enhance the resolution of the process. This local nanoparticle deposition and energy coupling enable an environmentally friendly and cost-effective process as well as a low-temperature manufacturing sequence to realize large-area, flexible electronics on polymer substrates

Programmable automated transistor test system

International Nuclear Information System (INIS)

Truong, L.V.; Sundberg, G.R.

1986-01-01

The paper describes a programmable automated transistor test system (PATTS) and its utilization to evaluate bipolar transistors and Darlingtons, and such MOSFET and special types as can be accommodated with the PATTS base-drive. An application of a pulsed power technique at low duty cycles in a non-destructive test is used to examine the dynamic switching characteristic curves of power transistors. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software. In addition a library of test data is established on disks, tapes, and hard copies for future reference

Integrated Microfluidic Membrane Transistor Utilizing Chemical Information for On-Chip Flow Control

Science.gov (United States)

Frank, Philipp; Schreiter, Joerg; Haefner, Sebastian; Paschew, Georgi; Voigt, Andreas; Richter, Andreas

2016-01-01

Microfluidics is a great enabling technology for biology, biotechnology, chemistry and general life sciences. Despite many promising predictions of its progress, microfluidics has not reached its full potential yet. To unleash this potential, we propose the use of intrinsically active hydrogels, which work as sensors and actuators at the same time, in microfluidic channel networks. These materials transfer a chemical input signal such as a substance concentration into a mechanical output. This way chemical information is processed and analyzed on the spot without the need for an external control unit. Inspired by the development electronics, our approach focuses on the development of single transistor-like components, which have the potential to be used in an integrated circuit technology. Here, we present membrane isolated chemical volume phase transition transistor (MIS-CVPT). The device is characterized in terms of the flow rate from source to drain, depending on the chemical concentration in the control channel, the source-drain pressure drop and the operating temperature. PMID:27571209

Integrated Microfluidic Membrane Transistor Utilizing Chemical Information for On-Chip Flow Control.

Science.gov (United States)

Frank, Philipp; Schreiter, Joerg; Haefner, Sebastian; Paschew, Georgi; Voigt, Andreas; Richter, Andreas

2016-01-01

Microfluidics is a great enabling technology for biology, biotechnology, chemistry and general life sciences. Despite many promising predictions of its progress, microfluidics has not reached its full potential yet. To unleash this potential, we propose the use of intrinsically active hydrogels, which work as sensors and actuators at the same time, in microfluidic channel networks. These materials transfer a chemical input signal such as a substance concentration into a mechanical output. This way chemical information is processed and analyzed on the spot without the need for an external control unit. Inspired by the development electronics, our approach focuses on the development of single transistor-like components, which have the potential to be used in an integrated circuit technology. Here, we present membrane isolated chemical volume phase transition transistor (MIS-CVPT). The device is characterized in terms of the flow rate from source to drain, depending on the chemical concentration in the control channel, the source-drain pressure drop and the operating temperature.

Single ZnO nanowire-PZT optothermal field effect transistors.

Science.gov (United States)

Hsieh, Chun-Yi; Lu, Meng-Lin; Chen, Ju-Ying; Chen, Yung-Ting; Chen, Yang-Fang; Shih, Wan Y; Shih, Wei-Heng

2012-09-07

A new type of pyroelectric field effect transistor based on a composite consisting of single zinc oxide nanowire and lead zirconate titanate (ZnO NW-PZT) has been developed. Under infrared (IR) laser illumination, the transconductance of the ZnO NW can be modulated by optothermal gating. The drain current can be increased or decreased by IR illumination depending on the polarization orientation of the Pb(Zr(0.3)Ti(0.7))O(3) (PZT) substrate. Furthermore, by combining the photocurrent behavior in the UV range and the optothermal gating effect in the IR range, the wide spectrum of response of current by light offers a variety of opportunities for nanoscale optoelectronic devices.

Vertical field effect tunneling transistor based on graphene-ultrathin Si nanomembrane heterostructures

Science.gov (United States)

Das, Tanmoy; Jang, Houk; Bok Lee, Jae; Chu, Hyunwoo; Kim, Seong Dae; Ahn, Jong-Hyun

2015-12-01

Graphene-based heterostructured vertical transistors have attracted a great deal of research interest. Herein we propose a Si-based technology platform for creating graphene/ultrathin semiconductor/metal (GSM) junctions, which can be applied to large-scale and low-power electronics compatible with a variety of substrates. We fabricated graphene/Si nanomembrane (NM)/metal vertical heterostructures by using a dry transfer technique to transfer Si NMs onto chemical vapor deposition-grown graphene layers. The resulting van der Waals interfaces between graphene and p-Si NMs exhibited nearly ideal Schottky barrier behavior. Due to the low density of states of graphene, the graphene/Si NM Schottky barrier height can be modulated by modulating the band profile in the channel region, yielding well-defined current modulation. We obtained a maximum current on/off ratio (Ion/Ioff) of up to ˜103, with a current density of 102 A cm-2. We also observed significant dependence of Schottky barrier height Δφb on the thickness of the Si NMs. We confirmed that the transport in these devices is dominated by the effects of the graphene/Si NM Schottky barrier.

Vertical field effect tunneling transistor based on graphene-ultrathin Si nanomembrane heterostructures

International Nuclear Information System (INIS)

Das, Tanmoy; Jang, Houk; Bok Lee, Jae; Chu, Hyunwoo; Dae Kim, Seong; Ahn, Jong-Hyun

2015-01-01

Graphene-based heterostructured vertical transistors have attracted a great deal of research interest. Herein we propose a Si-based technology platform for creating graphene/ultrathin semiconductor/metal (GSM) junctions, which can be applied to large-scale and low-power electronics compatible with a variety of substrates. We fabricated graphene/Si nanomembrane (NM)/metal vertical heterostructures by using a dry transfer technique to transfer Si NMs onto chemical vapor deposition-grown graphene layers. The resulting van der Waals interfaces between graphene and p-Si NMs exhibited nearly ideal Schottky barrier behavior. Due to the low density of states of graphene, the graphene/Si NM Schottky barrier height can be modulated by modulating the band profile in the channel region, yielding well-defined current modulation. We obtained a maximum current on/off ratio (I on /I off ) of up to ∼10 3 , with a current density of 10 2 A cm −2 . We also observed significant dependence of Schottky barrier height Δφ b on the thickness of the Si NMs. We confirmed that the transport in these devices is dominated by the effects of the graphene/Si NM Schottky barrier. (paper)

Physical studies of strained Si/SiGe heterostructures. From virtual substrates to nanodevices

Energy Technology Data Exchange (ETDEWEB)

Minamisawa, Renato Amaral

2011-10-21

During the past two decades, the decrease in intrinsic delay of MOSFETs has been driven by the scaling of the device dimensions. The performance improvement has relied mostly in the increase of source velocity with gate scaling, while the transport properties of the channel have remained constant, i.e., those of conventional Si. Starting at the 90 nm node, uniaxial strain has been introduced in the transistor channel in order to further increase the source velocity. Beyond the 32 nm node, novel channel materials, with superior carrier velocities, and novel device architectures are required in order to continue the performance enhancement of MOSFETs while preserving the electrostatic control. In this Thesis, different physical aspects of strained Si and SiGe materials are investigated as a mean to increase carrier velocity in MOSFET channels. Novel approaches for the fabrication of strained Si based on ion implantation and anneal induced relaxation of virtual substrates are developed. The strain relaxation of SiGe layers is improved using a buried thin Si:C layer in the Si(100) substrate. Further, a Si{sup +} ion implantation and annealing method is investigated for relaxing virtual substrates using lower implantation dose. Finally, the uniaxial relaxation of {l_brace}110{r_brace} surface oriented substrates is demonstrated using a He ion implantation and anneal technique. Apart of channel material studies, the fundamental and technological challenges involved in the integration of strained Si and SiGe into MOSFETs are assessed. The impact of source and drain formation on the elastic strain and electrical properties of strained Si layers and nanowires is examined. Also, the formation of ultra-shallow junction in strained Si/strained Si{sub 0.5}Ge{sub 0.5}/SSOI heterostructures is investigated using different types of ion implanted specie and annealing. The results show that BF{sup +}{sub 2} implantation and low temperature annealing are suitable approaches for

Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

International Nuclear Information System (INIS)

Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

2015-01-01

Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Universal power transistor base drive control unit

Science.gov (United States)

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Mesoscale control of organic crystalline thin films: effects of film morphology on the performance of organic transistors

Energy Technology Data Exchange (ETDEWEB)

Kim, Jaekyun; Park, Sungkyu [Chung-Ang University, Seoul (Korea, Republic of); Kim, Yonghoon [Sungkyunkwan University, Suwon (Korea, Republic of)

2014-08-15

We report mesoscale control of small molecular 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) crystalline thin films by varying the solute concentration in the fluidic channel method. A stepwise increase in the TIPS-pentacene concentration in the solution enabled us to prepare highly-crystallized ribbons, thin films, and thick films in a mesoscale range, respectively. All three types of deposited films exhibited an in-plane crystalline nature of (001) direction being normal to the substrate as well as crystalline domain growth parallel to the direction of the receding meniscus inside the fluidic channel. In addition, the film's morphology and thickness were found to have a great influence on the field-effect mobility of the transistors, and the highest average and maximum mobilities were achieved from transistors with thin-film semiconductor channels.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

Monolithic integration of detectors and transistors on high-resistivity silicon

International Nuclear Information System (INIS)

Dalla Betta, Gian-Franco; Batignani, Giovanni; Boscardin, Maurizio; Bosisio, Luciano; Gregori, Paolo; Pancheri, Lucio; Piemonte, Claudio; Ratti, Lodovico; Verzellesi, Giovanni; Zorzi, Nicola

2007-01-01

We report on the most recent results from an R and D activity aimed at the development of silicon radiation detectors with embedded front-end electronics. The key features of the fabrication technology and the available active devices are described. Selected results from the characterization of transistors and test structures are presented and discussed, and the considered application fields are addressed

Lg = 100 nm T-shaped gate AlGaN/GaN HEMTs on Si substrates with non-planar source/drain regrowth of highly-doped n+-GaN layer by MOCVD

International Nuclear Information System (INIS)

Huang Jie; Li Ming; Tang Chak-Wah; Lau Kei-May

2014-01-01

High-performance AlGaN/GaN high electron mobility transistors (HEMTs) grown on silicon substrates by metal—organic chemical-vapor deposition (MOCVD) with a selective non-planar n-type GaN source/drain (S/D) regrowth are reported. A device exhibited a non-alloyed Ohmic contact resistance of 0.209 Ω·mm and a comprehensive transconductance (g m ) of 247 mS/mm. The current gain cutoff frequency f T and maximum oscillation frequency f MAX of 100-nm HEMT with S/D regrowth were measured to be 65 GHz and 69 GHz. Compared with those of the standard GaN HEMT on silicon substrate, the f T and f MAX is 50% and 52% higher, respectively. (interdisciplinary physics and related areas of science and technology)

Low-background transistors for application in nuclear electronics

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

Investigations of silicon transistors were carried out to determine transistors with low value of base distributed resistance (R). Measurement results for R and current amplification coefficient β are presented for bipolar transistor several types. Correlations between R and β were studied. KT 399A, 2T640A and KT3117B transistors are found to be most adequate ones as a base for low-background amplifier development

Flexible Metal Oxide/Graphene Oxide Hybrid Neuromorphic Devices on Flexible Conducting Graphene Substrates

OpenAIRE

Wan, Chang Jin; Wang, Wei; Zhu, Li Qiang; Liu, Yang Hui; Feng, Ping; Liu, Zhao Ping; Shi, Yi; Wan, Qing

2016-01-01

Flexible metal oxide/graphene oxide hybrid multi-gate neuron transistors were fabricated on flexible graphene substrates. Dendritic integrations in both spatial and temporal modes were successfully emulated, and spatiotemporal correlated logics were obtained. A proof-of-principle visual system model for emulating lobula giant motion detector neuron was investigated. Our results are of great interest for flexible neuromorphic cognitive systems.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon

KAUST Repository

Lin, Che-Yu

2017-10-04

High-frequency operation with ultra-thin, lightweight and extremely flexible semiconducting electronics are highly desirable for the development of mobile devices, wearable electronic systems and defense technologies. In this work, the first experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density and flexible electronics.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon

KAUST Repository

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Li, Ming-Yang; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L.; Lan, Yann-Wen

2017-01-01

High-frequency operation with ultra-thin, lightweight and extremely flexible semiconducting electronics are highly desirable for the development of mobile devices, wearable electronic systems and defense technologies. In this work, the first experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe2-MoS2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density and flexible electronics.

Atomic-Monolayer Two-Dimensional Lateral Quasi-Heterojunction Bipolar Transistors with Resonant Tunneling Phenomenon.

Science.gov (United States)

Lin, Che-Yu; Zhu, Xiaodan; Tsai, Shin-Hung; Tsai, Shiao-Po; Lei, Sidong; Shi, Yumeng; Li, Lain-Jong; Huang, Shyh-Jer; Wu, Wen-Fa; Yeh, Wen-Kuan; Su, Yan-Kuin; Wang, Kang L; Lan, Yann-Wen

2017-11-28

High-frequency operation with ultrathin, lightweight, and extremely flexible semiconducting electronics is highly desirable for the development of mobile devices, wearable electronic systems, and defense technologies. In this work, the experimental observation of quasi-heterojunction bipolar transistors utilizing a monolayer of the lateral WSe 2 -MoS 2 junctions as the conducting p-n channel is demonstrated. Both lateral n-p-n and p-n-p heterojunction bipolar transistors are fabricated to exhibit the output characteristics and current gain. A maximum common-emitter current gain of around 3 is obtained in our prototype two-dimensional quasi-heterojunction bipolar transistors. Interestingly, we also observe the negative differential resistance in the electrical characteristics. A potential mechanism is that the negative differential resistance is induced by resonant tunneling phenomenon due to the formation of quantum well under applying high bias voltages. Our results open the door to two-dimensional materials for high-frequency, high-speed, high-density, and flexible electronics.

On-Chip Chemical Self-Assembly of Semiconducting Single-Walled Carbon Nanotubes (SWNTs): Toward Robust and Scale Invariant SWNTs Transistors.

Science.gov (United States)

Derenskyi, Vladimir; Gomulya, Widianta; Talsma, Wytse; Salazar-Rios, Jorge Mario; Fritsch, Martin; Nirmalraj, Peter; Riel, Heike; Allard, Sybille; Scherf, Ullrich; Loi, Maria A

2017-06-01

In this paper, the fabrication of carbon nanotubes field effect transistors by chemical self-assembly of semiconducting single walled carbon nanotubes (s-SWNTs) on prepatterned substrates is demonstrated. Polyfluorenes derivatives have been demonstrated to be effective in selecting s-SWNTs from raw mixtures. In this work the authors functionalized the polymer with side chains containing thiols, to obtain chemical self-assembly of the selected s-SWNTs on substrates with prepatterned gold electrodes. The authors show that the full side functionalization of the conjugated polymer with thiol groups partially disrupts the s-SWNTs selection, with the presence of metallic tubes in the dispersion. However, the authors determine that the selectivity can be recovered either by tuning the number of thiol groups in the polymer, or by modulating the polymer/SWNTs proportions. As demonstrated by optical and electrical measurements, the polymer containing 2.5% of thiol groups gives the best s-SWNT purity. Field-effect transistors with various channel lengths, using networks of SWNTs and individual tubes, are fabricated by direct chemical self-assembly of the SWNTs/thiolated-polyfluorenes on substrates with lithographically defined electrodes. The network devices show superior performance (mobility up to 24 cm 2 V -1 s -1 ), while SWNTs devices based on individual tubes show an unprecedented (100%) yield for working devices. Importantly, the SWNTs assembled by mean of the thiol groups are stably anchored to the substrate and are resistant to external perturbation as sonication in organic solvents. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Area and energy efficient high-performance ZnO wavy channel thin-film transistor

KAUST Repository

Hanna, Amir

2014-09-01

Increased output current while maintaining low power consumption in thin-film transistors (TFTs) is essential for future generation large-area high-resolution displays. Here, we show wavy channel (WC) architecture in TFT that allows the expansion of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased performance while maintaining the real estate integrity. The experimental WCTFTs show a linear increase in output current as a function of number of fins per device resulting in (3.5×) increase in output current when compared with planar counterparts that consume the same chip area. The new architecture also allows tuning the threshold voltage as a function of the number of fin features included in the device, as threshold voltage linearly decreased from 6.8 V for planar device to 2.6 V for WC devices with 32 fins. This makes the new architecture more power efficient as lower operation voltages could be used for WC devices compared with planar counterparts. It was also found that field effect mobility linearly increases with the number of fins included in the device, showing almost \\\\(1.8×) enhancements in the field effect mobility than that of the planar counterparts. This can be attributed to higher electric field in the channel due to the fin architecture and threshold voltage shift. © 2014 IEEE.

Wavy channel Thin Film Transistor for area efficient, high performance and low power applications

KAUST Repository

Hanna, Amir

2014-06-01

We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.4x increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, similar to 100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers a pragmatic opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications without any limitation any TFT materials.

Selective-area growth and controlled substrate coupling of transition metal dichalcogenides

Science.gov (United States)

Bersch, Brian M.; Eichfeld, Sarah M.; Lin, Yu-Chuan; Zhang, Kehao; Bhimanapati, Ganesh R.; Piasecki, Aleksander F.; Labella, Michael, III; Robinson, Joshua A.

2017-06-01

Developing a means for true bottom-up, selective-area growth of two-dimensional (2D) materials on device-ready substrates will enable synthesis in regions only where they are needed. Here, we demonstrate seed-free, site-specific nucleation of transition metal dichalcogenides (TMDs) with precise control over lateral growth by utilizing an ultra-thin polymeric surface functionalization capable of precluding nucleation and growth. This polymer functional layer (PFL) is derived from conventional photoresists and lithographic processing, and is compatible with multiple growth techniques, precursors (metal organics, solid-source) and TMDs. Additionally, we demonstrate that the substrate can play a major role in TMD transport properties. With proper TMD/substrate decoupling, top-gated field-effect transistors (FETs) fabricated with selectively-grown monolayer MoS2 channels are competitive with current reported MoS2 FETs. The work presented here demonstrates that substrate surface engineering is key to realizing precisely located and geometrically-defined 2D layers via unseeded chemical vapor deposition techniques.

Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs).

Science.gov (United States)

Kumar, Annie; Lee, Shuh-Ying; Yadav, Sachin; Tan, Kian Hua; Loke, Wan Khai; Dong, Yuan; Lee, Kwang Hong; Wicaksono, Satrio; Liang, Gengchiau; Yoon, Soon-Fatt; Antoniadis, Dimitri; Yeo, Yee-Chia; Gong, Xiao

2017-12-11

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an I ON /I OFF ratio of more than 10 6 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

Optimization of ultra-low-power CMOS transistors

International Nuclear Information System (INIS)

Stockinger, M.

2000-01-01

Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

Flexible digital x-ray technology for far-forward remote diagnostic and conformal x-ray imaging applications

Science.gov (United States)

Smith, Joseph; Marrs, Michael; Strnad, Mark; Apte, Raj B.; Bert, Julie; Allee, David; Colaneri, Nicholas; Forsythe, Eric; Morton, David

2013-05-01

Today's flat panel digital x-ray image sensors, which have been in production since the mid-1990s, are produced exclusively on glass substrates. While acceptable for use in a hospital or doctor's office, conventional glass substrate digital x-ray sensors are too fragile for use outside these controlled environments without extensive reinforcement. Reinforcement, however, significantly increases weight, bulk, and cost, making them impractical for far-forward remote diagnostic applications, which demand rugged and lightweight x-ray detectors. Additionally, glass substrate x-ray detectors are inherently rigid. This limits their use in curved or bendable, conformal x-ray imaging applications such as the non-destructive testing (NDT) of oil pipelines. However, by extending low-temperature thin-film transistor (TFT) technology previously demonstrated on plastic substrate- based electrophoretic and organic light emitting diode (OLED) flexible displays, it is now possible to manufacture durable, lightweight, as well as flexible digital x-ray detectors. In this paper, we discuss the principal technical approaches used to apply flexible display technology to two new large-area flexible digital x-ray sensors for defense, security, and industrial applications and demonstrate their imaging capabilities. Our results include a 4.8″ diagonal, 353 x 463 resolution, flexible digital x-ray detector, fabricated on a 6″ polyethylene naphthalate (PEN) plastic substrate; and a larger, 7.9″ diagonal, 720 x 640 resolution, flexible digital x-ray detector also fabricated on PEN and manufactured on a gen 2 (370 x 470 mm) substrate.

A striking performance improvement of fullerene n-channel field-effect transistors via synergistic interfacial modifications

International Nuclear Information System (INIS)

Du, Lili; Luo, Xiao; Wen, Zhanwei; Zhang, Jianping; Sun, Lei; Lv, Wenli; Li, Yao; Zhao, Feiyu; Zhong, Junkang; Ren, Qiang; Huang, Fobao; Xia, Hongquan; Peng, Yingquan

2015-01-01

For fullerene based n-channel transistors, remarkably improved device characteristics were achieved via charge injection and transport interfacial synergistic modifications using low-cost aluminium source/drain electrodes. Compared with the reference device without any modifications (device A), the as-fabricated transistor (device H) showed a dramatic improvement of saturation mobility from 0.0026 to 0.3078 cm 2 V −1 s −1 with a maximum on–off current ratio of 10 6 and a minimum subthreshold slope of 1.52 V decade −1 . AFM and XRD analysis manifested that the deposited C 60 films on PVA/OTS successive-modified SiO 2 substrate were highly dense polycrystalline and uniform with larger crystalline grain and less grain boundary. A gap state assisted electron injection mechanism was proposed to explicate the enhanced electrical conductivity considering BCP modification for charge injection interface, which has been well corroborated by a diode-based injection experiment and a theoretical calculation of contact resistances. We further demonstrated the application of the concept modification method to enable comparative time-stable operation of fullerene n-channel transistors. Given many key merits, we believed that this general method using multi-interface modifications could be extended to fabricate other n-channel OFETs with superior electrical performance and stability. (paper)

High Electron Mobility Thin-Film Transistors Based on Solution-Processed Semiconducting Metal Oxide Heterojunctions and Quasi-Superlattices

KAUST Repository

Lin, Yen-Hung; Faber, Hendrik; Labram, John G.; Stratakis, Emmanuel; Sygellou, Labrini; Kymakis, Emmanuel; Hastas, Nikolaos A.; Li, Ruipeng; Zhao, Kui; Amassian, Aram; Treat, Neil D.; McLachlan, Martyn; Anthopoulos, Thomas D.

2015-01-01

High mobility thin-film transistor technologies that can be implemented using simple and inexpensive fabrication methods are in great demand because of their applicability in a wide range of emerging optoelectronics. Here, a novel concept of thin-film transistors is reported that exploits the enhanced electron transport properties of low-dimensional polycrystalline heterojunctions and quasi-superlattices (QSLs) consisting of alternating layers of In2O3, Ga2O3, and ZnO grown by sequential spin casting of different precursors in air at low temperatures (180–200 °C). Optimized prototype QSL transistors exhibit band-like transport with electron mobilities approximately a tenfold greater (25–45 cm2 V−1 s−1) than single oxide devices (typically 2–5 cm2 V−1 s−1). Based on temperature-dependent electron transport and capacitance-voltage measurements, it is argued that the enhanced performance arises from the presence of quasi 2D electron gas-like systems formed at the carefully engineered oxide heterointerfaces. The QSL transistor concept proposed here can in principle extend to a range of other oxide material systems and deposition methods (sputtering, atomic layer deposition, spray pyrolysis, roll-to-roll, etc.) and can be seen as an extremely promising technology for application in next-generation large area optoelectronics such as ultrahigh definition optical displays and large-area microelectronics where high performance is a key requirement.

High Electron Mobility Thin-Film Transistors Based on Solution-Processed Semiconducting Metal Oxide Heterojunctions and Quasi-Superlattices

KAUST Repository

Lin, Yen-Hung

2015-05-26

High mobility thin-film transistor technologies that can be implemented using simple and inexpensive fabrication methods are in great demand because of their applicability in a wide range of emerging optoelectronics. Here, a novel concept of thin-film transistors is reported that exploits the enhanced electron transport properties of low-dimensional polycrystalline heterojunctions and quasi-superlattices (QSLs) consisting of alternating layers of In2O3, Ga2O3, and ZnO grown by sequential spin casting of different precursors in air at low temperatures (180–200 °C). Optimized prototype QSL transistors exhibit band-like transport with electron mobilities approximately a tenfold greater (25–45 cm2 V−1 s−1) than single oxide devices (typically 2–5 cm2 V−1 s−1). Based on temperature-dependent electron transport and capacitance-voltage measurements, it is argued that the enhanced performance arises from the presence of quasi 2D electron gas-like systems formed at the carefully engineered oxide heterointerfaces. The QSL transistor concept proposed here can in principle extend to a range of other oxide material systems and deposition methods (sputtering, atomic layer deposition, spray pyrolysis, roll-to-roll, etc.) and can be seen as an extremely promising technology for application in next-generation large area optoelectronics such as ultrahigh definition optical displays and large-area microelectronics where high performance is a key requirement.

Planar-Processed Polymer Transistors.

Science.gov (United States)

Xu, Yong; Sun, Huabin; Shin, Eul-Yong; Lin, Yen-Fu; Li, Wenwu; Noh, Yong-Young

2016-10-01

Planar-processed polymer transistors are proposed where the effective charge injection and the split unipolar charge transport are all on the top surface of the polymer film, showing ideal device characteristics with unparalleled performance. This technique provides a great solution to the problem of fabrication limitations, the ambiguous operating principle, and the performance improvements in practical applications of conjugated-polymer transistors. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low thermal budget annealing technique for high performance amorphous In-Ga-ZnO thin film transistors

Directory of Open Access Journals (Sweden)

Joong-Won Shin

2017-07-01

Full Text Available In this paper, we investigate a low thermal budget post-deposition-annealing (PDA process for amorphous In-Ga-ZnO (a-IGZO oxide semiconductor thin-film-transistors (TFTs. To evaluate the electrical characteristics and reliability of the TFTs after the PDA process, microwave annealing (MWA and rapid thermal annealing (RTA methods were applied, and the results were compared with those of the conventional annealing (CTA method. The a-IGZO TFTs fabricated with as-deposited films exhibited poor electrical characteristics; however, their characteristics were improved by the proposed PDA process. The CTA-treated TFTs had excellent electrical properties and stability, but the CTA method required high temperatures and long processing times. In contrast, the fabricated RTA-treated TFTs benefited from the lower thermal budget due to the short process time; however, they exhibited poor stability. The MWA method uses a low temperature (100 °C and short annealing time (2 min because microwaves transfer energy directly to the substrate, and this method effectively removed the defects in the a-IGZO TFTs. Consequently, they had a higher mobility, higher on-off current ratio, lower hysteresis voltage, lower subthreshold swing, and higher interface trap density than TFTs treated with CTA or RTA, and exhibited excellent stability. Based on these results, low thermal budget MWA is a promising technology for use on various substrates in next generation displays.

Low thermal budget annealing technique for high performance amorphous In-Ga-ZnO thin film transistors

Science.gov (United States)

Shin, Joong-Won; Cho, Won-Ju

2017-07-01

In this paper, we investigate a low thermal budget post-deposition-annealing (PDA) process for amorphous In-Ga-ZnO (a-IGZO) oxide semiconductor thin-film-transistors (TFTs). To evaluate the electrical characteristics and reliability of the TFTs after the PDA process, microwave annealing (MWA) and rapid thermal annealing (RTA) methods were applied, and the results were compared with those of the conventional annealing (CTA) method. The a-IGZO TFTs fabricated with as-deposited films exhibited poor electrical characteristics; however, their characteristics were improved by the proposed PDA process. The CTA-treated TFTs had excellent electrical properties and stability, but the CTA method required high temperatures and long processing times. In contrast, the fabricated RTA-treated TFTs benefited from the lower thermal budget due to the short process time; however, they exhibited poor stability. The MWA method uses a low temperature (100 °C) and short annealing time (2 min) because microwaves transfer energy directly to the substrate, and this method effectively removed the defects in the a-IGZO TFTs. Consequently, they had a higher mobility, higher on-off current ratio, lower hysteresis voltage, lower subthreshold swing, and higher interface trap density than TFTs treated with CTA or RTA, and exhibited excellent stability. Based on these results, low thermal budget MWA is a promising technology for use on various substrates in next generation displays.

Basic matrix algebra and transistor circuits

CERN Document Server

Zelinger, G

1963-01-01

Basic Matrix Algebra and Transistor Circuits deals with mastering the techniques of matrix algebra for application in transistors. This book attempts to unify fundamental subjects, such as matrix algebra, four-terminal network theory, transistor equivalent circuits, and pertinent design matters. Part I of this book focuses on basic matrix algebra of four-terminal networks, with descriptions of the different systems of matrices. This part also discusses both simple and complex network configurations and their associated transmission. This discussion is followed by the alternative methods of de

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

Science.gov (United States)

Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

2018-04-01

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

Highly Crumpled All-Carbon Transistors for Brain Activity Recording.

Science.gov (United States)

Yang, Long; Zhao, Yan; Xu, Wenjing; Shi, Enzheng; Wei, Wenjing; Li, Xinming; Cao, Anyuan; Cao, Yanping; Fang, Ying

2017-01-11

Neural probes based on graphene field-effect transistors have been demonstrated. Yet, the minimum detectable signal of graphene transistor-based probes is inversely proportional to the square root of the active graphene area. This fundamentally limits the scaling of graphene transistor-based neural probes for improved spatial resolution in brain activity recording. Here, we address this challenge using highly crumpled all-carbon transistors formed by compressing down to 16% of its initial area. All-carbon transistors, chemically synthesized by seamless integration of graphene channels and hybrid graphene/carbon nanotube electrodes, maintained structural integrity and stable electronic properties under large mechanical deformation, whereas stress-induced cracking and junction failure occurred in conventional graphene/metal transistors. Flexible, highly crumpled all-carbon transistors were further verified for in vivo recording of brain activity in rats. These results highlight the importance of advanced material and device design concepts to make improvements in neuroelectronics.

Passivation and Depassivation of Defects in Graphene-based field-effect transistors

Science.gov (United States)

O'Hara, Andrew; Wang, Pan; Perini, Chris J.; Fleetwood, Daniel M.; Vogel, Eric M.; Pantelides, Sokrates T.

Field effect transistors based on graphene on amorphous SiO2 substrates were fabricated, both with and without a top oxide passivation layer of Al2O3. Initial I-V characteristics of these devices show that the Fermi energy occurs below the Dirac point in graphene (i.e. p-type behavior). Introduction of environmental stresses, e.g. baking the devices, causes a shift in the Fermi energy relative to the Dirac point. 1/f noise measurements indicate the presence of charge trapping defects. In order to find the origins of this behavior, we construct atomistic models of the substrate/graphene interface and the graphene/oxide passivation layer interface. Using density functional theory, we investigate the role that the introduction and removal of hydrogen and hydroxide passivants has on the electronic structure of the graphene layer as well as the relative energetics for these processes to occur in order to gain insights into the experimental results. Supported by DTRA: 1-16-0032 and NSF: ECCS-1508898.

Graphene nanoribbon field-effect transistors on wafer-scale epitaxial graphene on SiC substrates

Directory of Open Access Journals (Sweden)

Wan Sik Hwang

2015-01-01

Full Text Available We report the realization of top-gated graphene nanoribbon field effect transistors (GNRFETs of ∼10 nm width on large-area epitaxial graphene exhibiting the opening of a band gap of ∼0.14 eV. Contrary to prior observations of disordered transport and severe edge-roughness effects of graphene nanoribbons (GNRs, the experimental results presented here clearly show that the transport mechanism in carefully fabricated GNRFETs is conventional band-transport at room temperature and inter-band tunneling at low temperature. The entire space of temperature, size, and geometry dependent transport properties and electrostatics of the GNRFETs are explained by a conventional thermionic emission and tunneling current model. Our combined experimental and modeling work proves that carefully fabricated narrow GNRs behave as conventional semiconductors and remain potential candidates for electronic switching devices.

Blending effect of 6,13-bis(triisopropylsilylethynyl) pentacene–graphene composite layers for flexible thin film transistors with a polymer gate dielectric

International Nuclear Information System (INIS)

Basu, Sarbani; Adriyanto, Feri; Wang, Yeong-Her

2014-01-01

Solution processible poly(4-vinylphenol) is employed as a transistor dielectric material for low cost processing on flexible substrates at low temperatures. A 6,13-bis (triisopropylsilylethynyl) (TIPS) pentacene–graphene hybrid semiconductor is drop cast to fabricate bottom-gate and bottom-contact field-effect transistor devices on flexible and glass substrates under an ambient air environment. A few layers of graphene flakes increase the area in the conduction channel, and form bridge connections between the crystalline regions of the semiconductor layer which can change the surface morphology of TIPS pentacene films. The TIPS pentacene–graphene hybrid semiconductor-based organic thin film transistors (OTFTs) cross-linked with a poly(4-vinylphenol) gate dielectric exhibit an effective field-effect mobility of 0.076 cm 2  V −1  s −1 and a threshold voltage of −0.7 V at V gs = −40 V. By contrast, typical TIPS pentacene shows four times lower mobility of 0.019 cm 2  V −1  s −1 and a threshold voltage of 5 V. The graphene/TIPS pentacene hybrids presented in this paper can enhance the electrical characteristics of OTFTs due to their high crystallinity, uniform large-grain distribution, and effective reduction of crystal misorientation of the organic semiconductor layer, as confirmed by x-ray diffraction spectroscopy, atomic force microscopy, and optical microscopy studies. (paper)

High Accuracy Transistor Compact Model Calibrations

Energy Technology Data Exchange (ETDEWEB)

Hembree, Charles E. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Mar, Alan [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Robertson, Perry J. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirements require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

Science.gov (United States)

2013-05-01

The largest company in the world is now a technology company (Apple Inc.) whose products are all enabled by transistors [2]. Any changes, for better...increasing standby battery life. The nVidia Tegra 3 mobile processor for applications in smartphones and tablets contains five cores: one low power...white paper, NVIDIA , 2011. 14. W. G. Vandenberghe, B. Sorée, W. Magnus, G. Groeseneken, and M. V. Fischetti, “Impact of field-induced quantum

Ultrasmall transistor-based light sources

DEFF Research Database (Denmark)

With Jensen, Per Baunegaard; Tavares, Luciana; Kjelstrup-Hansen, Jakob

Dette projekt fokuserer på at udvikle transistor baserede nanofiber lyskilder med det overordnede mål at udvikle effektive og nano skalerede flerfarvede lyskilder integreret on-chip.......Dette projekt fokuserer på at udvikle transistor baserede nanofiber lyskilder med det overordnede mål at udvikle effektive og nano skalerede flerfarvede lyskilder integreret on-chip....

Functional integrity of flexible n-channel metal–oxide–semiconductor field-effect transistors on a reversibly bistable platform

Energy Technology Data Exchange (ETDEWEB)

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Hussain, Muhammad M., E-mail: MuhammadMustafa.Hussain@kaust.edu.sa [Integrated Nanotechnology Laboratory, Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology, Thuwal 23955-6900 (Saudi Arabia); Aljedaani, Abdulrahman B. [High-Speed Fluids Imaging Laboratory, Physical Sciences and Engineering Division, King Abdullah University of Science and Technology, Thuwal 23955-6900 (Saudi Arabia)

2015-10-26

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal–oxide–semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

Functional integrity of flexible n-channel metal–oxide–semiconductor field-effect transistors on a reversibly bistable platform

International Nuclear Information System (INIS)

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Hussain, Muhammad M.; Aljedaani, Abdulrahman B.

2015-01-01

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal–oxide–semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties

Functional integrity of flexible n-channel metal–oxide–semiconductor field-effect transistors on a reversibly bistable platform

KAUST Repository

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Aljedaani, Abdulrahman B.; Hussain, Muhammad Mustafa

2015-01-01

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal–oxide–semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

Functional integrity of flexible n-channel metal-oxide-semiconductor field-effect transistors on a reversibly bistable platform

Science.gov (United States)

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Aljedaani, Abdulrahman B.; Hussain, Muhammad M.

2015-10-01

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal-oxide-semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

Effect of the Ion Mass and Energy on the Response of 70-nm SOI Transistors to the Ion Deposited Charge by Direct Ionization

International Nuclear Information System (INIS)

Raine, M.; Gaillardin, M.; Sauvestre, J.E.; Flament, O.; Bournel, A.; Aubry-Fortuna, V.

2010-01-01

The response of SOI transistors under heavy ion irradiation is analyzed using Geant4 and Synopsys Sentaurus device simulations. The ion mass and energy have a significant impact on the radial ionization profile of the ion deposited charge. For example, for an identical LET, the higher the ion energy per nucleon, the wider the radial ionization track. For a 70-nm SOI technology, the track radius of high energy ions (≥ 10 MeV/a) is larger than the transistor sensitive volume; part of the ion charge recombines in the highly doped source or drain regions and does not participate to the transistor electric response. At lower energy (≤ 10 MeV/a), as often used for ground testing, the track radius is smaller than the transistor sensitive volume, and the entire charge is used for the transistor response. The collected charge is then higher, corresponding to a worst-case response of the transistor. Implications for the hardness assurance of highly-scaled generations are discussed. (authors)

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

International Nuclear Information System (INIS)

Miyoshi, Makoto; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi; Mizuno, Masaya; Soga, Tetsuo

2015-01-01

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO 2 /Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO 2 /Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO 2 /Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm 2 /V s for electrons and 880 cm 2 /V s for holes, respectively

Transfer-free graphene synthesis on sapphire by catalyst metal agglomeration technique and demonstration of top-gate field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Miyoshi, Makoto, E-mail: miyoshi.makoto@nitech.ac.jp; Arima, Yukinori; Kubo, Toshiharu; Egawa, Takashi [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Mizuno, Masaya [Research Center for Nano Device and Advanced Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Soga, Tetsuo [Department of Frontier Materials, Nagoya Institute of Technology, Nagoya 466-8555 (Japan)

2015-08-17

Transfer-free graphene synthesis was performed on sapphire substrates by using the catalyst metal agglomeration technique, and the graphene film quality was compared to that synthesized on sputtered SiO{sub 2}/Si substrates. Raman scattering measurements indicated that the graphene film on sapphire has better structural qualities than that on sputtered SiO{sub 2}/Si substrates. The cross-sectional transmission microscopic study also revealed that the film flatness was drastically improved by using sapphire substrates instead of sputtered SiO{sub 2}/Si substrates. These quality improvements seemed to be due the chemical and thermal stabilities of sapphire. Top-gate field-effect transistors were fabricated using the graphene films on sapphire, and it was confirmed that their drain current can be modulated with applied gate voltages. The maximum field-effect mobilities were estimated to be 720 cm{sup 2}/V s for electrons and 880 cm{sup 2}/V s for holes, respectively.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

Science.gov (United States)

2014-01-01

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing. PMID:25276107

Balanced G-band Gm-boosted frequency doublers in transferred substrate InP HBT technology

DEFF Research Database (Denmark)

Johansen, Tom Keinicke; Thualfiqar, Al-Sawaf; Weimann, Nils

2016-01-01

In this paper, balanced G-band Gm-boosted frequency doublers in transferred substrate (TS) InP HBT technology are reported for the first time. The Gm-boosted frequency doublers consist of a phase compensated Marchand balun, Gm-boosted doubler stage, and an optional cascode gain stage at the outpu...

Three-dimensional photolithography technology for a fiber substrate using a microfabricated exposure module

International Nuclear Information System (INIS)

Lu, Yao; Zhang, Yi; Lu, Jian; Mimura, Akio; Matsumoto, Sohei; Itoh, Toshihiro

2010-01-01

This paper proposes a new three-dimensional (3D) photolithography technology for a high-resolution micropatterning process on a fiber substrate. A brief review on the lithography technology of the non-planar surface is also presented. The proposed technology mainly comprises the microfabrication of the 3D exposure module and the spray deposition of thin resist films on the fiber. The 3D exposure module is successfully prepared by the wet etching of a quartz substrate and the projection exposure method. The chief advantages of the 3D exposure module are long service life, low cost, narrow print gap and thus high resolution. A novel spray coating system has been developed for the preparation of uniform and thin resist films on the fibers, which are necessary for the high-resolution micropatterning process. The spray deposition process on the 125 µm in-diameter optical fiber has been systematically investigated. The viscosity and volatility of the resist solutions have complicated effects because the spray-coating deposition process on the fiber mainly consisted of the impinging region. The uniform and thin resist film down to 1 µm thick had been successfully achieved. Fine patterns with the line width down to 6 µm were successfully formed on the optical fiber by using the microfabricated exposure module. Preliminary photolithography experiments confirmed that the new 3D photolithography technology is one attractive low-cost solution to the integration of micro transducers onto the fibers for various applications. The 3D exposure module could also enable the continuous photolithography process on the fibers

An innovative large scale integration of silicon nanowire-based field effect transistors

Science.gov (United States)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Performance improvement for solution-processed high-mobility ZnO thin-film transistors

International Nuclear Information System (INIS)

Li Chensha; Loutfy, Rafik O; Li Yuning; Wu Yiliang; Ong, Beng S

2008-01-01

The fabrication technology of stable, non-toxic, transparent, high performance zinc oxide (ZnO) thin-film semiconductors via the solution process was investigated. Two methods, which were, respectively, annealing a spin-coated precursor solution and annealing a drop-coated precursor solution, were compared. The prepared ZnO thin-film semiconductor transistors have well-controlled, preferential crystal orientation and exhibit superior field-effect performance characteristics. But the ZnO thin-film transistor (TFT) fabricated by annealing a drop-coated precursor solution has a distinctly elevated linear mobility, which further approaches the saturated mobility, compared with that fabricated by annealing a spin-coated precursor solution. The performance of the solution-processed ZnO TFT was further improved when substituting the spin-coating process by the drop-coating process

Performance improvement for solution-processed high-mobility ZnO thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Li Chensha; Loutfy, Rafik O [Department of Chemical Engineering, McMaster University, 1280 Main Street West, Hamilton, Ontario L8S 4L7 (Canada); Li Yuning; Wu Yiliang; Ong, Beng S [Materials Design and Integration Laboratory, Xerox Research Centre of Canada, 2660 Speakman Drive, Mississauga, Ontario L5K 2L1 (Canada)], E-mail: lichnsa@163.com

2008-06-21

The fabrication technology of stable, non-toxic, transparent, high performance zinc oxide (ZnO) thin-film semiconductors via the solution process was investigated. Two methods, which were, respectively, annealing a spin-coated precursor solution and annealing a drop-coated precursor solution, were compared. The prepared ZnO thin-film semiconductor transistors have well-controlled, preferential crystal orientation and exhibit superior field-effect performance characteristics. But the ZnO thin-film transistor (TFT) fabricated by annealing a drop-coated precursor solution has a distinctly elevated linear mobility, which further approaches the saturated mobility, compared with that fabricated by annealing a spin-coated precursor solution. The performance of the solution-processed ZnO TFT was further improved when substituting the spin-coating process by the drop-coating process.

Research and development of basic technologies for the next generation industries, 'environment resistance strengthened elements'. Evaluation on the second term research and development; Jisedai sangyo kiban gijutsu kenkyu kaihatsu 'Taikankyo kyoka soshi'. Dainiki kenkyu kaihatsu hyoka

Energy Technology Data Exchange (ETDEWEB)

NONE

1986-03-31

In the research and development of the environment resistance strengthened elements with emphasis placed respectively on radiation resistance, heat resistance, and integration degree according to specific requirements in the using environments, the second term has developed an integration technology and its evaluation technology based on the achievements in the first term. In developing the heat resistant element technology, the technology to grow {beta}-SiC crystals was expanded to obtaining thin film crystals with high migratory performance by using higher temperatures. At the same time, development was performed on a technology to manufacture multiple number of transistors on one substrate, such as the doping technology and etching technology. Using this technology, schottky diodes and p-n junction elements being the basic structures of MES-FET and bipolar transistors were fabricated. In the evaluation and testing technology, the {gamma} dose measuring method using TLD was improved, the traceability of {gamma} ray irradiation amount was assured, the simplified irradiation testing method using X-ray was established, and the heat resistance testing technology for electronic parts was established. Furthermore, attempts were made on enhancing radiation resistance of the elements, such as in MOS silicon integrated circuit, bipolar silicon integrated circuit, and compound semiconductor integrated circuit. (NEDO)

Molecular materials for organic field-effect transistors

International Nuclear Information System (INIS)

Mori, T

2008-01-01

Organic field-effect transistors are important applications of thin films of molecular materials. A variety of materials have been explored for improving the performance of organic transistors. The materials are conventionally classified as p-channel and n-channel, but not only the performance but also even the carrier polarity is greatly dependent on the combinations of organic semiconductors and electrode materials. In this review, particular emphasis is laid on multi-sulfur compounds such as tetrathiafulvalenes and metal dithiolates. These compounds are components of highly conducting materials such as organic superconductors, but are also used in organic transistors. The charge-transfer complexes are used in organic transistors as active layers as well as electrodes. (topical review)

Multiple-channel detection of cellular activities by ion-sensitive transistors

Science.gov (United States)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

The importance of spinning speed in fabrication of spin-coated organic thin film transistors: Film morphology and field effect mobility

International Nuclear Information System (INIS)

Kotsuki, Kenji; Tanaka, Hiroshige; Obata, Seiji; Stauss, Sven; Terashima, Kazuo; Saiki, Koichiro

2014-01-01

We have investigated the film morphology and the field effect mobility of 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) thin films which were formed by spin coating on the SiO 2 substrate with solution-processed graphene electrodes. The domain size and the density of aggregates in the C8-BTBT film showed the same dependence on the spinning speed. These competitive two factors (domain size and density of aggregates) give an optimum spinning speed, at which the field effect mobility of C8-BTBT transistor showed a maximum (2.6 cm 2 /V s). This result indicates the importance of spinning speed in the fabrication of solution processed organic thin film transistors by spin coating.

Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

KAUST Repository

Hanna, Amir

2013-12-23

We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, ~100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits

Science.gov (United States)

Belenguer, Angel; Cano, Juan Luis; Esteban, Héctor; Artal, Eduardo; Boria, Vicente E.

2017-01-01

Substrate integrated circuits (SIC) have attracted much attention in the last years because of their great potential of low cost, easy manufacturing, integration in a circuit board, and higher-quality factor than planar circuits. A first suite of SIC where the waves propagate through dielectric have been first developed, based on the well-known substrate integrated waveguide (SIW) and related technological implementations. One step further has been made with a new suite of empty substrate integrated waveguides, where the waves propagate through air, thus reducing the associated losses. This is the case of the empty substrate integrated waveguide (ESIW) or the air-filled substrate integrated waveguide (air-filled SIW). However, all these SIC are H plane structures, so classical H plane solutions in rectangular waveguides have already been mapped to most of these new SIC. In this paper a novel E plane empty substrate integrated waveguide (ESIW-E) is presented. This structure allows to easily map classical E plane solutions in rectangular waveguide to this new substrate integrated solution. It is similar to the ESIW, although more layers are needed to build the structure. A wideband transition (covering the frequency range between 33 GHz and 50 GHz) from microstrip to ESIW-E is designed and manufactured. Measurements are successfully compared with simulation, proving the validity of this new SIC. A broadband high-frequency phase shifter (for operation from 35 GHz to 47 GHz) is successfully implemented in ESIW-E, thus proving the good performance of this new SIC in a practical application.

Photon-gated spin transistor

OpenAIRE

Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

2017-01-01

Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

Organic Thin-Film Transistor (OTFT-Based Sensors

Directory of Open Access Journals (Sweden)

Daniel Elkington

2014-04-01

Full Text Available Organic thin film transistors have been a popular research topic in recent decades and have found applications from flexible displays to disposable sensors. In this review, we present an overview of some notable articles reporting sensing applications for organic transistors with a focus on the most recent publications. In particular, we concentrate on three main types of organic transistor-based sensors: biosensors, pressure sensors and “e-nose”/vapour sensors.

Evaluation of Surface Cleaning Procedures for CTGS Substrates for SAW Technology with XPS

Directory of Open Access Journals (Sweden)

Erik Brachmann

2017-11-01

Full Text Available A highly efficient and reproducible cleaning procedure of piezoelectric substrates is essential in surface acoustic waves (SAW technology to fabricate high-quality SAW devices, especially for new applications such SAW sensors wherein new materials for piezoelectric substrates and interdigital transducers are used. Therefore, the development and critical evaluation of cleaning procedures for each material system that is under consideration becomes crucial. Contaminants like particles or the presence of organic/inorganic material on the substrate can dramatically influence and alter the properties of the thin film substrate composite, such as wettability, film adhesion, film texture, and so on. In this article, focus is given to different cleaning processes like SC-1 and SC-2, UV-ozone treatment, as well as cleaning by first-contact polymer Opticlean, which are applied for removal of contaminants from the piezoelectric substrate Ca 3 TaGa 3 Si 2 O 14 . By means of X-ray photoelectron spectroscopy, the presence of the most critical contaminants such as carbon, sodium, and iron removed through different cleaning procedures were studied and significant differences were observed between the outcomes of these procedures. Based on these results, a two-step cleaning process, combining SC-1 at a reduced temperature at 30 ∘ C instead of 80 ∘ C and a subsequent UV-ozone cleaning directly prior to deposition of the metallization, is suggested to achieve the lowest residual contamination level.

Critical current densities amd pinning mechanisms of high-Tc films on single crystalline and technologically relevant substrates. Final report

International Nuclear Information System (INIS)

Adrian, H.

1995-12-01

The report deals with six project tasks: (1) Effects of impurity additions at atomic level on the pinning behaviour and the critical current densities, examined in epitactic YBA 2 (Cu 1-x Ni x ) 3 O 7 films. It could be proven that the Ni atoms increase the activation energy for flux movement and the critical current density in a concentration range of 0 2 Sr 2 Ca n-1 Cu n O 2n+4+δ films (n = 2 and 3) with good crystalline properties, high critical currents, and high current densities were prepared. Thin YBa 2 Cu 3 O 7 films of high quality could be grown on saphire substrates, both by the MO-CVD process and by MBE. The aim of depositing biaxially textured YBa 2 Cu 3 O 7 films with high critical current densities on polycrystalline, metallic substrates was achieved by the IBAD process combined with MBE. The buffer layer was YSZ. Heterostructures of the layer sequence YBa 2 Cu 3 O 7 /CeO 2 /Y 0.3 Pr 0.7 Ba 2 Cu 3 O 7 /YBa 2 Cu 3 O 7 and YBa 2 Cu 3 O 7 /CeO 2 /Au were prepared by laser ablation and sputtering processes, in order to examine Josephson ramp contacts and superconducting field-effect transistors. (orig./MM) [de

Bulletin of Materials Science | Indian Academy of Sciences

Indian Academy of Sciences (India)

We report here RF MOSFET performance in sub-45-nm hybrid orientation CMOS technology. Based on the combination of hybrid orientation technology (HOT) and process-induced local strain engineering,MOSFET RF performance is investigated using CAD (TCAD) technology. Transistor optimization on (100) substrate ...

Fin field effect transistor directionality impacts printing of implantation shapes

Science.gov (United States)

Wang, Xiren; Granik, Yuri

2018-01-01

In modern integrated circuit (IC) fabrication processes, the photoresist receives considerable illumination energy that is reflected by underlying topography during optical lithography of implantation layers. Bottom antireflective coating (BARC) is helpful to mitigate the reflection. Often, however, BARC is not used, because its removal is technically challenging, in addition to its relatively high economic cost. Furthermore, the advanced technology nodes, such as 14/10-nm nodes, have introduced fin field effect transistor (FinFET), which makes reflection from nonuniform silicon substrates exceptionally complicated. Therefore, modeling reflection from topography becomes obligatory to accurately predict printing of implantation shapes. Typically, FinFET is always fixed in one direction in realistic designs. However, the same implantation rectangle may be oriented in either horizontal or vertical direction. Then, there are two types of relations between the critical dimension (CD) and FinFET, namely a parallel-to and a perpendicular-to relation. We examine the fin directionality impact on CD. We found that this impact may be considerable in some cases. We use our in-house rigorous optical topography simulator to reveal underlining physical reasons. One of the major causes of the CD differences is that in the parallel orientation, the solid sidewalls of the fins conduct considerable light reflections unlike for the perpendicular orientation. This finding can aid the compact modeling in optical proximity correction of implantation masks.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Science.gov (United States)

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

High Electron Mobility Thin‐Film Transistors Based on Solution‐Processed Semiconducting Metal Oxide Heterojunctions and Quasi‐Superlattices

Science.gov (United States)

Lin, Yen‐Hung; Faber, Hendrik; Labram, John G.; Stratakis, Emmanuel; Sygellou, Labrini; Kymakis, Emmanuel; Hastas, Nikolaos A.; Li, Ruipeng; Zhao, Kui; Amassian, Aram; Treat, Neil D.; McLachlan, Martyn

2015-01-01

High mobility thin‐film transistor technologies that can be implemented using simple and inexpensive fabrication methods are in great demand because of their applicability in a wide range of emerging optoelectronics. Here, a novel concept of thin‐film transistors is reported that exploits the enhanced electron transport properties of low‐dimensional polycrystalline heterojunctions and quasi‐superlattices (QSLs) consisting of alternating layers of In2O3, Ga2O3, and ZnO grown by sequential spin casting of different precursors in air at low temperatures (180–200 °C). Optimized prototype QSL transistors exhibit band‐like transport with electron mobilities approximately a tenfold greater (25–45 cm2 V−1 s−1) than single oxide devices (typically 2–5 cm2 V−1 s−1). Based on temperature‐dependent electron transport and capacitance‐voltage measurements, it is argued that the enhanced performance arises from the presence of quasi 2D electron gas‐like systems formed at the carefully engineered oxide heterointerfaces. The QSL transistor concept proposed here can in principle extend to a range of other oxide material systems and deposition methods (sputtering, atomic layer deposition, spray pyrolysis, roll‐to‐roll, etc.) and can be seen as an extremely promising technology for application in next‐generation large area optoelectronics such as ultrahigh definition optical displays and large‐area microelectronics where high performance is a key requirement. PMID:27660741

Efficient simulation of power MOS transistors

NARCIS (Netherlands)

Ugryumova, M.; Schilders, W.H.A.

2011-01-01

In this report we present a few industrial problems related to modeling of MOS transistors. We suggest an efficient algorithm for computing output current at the top ports of power MOS transistors for given voltage excitations. The suggested algorithm exploits the connection between the resistor and

Thermal transistor utilizing gas-liquid transition

KAUST Repository

Komatsu, Teruhisa S.

2011-01-25

We propose a simple thermal transistor, a device to control heat current. In order to effectively change the current, we utilize the gas-liquid transition of the heat-conducting medium (fluid) because the gas region can act as a good thermal insulator. The three terminals of the transistor are located at both ends and the center of the system, and are put into contact with distinct heat baths. The key idea is a special arrangement of the three terminals. The temperature at one end (the gate temperature) is used as an input signal to control the heat current between the center (source, hot) and another end (drain, cold). Simulating the nanoscale systems of this transistor, control of heat current is demonstrated. The heat current is effectively cut off when the gate temperature is cold and it flows normally when it is hot. By using an extended version of this transistor, we also simulate a primitive application for an inverter. © 2011 American Physical Society.

Water-gel for gating graphene transistors.

Science.gov (United States)

Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

2014-05-14

Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

An improved PIN photodetector with integrated JFET on high-resistivity silicon

International Nuclear Information System (INIS)

Dalla Betta, Gian-Franco; Piemonte, Claudio; Boscardin, Maurizio; Gregori, Paolo; Zorzi, Nicola; Fazzi, Alberto; Pignatel, Giorgio U.

2006-01-01

We report on a PIN photodetector integrated with a Junction Field Effect Transistor (JFET) on a high-resistivity silicon substrate. Owing to a modified fabrication technology, the electrical and noise characteristics of the JFET transistor have been enhanced with respect to the previous versions of the device, allowing the performance to be significantly improved. In this paper, the main design and technological aspects relevant to the proposed structure are addressed and experimental results from the electrical characterization are discussed

An improved bipolar junction transistor model for electrical and radiation effects

International Nuclear Information System (INIS)

Kleiner, C.T.; Messenger, G.C.

1982-01-01

The use of bipolar technology in hardened electronic design requires an in-depth understanding of how the Bipolar Junction Transistor (BJT) behaves under normal electrical and radiation environments. Significant improvements in BJT process technology have been reported, and the successful use of sophisticated Computer Aided Design (CAD) tools has aided implementation with respect to specific families of hardened devices. The most advanced BJT model used to date is the Improved Gummel-Poon (IGP) model which is used in CAA programs such as the SPICE II and SLICE programs. The earlier Ebers-Moll model (ref 1 and 2) has also been updated to compare with the older Gummel-Poon model. This paper describes an adaptation of an existing computer model which incorporates the best features of both models into a new, more accurate model called the Improved Bipolar Junction Transistor model. This paper also describes a unique approach to data reduction for the B(I /SUB c/) and V /SUB BE/(ACT) vs I /SUB c/characterizations which has been successfully programmed in Basic using a Commodore PET computer. This model is described in the following sections

Biosensor properties of SOI nanowire transistors with a PEALD Al{sub 2}O{sub 3} dielectric protective layer

Energy Technology Data Exchange (ETDEWEB)

Popov, V. P., E-mail: popov@isp.nsc.ru; Ilnitskii, M. A.; Zhanaev, E. D. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation); Myakon’kich, A. V.; Rudenko, K. V. [Russian Academy of Sciences, Physical Technological Institute (Russian Federation); Glukhov, A. V. [Novosibirsk Semiconductor Device Plant and Design Bureau (Russian Federation)

2016-05-15

The properties of protective dielectric layers of aluminum oxide Al{sub 2}O{sub 3} applied to prefabricated silicon-nanowire transistor biochips by the plasma enhanced atomic layer deposition (PEALD) method before being housed are studied depending on the deposition and annealing modes. Coating the natural silicon oxide with a nanometer Al{sub 2}O{sub 3} layer insignificantly decreases the femtomole sensitivity of biosensors, but provides their stability in bioliquids. In deionized water, transistors with annealed aluminum oxide are closed due to the trapping of negative charges of <(1–10) × 10{sup 11} cm{sup −2} at surface states. The application of a positive potential to the substrate (V{sub sub} > 25 V) makes it possible to eliminate the negative charge and to perform multiple measurements in liquid at least for half a year.

Ge/IIIV fin field-effect transistor common gate process and numerical simulations

Science.gov (United States)

Chen, Bo-Yuan; Chen, Jiann-Lin; Chu, Chun-Lin; Luo, Guang-Li; Lee, Shyong; Chang, Edward Yi

2017-04-01

This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

Science.gov (United States)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

Numerical study of self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride substrate

International Nuclear Information System (INIS)

Ding Yanfang; Zhu Ziqiang; Zhu Ming; Lin Chenglu

2006-01-01

Compared with bulk-silicon technology, silicon-on-insulator (SOI) technology possesses many advantages but it is inevitable that the buried silicon dioxide layer also thermally insulates the metal-oxide-silicon field-effect transistors (MOSFETs) from the bulk due to the low thermal conductivity. One of the alternative insulator to replace the buried oxide layer is aluminum nitride (MN), which has a thermal conductivity that is about 200 times higher than that of SiO 2 (320 W·m -1 ·K -1 versus 1.4 W·m -1 ·K -l ). To investigate the self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride (SOAN) substrate, a two-dimensional numerical analysis is performed by using a device simulator called MEDICI run on a Solaris workstation to simulate the electrical characteristics and temperature distribution by comparing with those of bulk and standard SOI MOSFETs. Our study suggests that AIN is a suitable alternative to silicon dioxide as a buried dielectric in SOI and expands the applications of SOI to high temperature conditions. (authors)

Interface-Dependent Effective Mobility in Graphene Field-Effect Transistors

Science.gov (United States)

Ahlberg, Patrik; Hinnemo, Malkolm; Zhang, Shi-Li; Olsson, Jörgen

2018-03-01

By pretreating the substrate of a graphene field-effect transistor (G-FET), a stable unipolar transfer characteristic, instead of the typical V-shape ambipolar behavior, has been demonstrated. This behavior is achieved through functionalization of the SiO2/Si substrate that changes the SiO2 surface from hydrophilic to hydrophobic, in combination with postdeposition of an Al2O3 film by atomic layer deposition (ALD). Consequently, the back-gated G-FET is found to have increased apparent hole mobility and suppressed apparent electron mobility. Furthermore, with addition of a top-gate electrode, the G-FET is in a double-gate configuration with independent top- or back-gate control. The observed difference in mobility is shown to also be dependent on the top-gate bias, with more pronounced effect at higher electric field. Thus, the combination of top and bottom gates allows control of the G-FET's electron and hole mobilities, i.e., of the transfer behavior. Based on these observations, it is proposed that polar ligands are introduced during the ALD step and, depending on their polarization, result in an apparent increase of the effective hole mobility and an apparent suppressed effective electron mobility.

Transistor reset preamplifier for high-rate high-resolution spectroscopy

International Nuclear Information System (INIS)

Landis, D.A.; Cork, C.P.; Madden, N.W.; Goulding, F.S.

1981-10-01

Pulsed transistor reset of high resolution charge sensitive preamplifiers used in cooled semiconductor spectrometers can sometimes have an advantage over pulsed light reset systems. Several versions of transistor reset spectrometers using both silicon and germanium detectors have been built. This paper discusses the advantages of the transistor reset system and illustrates several configurations of the packages used for the FET and reset transistor. It also describes the preamplifer circuit and shows the performance of the spectrometer at high rates

Room-Temperature-Processed Flexible Amorphous InGaZnO Thin Film Transistor.

Science.gov (United States)

Xiao, Xiang; Zhang, Letao; Shao, Yang; Zhou, Xiaoliang; He, Hongyu; Zhang, Shengdong

2017-12-13

A room-temperature flexible amorphous indium-gallium-zinc oxide thin film transistor (a-IGZO TFT) technology is developed on plastic substrates, in which both the gate dielectric and passivation layers of the TFTs are formed by an anodic oxidation (anodization) technique. While the gate dielectric Al 2 O 3 is grown with a conventional anodization on an Al:Nd gate electrode, the channel passivation layer Al 2 O 3 is formed using a localized anodization technique. The anodized Al 2 O 3 passivation layer shows a superior passivation effect to that of PECVD SiO 2 . The room-temperature-processed flexible a-IGZO TFT exhibits a field-effect mobility of 7.5 cm 2 /V·s, a subthreshold swing of 0.44 V/dec, an on-off ratio of 3.1 × 10 8 , and an acceptable gate-bias stability with threshold voltage shifts of 2.65 and -1.09 V under positive gate-bias stress and negative gate-bias stress, respectively. Bending and fatigue tests confirm that the flexible a-IGZO TFT also has a good mechanical reliability, with electrical performances remaining consistent up to a strain of 0.76% as well as after 1200 cycles of fatigue testing.

Protonic transistors from thin reflecting films

Energy Technology Data Exchange (ETDEWEB)

Ordinario, David D.; Phan, Long; Jocson, Jonah-Micah [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Nguyen, Tam [Department of Chemistry, University of California, Irvine, California 92697 (United States); Gorodetsky, Alon A., E-mail: alon.gorodetsky@uci.edu [Department of Chemical Engineering and Materials Science, University of California, Irvine, California 92697 (United States); Department of Chemistry, University of California, Irvine, California 92697 (United States)

2015-01-01

Ionic transistors from organic and biological materials hold great promise for bioelectronics applications. Thus, much research effort has focused on optimizing the performance of these devices. Herein, we experimentally validate a straightforward strategy for enhancing the high to low current ratios of protein-based protonic transistors. Upon reducing the thickness of the transistors’ active layers, we increase their high to low current ratios 2-fold while leaving the other figures of merit unchanged. The measured ratio of 3.3 is comparable to the best values found for analogous devices. These findings underscore the importance of the active layer geometry for optimum protonic transistor functionality.

The Mobility Enhancement of Indium Gallium Zinc Oxide Transistors via Low-temperature Crystallization using a Tantalum Catalytic Layer

OpenAIRE

Shin, Yeonwoo; Kim, Sang Tae; Kim, Kuntae; Kim, Mi Young; Oh, Saeroonter; Jeong, Jae Kyeong

2017-01-01

High-mobility indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are achieved through low-temperature crystallization enabled via a reaction with a transition metal catalytic layer. For conventional amorphous IGZO TFTs, the active layer crystallizes at thermal annealing temperatures of 600??C or higher, which is not suitable for displays using a glass substrate. The crystallization temperature is reduced when in contact with a Ta layer, where partial crystallization at the IGZO bac...

Modeling and Simulation of - and Silicon Germanium-Base Bipolar Transistors Operating at a Wide Range of Temperatures.

Science.gov (United States)

Shaheed, M. Reaz

1995-01-01

Higher speed at lower cost and at low power consumption is a driving force for today's semiconductor technology. Despite a substantial effort toward achieving this goal via alternative technologies such as III-V compounds, silicon technology still dominates mainstream electronics. Progress in silicon technology will continue for some time with continual scaling of device geometry. However, there are foreseeable limits on achievable device performance, reliability and scaling for room temperature technologies. Thus, reduced temperature operation is commonly viewed as a means for continuing the progress towards higher performance. Although silicon CMOS will be the first candidate for low temperature applications, bipolar devices will be used in a hybrid fashion, as line drivers or in limited critical path elements. Silicon -germanium-base bipolar transistors look especially attractive for low-temperature bipolar applications. At low temperatures, various new physical phenomena become important in determining device behavior. Carrier freeze-out effects which are negligible at room temperature, become of crucial importance for analyzing the low temperature device characteristics. The conventional Pearson-Bardeen model of activation energy, used for calculation of carrier freeze-out, is based on an incomplete picture of the physics that takes place and hence, leads to inaccurate results at low temperatures. Plasma -induced bandgap narrowing becomes more pronounced in device characteristics at low temperatures. Even with modern numerical simulators, this effect is not well modeled or simulated. In this dissertation, improved models for such physical phenomena are presented. For accurate simulation of carrier freeze-out, the Pearson-Bardeen model has been extended to include the temperature dependence of the activation energy. The extraction of the model is based on the rigorous, first-principle theoretical calculations available in the literature. The new model is shown

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

Science.gov (United States)

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

Investigation on pseudomorphic InGaAs/InAlAs/InP High Electron Mobility Transistors with regard to cryogenic applications

International Nuclear Information System (INIS)

Toennesmann, A.

2003-03-01

A wide variety of new data communication applications demand ever-increasing transmission capacities. The InGaAs/InAlAs/InP layer stack based high electron mobility transistor (HEMT) is currently regarded as the most promising active device in communication systems as it has the highest cut-off frequencies of all transistor types. Due to reduced phonon scattering of the charge carriers, the HEMT is expected to exhibit even better noise and high frequency characteristics for operations at cryogenic temperatures, for instance in mixers or oscillators located in satellites or ground based systems with appropriate cooling equipment. This work focuses on the reduction of access resistances and the fabrication of very short gate lengths as the biggest technological challenges realizing highest cut-off frequencies at any temperature. In addition, the reproducibility and robustness of the implemented gate technologies are fundamental criteria for applications. In comparison to other transistor designs, the InAlAs/InGaAs HEMTs are stronger affected by undesirable, partly material dependent, short channel effects like early breakdown, high gate currents, impact ionization, the kink effect, and a shift in the threshold voltage. Measurements at liquid nitrogen temperature on transistors produced in this work provide further insight into the poorly understood interrelationship between these effects. At liquid nitrogen temperature, the cut-off frequency of 180 GHz and the maximum oscillation frequency of 300 GHz of short channel transistors at room temperature increase by 20% and 30%, respectively, while the breakdown voltage remains at high values above 8 V. (orig.)

Performance Enhancement of Power Transistors and Radiation effect

International Nuclear Information System (INIS)

Hassn, Th.A.A.

2012-01-01

The main objective of this scientific research is studying the characteristic of bipolar junction transistor device and its performance under radiation fields and temperature effect as a control element in many power circuits. In this work we present the results of experimental measurements and analytical simulation of gamma – radiation effects on the electrical characteristics and operation of power transistor types 2N3773, 2N3055(as complementary silicon power transistor are designed for general-purpose switching and amplifier applications), three samples of each type were irradiated by gamma radiation with doses, 1 K rad, 5 K rad, 10 K rad, 30 K rad, and 10 Mrad, the experimental data are utilized to establish an analytical relation between the total absorbed dose of gamma irradiation and corresponding to effective density of generated charge in the internal structure of transistor, the electrical parameters which can be measured to estimate the generated defects in the power transistor are current gain, collector current and collected emitter leakage current , these changes cause the circuit to case proper functioning. Collector current and transconductance of each device are calibrated as a function of irradiated dose. Also the threshold voltage and transistor gain can be affected and also calibrated as a function of dose. A silicon NPN power transistor type 2N3773 intended for general purpose applications, were used in this work. It was designed for medium current and high power circuits. Performance and characteristic were discusses under temperature and gamma radiation doses. Also the internal junction thermal system of the transistor represented in terms of a junction thermal resistance (Rjth). The thermal resistance changed by ΔRjth, due to the external intended, also due to the gamma doses intended. The final result from the model analysis reveals that the emitter-bias configuration is quite stable by resistance ratio RB/RE. Also the current

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

Science.gov (United States)

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Ultraclean individual suspended single-walled carbon nanotube field effect transistor

Science.gov (United States)

Liu, Siyu; Zhang, Jian; Nshimiyimana, Jean Pierre; Chi, Xiannian; Hu, Xiao; Wu, Pei; Liu, Jia; Wang, Gongtang; Sun, Lianfeng

2018-04-01

In this work, we report an effective technique of fabricating ultraclean individual suspended single-walled carbon nanotube (SWNT) transistors. The surface tension of molten silver is utilized to suspend an individual SWNT between a pair of Pd electrodes during annealing treatment. This approach avoids the usage and the residues of organic resist attached to SWNTs, resulting ultraclean SWNT devices. And the resistance per micrometer of suspended SWNTs is found to be smaller than that of non-suspended SWNTs, indicating the effect of the substrate on the electrical properties of SWNTs. The ON-state resistance (˜50 kΩ), mobility of 8600 cm2 V-1 s-1 and large on/off ratio (˜105) of semiconducting suspended SWNT devices indicate its advantages and potential applications.

Outlook and emerging semiconducting materials for ambipolar transistors.

Science.gov (United States)

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flexible Proton-Gated Oxide Synaptic Transistors on Si Membrane.

Science.gov (United States)

Zhu, Li Qiang; Wan, Chang Jin; Gao, Ping Qi; Liu, Yang Hui; Xiao, Hui; Ye, Ji Chun; Wan, Qing

2016-08-24

Ion-conducting materials have received considerable attention for their applications in fuel cells, electrochemical devices, and sensors. Here, flexible indium zinc oxide (InZnO) synaptic transistors with multiple presynaptic inputs gated by proton-conducting phosphorosilicate glass-based electrolyte films are fabricated on ultrathin Si membranes. Transient characteristics of the proton gated InZnO synaptic transistors are investigated, indicating stable proton-gating behaviors. Short-term synaptic plasticities are mimicked on the proposed proton-gated synaptic transistors. Furthermore, synaptic integration regulations are mimicked on the proposed synaptic transistor networks. Spiking logic modulations are realized based on the transition between superlinear and sublinear synaptic integration. The multigates coupled flexible proton-gated oxide synaptic transistors may be interesting for neuroinspired platforms with sophisticated spatiotemporal information processing.

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

International Nuclear Information System (INIS)

Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

1990-01-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

AlGaN/GaN HEMT structures on ammono bulk GaN substrate

International Nuclear Information System (INIS)

Kruszewski, P; Prystawko, P; Krysko, M; Smalc-Koziorowska, J; Leszczynski, M; Kasalynas, I; Nowakowska-Siwinska, A; Plesiewicz, J; Dwilinski, R; Zajac, M; Kucharski, R

2014-01-01

The work shows a successful fabrication of AlGaN/GaN high electron mobility transistor (HEMT) structures on the bulk GaN substrate grown by ammonothermal method providing an ultralow dislocation density of 10 4  cm −2  and wafers of size up to 2 inches in diameter. The AlGaN layers grown by metalorganic chemical vapor phase epitaxy method demonstrate atomically smooth surface, flat interfaces with reproduced low dislocation density as in the substrate. The test electronic devices—Schottky diodes and transistors—were designed without surface passivation and were successfully fabricated using mask-less laser-based photolithography procedures. The Schottky barrier devices demonstrate exceptionally low reverse currents smaller by a few orders of magnitude in comparison to the Schottky diodes made of AlGaN/GaN HEMT on sapphire substrate. (paper)

Direct comparison of graphene devices before and after transfer to different substrates

International Nuclear Information System (INIS)