T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

Science.gov (United States)

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Circuit and method for controlling the threshold voltage of transistors.

NARCIS (Netherlands)

2008-01-01

A control unit, for controlling a threshold voltage of a circuit unit having transistor devices, includes a reference circuit and a measuring unit. The measuring unit is configured to measure a threshold voltage of at least one sensing transistor of the circuit unit, and to measure a threshold

A spiking neuron circuit based on a carbon nanotube transistor

International Nuclear Information System (INIS)

Chen, C-L; Kim, K; Truong, Q; Shen, A; Li, Z; Chen, Y

2012-01-01

A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions. (paper)

Transistor and integrated circuit manufacture

Energy Technology Data Exchange (ETDEWEB)

Colman, D

1978-09-27

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

Transistor and integrated circuit manufacture

International Nuclear Information System (INIS)

Colman, D.

1978-01-01

This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

The Smallest Transistor-Based Nonautonomous Chaotic Circuit

DEFF Research Database (Denmark)

Lindberg, Erik; Murali, K.; Tamasevicius, Arunas

2005-01-01

A nonautonomous chaotic circuit based on one transistor, two capacitors, and two resistors is described. The mechanism behind the chaotic performance is based on “disturbance of integration.” The forward part and the reverse part of the bipolar transistor are “fighting” about the charging...

E-Learning System for Design and Construction of Amplifier Using Transistors

Science.gov (United States)

Takemura, Atsushi

2014-01-01

This paper proposes a novel e-Learning system for the comprehensive understanding of electronic circuits with transistors. The proposed e-Learning system allows users to learn a wide range of topics, encompassing circuit theories, design, construction, and measurement. Given the fact that the amplifiers with transistors are an integral part of…

Scalable fabrication of self-aligned graphene transistors and circuits on glass.

Science.gov (United States)

Liao, Lei; Bai, Jingwei; Cheng, Rui; Zhou, Hailong; Liu, Lixin; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

2012-06-13

Graphene transistors are of considerable interest for radio frequency (rf) applications. High-frequency graphene transistors with the intrinsic cutoff frequency up to 300 GHz have been demonstrated. However, the graphene transistors reported to date only exhibit a limited extrinsic cutoff frequency up to about 10 GHz, and functional graphene circuits demonstrated so far can merely operate in the tens of megahertz regime, far from the potential the graphene transistors could offer. Here we report a scalable approach to fabricate self-aligned graphene transistors with the extrinsic cutoff frequency exceeding 50 GHz and graphene circuits that can operate in the 1-10 GHz regime. The devices are fabricated on a glass substrate through a self-aligned process by using chemical vapor deposition (CVD) grown graphene and a dielectrophoretic assembled nanowire gate array. The self-aligned process allows the achievement of unprecedented performance in CVD graphene transistors with a highest transconductance of 0.36 mS/μm. The use of an insulating substrate minimizes the parasitic capacitance and has therefore enabled graphene transistors with a record-high extrinsic cutoff frequency (> 50 GHz) achieved to date. The excellent extrinsic cutoff frequency readily allows configuring the graphene transistors into frequency doubling or mixing circuits functioning in the 1-10 GHz regime, a significant advancement over previous reports (∼20 MHz). The studies open a pathway to scalable fabrication of high-speed graphene transistors and functional circuits and represent a significant step forward to graphene based radio frequency devices.

Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

Science.gov (United States)

Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

2012-01-01

Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

Design of analog integrated circuits and systems

CERN Document Server

Laker, Kenneth R

1994-01-01

This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

A 10kW series resonant converter design, transistor characterization, and base-drive optimization

Science.gov (United States)

Robson, R.; Hancock, D.

1981-01-01

Transistors are characterized for use as switches in resonant circuit applications. A base drive circuit to provide the optimal base drive to these transistors under resonant circuit conditions is developed and then used in the design, fabrication and testing of a breadboard, spaceborne type 10 kW series resonant converter.

Lateral power transistors in integrated circuits

CERN Document Server

Erlbacher, Tobias

2014-01-01

This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

Atypical transistor-based chaotic oscillators: Design, realization, and diversity

Science.gov (United States)

Minati, Ludovico; Frasca, Mattia; OświÈ©cimka, Paweł; Faes, Luca; DroŻdŻ, Stanisław

2017-07-01

In this paper, we show that novel autonomous chaotic oscillators based on one or two bipolar junction transistors and a limited number of passive components can be obtained via random search with suitable heuristics. Chaos is a pervasive occurrence in these circuits, particularly after manual adjustment of a variable resistor placed in series with the supply voltage source. Following this approach, 49 unique circuits generating chaotic signals when physically realized were designed, representing the largest collection of circuits of this kind to date. These circuits are atypical as they do not trivially map onto known topologies or variations thereof. They feature diverse spectra and predominantly anti-persistent monofractal dynamics. Notably, we recurrently found a circuit comprising one resistor, one transistor, two inductors, and one capacitor, which generates a range of attractors depending on the parameter values. We also found a circuit yielding an irregular quantized spike-train resembling some aspects of neural discharge and another one generating a double-scroll attractor, which represent the smallest known transistor-based embodiments of these behaviors. Through three representative examples, we additionally show that diffusive coupling of heterogeneous oscillators of this kind may give rise to complex entrainment, such as lag synchronization with directed information transfer and generalized synchronization. The replicability and reproducibility of the experimental findings are good.

Effect of 1MeV electron beam on transistors and circuits

International Nuclear Information System (INIS)

Lee, Tae Hoon

1998-02-01

It has been known that semiconductor devices operating in a radiation environment exhibited significant alterations of their electrical responses. Since an electron beam bombardment produces lattice damage in Si and charged defects in SiO 2 , several electrical parameters of transistors exhibit significant changes. Those parameters are the current gain of BJT (Bipolar Junction Transistor) and the threshold voltage of MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The degradation of transistors brings about that of circuits. This paper presents the results of experiments and simulations performed to study the effects of 1MeV electron beam irradiation on selected silicon transistors and circuits. For BJTs, the current gains of npn (2N3904) and pnp (2N3906) linearly decreased as the irradiation dose increased, and from this result, the damage constants, Ks were obtained as 13.65 for 2N3904 and 22.52 for 2N3906 in MGy, indicating a more stable operation in the electron radiation environment for pnp than that for npn. The decrease of current gain was due to that of minority-carrier lifetime in the base region. For MOSFETs (CD4007s), the threshold voltages of NMOS and PMOS shifted to the lower values, which was resulted from the accumulation of charge in SiO 2 . The charges could be categorized into fixed oxide charge and interfacial trap charge. From experimental results, the amounts of the induced charges could be quantitatively estimated. These degradations of transistors brought about the decrease in the voltage gain of CE (Common Emitter) amplifier and the shifts in the inverting voltage of inverter. Additionally, PSpice simulations of these circuits were carried out by modeling of irradiated transistors. The comparison of simulation with experiment showed the relatively good agreement of simulation for the degradation of circuits after irradiation

Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

Science.gov (United States)

Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

2017-05-23

Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

Design of organic complementary circuits and systems on foil

CERN Document Server

Abdinia, Sahel; Cantatore, Eugenio

2015-01-01

This book describes new approaches to fabricate complementary organic electronics, and focuses on the design of circuits and practical systems created using these manufacturing approaches. The authors describe two state-of-the-art, complementary organic technologies, characteristics and modeling of their transistors and their capability to implement circuits and systems on foil. Readers will benefit from the valuable overview of the challenges and opportunities that these extremely innovative technologies provide. ·         Demonstrates first circuits implemented using specific complementary organic technologies, including first printed analog to digital converter, first dynamic logic on foil and largest complementary organic circuit ·         Includes step-by-step design from single transistor level to complete systems on foil ·         Provides a platform for comparing state-of-the-art complementary organic technologies and for comparing these with other similar technologies, spec...

Air-stable complementary-like circuits based on organic ambipolar transistors

NARCIS (Netherlands)

Anthopoulos, Thomas D.; Setayesh, Sepas; Smits, Edsger; Cantatore, Eugenio; Boer ,de Bert; Blom, Paul W. M.; de Leeuw, Dago M.; Cölle, Michael

2006-01-01

Air stable complementary-like circuits, such as voltage inverters (see figure) and ring oscillators, are fabricated using ambipolar organic transistors based on a nickel dithiolene derivative. In addition to the complementary-like character of the circuits, the technology is very simple and fully

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

Science.gov (United States)

Shin, SeungJun; Yu, YunSeop; Choi, JungBum

2008-10-01

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits.

Science.gov (United States)

Ghavami, Behnam; Raji, Mohsen; Pedram, Hossein

2011-08-26

Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process.

Push-pull converter with energy saving circuit for protecting switching transistors from peak power stress

Science.gov (United States)

Mclyman, W. T. (Inventor)

1981-01-01

In a push-pull converter, switching transistors are protected from peak power stresses by a separate snubber circuit in parallel with each comprising a capacitor and an inductor in series, and a diode in parallel with the inductor. The diode is connected to conduct current of the same polarity as the base-emitter juction of the transistor so that energy stored in the capacitor while the transistor is switched off, to protect it against peak power stress, discharges through the inductor when the transistor is turned on, and after the capacitor is discharges through the diode. To return this energy to the power supply, or to utilize this energy in some external circuit, the inductor may be replaced by a transformer having its secondary winding connected to the power supply or to the external circuit.

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Directory of Open Access Journals (Sweden)

Kwang-Jow Gan

2016-06-01

Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

Advanced Breakdown Modeling for Solid-State Circuit Design

NARCIS (Netherlands)

Milovanovi?, V.

2010-01-01

Modeling of the effects occurring outside the usual region of application of semiconductor devices is becoming more important with increasing demands set upon electronic systems for simultaneous speed and output power. Analog integrated circuit designers are forced to enter regimes of transistor

Design of a Negative Differential Resistance Circuit Element Using Single-Electron Transistors

Science.gov (United States)

Dixon, D. C.; Heij, C. P.; Hadley, P.; Mooij, J. E.

1998-03-01

Electronic circuit elements displaying negative differential resistance (NDR), such as tunnel diodes, have a wide variety of device applications, including oscillators, amplifiers, logic, and memory. We present a two-terminal device using two single-electron transistors (SET's) that demonstrates an NDR profile tuneable with gate voltages. If the capacitive coupling between the SET's is sufficiently larger than the junction capacitances, the device exhibits multiply-peaked NDR, allowing its use as a multi-valued digital element. We will also report recent experimental progress in measurements of such a device, fabricated using standard Al tunnel junctions, but with an additional overlap capacitor to allow the required inter-SET coupling.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit includes a light emitting diode which from time to time illuminates a photo-transistor, the photo-transistor serving when its output reaches a predetermined value to operate a trigger circuit. In order to allow for aging of the components, the current flow through the diode is increased when the output from the transistor falls below a known level. Conveniently, this is achieved by having a transistor in parallel with the diode, and turning the transistor off when the output from the phototransistor becomes too low. The circuit is designed to control the ignition system in an automobile engine.

Experimental study on short-circuit characteristics of the new protection circuit of insulated gate bipolar transistor

International Nuclear Information System (INIS)

Ji, In-Hwan; Choi, Young-Hwan; Ha, Min-Woo; Han, Min-Koo; Choi, Yearn-Ik

2006-01-01

A new protection circuit employing the collector to emitter voltage (V CE ) sensing scheme for short-circuit withstanding capability of the insulated gate bipolar transistor (IGBT) is proposed and verified by experimental results. Because the current path between the gate and collector can be successfully eliminated in the proposed protection circuit, the power consumption can be reduced and the gate input impedance can be increased. Previous study is limited to dc characteristics. However, experimental results show that the proposed protection circuit successfully reduces the over-current of main IGBT by 80.4% under the short-circuit condition

Digitally-assisted analog and RF CMOS circuit design for software-defined radio

CERN Document Server

Okada, Kenichi

2011-01-01

This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millions of transistors, as well as several real examples from the most recent research results.

A novel technique for CAD-optimization of analog circuits with bipolar transistors

Directory of Open Access Journals (Sweden)

B. Dimov

2009-05-01

Full Text Available In this paper, a novel approach for robust automatic optimization of analog circuits with bipolar transistors is presented. It includes additional formal parameters into the device model cards, which sweep the model parameters smoothly between the different device types. In this way, not only the sizing, but also the choice of the device type is committed to the optimization tool, thus improving the efficiency of the design process significantly.

Potential of carbon nanotube field effect transistors for analogue circuits

KAUST Repository

Hayat, Khizar; Cheema, Hammad; Shamim, Atif

2013-01-01

This Letter presents a detailed comparison of carbon nanotube field effect transistors (CNFETs) and metal oxide semiconductor field effect transistors (MOSFETs) with special focus on carbon nanotube FET's potential for implementing analogue circuits in the mm-wave and sub-terahertz range. The latest CNFET lithographic dimensions place it at-par with complementary metal oxide semiconductor in terms of current handling capability, whereas the forecasted improvement in the lithography enables the CNFETs to handle more than twice the current of MOSFETs. The comparison of RF parameters shows superior performance of CNFETs with a g m , f T and f max of 2.7, 2.6 and 4.5 times higher, respectively. MOSFET- and CNFET-based inverter, three-stage ring oscillator and LC oscillator have been designed and compared as well. The CNFET-based inverters are found to be ten times faster, the ring oscillator demonstrates three times higher oscillation frequency and CNFET-based LC oscillator also shows improved performance than its MOSFET counterpart.

Potential of carbon nanotube field effect transistors for analogue circuits

KAUST Repository

Hayat, Khizar

2013-05-11

This Letter presents a detailed comparison of carbon nanotube field effect transistors (CNFETs) and metal oxide semiconductor field effect transistors (MOSFETs) with special focus on carbon nanotube FET\\'s potential for implementing analogue circuits in the mm-wave and sub-terahertz range. The latest CNFET lithographic dimensions place it at-par with complementary metal oxide semiconductor in terms of current handling capability, whereas the forecasted improvement in the lithography enables the CNFETs to handle more than twice the current of MOSFETs. The comparison of RF parameters shows superior performance of CNFETs with a g m , f T and f max of 2.7, 2.6 and 4.5 times higher, respectively. MOSFET- and CNFET-based inverter, three-stage ring oscillator and LC oscillator have been designed and compared as well. The CNFET-based inverters are found to be ten times faster, the ring oscillator demonstrates three times higher oscillation frequency and CNFET-based LC oscillator also shows improved performance than its MOSFET counterpart.

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

Science.gov (United States)

Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

2016-08-10

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Silicon nanowire transistors

CERN Document Server

Bindal, Ahmet

2016-01-01

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

Science.gov (United States)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2006-01-01

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits

Free-Standing Organic Transistors and Circuits with Sub-Micron Thicknesses

Science.gov (United States)

Fukuda, Kenjiro; Sekine, Tomohito; Shiwaku, Rei; Morimoto, Takuya; Kumaki, Daisuke; Tokito, Shizuo

2016-01-01

The realization of wearable electronic devices with extremely thin and flexible form factors has been a major technological challenge. While substrates typically limit the thickness of thin-film electronic devices, they are usually necessary for their fabrication and functionality. Here we report on ultra-thin organic transistors and integrated circuits using device components whose substrates that have been removed. The fabricated organic circuits with total device thicknesses down to 350 nm have electrical performance levels close to those fabricated on conventional flexible substrates. Moreover, they exhibit excellent mechanical robustness, whereby their static and dynamic electrical characteristics do not change even under 50% compressive strain. Tests using systematically applied compressive strains reveal that these free-standing organic transistors possess anisotropic mechanical stability, and a strain model for a multilayer stack can be used to describe the strain in this sort of ultra-thin device. These results show the feasibility of ultimate-thin organic electronic devices using free-standing constructions. PMID:27278828

Tunneling field effect transistor technology

CERN Document Server

Chan, Mansun

2016-01-01

This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency. · Provides comprehensive reference to tunneling field effect transistors (TFETs); · Covers all aspects of TFETs, from device process to modeling and applications; · Enables design of power-efficient integrated circuits, with low power consumption TFETs.

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits

International Nuclear Information System (INIS)

Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S.; Uren, M.J.; Brunson, K.M.

1999-01-01

This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

Solid-state circuits

CERN Document Server

Pridham, G J

2013-01-01

Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

A current-mode multi-valued adder circuit for multi-operand addition

Science.gov (United States)

Cini, Ugur; Morgül, Avni

2011-06-01

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

Science.gov (United States)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

The design of a new spiking neuron using dual work function silicon nanowire transistors

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2007-01-01

A new spike neuron cell is designed using vertically grown, undoped silicon nanowire transistors. This study presents an entire design cycle from designing and optimizing vertical nanowire transistors for minimal power dissipation to realizing a neuron cell and measuring its dynamic power consumption, performance and layout area. The design cycle starts with determining individual metal gate work functions for NMOS and PMOS transistors as a function of wire radius to produce a 300 mV threshold voltage. The wire radius and effective channel length are subsequently varied to find a common body geometry for both transistors that yields smaller than 1 pA OFF current while producing maximum drive currents. A spike neuron cell is subsequently built using these transistors to measure its transient performance, power dissipation and layout area. Post-layout simulation results indicate that the neuron consumes 0.397 μW to generate a +1 V and 1.12 μW to generate a -1 V output pulse for a fan-out of five synapses at 500 MHz; the power dissipation increases by approximately 3 nW for each additional synapse at the output for generating either pulse. The neuron circuit occupies approximately 0.27 μm 2

Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

OpenAIRE

Hills, Gage; Zhang, Jie; Shulaker, Max Marcel; Wei, Hai; Lee, Chi-Shuen; Balasingam, Arjun; Wong, H. -S. Philip; Mitra, Subhasish

2015-01-01

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfor...

Design of chaotic analog noise generators with logistic map and MOS QT circuits

International Nuclear Information System (INIS)

Vazquez-Medina, R.; Diaz-Mendez, A.; Rio-Correa, J.L. del; Lopez-Hernandez, J.

2009-01-01

In this paper a method to design chaotic analog noise generators using MOS transistors is presented. Two aspects are considered, the determination of operation regime of the MOS circuit and the statistical distribution of its output signal. The operation regime is related with the transconductance linear (TL: translinear) principle. For MOS transistors this principle was originally formulated in weak inversion regime; but, strong inversion regimen is used because in 1991, Seevinck and Wiegerink made the generalization for this principle. The statistical distribution of the output signal on the circuit, which should be a uniform distribution, is related with the parameter value that rules the transfer function of the circuit, the initial condition (seed) in the circuit and its operation as chaotic generator. To show these concepts, the MOS Quadratic Translinear circuit proposed by Wiegerink in 1993 was selected and it is related with the logistic map and its properties. This circuit will operate as noise generator if it works in strong inversion regime using current-mode approach when the parameter that rules the transfer function is higher than the onset chaos value (3.5699456...) for the logistic map.

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

Science.gov (United States)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Gigahertz flexible graphene transistors for microwave integrated circuits.

Science.gov (United States)

Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

2014-08-26

Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations.

Design and Simulation of a 6-Bit Successive-Approximation ADC Using Modeled Organic Thin-Film Transistors

Directory of Open Access Journals (Sweden)

Huyen Thanh Pham

2016-01-01

Full Text Available We have demonstrated a method for using proper models of pentacene P-channel and fullerene N-channel thin-film transistors (TFTs in order to design and simulate organic integrated circuits. Initially, the transistors were fabricated, and we measured their main physical and electrical parameters. Then, these organic TFTs (OTFTs were modeled with support of an organic process design kit (OPDK added in Cadence. The key specifications of the modeled elements were extracted from measured data, whereas the fitting ones were elected to replicate experimental curves. The simulating process proves that frequency responses of the TFTs cover all biosignal frequency ranges; hence, it is reasonable to deploy the elements to design integrated circuits used in biomedical applications. Complying with complementary rules, the organic circuits work properly, including logic gates, flip-flops, comparators, and analog-to-digital converters (ADCs as well. The proposed successive-approximation-register (SAR ADC consumes a power of 883.7 µW and achieves an ENOB of 5.05 bits, a SNR of 32.17 dB at a supply voltage of 10 V, and a sampling frequency of about 2 KHz.

Failure of the integrated circuits involving complementary MOS transistors under thermal and ionizing radiation stresses

International Nuclear Information System (INIS)

Sarrabayrouse, G.; Rossel, P.; Buxo, J.; Vialaret, G.

Some criteria for reliability and sorting of complementary MOS transistor integrated circuits are proposed, that take account for special environmental stresses near plane reactors or nuclear reactor cores. An analysis of the damaging causes for these circuits at high and low temperatures is proposed, results obtained on the evolution of these devices under irradiation and irradiation behaviors are discussed. The whole set of experiments has been carried out on CD 4007 AD(K) circuits [fr

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

KAUST Repository

Gutiérrez-Heredia, Gerardo

2010-10-04

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/ parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 μA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 μA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O 3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas \\'parylene only\\' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented. © 2010 IOP Publishing Ltd.

A flexible organic active matrix circuit fabricated using novel organic thin film transistors and organic light-emitting diodes

KAUST Repository

Gutié rrez-Heredia, Gerardo; Gonzá lez, Luis A.; Alshareef, Husam N.; Gnade, Bruce E.; Quevedo-Ló pez, Manuel Angel Quevedo

2010-01-01

We present an active matrix circuit fabricated on plastic (polyethylene naphthalene, PEN) and glass substrates using organic thin film transistors and organic capacitors to control organic light-emitting diodes (OLEDs). The basic circuit is fabricated using two pentacene-based transistors and a capacitor using a novel aluminum oxide/parylene stack (Al2O3/ parylene) as the dielectric for both the transistor and the capacitor. We report that our circuit can deliver up to 15 μA to each OLED pixel. To achieve 200 cd m-2 of brightness a 10 μA current is needed; therefore, our approach can initially deliver 1.5× the required current to drive a single pixel. In contrast to parylene-only devices, the Al2O 3/parylene stack does not fail after stressing at a field of 1.7 MV cm-1 for >10 000 s, whereas 'parylene only' devices show breakdown at approximately 1000 s. Details of the integration scheme are presented. © 2010 IOP Publishing Ltd.

Investigation of high sensitivity radio-frequency readout circuit based on AlGaN/GaN high electron mobility transistor

International Nuclear Information System (INIS)

Zhang Xiao-Yu; Sun Jian-Dong; Li Xin-Xing; Zhou Yu; Lü Li; Qin Hua; Tan Ren-Bing

2015-01-01

An AlGaN/GaN high electron mobility transistor (HEMT) device is prepared by using a semiconductor nanofabrication process. A reflective radio-frequency (RF) readout circuit is designed and the HEMT device is assembled in an RF circuit through a coplanar waveguide transmission line. A gate capacitor of the HEMT and a surface-mounted inductor on the transmission line are formed to generate LC resonance. By tuning the gate voltage V g , the variations of gate capacitance and conductance of the HEMT are reflected sensitively from the resonance frequency and the magnitude of the RF reflection signal. The aim of the designed RF readout setup is to develop a highly sensitive HEMT-based detector. (paper)

Printed organic thin-film transistor-based integrated circuits

International Nuclear Information System (INIS)

Mandal, Saumen; Noh, Yong-Young

2015-01-01

Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted. (paper)

Microwave field-efffect transistors theory, design, and application

CERN Document Server

Pengelly, Raymond

1994-01-01

This book covers the use of devices in microwave circuits and includes such topics as semiconductor theory and transistor performance, CAD considerations, intermodulation, noise figure, signal handling, S-parameter mapping, narrow- and broadband techniques, packaging and thermal considerations.

Fabrication and simulation of organic transistors and functional circuits

Energy Technology Data Exchange (ETDEWEB)

Taylor, D. Martin, E-mail: d.m.taylor@bangor.ac.uk [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Patchett, Eifion R.; Williams, Aled [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Ding, Ziqian; Assender, Hazel E. [Department of Materials, Oxford University, Parks Road, Oxford OX1 3PH (United Kingdom); Morrison, John J.; Yeates, Stephen G. [School of Chemistry, University of Manchester, Oxford Road, Manchester M13 9PL (United Kingdom)

2015-07-29

Highlights: • Development of roll-to-roll fabrication protocol for organic TFTs and circuits. • Bottom-gate polystyrene/DNTT TFTs much better than top-gate TFTs. • High-yield and high mobility with polystyrene-buffered TPGDA. • Fabrication of functional circuits – ring oscillators and logic gates. • New baseline process allows TFT parameter extraction and circuit simulation. - Abstract: We report the development of a vacuum-evaporation route for the roll-to-roll fabrication of functioning organic circuits. A number of key findings and observations are highlighted which influenced the eventual fabrication protocol adopted. Initially, the role of interface roughness in determining carrier mobility in thin film transistors (TFTs) is investigated. Then it is shown that TFT yield is higher for devices fabricated on a flash-evaporated-plasma-polymerised tri(propyleneglycol) diacrylate (TPGDA) gate dielectric than for TFTs based on a spin-coated polystyrene (PS) dielectric. However, a degradation in mobility is observed which is attributed to the highly polar TPGDA surface. It is shown that high mobility, low gate-leakage currents and excellent stability are restored when the surface of TPGDA was buffered with a thin, spin-coated PS film. The resulting baseline process allowed arrays of functional circuits such as ring oscillators, NOR/NAND logic gates and S–R latches to be fabricated with high yield and their performance to be simulated.

Simulation of a spiking neuron circuit using carbon nanotube transistors

Energy Technology Data Exchange (ETDEWEB)

Najari, Montassar, E-mail: malnjar@jazanu.edu.sa [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); IKCE unit, Jazan University, Jazan (Saudi Arabia); El-Grour, Tarek, E-mail: grour-tarek@hotmail.fr [Departement of Physics, Faculty of Sciences, University of Gabes, Gabes (Tunisia); Jelliti, Sami, E-mail: sjelliti@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Hakami, Othman Mousa, E-mail: omhakami@jazanu.edu.sa [IKCE unit, Jazan University, Jazan (Saudi Arabia); Faculty of Sciences, Jazan University, Jazan (Saudi Arabia)

2016-06-10

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

Simulation of a spiking neuron circuit using carbon nanotube transistors

International Nuclear Information System (INIS)

Najari, Montassar; El-Grour, Tarek; Jelliti, Sami; Hakami, Othman Mousa

2016-01-01

Neuromorphic engineering is related to the existing analogies between the physical semiconductor VLSI (Very Large Scale Integration) and biophysics. Neuromorphic systems propose to reproduce the structure and function of biological neural systems for transferring their calculation capacity on silicon. Since the innovative research of Carver Mead, the neuromorphic engineering continues to emerge remarkable implementation of biological system. This work presents a simulation of an elementary neuron cell with a carbon nanotube transistor (CNTFET) based technology. The model of the cell neuron which was simulated is called integrate and fire (I&F) model firstly introduced by G. Indiveri in 2009. This circuit has been simulated with CNTFET technology using ADS environment to verify the neuromorphic activities in terms of membrane potential. This work has demonstrated the efficiency of this emergent device; i.e CNTFET on the design of such architecture in terms of power consumption and technology integration density.

Large signal S-parameters: modeling and radiation effects in microwave power transistors

International Nuclear Information System (INIS)

Graham, E.D. Jr.; Chaffin, R.J.; Gwyn, C.W.

1973-01-01

Microwave power transistors are usually characterized by measuring the source and load impedances, efficiency, and power output at a specified frequency and bias condition in a tuned circuit. These measurements provide limited data for circuit design and yield essentially no information concerning broadbanding possibilities. Recently, a method using large signal S-parameters has been developed which provides a rapid and repeatable means for measuring microwave power transistor parameters. These large signal S-parameters have been successfully used to design rf power amplifiers. Attempts at modeling rf power transistors have in the past been restricted to a modified Ebers-Moll procedure with numerous adjustable model parameters. The modified Ebers-Moll model is further complicated by inclusion of package parasitics. In the present paper an exact one-dimensional device analysis code has been used to model the performance of the transistor chip. This code has been integrated into the SCEPTRE circuit analysis code such that chip, package and circuit performance can be coupled together in the analysis. Using []his computational tool, rf transistor performance has been examined with particular attention given to the theoretical validity of large-signal S-parameters and the effects of nuclear radiation on device parameters. (auth)

Design and characterization of radiation resistant integrated circuits for the LHC particle detectors using deep sub-micron CMOS technologies

International Nuclear Information System (INIS)

Anelli, Giovanni Maria

2000-01-01

The electronic circuits associated with the particle detectors of the CERN Large Hadron Collider (LHC) have to work in a highly radioactive environment. This work proposes a methodology allowing the design of radiation resistant integrated circuits using the commercial sub-micron CMOS technology. This method uses the intrinsic radiation resistance of ultra-thin grid oxides, the technology of enclosed layout transistors (ELT), and the protection rings to avoid the radio-induced creation of leakage currents. In order to check the radiation tolerance level, several test structures have been designed and tested with different radiation sources. These tests have permitted to study the physical phenomena responsible for the damages induced by the radiations and the possible remedies. Then, the particular characteristics of ELT transistors and their influence on the design of complex integrated circuits has been explored. The modeling of the W/L ratio, the asymmetries (for instance in the output conductance) and the performance of ELT couplings have never been studied yet. The noise performance of the 0.25 μ CMOS technology, used in the design of several integrated circuits of the LHC detectors, has been characterized before and after irradiation. Finally, two integrated circuits designed using the proposed method are presented. The first one is an analogic memory and the other is a circuit used for the reading of the signals of one of the LHC detectors. Both circuits were irradiated and have endured very high doses practically without any sign of performance degradation. (J.S.)

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

Science.gov (United States)

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Analog circuit design designing dynamic circuit response

CERN Document Server

Feucht, Dennis

2010-01-01

This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

Flexible integrated diode-transistor logic (DTL) driving circuits based on printed carbon nanotube thin film transistors with low operation voltage.

Science.gov (United States)

Liu, Tingting; Zhao, Jianwen; Xu, Weiwei; Dou, Junyan; Zhao, Xinluo; Deng, Wei; Wei, Changting; Xu, Wenya; Guo, Wenrui; Su, Wenming; Jie, Jiansheng; Cui, Zheng

2018-01-03

Fabrication and application of hybrid functional circuits have become a hot research topic in the field of printed electronics. In this study, a novel flexible diode-transistor logic (DTL) driving circuit is proposed, which was fabricated based on a light emitting diode (LED) integrated with printed high-performance single-walled carbon nanotube (SWCNT) thin-film transistors (TFTs). The LED, which is made of AlGaInP on GaAs, is commercial off-the-shelf, which could generate free electrical charges upon white light illumination. Printed top-gate TFTs were made on a PET substrate by inkjet printing high purity semiconducting SWCNTs (sc-SWCNTs) ink as the semiconductor channel materials, together with printed silver ink as the top-gate electrode and printed poly(pyromellitic dianhydride-co-4,4'-oxydianiline) (PMDA/ODA) as gate dielectric layer. The LED, which is connected to the gate electrode of the TFT, generated electrical charge when illuminated, resulting in biased gate voltage to control the TFT from "ON" status to "OFF" status. The TFTs with a PMDA/ODA gate dielectric exhibited low operating voltages of ±1 V, a small subthreshold swing of 62-105 mV dec -1 and ON/OFF ratio of 10 6 , which enabled DTL driving circuits to have high ON currents, high dark-to-bright current ratios (up to 10 5 ) and good stability under repeated white light illumination. As an application, the flexible DTL driving circuit was connected to external quantum dot LEDs (QLEDs), demonstrating its ability to drive and to control the QLED.

Radiation effects on junction field-effect transistors (JFETS), MOSFETs, and bipolar transistors, as related to SSC circuit design

International Nuclear Information System (INIS)

Kennedy, E.J.; Alley, G.T.; Britton, C.L. Jr.; Skubic, P.L.; Gray, B.; Wu, A.

1990-01-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular, at currents ≤1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier

Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits; Quantification, modelisation et conception prenant en compte les etats anterieurs des signaux dans les circuits mixtes SOI/SOS

Energy Technology Data Exchange (ETDEWEB)

Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S. [Southampton Univ., Dept. of Electronics and Computer Sciences (United Kingdom); Uren, M.J.; Brunson, K.M. [DERA Farnborough, GU, Hants (United Kingdom)

1999-07-01

This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

Performance Enhancement of Power Transistors and Radiation effect

International Nuclear Information System (INIS)

Hassn, Th.A.A.

2012-01-01

The main objective of this scientific research is studying the characteristic of bipolar junction transistor device and its performance under radiation fields and temperature effect as a control element in many power circuits. In this work we present the results of experimental measurements and analytical simulation of gamma – radiation effects on the electrical characteristics and operation of power transistor types 2N3773, 2N3055(as complementary silicon power transistor are designed for general-purpose switching and amplifier applications), three samples of each type were irradiated by gamma radiation with doses, 1 K rad, 5 K rad, 10 K rad, 30 K rad, and 10 Mrad, the experimental data are utilized to establish an analytical relation between the total absorbed dose of gamma irradiation and corresponding to effective density of generated charge in the internal structure of transistor, the electrical parameters which can be measured to estimate the generated defects in the power transistor are current gain, collector current and collected emitter leakage current , these changes cause the circuit to case proper functioning. Collector current and transconductance of each device are calibrated as a function of irradiated dose. Also the threshold voltage and transistor gain can be affected and also calibrated as a function of dose. A silicon NPN power transistor type 2N3773 intended for general purpose applications, were used in this work. It was designed for medium current and high power circuits. Performance and characteristic were discusses under temperature and gamma radiation doses. Also the internal junction thermal system of the transistor represented in terms of a junction thermal resistance (Rjth). The thermal resistance changed by ΔRjth, due to the external intended, also due to the gamma doses intended. The final result from the model analysis reveals that the emitter-bias configuration is quite stable by resistance ratio RB/RE. Also the current

Gallium nitride based transistors for high-efficiency microwave switch-mode amplifiers

Energy Technology Data Exchange (ETDEWEB)

Maroldt, Stephan

2012-07-01

Highly-efficient switch-mode power amplifiers form key elements in future fully-digital base stations for mobile communication. This novel digital base station concept reduces system energy consumption, complexity, size and costs, while the flexibility in terms of multi-band operation and signal modulation improves. In this work, innovative core circuits for digital high-efficiency class-D and class-S power amplifiers based on gallium nitride (GaN) technology were developed for the application in digital base stations. A combination of optimized GaN devices and improvements in circuit design allow a highly-efficient switch-mode operation at mobile communication frequencies between 0.45 GHz and 2 GHz. Transistor device modeling for switch-mode operation, the simulation environment, and a broadband measurement system were established for the design and evaluation of digital switchmode power amplifiers. The design of broadband core circuits for switch-mode amplifier concepts was analyzed for dual-stage amplifier circuits, using an initial GaN technology with a gate length of 0.25 {mu}m. A speed-enhanced driver stage improved the circuit switching speed sufficiently above 1 GHz. Speed and efficiency of the amplifier core circuits were studied related to transistor parameters like cut-off frequency or gate capacitance. A reduced gate length was found to improve the switching speed, while a lower on-resistance allows the reduction of the inherent static losses of the GaN-based switches. Apart from this, the restriction of a 50 Ohm environment was found to be a major output power and switching speed limitation, due to a poor switching drive capability of the input capacitance of the GaN circuit. Finally, the optimized transistor and circuit design with an output gate width of 1.2 mm were effectively implemented in the given environment for an operation up to 2 GHz with a high drain efficiency of >65% and a digital output power of 5 W. A maximum output power of 9.7 W and a

Logic circuits based on individual semiconducting and metallic carbon-nanotube devices

International Nuclear Information System (INIS)

Ryu, Hyeyeon; Kaelblein, Daniel; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Klauk, Hagen; Weitz, R Thomas; Schmidt, Oliver G

2010-01-01

Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

KAUST Repository

Hanna, Amir

2015-12-04

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

NARCIS (Netherlands)

Houin, G.J.R.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

2016-01-01

The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance

Physical limits of silicon transistors and circuits

International Nuclear Information System (INIS)

Keyes, Robert W

2005-01-01

A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

Science.gov (United States)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

Science.gov (United States)

Karaki, Nobuo; Nanmoto, Takashi; Inoue, Satoshi

This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

Universal power transistor base drive control unit

Science.gov (United States)

Gale, Allan R.; Gritter, David J.

1988-01-01

A saturation condition regulator system for a power transistor which achieves the regulation objectives of a Baker clamp but without dumping excess base drive current into the transistor output circuit. The base drive current of the transistor is sensed and used through an active feedback circuit to produce an error signal which modulates the base drive current through a linearly operating FET. The collector base voltage of the power transistor is independently monitored to develop a second error signal which is also used to regulate base drive current. The current-sensitive circuit operates as a limiter. In addition, a fail-safe timing circuit is disclosed which automatically resets to a turn OFF condition in the event the transistor does not turn ON within a predetermined time after the input signal transition.

Pulse generator circuit triggerable by nuclear radiation

International Nuclear Information System (INIS)

Fredrickson, P.B.

1980-01-01

A pulse generator circuit triggerable by a pulse of nuclear radiation is described. The pulse generator circuit includes a pair of transistors arranged, together with other electrical components, in the topology of a standard monostable multivibrator circuit. The circuit differs most significantly from a standard monostable multivibrator circuit in that the circuit is adapted to be triggered by a pulse of nuclear radiation rather than electrically and the transistors have substantially different sensitivities to radiation, due to different physical and electrical characteristics and parameters. One of the transistors is employed principally as a radiation detector and is in a normally non-conducting state and the other transistor is normally in a conducting state. When the circuit is exposed to a pulse of nuclear radiation, currents are induced in the collector-base junctions of both transistors but, due to the different radiation sensitivities of the transistors, the current induced in the collector-base junction of the radiation-detecting transistor is substantially greater than that induced in the collector-base junction of the other transistor. The pulse of radiation causes the radiation-detecting transistor to operate in its conducting state, causing the other transistor to operate in its non-conducting state. As the radiation-detecting transistor operates in its conducting state, an output signal is produced at an output terminal connected to the radiation-detecting transistor indicating the presence of a predetermined intensity of nuclear radiation

Design and Preliminary Results of a Feedback Circuit for Plasma Displacement Control in IR-T1 Tokamak

International Nuclear Information System (INIS)

TalebiTaher, A.; Ghoranneviss, M.; Tarkeshian, R.; Salem, M. K.; Khorshid, P.

2008-01-01

Since displacement is very important for plasma position control, in IR-T1 tokamak a combination of two cosine coils and two saddle sine coils is used for horizontal displacement measurement. According to the multiple moment theory, the output of these coils linearly depends to radial displacement of plasma column. A new circuit for adding these signals to feedback system designed and unwanted effects of other fields in final output compensated. After compensation and calibration of the system, the output of horizontal displacement circuits applied to feedback control system. By considers the required auxiliary vertical field, a proportional amplifier and driver circuit are constructed to drive power transistors these power transistors switch the feedback bank capacitors. In the experiment, a good linear proportionality between displacement and output observed by applying an appropriate feedback field, the linger confinement time in IR-T1 tokamak obtained, applying this system to discharge increased the plasma duration and realizes repetitive discharges

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1968-01-01

Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

Device Process and Circuit Application Interaction for Harsh Electronics: Hf-In-Zn-O Thin Film Transistors as an Example

KAUST Repository

Ho, Chih-Hsiang

2017-06-27

The effects of Hf content on the radiation hardness of Hf-In-Zn-O thin-film transistors (HIZO TFTs) and HIZO TFTbased circuits are systemically examined. The evaluated circuits, including current-starved ring oscillator, energy harvesting and RF circuits are essential for space electronic systems. It is shown that HIZO TFTs with low Hf concentration have better initial performance while TFTs with high Hf concentration are more stable against radiation. On the other hand, for circuit application, the stable HIZO TFTs are not necessarily preferred for all circuits. The work demonstrates that understanding the device-circuit interactions is necessary for device optimization and circuit reliability improvements for harsh electronic systems.

Device Process and Circuit Application Interaction for Harsh Electronics: Hf-In-Zn-O Thin Film Transistors as an Example

KAUST Repository

Ho, Chih-Hsiang; Tsai, Dung-Sheng; Lu, Chao; Kim, Soo Youn; Mungan, Selin; Yang, Shih-Guo; Zhang, Yuanzhi; He, Jr-Hau

2017-01-01

The effects of Hf content on the radiation hardness of Hf-In-Zn-O thin-film transistors (HIZO TFTs) and HIZO TFTbased circuits are systemically examined. The evaluated circuits, including current-starved ring oscillator, energy harvesting and RF circuits are essential for space electronic systems. It is shown that HIZO TFTs with low Hf concentration have better initial performance while TFTs with high Hf concentration are more stable against radiation. On the other hand, for circuit application, the stable HIZO TFTs are not necessarily preferred for all circuits. The work demonstrates that understanding the device-circuit interactions is necessary for device optimization and circuit reliability improvements for harsh electronic systems.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

Science.gov (United States)

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMS

KAUST Repository

Dadgour, Hamed F.

2010-01-01

Nano-Electro-Mechanical Switches (NEMS) offer the prospect of improved energy-efficiency in digital circuits due to their near-zero subthreshold leakage and extremely low subthreshold swing values. Among the different approaches of implementing NEMS, laterallyactuated double-gate NEMS devices have attracted much attention as they provide unique and exciting circuit design opportunities. For instance, this paper demonstrates that compact XOR/XNOR gates can be implemented using only two such NEMS transistors. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms) are grouped only in horizontal and/or vertical directions; the diagonal (or zig-zag) grouping of adjacent "1s" is not an option due to the absence of compact XOR/XNOR gates. However, this work demonstrates, for the first time ever, that in lateral double-gate NEMS-based circuits, grouping of minterms is possible in horizontal and vertical as well as diagonal fashions. This is because the diagonal groupings of minterms require XOR/XNOR operations, which are available in such NEMS-based circuits at minimal costs. This novel design paradigm facilitates more compact implementations of Boolean functions and thus, considerably improves their energy-efficiency. For example, a lateral NEMS-based full-adder is implemented using less than half the number of transistors, which is required by a CMOS-based full-adder. Furthermore, circuit simulations are performed to evaluate the energy-efficiencies of the NEMS-based 32-bit carry-save adders compared to their standard CMOS-based counterparts. Copyright 2010 ACM.

High voltage short plus generation based on avalanche circuit

International Nuclear Information System (INIS)

Hu Yuanfeng; Yu Xiaoqi

2006-01-01

Simulate the avalanche circuit in series with PSPICE module, design the high voltage short plus generation circuit by avalanche transistor in series for the sweep deflection circuit of streak camera. The output voltage ranges 1.2 KV into 50 ohm load. The rise time of the circuit is less than 3 ns. (authors)

High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

Energy Technology Data Exchange (ETDEWEB)

Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

2014-08-11

High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

The circuit designer's companion

CERN Document Server

Williams, Tim

1991-01-01

The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

Radiation effects on JFETS, MOSFETS, and bipolar transistors, as related to SSC circuit design

Energy Technology Data Exchange (ETDEWEB)

Kennedy, E J; Gray, B; Wu, A [Dept. of Electrical and Computer Engineering, Univ. of Tennessee, Knoxville, TN (United States); Alley, G T; Britton, Jr, C L [Oak Ridge National Lab., TN (United States); Skubic, P L [Univ. of Oklahoma, Dept. of Physics and Astronomy, Norman, OK (United States)

1991-10-01

Some results of radiation effects on selected junction field-effect transistors, MOS field-effect transistors, and bipolar junction transistors are presented. The evaluations include dc parameters, as well as capacitive variations and noise evaluations. The tests are made at the low current and voltage levels (in particular at currents {<=} 1 mA) that are essential for the low-power regimes required by SSC circuitry. Detailed noise data are presented both before and after 5-Mrad (gamma) total-dose exposure. SPICE radiation models for three high-frequency bipolar processes are compared for a typical charge-sensitive preamplifier. (orig.).

Analog circuit design

CERN Document Server

Dobkin, Bob

2012-01-01

Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1972-01-01

Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

Transistor challenges - A DRAM perspective

International Nuclear Information System (INIS)

Faul, Juergen W.; Henke, Dietmar

2005-01-01

Key challenges of the transistor scaling from a DRAM perspective will be reviewed. Both, array transistors as well as DRAM support devices face challenges that differ essentially from high performance logic device scaling. As a major difference, retention time and standby current requirements characterize special boundary conditions in the DRAM device design. Array device scaling is determined by a chip size driven aggressive node scaling. To continue scaling, major innovations need to be introduced into state-of-the-art planar array transistors. Alternatively, non planar device concepts will have to be evaluated. Support device design for DRAMs is driven by today's market demand for increased chip performances at little to no extra cost. Major innovations are required to continue that path. Besides this strive for performance increase, special limitations for 'on pitch' circuits at the array edge will come up due to the aggressive cell size scaling

Total dose and dose rate models for bipolar transistors in circuit simulation.

Energy Technology Data Exchange (ETDEWEB)

Campbell, Phillip Montgomery; Wix, Steven D.

2013-05-01

The objective of this work is to develop a model for total dose effects in bipolar junction transistors for use in circuit simulation. The components of the model are an electrical model of device performance that includes the effects of trapped charge on device behavior, and a model that calculates the trapped charge densities in a specific device structure as a function of radiation dose and dose rate. Simulations based on this model are found to agree well with measurements on a number of devices for which data are available.

Enchanced total dose damage in junction field effect transistors and related linear integrated circuits

International Nuclear Information System (INIS)

Flament, O.; Autran, J.L.; Roche, P.; Leray, J.L.; Musseau, O.

1996-01-01

Enhanced total dose damage of Junction Field-effect Transistors (JFETs) due to low dose rate and/or elevated temperature has been investigated for elementary p-channel structures fabricated on bulk and SOI substrates as well as for related linear integrated circuits. All these devices were fabricated with conventional junction isolation (field oxide). Large increases in damage have been revealed by performing high temperature and/or low dose rate irradiations. These results are consistent with previous studies concerning bipolar field oxides under low-field conditions. They suggest that the transport of radiation-induced holes through the oxide is the underlying mechanism. Such an enhanced degradation must be taken into account for low dose rate effects on linear integrated circuits

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications.

Science.gov (United States)

Vidor, Fábio F; Meyers, Thorsten; Hilleringmann, Ulrich

2016-08-23

Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high- k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the I ON / I OFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V / V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.

Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications

Directory of Open Access Journals (Sweden)

Fábio F. Vidor

2016-08-01

Full Text Available Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high-k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.

Integrated amplifying circuit with MOS transistors

Energy Technology Data Exchange (ETDEWEB)

Baylac, B; Merckel, G; Meunier, P

1974-01-25

The invention relates to a feedback-pass-band amplifier with MOS-transistors. The differential stage of conventional amplifiers is changed into an adding state, whereas the differential amplification stages are changed into amplifier inverter stages. All MOS transistors used in that amplifier are of similar configuration and are interdigitized, whereby the operating speed dispersion is reduced. This can be applied to obtaining a measurement channel for proportional chambers.

Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

Science.gov (United States)

Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

2013-05-01

ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

MOS integrated circuit design

CERN Document Server

Wolfendale, E

2013-01-01

MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

High mobility and quantum well transistors design and TCAD simulation

CERN Document Server

Hellings, Geert

2013-01-01

For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Qu...

Ultra-low power integrated circuit design circuits, systems, and applications

CERN Document Server

Li, Dongmei; Wang, Zhihua

2014-01-01

This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

ESD analog circuits and design

CERN Document Server

Voldman, Steven H

2014-01-01

A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

Water-soluble thin film transistors and circuits based on amorphous indium-gallium-zinc oxide.

Science.gov (United States)

Jin, Sung Hun; Kang, Seung-Kyun; Cho, In-Tak; Han, Sang Youn; Chung, Ha Uk; Lee, Dong Joon; Shin, Jongmin; Baek, Geun Woo; Kim, Tae-il; Lee, Jong-Ho; Rogers, John A

2015-04-22

This paper presents device designs, circuit demonstrations, and dissolution kinetics for amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) comprised completely of water-soluble materials, including SiNx, SiOx, molybdenum, and poly(vinyl alcohol) (PVA). Collections of these types of physically transient a-IGZO TFTs and 5-stage ring oscillators (ROs), constructed with them, show field effect mobilities (∼10 cm2/Vs), on/off ratios (∼2×10(6)), subthreshold slopes (∼220 mV/dec), Ohmic contact properties, and oscillation frequency of 5.67 kHz at supply voltages of 19 V, all comparable to otherwise similar devices constructed in conventional ways with standard, nontransient materials. Studies of dissolution kinetics for a-IGZO films in deionized water, bovine serum, and phosphate buffer saline solution provide data of relevance for the potential use of these materials and this technology in temporary biomedical implants.

Design automation for integrated nonlinear logic circuits (Conference Presentation)

Science.gov (United States)

Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

2016-05-01

A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

Reprogrammable read only variable threshold transistor memory with isolated addressing buffer

Science.gov (United States)

Lodi, Robert J.

1976-01-01

A monolithic integrated circuit, fully decoded memory comprises a rectangular array of variable threshold field effect transistors organized into a plurality of multi-bit words. Binary address inputs to the memory are decoded by a field effect transistor decoder into a plurality of word selection lines each of which activates an address buffer circuit. Each address buffer circuit, in turn, drives a word line of the memory array. In accordance with the word line selected by the decoder the activated buffer circuit directs reading or writing voltages to the transistors comprising the memory words. All of the buffer circuits additionally are connected to a common terminal for clearing all of the memory transistors to a predetermined state by the application to the common terminal of a large magnitude voltage of a predetermined polarity. The address decoder, the buffer and the memory array, as well as control and input/output control and buffer field effect transistor circuits, are fabricated on a common substrate with means provided to isolate the substrate of the address buffer transistors from the remainder of the substrate so that the bulk clearing function of simultaneously placing all of the memory transistors into a predetermined state can be performed.

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

Ripple gate drive circuit for fast operation of series connected IGBTs

Science.gov (United States)

Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

2005-09-20

A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

Design of Integrated Circuits Approaching Terahertz Frequencies

OpenAIRE

Yan, Lei; Johansen, Tom Keinicke

2013-01-01

In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also important for driving THz signal sources. To meet the requirement of high output power, amplifiers based on InP double heterojunction bipolar transistor (DHBT) devices from the III-V Lab in Marcoussic,...

Standardization of Schwarz-Christoffel transformation for engineering design of semiconductor and hybrid integrated-circuit elements

Science.gov (United States)

Yashin, A. A.

1985-04-01

A semiconductor or hybrid structure into a calculable two-dimensional region mapped by the Schwarz-Christoffel transformation and a universal algorithm can be constructed on the basis of Maxwell's electro-magnetic-thermal similarity principle for engineering design of integrated-circuit elements. The design procedure involves conformal mapping of the original region into a polygon and then the latter into a rectangle with uniform field distribution, where conductances and capacitances are calculated, using tabulated standard mapping functions. Subsequent synthesis of a device requires inverse conformal mapping. Devices adaptable as integrated-circuit elements are high-resistance film resistors with periodic serration, distributed-resistance film attenuators with high transformation ratio, coplanar microstrip lines, bipolar transistors, directional couplers with distributed coupling to microstrip lines for microwave bulk devices, and quasirregular smooth matching transitions from asymmetric to coplanar microstrip lines.

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

International Nuclear Information System (INIS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-01-01

Since 1989 the Solenoidal Detector Collaboration (SDC) has been developing a general purpose detector to be operated at the Superconducting Super Collider (SSC). A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDS silicon tracker. The IC was designed and tested at LBL and was fabricated using AT and T's CBIC-U2, 4 GHz f T complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 μm pitch double-sided silicon strip detector. The chip measures 6.8 mm x 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a φ = 10 14 protons/cm 2 have been performed on the JC, demonstrating the radiation hardness of the complementary bipolar process

Digital signal processing in power electronics control circuits

CERN Document Server

Sozanski, Krzysztof

2013-01-01

Many digital control circuits in current literature are described using analog transmittance. This may not always be acceptable, especially if the sampling frequency and power transistor switching frequencies are close to the band of interest. Therefore, a digital circuit is considered as a digital controller rather than an analog circuit. This helps to avoid errors and instability in high frequency components. Digital Signal Processing in Power Electronics Control Circuits covers problems concerning the design and realization of digital control algorithms for power electronics circuits using

Development of a construction and manufacturing techniques of complementary transistors for the radiation tolerant integrated circuits

Directory of Open Access Journals (Sweden)

Gorban A. N.

2011-06-01

Full Text Available The construction of vertical complementary transistors with the full dielectric isolation is developed, new technolo-gical processes of creation on their basis the radiation tolerant integrated circuits with parameters which provide low values of a leakage current along with the considerable values of a forward current and breakdown voltage at the information signals exchange frequency of about 500 kHz are developed.

Integrated circuit design using design automation

International Nuclear Information System (INIS)

Gwyn, C.W.

1976-09-01

Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Directory of Open Access Journals (Sweden)

Huei Chaeng Chin

2014-01-01

Full Text Available Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET for applications in ultralarge-scale integration (ULSI is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP and power-delay product (PDP of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg, for subthreshold swing (SS, drain-induced barrier lowering (DIBL, and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

Process design kit and circuits at a 2 µm technology node for flexible wearable electronics applications (Conference Presentation)

Science.gov (United States)

Torres-Miranda, Miguel; Petritz, Andreas; Gold, Herbert; Stadlober, Barbara

2016-09-01

In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A "plastic wafer" is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

Guidelines on the Switch Transistors Sizing Using the Symbolic Description for the Cross-Coupled Charge Pump

Directory of Open Access Journals (Sweden)

J. Marek

2017-09-01

Full Text Available This paper presents a symbolic description of the design process of the switch transistors for the cross- coupled charge pump applications. Discrete-time analog circuits are usually designed by the numerical algorithms in the professional simulator software which can be an extremely time-consuming process in contrast to described analytical procedure. The significant part of the pumping losses is caused by the reverse current through the switch transistors due to continuous-time voltage change on the main capacitors. Design process is based on the analytical expression of the time response characteristics of the pump stage as an analog system with using BSIM model equations. The main benefit of the article is the analytical transistors sizing formula, so that the maximum voltage gain is achieved. The diode transistor is dimensioned for the pump requirements, as the maximal pump output ripple voltage, current, etc. The characteristics of the proposed circuit has been verified by simulation in ELDO Spice. Results are valid for N-stage charge pump and also applicable for other model equations as PSP, EKV.

Mesoscopic photon heat transistor

DEFF Research Database (Denmark)

Ojanen, T.; Jauho, Antti-Pekka

2008-01-01

We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir-Wingreen-Landauer-typ......We show that the heat transport between two bodies, mediated by electromagnetic fluctuations, can be controlled with an intermediate quantum circuit-leading to the device concept of a mesoscopic photon heat transistor (MPHT). Our theoretical analysis is based on a novel Meir......-Wingreen-Landauer-type of conductance formula, which gives the photonic heat current through an arbitrary circuit element coupled to two dissipative reservoirs at finite temperatures. As an illustration we present an exact solution for the case when the intermediate circuit can be described as an electromagnetic resonator. We discuss...

Design and fabrication of ZnO/TiO2-based thin-film inverter circuits using solution processing techniques

International Nuclear Information System (INIS)

Liau, Leo Chau-Kuang; Kuo, Juo-Wei; Chiang, Hsin-Ni

2012-01-01

Novel and cost-effective ceramic-based thin-film inverter circuits, based on two layers of TiO 2 and ZnO films to construct junction field-effect transistors (FETs), were designed and fabricated by solution coating techniques. The double layers of the sol–gel ZnO and TiO 2 films were coated and characterized as a diode according to the current–voltage performance. Two types of FETs, the p-channel (p-FET) and the n-channel (n-FET) devices, were produced using different coating sequences of ZnO and TiO 2 layers. Both of the transistor performances were evaluated by analyzing the source–drain current versus voltage (I ds –V ds ) data with the control of the gate voltage (V g ). The ZnO/TiO 2 -based inverter circuits, such as the complementary-FET device, were further fabricated using the integration of the p-FET and the n-FET. The voltage transfer characteristics of the inverters were estimated by the tests of the input voltage (V in ) versus the output voltage (V out ) for the thin-film inverter circuits. (paper)

Four-terminal circuit element with photonic core

Science.gov (United States)

Sampayan, Stephen

2017-08-29

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated based on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.

Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET (QDG-QDCFET)

Science.gov (United States)

Karmakar, Supriya

2014-10-01

This paper presents the implementation of quaternary logic circuits based on quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFET). The super lattice structure in the quantum dot channel region of QDG-QDCFET and the electron tunnelling from inversion channel to the quantum dot layer in the gate region of a QDG-QDCFET change the threshold voltage of this device which produces two intermediate states between its ON and OFF states. This property of QDG-QDCFET is used to implement multi-valued logic for future multi-valued logic circuit. This paper presents the design of basic quaternary logic operation such as inverter, AND and OR operation based on QDG-QDCFET.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

Science.gov (United States)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

A hybrid pulse combining topology utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer.

Science.gov (United States)

Li, Jiangtao; Zhao, Zheng; Sun, Yi; Liu, Yuhao; Ren, Ziyuan; He, Jiaxin; Cao, Hui; Zheng, Minjun

2017-03-01

Numerous applications driven by pulsed voltage require pulses to be with high amplitude, high repetitive frequency, and narrow width, which could be satisfied by utilizing avalanche transistors. The output improvement is severely limited by power capacities of transistors. Pulse combining is an effective approach to increase the output amplitude while still adopting conventional pulse generating modules. However, there are drawbacks in traditional topologies including the saturation tendency of combining efficiency and waveform oscillation. In this paper, a hybrid pulse combining topology was adopted utilizing the combination of modularized avalanche transistor Marx circuits, direct pulse adding, and transmission line transformer. The factors affecting the combining efficiency were determined including the output time synchronization of Marx circuits, and the quantity and position of magnetic cores. The numbers of the parallel modules and the stages were determined by the output characteristics of each combining method. Experimental results illustrated the ability of generating pulses with 2-14 kV amplitude, 7-11 ns width, and a maximum 10 kHz repetitive rate on a matched 50-300 Ω resistive load. The hybrid topology would be a convinced pulse combining method for similar nanosecond pulse generators based on the solid-state switches.

Modern TTL circuits manual

CERN Document Server

Marston, R M

2013-01-01

Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

Directory of Open Access Journals (Sweden)

Mohammad Reza Shokrani

2014-01-01

Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

Science.gov (United States)

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Ultra-high gain diffusion-driven organic transistor

Science.gov (United States)

Torricelli, Fabrizio; Colalongo, Luigi; Raiteri, Daniele; Kovács-Vajna, Zsolt Miklós; Cantatore, Eugenio

2016-01-01

Emerging large-area technologies based on organic transistors are enabling the fabrication of low-cost flexible circuits, smart sensors and biomedical devices. High-gain transistors are essential for the development of large-scale circuit integration, high-sensitivity sensors and signal amplification in sensing systems. Unfortunately, organic field-effect transistors show limited gain, usually of the order of tens, because of the large contact resistance and channel-length modulation. Here we show a new organic field-effect transistor architecture with a gain larger than 700. This is the highest gain ever reported for organic field-effect transistors. In the proposed organic field-effect transistor, the charge injection and extraction at the metal–semiconductor contacts are driven by the charge diffusion. The ideal conditions of ohmic contacts with negligible contact resistance and flat current saturation are demonstrated. The approach is general and can be extended to any thin-film technology opening unprecedented opportunities for the development of high-performance flexible electronics. PMID:26829567

Nature of size effects in compact models of field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Torkhov, N. A., E-mail: trkf@mail.ru [Tomsk State University, Tomsk 634050 (Russian Federation); Scientific-Research Institute of Semiconductor Devices, Tomsk 634050 (Russian Federation); Tomsk State University of Control Systems and Radioelectronics, Tomsk 634050 (Russian Federation); Babak, L. I.; Kokolov, A. A.; Salnikov, A. S.; Dobush, I. M. [Tomsk State University of Control Systems and Radioelectronics, Tomsk 634050 (Russian Federation); Novikov, V. A., E-mail: novikovvadim@mail.ru; Ivonin, I. V. [Tomsk State University, Tomsk 634050 (Russian Federation)

2016-03-07

Investigations have shown that in the local approximation (for sizes L < 100 μm), AlGaN/GaN high electron mobility transistor (HEMT) structures satisfy to all properties of chaotic systems and can be described in the language of fractal geometry of fractional dimensions. For such objects, values of their electrophysical characteristics depend on the linear sizes of the examined regions, which explain the presence of the so-called size effects—dependences of the electrophysical and instrumental characteristics on the linear sizes of the active elements of semiconductor devices. In the present work, a relationship has been established for the linear model parameters of the equivalent circuit elements of internal transistors with fractal geometry of the heteroepitaxial structure manifested through a dependence of its relative electrophysical characteristics on the linear sizes of the examined surface areas. For the HEMTs, this implies dependences of their relative static (A/mm, mA/V/mm, Ω/mm, etc.) and microwave characteristics (W/mm) on the width d of the sink-source channel and on the number of sections n that leads to a nonlinear dependence of the retrieved parameter values of equivalent circuit elements of linear internal transistor models on n and d. Thus, it has been demonstrated that the size effects in semiconductors determined by the fractal geometry must be taken into account when investigating the properties of semiconductor objects on the levels less than the local approximation limit and designing and manufacturing field effect transistors. In general, the suggested approach allows a complex of problems to be solved on designing, optimizing, and retrieving the parameters of equivalent circuits of linear and nonlinear models of not only field effect transistors but also any arbitrary semiconductor devices with nonlinear instrumental characteristics.

Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters

Directory of Open Access Journals (Sweden)

Vytautas Bleizgys

2011-03-01

Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian

Specs: Simulation Program for Electronic Circuits and Systems

Science.gov (United States)

de Geus, Aart Jan

Simulation tools are central to the development and verification of very large scale integrated circuits. Circuit simulation has been used for over two decades to verify the behavior of designs. Recently the introduction of switch-level simulators which model MOS transistors in terms of switches has helped to overcome the long runtimes associated with full circuit simulation. Used strictly for functional verification and fault simulation, switch -level simulation can only give very rough estimates of the timing of a circuit. In this dissertation an approach is presented which adds a timing capability to switch-level simulators at relatively little extra CPU cost. A new logic state concept is introduced which consists of a set of discrete voltage steps. Signals are known only in terms of these states thus allowing all current computations to be table driven. State changes are scheduled in the same fashion as in the case of gate-level simulators, making the simulator event-driven. The simulator is of mixed-mode nature in that it can model portions of a design at either the gate or transistor level. In order to represent the "unknown" state, a signal consists of both an upper and a lower bound defining a signal envelope. Both bounds are expressed in terms of states. In order to speed up the simulation, MOS networks are subdivided in small pull-up and pull-down transistor configurations that can be preanalysed and prepared for fast evaluation during the simulation. These concepts have been implemented in the program SPECS (Simulation Program For Electronic Circuits and Systems) and examples of simulations are given.

Distributed amplifier using Josephson vortex flow transistors

International Nuclear Information System (INIS)

McGinnis, D.P.; Beyer, J.B.; Nordman, J.E.

1986-01-01

A wide-band traveling wave amplifier using vortex flow transistors is proposed. A vortex flow transistor is a long Josephson junction used as a current controlled voltage source. The dual nature of this device to the field effect transistor is exploited. A circuit model of this device is proposed and a distributed amplifier utilizing 50 vortex flow transistors is predicted to have useful gain to 100 GHz

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

Performance evaluation of parallel electric field tunnel field-effect transistor by a distributed-element circuit model

Science.gov (United States)

Morita, Yukinori; Mori, Takahiro; Migita, Shinji; Mizubayashi, Wataru; Tanabe, Akihito; Fukuda, Koichi; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shin-ichi; Liu, Yongxun; Masahara, Meishoku; Ota, Hiroyuki

2014-12-01

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field was evaluated. The TFET was fabricated by inserting an epitaxially-grown parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer.

Multi-channel spintronic transistor design based on magnetoelectric barriers and spin-orbital effects

International Nuclear Information System (INIS)

Fujita, T; Jalil, M B A; Tan, S G

2008-01-01

We present a spin transistor design based on spin-orbital interactions in a two-dimensional electron gas, with magnetic barriers induced by a patterned ferromagnetic gate. The proposed device overcomes certain shortcomings of previous spin transistor designs such as long device length and degradation of conductance modulation for multi-channel transport. The robustness of our device for multi-channel transport is unique in spin transistor designs based on spin-orbit coupling. The device is more practical in fabrication and experimental respects compared to previously conceived single-mode spin transistors

A 10-kW series resonant converter design, transistor characterization, and base-drive optimization

Science.gov (United States)

Robson, R. R.; Hancock, D. J.

1982-01-01

The development, components, and performance of a transistor-based 10 kW series resonant converter for use in resonant circuits in space applications is described. The transistors serve to switch on the converter current, which has a half-sinusoid waveform when the transistor is in saturation. The goal of the program was to handle an input-output voltage range of 230-270 Vdc, an output voltage range of 200-500 Vdc, and a current limit range of 0-20 A. Testing procedures for the D60T and D7ST transistors are outlined and base drive waveforms are presented. The total device dissipation was minimized and found to be independent of the regenerative feedback ratio at lower current levels. Dissipation was set at within 10% and rise times were found to be acceptable. The finished unit displayed a 91% efficiency at full power levels of 500 V and 20 A and 93.7% at 500 V and 10 A.

Nanofluidic Transistor Circuits

Science.gov (United States)

Chang, Hsueh-Chia; Cheng, Li-Jing; Yan, Yu; Slouka, Zdenek; Senapati, Satyajyoti

2012-02-01

Non-equilibrium ion/fluid transport physics across on-chip membranes/nanopores is used to construct rectifying, hysteretic, oscillatory, excitatory and inhibitory nanofluidic elements. Analogs to linear resistors, capacitors, inductors and constant-phase elements were reported earlier (Chang and Yossifon, BMF 2009). Nonlinear rectifier is designed by introducing intra-membrane conductivity gradient and by asymmetric external depletion with a reverse rectification (Yossifon and Chang, PRL, PRE, Europhys Lett 2009-2011). Gating phenomenon is introduced by functionalizing polyelectrolytes whose conformation is field/pH sensitive (Wang, Chang and Zhu, Macromolecules 2010). Surface ion depletion can drive Rubinstein's microvortex instability (Chang, Yossifon and Demekhin, Annual Rev of Fluid Mech, 2012) or Onsager-Wien's water dissociation phenomenon, leading to two distinct overlimiting I-V features. Bipolar membranes exhibit an S-hysteresis due to water dissociation (Cheng and Chang, BMF 2011). Coupling the hysteretic diode with some linear elements result in autonomous ion current oscillations, which undergo classical transitions to chaos. Our integrated nanofluidic circuits are used for molecular sensing, protein separation/concentration, electrospray etc.

Imperceptible and Ultraflexible p-Type Transistors and Macroelectronics Based on Carbon Nanotubes.

Science.gov (United States)

Cao, Xuan; Cao, Yu; Zhou, Chongwu

2016-01-26

Flexible thin-film transistors based on semiconducting single-wall carbon nanotubes are promising for flexible digital circuits, artificial skins, radio frequency devices, active-matrix-based displays, and sensors due to the outstanding electrical properties and intrinsic mechanical strength of carbon nanotubes. Nevertheless, previous research effort only led to nanotube thin-film transistors with the smallest bending radius down to 1 mm. In this paper, we have realized the full potential of carbon nanotubes by making ultraflexible and imperceptible p-type transistors and circuits with a bending radius down to 40 μm. In addition, the resulted transistors show mobility up to 12.04 cm(2) V(-1) S(-1), high on-off ratio (∼10(6)), ultralight weight (transistors and circuits have great potential to work as indispensable components for ultraflexible complementary electronics.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

Science.gov (United States)

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Benchmarking organic mixed conductors for transistors

KAUST Repository

Inal, Sahika

2017-11-20

Organic mixed conductors have garnered significant attention in applications from bioelectronics to energy storage/generation. Their implementation in organic transistors has led to enhanced biosensing, neuromorphic function, and specialized circuits. While a narrow class of conducting polymers continues to excel in these new applications, materials design efforts have accelerated as researchers target new functionality, processability, and improved performance/stability. Materials for organic electrochemical transistors (OECTs) require both efficient electronic transport and facile ion injection in order to sustain high capacity. In this work, we show that the product of the electronic mobility and volumetric charge storage capacity (µC*) is the materials/system figure of merit; we use this framework to benchmark and compare the steady-state OECT performance of ten previously reported materials. This product can be independently verified and decoupled to guide materials design and processing. OECTs can therefore be used as a tool for understanding and designing new organic mixed conductors.

Benchmarking organic mixed conductors for transistors

KAUST Repository

Inal, Sahika; Malliaras, George G.; Rivnay, Jonathan

2017-01-01

Organic mixed conductors have garnered significant attention in applications from bioelectronics to energy storage/generation. Their implementation in organic transistors has led to enhanced biosensing, neuromorphic function, and specialized circuits. While a narrow class of conducting polymers continues to excel in these new applications, materials design efforts have accelerated as researchers target new functionality, processability, and improved performance/stability. Materials for organic electrochemical transistors (OECTs) require both efficient electronic transport and facile ion injection in order to sustain high capacity. In this work, we show that the product of the electronic mobility and volumetric charge storage capacity (µC*) is the materials/system figure of merit; we use this framework to benchmark and compare the steady-state OECT performance of ten previously reported materials. This product can be independently verified and decoupled to guide materials design and processing. OECTs can therefore be used as a tool for understanding and designing new organic mixed conductors.

Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

KAUST Repository

Lechuga Aranda, Jesus Javier

2016-05-01

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

Carbon Based Transistors and Nanoelectronic Devices

Science.gov (United States)

Rouhi, Nima

Carbon based materials (carbon nanotube and graphene) has been extensively researched during the past decade as one of the promising materials to be used in high performance device technology. In long term it is thought that they may replace digital and/or analog electronic devices, due to their size, near-ballistic transport, and high stability. However, a more realistic point of insertion into market may be the printed nanoelectronic circuits and sensors. These applications include printed circuits for flexible electronics and displays, large-scale bendable electrical contacts, bio-membranes and bio sensors, RFID tags, etc. In order to obtain high performance thin film transistors (as the basic building block of electronic circuits) one should be able to manufacture dense arrays of all semiconducting nanotubes. Besides, graphene synthesize and transfer technology is in its infancy and there is plenty of room to improve the current techniques. To realize the performance of nanotube and graphene films in such systems, we need to economically fabricate large-scale devices based on these materials. Following that the performance control over such devices should also be considered for future design variations for broad range of applications. Here we have first investigated carbon nanotube ink as the base material for our devices. The primary ink used consisted of both metallic and semiconducting nanotubes which resulted in networks suitable for moderate-resistivity electrical connections (such as interconnects) and rfmatching circuits. Next, purified all-semiconducting nanotube ink was used to fabricate waferscale, high performance (high mobility, and high on/off ratio) thin film transistors for printed electronic applications. The parameters affecting device performance were studied in detail to establish a roadmap for the future of purified nanotube ink printed thin film transistors. The trade of between mobility and on/off ratio of such devices was studied and the

Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

Science.gov (United States)

Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

2017-04-01

In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

InP Heterojunction Bipolar Transistor Amplifiers to 255 GHz

Science.gov (United States)

Radisic, Vesna; Sawdai, Donald; Scott, Dennis; Deal, William; Dang, Linh; Li, Danny; Cavus, Abdullah; To, Richard; Lai, Richard

2009-01-01

Two single-stage InP heterojunction bipolar transistor (HBT) amplifiers operate at 184 and 255 GHz, using Northrop Grumman Corporation s InP HBT MMIC (monolithic microwave integrated circuit) technology. At the time of this reporting, these are reported to be the highest HBT amplifiers ever created. The purpose of the amplifier design is to evaluate the technology capability for high-frequency designs and verify the model for future development work.

Transistor design considerations for low-noise preamplifiers

International Nuclear Information System (INIS)

Fair, R.B.

1976-01-01

A review is presented of design considerations for GaAs Schottky-barrier FETs and other types of transistors in low-noise amplifiers for capacitive sources which are used in nuclear radiation detectors and high speed fiber-optic communication systems. Ultimate limits on performance are evaluated in terms of the g/sub m//C/sub i/ ratio and the gate leakage current to minimize the noise sources. Si bipolar transistors and the future prospects of GaAs, Si and InAs MISFETs are discussed, and performance is compared to FETs currently being used in low-noise preamplifiers

Effect of electrode design on crosstalk between neighboring organic field-effect transistors based on one single crystal

Science.gov (United States)

Li, Mengjie; Tang, Qingxin; Tong, Yanhong; Zhao, Xiaoli; Zhou, Shujun; Liu, Yichun

2018-03-01

The design of high-integration organic circuits must be such that the interference between neighboring devices is eliminated. Here, rubrene crystals were used to study the effect of the electrode design on crosstalk between neighboring organic field-effect transistors (OFETs). Results show that a decreased source/drain interval and gate electrode width can decrease the diffraction distance of the current, and therefore can weaken the crosstalk. In addition, the inherent low carrier concentration in organic semiconductors can create a high-resistance barrier at the space between gate electrodes of neighboring devices, limiting or even eliminating the crosstalk as a result of the gate electrode width being smaller than the source/drain electrode width.

High Accuracy Transistor Compact Model Calibrations

Energy Technology Data Exchange (ETDEWEB)

Hembree, Charles E. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Mar, Alan [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Robertson, Perry J. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

2015-09-01

Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspond- ingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirements require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantifi- cation of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transis- tors have been developed and are described in this report.

Design and implementation of fast charging circuit for repetitive compact torus injector

International Nuclear Information System (INIS)

Onchi, T.; McColl, D.; Dreval, M.; Wolfe, S.; Xiao, C.; Hirose, A.

2014-01-01

A novel circuit for compact torus (CT) injector operated at high repetition rates has been developed. The core technology adopted in the present work is to charge a large storage capacitor bank and quickly charge the CT capacitor bank through a stack of insulated-gate bipolar transistors (IGBTs). A system consisting of IGBTs and slow banks for the repetitive operation has been developed and installed for each discharge circuit of the University of Saskatchewan Compact Torus Injector (USCTI). A repetition rate up to 1.7 Hz and a burst of 8 CTs have been achieved

Active component modeling for analog integrated circuit design. Model parametrization and implementation in the SPICE-PAC circuit simulator

International Nuclear Information System (INIS)

Marchal, Xavier

1992-01-01

In order to use CAD efficiently in the analysis and design of electronic Integrated circuits, adequate modeling of active non-linear devices such as MOSFET transistors must be available to the designer. Many mathematical forms can be given to those models, such as explicit relations, or implicit equations to be solved. A major requirement in developing MOS transistor models for IC simulation is the availability of electrical characteristic curves over a wide range of channel width and length, including the sub-micrometer range. To account in a convenient way for bulk charge influence on I_D_S = f(V_D_S, V_G_S, v_B_S) device characteristics, all 3 standard SPICE MOS models use an empirical fitting parameter called the 'charge sharing factor'. Unfortunately, this formulation produces models which only describe correctly either some of the short channel phenomena, or some particular operating conditions (low injection, avalanche effect, etc.). We present here a cellular model (CDM = Charge Distributed Model) implemented in the open modular SPICE-PAC Simulator; this model is derived from the 4-terminal WANG charge controlled MOSFET model, using the charge sheet approximation. The CDM model describes device characteristics in ail operating regions without introducing drain current discontinuities and without requiring a 'charge sharing factor'. A usual problem to be faced by designers when they simulate MOS ICs is to find a reliable source of model parameters. Though most models have a physical basis, some of their parameters cannot be easily estimated from physical considerations. It can also happen that physically determined parameters values do not produce a good fit to measured device characteristics. Thus it is generally necessary to extract model parameters from measured transistor data, to ensure that model equations approximate measured curves accurately enough. Model parameters extraction can be done in 2 different ways, exposed in this thesis. The first

Optimized circuit design for flexible 8-bit RFID transponders with active layer of ink-jet printed small molecule semiconductors

NARCIS (Netherlands)

Kjellander, B.K.C.; Smaal, W.T.T.; Myny, K.; Genoe, J.; Dehaene, W.; Heremans, P.; Gelinck, G.H.

2013-01-01

We ink-jet print a blend of 6,13-bis(triisopropyl-silylethynyl)pentacene and polystyrene as the active layer for flexible circuits. The discrete ink-jet printed transistors exhibit a saturation mobility of 0.5 cm2 V -1 s-1. The relative spread in transistor characteristics can be very large. This

Advances in Analog Circuit Design 2015

CERN Document Server

Baschirotto, Andrea; Harpe, Pieter

2016-01-01

This book is based on the 18 tutorials presented during the 24th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of efficient sensor interfaces and low-power RF systems. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing.

Circuit design on plastic foils

CERN Document Server

Raiteri, Daniele; Roermund, Arthur H M

2015-01-01

This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics.  The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.   • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels.

Static Characteristics of the Ferroelectric Transistor Inverter

Science.gov (United States)

Mitchell, Cody; Laws, crystal; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

The inverter is one of the most fundamental building blocks of digital logic, and it can be used as the foundation for understanding more complex logic gates and circuits. This paper presents the characteristics of an inverter circuit using a ferroelectric field-effect transistor. The voltage transfer characteristics are analyzed with respect to varying parameters such as supply voltage, input voltage, and load resistance. The effects of the ferroelectric layer between the gate and semiconductor are examined, and comparisons are made between the inverters using ferroelectric transistors and those using traditional MOSFETs.

Graphene radio frequency receiver integrated circuit.

Science.gov (United States)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

OpenAIRE

石橋, 孝昭

2012-01-01

This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

An analog integrated circuit design laboratory

OpenAIRE

Mondragon-Torres, A.F.; Mayhugh, Jr.; Pineda de Gyvez, J.; Silva-Martinez, J.; Sanchez-Sinencio, E.

2003-01-01

We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a laboratory manual with analog circuit design theory, pre-laboratory exercises and circuit design specifications; a reference web page with step by step instructions and examples; the use of mathematical tools for automation and analysis; and state of the art CAD design tools in use by industry. Upon completion of the ...

A high current, high speed pulser using avalanche transistors

International Nuclear Information System (INIS)

Hosono, Yoneichi; Hasegawa, Ken-ichi

1985-01-01

A high current, high speed pulser for the beam pulsing of a linear accelerator is described. It uses seven avalanche transistors in cascade. Design of a trigger circuit to obtain fast rise time is discussed. The characteristics of the pulser are : (a) Rise time = 0.9 ns (FWHM) and (d) Life time asymptotically equals 2000 -- 3000 hr (at 50 Hz). (author)

Analog circuit design art, science, and personalities

CERN Document Server

Williams, Jim

1991-01-01

Analog Circuit Design: Art, Science, and Personalities discusses the many approaches and styles in the practice of analog circuit design. The book is written in an informal yet informative manner, making it easily understandable to those new in the field. The selection covers the definition, history, current practice, and future direction of analog design; the practice proper; and the styles in analog circuit design. The book also includes the problems usually encountered in analog circuit design; approach to feedback loop design; and other different techniques and applications. The text is

Circuit design for reliability

CERN Document Server

Cao, Yu; Wirth, Gilson

2015-01-01

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

Modeling of charge transport in ion bipolar junction transistors.

Science.gov (United States)

Volkov, Anton V; Tybrandt, Klas; Berggren, Magnus; Zozoulenko, Igor V

2014-06-17

Spatiotemporal control of the complex chemical microenvironment is of great importance to many fields within life science. One way to facilitate such control is to construct delivery circuits, comprising arrays of dispensing outlets, for ions and charged biomolecules based on ionic transistors. This allows for addressability of ionic signals, which opens up for spatiotemporally controlled delivery in a highly complex manner. One class of ionic transistors, the ion bipolar junction transistors (IBJTs), is especially attractive for these applications because these transistors are functional at physiological conditions and have been employed to modulate the delivery of neurotransmitters to regulate signaling in neuronal cells. Further, the first integrated complementary ionic circuits were recently developed on the basis of these ionic transistors. However, a detailed understanding of the device physics of these transistors is still lacking and hampers further development of components and circuits. Here, we report on the modeling of IBJTs using Poisson's and Nernst-Planck equations and the finite element method. A two-dimensional model of the device is employed that successfully reproduces the main characteristics of the measurement data. On the basis of the detailed concentration and potential profiles provided by the model, the different modes of operation of the transistor are analyzed as well as the transitions between the different modes. The model correctly predicts the measured threshold voltage, which is explained in terms of membrane potentials. All in all, the results provide the basis for a detailed understanding of IBJT operation. This new knowledge is employed to discuss potential improvements of ion bipolar junction transistors in terms of miniaturization and device parameters.

Source-circuit design overview

Science.gov (United States)

Ross, R. G., Jr.

1983-01-01

The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

Recent Progress in the Development of Printed Thin-Film Transistors and Circuits with High-Resolution Printing Technology.

Science.gov (United States)

Fukuda, Kenjiro; Someya, Takao

2017-07-01

Printed electronics enable the fabrication of large-scale, low-cost electronic devices and systems, and thus offer significant possibilities in terms of developing new electronics/optics applications in various fields. Almost all electronic applications require information processing using logic circuits. Hence, realizing the high-speed operation of logic circuits is also important for printed devices. This report summarizes recent progress in the development of printed thin-film transistors (TFTs) and integrated circuits in terms of materials, printing technologies, and applications. The first part of this report gives an overview of the development of functional inks such as semiconductors, electrodes, and dielectrics. The second part discusses high-resolution printing technologies and strategies to enable high-resolution patterning. The main focus of this report is on obtaining printed electrodes with high-resolution patterning and the electrical performance of printed TFTs using such printed electrodes. In the final part, some applications of printed electronics are introduced to exemplify their potential. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Simplified design of filter circuits

CERN Document Server

Lenk, John

1999-01-01

Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets

A built-in current sensor using thin-film transistors

Energy Technology Data Exchange (ETDEWEB)

Hatzopoulos, A A [Department of Electrical and Computer Eng., Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Siskos, S [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Dimitriadis, C A [Department of Physics, Microelectronic device characterization and design Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Papadopoulos, N [Department of Electrical and Computer Eng., Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Pappas, I [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece); Nalpantidis, L [Department of Physics, Electronics Lab., Aristotle University of Thessaloniki, 54124 Thessaloniki (Greece)

2005-01-01

A simple current mirror using TFTs with input terminals which are capacitively coupled to the TFT gate, is used in this work, to design a built-in current sensor (BICS). The important feature in this application is that the voltage drop across the sensing TFT device can be reduced to almost zero value, while preserving transistor operation in the saturation region. This makes the proposed BICS appropriate for TFT applications without affecting the circuit operation. It also results in adequate linearity for the current monitoring, making the structure applicable to digital as well as to analog and mixed-signal circuit testing.

Automatic design of digital synthetic gene circuits.

Directory of Open Access Journals (Sweden)

Mario A Marchisio

2011-02-01

Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

Discharge quenching circuit for counters

International Nuclear Information System (INIS)

Karasik, A.S.

1982-01-01

A circuit for quenching discharges in gas-discharge detectors with working voltage of 3-5 kV based on transistors operating in the avalanche mode is described. The quenching circuit consists of a coordinating emitter follower, amplifier-shaper for avalanche key cascade control which changes potential on the counter electrodes and a shaper of discharge quenching duration. The emitter follower is assembled according to a widely used flowsheet with two transistors. The circuit permits to obtain a rectangular quenching pulse with front of 100 ns and an amplitude of up to 3.2 kV at duration of 500 μm-8 ms. Application of the quenching circuit described permits to obtain countering characteristics with the slope less than or equal to 0.02%/V and plateau extent greater than or equal to 300 V [ru

Transistor reset preamplifier for high-rate high-resolution spectroscopy

International Nuclear Information System (INIS)

Landis, D.A.; Cork, C.P.; Madden, N.W.; Goulding, F.S.

1981-10-01

Pulsed transistor reset of high resolution charge sensitive preamplifiers used in cooled semiconductor spectrometers can sometimes have an advantage over pulsed light reset systems. Several versions of transistor reset spectrometers using both silicon and germanium detectors have been built. This paper discusses the advantages of the transistor reset system and illustrates several configurations of the packages used for the FET and reset transistor. It also describes the preamplifer circuit and shows the performance of the spectrometer at high rates

Current-mode minimax circuit

NARCIS (Netherlands)

Wassenaar, R.F.

1992-01-01

The minimum-maximum (minimax) circuit selects the minimum and maximum of two input currents. Four transistors in matched pairs are operated in the saturation region. Because the behavior of the circuit is based on matched devices and is independent of the relationship between the drain current and

Transistor analogs of emergent iono-neuronal dynamics.

Science.gov (United States)

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

Balancing Hole and Electron Conduction in Ambipolar Split-Gate Thin-Film Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Lee, Dong-Kyu; Smits, Edsger C P; Gelinck, Gerwin H; Ahn, Hyungju; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2017-07-10

Complementary organic electronics is a key enabling technology for the development of new applications including smart ubiquitous sensors, wearable electronics, and healthcare devices. High-performance, high-functionality and reliable complementary circuits require n- and p-type thin-film transistors with balanced characteristics. Recent advancements in ambipolar organic transistors in terms of semiconductor and device engineering demonstrate the great potential of this route but, unfortunately, the actual development of ambipolar organic complementary electronics is currently hampered by the uneven electron (n-type) and hole (p-type) conduction in ambipolar organic transistors. Here we show ambipolar organic thin-film transistors with balanced n-type and p-type operation. By manipulating air exposure and vacuum annealing conditions, we show that well-balanced electron and hole transport properties can be easily obtained. The method is used to control hole and electron conductions in split-gate transistors based on a solution-processed donor-acceptor semiconducting polymer. Complementary logic inverters with balanced charging and discharging characteristics are demonstrated. These findings may open up new opportunities for the rational design of complementary electronics based on ambipolar organic transistors.

A novel high voltage start up circuit for an integrated switched mode power supply

Energy Technology Data Exchange (ETDEWEB)

Hu Hao; Chen Xingbi, E-mail: huhao21@uestc.edu.c [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)

2010-09-15

A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions. (semiconductor devices)

Modeling and simulation of 4H-SiC field effect transistor

Science.gov (United States)

Pedryc, A.; Martychowiec, A.; Kociubiński, A.

2017-08-01

This paper presents the technological issue of silicon carbide MOSFET design. Through the use of simulations of silicon carbide transistor, the influence of the different the technological parameters are described and discussed. MOSFET transistor was performed in Silvaco TCAD using technology elaborated at Lublin University of Technology. The most important parameters related to ion implantation, which was used in p-i-n photodiode technology. The electrical simulations were performed, transfer and output characteristics for different values of technological parameters were generated - influence of gate oxide thickness on threshold voltage and influence of channel length modulation were checked. The results of simulations as well as transfer and output characteristics allowed to select optimal parameters between expected device working and available technology - gate oxide thickness and transistor channel length were established. This work was in fact carried out to increase our understanding of the device characteristics so as to allow the design of new SiC circuits which could meet the stressful requirements of ultraviolet detector systems.

Trigger circuit

International Nuclear Information System (INIS)

Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.

1984-01-01

A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)

Automatic circuit analysis based on mask information

International Nuclear Information System (INIS)

Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.

1976-01-01

The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program

Semiconductors integrated circuit design for manufacturability

CERN Document Server

Balasinki, Artur

2011-01-01

Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

Testing and verification of a novel single-channel IGBT driver circuit

Directory of Open Access Journals (Sweden)

Lukić Milan

2016-01-01

Full Text Available This paper presents a novel single-channel IGBT driver circuit together with a procedure for testing and verification. It is based on a specialized integrated circuit with complete range of protective functions. Experiments are performed to test and verify its behaviour. Experimental results are presented in the form of oscilloscope recordings. It is concluded that the new driver circuit is compatible with modern IGBT transistors and power converter demands and that it can be applied in new designs. It is a part of new 20kW industrial-grade boost converter.

Digital logic circuit design with ALTERA MAX+PLUS II

International Nuclear Information System (INIS)

Lee, Seung Ho; Park, Yong Su; Lee, Ju Heon

2006-03-01

Contents of this book are the kinds of integrated circuit, design process of integrated circuit, introduction of ALTERA MAX+PLUS II, designing logic circuit with VHDL of ALTERA MAX+PLUS II, grammar and practice of VHDL of ALTERA MAX+PLUS II, design for adder, subtractor, parallel binary subtractor, BCD design, CLA design, code converter design, ALU design, register design, counter design, accumulator design, state machine design, frequency divider design, circuit design with TENMILLION counter, LCD module, circuit design for control the outside RAM in training kit and introduction for HEB-DTK-20K-240/HBE-DTK-IOK.

Development and Experimental Evaluation of an Automated Multi-Media Course on Transistors.

Science.gov (United States)

Whitted, J.H., Jr.; And Others

A completely automated multi-media self-study program for teaching a portion of electronic solid-state fundamentals was developed. The subject matter areas included were fundamental theory of transistors, transistor amplifier fundamentals, and simple mathematical analysis of transistors including equivalent circuits, parameters, and characteristic…

Triple inverter pierce oscillator circuit suitable for CMOS

Science.gov (United States)

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

Science.gov (United States)

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Performance of in-pixel circuits for photon counting arrays (PCAs) based on polycrystalline silicon TFTs

International Nuclear Information System (INIS)

Liang, Albert K; Koniczek, Martin; Antonuk, Larry E; El-Mohri, Youcef; Zhao, Qihua; Street, Robert A; Lu, Jeng Ping

2016-01-01

Photon counting arrays (PCAs), defined as pixelated imagers which measure the absorbed energy of x-ray photons individually and record this information digitally, are of increasing clinical interest. A number of PCA prototypes with a 1 mm pixel-to-pixel pitch have recently been fabricated with polycrystalline silicon (poly-Si)—a thin-film technology capable of creating monolithic imagers of a size commensurate with human anatomy. In this study, analog and digital simulation frameworks were developed to provide insight into the influence of individual poly-Si transistors on pixel circuit performance—information that is not readily available through empirical means. The simulation frameworks were used to characterize the circuit designs employed in the prototypes. The analog framework, which determines the noise produced by individual transistors, was used to estimate energy resolution, as well as to identify which transistors contribute the most noise. The digital framework, which analyzes how well circuits function in the presence of significant variations in transistor properties, was used to estimate how fast a circuit can produce an output (referred to as output count rate). In addition, an algorithm was developed and used to estimate the minimum pixel pitch that could be achieved for the pixel circuits of the current prototypes. The simulation frameworks predict that the analog component of the PCA prototypes could have energy resolution as low as 8.9% full width at half maximum (FWHM) at 70 keV; and the digital components should work well even in the presence of significant thin-film transistor (TFT) variations, with the fastest component having output count rates as high as 3 MHz. Finally, based on conceivable improvements in the underlying fabrication process, the algorithm predicts that the 1 mm pitch of the current PCA prototypes could be reduced significantly, potentially to between ∼240 and 290 μm. (paper)

High efficiency inverter and ballast circuits

International Nuclear Information System (INIS)

Nilssen, O.K.

1984-01-01

A high efficiency push-pull inverter circuit employing a pair of relatively high power switching transistors is described. The switching on and off of the transistors is precisely controlled to minimize power losses due to common-mode conduction or due to transient conditions that occur in the process of turning a transistor on or off. Two current feed-back transformers are employed in the transistor base drives; one being saturable for providing a positive feedback, and the other being non-saturable for providing a subtractive feedback

A Novel Realization of Low-Power and Low-Distortion Multiplier Circuit with Improved Dynamic Range

Directory of Open Access Journals (Sweden)

Ali Naderi Saatlo

2017-01-01

Full Text Available A novel topology of four-quadrant analog multiplier circuit is presented in this paper. The voltage mode technique is employed to design the circuit in CMOS technology. The dynamic input and output ranges of the circuit are improved owing to the fact that the circuit works in the saturation region not in weak inversion. Also the proposed multiplier is suitable for low voltage operation and its power consumption is relatively low. In order to verify the performance of the proposed circuit, performance of the circuit affected by second order effects including transistor mismatch and mobility reduction is analyzed in detail. It will be shown that any conceivable mismatch in the transistor parameters leads to second harmonic distortion. Additionally, the effect of mobility reduction in the third harmonic distortion will be computed. In order to simulate the circuit, Cadence and HSPICE software are used with TSMC level 49 (BSIM3v3 parameters for 0.18 μm CMOS technology, where under supply voltage of 1.5 V, total power consumption is 44 µW, the corresponding average nonlinearity remains as low as 1 %, and the input range of the circuit is ± 400 mV.

The analysis and design of linear circuits

CERN Document Server

Thomas, Roland E; Toussaint, Gregory J

2009-01-01

The Analysis and Design of Linear Circuits, 6e gives the reader the opportunity to not only analyze, but also design and evaluate linear circuits as early as possible. The text's abundance of problems, applications, pedagogical tools, and realistic examples helps engineers develop the skills needed to solve problems, design practical alternatives, and choose the best design from several competing solutions. Engineers searching for an accessible introduction to resistance circuits will benefit from this book that emphasizes the early development of engineering judgment.

Sequential circuit design for radiation hardened multiple voltage integrated circuits

Science.gov (United States)

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Designing Novel Quaternary Quantum Reversible Subtractor Circuits

Science.gov (United States)

Haghparast, Majid; Monfared, Asma Taheri

2018-01-01

Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.

Four quadrant control circuit for a brushless three-phase dc motor

Science.gov (United States)

Nola, Frank J. (Inventor)

1987-01-01

A control circuit is provided for a brushless three-phase dc motor which affords four quadrant control from a single command. The control circuit probes acceleration of the motor in both clockwise and counterclockwise directions and braking and generation in both clockwise and counterclockwise directions. In addition to turning on individual transistors of the transistor pairs connected to the phase windings of the motor for 120 deg periods while the other transistor of that pair is off, the control circuit also provides, in a future mode of operation, turning the two transistors of each pair on and off alternately at a phase modulation frequency during such a 120 deg period. A feedback signal is derived which is proportional to the motor current and which has a polarity consistent with the command signal, such that negative feedback results.

Ultra-low power circuits based on tunnel FETs for energy harvesting applications

OpenAIRE

Cavalheiro, David

2017-01-01

There has been a tremendous evolution in integrated circuit technology in the past decades. With the scaling of complementary metal-oxide-semiconductor (CMOS) transistors, faster, less power consuming and more complex chips per unit area have made possible electronic gadgets to evolve to what we see today. The increasing demand in electronic portability imposes low power consumption as a key metric to analog and digital circuit design. While dynamic power consumption decreases quadraticall...

General Tokamak Circuit Simulation Program-GTCSP

International Nuclear Information System (INIS)

Matsukawa, Makoto; Miura, Yushi; Aoyagi, Tetsuo.

1997-05-01

General Tokamak Circuit Simulation Program (GTCSP) was originally developed for the design work of JT-60 Power Supply System in JAERI. Therefore the prepared models (components) to be analyzed are generator, thyristor converter and coils. This is one of the unique points of GTCSP in comparison with other conventional electric circuit analysis program, because they make a circuit from the small devices such as resister, coil, condenser, transistor and so on. However, GTCSP is also clearly conventional because it is possible to construct an electric circuit freely with the prepared components. Moreover, a similar function could be realized by addition a new component to GTCSP. This report is assumed to be used as an User Manual of the GTCSP, not only to present the development and the analytical functions. Then some useful examples are described, and how to get graphic outputs are also mentioned. (author)

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Science.gov (United States)

Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

2000-01-01

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

A guide to printed circuit board design

CERN Document Server

Hamilton, Charles

1984-01-01

A Guide to Printed Circuit Board Design discusses the basic design principles of printed circuit board (PCB). The book consists of nine chapters; each chapter provides both text discussion and illustration relevant to the topic being discussed. Chapter 1 talks about understanding the circuit diagram, and Chapter 2 covers how to compile component information file. Chapter 3 deals with the design layout, while Chapter 4 talks about preparing the master artworks. The book also covers generating computer aided design (CAD) master patterns, and then discusses how to prepare the production drawing a

An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process

International Nuclear Information System (INIS)

Gao Peijun; Min Hao; Oh, N J

2009-01-01

A differential LC voltage controlled oscillator (VCO) employing parasitic vertical-NPN (V-NPN) transistors as a negative g m -cell is presented to improve the close-in phase noise. The V-NPN transistors have lower flicker noise compared to MOS transistors. DC and AC characteristics of the V-NPN transistors are measured to facilitate the VCO design. The proposed VCO is implemented in a 0.18 μm CMOS RF/mixed signal process, and the measurement results show the close-in phase noise is improved by 3.5-9.1 dB from 100 Hz to 10 kHz offset compared to that of a similar CMOS VCO. The proposed VCO consumes only 0.41 mA from a 1.5 V power supply. (semiconductor integrated circuits)

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors

Directory of Open Access Journals (Sweden)

Jiawei Zhang

2017-03-01

Full Text Available Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO and p-type tin monoxide (SnO is presented. The IGZO thin-film transistor (TFT shows a linear mobility of 11.9 cm2/(V∙s and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm2/(V∙s and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics.

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors.

Science.gov (United States)

Zhang, Jiawei; Yang, Jia; Li, Yunpeng; Wilson, Joshua; Ma, Xiaochen; Xin, Qian; Song, Aimin

2017-03-21

Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO) and p-type tin monoxide (SnO) is presented. The IGZO thin-film transistor (TFT) shows a linear mobility of 11.9 cm²/(V∙s) and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm²/(V∙s) and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics.

Base profile design for high-performance operation of bipolar transistors at liquid-nitrogen temperature

International Nuclear Information System (INIS)

Stork, J.M.C.; Harame, D.L.; Meyerson, B.S.; Nguyen, T.N.

1989-01-01

The base profile requirements of Si bipolar junction transistors (BJT's) high-performance operation at liquid-nitrogen temperature are examined. Measurements of thin epitaxial-base polysilicon-emitter n-p-n transistors with increasing base doping show the effects of bandgap narrowing, mobility changes, and carrier freezeout. At room temperature the collector current at low injection is proportional to the integrated base charge, independent of the impurity distribution. At temperatures below 150 Κ, however, minority injection is dominated by the peak base doping because of the greater effectiveness of bandgap narrowing. When the peak doping in the base approaches 10 19 cm -3 , the bandgap difference between emitter and base is sufficiently small that the current gain no longer monotonically decreases with lower temperature but instead shows a maximum as low as 180 Κ. The device design window appears limited at the low-current end by increased base-emitter leakage due to tunneling and by resistance control at the high-current end. Using the measured dc characteristics, circuit delay calculations are made to estimate the performance of an ECL ring oscillator at room and liquid-nitrogen temperatures. It is shown that if the base doping can be raised to 10 19 cm -3 while keeping the base thickness constant, the minimum delay at liquid nitrogen can approach the delay of optimized devices at room temperature

The dual role of multiple-transistor charge sharing collection in single-event transients

International Nuclear Information System (INIS)

Guo Yang; Chen Jian-Jun; He Yi-Bai; Liang Bin; Liu Bi-Wei

2013-01-01

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients (SETs) due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal—oxide semiconductor field-effect transistor (PMOS FET), but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies. (condensed matter: structural, mechanical, and thermal properties)

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

Energy Technology Data Exchange (ETDEWEB)

Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

Science.gov (United States)

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

International Nuclear Information System (INIS)

Li Shu; Zhang Tong

2008-01-01

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance

Circuit design techniques for non-crystalline semiconductors

CERN Document Server

Sambandan, Sanjiv

2012-01-01

Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

Nanogap Electrodes towards Solid State Single-Molecule Transistors.

Science.gov (United States)

Cui, Ajuan; Dong, Huanli; Hu, Wenping

2015-12-01

With the establishment of complementary metal-oxide-semiconductor (CMOS)-based integrated circuit technology, it has become more difficult to follow Moore's law to further downscale the size of electronic components. Devices based on various nanostructures were constructed to continue the trend in the minimization of electronics, and molecular devices are among the most promising candidates. Compared with other candidates, molecular devices show unique superiorities, and intensive studies on molecular devices have been carried out both experimentally and theoretically at the present time. Compared to two-terminal molecular devices, three-terminal devices, namely single-molecule transistors, show unique advantages both in fundamental research and application and are considered to be an essential part of integrated circuits based on molecular devices. However, it is very difficult to construct them using the traditional microfabrication techniques directly, thus new fabrication strategies are developed. This review aims to provide an exclusive way of manufacturing solid state gated nanogap electrodes, the foundation of constructing transistors of single or a few molecules. Such single-molecule transistors have the potential to be used to build integrated circuits. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A novel charge pump drive circuit for power MOSFETs

International Nuclear Information System (INIS)

Wang Songlin; Zhou Bo; Wang Hui; Guo Wangrui; Ye Qiang

2010-01-01

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW. (semiconductor integrated circuits)

Design procedure for millimeter-wave InP DHBT stacked power amplifiers

DEFF Research Database (Denmark)

Squartecchia, Michele; Johansen, Tom Keinicke; Midili, Virginio

2015-01-01

The stacked-transistor concept for power amplifiers (PA) has been investigated in this work. Specifically, this architecture has been applied in the design of millimeter-wave monolithic microwave integrated circuits (MMICs) using indium phosphide (InP) double heterojunction bipolar transistors...

Memristive device based on a depletion-type SONOS field effect transistor

Science.gov (United States)

Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

2017-06-01

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Microelectronic circuit design for energy harvesting systems

CERN Document Server

Di Paolo Emilio, Maurizio

2017-01-01

This book describes the design of microelectronic circuits for energy harvesting, broadband energy conversion, new methods and technologies for energy conversion. The author also discusses the design of power management circuits and the implementation of voltage regulators. Coverage includes advanced methods in low and high power electronics, as well as principles of micro-scale design based on piezoelectric, electromagnetic and thermoelectric technologies with control and conditioning circuit design. Provides a single-source reference to energy harvesting and its applications; Serves as a practical guide to microelectronics design for energy harvesting, with application to mobile power supplies; Enables readers to develop energy harvesting systems for wearable/mobile electronics.

Macromodels of digital integrated circuits for program packages of circuit engineering design

Science.gov (United States)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

CMOS digital integrated circuits a first course

CERN Document Server

Hawkins, Charles; Zarkesh-Ha, Payman

2016-01-01

This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

Transistor Small Signal Analysis under Radiation Effects

International Nuclear Information System (INIS)

Sharshar, K.A.A.

2004-01-01

A Small signal transistor parameters dedicate the operation of bipolar transistor before and after exposed to gamma radiation (1 Mrad up to 5 Mrads) and electron beam(1 MeV, 25 mA) with the same doses as a radiation sources, the electrical parameters of the device are changed. The circuit Model has been discussed.Parameters, such as internal emitter resistance (re), internal base resistance, internal collector resistance (re), emitter base photocurrent (Ippe) and base collector photocurrent (Ippe). These parameters affect on the operation of the device in its applications, which work as an effective element, such as current gain (hFE≡β)degradation it's and effective parameter in the device operation. Also the leakage currents (IcBO) and (IEBO) are most important parameters, Which increased with radiation doses. Theoretical representation of the change in the equivalent circuit for NPN and PNP bipolar transistor were discussed, the input and output parameters of the two types were discussed due to the change in small signal input resistance of the two types. The emitter resistance(re) were changed by the effect of gamma and electron beam irradiation, which makes a change in the role of matching impedances between transistor stages. Also the transistor stability factors S(Ico), S(VBE) and S(β are detected to indicate the transistor operations after exposed to radiation fields. In low doses the gain stability is modified due to recombination of induced charge generated during device fabrication. Also the load resistance values are connected to compensate the effect

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

Science.gov (United States)

Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

2012-01-01

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

Foundations for microstrip circuit design

CERN Document Server

Edwards, Terry

2016-01-01

Building on the success of the previous three editions, Foundations for Microstrip Circuit Design offers extensive new, updated and revised material based upon the latest research. Strongly design-oriented, this fourth edition provides the reader with a fundamental understanding of this fast expanding field making it a definitive source for professional engineers and researchers and an indispensable reference for senior students in electronic engineering. Topics new to this edition: microwave substrates, multilayer transmission line structures, modern EM tools and techniques, microstrip and planar transmision line design, transmission line theory, substrates for planar transmission lines, Vias, wirebonds, 3D integrated interposer structures, computer-aided design, microstrip and power-dependent effects, circuit models, microwave network analysis, microstrip passive elements, and slotline design fundamentals.

Electrical pulse burnout of transistors in intense ionizing radiation

International Nuclear Information System (INIS)

Hartman, E.F.; Evans, D.C.

1975-01-01

Tests examining possible synergistic effects of electrical pulses and ionizing radiation on transistors were performed and energy/power thresholds for transistor burnout determined. The effect of ionizing radiation on burnout thresholds was found to be minimal, indicating that electrical pulse testing in the absence of radiation produces burnout-threshold results which are applicable to IEMP studies. The conditions of ionized transistor junctions and radiation induced current surges at semiconductor device terminals are inherent in IEMP studies of electrical circuits

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

Science.gov (United States)

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-02

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

Uniformity of fully gravure printed organic field-effect transistors

International Nuclear Information System (INIS)

Hambsch, M.; Reuter, K.; Stanel, M.; Schmidt, G.; Kempa, H.; Fuegmann, U.; Hahn, U.; Huebler, A.C.

2010-01-01

Fully mass-printed organic field-effect transistors were made completely by means of gravure printing. Therefore a special printing layout was developed in order to avoid register problems in print direction. Upon using this layout, contact pads for source-drain electrodes of the transistors are printed together with the gate electrodes in one and the same printing run. More than 50,000 transistors have been produced and by random tests a yield of approximately 75% has been determined. The principle suitability of the gravure printed transistors for integrated circuits has been shown by the realization of ring oscillators.

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Shikha Panwar

2014-01-01

Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

Analog integrated circuits design for processing physiological signals.

Science.gov (United States)

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

Wireless transceiver circuits system perspectives and design aspects

CERN Document Server

Rhee, Woogeun

2015-01-01

This cutting-edge work contains comprehensive coverage of integrated circuit (IC) design for modern transceiver circuits and wireless systems. Ranging in scope from system perspectives to practical circuit design for emerging wireless applications, the book includes detailed discussions of transceiver architectures and system parameters, mm-wave circuits, ultra-low-power radios for biomedical and sensor applications, and the latest circuit techniques. Written by renowned international experts in IC industry and academia, the text is an ideal reference for engineers and researchers in the area

Circuit arrangement of an electronic component for the design of fail-safe protective circuits

International Nuclear Information System (INIS)

Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

1974-01-01

The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

Method for double-sided processing of thin film transistors

Science.gov (United States)

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2008-04-08

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

Energy Technology Data Exchange (ETDEWEB)

Curry, M. J. [Department of Physics and Astronomy, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); England, T. D.; Bishop, N. C.; Ten-Eyck, G.; Wendt, J. R.; Pluym, T.; Lilly, M. P.; Carroll, M. S. [Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); Carr, S. M. [Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States)

2015-05-18

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10–100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.

23rd workshop on Advances in Analog Circuit Design

CERN Document Server

Baschirotto, Andrea; Makinwa, Kofi

2015-01-01

This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    • Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing; • Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; • Presents material in a tutorial-based format.

Design and Simulation of a New Optimized Full-Adder Using Carbon Nano Tube Technology

Directory of Open Access Journals (Sweden)

Abbas Asadi Aghbolaghi

2015-07-01

Full Text Available The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition, subtraction, multiplication, and division. so, in this paper a new low power and high performance full adder cell has been proposed with the benefit of using carbon nano tube field effect transistors. The proposed design contains 12 CNTFET transistors which are connected in pass transistor logic style to make the desired functionality. Carbon Nano Tube Field Effect Transistor (CNTFET has modified electrical characteristics such as low power consumption and high speed in comparison with MOSFET transistor; The proposed design is simulated using Hspice software based on CNTFET model and 0.65V supply voltage. the simulations are done considering three different frequencies, and three different load capacitors. The simulation results, which demonstrated in tables and diagrams, proved the superiority of proposed design in terms of power consumption and performance (PDP compared to the existing counterparts.

Modeling and the analysis of control logic for a digital PWM controller based on a nano electronic single electron transistor

Directory of Open Access Journals (Sweden)

Rathnakannan Kailasam

2008-01-01

Full Text Available This paper describes the modelling and the analysis of control logic for a Nano-Device- based PWM controller. A comprehensive simple SPICE schematic model for Single Electron transistor has been proposed. The operation of basic Single Electron Transistor logic gates and SET flip flops were successfully designed and their performances analyzed. The proposed design for realizing the logic gates and flip-flops is used in constructing the PWM controller utilized for switching the buck converter circuit. The output of the converter circuit is compared with reference voltage, and when the error voltage and the reference are matched the latch is reset so as to generate the PWM signal. Due to the simplicity and accuracy of the compact model, the simulation time and speed are much faster, which makes it potentially applicable in large-scale circuit simulation. This study confirms that the SET-based PWM controller is small in size, consumes ultra low power and operates at high speeds without compromising any performance. In addition these devices are capable of measuring charges of extremely high sensitivity.

Problems of noise modeling in the presence of total current branching in high electron mobility transistor and field-effect transistor channels

International Nuclear Information System (INIS)

Shiktorov, P; Starikov, E; Gružinskis, V; Varani, L; Sabatini, G; Marinchio, H; Reggiani, L

2009-01-01

In the framework of analytical and hydrodynamic models for the description of carrier transport and noise in high electron mobility transistor/field-effect transistor channels the main features of the intrinsic noise of transistors are investigated under continuous branching of the current between channel and gate. It is shown that the current-noise and voltage-noise spectra at the transistor terminals contain an excess noise related to thermal excitation of plasma wave modes in the dielectric layer between the channel and gate. It is found that the set of modes of excited plasma waves can be governed by the external embedding circuits, thus violating a universal description of noise in terms of Norton and Thevenin noise generators

G(sup 4)FET Implementations of Some Logic Circuits

Science.gov (United States)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

Temperature dependence of the current in Schottky-barrier source-gated transistors

Science.gov (United States)

Sporea, R. A.; Overy, M.; Shannon, J. M.; Silva, S. R. P.

2015-05-01

The temperature dependence of the drain current is an important parameter in thin-film transistors. In this paper, we propose that in source-gated transistors (SGTs), this temperature dependence can be controlled and tuned by varying the length of the source electrode. SGTs comprise a reverse biased potential barrier at the source which controls the current. As a result, a large activation energy for the drain current may be present which, although useful in specific temperature sensing applications, is in general deleterious in many circuit functions. With support from numerical simulations with Silvaco Atlas, we describe how increasing the length of the source electrode can be used to reduce the activation energy of SGT drain current, while maintaining the defining characteristics of SGTs: low saturation voltage, high output impedance in saturation, and tolerance to geometry variations. In this study, we apply the dual current injection modes to obtain drain currents with high and low activation energies and propose mechanisms for their exploitation in future large-area integrated circuit designs.

Variability aware compact model characterization for statistical circuit design optimization

Science.gov (United States)

Qiao, Ying; Qian, Kun; Spanos, Costas J.

2012-03-01

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.

Circuit for automatic load sharing in parallel converter modules

Science.gov (United States)

Nagano, S. (Inventor)

1979-01-01

A nondissipative circuit for automatic load sharing in parallel converter modules having push-pull power transistors is presented. Each transistor has a separate current-sensing transformer and an impedance-adjusting transformer in series with its collector. The impedance-adjusting transformer functions as a current-controlled variable impedance that is responsive to the difference between the peak collector current of the transistor and the average peak current of all collector currents of power transistors in all modules, thereby to control the collector currents of all power transistors with reference to the average peak collector current.

Mouldable all-carbon integrated circuits.

Science.gov (United States)

Sun, Dong-Ming; Timmermans, Marina Y; Kaskela, Antti; Nasibulin, Albert G; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I; Ohno, Yutaka

2013-01-01

A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027 cm(2) V(-1) s(-1) and an ON/OFF ratio of 10(5). The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

Oscillator circuits frontiers in design, analysis and applications

CERN Document Server

2016-01-01

This book surveys recent developments in the design, analysis and applications of oscillator circuit design. It highlights developments in the analysis of synchronization and wave phenomena, new analytical and design methods and their application, and novel engineering applications of oscillator circuits.

The design of charge measurement circuit of MWPC

International Nuclear Information System (INIS)

Guan Xiaolei; Xiang Haisheng; Sheng Huayi; Zhao Yubin; Zhao Pingping; Zhang Hongyu; Jiang Xiaoshan; Zhao Jingwei; Zhao Dongxu

2010-01-01

It introduces the design of charge measurement (MQ) circuit of MWPC, including how MQ works in the whole MWPC readout electronic system, the architecture of MQ circuit, and the logic and algorithm design of FPGA. MQ circuit can also be applied to readout systems for other detectors. The test results in different working modes are provided. (authors)

Magnetophoretic transistors in a tri-axial magnetic field.

Science.gov (United States)

Abedini-Nassab, Roozbeh; Joh, Daniel Y; Albarghouthi, Faris; Chilkoti, Ashutosh; Murdoch, David M; Yellen, Benjamin B

2016-10-18

The ability to direct and sort individual biological and non-biological particles into spatially addressable locations is fundamentally important to the emerging field of single cell biology. Towards this goal, we demonstrate a new class of magnetophoretic transistors, which can switch single magnetically labeled cells and magnetic beads between different paths in a microfluidic chamber. Compared with prior work on magnetophoretic transistors driven by a two-dimensional in-plane rotating field, the addition of a vertical magnetic field bias provides significant advantages in preventing the formation of particle clumps and in better replicating the operating principles of circuits in general. However, the three-dimensional driving field requires a complete redesign of the magnetic track geometry and switching electrodes. We have solved this problem by developing several types of transistor geometries which can switch particles between two different tracks by either presenting a local energy barrier or by repelling magnetic objects away from a given track, hereby denoted as "barrier" and "repulsion" transistors, respectively. For both types of transistors, we observe complete switching of magnetic objects with currents of ∼40 mA, which is consistent over a range of particle sizes (8-15 μm). The switching efficiency was also tested at various magnetic field strengths (50-90 Oe) and driving frequencies (0.1-0.6 Hz); however, we again found that the device performance only weakly depended on these parameters. These findings support the use of these novel transistor geometries to form circuit architectures in which cells can be placed in defined locations and retrieved on demand.

Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

KAUST Repository

Hanna, Amir; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2015-01-01

We report a Wavy Channel (WC) architecture thin film transistor (TFT) for extended device width by integrating continuous vertical fin like features with lateral continuous plane in the substrate. For a WC TFT which has 50% larger device width, the enhancement in the output drive current is 100%, when compared to a conventional planar TFT consuming the same chip area. This current increase is attributed to both the extra width and enhanced field effect mobility due to corner effects. This shows the potential of WC architecture to boast circuit performance without the need for aggressive gate length scaling. © 2015 IEEE.

Wavy Channel architecture thin film transistor (TFT) using amorphous zinc oxide for high-performance and low-power semiconductor circuits

KAUST Repository

Hanna, Amir

2015-08-12

We report a Wavy Channel (WC) architecture thin film transistor (TFT) for extended device width by integrating continuous vertical fin like features with lateral continuous plane in the substrate. For a WC TFT which has 50% larger device width, the enhancement in the output drive current is 100%, when compared to a conventional planar TFT consuming the same chip area. This current increase is attributed to both the extra width and enhanced field effect mobility due to corner effects. This shows the potential of WC architecture to boast circuit performance without the need for aggressive gate length scaling. © 2015 IEEE.

CAD-CAM printed circuit board design

Science.gov (United States)

Agy, W. E.

A step-by-step procedure for a printed circuit design achieved by CAD is presented. The operator at the interactive CRT station moves a stylus across a graphics tablet and intersperses commands which result in computer-generated pictorial forms on the screen that were drawn on the pad. Standard symbols are used for commands allowing, for instance, connections to be made of specific types in certain locations, which can be automatically edited from a materials list. An entire network of drawn lines can be referenced by a signal name for recall, and a finished circuit schematic can be checked for designs rules compliance, including fault reporting in terms of designator/pin number. A map may be present delineating the boundaries of the circuitry area, and previously completed circuitry segments can be recalled for piece-by-piece assembly of the circuit board.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

Science.gov (United States)

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Multiple-channel detection of cellular activities by ion-sensitive transistors

Science.gov (United States)

Machida, Satoru; Shimada, Hideto; Motoyama, Yumi

2018-04-01

An ion-sensitive field-effect transistor to record cellular activities was demonstrated. This field-effect transistor (bio transistor) includes cultured cells on the gate insulator instead of gate electrode. The bio transistor converts a change in potential underneath the cells into variation of the drain current when ion channels open. The bio transistor has high detection sensitivity to even minute variations in potential utilizing a subthreshold swing region. To open ion channels, a reagent solution (acetylcholine) was added to a human-originating cell cultured on the bio transistor. The drain current was successfully decreased with the addition of acetylcholine. Moreover, we attempted to detect the opening of ion channels using a multiple-channel measurement circuit containing several bio transistors. As a consequence, the drain current distinctly decreased only after the addition of acetylcholine. We confirmed that this measurement system including bio transistors enables to observation of cellular activities sensitively and simultaneously.

RF microwave circuit design for wireless applications

CERN Document Server

Rohde, Ulrich L

2012-01-01

Provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling the newest IC technologies Revised and completely updated, RF/Microwave Circuit Design for Wireless Applications, Second Edition is a unique, state-of-the-art guide to wireless integrated circuit design that provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling even the newest IC technologies. It emphasizes practical design solutions for high-performance devices and circuitry, incorporating ample exa

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

A pattern recognition approach to transistor array parameter variance

Science.gov (United States)

da F. Costa, Luciano; Silva, Filipi N.; Comin, Cesar H.

2018-06-01

The properties of semiconductor devices, including bipolar junction transistors (BJTs), are known to vary substantially in terms of their parameters. In this work, an experimental approach, including pattern recognition concepts and methods such as principal component analysis (PCA) and linear discriminant analysis (LDA), was used to experimentally investigate the variation among BJTs belonging to integrated circuits known as transistor arrays. It was shown that a good deal of the devices variance can be captured using only two PCA axes. It was also verified that, though substantially small variation of parameters is observed for BJT from the same array, larger variation arises between BJTs from distinct arrays, suggesting the consideration of device characteristics in more critical analog designs. As a consequence of its supervised nature, LDA was able to provide a substantial separation of the BJT into clusters, corresponding to each transistor array. In addition, the LDA mapping into two dimensions revealed a clear relationship between the considered measurements. Interestingly, a specific mapping suggested by the PCA, involving the total harmonic distortion variation expressed in terms of the average voltage gain, yielded an even better separation between the transistor array clusters. All in all, this work yielded interesting results from both semiconductor engineering and pattern recognition perspectives.

Design, Analysis and Test of Logic Circuits Under Uncertainty

CERN Document Server

Krishnaswamy, Smita; Hayes, John P

2013-01-01

Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...

Active component modeling for analog integrated circuit design. Model parametrization and implementation in the SPICE-PAC circuit simulator; Modelisation de composants actifs pour la CAO de circuits integres analogiques. Parametrage et implantation de modeles dans le simulateur SPICE-PAC

Energy Technology Data Exchange (ETDEWEB)

Marchal, Xavier

1992-06-19

In order to use CAD efficiently in the analysis and design of electronic Integrated circuits, adequate modeling of active non-linear devices such as MOSFET transistors must be available to the designer. Many mathematical forms can be given to those models, such as explicit relations, or implicit equations to be solved. A major requirement in developing MOS transistor models for IC simulation is the availability of electrical characteristic curves over a wide range of channel width and length, including the sub-micrometer range. To account in a convenient way for bulk charge influence on I{sub DS} = f(V{sub DS}, V{sub GS}, v{sub BS}) device characteristics, all 3 standard SPICE MOS models use an empirical fitting parameter called the 'charge sharing factor'. Unfortunately, this formulation produces models which only describe correctly either some of the short channel phenomena, or some particular operating conditions (low injection, avalanche effect, etc.). We present here a cellular model (CDM = Charge Distributed Model) implemented in the open modular SPICE-PAC Simulator; this model is derived from the 4-terminal WANG charge controlled MOSFET model, using the charge sheet approximation. The CDM model describes device characteristics in ail operating regions without introducing drain current discontinuities and without requiring a 'charge sharing factor'. A usual problem to be faced by designers when they simulate MOS ICs is to find a reliable source of model parameters. Though most models have a physical basis, some of their parameters cannot be easily estimated from physical considerations. It can also happen that physically determined parameters values do not produce a good fit to measured device characteristics. Thus it is generally necessary to extract model parameters from measured transistor data, to ensure that model equations approximate measured curves accurately enough. Model parameters extraction can be done in 2 different ways, exposed in this thesis

An integrated circuit switch

Science.gov (United States)

Bonin, E. L.

1969-01-01

Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

Monolithic integrated photoreceiver for 1.3--1.55-μm wavelengths: Association of a Schottky photodiode and a field-effect transistor on GaInP-GaInAs heteroepitaxy

International Nuclear Information System (INIS)

Therani, A.H.; Decoster, D.; Vilcot, J.P.; Razeghi, M.

1988-01-01

We present a monolithic integrated circuit associating a Schottky photodiode and a field-effect transistor which has been fabricated, for the first time, on Ga/sub 0.49/In/sub 0.51/P/Ga/sub 0.47/In/sub 0.53/As strained heteroepitaxial material. Static, dynamic, and noise properties of the Schottky photodiode, the field-effect transistor, and the integrated circuit have been investigated and are reported. As an example, dynamic responsivity up to 50 A/W can be achieved at 1.3-μm wavelength for the integrated photoreceiver. The performance of the device is discussed, taking into account the integrated circuit design and the main characteristics of the material

RF Circuit Design in Nanometer CMOS

NARCIS (Netherlands)

Nauta, Bram

2007-01-01

With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

Controllable clock circuit design in PEM system

International Nuclear Information System (INIS)

Sun Yunhua; Wang Peihua; Hu Tingting; Feng Baotong; Shuai Lei; Huang Huan; Wei Shujun; Li Ke; Zhao Jingwei; Wei Long

2011-01-01

A high-precision synchronized clock circuit design will be presented, which can supply steady, reliable and anti-jamming clock signal for the data acquirement (DAQ) system of Positron Emission Mammography (PEM). This circuit design is based on the Single-Chip Microcomputer and high-precision clock chip, and can achieve multiple controllable clock signals. The jamming between the clock signals can be reduced greatly with the differential transmission. Meanwhile, the adoption of CAN bus control in the clock circuit can prompt the clock signals to be transmitted or masked simultaneously when needed. (authors)

Controllable clock circuit design in PEM system

International Nuclear Information System (INIS)

Sun Yunhua; Wang Peilin; Hu Tingting; Feng Baotong; Shuai Lei; Huang Huan; Wei Shujun; Li Ke; Zhao Jingwei; Wei Long

2010-01-01

A high-precision synchronized clock circuit design will be presented, which can supply steady, reliable and anti-jamming clock signal for the data acquirement (DAQ) system of Positron Emission Mammography (PEM). This circuit design is based on the Single-Chip Microcomputer and high-precision clock chip, and can achieve multiple controllable clock signals. The jamming between the clock signals can be reduced greatly with the differential transmission. Meanwhile, the adoption of CAN bus control in the clock circuit can prompt the clock signals to be transmitted or masked simultaneously when needed. (authors)

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

Directory of Open Access Journals (Sweden)

Joyjit Mukhopadhyay

2012-01-01

Full Text Available This paper presents a technique for the modeling and design of a nano scale CMOS inverter circuit using artificial neural network and particle swarm optimization algorithm such that the switching characteristics of the circuit is symmetric, that is, has nearly equal rise and fall time and equal output high-to-low and low-to-high propagation delay. The channel width of the transistors and the load capacitor value are taken as design parameters. The designed circuit has been implemented at the transistor-level and simulated using TSPICE for 45 nm process technology. The PSO-generated results have been compared with SPICE results. A very good accuracy has been achieved. In addition, the advantage of the present approach over an existing approach for the same purpose has been demonstrated through simulation results.

Switching Characteristics of Ferroelectric Transistor Inverters

Science.gov (United States)

Laws, Crystal; Mitchell, Coey; MacLeod, Todd C.; Ho, Fat D.

2010-01-01

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

Practical design of digital circuits basic logic to microprocessors

CERN Document Server

Kampel, Ian

1983-01-01

Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

Science.gov (United States)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Design of 3D integrated circuits and systems

CERN Document Server

Sharma, Rohit

2014-01-01

Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

Continuous-Wave Single-Photon Transistor Based on a Superconducting Circuit

DEFF Research Database (Denmark)

Kyriienko, Oleksandr; Sørensen, Anders Søndberg

2016-01-01

We propose a microwave frequency single-photon transistor which can operate under continuous wave probing and represents an efficient single microwave photon detector. It can be realized using an impedance matched system of a three level artificial ladder-type atom coupled to two microwave cavities...... and the appearance of a photon flux leaving the second cavity through a separate input-output port. The proposal does not require time variation of the probe signals, thus corresponding to a passive version of a single-photon transistor. The resulting device is robust to qubit dephasing processes, possesses low dark...

Low cost design of microprocessor EDAC circuit

International Nuclear Information System (INIS)

Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

2015-01-01

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

Introduction of circuit design on RFID system

International Nuclear Information System (INIS)

Pak, Sunho

2007-06-01

This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

Introduction of circuit design on RFID system

Energy Technology Data Exchange (ETDEWEB)

Pak, Sunho

2007-06-15

This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

Integrated circuits and logic operations based on single-layer MoS2.

Science.gov (United States)

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

Design of a High Linearity Four-Quadrant Analog Multiplier in Wideband Frequency Range

Directory of Open Access Journals (Sweden)

Abdul kareem Mokif Obais

2017-05-01

Full Text Available In this paper, a voltage mode four quadrant analog multiplier in the wideband frequency rangeis designed using a wideband operational amplifier (OPAMP and squaring circuits. The wideband OPAMP is designed using 10 identical NMOS transistorsand operated with supply voltages of ±12V. Two NMOS transistors and two wideband OPAMP are utilized in the design of the proposed squaring circuit. All the NMOS transistors are based on 0.35µm NMOStechnology. The multiplier has input and output voltage ranges of ±10 V, high range of linearity from -10 V to +10 V, and cutoff frequency of about 5 GHz. The proposed multiplier is designed on PSpice in Orcad 16.6

Transistor regenerative spectrometer for 14N nuclear quadrupole resonance study

International Nuclear Information System (INIS)

Anferov, V.P.; Mikhal'kov, V.M.

1981-01-01

Improvement of the Robinson transducer for investigations of nuclear quadrupole resonance (NQR) in 14 N is described. Amplifier of the suggested transducer is made using p-n field effect transistor and small-noise SHF bipolar transistor. Such a circuit permits to obtain optimal relation between input resistance, low-frequency noises and transconductance which provides uniform gain of the transducer in the frequency range of 0.6-12 MHz and permits to construct a transistor spectrometer of NQR not yielding to a lamp spectrometer in sensitivity [ru

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

Directory of Open Access Journals (Sweden)

A. Kishore Kumar

2013-01-01

Full Text Available Asynchronous adiabatic logic (AAL is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

Test and Diagnosis of Integrated Circuits

OpenAIRE

Bosio , Alberto

2015-01-01

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

Circuit and interconnect design for high bit-rate applications

NARCIS (Netherlands)

Veenstra, H.

2006-01-01

This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate

Joule-Thief Circuit Performance for Electricity Energy Saving of Emergency Lamps

Science.gov (United States)

Nuryanto Budisusila, Eka; Arifin, Bustanul

2017-04-01

The alternative energy such as battery as power source is required as energy source failures. The other need is outdoor lighting. The electrical power source is expected to be a power saving, optimum and has long life operating. The Joule-Thief circuit is one of solution method for energy saving by using raised electromagnetic force on cored coil when there is back-current. This circuit has a transistor operated as a switch to cut voltage and current flowing along the coils. The present of current causing magnetic induction and generates energy. Experimental prototype was designed by using battery 1.5V to activate Light Emitting Diode or LED as load. The LED was connected in parallel or serial circuit configuration. The result show that the joule-thief circuit able to supply LED circuits up to 40 LEDs.

A photocurrent compensation method of bipolar transistors under high dose rate radiation and its experimental research

International Nuclear Information System (INIS)

Yin Xuesong; Liu Zhongli; Li Chunji; Yu Fang

2005-01-01

Experiment using discrete bipolar transistors has been performed to verify the effect of the photocurrent compensation method. The theory of the dose rate effects of bipolar transistors and the photocurrent compensation method are introduced. The comparison between the response of hardened and unhardened circuits under high dose rate radiation is discussed. The experimental results show instructiveness to the hardness of bipolar integrated circuits under transient radiation. (authors)

On stethoscope design: a challenge for biomedical circuit designers.

Science.gov (United States)

Hahn, A W

2001-01-01

Most clinicians learned the art and science of auscultation using an acoustic stethoscope. While many models of electronic stethoscopes have been marketed over the years, none of them seem to do a very good job of emulating the most common forms of acoustic stethoscopes available. This paper is an appeal to biomedical circuit designers to learn more about the acoustics of commonly used stethoscopes and to develop an appropriate group of circuits which would emulate them much like music synthesizers can emulate almost any musical instrument. The implications are for creative designers to move toward a rational and acceptable design for both personal physician use and for telemedicine.

Validation of Nonlinear Bipolar Transistor Model by Small-Signal Measurements

DEFF Research Database (Denmark)

Vidkjær, Jens; Porra, V.; Zhu, J.

1992-01-01

A new method for the validity analysis of nonlinear transistor models is presented based on DC-and small-signal S-parameter measurements and realistic consideration of the measurement and de-embedding errors and singularities of the small-signal equivalent circuit. As an example, some analysis...... results for an extended Gummel Poon model are presented in the case of a UHF bipolar power transistor....

Unipolar n-Type Black Phosphorus Transistors with Low Work Function Contacts.

Science.gov (United States)

Wang, Ching-Hua; Incorvia, Jean Anne C; McClellan, Connor J; Yu, Andrew C; Mleczko, Michal J; Pop, Eric; Wong, H-S Philip

2018-05-09

Black phosphorus (BP) is a promising two-dimensional (2D) material for nanoscale transistors, due to its expected higher mobility than other 2D semiconductors. While most studies have reported ambipolar BP with a stronger p-type transport, it is important to fabricate both unipolar p- and n-type transistors for low-power digital circuits. Here, we report unipolar n-type BP transistors with low work function Sc and Er contacts, demonstrating a record high n-type current of 200 μA/μm in 6.5 nm thick BP. Intriguingly, the electrical transport of the as-fabricated, capped devices changes from ambipolar to n-type unipolar behavior after a month at room temperature. Transmission electron microscopy analysis of the contact cross-section reveals an intermixing layer consisting of partly oxidized metal at the interface. This intermixing layer results in a low n-type Schottky barrier between Sc and BP, leading to the unipolar behavior of the BP transistor. This unipolar transport with a suppressed p-type current is favorable for digital logic circuits to ensure a lower off-power consumption.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric

Science.gov (United States)

Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu

2016-05-01

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Analog circuit design art, science and personalities

CERN Document Server

Williams, Jim

1991-01-01

This book is far more than just another tutorial or reference guide - it's a tour through the world of analog design, combining theory and applications with the philosophies behind the design process. Readers will learn how leading analog circuit designers approach problems and how they think about solutions to those problems. They'll also learn about the `analog way' - a broad, flexible method of thinking about analog design tasks.A comprehensive and useful guide to analog theory and applications. Covers visualizing the operation of analog circuits. Looks at how to rap

Plasma wave instability and amplification of terahertz radiation in field-effect-transistor arrays

International Nuclear Information System (INIS)

Popov, V V; Tsymbalov, G M; Shur, M S

2008-01-01

We show that the strong amplification of terahertz radiation takes place in an array of field-effect transistors at small DC drain currents due to hydrodynamic plasmon instability of the collective plasmon mode. Planar designs compatible with standard integrated circuit fabrication processes and strong coupling of terahertz radiation to plasmon modes in FET arrays make such arrays very attractive for potential applications in solid-state terahertz amplifiers and emitters

Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

Science.gov (United States)

Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

2017-07-01

Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

Synthetic Biology: A Unifying View and Review Using Analog Circuits.

Science.gov (United States)

Teo, Jonathan J Y; Woo, Sung Sik; Sarpeshkar, Rahul

2015-08-01

We review the field of synthetic biology from an analog circuits and analog computation perspective, focusing on circuits that have been built in living cells. This perspective is well suited to pictorially, symbolically, and quantitatively representing the nonlinear, dynamic, and stochastic (noisy) ordinary and partial differential equations that rigorously describe the molecular circuits of synthetic biology. This perspective enables us to construct a canonical analog circuit schematic that helps unify and review the operation of many fundamental circuits that have been built in synthetic biology at the DNA, RNA, protein, and small-molecule levels over nearly two decades. We review 17 circuits in the literature as particular examples of feedforward and feedback analog circuits that arise from special topological cases of the canonical analog circuit schematic. Digital circuit operation of these circuits represents a special case of saturated analog circuit behavior and is automatically incorporated as well. Many issues that have prevented synthetic biology from scaling are naturally represented in analog circuit schematics. Furthermore, the deep similarity between the Boltzmann thermodynamic equations that describe noisy electronic current flow in subthreshold transistors and noisy molecular flux in biochemical reactions has helped map analog circuit motifs in electronics to analog circuit motifs in cells and vice versa via a `cytomorphic' approach. Thus, a body of knowledge in analog electronic circuit design, analysis, simulation, and implementation may also be useful in the robust and efficient design of molecular circuits in synthetic biology, helping it to scale to more complex circuits in the future.

Implementation of Self-Bias Transistor on Voting Logic

International Nuclear Information System (INIS)

Harzawardi Hasim; Syirrazie Che Soh

2014-01-01

Study in the eld of digital integrated circuit (IC) already become common to the modern industrial. Day by day we have been introduced with new gadget that was developed based on transistor. This paper will study the implementation of self-bias transistor on voting logic. The self-bias transistor will connected both on pull-up network and pull-down network. On previous research, study on comparison of total number of transistors, time propagation delay, and frequency between NAND and NOR gate of voting logic. It's show, with the same number of transistor, NAND gate achieve high frequency and low time propagation delay compare to NOR gate. We extend this analysis by comparing the total number of transistor, time propagation delay, frequency and power dissipation between common NAND gate with self-bias NAND gate. Extensive LTSpice simulations were performed using IBM 90 nm CMOS(Complementary Metal Oxide Semiconductor) process technology. The result show self-bias voting NAND gate consumes 54 % less power dissipation, 43% slow frequency and 43 % high time propagation delay compare to common voting NAND gate. (author)

25th workshop on Advances in Analog Circuit Design

CERN Document Server

Harpe, Pieter; Makinwa, Kofi

2017-01-01

This book is based on the 18 tutorials presented during the 25th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of continuous-time sigma-delta modulators, automotive electronics, and power management. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

TCAD analysis of short-circuit oscillations in IGBTs

DEFF Research Database (Denmark)

Reigosa, Paula Diaz; Iannuzzo, Francesco; Rahimo, Munaf

2017-01-01

Insulated-Gate Bipolar Transistors (IGBTs) exhibit a gate-voltage oscillation phenomenon during short-circuit, which can result in a gate-oxide breakdown. The oscillations have been investigated through device simulations and experimental investigations of a 3.3-kV IGBT. It has been found...... during short circuit....

Applications of modularized circuit designs in a new hyper-chaotic system circuit implementation

International Nuclear Information System (INIS)

Wang Rui; Sun Hui; Wang Jie-Zhi; Wang Lu; Wang Yan-Chao

2015-01-01

Modularized circuit designs for chaotic systems are introduced in this paper. Especially, a typical improved modularized design strategy is proposed and applied to a new hyper-chaotic system circuit implementation. In this paper, the detailed design procedures are described. Multisim simulations and physical experiments are conducted, and the simulation results are compared with Matlab simulation results for different system parameter pairs. These results are consistent with each other and they verify the existence of the hyper-chaotic attractor for this new hyper-chaotic system. (paper)

Scaling of graphene integrated circuits.

Science.gov (United States)

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

New way on designing majorant coincidence circuits

International Nuclear Information System (INIS)

Gajdamaka, R.I.; Kalinnikov, V.A.; Nikityuk, N.M.; Shirikov, V.P.

1982-01-01

A new way of designing fast devices of combinatorial selection by the number of particles passing through a multichannel charged particle detector is decribed. The algorithm of their operation is based on modern algebraic coding theory. By application of analytical computational methods Boolean expressions can be obtianed for designing basic circuits for a large number of inputs. An example of computation of 15 inputs majorant coincidence circuit is considered

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

Science.gov (United States)

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

Science.gov (United States)

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Designing Asynchronous Circuits for Low Power: An IFIR Filter

DEFF Research Database (Denmark)

Nielsen, Lars Skovby; Sparsø, Jens

1999-01-01

This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated...

Insulated transcriptional elements enable precise design of genetic circuits.

Science.gov (United States)

Zong, Yeqing; Zhang, Haoqian M; Lyu, Cheng; Ji, Xiangyu; Hou, Junran; Guo, Xian; Ouyang, Qi; Lou, Chunbo

2017-07-03

Rational engineering of biological systems is often complicated by the complex but unwanted interactions between cellular components at multiple levels. Here we address this issue at the level of prokaryotic transcription by insulating minimal promoters and operators to prevent their interaction and enable the biophysical modeling of synthetic transcription without free parameters. This approach allows genetic circuit design with extraordinary precision and diversity, and consequently simplifies the design-build-test-learn cycle of circuit engineering to a mix-and-match workflow. As a demonstration, combinatorial promoters encoding NOT-gate functions were designed from scratch with mean errors of 96% using our insulated transcription elements. Furthermore, four-node transcriptional networks with incoherent feed-forward loops that execute stripe-forming functions were obtained without any trial-and-error work. This insulation-based engineering strategy improves the resolution of genetic circuit technology and provides a simple approach for designing genetic circuits for systems and synthetic biology.Unwanted interactions between cellular components can complicate rational engineering of biological systems. Here the authors design insulated minimal promoters and operators that enable biophysical modeling of bacterial transcription without free parameters for precise circuit design.

Development of high-performance printed organic field-effect transistors and integrated circuits.

Science.gov (United States)

Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

2015-10-28

Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

Total dose effects on elementary transistors of a comparator in bipolar technology

International Nuclear Information System (INIS)

Sarrabayrouse, G.; Guerre, F.X.

1995-01-01

In the present work we investigate elementary transistors behaviour of an Integrated Circuit using junction isolation bipolar technology. Polarization conditions and dose rate effects on the main elementary transistor types are analysed. Furthermore, the IC electronic function degradations are studied. Finally, a comparison between the function degradations and the elementary component ones is attempted. (author)

Programming languages for circuit design.

Science.gov (United States)

Pedersen, Michael; Yordanov, Boyan

2015-01-01

This chapter provides an overview of a programming language for Genetic Engineering of Cells (GEC). A GEC program specifies a genetic circuit at a high level of abstraction through constraints on otherwise unspecified DNA parts. The GEC compiler then selects parts which satisfy the constraints from a given parts database. GEC further provides more conventional programming language constructs for abstraction, e.g., through modularity. The GEC language and compiler is available through a Web tool which also provides functionality, e.g., for simulation of designed circuits.

Research of the voltage and current stabilization processes by using the silicon field-effect transistor

International Nuclear Information System (INIS)

Karimov, A.V.; Yodgorova, D.M.; Kamanov, B.M.; Giyasova, F.A.; Yakudov, A.A.

2012-01-01

The silicon field-effect transistors were investigated to use in circuits for stabilization of current and voltage. As in gallium arsenide field-effect transistors, in silicon field-effect transistors with p-n-junction a new mechanism of saturation of the drain current is experimentally found out due to both transverse and longitudinal compression of channel by additional resistance between the source and the gate of the transistor. The criteria for evaluating the coefficients of stabilization of transient current suppressors and voltage stabilizator based on the field-effect transistor are considered. (authors)

Comparing SiGe HBT Amplifier Circuits for Fast Single-shot Spin Readout

Science.gov (United States)

England, Troy; Curry, Matthew; Carr, Stephen; Mounce, Andrew; Jock, Ryan; Sharma, Peter; Bureau-Oxton, Chloe; Rudolph, Martin; Hardin, Terry; Carroll, Malcolm

Fast, low-power quantum state readout is one of many challenges facing quantum information processing. Single electron transistors (SETs) are potentially fast, sensitive detectors for performing spin readout. From a circuit perspective, however, their output impedance and nonlinear conductance are ill suited to drive the parasitic capacitance of coaxial conductors used in cryogenic environments, necessitating a cryogenic amplification stage. We will compare two amplifiers based on single-transistor circuits implemented with silicon germanium heterojunction bipolar transistors. Both amplifiers provide gain at low power levels, but the dynamics of each circuit vary significantly. We will explore the gain mechanisms, linearity, and noise of each circuit and explain the situations in which each amplifier is best used. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

New pixel circuit compensating poly-si TFT threshold-voltage shift for a driving AMOLED

International Nuclear Information System (INIS)

Fan, C. L.; Lin, Y. Y.; Lin, B. S.; Chang, J. Y.; Fan, C. L.; Chang, H. C.

2010-01-01

This study presents a novel pixel circuit that uses only n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS-TFTs) to simplify the fabrication process of active matrix organic light-emitting diode (AMOLED) displays. The proposed pixel circuit consists of five switching TFTs, one driving TFT (DTFT), and two capacitors. The output current and the OLED anode voltage error rates are about 3% and 0.7%, respectively. Thus, the pixel circuit can realize uniform output current with high immunity to the poly-Si TFT threshold voltage deviation. The proposed novel pixel design has great potential for use in large-size, high-resolution AMOLED displays.

The Fault Detection, Localization, and Tolerant Operation of Modular Multilevel Converters with an Insulated Gate Bipolar Transistor (IGBT Open Circuit Fault

Directory of Open Access Journals (Sweden)

Wei Li

2018-04-01

Full Text Available Reliability is one of the critical issues for a modular multilevel converter (MMC since it consists of a large number of series-connected power electronics submodules (SMs. In this paper, a complete control strategy including fault detection, localization, and tolerant operation is proposed for the MMC under an insulated gate bipolar transistor (IGBT open circuit fault. According to the output characteristics of the SM with the open-circuit fault of IGBT, a fault detection method based on the circulating current and output current observation is used. In order to further precisely locate the position of the faulty SM, a fault localization method based on the SM capacitor voltage observation is developed. After the faulty SM is isolated, the continuous operation of the converter is ensured by adopting the fault-tolerant strategy based on the use of redundant modules. To verify the proposed fault detection, fault localization, and fault-tolerant operation strategies, a 900 kVA MMC system under the conditions of an IGBT open circuit is developed in the Matlab/Simulink platform. The capabilities of rapid detection, precise positioning, and fault-tolerant operation of the investigated detection and control algorithms are also demonstrated.

Circuit design for RF transceivers

CERN Document Server

Leenaerts, Domine; Vaucher, Cicero S

2007-01-01

Second edition of this successful 2001 RF Circuit Design book, has been updated, latest technology reviews have been added as well as several actual case studies. Due to the authors being active in industry as well as academia, this should prove to be an essential guide on RF Transceiver Design for students and engineers.

MOSFET analog memory circuit achieves long duration signal storage

Science.gov (United States)

1966-01-01

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Design method for a digitally trimmable MOS transistor structure

DEFF Research Database (Denmark)

Ning, Feng; Bruun, Erik

1996-01-01

A digitally trimmable MOS transistor is a MOS transistor consisting of a drain, a source, and a main gate as well as several subgates. The transconductance of the transistor is tunabledigitally by means of connecting subgates either to the main gate or to the source terminal. In this paper, a sys...

Pulse GaAs field transistor amplifier with subnanosecond time transient

International Nuclear Information System (INIS)

Sidnev, A.N.

1987-01-01

Pulse amplifier on fast field effect GaAs transistors with Schottky barrier is described. The amplifier contains four cascades, the first three of which are made on combined transistors on the common-drain circuit. The last cascade is made on high-power field effect GaAs transistor for coordination with 50 ohm load. The amplifier operates within the range of input signals from 0.5 up to 100 mV with repetition frequency up to 16 Hz, The gain of the amplifier is ≅ 20 dB. The setting time at output pulses amplitude up to 1 V constitutes ∼ 0.2 ns

A multiwire ionization chamber readout circuit using current mirrors

International Nuclear Information System (INIS)

Rawnsley, W.R.; Smith, D.; Moskven, T.

1997-01-01

A circuit which utilizes current mirrors has been used to apply high voltage bias to the wires of a multiwire ionization chamber (MWIC) profile monitor while still allowing measurement of the beam-induced ion-electron currents collected on the wires. Bias voltages of up to 250 V have been used while wire currents over a range of 0.5 nA to 50 nA have been measured. The circuit is unipolar but can be designed for positive or negative bias. The mirrors also provide a current gain of 10, reducing the effects of transistor leakage and extending the useful range of the circuit to lower signal levels. A module containing 32 Wilson current mirrors has been constructed and is used with a MWIC monitor in TRIUMF close-quote s Parity experiment beamline. copyright 1997 American Institute of Physics

Enhanced low dose rate sensitivity (ELDRS) in a voltage comparator which only utilizes complementary vertical NPN and PNP transistors

International Nuclear Information System (INIS)

Krieg, J.F.; Titus, J.L.; Emily, D.; Gehlhausen, M.; Swonger, J.; Platteter, D.

1999-01-01

For the first time, enhanced low dose rate sensitivity (ELDRS) is reported in a vertical bipolar process. A radiation hardness assurance (RHA) test method was successfully demonstrated on a linear circuit, the HS139RH quad comparator, and its discrete transistor elements. This circuit only uses vertical NPN and PNP transistors. Radiation tests on the HS139RH were performed at 25 C using dose rates of 50 rd(Si)/s, 100 mrd(Si)/s and 10 mrd(Si)/s, and at 100 C using a dose rate of 10 rd(Si)/s. Tests at dose rates of 50 rd(Si)/s at 25 C and 10 rd(Si)/s at 100 C were performed on discrete vertical NPN and PNP transistor elements which comprise the HS139RH. Transistor and circuit responses were evaluated. The die's passivation overcoat layers were varied to examine the effect of removing a nitride layer and thinning a deposited SiO 2 (silox) layer

N-type organic electrochemical transistors with stability in water

KAUST Repository

Giovannitti, Alexander

2016-10-07

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurements in water show no degradation when tested for 2 h under continuous cycling. This demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.

N-type organic electrochemical transistors with stability in water

KAUST Repository

Giovannitti, Alexander; Nielsen, Christian B.; Sbircea, Dan-Tiberiu; Inal, Sahika; Donahue, Mary; Niazi, Muhammad Rizwan; Hanifi, David A.; Amassian, Aram; Malliaras, George G.; Rivnay, Jonathan; McCulloch, Iain

2016-01-01

Organic electrochemical transistors (OECTs) are receiving significant attention due to their ability to efficiently transduce biological signals. A major limitation of this technology is that only p-type materials have been reported, which precludes the development of complementary circuits, and limits sensor technologies. Here, we report the first ever n-type OECT, with relatively balanced ambipolar charge transport characteristics based on a polymer that supports both hole and electron transport along its backbone when doped through an aqueous electrolyte and in the presence of oxygen. This new semiconducting polymer is designed specifically to facilitate ion transport and promote electrochemical doping. Stability measurements in water show no degradation when tested for 2 h under continuous cycling. This demonstration opens the possibility to develop complementary circuits based on OECTs and to improve the sophistication of bioelectronic devices.

Automating analog design: Taming the shrew

Science.gov (United States)

Barlow, A.

1990-01-01

The pace of progress in the design of integrated circuits continues to amaze observers inside and outside of the industry. Three decades ago, a 50 transistor chip was a technological wonder. Fifteen year later, a 5000 transistor device would 'wow' the crowds. Today, 50,000 transistor chips will earn a 'not too bad' assessment, but it takes 500,000 to really leave an impression. In 1975 a typical ASIC device had 1000 transistors, took one year to first samples (and two years to production) and sold for about 5 cents per transistor. Today's 50,000 transistor gate array takes about 4 months from spec to silicon, works the first time, and sells for about 0.02 cents per transistor. Fifteen years ago, the single most laborious and error prone step in IC design was the physical layout. Today, most IC's never see the hand of a layout designer: and automatic place and route tool converts the engineer's computer captured schematic to a complete physical design using a gate array or a library of standard cells also created by software rather than by designers. CAD has also been a generous benefactor to the digital design process. The architect of today's digital systems creates the design using an RTL or other high level simulator. Then the designer pushes a button to invoke the logic synthesizer-optimizer tool. A fault analyzer checks the result for testability and suggests where scan based cells will improve test coverage. One obstinate holdout amidst this parade of progress is the automation of analog design and its reduction to semi-custom techniques. This paper investigates the application of CAD techniques to analog design.

Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09-micron High Electron Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC)

Science.gov (United States)

2016-03-01

ARL-TN-0743 ● MAR 2016 US Army Research Laboratory Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for...originator. ARL-TN-0743 ● MAR 2016 US Army Research Laboratory Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo...To) October 2015–January 2016 4. TITLE AND SUBTITLE Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09

Magnonic logic circuits

International Nuclear Information System (INIS)

Khitun, Alexander; Bao Mingqiang; Wang, Kang L

2010-01-01

We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

A new integrated microwave SQUID circuit design

International Nuclear Information System (INIS)

Erne, S.N.; Finnegan, T.F.

1980-01-01

In this paper we consider the design and operation of a planar thin-film rf-SQUID circuit which can be realized via microwave-integrated-circuit (MIC) techniques and which differs substantially from pervious microwave SQUID configurations involving either mechanical point-contact or cylindrical thin-film micro-bridge geometries. (orig.)

Design and implementation of sigma delta modulators (ΣΔm) for class D audio amplifiers using differential pairs

CERN Document Server

Pereira, Nuno

2015-01-01

This book focuses on the design of a 3rd Order CT-ΣΔM where the integrator stages of the filter are implemented with Bipolar-Junction Transistors (BJT) differential pairs. These circuits are fully analyzed and the design method is carefully explained. The design method is validated through experimental measurements of several prototype circuits.

Design considerations for CdTe Nanotetrapods as electronic devices. krogstrup@fys.ku.dk.

Science.gov (United States)

Teich-McGoldrick, S L; Bellanger, M; Caussanel, M; Tsetseris, L; Pantelides, S T; Glotzer, S C; Schrimpf, R D

2009-11-01

We investigate the feasibility of using CdTe nanotetrapods as circuit elements using models and simulation at multiple scales. Technology computer-aided design tools are used to simulate the electrical behavior for both metal-semiconductor field-effect transistors and junction field-effect transistors. Our results show that by varying the doping concentrations and material composition, CdTe nanotetrapods have the potential to be useful circuit elements. Monte Carlo simulations provide insight into how control over interparticle and particle-substrate interactions can lead to the directed assembly of ordered arrays of electrically gated nanotetrapods.

Low-threshold amplitude discriminator circuit with tunnel diode and two transistors in differential connection

International Nuclear Information System (INIS)

Ryba, J.; Volny, J.

1973-01-01

The connection is designed of a low-threshold amplitude discriminator and a tunnel diode with two transistors in differential connection. The discriminator is by its simple connection, its low consumption and high temperature stability suitable especially for portable radiation detectors. The tunnel diode is connected by one pole to a collector clamp and by the other to the supply voltage. A suitable resistor is connected in parallel with the tunnel diode to meet demands for higher sensitivity. (Z.S.)

Organic electrochemical transistors

Science.gov (United States)

Rivnay, Jonathan; Inal, Sahika; Salleo, Alberto; Owens, Róisín M.; Berggren, Magnus; Malliaras, George G.

2018-02-01

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Organic electrochemical transistors

KAUST Repository

Rivnay, Jonathan

2018-01-16

Organic electrochemical transistors (OECTs) make effective use of ion injection from an electrolyte to modulate the bulk conductivity of an organic semiconductor channel. The coupling between ionic and electronic charges within the entire volume of the channel endows OECTs with high transconductance compared with that of field-effect transistors, but also limits their response time. The synthetic tunability, facile deposition and biocompatibility of organic materials make OECTs particularly suitable for applications in biological interfacing, printed logic circuitry and neuromorphic devices. In this Review, we discuss the physics and the mechanism of operation of OECTs, focusing on their identifying characteristics. We highlight organic materials that are currently being used in OECTs and survey the history of OECT technology. In addition, form factors, fabrication technologies and applications such as bioelectronics, circuits and memory devices are examined. Finally, we take a critical look at the future of OECT research and development.

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

Science.gov (United States)

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-10-08

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

Science.gov (United States)

Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

2014-01-01

Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT ~ 0.9 GHz, fMAX ~ 1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics. PMID:25295573

22nd Workshop on Advances in Analog Circuit Design

CERN Document Server

Makinwa, Kofi; Harpe, Pieter

2014-01-01

This book is based on the 18 tutorials presented during the 22nd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including frequency reference, power management for systems-on-chip, and smart wireless interfaces.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of frequency reference, power management for systems-on-chip, and smart wireless interfaces.

Vertically integrated circuit development at Fermilab for detectors

International Nuclear Information System (INIS)

Yarema, R; Deptuch, G; Hoff, J; Khalid, F; Lipton, R; Shenai, A; Trimpl, M; Zimmerman, T

2013-01-01

Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

Science.gov (United States)

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

PUZZLE - A program for computer-aided design of printed circuit artwork

Science.gov (United States)

Harrell, D. A. W.; Zane, R.

1971-01-01

Program assists in solving spacing problems encountered in printed circuit /PC/ design. It is intended to have maximum use for two-sided PC boards carrying integrated circuits, and also aids design of discrete component circuits.

Low-frequency noise behavior of polysilicon emitter bipolar junction transistors: a review

Science.gov (United States)

Deen, M. Jamal; Pascal, Fabien

2003-05-01

For many analog integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. In this paper, we begin by motivating the reader with reasons why bipolar transistors are still of great interest for analog integrated circuits. This motivation includes a comparison between BJT and the MOSFET using a simple small-signal equivalent circuit to derive important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. The effects of different processing technologies and conditions on the noise performance of PE-BJTs is reviewed and a summary of some of the key technological steps and device parameters and their effects on noise is discussed. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low frequency noise in ultra-small geometries is a serious issue since the rate of increase of the noise dispersion is faster than the noise itself as the emitter geometry is scaled to smaller values. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe heteorjunction bipolar transistors and MOSFETs, are presented after the conclusions.

Design for ASIC reliability for low-temperature applications

Science.gov (United States)

Chen, Yuan; Mojaradi, Mohammad; Westergard, Lynett; Billman, Curtis; Cozy, Scott; Burke, Gary; Kolawa, Elizabeth

2005-01-01

In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.

A Cytomorphic Chip for Quantitative Modeling of Fundamental Bio-Molecular Circuits.

Science.gov (United States)

2015-08-01

We describe a 0.35 μm BiCMOS silicon chip that quantitatively models fundamental molecular circuits via efficient log-domain cytomorphic transistor equivalents. These circuits include those for biochemical binding with automatic representation of non-modular and loading behavior, e.g., in cascade and fan-out topologies; for representing variable Hill-coefficient operation and cooperative binding; for representing inducer, transcription-factor, and DNA binding; for probabilistic gene transcription with analogic representations of log-linear and saturating operation; for gain, degradation, and dynamics of mRNA and protein variables in transcription and translation; and, for faithfully representing biological noise via tunable stochastic transistor circuits. The use of on-chip DACs and ADCs enables multiple chips to interact via incoming and outgoing molecular digital data packets and thus create scalable biochemical reaction networks. The use of off-chip digital processors and on-chip digital memory enables programmable connectivity and parameter storage. We show that published static and dynamic MATLAB models of synthetic biological circuits including repressilators, feed-forward loops, and feedback oscillators are in excellent quantitative agreement with those from transistor circuits on the chip. Computationally intensive stochastic Gillespie simulations of molecular production are also rapidly reproduced by the chip and can be reliably tuned over the range of signal-to-noise ratios observed in biological cells.

Silicon integrated circuits part A : supplement 2

CERN Document Server

Kahng, Dawon

1981-01-01

Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

Digital logic circuit design with ALTERA MAX+PLUS II

International Nuclear Information System (INIS)

Lee, Seung Ho; Park, Yong Su; Park, Gun Jong; Lee, Ju Heon

2006-09-01

This book is composed of five parts. The first part has introduction of ALTERA MAX+PLUS II and graphic editor, text editor, compiler, waveform editor simulator and timing analyzer of it. The second part is about direction of digital logic circuit design with training kit. The third part has grammar and practice of VHDL in ALTERA MAX+PLUS II including example and history of VHDL. The fourth part shows the design example of digital logic circuit by VHDL of ALTERA MAX+PLUS II which lists designs of adder and subtractor, code converter, counter, state machine and LCD module. The last part explains design example of digital logic circuit by graphic editor in ALTERA MAX+PLUS II.

Artificial immune system algorithm in VLSI circuit configuration

Science.gov (United States)

Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

2017-08-01

In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

On theory of single-molecule transistor

International Nuclear Information System (INIS)

Tran Tien Phuc

2009-01-01

The results of the study on single-molecule transistor are mainly investigated in this paper. The structure of constructed single-molecule transistor is similar to a conventional MOSFET. The conductive channel of the transistors is a single-molecule of halogenated benzene derivatives. The chemical simulation software CAChe was used to design and implement for the essential parameter of the molecules utilized as the conductive channel. The GUI of Matlab has been built to design its graphical interface, calculate and plot the output I-V characteristic curves for the transistor. The influence of temperature, length and width of the conductive channel, and gate voltage is considered. As a result, the simulated curves are similar to the traditional MOSFET's. The operating temperature range of the transistors is wider compared with silicon semiconductors. The supply voltage for transistors is only about 1 V. The size of transistors in this research is several nanometers.

Integrated circuit structure

International Nuclear Information System (INIS)

1981-01-01

The invention describes the fabrication of integrated circuit structures, such as read-only memory components of field-effect transistors, which may be fabricated and then maintained in inventory, and later selectively modified in accordance with a desired pattern. It is claimed that MOS depletion-mode devices in accordance with the invention can be fabricated at lower cost and at higher yields. (U.K.)

Design of delay insensitive circuits using multi-ring structures

DEFF Research Database (Denmark)

Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

1992-01-01

The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...

A design method of oscillatory De-Qing circuit

International Nuclear Information System (INIS)

Feng Wenquan

1988-01-01

With some particular advantages the oscillatory De-Qing circuit now is widely used. However its design is very complex. By means of a quantitative analysis for this circuit a group of design formulas is obtained. According to these design formulas the maximum allowable charging inductance L c , the De-Qing network resistance R and capacitance C can easily be determined, if the PFN capacitance C N , the maximum pulse frequency F max , and percentage regulation η are given. Simple and direct formulas for specific situation are listed. Finally, a design example is given and a comparison with experimental result is made, which shows that the design method is feasible and reliable

A real time status monitor for transistor bank driver power limit resistor in boost injection kicker power supply

Energy Technology Data Exchange (ETDEWEB)

Mi, J.; Tan, Y.; Zhang, W.

2011-03-28

For years suffering of Booster Injection Kicker transistor bank driver regulator troubleshooting, a new real time monitor system has been developed. A simple and floating circuit has been designed and tested. This circuit monitor system can monitor the driver regulator power limit resistor status in real time and warn machine operator if the power limit resistor changes values. This paper will mainly introduce the power supply and the new designed monitoring system. This real time resistor monitor circuit shows a useful method to monitor some critical parts in the booster pulse power supply. After two years accelerator operation, it shows that this monitor works well. Previously, we spent a lot of time in booster machine trouble shooting. We will reinstall all 4 PCB into Euro Card Standard Chassis when the power supply system will be updated.

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

Science.gov (United States)

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Design and Performance Analysis of Depletion-Mode InSb Quantum-Well Field-Effect Transistor for Logic Applications

Science.gov (United States)

Islam, R.; Uddin, M. M.; Hossain, M. Mofazzal; Matin, M. A.

The design of a 1μm gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42m2V-1s-1 at Vg=0V, a small pinch off gate voltage (Vp) of -0.25V, a maximum extrinsic transconductance (gm) of ˜4.85mS/μm and a drain current density of more than 3.34mA/μm. A short-circuit current-gain cut-off frequency (fT) of 374GHz and a maximum oscillation frequency (fmax) of 645GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.

Transistor precision pulse-shaper with short recovery time; Dispositif de haute precision pour la mise en forme des impulsions, a transistors et a faible temps de recuperation; Tranzistornyj tochnyj formirovatel' impul'sov s korotkim vremenem vosstanovleniya; Formador de impulsos de precision, transistorizado, de corto tiempo de recuperacion

Energy Technology Data Exchange (ETDEWEB)

Lotto, I De [European Atomic Energy Community, CCR, Ispra (Italy)

1962-04-15

A pulse-shaper with a short recovery time is very often necessary in nuclear electronics. The pulse-shaper which has the lowest recovery time is the one-shot multivibrator with RC timing-network. This type of timing network and the influence of transistor characteristics on the performance of this circuit are analysed. Some circuit modifications are suggested for obtaining (1) a pulse-width precision better than 2% without the need for individual adjustments and (2) a pulse-width stability better than 1% over a 20{sup o}C temperature range. The circuit is so designed that use is allowed of transistors with a low base-emitter inverse-voltage like that of most of the fastest types. (author) [French] Un dispositif de mise en forme des impulsions, a faible temps de recuperation, est frequemment indispensable en electronique nucleaire. Le dispositif ayant le temps de recuperation le plus faible est le multivibrateur a un seul coup muni d'un systeme de synchronisation RC. L'auteur analyse ce systeme de synchronisation et les effets des caracteristiques des transistors sur le rendement du circuit. Il propose d'apporter au circuit certaines modifications en vue d'obtenir: 1{sup o} une largeur d'impulsion d'une precision superieure a 2% sans qu'il soit necessaire de proceder a divers ajustements, et 2{sup o} une largeur d'impulsion d'une stabilite superieure a 1% sur une gamme de temperature de 20{sup o}C. Le circuit est concu de telle maniere qu'il permet d'utiliser, comme pour les circuits ultra-rapides, des transistors a tension inverse base-emetteur faible. (author) [Spanish] En electronica nuclear es a menudo necesario un formador de impulsos de corto periodo de recuperacion. El formador de impulsos de periodo de recuperacion mas breve es el univibrador con periodo determinado por una RC. Se estudia este circuito y la influencia de las caracteristicas de los transistores en su funcionamiento. Se sugieren algunas modificaciones para obtener 1) una precision en la

Power management techniques for integrated circuit design

CERN Document Server

Chen, Ke-Horng

2016-01-01

This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

An AMOLED AC-Biased Pixel Design Compensating the Threshold Voltage and I-R Drop

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2011-01-01

Full Text Available We propose a novel pixel design and an AC bias driving method for active-matrix organic light-emitting diode (AM-OLED displays using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs. The proposed threshold voltage and I-R drop compensation circuit, which comprised three transistors and one capacitor, have been verified to supply uniform output current by simulation work using the Automatic Integrated Circuit Modeling Simulation Program with Integrated Circuit Emphasis (AIM-SPICE simulator. The simulated results demonstrate excellent properties such as low error rate of OLED anode voltage variation (<0.7% and low voltage drop of VDD power line. The proposed pixel circuit effectively enables threshold-voltage-deviation correction of driving TFT and compensates for the voltage drop of VDD power line using AC bias on OLED cathode.

Electrical circuit for checking the state of charge of a vehicle battery. Elektrische Schaltung zur Kontrolle des Ladezustandes einer Batterie in Kraftfahrzeugen

Energy Technology Data Exchange (ETDEWEB)

Gamulescu, A

1981-05-27

The invention concerns an electrical circuit for checking the state of charge of a vehicle battery. The circuit consists of a transistor, whose collector is connected via a series resistance and a Zener diode to the positive pole of the battery. The breakdown voltage of the Zener diode is about 12 volts. The emitter of the transistor is connected via an LED to earth. A second LED is connected in parallel with the collector-emitter circuit of the transistor, which works via a voltage divider. This voltage divider reduces the voltage at the LED with the transistor which is conducting to about 0.7 volts. A second Zener diode connected via a series resistance to the positive pole is also provided. Its breakdown voltage is 15 volts.

Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

Directory of Open Access Journals (Sweden)

Ruiping Cao

2014-01-01

Full Text Available In high-speed applications, MOS current mode logic (MCML is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP. However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

Compact physical model of a-IGZO TFTs for circuit simulation

NARCIS (Netherlands)

Ghittorelli, M.; Torricelli, F.; Garripoli, C.; Van Der Steen, J.L.J.P.; Gelinck, G.H.; Abdinia, S.; Cantatore, E.; Kovacs-Vajna, Z.M.

2017-01-01

Amorphous InGaZnO (a-IGZO) is a candidate material for thin-film transistors (TFTs) owing to its large electron mobility. The development of high functionality circuits requires accurate and efficient circuit simulation that, in turn, is based on compact physical a-IGZO TFTs models. Here we propose

Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

Directory of Open Access Journals (Sweden)

Zheng Xie

2013-01-01

Full Text Available The intrinsic variability of nanoscale VLSI technology must be taken into account when analyzing circuit designs to predict likely yield. Monte-Carlo- (MC- and quasi-MC- (QMC- based statistical techniques do this by analysing many randomised or quasirandomised copies of circuits. The randomisation must model forms of variability that occur in nano-CMOS technology, including “atomistic” effects without intradie correlation and effects with intradie correlation between neighbouring devices. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The use of principal components analysis, behavioural modeling, and an implementation of “Statistical Blockade” (SB is shown to be capable of achieving significant reduction in the computational costs. A computation time reduction of 98.7% was achieved for a commonly used asynchronous circuit element. Replacing MC by QMC analysis can achieve further computation reduction, and this is illustrated for more complex circuits, with the results being compared with those of transistor-level simulations. The “yield prediction” analysis of SRAM arrays is taken as a case study, where the arrays contain up to 1536 transistors modelled using parameters appropriate to 35 nm technology. It is reported that savings of up to 99.85% in computation time were obtained.

Analysis of transistor and snubber turn-off dynamics in high-frequency high-voltage high-power converters

Science.gov (United States)

Wilson, P. M.; Wilson, T. G.; Owen, H. A., Jr.

Dc to dc converters which operate reliably and efficiently at switching frequencies high enough to effect substantial reductions in the size and weight of converter energy storage elements are studied. A two winding current or voltage stepup (buck boost) dc-to-dc converter power stage submodule designed to operate in the 2.5-kW range, with an input voltage range of 110 to 180 V dc, and an output voltage of 250 V dc is emphasized. In order to assess the limitations of present day component and circuit technologies, a design goal switching frequency of 10 kHz was maintained. The converter design requirements represent a unique combination of high frequency, high voltage, and high power operation. The turn off dynamics of the primary circuit power switching transistor and its associated turn off snubber circuitry are investigated.

Design of a 1-chip IBM-3270 protocol handler

NARCIS (Netherlands)

Spaanenburg, L.

1989-01-01

The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4

Digital integrated circuit design using Verilog and SystemVerilog

CERN Document Server

Mehler, Ronald W

2014-01-01

For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

Magnon transistor for all-magnon data processing.

Science.gov (United States)

Chumak, Andrii V; Serga, Alexander A; Hillebrands, Burkard

2014-08-21

An attractive direction in next-generation information processing is the development of systems employing particles or quasiparticles other than electrons--ideally with low dissipation--as information carriers. One such candidate is the magnon: the quasiparticle associated with the eigen-excitations of magnetic materials known as spin waves. The realization of single-chip all-magnon information systems demands the development of circuits in which magnon currents can be manipulated by magnons themselves. Using a magnonic crystal--an artificial magnetic material--to enhance nonlinear magnon-magnon interactions, we have succeeded in the realization of magnon-by-magnon control, and the development of a magnon transistor. We present a proof of concept three-terminal device fabricated from an electrically insulating magnetic material. We demonstrate that the density of magnons flowing from the transistor's source to its drain can be decreased three orders of magnitude by the injection of magnons into the transistor's gate.

Nucleic acids for the rational design of reaction circuits.

Science.gov (United States)

Padirac, Adrien; Fujii, Teruo; Rondelez, Yannick

2013-08-01

Nucleic acid-based circuits are rationally designed in vitro assemblies that can perform complex preencoded programs. They can be used to mimic in silico computations. Recent works emphasized the modularity and robustness of these circuits, which allow their scaling-up. Another new development has led to dynamic, time-responsive systems that can display emergent behaviors like oscillations. These are closely related to biological architectures and provide an in vitro model of in vivo information processing. Nucleic acid circuits have already been used to handle various processes for technological or biotechnological purposes. Future applications of these chemical smart systems will benefit from the rapidly growing ability to design, construct, and model nucleic acid circuits of increasing size. Copyright © 2012 Elsevier Ltd. All rights reserved.

Recent advances in understanding total-dose effects in bipolar transistors

International Nuclear Information System (INIS)

Schrimpf, R.D.

1996-01-01

Gain degradation in irradiated bipolar transistors can be a significant problem, particularly in linear integrated circuits. In many bipolar technologies, the degradation is greater for irradiation at low dose rates than it is for typical laboratory dose rates. Ionizing radiation causes the base current in bipolar transistors to increase, due to the presence of net positive charge in the oxides covering sensitive device areas and increases in surface recombination velocity. Understanding the mechanisms responsible for radiation-induced gain degradation in bipolar transistors is important in developing appropriate hardness assurance methods. This paper reviews recent modeling and experimental work, with the emphasis on low-dose-rate effects. A promising hardness assurance method based on irradiation at elevated temperatures is described

Radio frequency and linearity performance of transistors using high-purity semiconducting carbon nanotubes.

Science.gov (United States)

Wang, Chuan; Badmaev, Alexander; Jooyaie, Alborz; Bao, Mingqiang; Wang, Kang L; Galatsis, Kosmas; Zhou, Chongwu

2011-05-24

This paper reports the radio frequency (RF) and linearity performance of transistors using high-purity semiconducting carbon nanotubes. High-density, uniform semiconducting nanotube networks are deposited at wafer scale using our APTES-assisted nanotube deposition technique, and RF transistors with channel lengths down to 500 nm are fabricated. We report on transistors exhibiting a cutoff frequency (f(t)) of 5 GHz and with maximum oscillation frequency (f(max)) of 1.5 GHz. Besides the cutoff frequency, the other important figure of merit for the RF transistors is the device linearity. For the first time, we report carbon nanotube RF transistor linearity metrics up to 1 GHz. Without the use of active probes to provide the high impedance termination, the measurement bandwidth is therefore not limited, and the linearity measurements can be conducted at the frequencies where the transistors are intended to be operating. We conclude that semiconducting nanotube-based transistors are potentially promising building blocks for highly linear RF electronics and circuit applications.

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

Science.gov (United States)

Dell'Erba, Giorgio; Luzio, Alessandro; Natali, Dario; Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu; Noh, Yong-Young; Caironi, Mario

2014-04-01

Ambipolar semiconducting polymers, characterized by both high electron (μe) and hole (μh) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μh = 0.29 cm2/V s and μe = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μe = 0.12 cm2/V s and μh = 8 × 10-4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Growth of a single-wall carbon nanotube film and its patterning as an n-type field effect transistor device using an integrated circuit compatible process

Energy Technology Data Exchange (ETDEWEB)

Shiau, S H; Gau, C [Institute of Aeronautics and Astronautics, and Center for Micro/Nano Science and Technology, National Cheng Kung University, Tainan, Taiwan (China); Liu, C W; Dai, B T [National Nano Device Laboratories, No. 27, Nanke 3rd Road, Science-based Industrial Park, Hsin-shi, Tainan, Taiwan (China)], E-mail: gauc@mail.ncku.edu.tw

2008-03-12

This study presents the synthesis of a dense single-wall carbon nanotube (SWNT) network on a silicon substrate using alcohol as the source gas. The nanosize catalysts required are made by the reduction of metal compounds in ethanol. The key point in spreading the nanoparticles on the substrate, so that the SWNT network can be grown over the entire wafer, is making the substrate surface hydrophilic. This SWNT network is so dense that it can be treated like a thin film. Methods of patterning this SWNT film with integrated circuit compatible processes are presented and discussed for the first time in the literature. Finally, fabrication and characteristic measurements of a field effect transistor (FET) using this SWNT film are also demonstrated. This FET is shown to have better electronic properties than any other kind of thin film transistor. This thin film with good electronic properties can be readily applied in the processing of many other SWNT electronic devices.

Custom high-reliability radiation-hard CMOS-LSI circuit design

International Nuclear Information System (INIS)

Barnard, W.J.

1981-01-01

Sandia has developed a custom CMOS-LSI design capability to provide high reliability radiation-hardened circuits. This capability relies on (1) proven design practices to enhance reliability, (2) use of well characterized cells and logic modules, (3) computer-aided design tools to reduce design time and errors and to standardize design definition, and (4) close working relationships with the system designer and technology fabrication personnel. Trade-offs are made during the design between circuit complexity/performance and technology/producibility for high reliability and radiation-hardened designs to result. Sandia has developed and is maintaining a radiation-hardened bulk CMOS technology fabrication line for production of prototype and small production volume parts

An optimum design of R-C oscillatory De-Qing circuit

International Nuclear Information System (INIS)

Cao Dezhang; Pan Linghe; Yang Tianlu

1990-01-01

An optimum design of R-C oscillatory De-Qing circuit has been developed for voltage regulation of the pulse modulator. When a new coefficient T 3 /T is introduced, the selection of De-Qing circuit parameters will become quite simple and the optimum parameters can be calculated directly. The De-Qing circuit parameters calculated will be effective in the whole range of the percentage regulation η from zero to maximum design value. The limit value of η is 0.36 or 0.29, theoretically, when the time constant of the De-Qing circuit is 3RC or 5RC respectively

Integrated circuit devices in control systems of coal mining complexes

Energy Technology Data Exchange (ETDEWEB)

1983-01-01

Systems of automatic monitoring and control of coal mining complexes developed in the 1960's used electromagnetic relays, thyristors, and flip-flops on transistors of varying conductivity. The circuits' designers, devoted much attention to ensuring spark safety, lowering power consumption, and raising noise immunity and repairability of functional devices. The fast development of integrated circuitry led to the use of microelectronic components in most devices of mine automation. An analysis of specifications and experimental research into integrated circuits (IMS) shows that the series K 176 IMS components made by CMOS technology best meet mine conditions of operation. The use of IMS devices under mine conditions has demonstrated their high reliability. Further development of integrated circuitry involve using microprocessors and microcomputers. (SC)

Design structure for in-system redundant array repair in integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Control circuits in power electronics practical issues in design and implementation

CERN Document Server

Castilla, Miguel

2016-01-01

Control circuits are a key element in the operation and performance of power electronics converters. This book describes practical issues related to the design and implementation of these control circuits, and is divided into three parts - analogue control circuits, digital control circuits, and new trends in control circuits.

Pulse Detecting Genetic Circuit – A New Design Approach

Science.gov (United States)

Inniss, Mara; Iba, Hitoshi; Way, Jeffrey C.

2016-01-01

A robust cellular counter could enable synthetic biologists to design complex circuits with diverse behaviors. The existing synthetic-biological counters, responsive to the beginning of the pulse, are sensitive to the pulse duration. Here we present a pulse detecting circuit that responds only at the falling edge of a pulse–analogous to negative edge triggered electric circuits. As biological events do not follow precise timing, use of such a pulse detector would enable the design of robust asynchronous counters which can count the completion of events. This transcription-based pulse detecting circuit depends on the interaction of two co-expressed lambdoid phage-derived proteins: the first is unstable and inhibits the regulatory activity of the second, stable protein. At the end of the pulse the unstable inhibitor protein disappears from the cell and the second protein triggers the recording of the event completion. Using stochastic simulation we showed that the proposed design can detect the completion of the pulse irrespective to the pulse duration. In our simulation we also showed that fusing the pulse detector with a phage lambda memory element we can construct a counter which can be extended to count larger numbers. The proposed design principle is a new control mechanism for synthetic biology which can be integrated in different circuits for identifying the completion of an event. PMID:27907045

Radio frequency integrated circuit design for cognitive radio systems

CERN Document Server

Fahim, Amr

2015-01-01

This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

Parts & Pools: A Framework for Modular Design of Synthetic Gene Circuits

Energy Technology Data Exchange (ETDEWEB)

Marchisio, Mario Andrea, E-mail: marchisio@hit.edu.cn [School of Life Science and Technology, Harbin Institute of Technology, Harbin (China)

2014-10-06

Published in 2008, Parts & Pools represents one of the first attempts to conceptualize the modular design of bacterial synthetic gene circuits with Standard Biological Parts (DNA segments) and Pools of molecules referred to as common signal carriers (e.g., RNA polymerases and ribosomes). The original framework for modeling bacterial components and designing prokaryotic circuits evolved over the last years and brought, first, to the development of an algorithm for the automatic design of Boolean gene circuits. This is a remarkable achievement since gene digital circuits have a broad range of applications that goes from biosensors for health and environment care to computational devices. More recently, Parts & Pools was enabled to give a proper formal description of eukaryotic biological circuit components. This was possible by employing a rule-based modeling approach, a technique that permits a faithful calculation of all the species and reactions involved in complex systems such as eukaryotic cells and compartments. In this way, Parts & Pools is currently suitable for the visual and modular design of synthetic gene circuits in yeast and mammalian cells too.

Parts & Pools: A Framework for Modular Design of Synthetic Gene Circuits

International Nuclear Information System (INIS)

Marchisio, Mario Andrea

2014-01-01

Published in 2008, Parts & Pools represents one of the first attempts to conceptualize the modular design of bacterial synthetic gene circuits with Standard Biological Parts (DNA segments) and Pools of molecules referred to as common signal carriers (e.g., RNA polymerases and ribosomes). The original framework for modeling bacterial components and designing prokaryotic circuits evolved over the last years and brought, first, to the development of an algorithm for the automatic design of Boolean gene circuits. This is a remarkable achievement since gene digital circuits have a broad range of applications that goes from biosensors for health and environment care to computational devices. More recently, Parts & Pools was enabled to give a proper formal description of eukaryotic biological circuit components. This was possible by employing a rule-based modeling approach, a technique that permits a faithful calculation of all the species and reactions involved in complex systems such as eukaryotic cells and compartments. In this way, Parts & Pools is currently suitable for the visual and modular design of synthetic gene circuits in yeast and mammalian cells too.

Outlook and emerging semiconducting materials for ambipolar transistors.

Science.gov (United States)

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ignition circuit for combustion engines

Energy Technology Data Exchange (ETDEWEB)

Becker, H W

1977-05-26

The invention refers to the ignition circuit for combustion engines, which are battery fed. The circuit contains a transistor and an oscillator to produce an output voltage on the secondary winding of an output transformer to supply an ignition current. The plant is controlled by an interrupter. The purpose of the invention is to form such a circuit that improved sparks for ignition are produced, on the one hand, and that on the other hand, the plant can continue to function after loss of the oscillator. The problem is solved by the battery and the secondary winding of the output transformers of the oscillator are connected via a rectifier circuit to produce a resultant total voltage with the ignition coil from the battery voltage and the rectified pulsating oscillator output.

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

Thin Film Transistor Control Circuitry for MEMS Acoustic Transducers

Science.gov (United States)

Daugherty, Robin

This work seeks to develop a practical solution for short range ultrasonic communications and produce an integrated array of acoustic transmitters on a flexible substrate. This is done using flexible thin film transistor (TFT) and micro electromechanical systems (MEMS). The goal is to develop a flexible system capable of communicating in the ultrasonic frequency range at a distance of 10-100 meters. This requires a great deal of innovation on the part of the FDC team developing the TFT driving circuitry and the MEMS team adapting the technology for fabrication on a flexible substrate. The technologies required for this research are independently developed. The TFT development is driven primarily by research into flexible displays. The MEMS development is driving by research in biosensors and micro actuators. This project involves the integration of TFT flexible circuit capabilities with MEMS micro actuators in the novel area of flexible acoustic transmitter arrays. This thesis focuses on the design, testing and analysis of the circuit components required for this project.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

Science.gov (United States)

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Science.gov (United States)

Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris

2000-01-01

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

Science.gov (United States)

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

Energy Technology Data Exchange (ETDEWEB)

Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

2000-08-10

In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

Science.gov (United States)

2013-05-01

The largest company in the world is now a technology company (Apple Inc.) whose products are all enabled by transistors [2]. Any changes, for better...increasing standby battery life. The nVidia Tegra 3 mobile processor for applications in smartphones and tablets contains five cores: one low power...white paper, NVIDIA , 2011. 14. W. G. Vandenberghe, B. Sorée, W. Magnus, G. Groeseneken, and M. V. Fischetti, “Impact of field-induced quantum

Driver Circuit For High-Power MOSFET's

Science.gov (United States)

Letzer, Kevin A.

1991-01-01

Driver circuit generates rapid-voltage-transition pulses needed to switch high-power metal oxide/semiconductor field-effect transistor (MOSFET) modules rapidly between full "on" and full "off". Rapid switching reduces time of overlap between appreciable current through and appreciable voltage across such modules, thereby increasing power efficiency.

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

Science.gov (United States)

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

Science.gov (United States)

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

International Nuclear Information System (INIS)

Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

1992-01-01

Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

Transistor electronics use of semiconductor components in switching operations

CERN Document Server

Rumpf, Karl-Heinz

2014-01-01

Transistor Electronics: Use of Semiconductor Components in Switching Operations presents the semiconductor components as well as their elementary circuits. This book discusses the scope of application of electronic devices to increase productivity. Organized into eight chapters, this book begins with an overview of the general equation for the representation of integer positive numbers. This text then examines the properties and characteristics of basic electronic components, which relates to an understanding of the operation of semiconductors. Other chapters consider the electronic circuit ar

Estimation of leakage power and delay in CMOS circuits using parametric variation

Directory of Open Access Journals (Sweden)

Preeti Verma

2016-09-01

Full Text Available With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz at 400 mHz.

Simulated annealing method for electronic circuits design: adaptation and comparison with other optimization methods

International Nuclear Information System (INIS)

Berthiau, G.

1995-10-01

The circuit design problem consists in determining acceptable parameter values (resistors, capacitors, transistors geometries ...) which allow the circuit to meet various user given operational criteria (DC consumption, AC bandwidth, transient times ...). This task is equivalent to a multidimensional and/or multi objective optimization problem: n-variables functions have to be minimized in an hyper-rectangular domain ; equality constraints can be eventually specified. A similar problem consists in fitting component models. In this way, the optimization variables are the model parameters and one aims at minimizing a cost function built on the error between the model response and the data measured on the component. The chosen optimization method for this kind of problem is the simulated annealing method. This method, provided by the combinatorial optimization domain, has been adapted and compared with other global optimization methods for the continuous variables problems. An efficient strategy of variables discretization and a set of complementary stopping criteria have been proposed. The different parameters of the method have been adjusted with analytical functions of which minima are known, classically used in the literature. Our simulated annealing algorithm has been coupled with an open electrical simulator SPICE-PAC of which the modular structure allows the chaining of simulations required by the circuit optimization process. We proposed, for high-dimensional problems, a partitioning technique which ensures proportionality between CPU-time and variables number. To compare our method with others, we have adapted three other methods coming from combinatorial optimization domain - the threshold method, a genetic algorithm and the Tabu search method - The tests have been performed on the same set of test functions and the results allow a first comparison between these methods applied to continuous optimization variables. Finally, our simulated annealing program

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Analog Circuit Design Optimization Based on Evolutionary Algorithms

Directory of Open Access Journals (Sweden)

Mansour Barari

2014-01-01

Full Text Available This paper investigates an evolutionary-based designing system for automated sizing of analog integrated circuits (ICs. Two evolutionary algorithms, genetic algorithm and PSO (Parswal particle swarm optimization algorithm, are proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through specific electrical simulation, to the optimization system in the MATLAB environment, for the selected topology. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met. Comparisons with available methods like genetic algorithms show that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.

Monolithic acoustic graphene transistors based on lithium niobate thin film

Science.gov (United States)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. [Statutory Provisions] Trailing cables for medium-voltage circuits shall include grounding...

Flexible low-voltage organic transistors with high thermal stability at 250 °C.

Science.gov (United States)

Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Zschieschang, Ute; Klauk, Hagen; Takimiya, Kazuo; Sadamitsu, Yuji; Hamada, Masahiro; Sekitani, Tsuyoshi; Someya, Takao

2013-07-19

Low-operating-voltage flexible organic thin-film transistors with high thermal stability using DPh-DNTT and SAM gate dielectrics are reported. The mobility of the transistors are decreased by 23% after heating to 250 °C for 30 min. Furthermore, flexible organic pseudo-CMOS inverter circuits, which are functional after heating to 200 °C, are demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Low Noise Electronic Circuit

NARCIS (Netherlands)

Annema, Anne J.; Leenaerts, Dominicus M.W.; de Vreede, Petrus W.H.

2002-01-01

An electronic circuit, which can be used as a Low Noise Amplifier (LNA), comprises two complementary Field Effect Transistors (M1, M2; M5, M6), each having a gate, a source and a drain. The gates are connected together as a common input terminal, and the drains are connected together as a

Circuit Design of Surface Acoustic Wave Based Micro Force Sensor

Directory of Open Access Journals (Sweden)

Yuanyuan Li

2014-01-01

Full Text Available Pressure sensors are commonly used in industrial production and mechanical system. However, resistance strain, piezoresistive sensor, and ceramic capacitive pressure sensors possess limitations, especially in micro force measurement. A surface acoustic wave (SAW based micro force sensor is designed in this paper, which is based on the theories of wavelet transform, SAW detection, and pierce oscillator circuits. Using lithium niobate as the basal material, a mathematical model is established to analyze the frequency, and a peripheral circuit is designed to measure the micro force. The SAW based micro force sensor is tested to show the reasonable design of detection circuit and the stability of frequency and amplitude.

Electronic circuit design with HEP computational tools

International Nuclear Information System (INIS)

Vaz, Mario

1996-01-01

CPSPICE is an electronic circuit statistical simulation program developed to run in a parallel environment under UNIX operating system and TCP/IP communications protocol, using CPS - Cooperative Processes Software , SPICE program and CERNLIB software package. It is part of a set of tools being develop, intended to help electronic engineers to design, model and simulate complex systems and circuits for High Energy Physics detectors, based on statistical methods, using the same software and methodology used by HEP physicists for data analysis. CPSPICE simulates electronic circuits by Monte Carlo method, through several different processes running simultaneously SPICE in UNIX parallel computers or workstation farms. Data transfer between CPS processes for a modified version of SPICE2G6 is done by RAM memory, but can also be done through hard disk files if no source files are available for the simulator, and for bigger simulation outputs files. Simulation results are written in a HBOOK file as a NTUPLE, to be examined by HBOOK in batch model or graphics, and analyzed by statistical procedures available. The HBOOK file be stored on hard disk for small amount of data, or into Exabyte tape file for large amount of data. HEP tools also helps circuit or component modeling, like MINUT program from CERNLIB, that implements Nelder and Mead Simplex and Gradient with or without derivatives algorithms, and can be used for design optimization.This paper presents CPSPICE program implementation. The scheme adopted is suitable to make parallel other electronic circuit simulators. (author)

Characterization of a Common-Source Amplifier Using Ferroelectric Transistors

Science.gov (United States)

Hunt, Mitchell; Sayyah, Rana; MacLeond, Todd C.; Ho, Pat D.

2010-01-01

This paper presents empirical data that was collected through experiments using a FeFET in the established common-source amplifier circuit. The unique behavior of the FeFET lends itself to interesting and useful operation in this widely used common-source amplifier. The paper examines the effect of using a ferroelectric transistor for the amplifier. It also examines the effects of varying load resistance, biasing, and input voltages on the output signal and gives several examples of the output of the amplifier for a given input. The difference between a commonsource amplifier using a ferroelectric transistor and that using a MOSFET is addressed.

Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

Energy Technology Data Exchange (ETDEWEB)

Dell' Erba, Giorgio; Natali, Dario [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano (Italy); Luzio, Alessandro; Caironi, Mario, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu [Heeger Center for Advanced Materials, School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), 261 Cheomdan-gwagiro, Buk-gu, Gwangju 500-712 (Korea, Republic of); Noh, Yong-Young, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Department of Energy and Materials Engineering, Dongguk University, 26 Pil-dong, 3-ga, Jung-gu, Seoul 100-715 (Korea, Republic of)

2014-04-14

Ambipolar semiconducting polymers, characterized by both high electron (μ{sub e}) and hole (μ{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μ{sub h} = 0.29 cm{sup 2}/V s and μ{sub e} = 0.001 cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μ{sub e} = 0.12 cm{sup 2}/V s and μ{sub h} = 8 × 10{sup −4} cm{sup 2}/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

Science.gov (United States)

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Evolvable designs of experiments applications for circuits

CERN Document Server

Iordache, Octavian

2009-01-01

Adopting a groundbreaking approach, the highly regarded author shows how to design methods for planning increasingly complex experiments. He begins with a brief introduction to standard quality methods and the technology in standard electric circuits. The book then gives numerous examples of how to apply the proposed methodology in a series of real-life case studies. Although these case studies are taken from the printed circuit board industry, the methods are equally applicable to other fields of engineering.

High-frequency analog integrated circuit design

CERN Document Server

1995-01-01

To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

Integrated all optical transmodulator circuits with non-linear gain elements and tunable optical fibers

NARCIS (Netherlands)

Kuindersma, P.I.; Leijtens, X.J.M.; Zantvoort, van J.H.C.; Waardt, de H.

2012-01-01

We characterize integrated InP circuits for high speed ‘all-optical’ signal processing. Single chip circuits act as optical transistors. Transmodulation is performed by non-linear gain sections. Integrated tunable filters give signal equalization in time domain.

Servo Platform Circuit Design of Pendulous Gyroscope Based on DSP

Science.gov (United States)

Tan, Lilong; Wang, Pengcheng; Zhong, Qiyuan; Zhang, Cui; Liu, Yunfei

2018-03-01

In order to solve the problem when a certain type of pendulous gyroscope in the initial installation deviation more than 40 degrees, that the servo platform can not be up to the speed of the gyroscope in the rough north seeking phase. This paper takes the digital signal processor TMS320F28027 as the core, uses incremental digital PID algorithm, carries out the circuit design of the servo platform. Firstly, the hardware circuit is divided into three parts: DSP minimum system, motor driving circuit and signal processing circuit, then the mathematical model of incremental digital PID algorithm is established, based on the model, writes the PID control program in CCS3.3, finally, the servo motor tracking control experiment is carried out, it shows that the design can significantly improve the tracking ability of the servo platform, and the design has good engineering practice.

Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors

Science.gov (United States)

Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.

A Novel Leakage-tolerant Domino Logic Circuit With Feedback From Footer Transistor In Ultra Deep Submicron CMOS

DEFF Research Database (Denmark)

Moradi, Farshad; Peiravi, Ali; Mahmoodi, Hamid

As the CMOS manufacturing process scales down into the ultra deep sub-micron regime, the leakage current becomes an increasingly more important consideration in VLSI circuit design. In this paper, a high speed and noise immune domino logic circuit is presented which uses the property of the footer...

High-frequency self-aligned graphene transistors with transferred gate stacks

Science.gov (United States)

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

[Design of blood-pressure parameter auto-acquisition circuit].

Science.gov (United States)

Chen, Y P; Zhang, D L; Bai, H W; Zhang, D A

2000-02-01

This paper presents the realization and design of a kind of blood-pressure parameter auto-acquisition circuit. The auto-acquisition of blood-pressure parameter controlled by 89C2051 single chip microcomputer is accomplished by collecting and processing the driving signal of LCD. The circuit that is successfully applied in the home unit of telemedicine system has the simple and reliable properties.

Design of An Energy Efficient Hydraulic Regenerative circuit

Science.gov (United States)

Ramesh, S.; Ashok, S. Denis; Nagaraj, Shanmukha; Adithyakumar, C. R.; Reddy, M. Lohith Kumar; Naulakha, Niranjan Kumar

2018-02-01

Increasing cost and power demand, leads to evaluation of new method to increase through productivity and help to solve the power demands. Many researchers have break through to increase the efficiency of a hydraulic power pack, one of the promising methods is the concept of regenerative. The objective of this research work is to increase the efficiency of a hydraulic circuit by introducing a concept of regenerative circuit. A Regenerative circuit is a system that is used to speed up the extension stroke of the double acting single rod hydraulic cylinder. The output is connected to the input in the directional control value. By this concept, increase in velocity of the piston and decrease the cycle time. For the research, a basic hydraulic circuit and a regenerative circuit are designated and compared both with their results. The analysis was based on their time taken for extension and retraction of the piston. From the detailed analysis of both the hydraulic circuits, it is found that the efficiency by introducing hydraulic regenerative circuit increased by is 5.3%. The obtained results conclude that, implementing hydraulic regenerative circuit in a hydraulic power pack decreases power consumption, reduces cycle time and increases productivity in a longer run.

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

Science.gov (United States)

Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

2008-07-24

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

A Wide-Range Tunable Level-Keeper Using Vertical Metal-Oxide-Semiconductor Field-Effect Transistors for Current-Reuse Systems

Science.gov (United States)

Tanoi, Satoru; Endoh, Tetsuo

2012-04-01

A wide-range tunable level-keeper using vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed for current-reuse analog systems. The design keys for widening tunable range of the operation are a two-path feed-back and a vertical MOSFET with back-bias-effect free. The proposed circuit with the vertical MOSFETs shows the 1.23-V tunable-range of the input level with the 2.4-V internal-supply voltage (VDD) in the simulation. This tunable-range of the proposed circuit is 4.7 times wider than that of the conventional. The achieved current efficiency of the proposed level-keeper is 66% at the 1.2-V output with the 2.4-V VDD. This efficiency of the proposed circuit is twice higher than that of the traditional voltage down converter.

Analog circuit design automation for performance

NARCIS (Netherlands)

Ning, Zhen-Qiu; Ning, Zhen-Qiu; Kole, Marq; Kole, M.E.; Mouthaan, A.J.; Wallinga, Hans

1992-01-01

This paper describes an improved version of the program SEAS (a Simulated Evolution approach for Analog circuit Synthesis), in which an approach for selection of alternatives based on the evaluation of mutation values is developed, and design automafion for high performance comparators is covered.

Electromagnetic Compatibility Design of the Computer Circuits

Science.gov (United States)

Zitai, Hong

2018-02-01

Computers and the Internet have gradually penetrated into every aspect of people’s daily work. But with the improvement of electronic equipment as well as electrical system, the electromagnetic environment becomes much more complex. Electromagnetic interference has become an important factor to hinder the normal operation of electronic equipment. In order to analyse the computer circuit compatible with the electromagnetic compatibility, this paper starts from the computer electromagnetic and the conception of electromagnetic compatibility. And then, through the analysis of the main circuit and system of computer electromagnetic compatibility problems, we can design the computer circuits in term of electromagnetic compatibility. Finally, the basic contents and methods of EMC test are expounded in order to ensure the electromagnetic compatibility of equipment.

High-performance indium gallium phosphide/gallium arsenide heterojunction bipolar transistors

Science.gov (United States)

Ahmari, David Abbas

Heterojunction bipolar transistors (HBTs) have demonstrated the high-frequency characteristics as well as the high linearity, gain, and power efficiency necessary to make them attractive for a variety of applications. Specific applications for which HBTs are well suited include amplifiers, analog-to-digital converters, current sources, and optoelectronic integrated circuits. Currently, most commercially available HBT-based integrated circuits employ the AlGaAs/GaAs material system in applications such as a 4-GHz gain block used in wireless phones. As modern systems require higher-performance and lower-cost devices, HBTs utilizing the newer, InGaP/GaAs and InP/InGaAs material systems will begin to dominate the HBT market. To enable the widespread use of InGaP/GaAs HBTs, much research on the fabrication, performance, and characterization of these devices is required. This dissertation will discuss the design and implementation of high-performance InGaP/GaAs HBTs as well as study HBT device physics and characterization.

Measurement of low-frequency base and collector current noise and coherence in SiGe heterojunction bipolar transistors using transimpedance amplifiers

NARCIS (Netherlands)

Bruce, S.P.O.; Vandamme, L.K.J.; Rydberg, A.

1999-01-01

Transimpedance amplifiers have been used for direct study of current noise in silicon germanium (SiGe) heterojunction bipolar transistors (HBT's) at different biasing conditions. This has facilitated a wider range of resistances in the measurement circuit around the transistor than is possible when

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

Science.gov (United States)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

Design of pressure-driven microfluidic networks using electric circuit analogy.

Science.gov (United States)

Oh, Kwang W; Lee, Kangsun; Ahn, Byungwook; Furlani, Edward P

2012-02-07

This article reviews the application of electric circuit methods for the analysis of pressure-driven microfluidic networks with an emphasis on concentration- and flow-dependent systems. The application of circuit methods to microfluidics is based on the analogous behaviour of hydraulic and electric circuits with correlations of pressure to voltage, volumetric flow rate to current, and hydraulic to electric resistance. Circuit analysis enables rapid predictions of pressure-driven laminar flow in microchannels and is very useful for designing complex microfluidic networks in advance of fabrication. This article provides a comprehensive overview of the physics of pressure-driven laminar flow, the formal analogy between electric and hydraulic circuits, applications of circuit theory to microfluidic network-based devices, recent development and applications of concentration- and flow-dependent microfluidic networks, and promising future applications. The lab-on-a-chip (LOC) and microfluidics community will gain insightful ideas and practical design strategies for developing unique microfluidic network-based devices to address a broad range of biological, chemical, pharmaceutical, and other scientific and technical challenges.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

Science.gov (United States)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Electrostatic Discharge Current Linear Approach and Circuit Design Method

Directory of Open Access Journals (Sweden)

Pavlos K. Katsivelis

2010-11-01

Full Text Available The Electrostatic Discharge phenomenon is a great threat to all electronic devices and ICs. An electric charge passing rapidly from a charged body to another can seriously harm the last one. However, there is a lack in a linear mathematical approach which will make it possible to design a circuit capable of producing such a sophisticated current waveform. The commonly accepted Electrostatic Discharge current waveform is the one set by the IEC 61000-4-2. However, the over-simplified circuit included in the same standard is incapable of producing such a waveform. Treating the Electrostatic Discharge current waveform of the IEC 61000-4-2 as reference, an approximation method, based on Prony’s method, is developed and applied in order to obtain a linear system’s response. Considering a known input, a method to design a circuit, able to generate this ESD current waveform in presented. The circuit synthesis assumes ideal active elements. A simulation is carried out using the PSpice software.

Study and simulation of the time behaviour of MOS transistor devices. Application to a logic assembly

International Nuclear Information System (INIS)

Barocas, Marcel

1974-01-01

The objective of this research thesis is to determine, by simulation, the time response of devices based on MOS transistors. After a theoretical study of the MOS element, the author develops a transistor model based on its physical components. This model is firstly used to obtain the transistor static characteristics. The author then studies the time response of the inverter logic circuit which is the basic operator of these circuits. Theoretical results are verified by simulation and by experiments. The author then reports a detailed study of the inverter input impedance, and the decoupling property between logic operators in cascade. The simulation confirms the obtained results. Based on this decoupling property, the output time response of a logic chain is studied by using a simulation software. A general method of determination of the output time response is developed with application to a logic assembly [fr

Fabricating an organic complementary inverter by integrating two transistors on a single substrate

International Nuclear Information System (INIS)

Wang Jun; Wei Bin; Zhang Jianhua

2008-01-01

Organic complementary inverters were fabricated by integrating two transistors of different electric type on a single substrate. One is a p-type organic heterojunction transistor with a depletion–accumulation mode that acts as a load element. The other is an n-type transistor with an accumulation mode that acts as a drive element. Typical inverter characteristics with a voltage gain of 12 were obtained. Compared with conventional devices, our organic complementary inverter used only one-step patterning of an organic semiconductor, and simultaneously suppressed the leakage current between supply voltage and ground. Therefore, current studies provide a simpler path to fabrication of organic complementary circuits

Improving the performance of X-ray proportional counters by using field transistor preamplifiers

International Nuclear Information System (INIS)

Kalinina, N.I.; Mel'ttser, L.V.; Pan'kin, V.V.

1972-01-01

The possibility of using low-noise field-effect transistors with the n-channel in preamplifiers for x-ray proportional counters constitutes the object of this article. The operation of the preamplifier assembled according to the scheme of the voltage amplifier and charge-sensitive preamplifier has been studied. The use of the field-effect transistor with the n-channel in preamplifiers for proportional counters allows to improve significantly the energy resolution and operation at reduced voltage and at high loads. Notably good results have been obtained when constructing the circuit of the premplifier with the field-effect transistor on the charge-sensitive principle. The use of home-produced field-effect transistors makes it possible to construct detectors of roentgen radiometric instruments to measure light element content with proportional counters at reduced voltage

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity

International Nuclear Information System (INIS)

Li Jinjin; Zhu Kadi

2011-01-01

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

A quantum optical transistor with a single quantum dot in a photonic crystal nanocavity.

Science.gov (United States)

Li, Jin-Jin; Zhu, Ka-Di

2011-02-04

Laser and strong coupling can coexist in a single quantum dot (QD) coupled to a photonic crystal nanocavity. This provides an important clue towards the realization of a quantum optical transistor. Using experimentally realistic parameters, in this work, theoretical analysis shows that such a quantum optical transistor can be switched on or off by turning on or off the pump laser, which corresponds to attenuation or amplification of the probe laser, respectively. Furthermore, based on this quantum optical transistor, an all-optical measurement of the vacuum Rabi splitting is also presented. The idea of associating a quantum optical transistor with this coupled QD-nanocavity system may achieve images of light controlling light in all-optical logic circuits and quantum computers.

Design of remote laser-induced fluorescence system's acquisition circuit

Science.gov (United States)

Wang, Guoqing; Lou, Yue; Wang, Ran; Yan, Debao; Li, Xin; Zhao, Xin; Chen, Dong; Zhao, Qi

2017-10-01

Laser-induced fluorescence system(LIfS) has been found its significant application in identifying one kind of substance from another by its properties even it's thimbleful, and becomes useful in plenty of fields. Many superior works have reported LIfS' theoretical analysis , designs and uses. However, the usual LIPS is always constructed in labs to detect matter quite closely, for the system using low-power laser as excitation source and charge coupled device (CCD) as detector. Promoting the detectivity of LIfS is of much concern to spread its application. Here, we take a high-energy narrow-pulse laser instead of commonly used continuous wave laser to operate sample, thus we can get strong fluorescent. Besides, photomultiplier (PMT) with high sensitivity is adopted in our system to detect extremely weak fluorescence after a long flight time from the sample to the detector. Another advantage in our system, as the fluorescence collected into spectroscopy, multiple wavelengths of light can be converted to the corresponding electrical signals with the linear array multichannel PMT. Therefore, at the cost of high-powered incentive and high-sensitive detector, a remote LIFS is get. In order to run this system, it is of importance to turn light signal to digital signal which can be processed by computer. The pulse width of fluorescence is deeply associated with excitation laser, at the nanosecond(ns) level, which has a high demand for acquisition circuit. We design an acquisition circuit including, I/V conversion circuit, amplifying circuit and peak-holding circuit. The simulation of circuit shows that peak-holding circuit can be one effective approach to reducing difficulty of acquisition circuit.

Improvement in Brightness Uniformity by Compensating for the Threshold Voltages of Both the Driving Thin-Film Transistor and the Organic Light-Emitting Diode for Active-Matrix Organic Light-Emitting Diode Displays

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2014-01-01

Full Text Available This paper proposes a novel pixel circuit design and driving method for active-matrix organic light-emitting diode (AM-OLED displays that use low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs as driving element. The automatic integrated circuit modeling simulation program with integrated circuit emphasis (AIM-SPICE simulator was used to verify that the proposed pixel circuit, which comprises five transistors and one capacitor, can supply uniform output current. The voltage programming method of the proposed pixel circuit comprises three periods: reset, compensation with data input, and emission periods. The simulated results reflected excellent performance. For instance, when ΔVTH=±0.33 V, the average error rate of the OLED current variation was low (<0.8%, and when ΔVTH_OLED=+0.33 V, the error rate of the OLED current variation was 4.7%. Moreover, when the I×R (current × resistance drop voltage of a power line was 0.3 V, the error rate of the OLED current variation was 5.8%. The simulated results indicated that the proposed pixel circuit exhibits high immunity to the threshold voltage deviation of both the driving poly-Si TFTs and OLEDs, and simultaneously compensates for the I×R drop voltage of a power line.