Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

Directory of Open Access Journals (Sweden)

Shisheng Cai

2017-03-01

Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

Sample pretreatment for the determination of metal impurities in silicon wafer

International Nuclear Information System (INIS)

Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

1999-01-01

The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Science.gov (United States)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Sol-gel bonding of silicon wafers

International Nuclear Information System (INIS)

Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

2005-01-01

Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

KAUST Repository

Yang, Xiaoming

2014-10-01

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

KAUST Repository

Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

2014-01-01

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

Silicon waveguides produced by wafer bonding

DEFF Research Database (Denmark)

Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

2005-01-01

X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

Science.gov (United States)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

2009-07-01

Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Lamb wave propagation in monocrystalline silicon wafers.

Science.gov (United States)

Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

CERN Multimedia

Honma, Alan

1999-01-01

Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

International Nuclear Information System (INIS)

Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

2006-01-01

The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

International Nuclear Information System (INIS)

Brehm, L.; Kregsamer, P.; Pianetta, P.

2000-01-01

It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

International Nuclear Information System (INIS)

Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

1999-01-01

The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

CERN Multimedia

Honma, Alan

1999-01-01

Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

Cohesive zone model for direct silicon wafer bonding

Science.gov (United States)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

International Nuclear Information System (INIS)

Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

2014-01-01

Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

Science.gov (United States)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

International Nuclear Information System (INIS)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-01-01

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

Science.gov (United States)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

External self-gettering of nickel in float zone silicon wafers

Science.gov (United States)

Gay, N.; Martinuzzi, S.

1997-05-01

During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

Characterization of silicon-on-insulator wafers

Science.gov (United States)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

International Nuclear Information System (INIS)

Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

2003-01-01

Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

Chemical polishing of epitoxial silicon wafer

International Nuclear Information System (INIS)

Osada, Shohei

1978-01-01

SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

First thin AC-coupled silicon strip sensors on 8-inch wafers

Energy Technology Data Exchange (ETDEWEB)

Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

2016-09-11

The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

Directory of Open Access Journals (Sweden)

V. A. Solodukha

2016-01-01

Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

Science.gov (United States)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

International Nuclear Information System (INIS)

Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

2006-01-01

An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

Science.gov (United States)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Industrial Silicon Wafer Solar Cells

Directory of Open Access Journals (Sweden)

Dirk-Holger Neuhaus

2007-01-01

Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

Residual stress in silicon wafer using IR polariscope

Science.gov (United States)

Lu, Zhijia; Wang, Pin; Asundi, Anand

2008-09-01

The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

Science.gov (United States)

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-03-30

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

Science.gov (United States)

Kulshreshtha, Prashant Kumar

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

Science.gov (United States)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Peptide and protein loading into porous silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

2008-02-15

The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

Science.gov (United States)

Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

2013-04-01

In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

Science.gov (United States)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Eutectic and solid-state wafer bonding of silicon with gold

International Nuclear Information System (INIS)

Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

2012-01-01

Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

Science.gov (United States)

Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

2018-06-01

Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

Science.gov (United States)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

"Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

Science.gov (United States)

Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

2013-04-01

During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

NARCIS (Netherlands)

Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

International Nuclear Information System (INIS)

Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

2007-01-01

The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

2014-02-07

Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

Contacting graphene in a 200 mm wafer silicon technology environment

Science.gov (United States)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

Science.gov (United States)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

Science.gov (United States)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

Process induced sub-surface damage in mechanically ground silicon wafers

International Nuclear Information System (INIS)

Yang Yu; De Munck, Koen; Teixeira, Ricardo Cotrin; Swinnen, Bart; De Wolf, Ingrid; Verlinden, Bert

2008-01-01

Micro-Raman spectroscopy, scanning electron microcopy, atomic force microscopy and preferential etching were used to characterize the sub-surface damage induced by the rough and fine grinding steps used to make ultra-thin silicon wafers. The roughly and ultra-finely ground silicon wafers were examined on both the machined (1 0 0) planes and the cross-sectional (1 1 0) planes. They reveal similar multi-layer damage structures, consisting of amorphous, plastically deformed and elastically stressed layers. However, the thickness of each layer in the roughly ground sample is much higher than its counterpart layers in the ultra-finely ground sample. The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30 MPa, respectively. In each case, the top amorphous layer is believed to be the result of sequential phase transformations (Si-I to Si-II to amorphous Si). These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in rough grinding, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks

Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

Directory of Open Access Journals (Sweden)

Di Di

2014-01-01

Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

Directory of Open Access Journals (Sweden)

Min-Kyoo Song

2013-01-01

Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

Energy Technology Data Exchange (ETDEWEB)

Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

2012-09-15

We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

Tests of a silicon wafer based neutron collimator

International Nuclear Information System (INIS)

Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

2001-01-01

A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

Tests of a silicon wafer based neutron collimator

CERN Document Server

Cussen, L D; Anderson, I S; Hoeghoj, P

2001-01-01

A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

Coherent spin transport through a 350 micron thick silicon wafer.

Science.gov (United States)

Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

2007-10-26

We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

Science.gov (United States)

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

Science.gov (United States)

Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

2017-09-01

Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

Ambient plasma treatment of silicon wafers for surface passivation recovery

Science.gov (United States)

Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

2017-08-01

In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

Electrical Interconnections Through CMOS Wafers

DEFF Research Database (Denmark)

Rasmussen, Frank Engel

2003-01-01

Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

Denuded zone in Czochralski silicon wafer with high carbon content

International Nuclear Information System (INIS)

Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

2006-01-01

The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

Denuded zone in Czochralski silicon wafer with high carbon content

Science.gov (United States)

Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

2006-12-01

The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

Directory of Open Access Journals (Sweden)

Gnilenko A. B.

2012-02-01

Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

A Reuse Evaluation for Solar-Cell Silicon Wafers via Shift Revolution and Tool Rotation Using Magnetic Assistance in Ultrasonic Electrochemical Micromachining

Directory of Open Access Journals (Sweden)

P. S. Pa

2013-01-01

Full Text Available A new reuse fabrication using a tool module with rotation and revolution through a process of magnetic assistance in ultrasonic electrochemical micromachining (UEMM for removal of the surface layers from silicon wafers of solar cells is demonstrated. The target of the proposed reuse fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach to removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. The high revolution speed of the shift with the high rotation speed of the designed tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. High frequency and high power of ultrasonic with large electrolyte flow rate and high magnetic strengths with a small distance between the two magnets provide a large discharge effect and good removal; only a short period of time is required to remove the epoxy film and Si3N4 layer easily and cleanly.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

Science.gov (United States)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

International Nuclear Information System (INIS)

Vega, M; Lasorsa, C; Lerner, B; Perez, M; Granell, P

2016-01-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production. (paper)

Effect of PECVD SiNx/SiOy Nx –Si interface property on surface passivation of silicon wafer

International Nuclear Information System (INIS)

Jia Xiao-Jie; Zhou Chun-Lan; Zhou Su; Wang Wen-Jing; Zhu Jun-Jie

2016-01-01

It is studied in this paper that the electrical characteristics of the interface between SiO y N x /SiN x stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiO y N x layer on interface parameters, such as interface state density Di t and fixed charge Q f , and the surface passivation quality of silicon are observed. Capacitance–voltage measurements reveal that inserting a thin SiO y N x layer between the SiN x and the silicon wafer can suppress Q f in the film and D it at the interface. The positive Q f and D it and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiO y N x film increasing. Prepared by deposition at a low temperature and a low ratio of N 2 O/SiH 4 flow rate, the SiO y N x /SiN x stacks result in a low effective surface recombination velocity (S eff ) of 6 cm/s on a p-type 1 Ω·cm–5 Ω·cm FZ silicon wafer. The positive relationship between S eff and D it suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. (paper)

Detection of trace contamination of copper on a silicon wafer with TXRF

International Nuclear Information System (INIS)

Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

2000-01-01

The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

Formation of cross-cutting structures with different porosity on thick silicon wafers

Directory of Open Access Journals (Sweden)

Vera A. Yuzova

2017-06-01

The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

Energy Technology Data Exchange (ETDEWEB)

Antoniadis, H.

2011-03-01

Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink high efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.

Materials preparation and fabrication of pyroelectric polymer/silicon MOSFET detector arrays. Final report

International Nuclear Information System (INIS)

Bloomfield, P.

1992-01-01

The authors have delivered several 64-element linear arrays of pyroelectric elements fully integrated on silicon wafers with MOS readout devices. They have delivered detailed drawings of the linear arrays to LANL. They have processed a series of two inch wafers per submitted design. Each two inch wafer contains two 64 element arrays. After spin-coating copolymer onto the arrays, vacuum depositing the top electrodes, and polarizing the copolymer films so as to make them pyroelectrically active, each wafer was split in half. The authors developed a thicker oxide coating separating the extended gate electrode (beneath the polymer detector) from the silicon. This should reduce its parasitic capacitance and hence improve the S/N. They provided LANL three processed 64 element sensor arrays. Each array was affixed to a connector panel and selected solder pads of the common ground, the common source voltage supply connections, the 64 individual drain connections, and the 64 drain connections (for direct pyroelectric sensing response rather than the MOSFET action) were wire bonded to the connector panel solder pads. This entails (64 + 64 + 1 + 1) = 130 possible bond connections per 64 element array. This report now details the processing steps and the progress of the individual wafers as they were carried through from beginning to end

Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

Science.gov (United States)

Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

2012-03-01

Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

Development of thin film measurement program of wafer for spin etcher

International Nuclear Information System (INIS)

Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

2001-01-01

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

Development of thin film measurement program of wafer for spin etcher

Energy Technology Data Exchange (ETDEWEB)

Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

2001-11-15

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

Science.gov (United States)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

Science.gov (United States)

Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

2013-05-06

Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

Science.gov (United States)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

International Nuclear Information System (INIS)

Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

2006-01-01

The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

Sol-gel bonding of silicon wafers

International Nuclear Information System (INIS)

Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

2005-01-01

Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

KAUST Repository

Bahabry, Rabab R.

2018-01-02

Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

KAUST Repository

Bahabry, Rabab R.; Kutbee, Arwa T.; Khan, Sherjeel M.; Sepulveda, Adrian C.; Wicaksono, Irmandy; Nour, Maha A.; Wehbe, Nimer; Almislem, Amani Saleh Saad; Ghoneim, Mohamed T.; Sevilla, Galo T.; Syed, Ahad; Shaikh, Sohail F.; Hussain, Muhammad Mustafa

2018-01-01

Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

The uses of Man-Made diamond in wafering applications

Science.gov (United States)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Quantitative analysis of phosphosilicate glass films on silicon wafers for calibration of x-ray fluorescence spectrometry standards

International Nuclear Information System (INIS)

Weissman, S.H.

1983-01-01

The phosphorus and silicon contents of phosphosilicate glass films deposited by chemical vapor deposition (CVD) on silicon wafers were determined. These films were prepared for use as x-ray fluorescence (XRF) spectrometry standards. The thin films were removed from the wafer by etching with dilute hydrofluoric acid, and the P and Si concentrations in solution were determined by inductively coupled plasma atomic emission spectroscopy (ICP). The calculated phosphorus concentration ranged from 2.2 to 12 wt %, with an uncertainty of 2.73 to 10.1 relative percent. Variation between the calculated weight loss (summation of P 2 O 5 and SiO 2 amounts as determined by ICP) and the measured weight loss (determined gravimetrically) averaged 4.9%. Results from the ICP method, Fourier transform-infrared spectroscopy (FT-IR), dispersive infrared spectroscopy, electron microprobe, and x-ray fluorescence spectroscopy for the same samples are compared

Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

2016-02-15

Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

Science.gov (United States)

Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

2018-01-01

Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

Synthesis of thermoresponsive poly(N-isopropylacrylamide) brush on silicon wafer surface via atom transfer radical polymerization

Energy Technology Data Exchange (ETDEWEB)

Turan, Eylem; Demirci, Serkan [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey); Caykara, Tuncer, E-mail: caykara@gazi.edu.t [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey)

2010-08-31

Thermoresponsive poly(N-isopropylacrylamide) [poly(NIPAM)] brush on silicon wafer surface was prepared by combining the self-assembled monolayer of initiator and atom transfer radical polymerization (ATRP). The resulting polymer brush was characterized by in situ reflectance Fourier transform infrared spectroscopy, atomic force microscopy and ellipsometry techniques. Gel permeation chromatography determination of the number-average molecular weight and polydispersity index of the brush detached from the silicon wafer surface suggested that the surface-initiated ATRP method can provide relatively homogeneous polymer brush. Contact angle measurements exhibited a two-stage increase upon heating over the board temperature range 25-45 {sup o}C, which is in contrast to the fact that free poly(NIPAM) homopolymer in aqueous solution exhibits a phase transition at ca. 34 {sup o}C within a narrow temperature range. The first de-wetting transition takes place at 27 {sup o}C, which can be tentatively attributed to the n-cluster induced collapse of the inner region of poly(NIPAM) brush close to the silicon surface; the second de-wetting transition occurs at 38 {sup o}C, which can be attributed to the outer region of poly(NIPAM) brush, possessing much lower chain density compared to that of the inner part.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

Science.gov (United States)

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Analysis of borophosphosilicate glass layers on silicon wafers by X-ray emission from photon and electron excitation

International Nuclear Information System (INIS)

Elgersma, O.; Borstrok, J.J.M.

1989-01-01

Phosphorus and oxygen concentrations in the homogeneous layer of borosilicate glass (BPSG) deposited on Si-integrated circuits are determined by X-ray fluorescence from photon excitation. The X-ray emission from electron excitation in an open X-ray tube instrument yields a sufficiently precise determination of the boron content. The thickness of the layer can be derived from silicon Kα-fluorescence. A calibration model is proposed for photon as well as for electron excitation. The experimentally determined parameters in this model well agree with those derived from fundamental parameters for X-ray absorption and emission. The chemical surrounding of silicon affects strongly the peak profile of the silicon Kβ-emission. This enables to distinguish emission from the silicon atoms in the wafer and from the silicon atoms in the silicon oxide complexes of the BPSG-layer. (author)

Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

International Nuclear Information System (INIS)

Mou, Chun-Yueh; Yuan, Wei-Li; Shih, Chih-Hsin

2013-01-01

Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate

Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Mou, Chun-Yueh, E-mail: cymou165@gmail.com; Yuan, Wei-Li; Shih, Chih-Hsin

2013-06-30

Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate.

Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

International Nuclear Information System (INIS)

Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

2005-01-01

This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

Wafer of Intel Pentium 4 Prescott Chips

CERN Multimedia

Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

International Nuclear Information System (INIS)

Takahara, Hikari; Mori, Yoshihiro; Shibata, Harumi; Shimazaki, Ayako; Shabani, Mohammad B.; Yamagami, Motoyuki; Yabumoto, Norikuni; Nishihagi, Kazuo; Gohshi, Yohichi

2013-01-01

Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10 9 and 5 × 10 10 atoms/cm 2 Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO 2 , silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10 10 atoms/cm 2 . • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

Science.gov (United States)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

The influence of diffusion of fluorine compounds for silicon lateral etching

Energy Technology Data Exchange (ETDEWEB)

Verdonck, Patrick; Goodyear, Alec; Braithwaite, Nicholas St.John

2004-07-01

In an earlier study, it was proposed that long-range surface transport of fluorine atoms could precede the eventual binding to a silicon atom. The rate of binding increases if the silicon is bombarded with high energy ions. In this study, the lateral etching of a silicon layer, sandwiched between two silicon dioxide layers, was studied in order to investigate and extend these hypotheses. The under etching of the silicon layer was higher for wafers which suffered ion bombardment, showing that this mechanism is important even for horizontal etching. At the same time, the thickness of the silicon layer was varied. In all cases, the thinner silicon layer etched much faster then the thicker layer, indicating that fluorine surface transport is much more important than re-emission for these processes. The etch rate increase with ion bombardment can be explained by the fact that part of the energy of the incoming ions is transferred to the fluorine compounds which are on the horizontal surfaces and that ion bombardment enhances the fluorine surface transport.

Nano-Photonic Structures for Light Trapping in Ultra-Thin Crystalline Silicon Solar Cells

Directory of Open Access Journals (Sweden)

Prathap Pathi

2017-01-01

Full Text Available Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a dense mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm and is slightly lower (by ~5% at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm silicon and just 1%–2% for thicker (>100 μm cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. This architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.

Use of porous silicon to minimize oxidation induced stacking fault defects in silicon

International Nuclear Information System (INIS)

Shieh, S.Y.; Evans, J.W.

1992-01-01

This paper presents methods for minimizing stacking fault defects, generated during oxidation of silicon, include damaging the back of the wafer or depositing poly-silicon on the back. In either case a highly defective structure is created and this is capable of gettering either self-interstitials or impurities which promote nucleation of stacking fault defects. A novel method of minimizing these defects is to form a patch of porous silicon on the back of the wafer by electrochemical etching. Annealing under inert gas prior to oxidation may then result in the necessary gettering. Experiments were carried out in which wafers were subjected to this treatment. Subsequent to oxidation, the wafers were etched to remove oxide and reveal defects. The regions of the wafer adjacent to the porous silicon patch were defect-free, whereas remote regions had defects. Deep level transient spectroscopy has been used to examine the gettering capability of porous silicon, and the paper discusses the mechanism by which the porous silicon getters

Locally-enhanced light scattering by a monocrystalline silicon wafer

Directory of Open Access Journals (Sweden)

Li Ma

2018-03-01

Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto

2014-02-25

In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

Science.gov (United States)

Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

2018-02-01

We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

Wafer bonding applications and technology

CERN Document Server

Gösele, Ulrich

2004-01-01

During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

Science.gov (United States)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

Energy Technology Data Exchange (ETDEWEB)

Tiriolo, Raffaele [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Rangnekar, Neel [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Zhang, Han [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Shete, Meera [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Bai, Peng [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Nelson, John [Characterization Facility, University of Minnesota, 12 Shepherd Labs, 100 Union St. S.E. Minneapolis MN 55455 USA; Karapetrova, Evguenia [Surface Scattering and Microdiffraction, X-ray Science Division, Argonne National Laboratory, 9700 S. Cass Ave, Building 438-D002 Argonne IL 60439 USA; Macosko, Christopher W. [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Siepmann, Joern Ilja [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Lamanna, Ernesto [Department of Health Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Lavano, Angelo [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Tsapatsis, Michael [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA

2017-05-08

A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.

Interfacial Characteristics of TiN Coatings on SUS304 and Silicon Wafer Substrates with Pulsed Laser Thermal Shock

International Nuclear Information System (INIS)

Seo, Nokun; Jeon, Seol; Choi, Youngkue; Shin, Hyun-Gyoo; Lee, Heesoo; Jeon, Min-Seok

2014-01-01

TiN coatings prepared on different substrates that had different coefficients of thermal expansion were subjected to pulsed laser thermal shock and observed by using FIB milling to compare the deterioration behaviors. TiN coating on SUS304, which had a larger CTE (⁓17.3 × 10 - 6 /℃) than the coating was degraded with pores and cracks on the surface and showed significant spalling of the coating layer over a certain laser pulses. TiN coating on silicon wafer with a smaller CTE value, ⁓4.2 × 10‒6 /℃, than the coating exhibited less degradation of the coating layer at the same ablation condition. Cracks propagated at the interface were observed in the coating on the silicon wafer, which induced a compressive stress to the coating. The coating on the SUS304 showed less interface cracks while the tensile stress was applied to the coating. Delamination of the coating layer related to the intercolumnar cracks at the interface was observed in both coatings through bright-field TEM analysis.

Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

International Nuclear Information System (INIS)

Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

2012-01-01

Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

2017-05-10

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

International Nuclear Information System (INIS)

Ngo, H-D; Hiess, Andre; Seidemann, Volker; Studzinski, Daniel; Lange, Martin; Leib, Juergen; Shariff, Dzafir; Ashraf, Huma; Steel, Mike; Atabo, Lilian; Reast, Jon

2006-01-01

This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained and plasma configurations are described elsewhere. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

Science.gov (United States)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

Science.gov (United States)

Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

2013-08-20

To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

Directory of Open Access Journals (Sweden)

S. A. Chizhik

2013-01-01

Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

Reduction of absorption loss in multicrystalline silicon via combination of mechanical grooving and porous silicon

Energy Technology Data Exchange (ETDEWEB)

Ben Rabha, Mohamed; Mohamed, Seifeddine Belhadj; Dimassi, Wissem; Gaidi, Mounir; Ezzaouia, Hatem; Bessais, Brahim [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, Technopole de Borj-Cedria, BP 95, 2050 Hammam-Lif (Tunisia)

2011-03-15

Surface texturing of silicon wafer is a key step to enhance light absorption and to improve the solar cell performances. While alkaline-texturing of single crystalline silicon wafers was well established, no efficient chemical solution has been successfully developed for multicrystalline silicon wafers. Thus, the use of alternative new methods for effective texturization of multicrystalline silicon is worth to be investigated. One of the promising texturing techniques of multicrystalline silicon wafers is the use of mechanical grooves. However, most often, physical damages occur during mechanical grooves of the wafer surface, which in turn require an additional step of wet processing-removal damage. Electrochemical surface treatment seems to be an adequate solution for removing mechanical damage throughout porous silicon formation. The topography of untreated and porous silicon-treated mechanically textured surface was investigated using scanning electron microscopy (SEM). As a result of the electrochemical surface treatment, the total reflectivity drops to about 5% in the 400-1000 nm wavelength range and the effective minority carrier diffusion length enhances from 190 {mu}m to about 230 {mu}m (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

Science.gov (United States)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

Internal Friction and Young's Modulus Measurements on SiO2 and Ta2O5 Films Done with an Ultra-High Q Silicon-Wafer Suspension

Directory of Open Access Journals (Sweden)

Granata M.

2015-04-01

Full Text Available In order to study the internal friction of thin films a nodal suspension system called GeNS (Gentle Nodal Suspension has been developed. The key features of this system are: i the possibility to use substrates easily available like silicon wafers; ii extremely low excess losses coming from the suspension system which allows to measure Q factors in excess of 2×108 on 3” diameter wafers; iii reproducibility of measurements within few percent on mechanical losses and 0.01% on resonant frequencies; iv absence of clamping; v the capability to operate at cryogenic temperatures. Measurements at cryogenic temperatures on SiO2 and at room temperature only on Ta2O5 films deposited on silicon are presented.

Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

Science.gov (United States)

Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

2013-01-02

Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

Energy Technology Data Exchange (ETDEWEB)

Trushin, Maxim

2011-07-15

The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

1366 Project Silicon: Reclaiming US Silicon PV Leadership

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

2016-02-16

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

Science.gov (United States)

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

Reliability assessment of ultra-thin HfO{sub 2} films deposited on silicon wafer

Energy Technology Data Exchange (ETDEWEB)

Fu, Wei-En [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Chang, Chia-Wei [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Chang, Yong-Qing [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Yao, Chih-Kai [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Liao, Jiunn-Der, E-mail: jdliao@mail.ncku.edu.tw [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China)

2012-09-01

Highlights: Black-Right-Pointing-Pointer Nano-mechanical properties on annealed ultra-thin HfO{sub 2} film are studied. Black-Right-Pointing-Pointer By AFM analysis, hardness of the crystallized HfO{sub 2} film significantly increases. Black-Right-Pointing-Pointer By nano-indention, the film hardness increases with less contact stiffness. Black-Right-Pointing-Pointer Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO{sub 2}) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO{sub 2} films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO{sub 2} films deposited on silicon wafers (HfO{sub 2}/SiO{sub 2}/Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO{sub 2} (nominal thickness Almost-Equal-To 10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO{sub 2} phases for the atomic layer deposited HfO{sub 2}. The HfSi{sub x}O{sub y} complex formed at the interface between HfO{sub 2} and SiO{sub 2}/Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO{sub 2} film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically

Silicon epitaxy on textured double layer porous silicon by LPCVD

International Nuclear Information System (INIS)

Cai Hong; Shen Honglie; Zhang Lei; Huang Haibin; Lu Linfeng; Tang Zhengxia; Shen Jiancang

2010-01-01

Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521 cm -1 have a width of 7.8 cm -1 , which reveals the high crystalline quality of the silicon epitaxy.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

Science.gov (United States)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

International Nuclear Information System (INIS)

Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

2017-01-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

Science.gov (United States)

Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

2013-11-22

Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

Science.gov (United States)

Norris, D J; Myronov, M; Leadley, D R; Walther, T

2017-12-01

We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

Crystallization behavior of polyethylene on silicon wafers in solution casting processes traced by time-resolved measurements of synchrotron grazing-incidence small-angle and wide-angle X-ray scattering

International Nuclear Information System (INIS)

Sasaki, S; Masunaga, H; Takata, M; Itou, K; Tashiro, K; Okuda, H; Takahara, A

2009-01-01

Crystallization behavior of polyethylene (PE) on silicon wafers in solution casting processes has been successfully traced by time-resolved grazing-incidence small-angle and wide-angle X-ray scattering (GISWAXS) measurements utilizing synchrotron radiation. A p-xylene solution of PE kept at ca. 343 K was dropped on a silicon wafer at ca. 298 K. While the p-xylene evaporated naturally from the dropped solution sample, PE chains crystallized to be a thin film. Raman spectral measurements were performed simultaneously with the GISWAXS measurements to evaluate quantitatively the p-xylene the dropped solution contained. Grazing-incidence wide-angle X-ray scattering (GIWAXS) patterns indicated nucleation and crystal growth in the dropped solution and the following as-cast film. GIWAXS and Raman spectral data revealed that crystallization of PE was enhanced after complete evaporation of the p-xylene from the dropped solution. The [110] and [200] directions of the orthorhombic PE crystal became relatively parallel to the wafer surface with time, which implied that the flat-on lamellae with respect to the wafer surface were mainly formed in the as-cast film. On the other hand, grazing-incidence small-angle X-ray scattering (GISAXS) patterns implied formation of isolated lamellae in the dropped solution. The lamellae and amorphous might alternatively be stacked in the preferred direction perpendicular to the wafer surface. The synchrotron GISWAXS experimental method could be applied for kinetic study on hierarchical structure of polymer thin films.

Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

OpenAIRE

Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

2018-01-01

A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

Porous Silicon Nanowires

Science.gov (United States)

Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

2011-01-01

In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

Directory of Open Access Journals (Sweden)

Xianshu eLuo

2015-04-01

Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

Reticle variation influence on manufacturing line and wafer device performance

Science.gov (United States)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

Science.gov (United States)

Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

2004-10-01

The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

Energy Technology Data Exchange (ETDEWEB)

Rouault de Coligny, P.

2002-09-15

This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

Directory of Open Access Journals (Sweden)

Kae Dal Kwack

2011-01-01

Full Text Available A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

Science.gov (United States)

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

Science.gov (United States)

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light. PMID:22319353

Probing and irradiation tests of ALICE pixel chip wafers and sensors

CERN Document Server

Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

2004-01-01

In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

International Nuclear Information System (INIS)

Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

2005-01-01

Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

Hybrid Integrated Platforms for Silicon Photonics

Science.gov (United States)

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

Science.gov (United States)

Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

2017-09-01

The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

Silicon nanowire-based solar cells

Energy Technology Data Exchange (ETDEWEB)

Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S [Institute of Photonic Technology, Albert-Einstein-Strasse 9, D-07745 Jena (Germany)], E-mail: thomas.stelzner@ipht-jena.de

2008-07-23

The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm{sup 2} open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm{sup -2} were obtained.

Silicon nanowire-based solar cells

International Nuclear Information System (INIS)

Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S

2008-01-01

The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm 2 open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm -2 were obtained

The photovoltaic recharges its batteries

International Nuclear Information System (INIS)

Marandet, L.; Claverie, A.

2006-01-01

Facing the silicon prices increase, many projects appear to solve the supplying problem. This document presents the possible solutions proposed by the research, to control the raw material and to develop new technologies: the solar silicon, the thicker wafers, the energy efficiency, the third generation cells, the organic cell. (A.L.B.)

Characterizing SOI Wafers By Use Of AOTF-PHI

Science.gov (United States)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

International Nuclear Information System (INIS)

Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

1993-01-01

The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

Science.gov (United States)

Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

2018-01-01

Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

Polycrystalline Silicon Gettered by Porous Silicon and Heavy Phosphorous Diffusion

Institute of Scientific and Technical Information of China (English)

LIU Zuming(刘祖明); Souleymane K Traore; ZHANG Zhongwen(张忠文); LUO Yi(罗毅)

2004-01-01

The biggest barrier for photovoltaic (PV) utilization is its high cost, so the key for scale PV utilization is to further decrease the cost of solar cells. One way to improve the efficiency, and therefore lower the cost, is to increase the minority carrier lifetime by controlling the material defects. The main defects in grain boundaries of polycrystalline silicon gettered by porous silicon and heavy phosphorous diffusion have been studied. The porous silicon was formed on the two surfaces of wafers by chemical etching. Phosphorous was then diffused into the wafers at high temperature (900℃). After the porous silicon and diffusion layers were removed, the minority carrier lifetime was measured by photo-conductor decay. The results show that the lifetime's minority carriers are increased greatly after such treatment.

Hybrid Integrated Platforms for Silicon Photonics

Directory of Open Access Journals (Sweden)

John E. Bowers

2010-03-01

Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Study on structural properties of epitaxial silicon films on annealed double layer porous silicon

International Nuclear Information System (INIS)

Yue Zhihao; Shen Honglie; Cai Hong; Lv Hongjie; Liu Bin

2012-01-01

In this paper, epitaxial silicon films were grown on annealed double layer porous silicon by LPCVD. The evolvement of the double layer porous silicon before and after thermal annealing was investigated by scanning electron microscope. X-ray diffraction and Raman spectroscopy were used to investigate the structural properties of the epitaxial silicon thin films grown at different temperature and different pressure. The results show that the surface of the low-porosity layer becomes smooth and there are just few silicon-bridges connecting the porous layer and the substrate wafer. The qualities of the epitaxial silicon thin films become better along with increasing deposition temperature. All of the Raman peaks of silicon films with different deposition pressure are situated at 521 cm -1 under the deposition temperature of 1100 °C, and the Raman intensity of the silicon film deposited at 100 Pa is much closer to that of the monocrystalline silicon wafer. The epitaxial silicon films are all (4 0 0)-oriented and (4 0 0) peak of silicon film deposited at 100 Pa is more symmetric.

Compton recoil electron tracking with silicon strip detectors

International Nuclear Information System (INIS)

O'Neill, T.J.; Ait-Ouamer, F.; Schwartz, I.; Tumer, O.T.; White, R.S.; Zych, A.D.

1992-01-01

The application of silicon strip detectors to Compton gamma ray astronomy telescopes is described in this paper. The Silicon Compton Recoil Telescope (SCRT) tracks Compton recoil electrons in silicon strip converters to provide a unique direction for Compton scattered gamma rays above 1 MeV. With strip detectors of modest positional and energy resolutions of 1 mm FWHM and 3% at 662 keV, respectively, 'true imaging' can be achieved to provide an order of magnitude improvement in sensitivity to 1.6 x 10 - 6 γ/cm 2 -s at 2 MeV. The results of extensive Monte Carlo calculations of recoil electrons traversing multiple layers of 200 micron silicon wafers are presented. Multiple Coulomb scattering of the recoil electron in the silicon wafer of the Compton interaction and the next adjacent wafer is the basic limitation to determining the electron's initial direction

Fabrication of novel AFM probe with high-aspect-ratio ultra-sharp three-face silicon nitride tips

NARCIS (Netherlands)

Vermeer, Rolf; Berenschot, Johan W.; Sarajlic, Edin; Tas, Niels Roelof; Jansen, Henricus V.

In this paper we present the wafer-scale fabrication of molded AFM probes with high aspect ratio ultra-sharp three-plane silicon nitride tips. Using $\\langle$111$\\rangle$ silicon wafers a dedicated process is developed to fabricate molds in the silicon wafer that have a flat triangular bottom

Silicon heterojunction solar cells with novel fluorinated n-type nanocrystalline silicon oxide emitters on p-type crystalline silicon

Science.gov (United States)

Dhar, Sukanta; Mandal, Sourav; Das, Gourab; Mukhopadhyay, Sumita; Pratim Ray, Partha; Banerjee, Chandan; Barua, Asok Kumar

2015-08-01

A novel fluorinated phosphorus doped silicon oxide based nanocrystalline material have been used to prepare heterojunction solar cells on flat p-type crystalline silicon (c-Si) Czochralski (CZ) wafers. The n-type nc-SiO:F:H material were deposited by radio frequency plasma enhanced chemical vapor deposition. Deposited films were characterized in detail by using atomic force microscopy (AFM), high resolution transmission electron microscopy (HRTEM), Raman, fourier transform infrared spectroscopy (FTIR) and optoelectronics properties have been studied using temperature dependent conductivity measurement, Ellipsometry, UV-vis spectrum analysis etc. It is observed that the cell fabricated with fluorinated silicon oxide emitter showing higher initial efficiency (η = 15.64%, Jsc = 32.10 mA/cm2, Voc = 0.630 V, FF = 0.77) for 1 cm2 cell area compare to conventional n-a-Si:H emitter (14.73%) on flat c-Si wafer. These results indicate that n type nc-SiO:F:H material is a promising candidate for heterojunction solar cell on p-type crystalline wafers. The high Jsc value is associated with excellent quantum efficiencies at short wavelengths (<500 nm).

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

Science.gov (United States)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

Liquid phase epitaxial growth of silicon on porous silicon for photovoltaic applications

International Nuclear Information System (INIS)

Berger, S.; Quoizola, S.; Fave, A.; Kaminski, A.; Perichon, S.; Barbier, D.; Laugier, A.

2001-01-01

The aim of this experiment is to grow a thin silicon layer ( 2 atmosphere, and finally LPE silicon growth with different temperature profiles in order to obtain a silicon layer on the sacrificial porous silicon (p-Si). We observed a pyramidal growth on the surface of the (100) porous silicon but the coalescence was difficult to obtain. However, on a p-Si (111) oriented wafer, homogeneous layers were obtained. (orig.)

A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

Energy Technology Data Exchange (ETDEWEB)

Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

2016-12-15

In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Wafer scale integration of catalyst dots into nonplanar microsystems

DEFF Research Database (Denmark)

Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

2007-01-01

In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

a Study of Oxygen Precipitation in Heavily Doped Silicon.

Science.gov (United States)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation

Silicon (100)/SiO2 by XPS

Energy Technology Data Exchange (ETDEWEB)

Jensen, David S.; Kanyal, Supriya S.; Madaan, Nitesh; Vail, Michael A.; Dadson, Andrew; Engelhard, Mark H.; Linford, Matthew R.

2013-09-25

Silicon (100) wafers are ubiquitous in microfabrication and, accordingly, their surface characteristics are important. Herein, we report the analysis of Si (100) via X-ray photoelectron spectroscopy (XPS) using monochromatic Al K radiation. Survey scans show that the material is primarily silicon and oxygen, and the Si 2p region shows two peaks that correspond to elemental silicon and silicon dioxide. Using these peaks the thickness of the native oxide (SiO2) was estimated using the equation of Strohmeier.1 The oxygen peak is symmetric. The material shows small amounts of carbon, fluorine, and nitrogen contamination. These silicon wafers are used as the base material for subsequent growth of templated carbon nanotubes.

Wafer level packaging of MEMS

International Nuclear Information System (INIS)

Esashi, Masayoshi

2008-01-01

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

Quasimetallic silicon micromachined photonic crystals

International Nuclear Information System (INIS)

Temelkuran, B.; Bayindir, Mehmet; Ozbay, E.; Kavanaugh, J. P.; Sigalas, M. M.; Tuttle, G.

2001-01-01

We report on fabrication of a layer-by-layer photonic crystal using highly doped silicon wafers processed by semiconductor micromachining techniques. The crystals, built using (100) silicon wafers, resulted in an upper stop band edge at 100 GHz. The transmission and defect characteristics of these structures were found to be analogous to metallic photonic crystals. We also investigated the effect of doping concentration on the defect characteristics. The experimental results agree well with predictions of the transfer matrix method simulations

Effect of potential steps on porous silicon formation

International Nuclear Information System (INIS)

Cheng Xuan; Feng Zude; Luo Guangfeng

2003-01-01

Porous silicon microstructures were fabricated by applying potential steps through which both anodic and cathodic potentials were periodically applied to silicon wafers. The electrochemical behaviors of porous silicon layers were examined by performing polarization measurements, followed by analyzing the open-circuit potential (E ocp ) and the reaction rate in terms of corrosion current density (j corr ). The surface morphologies and surface products of porous silicon were characterized by scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). It was found that the values of E ocp and j corr varied more significantly and irregularly during different polarization stages when the potentials were continuously applied to the wafer surface, while virtually unchanged after 2 min of periodic potential application. In addition, slower reaction rates were observed with applying potential steps, as indicated by smaller values of j corr . The enhancement on refreshment of silicon surfaces by periodic potential polarization significantly accelerated the growth of porous silicon. The microstructures became more uniformed and better defined due to the improved passivating nature of wafer surfaces

Low temperature spalling of silicon: A crack propagation study

Energy Technology Data Exchange (ETDEWEB)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

Science.gov (United States)

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

Proposed method of assembly for the BCD silicon strip vertex detector modules

International Nuclear Information System (INIS)

Lindenmeyer, C.

1989-01-01

The BCD Silicon strip Vertex Detector is constructed of 10 identical central region modules and 18 similar forward region modules. This memo describes a method of assembling these modules from individual silicon wafers. Each wafer is fitted with associated front end electronics and cables and has been tested to insure that only good wafers reach the final assembly stage. 5 figs

Cost of Czochralski wafers as a function of diameter

Science.gov (United States)

Leipold, M. H.; Radics, C.; Kachare, A.

1980-02-01

The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

Silicon hybrid integration

International Nuclear Information System (INIS)

Li Xianyao; Yuan Taonu; Shao Shiqian; Shi Zujun; Wang Yi; Yu Yude; Yu Jinzhong

2011-01-01

Recently,much attention has concentrated on silicon based photonic integrated circuits (PICs), which provide a cost-effective solution for high speed, wide bandwidth optical interconnection and optical communication.To integrate III-V compounds and germanium semiconductors on silicon substrates,at present there are two kinds of manufacturing methods, i.e., heteroepitaxy and bonding. Low-temperature wafer bonding which can overcome the high growth temperature, lattice mismatch,and incompatibility of thermal expansion coefficients during heteroepitaxy, has offered the possibility for large-scale heterogeneous integration. In this paper, several commonly used bonding methods are reviewed, and the future trends of low temperature wafer bonding envisaged. (authors)

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

Science.gov (United States)

Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

2017-04-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

International Nuclear Information System (INIS)

Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

2017-01-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

Directory of Open Access Journals (Sweden)

Ali Attaran

2014-01-01

Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

Directory of Open Access Journals (Sweden)

Azrul Azlan Hamzah

2008-11-01

Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

Fabrication and Modification of Nanoporous Silicon Particles

Science.gov (United States)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

Science.gov (United States)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Sacrificial wafer bonding for planarization after very deep etching

NARCIS (Netherlands)

Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

Ion-implanted capacitively coupled silicon strip detectors with integrated polysilicon bias resistors processed on a 100 mm wafer

International Nuclear Information System (INIS)

Hietanen, I.; Lindgren, J.; Orava, R.; Tuuva, T.; Voutilainen, M.; Brenner, R.; Andersson, M.; Leinonen, K.; Ronkainen, H.

1991-01-01

Double-sided silicon strip detectors with integrated coupling capacitors and polysilicon resistors have been processed on a 100 mm wafer. A detector with an active area of 19x19 mm 2 was connected to LSI readout electronics and tested. The strip pitch of the detector is 25 μm on the p-side and 50 μm on the n-side. The readout pitch is 50 μm on both sides. The number of readout strips is 774 and the total number of strips is 1161. On the p-side a signal-to-noise of 35 has been measured using a 90 Sr β-source. The n-side has been studied using a laser. (orig.)

Seedless electroplating on patterned silicon

NARCIS (Netherlands)

Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

2006-01-01

Nickel thin films have been electrodeposited without the use of an additional seed layer, on highly doped silicon wafers. These substrates conduct sufficiently well to allow deposition using a peripherical electrical contact on the wafer. Films 2 μm thick have been deposited using a nickel sulfamate

Bias-assisted KOH etching of macroporous silicon membranes

International Nuclear Information System (INIS)

Mathwig, K; Geilhufe, M; Müller, F; Gösele, U

2011-01-01

This paper presents an improved technique to fabricate porous membranes from macroporous silicon as a starting material. A crucial step in the fabrication process is the dissolution of silicon from the backside of the porous wafer by aqueous potassium hydroxide to open up the pores. We improved this step by biasing the silicon wafer electrically against the KOH. By monitoring the current–time characteristics a good control of the process is achieved and the yield is improved. Also, the etching can be stopped instantaneously and automatically by short-circuiting Si and KOH. Moreover, the bias-assisted etching allows for the controlled fabrication of silicon dioxide tube arrays when the silicon pore walls are oxidized and inverted pores are released.

Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

NARCIS (Netherlands)

Haneveld, J.; Berenschot, Johan W.; Maury, P.A.; Jansen, Henricus V.

2005-01-01

A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7-20 nm wide, 40-100 nm high and centimeters long. All dimensions are easily

Hydrogen-induced structural changes in polycrystalline silicon as revealed by positron lifetime spectroscopy

International Nuclear Information System (INIS)

Arole, V.M.; Takwale, M.G.; Bhide, V.G.

1989-01-01

Hydrogen passivation of polycrystalline silicon wafer is carried out in order to reduce the deleterious effects of grain boundaries. A systematic variation is made in the process parameters implemented during hydrogen passivation and the results of room temperature resistivity measurements are reported. As an efficient tool to study the structure change, positron lifetime spectroscopic measurements are performed on original and hydrogenated polycrystalline silicon wafers and a systematic correlation is sought between the changes that take place in the electrical and structural properties of polycrystalline silicon wafer, brought about by hydrogen passivation. (author)

Xe{sup +} ion beam induced rippled structures on Si miscut wafers

Energy Technology Data Exchange (ETDEWEB)

Hanisch, Antje; Grenzer, Joerg [Forschungszentrum Dresden-Rossendorf, Dresden (Germany); Biermanns, Andreas; Pietsch, Ullrich [Institute of Physics, University of Siegen (Germany)

2009-07-01

We report on the influence of the initial roughness and crystallography of the substrate on the formation of self-organized ripple structures on semiconductors surfaces by noble gas ion bombardment. The Bradley-Harper theory predicts that an initial roughness is most important for starting the sputtering process which in the ends leads to the evolution of regular patterns. We produced periodic structures with intermediate Xe{sup +} ion energies (5-70 keV) at different incidence and azimuthal angles which lead to the assumption that also crystallography plays a role at the beginning of ripple evolution. Most of the previous investigations started from the original roughness of a polished silicon wafer. We used (001) silicon wafers with a miscut angle of 1 , 5 and 10 towards[110]. We studied the ripple formation keeping the ion beam parallel to the[111],[-1-11] or[-111] direction, i.e. parallel, antiparallel or perpendicular to the miscut direction[110]. The parallel and antiparallel case implies a variation of the incidence angle with increased roughness over the surface step terraces. The perpendicular orientation means almost no roughness. The results were compared to normal Si(001) and Si(111) wafers.

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

CERN Document Server

Bronuzzi, J.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

Science.gov (United States)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Electroless porous silicon formation applied to fabrication of boron-silica-glass cantilevers

DEFF Research Database (Denmark)

Teva, Jordi; Davis, Zachary James; Hansen, Ole

2010-01-01

This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5-1 mm3) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases...... where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing...... for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH...

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

Science.gov (United States)

Grant, Nicholas E.

2016-01-01

A procedure to measure the bulk lifetime (>100 µsec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (<1012 cm-3). PMID:26779939

Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

Science.gov (United States)

Egelkrout, D. W.

1981-01-01

Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

Linear self-assembly and grafting of gold nanorods into arrayed micrometer-long nanowires on a silicon wafer via a combined top-down/bottom-up approach.

Science.gov (United States)

Lestini, Elena; Andrei, Codrin; Zerulla, Dominic

2018-01-01

Macroscopically long wire-like arrangements of gold nanoparticles were obtained by controlled evaporation and partial coalescence of an aqueous colloidal solution of capped CTAB-Au nanorods onto a functionalised 3-mercaptopropyl trimethoxysilane (MPTMS) silicon substrate, using a removable, silicon wafer with a hydrophobic surface that serves as a "handrail" for the initial nanorods' linear self-assembly. The wire-like structures display a quasi-continuous pattern by thermal annealing of the gold nanorods when the solvent (i.e. water) is evaporated at temperatures rising from 20°C to 140°C. Formation of both single and self-replicating parallel 1D-superstructures consisting of two or even three wires is observed and explained under such conditions.

TXRF analysis of trace metals in thin silicon nitride films

International Nuclear Information System (INIS)

Vereecke, G.; Arnauts, S.; Verstraeten, K.; Schaekers, M.; Heyrts, M.M.

2000-01-01

As critical dimensions of integrated circuits continue to decrease, high dielectric constant materials such as silicon nitride are being considered to replace silicon dioxide in capacitors and transistors. The achievement of low levels of metal contamination in these layers is critical for high performance and reliability. Existing methods of quantitative analysis of trace metals in silicon nitride require high amounts of sample (from about 0.1 to 1 g, compared to a mass of 0.2 mg for a 2 nm thick film on a 8'' silicon wafer), and involve digestion steps not applicable to films on wafers or non-standard techniques such as neutron activation analysis. A novel approach has recently been developed to analyze trace metals in thin films with analytical techniques currently used in the semiconductor industry. Sample preparation consists of three steps: (1) decomposition of the silicon nitride matrix by moist HF condensed at the wafer surface to form ammonium fluosilicate. (2) vaporization of the fluosilicate by a short heat treatment at 300 o C. (3) collection of contaminants by scanning the wafer surface with a solution droplet (VPD-DSC procedure). The determination of trace metals is performed by drying the droplet on the wafer and by analyzing the residue by TXRF, as it offers the advantages of multi-elemental analysis with no dilution of the sample. The lower limits of detection for metals in 2 nm thick films on 8'' silicon wafers range from about 10 to 200 ng/g. The present study will focus on the matrix effects and the possible loss of analyte associated with the evaporation of the fluosilicate salt, in relation with the accuracy and the reproducibility of the method. The benefits of using an internal standard will be assessed. Results will be presented from both model samples (ammonium fluoride contaminated with metallic salts) and real samples (silicon nitride films from a production tool). (author)

GeSn-on-insulator substrate formed by direct wafer bonding

Energy Technology Data Exchange (ETDEWEB)

Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

2016-07-11

GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

Mechanically flexible optically transparent porous mono-crystalline silicon substrate

KAUST Repository

Rojas, Jhonathan Prieto; Syed, Ahad A.; Hussain, Muhammad Mustafa

2012-01-01

For the first time, we present a simple process to fabricate a thin (≥5μm), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon <100> wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates. © 2012 IEEE.

High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

CERN Document Server

Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

2003-01-01

Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

Silicon-Rich Silicon Carbide Hole-Selective Rear Contacts for Crystalline-Silicon-Based Solar Cells.

Science.gov (United States)

Nogay, Gizem; Stuckelberger, Josua; Wyss, Philippe; Jeangros, Quentin; Allebé, Christophe; Niquille, Xavier; Debrot, Fabien; Despeisse, Matthieu; Haug, Franz-Josef; Löper, Philipp; Ballif, Christophe

2016-12-28

The use of passivating contacts compatible with typical homojunction thermal processes is one of the most promising approaches to realizing high-efficiency silicon solar cells. In this work, we investigate an alternative rear-passivating contact targeting facile implementation to industrial p-type solar cells. The contact structure consists of a chemically grown thin silicon oxide layer, which is capped with a boron-doped silicon-rich silicon carbide [SiC x (p)] layer and then annealed at 800-900 °C. Transmission electron microscopy reveals that the thin chemical oxide layer disappears upon thermal annealing up to 900 °C, leading to degraded surface passivation. We interpret this in terms of a chemical reaction between carbon atoms in the SiC x (p) layer and the adjacent chemical oxide layer. To prevent this reaction, an intrinsic silicon interlayer was introduced between the chemical oxide and the SiC x (p) layer. We show that this intrinsic silicon interlayer is beneficial for surface passivation. Optimized passivation is obtained with a 10-nm-thick intrinsic silicon interlayer, yielding an emitter saturation current density of 17 fA cm -2 on p-type wafers, which translates into an implied open-circuit voltage of 708 mV. The potential of the developed contact at the rear side is further investigated by realizing a proof-of-concept hybrid solar cell, featuring a heterojunction front-side contact made of intrinsic amorphous silicon and phosphorus-doped amorphous silicon. Even though the presented cells are limited by front-side reflection and front-side parasitic absorption, the obtained cell with a V oc of 694.7 mV, a FF of 79.1%, and an efficiency of 20.44% demonstrates the potential of the p + /p-wafer full-side-passivated rear-side scheme shown here.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

Science.gov (United States)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

Flexible Thermoelectric Generators on Silicon Fabric

KAUST Repository

Sevilla, Galo T.

2012-11-01

In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

International Nuclear Information System (INIS)

Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

2000-01-01

Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

Science.gov (United States)

Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

2018-05-01

An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

Wafer integrated micro-scale concentrating photovoltaics

Science.gov (United States)

Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

2017-09-01

Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

Effect of silicon solar cell processing parameters and crystallinity on mechanical strength

Energy Technology Data Exchange (ETDEWEB)

Popovich, V.A.; Yunus, A.; Janssen, M.; Richardson, I.M. [Delft University of Technology, Department of Materials Science and Engineering, Delft (Netherlands); Bennett, I.J. [Energy Research Centre of the Netherlands, Solar Energy, PV Module Technology, Petten (Netherlands)

2011-01-15

Silicon wafer thickness reduction without increasing the wafer strength leads to a high breakage rate during subsequent handling and processing steps. Cracking of solar cells has become one of the major sources of solar module failure and rejection. Hence, it is important to evaluate the mechanical strength of solar cells and influencing factors. The purpose of this work is to understand the fracture behavior of silicon solar cells and to provide information regarding the bending strength of the cells. Triple junctions, grain size and grain boundaries are considered to investigate the effect of crystallinity features on silicon wafer strength. Significant changes in fracture strength are found as a result of metallization morphology and crystallinity of silicon solar cells. It is observed that aluminum paste type influences the strength of the solar cells. (author)

I-line stepper based overlay evaluation method for wafer bonding applications

Science.gov (United States)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

Design and development of wafer-level near-infrared micro-camera

Science.gov (United States)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Haldar, Pradeep; Dhar, Nibir K.; Lewis, Jay S.; Wijewarnasuriya, Priyalal; Puri, Yash R.; Sood, Ashok K.

2015-08-01

SiGe offers a low-cost alternative to conventional infrared sensor material systems such as InGaAs, InSb, and HgCdTe for developing near-infrared (NIR) photodetector devices that do not require cooling and can offer high bandwidths and responsivities. As a result of the significant difference in thermal expansion coefficients between germanium and silicon, tensile strain incorporated into Ge epitaxial layers deposited on Si utilizing specialized growth processes can extend the operational range of detection to 1600 nm and longer wavelengths. We have fabricated SiGe based PIN detector devices on 300 mm diameter Si wafers in order to take advantage of high throughput, large-area complementary metal-oxide semiconductor (CMOS) technology. This device fabrication process involves low temperature epitaxial deposition of Ge to form a thin p+ seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. An n+-Ge layer formed by ion implantation of phosphorus, passivating oxide cap, and then top copper contacts complete the PIN photodetector design. Various techniques including transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS) have been employed to characterize the material and structural properties of the epitaxial growth and fabricated detector devices. In addition, electrical characterization was performed to compare the I-V dark current vs. photocurrent response as well as the time and wavelength varying photoresponse properties of the fabricated devices, results of which are likewise presented.

CHARACTERIZATION OF THE ELECTROPHYSICAL PROPERTIES OF SILICON-SILICON DIOXIDE INTERFACE USING PROBE ELECTROMETRY METHODS

Directory of Open Access Journals (Sweden)

V. А. Pilipenko

2017-01-01

Full Text Available Introduction of submicron design standards into microelectronic industry and a decrease of the gate dielectric thickness raise the importance of the analysis of microinhomogeneities in the silicon-silicon dioxide system. However, there is very little to no information on practical implementation of probe electrometry methods, and particularly scanning Kelvin probe method, in the interoperational control of real semiconductor manufacturing process. The purpose of the study was the development of methods for nondestructive testing of semiconductor wafers based on the determination of electrophysical properties of the silicon-silicon dioxide interface and their spatial distribution over wafer’s surface using non-contact probe electrometry methods.Traditional C-V curve analysis and scanning Kelvin probe method were used to characterize silicon- silicon dioxide interface. The samples under testing were silicon wafers of KEF 4.5 and KDB 12 type (orientation <100>, diameter 100 mm.Probe electrometry results revealed uniform spatial distribution of wafer’s surface potential after its preliminary rapid thermal treatment. Silicon-silicon dioxide electric potential values were also higher after treatment than before it. This potential growth correlates with the drop in interface charge density. At the same time local changes in surface potential indicate changes in surface layer structure.Probe electrometry results qualitatively reflect changes of interface charge density in silicon-silicon dioxide structure during its technological treatment. Inhomogeneities of surface potential distribution reflect inhomogeneity of damaged layer thickness and can be used as a means for localization of interface treatment defects.

Surface Passivation for Silicon Heterojunction Solar Cells

NARCIS (Netherlands)

Deligiannis, D.

2017-01-01

Silicon heterojunction solar cells (SHJ) are currently one of the most promising solar cell technologies in the world. The SHJ solar cell is based on a crystalline silicon (c-Si) wafer, passivated on both sides with a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer. Subsequently, p-type

Stabilisation of a thin crystalline Si wafer solar cell using glass substrate; Duenne kristalline Silizium Wafer-Solarzelle mit Glastraeger stabilisiert

Energy Technology Data Exchange (ETDEWEB)

Muehlbauer, Maria

2009-07-01

An attempt was made to stabilise ultrathin crystalline silicon wafers (< 100 {mu}m) by a support material (BOROFLOAT33 by Schott Glas). It was found that the total serial resistance results mainly from the specific resistance of the back contact, and that especially the ultrathin solar cells have high recombination in the back. The ultrathin Si wafers also are slightly corrugated, which results in uneven joining of the Si wafer with the glass support. For optimisation, the solar cells of this specific types, with different thicknesses, were modelled in the one-dimensional simulation code PC1D, including all material-specific and electric properties. It was found that a slight reduction of the serial resistance will be enough for a significant improvement of the efficiency of the stabilized solar cell. With this knowledge, selective optimisation of the stabilised solar cells was possible, with the following results: 1. The improved temperature-time profile of the RTP step will improve the solar cell parameters for all Si thicknesses, which is assumed to be the result of better quality of the Al/Si back contact. 2. Thicker aluminium layers improved passivation on the back of solar cells with a thickness of 300 {mu}m and 120 {mu}m. In thinner stabilised solar cells, this measure resulted in enhanced formation of shunts and did not reduce the recombination rate on the back of the solar cell. 3. An additional optimisation step was the introduction of the so-called 'combined method' in which part of the aluminium layer is replaced by silkscreen paste. This combination, with adequate preparation, ensures uniform joining of the ultrathin silicon to the glass carrier. The resulting intermediate layers are highly homogeneous and have good fill factors and current densities for thin solar cells with a si thickness of 60 {mu}m. A decisive argument for the combined method is its near-100% reproducibility. [German] Ziel dieser Arbeit ist es sehr duenne kristalline

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

Science.gov (United States)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

International Nuclear Information System (INIS)

Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

2013-01-01

This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

Directory of Open Access Journals (Sweden)

Nigel T. Maidment

2008-08-01

Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

Physical mechanisms of Cu-Cu wafer bonding

International Nuclear Information System (INIS)

Rebhan, B.

2014-01-01

Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

Low temperature sacrificial wafer bonding for planarization after very deep etching

NARCIS (Netherlands)

Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

1994-01-01

A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

Silicon Nanowire Fabrication Using Edge and Corner Lithography

NARCIS (Netherlands)

Yagubizade, H.; Berenschot, Johan W.; Jansen, Henricus V.; Elwenspoek, Michael Curt; Tas, Niels Roelof

2010-01-01

This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features

Pulsed Laser Interactions with Silicon Nano structures in Emitter Formation

International Nuclear Information System (INIS)

Huat, V.L.C.; Leong, C.S.; Kamaruzzaman Sopian, Saleem Hussain Zaidi

2015-01-01

Silicon wafer thinning is now approaching fundamental limits for wafer thickness owing to thermal expansion mismatch between Al and Si, reduced yields in wet-chemical processing as a result of fragility, and reduced optical absorption. An alternate manufacturing approach is needed to eliminate current manufacturing issues. In recent years, pulsed lasers have become readily available and costs have been significantly reduced. Pulsed laser interactions with silicon, in terms of micromachining, diffusions, and edge isolation, are well known, and have become industrial manufacturing tools. In this paper, pulsed laser interactions with silicon nano structures were identified as the most desirable solution for the fundamental limitations discussed above. Silicon nano structures have the capability for extremely high absorption that significantly reduces requirements for laser power, as well as thermal shock to the thinner wafer. Laser-assisted crystallization, in the presence of doping materials, leads to nano structure profiles that are highly desirable for sunlight absorption. The objective of this paper is the replacement of high temperature POCl_3 diffusion by laser-assisted phosphorus layers. With these improvements, complete low-temperature processing of thinner wafers was achievable with 3.7 % efficiency. Two-dimensional laser scanning was proved to be able to form uniformly annealed surfaces with higher fill factor and open-circuit voltage. (author)

Fabrication of a silicon oxide stamp by edge lithography reinforced with silicon nitride for nanoimprint lithography

NARCIS (Netherlands)

Zhao, Yiping; Berenschot, Johan W.; de Boer, M.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

2008-01-01

The fabrication of a stamp reinforced with silicon nitride is presented for its use in nanoimprint lithography. The fabrication process is based on edge lithography using conventional optical lithography and wet anisotropic etching of 110 silicon wafers. SiO2 nano-ridges of 20 nm in width were

The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

International Nuclear Information System (INIS)

Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

2004-01-01

We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

Science.gov (United States)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

Material Properties of Laser-Welded Thin Silicon Foils

Directory of Open Access Journals (Sweden)

M. T. Hessmann

2013-01-01

Full Text Available An extended monocrystalline silicon base foil offers a great opportunity to combine low-cost production with high efficiency silicon solar cells on a large scale. By overcoming the area restriction of ingot-based monocrystalline silicon wafer production, costs could be decreased to thin film solar cell range. The extended monocrystalline silicon base foil consists of several individual thin silicon wafers which are welded together. A comparison of three different approaches to weld 50 μm thin silicon foils is investigated here: (1 laser spot welding with low constant feed speed, (2 laser line welding, and (3 keyhole welding. Cross-sections are prepared and analyzed by electron backscatter diffraction (EBSD to reveal changes in the crystal structure at the welding side after laser irradiation. The treatment leads to the appearance of new grains and boundaries. The induced internal stress, using the three different laser welding processes, was investigated by micro-Raman analysis. We conclude that the keyhole welding process is the most favorable to produce thin silicon foils.

High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

International Nuclear Information System (INIS)

Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

2006-01-01

A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

Non-catalytic direct synthesis of graphene on Si (111) wafers by using inductively-coupled plasma chemical vapor deposition

Science.gov (United States)

Hwang, Sung Won; Shin, Hyunho; Lee, Bongsoo; Choi, Suk-Ho

2016-08-01

We employ inductively-coupled plasma chemical vapor deposition for non-catalytic growth of graphene on a Si (111) wafer or glass substrate, which is useful for practical device applications of graphene without transfer processes. At a RF power (P) of 500 W under C2H2 flow, defect-free 3 ˜ 5-layer graphene is grown on Si (111) wafers, but on glass substrate, the layer is thicker and defective, as characterized by Raman spectroscopy and electron microscopy. The graphene is produced on Si (111) for P down to 190 W whereas it is almost not formed on glass for P < 250 W, possibly resulting from the weak catalytic-reaction-like effect on glass. These results are discussed based on possible growth mechanisms.

Modification of the properties of porous silicon on adsorption of iodine molecules

International Nuclear Information System (INIS)

Vorontsov, A. S.; Osminkina, L. A.; Tkachenko, A. E.; Konstantinova, E. A.; Elenskii, V. G.; Timoshenko, V. Yu.; Kashkarov, P. K.

2007-01-01

Infrared spectroscopy and electron spin resonance measurements are used to study the properties of porous silicon layers on adsorption of the I 2 iodine molecules. The layers are formed on the p-an n-Si single-crystal wafers. It is established that, in the atmosphere of I 2 molecules, the charge-carrier concentration in the layers produced on the p-type wafers can be noticeably increased: the concentration of holes can attain values on the order of ∼10 18 -10 19 cm -3 . In porous silicon layers formed on the n-type wafers, the adsorption-induced inversion of the type of charge carriers and the partial substitution of silicon-hydrogen bonds by silicon-iodine bonds are observed. A decrease in the concentration of surface paramagnetic defects, P b centers, is observed in the samples with adsorbed iodine. The experimental data are interpreted in the context of the model in which it is assumed that both deep and shallow acceptor states are formed at the surface of silicon nanocrystals upon the adsorption of I 2 molecules

Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

International Nuclear Information System (INIS)

Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

2013-01-01

The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

Report on achievements in fiscal 1999. Development of energy usage rationalizing silicon manufacturing process (Development of manufacturing technology for mass production of silicon for solar cells); 1999 nendo energy shiyo gorika silicon seizo process kaihatsu seika hokokusho. Taiyo denchiyo silicon ryosanka seizo gijutsu no kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

Discussions were given on manufacture of raw material silicon for solar cells with regard to boron removal, solidification, finishing and refining of metallic impurities, refining of unutilized silicon scraps, and making them into wafers and solar cells after refining. This paper summarizes the achievements in fiscal 1999. With regard to purity deterioration due to contamination by boron containing silica powder generated during the boron removal in the manufacturing process, the facilities were modified resulting in the reduction thereof to 0.04 ppmw or less. Regarding the repetitive use of boron removing crucibles, the experiment identified the possibility of using them for more than three times. In trial fabrication of samples by using the solidification refining and cast integrated process, ingots of 550 mm square and about 300 mm high were obtained, which were sliced into 10-cm square materials for use as wafers. Measurement of the conversion efficiency has resulted in 13% or more which is almost equivalent in the center and edges of the ingot. It was revealed that solar cell wafers may be fabricated by using this process, which can use either the p-type low-resistance silicon scraps or the metallic silicon as the starting material. (NEDO)

Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

NARCIS (Netherlands)

Popovich, V.A.

2013-01-01

Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

In-line high-rate evaporation of aluminum for the metallization of silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Mader, Christoph Paul

2012-07-11

This work focuses on the in-line high-rate evaporation of aluminum for contacting rear sides of silicon solar cells. The substrate temperature during the deposition process, the wafer bow after deposition, and the electrical properties of evaporated contacts are investigated. Furthermore, this work demonstrates for the first time the formation of aluminum-doped silicon regions by the in-line high-rate evaporation of aluminum without any further temperature treatment. The temperature of silicon wafers during in-line high-rate evaporation of aluminum is investigated in this work. The temperatures are found to depend on the wafer thickness W, the aluminum layer thickness d, and on the wafer emissivity {epsilon}. Two-dimensional finite-element simulations reproduce the measured peak temperatures with an accuracy of 97%. This work also investigates the wafer bow after in-line high-rate evaporation and shows that the elastic theory overestimates the wafer bow of planar Si wafers. The lower bow is explained with plastic deformation in the Al layer. Due to the plastic deformation only the first 79 K in temperature decrease result in a bow formation. Furthermore the electrical properties of evaporated point contacts are examined in this work. Parameterizations for the measured saturation currents of contacted p-type Si wafers and of contacted boron-diffused p{sup +}-type layers are presented. The contact resistivity of the deposited Al layers to silicon for various deposition processes and silicon surface concentrations are presented and the activation energy of the contact formation is determined. The measured saturation current densities and contact resistivities of the evaporated contacts are used in one-dimensional numerical Simulations and the impact on energy conversion efficiency of replacing a screen-printed rear side by an evaporated rear side is presented. For the first time the formation of aluminum-doped p{sup +}-type (Al-p{sup +}) silicon regions by the in

Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

International Nuclear Information System (INIS)

Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

2010-01-01

This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

International Nuclear Information System (INIS)

Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

2009-01-01

Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

Method of producing buried porous silicon-geramanium layers in monocrystalline silicon lattices

Science.gov (United States)

Fathauer, Robert W. (Inventor); George, Thomas (Inventor); Jones, Eric W. (Inventor)

1997-01-01

Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si--Ge layers followed by patterning into mesa structures. The mesa structures are stain etched resulting in porosification of the Si--Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si--Ge layers produced in a similar manner emitted visible light at room temperature.

Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

Science.gov (United States)

Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

2017-06-01

In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

International Nuclear Information System (INIS)

Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

2004-01-01

Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Science and technology of plasma activated direct wafer bonding

Science.gov (United States)

Roberds, Brian Edward

This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

Science.gov (United States)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

Science.gov (United States)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca

2015-09-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

2015-01-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Micro-spectroscopy on silicon wafers and solar cells

Directory of Open Access Journals (Sweden)

Gundel Paul

2011-01-01

Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

Manipulation of polystyrene nanoparticles on a silicon wafer in the peak force tapping mode in water: pH-dependent friction and adhesion force

Energy Technology Data Exchange (ETDEWEB)

Schiwek, Simon; Stark, Robert W., E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de; Dietz, Christian, E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany); Physics of Surfaces, Institute of Materials Science, Technische Universität Darmstadt, Alarich-Weiss-Str. 16, 64287 Darmstadt (Germany); Heim, Lars-Oliver [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany)

2015-03-14

The friction force between nanoparticles and a silicon wafer is a crucial parameter for cleaning processes in the semiconductor industry. However, little is known about the pH-dependency of the friction forces and the shear strength at the interface. Here, we push polystyrene nanoparticles, 100 nm in diameter, with the tip of an atomic force microscope and measure the pH-dependency of the friction, adhesion, and normal forces on a silicon substrate covered with a native silicon dioxide layer. The peak force tapping mode was applied to control the vertical force on these particles. We successively increased the applied load until the particles started to move. The main advantage of this technique over single manipulation processes is the achievement of a large number of manipulation events in short time and in a straightforward manner. Geometrical considerations of the interaction forces at the tip-particle interface allowed us to calculate the friction force and shear strength from the applied normal force depending on the pH of an aqueous solution. The results clearly demonstrated that particle removal should be performed with a basic solution at pH 9 because of the low interaction forces between particle and substrate.

Electroless porous silicon formation applied to fabrication of boron–silica–glass cantilevers

International Nuclear Information System (INIS)

Teva, J; Davis, Z J; Hansen, O

2010-01-01

This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5–1 mm 3 ) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing the etching rate and reproducibility of the etching. In addition to that, a study of the morphology of the pore that is obtained by this technique is presented. The results from the characterization of the process are applied to the fabrication of boron–silica–glass cantilevers that serve as a platform for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH solution

Increasing the efficiency of silicon heterojunction solar cells and modules by light soaking

KAUST Repository

Kobayashi, Eiji; De Wolf, Stefaan; Levrat, Jacques; Descoeudres, Antoine; Despeisse, Matthieu; Haug, Franz-Josef; Ballif, Christophe

2017-01-01

Silicon heterojunction solar cells use crystalline silicon (c-Si) wafers as optical absorbers and employ bilayers of doped/intrinsic hydrogenated amorphous silicon (a-Si:H) to form passivating contacts. Recently, we demonstrated that such solar

Femtosecond versus nanosecond laser machining: comparison of induced stresses and structural changes in silicon wafers

International Nuclear Information System (INIS)

Amer, M.S.; El-Ashry, M.A.; Dosser, L.R.; Hix, K.E.; Maguire, J.F.; Irwin, Bryan

2005-01-01

Laser micromachining has proven to be a very successful tool for precision machining and microfabrication with applications in microelectronics, MEMS, medical device, aerospace, biomedical, and defense applications. Femtosecond (FS) laser micromachining is usually thought to be of minimal heat-affected zone (HAZ) local to the micromachined feature. The assumption of reduced HAZ is attributed to the absence of direct coupling of the laser energy into the thermal modes of the material during irradiation. However, a substantial HAZ is thought to exist when machining with lasers having pulse durations in the nanosecond (NS) regime. In this paper, we compare the results of micromachining a single crystal silicon wafer using a 150-femtosecond and a 30-nanosecond lasers. Induced stress and amorphization of the silicon single crystal were monitored using micro-Raman spectroscopy as a function of the fluence and pulse duration of the incident laser. The onset of average induced stress occurs at lower fluence when machining with the femtosecond pulse laser. Induced stresses were found to maximize at fluence of 44 J cm -2 and 8 J cm -2 for nanosecond and femtosecond pulsed lasers, respectively. In both laser pulse regimes, a maximum induced stress is observed at which point the induced stress begins to decrease as the fluence is increased. The maximum induced stress was comparable at 2.0 GPa and 1.5 GPa for the two lasers. For the nanosecond pulse laser, the induced amorphization reached a plateau of approximately 20% for fluence exceeding 22 J cm -2 . For the femtosecond pulse laser, however, induced amorphization was approximately 17% independent of the laser fluence within the experimental range. These two values can be considered nominally the same within experimental error. For femtosecond laser machining, some effect of the laser polarization on the amount of induced stress and amorphization was also observed

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

Science.gov (United States)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Annual Subcontract Report, 1 October 2003--30 September 2004

Energy Technology Data Exchange (ETDEWEB)

Wohlgemuth, J.; Narayanan, M.

2005-03-01

The major objectives of this program are to continue the advancement of BP Solar polycrystalline silicon manufacturing technology. The program includes work in the following areas: Efforts in the casting area to increase ingot size, improve ingot material quality, and improve handling of silicon feedstock as it is loaded into the casting stations; developing wire saws to slice 100- m-thick silicon wafers on 290- m centers; developing equipment for demounting and subsequent handling of very thin silicon wafers; developing cell processes using 100- m-thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%; expanding existing in-line manufacturing data reporting systems to provide active process control; establishing a 50-MW (annual nominal capacity) green-field Mega-plant factory model template based on this new thin polycrystalline silicon technology; facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock.

Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

Science.gov (United States)

Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

2018-01-01

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

Excellent Silicon Surface Passivation Achieved by Industrial Inductively Coupled Plasma Deposited Hydrogenated Intrinsic Amorphous Silicon Suboxide

Directory of Open Access Journals (Sweden)

Jia Ge

2014-01-01

Full Text Available We present an alternative method of depositing a high-quality passivation film for heterojunction silicon wafer solar cells, in this paper. The deposition of hydrogenated intrinsic amorphous silicon suboxide is accomplished by decomposing hydrogen, silane, and carbon dioxide in an industrial remote inductively coupled plasma platform. Through the investigation on CO2 partial pressure and process temperature, excellent surface passivation quality and optical properties are achieved. It is found that the hydrogen content in the film is much higher than what is commonly reported in intrinsic amorphous silicon due to oxygen incorporation. The observed slow depletion of hydrogen with increasing temperature greatly enhances its process window as well. The effective lifetime of symmetrically passivated samples under the optimal condition exceeds 4.7 ms on planar n-type Czochralski silicon wafers with a resistivity of 1 Ωcm, which is equivalent to an effective surface recombination velocity of less than 1.7 cms−1 and an implied open-circuit voltage (Voc of 741 mV. A comparison with several high quality passivation schemes for solar cells reveals that the developed inductively coupled plasma deposited films show excellent passivation quality. The excellent optical property and resistance to degradation make it an excellent substitute for industrial heterojunction silicon solar cell production.

Electro-optical properties of dislocations in silicon and their possible application for light emitters

Energy Technology Data Exchange (ETDEWEB)

Arguirov, Tzanimir Vladimirov

2007-10-14

This thesis addresses the electro-optical properties of silicon, containing dislocations. The work demonstrates that dislocation specific radiation may provide a means for optical diagnostics of solar cell grade silicon. It provides insight into the mechanisms governing the dislocation recombination activity, their radiation, and how are they influenced by other defects present in silicon. We demonstrate that photoluminescence mapping is useful for monitoring the recombination activity in solar cell grade silicon and can be applied for identification of contaminants, based on their photoluminescence signatures. It is shown that the recombination at dislocations is strongly influenced by the presence of metals at the dislocation sites. The dislocation radiation activity correlates with their electrical activity. It is shown that the dislocation and band-to-band luminescence are essentially anti-correlated. {beta}FeSi{sub 2} precipitates, with a luminescence at 0.8 eV, were detected within the grains of block cast materials. They exhibit a characteristic feature of quantum dots, namely blinking. The second aspect of the thesis concerns the topic of silicon based light emitters for on-chip optical interconnects. The goal is an enhancement of sub-band-gap or band-to-band radiation by controlled formation of dislocation-rich areas in microelectronics-grade silicon as well as understanding of the processes governing such enhancement. For light emitters based on band-to-band emission it is shown, that internal quantum efficiency of nearly 2 % can be achieved, but the emission is essentially generated in the bulk of the wafer. On the other hand, light emitters utilizing the emission from dislocation-rich areas of a well localized wafer depth were explored. Three different methods for reproducible formation of a dislocation-rich region beneath the wafer surface were investigated and evaluated in view of their room temperature sub-band-gap radiation: (1) silicon implantation

Comparative Study on Electronic, Emission, Spontaneous Property of Porous Silicon in Different Solvents

Directory of Open Access Journals (Sweden)

M. Naziruddin Khan

2014-01-01

Full Text Available Luminescent porous silicon (Psi fabricated by simple chemical etching technique in different organic solvents was studied. By quantifying the silicon wafer piece, optical properties of the Psi in solutions were investigated. Observation shows that no photoluminescence light of Psi in all solvents is emitted. Morphology of Psi in different solvents indicates that the structure and distribution of Psi are differently observed. Particles are uniformly dispersive with the sizes around more or less 5–8 nm. The crystallographic plane and high crystalline nature of Psi is observed by selected area diffraction (SED and XRD. Electronic properties of Psi in solutions are influenced due to the variation of quantity of wafer and nature of solvent. Influence in band gaps of Psi calculated by Tauc’s method is obtained due to change of absorption edge of Psi in solvents. PL intensities are observed to be depending on quantity of silicon wafer, etched cross-section area on wafer surface. Effects on emission peaks and bands of Psi under temperature annealing are observed. The spontaneous signals of Psi measured under high power Pico second laser 355 nm source are significant, influenced by the nature of solvent, pumped energy, and quantity of Si wafer piece used in etching process.

Selective etching of n-type silicon in pn junction structure in hydrofluoric acid and its application in silicon nanowire fabrication

International Nuclear Information System (INIS)

Wang Huiquan; Jin Zhonghe; Zheng Yangming; Ma Huilian; Wang Yuelin; Li Tie

2008-01-01

Boron is selectively implanted on the surface of an n-type silicon wafer to form a p-type area surrounded by an n-type area. The wafer is then put into a buffered oxide etch solution. It is found that the n-type area can be selectively etched without illumination, with an etching rate lower than 1 nm min -1 , while the p-type area can be selectively etched under illumination with a much higher etching rate. The possible mechanism of the etching phenomenon is discussed. A simple fabrication process of silicon nanowires is proposed according to the above phenomenon. In this process only traditional micro-electromechanical system technology is used. Dimensions of the fabricated nanowire can be controlled well. A 50 nm wide and 50 nm thick silicon nanowire has been formed using this method

120 mm Single-crystalline perovskite and wafers: towards viable applications

Institute of Scientific and Technical Information of China (English)

Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

2017-01-01

As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75％ RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

Methods and mechanisms of gettering of silicon structures in the production of integrated circuits

Directory of Open Access Journals (Sweden)

Pilipenko V. A.

2013-05-01

Full Text Available Increasing the degree of integration of hardware components imposes more stringent requirements for the reduction of the concentration of contaminants and oxidation stacking faults in the original silicon wafers with its preservation in the IC manufacturing process cycle. This causes high relevance of the application of gettering in modern microelectronic technology. The existing methods of silicon wafers gettering and the mechanisms of their occurrence are considered.

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

Science.gov (United States)

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Multiproject wafers: not just for million-dollar mask sets

Science.gov (United States)

Morse, Richard D.

2003-06-01

With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

Science.gov (United States)

Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

2011-01-01

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

Nanopatterned Silicon Substrate Use in Heterojunction Thin Film Solar Cells Made by Magnetron Sputtering

Directory of Open Access Journals (Sweden)

Shao-Ze Tseng

2014-01-01

Full Text Available This paper describes a method for fabricating silicon heterojunction thin film solar cells with an ITO/p-type a-Si : H/n-type c-Si structure by radiofrequency magnetron sputtering. A short-circuit current density and efficiency of 28.80 mA/cm2 and 8.67% were achieved. Novel nanopatterned silicon wafers for use in cells are presented. Improved heterojunction cells are formed on a nanopatterned silicon substrate that is prepared with a self-assembled monolayer of SiO2 nanospheres with a diameter of 550 nm used as an etching mask. The efficiency of the nanopattern silicon substrate heterojunction cells was 31.49% greater than that of heterojunction cells on a flat silicon wafer.

Serial section scanning electron microscopy (S3EM) on silicon wafers for ultra-structural volume imaging of cells and tissues.

Science.gov (United States)

Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

2012-01-01

High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3)EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3) volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3)EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3)EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

Directory of Open Access Journals (Sweden)

Heinz Horstmann

Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

Directory of Open Access Journals (Sweden)

Liu Haijun

2015-12-01

Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

A simple chemical method for the separation of phosphorus interfering the trace element determinations by neutron activation analysis in high doped silicon wafers

International Nuclear Information System (INIS)

Wagler, H.; Flachowsky, J.

1986-01-01

Neutron activation analysis is one of the most available method for the determination of trace elements, but in the case of P-doped silicon wafers the 32 P-activity interferes the gamma spectrometry. It is not possible to determine the trace elements without chemical manipulations. On the other hand, time consuming chemical separations should be avoided. Therefore, a simple and rapid P-separation method has to be developed, in which the following twelve trace elements should be taken into consideration: Ag, As, Au, Co, Cr, Cu, Fe, Mo, Na, Sb, W, and Zn. After acid oxidative dissolution of the activated sample, P is present as phosphate ion. The phosphate ion is removed by precipitation as BiPO 4 . (author)

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

Science.gov (United States)

Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

2018-05-01

Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

Directory of Open Access Journals (Sweden)

Zhiwei Zhang

2018-05-01

Full Text Available Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young’s modulus, ultimate tensile strength (UTS, and strain at fracture is observed.

Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

International Nuclear Information System (INIS)

Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

2011-01-01

This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

Alternative method for steam generation for thermal oxidation of silicon

Science.gov (United States)

Spiegelman, Jeffrey J.

2010-02-01

Thermal oxidation of silicon is an important process step in MEMS device fabrication. Thicker oxide layers are often used as structural components and can take days or weeks to grow, causing high gas costs, maintenance issues, and a process bottleneck. Pyrolytic steam, which is generated from hydrogen and oxygen combustion, was the default process, but has serious drawbacks: cost, safety, particles, permitting, reduced growth rate, rapid hydrogen consumption, component breakdown and limited steam flow rates. Results from data collected over a 24 month period by a MEMS manufacturer supports replacement of pyrolytic torches with RASIRC Steamer technology to reduce process cycle time and enable expansion previously limited by local hydrogen permitting. Data was gathered to determine whether Steamers can meet or exceed pyrolytic torch performance. The RASIRC Steamer uses de-ionized water as its steam source, eliminating dependence on hydrogen and oxygen. A non-porous hydrophilic membrane selectively allows water vapor to pass. All other molecules are greatly restricted, so contaminants in water such as dissolved gases, ions, total organic compounds (TOC), particles, and metals can be removed in the steam phase. The MEMS manufacturer improved growth rate by 7% over the growth range from 1μm to 3.5μm. Over a four month period, wafer uniformity, refractive index, wafer stress, and etch rate were tracked with no significant difference found. The elimination of hydrogen generated a four-month return on investment (ROI). Mean time between failure (MTBF) was increased from 3 weeks to 32 weeks based on three Steamers operating over eight months.

Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

International Nuclear Information System (INIS)

Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

2002-01-01

Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

Advances in Contactless Silicon Defect and Impurity Diagnostics Based on Lifetime Spectroscopy and Infrared Imaging

Directory of Open Access Journals (Sweden)

Jan Schmidt

2007-01-01

Full Text Available This paper gives a review of some recent developments in the field of contactless silicon wafer characterization techniques based on lifetime spectroscopy and infrared imaging. In the first part of the contribution, we outline the status of different lifetime spectroscopy approaches suitable for the identification of impurities in silicon and discuss—in more detail—the technique of temperature- and injection-dependent lifetime spectroscopy. The second part of the paper focuses on the application of infrared cameras to analyze spatial inhomogeneities in silicon wafers. By measuring the infrared signal absorbed or emitted from light-generated free excess carriers, high-resolution recombination lifetime mappings can be generated within seconds to minutes. In addition, mappings of non-recombination-active trapping centers can be deduced from injection-dependent infrared lifetime images. The trap density has been demonstrated to be an important additional parameter in the characterization and assessment of solar-grade multicrystalline silicon wafers, as areas of increased trap density tend to deteriorate during solar cell processing.

Laser shock ignition of porous silicon based nano-energetic films

International Nuclear Information System (INIS)

Plummer, A.; Gascooke, J.; Shapter, J.; Kuznetsov, V. A.; Voelcker, N. H.

2014-01-01

Nanoporous silicon films on a silicon wafer were loaded with sodium perchlorate and initiated using illumination with infrared laser pulses to cause laser thermal ignition and laser-generated shock waves. Using Photon Doppler Velocimetry, it was determined that these waves are weak stress waves with a threshold intensity of 131 MPa in the silicon substrate. Shock generation was achieved through confinement of a plasma, generated upon irradiation of an absorptive paint layer held against the substrate side of the wafer. These stress waves were below the threshold required for sample fracturing. Exploiting either the laser thermal or laser-generated shock mechanisms of ignition may permit use of pSi energetic materials in applications otherwise precluded due to their environmental sensitivity

Laser shock ignition of porous silicon based nano-energetic films

Energy Technology Data Exchange (ETDEWEB)

Plummer, A.; Gascooke, J.; Shapter, J. [School of Chemical and Physical Sciences, Flinders University, 5042, Bedford Park (Australia); Centre of Expertise in Energetic Materials (CEEM), Bedford Park (Australia); Kuznetsov, V. A., E-mail: nico.voelcker@unisa.edu.au, E-mail: Valerian.Kuznetsov@dsto.defence.gov.au [School of Chemical and Physical Sciences, Flinders University, 5042, Bedford Park (Australia); Centre of Expertise in Energetic Materials (CEEM), Bedford Park (Australia); Weapons and Combat Systems Division, Defence Science and Technology Organisation, Edinburgh 5111 (Australia); Voelcker, N. H., E-mail: nico.voelcker@unisa.edu.au, E-mail: Valerian.Kuznetsov@dsto.defence.gov.au [Mawson Institute, University of South Australia, 5095, Mawson Lakes (Australia)

2014-08-07

Nanoporous silicon films on a silicon wafer were loaded with sodium perchlorate and initiated using illumination with infrared laser pulses to cause laser thermal ignition and laser-generated shock waves. Using Photon Doppler Velocimetry, it was determined that these waves are weak stress waves with a threshold intensity of 131 MPa in the silicon substrate. Shock generation was achieved through confinement of a plasma, generated upon irradiation of an absorptive paint layer held against the substrate side of the wafer. These stress waves were below the threshold required for sample fracturing. Exploiting either the laser thermal or laser-generated shock mechanisms of ignition may permit use of pSi energetic materials in applications otherwise precluded due to their environmental sensitivity.

Silicon heterojunction solar cell passivation in combination with nanocrystalline silicon oxide emitters

NARCIS (Netherlands)

Gatz, H.A.; Rath, J.K.; Verheijen, M.A.; Kessels, W.M.M.; Schropp, R.E.I.

2016-01-01

Silicon heterojunction solar cells (SHJ) are well known for their high efficiencies, enabled by their remarkably high open-circuit voltages (VOC). A key factor in achieving these values is a good passivation of the crystalline wafer interface. One of the restrictions during SHJ solar cell production

Nanostructured silicon ferromagnet collected by a permanent neodymium magnet.

Science.gov (United States)

Okuno, Takahisa; Thürmer, Stephan; Kanoh, Hirofumi

2017-11-30

Nanostructured silicon (N-Si) was prepared by anodic electroetching of p-type silicon wafers. The obtained magnetic particles were separated by a permanent neodymium magnet as a magnetic nanostructured silicon (mN-Si). The N-Si and mN-Si exhibited different magnetic properties: the N-Si exhibited ferromagnetic-like behaviour, whereas the mN-Si exhibited superparamagnetic-like behaviour.

Silicon Nanowire Field-effect Chemical Sensor

OpenAIRE

Chen, S.

2011-01-01

This thesis describes the work that has been done on the project “Design and optimization of silicon nanowire for chemical sensing‿, including Si-NW fabrication, electrical/electrochemical modeling, the application as ISFET, and the build-up of Si- NW/LOC system for automatic sample delivery. A novel top-down fabrication technique was presented for single-crystal Si-NW fabrication realized with conventional microfabrication technique. High quality triangular Si-NWs were made with high wafer-s...

Silicon on insulator self-aligned transistors

Science.gov (United States)

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

The impact of silicon feedstock on the PV module cost

NARCIS (Netherlands)

del Coso, G.; del Cañizo, C.; Sinke, W.C.

2010-01-01

The impact of the use of new (solar grade) silicon feedstock materials on the manufacturing cost of wafer-based crystalline silicon photovoltaic modules is analyzed considering effects of material cost, efficiency of utilisation, and quality. Calculations based on data provided by European industry

Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Annual Subcontract Report, 1 April 2002--30 September 2003 (Revised)

Energy Technology Data Exchange (ETDEWEB)

Wohlgemuth, J.; Shea, S. P.

2004-04-01

The goal of BP Solar's Crystalline PVMaT program is to improve the present polycrystalline silicon manufacturing facility to reduce cost, improve efficiency, and increase production capacity. Key components of the program are: increasing ingot size; improving ingot material quality; improving material handling; developing wire saws to slice 100 ..mu..m thick silicon wafers on 200 ..mu..m centers; developing equipment for demounting and subsequent handling of very thin silicon wafers; developing cell processes using 100 ..mu..m thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%; expanding existing in-line manufacturing data reporting systems to provide active process control; establishing a 50 MW (annual nominal capacity) green-field Mega plant factory model template based on this new thin polycrystalline silicon technology; and facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock.

Development of Novel Front Contract Pastes for Crystalline Silicon Solar Cells

Energy Technology Data Exchange (ETDEWEB)

Duty, C.; Jellison, D. G.E. P.; Joshi, P.

2012-04-05

In order to improve the efficiencies of silicon solar cells, paste to silicon contact formation mechanisms must be more thoroughly understood as a function of paste chemistry, wafer properties and firing conditions. Ferro Corporation has been involved in paste development for over 30 years and has extensive expertise in glass and paste formulations. This project has focused on the characterization of the interface between the top contact material (silver paste) and the underlying silicon wafer. It is believed that the interface between the front contact silver and the silicon wafer plays a dominant role in the electrical performance of the solar cell. Development of an improved front contact microstructure depends on the paste chemistry, paste interaction with the SiNx, and silicon (“Si”) substrate, silicon sheet resistivity, and the firing profile. Typical front contact ink contains silver metal powders and flakes, glass powder and other inorganic additives suspended in an organic medium of resin and solvent. During fast firing cycles glass melts, wets, corrodes the SiNx layer, and then interacts with underlying Si. Glass chemistry is also a critical factor in the development of an optimum front contact microstructure. Over the course of this project, several fundamental characteristics of the Ag/Si interface were documented, including a higher-than-expected distribution of voids along the interface, which could significantly impact electrical conductivity. Several techniques were also investigated for the interfacial analysis, including STEM, EDS, FIB, EBSD, and ellipsometry.

Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Final Subcontract Report, 1 April 2002--28 February 2006

Energy Technology Data Exchange (ETDEWEB)

Wohlgemuth, J.; Narayanan, M.

2006-07-01

The major objectives of this program were to continue advances of BP Solar polycrystalline silicon manufacturing technology. The Program included work in the following areas. (1) Efforts in the casting area to increase ingot size, improve ingot material quality, and improve handling of silicon feedstock as it is loaded into the casting stations. (2) Developing wire saws to slice 100-..mu..m-thick silicon wafers on 290-..mu..m-centers. (3) Developing equipment for demounting and subsequent handling of very thin silicon wafers. (4) Developing cell processes using 100-..mu..m-thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%. (5) Expanding existing in-line manufacturing data reporting systems to provide active process control. (6) Establishing a 50-MW (annual nominal capacity) green-field Mega-plant factory model template based on this new thin polycrystalline silicon technology. (7) Facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock..

Porous silicon: Synthesis and optical properties

International Nuclear Information System (INIS)

Naddaf, M.; Awad, F.

2006-01-01

Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

Porous silicon: Synthesis and optical properties

International Nuclear Information System (INIS)

Naddaf, M.; Awad, F.

2006-06-01

Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

International Nuclear Information System (INIS)

Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

Tunnel Oxides Formed by Field-Induced Anodisation for Passivated Contacts of Silicon Solar Cells

Directory of Open Access Journals (Sweden)

Jingnan Tong

2018-02-01

Full Text Available Tunnel silicon oxides form a critical component for passivated contacts for silicon solar cells. They need to be sufficiently thin to allow carriers to tunnel through and to be uniform both in thickness and stoichiometry across the silicon wafer surface, to ensure uniform and low recombination velocities if high conversion efficiencies are to be achieved. This paper reports on the formation of ultra-thin silicon oxide layers by field-induced anodisation (FIA, a process that ensures uniform oxide thickness by passing the anodisation current perpendicularly through the wafer to the silicon surface that is anodised. Spectroscopical analyses show that the FIA oxides contain a lower fraction of Si-rich sub-oxides compared to wet-chemical oxides, resulting in lower recombination velocities at the silicon and oxide interface. This property along with its low temperature formation highlights the potential for FIA to be used to form low-cost tunnel oxide layers for passivated contacts of silicon solar cells.

Study of irradiation induced defects in silicon

International Nuclear Information System (INIS)

Pal, Gayatri; Sebastian, K.C.; Somayajulu, D.R.S.; Chintalapudi, S.N.

2000-01-01

Pure high resistivity (6000 ohm-cm) silicon wafers were recoil implanted with 1.8 MeV 111 In ions. As-irradiated wafers showed a 13 MHz quadrupole interaction frequency, which was not observed earlier. The annealing behaviour of these defects in the implanted wafers was studied between room temperature and 1073 K. At different annealing temperatures two more interaction frequencies corresponding to defect complexes D2 and D3 are observed. Even though the experimental conditions were different, these are identical to the earlier reported ones. Based on an empirical point charge model calculation, an attempt is made to identify the configuration of these defect complexes. (author)

Silicon Nanowires for Solar Thermal Energy Harvesting: an Experimental Evaluation on the Trade-off Effects of the Spectral Optical Properties.

Science.gov (United States)

Sekone, Abdoul Karim; Chen, Yu-Bin; Lu, Ming-Chang; Chen, Wen-Kai; Liu, Chia-An; Lee, Ming-Tsang

2016-12-01

Silicon nanowire possesses great potential as the material for renewable energy harvesting and conversion. The significantly reduced spectral reflectivity of silicon nanowire to visible light makes it even more attractive in solar energy applications. However, the benefit of its use for solar thermal energy harvesting remains to be investigated and has so far not been clearly reported. The purpose of this study is to provide practical information and insight into the performance of silicon nanowires in solar thermal energy conversion systems. Spectral hemispherical reflectivity and transmissivity of the black silicon nanowire array on silicon wafer substrate were measured. It was observed that the reflectivity is lower in the visible range but higher in the infrared range compared to the plain silicon wafer. A drying experiment and a theoretical calculation were carried out to directly evaluate the effects of the trade-off between scattering properties at different wavelengths. It is clearly seen that silicon nanowires can improve the solar thermal energy harnessing. The results showed that a 17.8 % increase in the harvest and utilization of solar thermal energy could be achieved using a silicon nanowire array on silicon substrate as compared to that obtained with a plain silicon wafer.

Modification of inkjet printer for polymer sensitive layer preparation on silicon-based gas sensors

Directory of Open Access Journals (Sweden)

Tianjian Li

2015-04-01

Full Text Available Inkjet printing is a versatile, low cost deposition technology with the capabilities for the localized deposition of high precision, patterned deposition in a programmable way, and the parallel deposition of a variety of materials. This paper demonstrates a new method of modifying the consumer inkjet printer to prepare polymer-sensitive layers on silicon wafer for gas sensor applications. A special printing tray for the modified inkjet printer to support a 4-inch silicon wafer is designed. The positioning accuracy of the deposition system is tested, based on the newly modified printer. The experimental data show that the positioning errors in the horizontal direction are negligibly small, while the positioning errors in the vertical direction rise with the increase of the printing distance of the wafer. The method for making suitable ink to be deposited to form the polymer-sensitive layer is also discussed. In the testing, a solution of 0.1 wt% polyvinyl alcohol (PVA was used as ink to prepare a sensitive layer with certain dimensions at a specific location on the surface of the silicon wafer, and the results prove the feasibility of the methods presented in this article.

Comparison of aggregation behaviors between ionic liquid-type imidazolium gemini surfactant [C12-4-C12im]Br2 and its monomer [C12mim]Br on silicon wafer.

Science.gov (United States)

Ao, Mingqi; Xu, Guiying; Pang, Jinyu; Zhao, Taotao

2009-09-01

The aggregation of ionic liquid-type imidazolium gemini surfactant [C(12)-4-C(12)im]Br(2) on silicon wafer, which is compared with its monomer [C(12)mim]Br, have been studied. AFM morphology images and contact angle measurements suggest that the aggregations of [C(12)-4-C(12)im]Br(2) and [C(12)mim]Br on silicon wafer follow different mechanisms. Below the critical surface aggregation concentrations (CSAC), both surfactant molecules are adsorbed with their hydrophobic tails facing the air. But above the CSAC, [C(12)-4-C(12)im]Br(2) molecules finally form a bilayer structure with hydrophilic head groups facing the air, whereas [C(12)mim]Br molecules form a multilayer structure, and with increasing its concentration, the layer numbers increase with the hydrophobic chains and hydrophilic head groups facing the air by turns. Besides, the watery wettability of [C(12)-4-C(12)im]Br(2)-treated silica surface is lower than that of [C(12)mim]Br at the concentration of 5.0 cmc, and the infrared spectroscopy suggests that the poorer watery wettability of [C(12)-4-C(12)im]Br(2) may be relative to the less-ordered packing of methylene chains inside the aggregate. These different aggregation behaviors for the two surfactants ascribe to the different molecular structures and electrostatic interactions. This work would have certain theoretical guidance meaning on the modification of solid surface.

Effects of laser fluence on silicon modification by four-beam laser interference

International Nuclear Information System (INIS)

Zhao, Le; Li, Dayou; Wang, Zuobin; Yue, Yong; Zhang, Jinjin; Yu, Miao; Li, Siwei

2015-01-01

This paper discusses the effects of laser fluence on silicon modification by four-beam laser interference. In this work, four-beam laser interference was used to pattern single crystal silicon wafers for the fabrication of surface structures, and the number of laser pulses was applied to the process in air. By controlling the parameters of laser irradiation, different shapes of silicon structures were fabricated. The results were obtained with the single laser fluence of 354 mJ/cm 2 , 495 mJ/cm 2 , and 637 mJ/cm 2 , the pulse repetition rate of 10 Hz, the laser exposure pulses of 30, 100, and 300, the laser wavelength of 1064 nm, and the pulse duration of 7–9 ns. The effects of the heat transfer and the radiation of laser interference plasma on silicon wafer surfaces were investigated. The equations of heat flow and radiation effects of laser plasma of interfering patterns in a four-beam laser interference distribution were proposed to describe their impacts on silicon wafer surfaces. The experimental results have shown that the laser fluence has to be properly selected for the fabrication of well-defined surface structures in a four-beam laser interference process. Laser interference patterns can directly fabricate different shape structures for their corresponding applications

Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

International Nuclear Information System (INIS)

Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

2015-01-01

Graphical abstract: - Highlights: • How Ag transfers F − to the adjacent Si atom was investigated and deduced by DFT at atomic scale. • Three-electrode CV tests proved the transferring function of Ag in the etching reaction. • Uniform SiNWAs were fabricated on unpolished silicon wafers with KOH pretreatment. - Abstract: Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F − ) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F − , smaller azimuth angle of F−Ag(T4)−Si, shorter bond length of F−Si compared with F−Ag. As F − was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF 4 when it bonded with enough F − while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F − to Si

Buried Porous Silicon-Germanium Layers in Monocrystalline Silicon Lattices

Science.gov (United States)

Fathauer, Robert W. (Inventor); George, Thomas (Inventor); Jones, Eric W. (Inventor)

1998-01-01

Monocrystalline semiconductor lattices with a buried porous semiconductor layer having different chemical composition is discussed and monocrystalline semiconductor superlattices with a buried porous semiconductor layers having different chemical composition than that of its monocrystalline semiconductor superlattice are discussed. Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si-Ge layers followed by patterning into mesa structures. The mesa structures are strain etched resulting in porosification of the Si-Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si-Ge layers produced in a similar manner emitted visible light at room temperature.

Combination of gettering and etching in multicrystalline silicon used in solar cells processing

International Nuclear Information System (INIS)

Dimassi, W.; Bouaicha, M.; Nouri, H.; Ben Nasrallah, S.; Bessais, B.

2006-01-01

Undesired impurities can be removed away from multicrystalline silicon (mc-Si) wafers by combining porous silicon (PS) formation and heat treatments. The gettering procedure used in this work is based on the formation of a PS film at both back and front sides of the mc-Si wafers, followed by a heat treatment. The latter was achieved in an infrared furnace at different temperatures and during various periods. We show that when the based material undergoes such a gettering, the electrical properties (short-circuit current, open-circuit voltage, serial and shunt resistances) and the electronic parameters (diffusion length and grain boundary recombination velocity) of the corresponding solar cells can be improved only if some regions of the wafers are etched. Compared to reference cells based on untreated wafers, the diffusion length and grain boundary recombination velocity of solar cells fabricated from gettered and etched samples was improved by about 30% and reduced by a factor of 10, respectively

Reducing the porosity and reflection loss of silicon nanowires by a sticky tape

International Nuclear Information System (INIS)

Liu, Junjun; Huang, Zhifeng

2015-01-01

Engineering the porosity of silicon nanowires (SiNWs) is of fundamental importance, and this work introduces a new method for doing so. Metal-assisted chemical etching (MACE) of heavily doped Si(100) creates mesoporous silicon nanowires (mp-SiNWs). mp-SiNWs are transferred from the MACE-treated wafer to a sticky tape, leaving residues composed of broken mp-SiNWs and a mesoporous Si layer on the wafer. Then the taped wafer is re-treated by MACE, without changing the etching conditions. The second MACE treatment generates mp-SiNWs that are less porous and longer than those generated by the first MACE treatment, which can be attributed to the difference in the surface topography at the beginning of the etching process. Less porous mp-SiNWs reduce optical scattering from the porous Si skeletons, and vertically protrude on the wafer without aggregation to facilitate optical trapping. Consequently, less porous mp-SiNWs effectively reduce ultraviolet-visible reflection loss. (paper)

Investigation of the morphology and electrical characteristics of FeSi2 quantum dots on silicon

International Nuclear Information System (INIS)

Dozsa, L.; Molnar, G.; Horvath, Zs.J.; Toth, A.L.; Gyulai, J.; Raineri, V.; Giannazzo, F.

2004-01-01

β-FeSi 2 quantum dots (QD) were grown by evaporating 2, 4 and 7 nm Fe onto Si(1 0 0) wafers and in situ annealed at 600 deg. C for 10 min. QDs were grown also by reactive deposition epitaxy (RDE) evaporating 2 nm Fe onto a 600 deg. C Si substrate and annealed further for 5 min. MIS structures were prepared by evaporating SiO x over the QDs and Al dots on the oxide. The SEM investigations show the density of the QDs is about 10 10 cm -2 in the 2 and 4 nm Fe samples, and it increases to about 3x10 11 cm -2 in the 7 nm Fe sample. The nanoscope investigation shows well resolved QDs only in the 7 nm Fe samples, but their density and size do not allow individual characterization of the QDs by scanning capacitance microscopic measurements. In the RDE samples the QDs are small and irregular, indicating the need for thicker Fe layer. Capacitance-voltage (C-V) measurements show point defects generated by silicidation which compensate the silicon doping (2x10 15 cm -3 ) in about 1 μm depth. C-V results show that in the RDE samples less point defect are generated, their concentration is lower than doping of the Si wafers. The electrical characteristics of MIS structures show that the room temperature deposited iron degrades the I-V characteristics, and induces leakage

Particle precipitation in connection with KOH etching of silicon

DEFF Research Database (Denmark)

Nielsen, Christian Bergenstof; Christensen, Carsten; Pedersen, Casper

2004-01-01

This paper considers the precipitation of iron oxide particles in connection with the KOH etching of cavities in silicon wafers. The findings presented in this paper suggest that the source to the particles is the KOH pellets used for making the etching solution. Experiments show that the precipi......This paper considers the precipitation of iron oxide particles in connection with the KOH etching of cavities in silicon wafers. The findings presented in this paper suggest that the source to the particles is the KOH pellets used for making the etching solution. Experiments show...... that the precipitation is independent of KOH etching time, but that the amount of deposited material varies with dopant type and dopant concentration. The experiments also suggest that the precipitation occurs when the silicon wafers are removed from the KOH etching solution and not during the etching procedure. When...... not removed, the iron oxide particles cause etch pits on the Si surface when later processed and exposed to phosphoric acid. It has been found that the particles can be removed in an HCl solution, but not completely in an H2SO4- H2O2 solution. The paper discusses the involved precipitation mechanism in terms...

Wafer-level manufacturing technology of glass microlenses

Science.gov (United States)

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Optical and passivating properties of hydrogenated amorphous silicon nitride deposited by plasma enhanced chemical vapour deposition for application on silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Wight, Daniel Nilsen

2008-07-01

Within this thesis, several important subjects related to the use of amorphous silicon nitride made by plasma enhanced chemical vapour deposition as an anti-reflective coating on silicon solar cells are presented. The first part of the thesis covers optical simulations to optimise single and double layer anti-reflective coatings with respect to optical performance when situated on a silicon solar cell. The second part investigates the relationship between important physical properties of silicon nitride films when deposited under different conditions. The optical simulations were either based on minimising the reflectance off a silicon nitride/silicon wafer stack or maximising the transmittance through the silicon nitride into the silicon wafer. The former method allowed consideration of the reflectance off the back surface of the wafer, which occurs typically at wavelengths above 1000 nm due to the transparency of silicon at these wavelengths. However, this method does not take into consideration the absorption occurring in the silicon nitride, which is negligible at low refractive indexes but quite significant when the refractive index increases above 2.1. For high-index silicon nitride films, the latter method is more accurate as it considers both reflectance and absorbance in the film to calculate the transmittance into the Si wafer. Both methods reach similar values for film thickness and refractive index for optimised single layer anti-reflective coatings, due to the negligible absorption occurring in these films. For double layer coatings, though, the reflectance based simulations overestimated the optimum refractive index for the bottom layer, which would have lead to excessive absorption if applied to real anti-reflective coatings. The experimental study on physical properties for silicon nitride films deposited under varying conditions concentrated on the estimation of properties important for its applications, such as optical properties, passivation

Innovative technologies for emitter formation of crystalline silicon solar cells using in-line diffusion; Innovative Technologien zur Emittererzeugung fuer kristalline Silizium-Solarzellen mittels Durchlaufdiffusion

Energy Technology Data Exchange (ETDEWEB)

Voyer, Catherine

2009-04-20

An in-line emitter formation process for crystalline silicon solar cells was developed. The wafers were coated at room temperature with dilute phosphoric acid (2.5 w/w% in water) using ultrasonic spraying and then heated up to temperatures around 900 C in a metal-contamination-free in-line furnace. In the first zones of the furnace, a phosphosilicate glass (PSG) is formed on the silicon surface and serves as the doping source. The PSG thickness was adjusted by varying the flow rate of dilute phosphoric acid to the spray nozzle and took on values appropriate for emitter formation, in the range of {proportional_to}40-120 nm. A surfactant mixture was added to the dilute phosphoric acid in order to obtain complete wetting of the silicon surface. The mixture, which was composed of a hydrocarbon surfactant and of a fluorosurfactant, achieved better wetting properties than would be possible when using only one of the two surfactants. The spray solution containing only the hydrocarbon surfactant achieved a faster drop flattening, while the spray solution containing only the fluorosurfactant achieved a lower static surface tension. The mixture allowed for a combination of these desired properties: The drops coalesced together sufficiently rapidly (before drying) on the silicon surface to form a complete dopant source liquid layer and this layer remains sufficiently homogeneous during the layer drying. The sprayed-on layer is thicker ({proportional_to}15 microns) than the height of the surface texture ({proportional_to}5-10 microns). The liquid strives for a state of equilibrium, a convex meniscus. The topography of the liquid surface at the time at which the increase in viscosity puts an end to the liquid flow is reflected in the topography of the PSG thickness. The corresponding variations in sheet resistance across a wafer are sufficiently small for solar cells. Furthermore, the liquid layer conforms itself, during the drying, to the surface texture on a microscopic scale

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

International Nuclear Information System (INIS)

Holland, S.E.

2000-01-01

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels

Optimization of Controllable Factors in the Aluminum Silicon Eutectic Paste and Rear Silicon Nitride Mono-Passivation Layer of PERC Solar Cells

Science.gov (United States)

Park, Sungeun; Park, Hyomin; Kim, Dongseop; Yang, JungYup; Lee, Dongho; Kim, Young-Su; Kim, Hyun-Jong; Suh, Dongchul; Min, Byoung Koun; Kim, Kyung Nam; Park, Se Jin; Kim, Donghwan; Lee, Hae-Seok; Nam, Junggyu; Kang, Yoonmook

2018-05-01

Passivated emitter and rear contact (PERC) is a promising technology owing to high efficiency can be achieved with p-type wafer and their easily applicable to existing lines. In case of using p-type mono wafer, 0.5-1% efficiency increase is expected with PERC technologies compared to existing Al BSF solar cells, while for multi-wafer solar cells it is 0.5-0.8%. We addressed the optimization of PERC solar cells using the Al paste. The paste was prepared from the aluminum-silicon alloy with eutectic composition to avoid the formation of voids that degrade the open-circuit voltage. The glass frit of the paste was changed to improve adhesion. Scanning electron microscopy revealed voids and local back surface field between the aluminum electrode and silicon base. We confirmed the conditions on the SiNx passivation layer for achieving higher efficiency and better adhesion for long-term stability. The cell characteristics were compared across cells containing different pastes. PERC solar cells with the Al/Si eutectic paste exhibited the efficiency of 19.6%.

Optimization of the Surface Structure on Black Silicon for Surface Passivation.

Science.gov (United States)

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-12-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al 2 O 3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH 4 OH/H 2 O 2 /H 2 O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Improvement of silicon direct bonding using surfaces activated by hydrogen plasma treatment

CERN Document Server

Choi, W B; Lee Jae Sik; Sung, M Y

2000-01-01

The plasma surface treatment, using hydrogen gas, of silicon wafers was studied as a pretreatment for silicon direct bonding. Chemical reactions of the hydrogen plasma with the surfaces were used for both surface activation and removal of surface contaminants. Exposure of the silicon wafers to the plasma formed an active oxide layer on the surface. This layer was hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposure time and power. The surface became smoother with shorter plasma exposure time and lower power. In addition, the plasma surface treatment was very efficient in removing the carbon contaminants on the silicon surface. The value of the initial surface energy, as estimated by using the crack propagation method, was 506 mJ/M sup 2 , which was up to about three times higher than the value for the conventional direct bonding method using wet chemical treatments.

Production of Solar Grade (SoG) Silicon by Refining Liquid Metallurgical Grade (MG) Silicon: Final Report, 19 April 2001; FINAL

International Nuclear Information System (INIS)

Khattack, C. P.; Joyce, D. B.; Schmid, F.

2001-01-01

This report summarizes the results of the developed technology for producing SoG silicon by upgrading MG silicon with a cost goal of$20/kg in large-scale production. A Heat Exchanger Method (HEM) furnace originally designed to produce multicrystalline ingots was modified to refine molten MG silicon feedstock prior to directional solidification. Based on theoretical calculations, simple processing techniques, such as gas blowing through the melt, reaction with moisture, and slagging have been used to remove B from molten MG silicon. The charge size was scaled up from 1 kg to 300 kg in incremental steps and effective refining was achieved. After the refining parameters were established, improvements to increase the impurity reduction rates were emphasized. With this approach, 50 kg of commercially available as-received MG silicon was processed for a refining time of about 13 hours. A half life of and lt;2 hours was achieved, and the B concentration was reduced to 0.3 ppma and P concentration to 10 ppma from the original values of 20 to 60 ppma, and all other impurities to and lt;0.1 ppma. Achieving and lt;1 ppma B by this simple refining technique is a breakthrough towards the goal of achieving low-cost SoG silicon for PV applications. While the P reduction process was being optimized, the successful B reduction process was applied to a category of electronics industry silicon scrap previously unacceptable for PV feedstock use because of its high B content (50-400 ppma). This material after refining showed that its B content was reduced by several orders of magnitude, to(approx)1 ppma (0.4 ohm-cm, or about 5x1016 cm-3). NREL's Silicon Materials Research team grew and wafered small and lt;100 and gt; dislocation-free Czochralski (Cz) crystals from the new feedstock material for diagnostic tests of electrical properties, C and O impurity levels, and PV performance relative to similar crystals grown from EG feedstock and commercial Cz wafers. The PV conversion

Silicon-micromachined microchannel plates

CERN Document Server

Beetz, C P; Steinbeck, J; Lemieux, B; Winn, D R

2000-01-01

Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of approx 0.5 to approx 25 mu m, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposite...

Organization of silicon nanocrystals by localized electrochemical etching

International Nuclear Information System (INIS)

Ayari-Kanoun, Asma; Drouin, Dominique; Beauvais, Jacques; Lysenko, Vladimir; Nychyporuk, Tetyana; Souifi, Abdelkader

2009-01-01

An approach to form a monolayer of organized silicon nanocrystals on a monocrystalline Si wafer is reported. Ordered arrays of nanoholes in a silicon nitride layer were obtained by combining electron beam lithography and plasma etching. Then, a short electrochemical etching current pulse led to formation of a single Si nanocrystal per each nanohole. As a result, high quality silicon nanocrystal arrays were formed with well controlled and reproducible morphologies. In future, this approach can be used to fabricate single electron devices.

Porous silicon carbide (SIC) semiconductor device

Science.gov (United States)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Temperature-dependent interface characteristic of silicon wafer bonding based on an amorphous germanium layer deposited by DC-magnetron sputtering

Science.gov (United States)

Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

2018-03-01

We report a near-bubble-free low-temperature silicon (Si) wafer bonding with a thin amorphous Ge (a-Ge) intermediate layer. The DC-magnetron-sputtered a-Ge film on Si is demonstrated to be extremely flat (RMS = 0.28 nm) and hydrophilic (contact angle = 3°). The effect of the post-annealing temperature on the surface morphology and crystallinity of a-Ge film at the bonded interface is systematically identified. The relationship among the bubble density, annealing temperature, and crystallinity of a-Ge film is also clearly clarified. The crystallization of a-Ge film firstly appears at the bubble region. More interesting feature is that the crystallization starts from the center of the bubbles and sprawls to the bubble edge gradually. The H2 by-product is finally absorbed by intermediate Ge layer with crystalline phase after post annealing. Moreover, the whole a-Ge film out of the bubble totally crystallizes when the annealing time increases. This Ge integration at the bubble region leads to the decrease of the bubble density, which in turn increases the bonding strength.

Silicon photonics: some remaining challenges

Science.gov (United States)

Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

2016-03-01

This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

Laser direct writing of oxide structures on hydrogen-passivated silicon surfaces

DEFF Research Database (Denmark)

Müllenborn, Matthias; Birkelund, Karen; Grey, Francois

1996-01-01

on amorphous and crystalline silicon surfaces in order to determine the depassivation mechanism. The minimum linewidth achieved is about 450 nm using writing speeds of up to 100 mm/s. The process is fully compatible with local oxidation of silicon by scanning probe lithography. Wafer-scale patterns can...

NTD Silicon; Product Characteristics, Main Uses and Growth Potential

International Nuclear Information System (INIS)

Hansen, M. G.; Bjorling, C. F.

2013-01-01

Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain

NTD Silicon; Product Characteristics, Main Uses and Growth Potential

Energy Technology Data Exchange (ETDEWEB)

Hansen, M. G.; Bjorling, C. F. [Topsil Semiconductor Materials A/S, Odense (Denmark)

2013-07-01

Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain.

Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

International Nuclear Information System (INIS)

Moslehi, M.M.; Davis, C.

1989-01-01

Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

Fabrication of micromirrors with pyramidal shape using anisotropic etching of silicon

OpenAIRE

Moktadir, Z.; Vijaya Prakash, G.; Trupke, M.; Koukharenko, E.; Kraft, M.; Baumberg, J.J.; Eriksson, S.; Hinds, E.A.

2005-01-01

Gold micro-mirrors have been formed in silicon in an inverted pyramidal shape. The pyramidal structures are created in the (100) surface of a silicon wafer by anisotropic etching in potassium hydroxide. High quality micro-mirrors are then formed by sputtering gold onto the smooth silicon (111) faces of the pyramids. These mirrors show great promise as high quality optical devices suitable for integration into MOEMS systems.

Single crystalline silicon solar cells with rib structure

Directory of Open Access Journals (Sweden)

Shuhei Yoshiba

2017-02-01

Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

Floating Silicon Method

Energy Technology Data Exchange (ETDEWEB)

Kellerman, Peter

2013-12-21

The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

Microscratch testing method for systematic evaluation of the adhesion of atomic layer deposited thin films on silicon

Energy Technology Data Exchange (ETDEWEB)

Kilpi, Lauri, E-mail: Lauri.Kilpi@vtt.fi; Ylivaara, Oili M. E.; Vaajoki, Antti; Puurunen, Riikka L.; Ronkainen, Helena [VTT Technical Research Centre of Finland Ltd., P.O. Box 1000, FI-02044 VTT (Finland); Malm, Jari [Department of Physics, University of Jyväskylä, P.O. Box 35, Jyväskylä 40014 (Finland); Sintonen, Sakari [Department of Micro- and Nanosciences, Aalto University School of Electrical Engineering, P.O. Box 13500, FI-00076 AALTO (Finland); Tuominen, Marko [ASM Microchemistry Oy, Pietari Kalmin katu 1 F 2, FIN-00560 Helsinki (Finland)

2016-01-15

The scratch test method is widely used for adhesion evaluation of thin films and coatings. Usual critical load criteria designed for scratch testing of coatings were not applicable to thin atomic layer deposition (ALD) films on silicon wafers. Thus, the bases for critical load evaluation were established and the critical loads suitable for ALD coating adhesion evaluation on silicon wafers were determined in this paper as L{sub CSi1}, L{sub CSi2}, L{sub CALD1}, and L{sub CALD2}, representing the failure points of the silicon substrate and the coating delamination points of the ALD coating. The adhesion performance of the ALD Al{sub 2}O{sub 3}, TiO{sub 2}, TiN, and TaCN+Ru coatings with a thickness range between 20 and 600 nm and deposition temperature between 30 and 410 °C on silicon wafers was investigated. In addition, the impact of the annealing process after deposition on adhesion was evaluated for selected cases. The tests carried out using scratch and Scotch tape test showed that the coating deposition and annealing temperature, thickness of the coating, and surface pretreatments of the Si wafer had an impact on the adhesion performance of the ALD coatings on the silicon wafer. There was also an improved load carrying capacity due to Al{sub 2}O{sub 3}, the magnitude of which depended on the coating thickness and the deposition temperature. The tape tests were carried out for selected coatings as a comparison. The results show that the scratch test is a useful and applicable tool for adhesion evaluation of ALD coatings, even when carried out for thin (20 nm thick) coatings.

Atomic and electronic structures of novel silicon surface structures

Energy Technology Data Exchange (ETDEWEB)

Terry, J.H. Jr.

1997-03-01

The modification of silicon surfaces is presently of great interest to the semiconductor device community. Three distinct areas are the subject of inquiry: first, modification of the silicon electronic structure; second, passivation of the silicon surface; and third, functionalization of the silicon surface. It is believed that surface modification of these types will lead to useful electronic devices by pairing these modified surfaces with traditional silicon device technology. Therefore, silicon wafers with modified electronic structure (light-emitting porous silicon), passivated surfaces (H-Si(111), Cl-Si(111), Alkyl-Si(111)), and functionalized surfaces (Alkyl-Si(111)) have been studied in order to determine the fundamental properties of surface geometry and electronic structure using synchrotron radiation-based techniques.

TEM investigation of aluminium containing precipitates in high aluminium doped silicon carbide

International Nuclear Information System (INIS)

Wong-Leung, J.; FitzGerald, J.D.

2002-01-01

Full text: Silicon carbide is a promising semiconductor material for applications in high temperature and high power devices. The successful growth of good quality epilayers in this material has enhanced its potential for device applications. As a novel semiconductor material, there is a need for studying its basic physical properties and the role of dopants in this material. In this study, silicon carbide epilayers were grown on 4H-SiC wafers of (0001) orientation with a miscut angle of 8 deg at a temperature of 1550 deg C. The epilayers contained regions of high aluminium doping well above the solubility of aluminium in silicon carbide. High temperature annealing of this material resulted in the precipitation of aluminium in the wafers. The samples were analysed by secondary ion mass spectrometry and transmission electron microscopy. Selected area diffraction studies show the presence of aluminium carbide and aluminium silicon carbide phases. Copyright (2002) Australian Society for Electron Microscopy Inc

Thin Single Crystal Silicon Solar Cells on Ceramic Substrates: November 2009 - November 2010

Energy Technology Data Exchange (ETDEWEB)

Kumar, A.; Ravi, K. V.

2011-06-01

In this program we have been developing a technology for fabricating thin (< 50 micrometres) single crystal silicon wafers on foreign substrates. We reverse the conventional approach of depositing or forming silicon on foreign substrates by depositing or forming thick (200 to 400 micrometres) ceramic materials on high quality single crystal silicon films ~ 50 micrometres thick. Our key innovation is the fabrication of thin, refractory, and self-adhering 'handling layers or substrates' on thin epitaxial silicon films in-situ, from powder precursors obtained from low cost raw materials. This 'handling layer' has sufficient strength for device and module processing and fabrication. Successful production of full sized (125 mm X 125 mm) silicon on ceramic wafers with 50 micrometre thick single crystal silicon has been achieved and device process flow developed for solar cell fabrication. Impurity transfer from the ceramic to the silicon during the elevated temperature consolidation process has resulted in very low minority carrier lifetimes and resulting low cell efficiencies. Detailed analysis of minority carrier lifetime, metals analysis and device characterization have been done. A full sized solar cell efficiency of 8% has been demonstrated.

Damage-free polishing of monocrystalline silicon wafers without chemical additives

International Nuclear Information System (INIS)

Biddut, A.Q.; Zhang, L.C.; Ali, Y.M.; Liu, Z.

2008-01-01

This investigation explores the possibility and identifies the mechanism of damage-free polishing of monocrystalline silicon without chemical additives. Using high resolution electron microscopy and contact mechanics, the study concludes that a damage-free polishing process without chemicals is feasible. All forms of damages, such as amorphous Si, dislocations and plane shifting, can be eliminated by avoiding the initiation of the β-tin phase of silicon during polishing. When using 50 nm abrasives, the nominal pressure to achieve damage-free polishing is 20 kPa

Silicon-micromachined microchannel plates

International Nuclear Information System (INIS)

Beetz, Charles P.; Boerstler, Robert; Steinbeck, John; Lemieux, Bryan; Winn, David R.

2000-01-01

Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of ∼0.5 to ∼25 μm, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposited or nucleated in the channels or the first strike surface. Results on resistivity, secondary emission and gain are presented

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

Science.gov (United States)

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

2013-12-03

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Fast determination of impurities in metallurgical grade silicon for photovoltaics by instrumental neutron activation analysis

International Nuclear Information System (INIS)

Hampel, J.; Boldt, F.M.; Gerstenberg, H.; Hampel, G.; Kratz, J.V.; Reber, S.; Wiehl, N.

2011-01-01

Standard wafer solar cells are made of near-semiconductor quality silicon. This high quality material makes up a significant part of the total costs of a solar module. Therefore, new concepts with less expensive so called solar grade silicon directly based on physiochemically upgraded metallurgical grade silicon are investigated. Metallurgical grade silicon contains large amounts of impurities, mainly transition metals like Fe, Cr, Mn, and Co, which degrade the minority carrier lifetime and thus the solar cell efficiency. A major reduction of the transition metal content occurs during the unidirectional crystallization due to the low segregation coefficient between the solid and liquid phase. A further reduction of the impurity level has to be done by gettering procedures applied to the silicon wafers. The efficiency of such cleaning procedures of metallurgical grade silicon is studied by instrumental neutron activation analysis (INAA). Small sized silicon wafers of approximately 200 mg with and without gettering step were analyzed. To accelerate the detection of transition metals in a crystallized silicon ingot, experiments of scanning whole vertical silicon columns with a diameter of approximately 1 cm by gamma spectroscopy were carried out. It was demonstrated that impurity profiles can be obtained in a comparably short time. Relatively constant transition metal ratios were found throughout an entire silicon ingot. This led to the conclusion that the determination of several metal profiles might be possible by the detection of only one 'leading element'. As the determination of Mn in silicon can be done quite fast compared to elements like Fe, Cr, and Co, it could be used as a rough marker for the overall metal concentration level. Thus, a fast way to determine impurities in photovoltaic silicon material is demonstrated. - Highlights: → We demonstrate a fast way to determine impurities in photovoltaic silicon by NAA. → We make first experiments of locally

Microelectronic temperature sensor; silicon temperature sensor

International Nuclear Information System (INIS)

Beitner, M.; Kanert, W.; Reichert, H.

1982-01-01

The goal of this work was to develop a silicon temperature sensor with a sensitivity and a reliability as high and a tolerance as small as possible, for use in measurement and control. By employing the principle of spreading-resistance, using silicon doped by neutron transmutation, and trimming of the single wafer tolerances of resistance less than +- 5% can be obtained; overstress tests yielded a long-term stability better than 0.2%. Some applications show the advantageous use of this sensor. (orig.) [de

A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

International Nuclear Information System (INIS)

Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

2010-01-01

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

The silicon vertex tracker for star and future applications of silicon drift detectors

International Nuclear Information System (INIS)

Bellwied, Rene

2001-01-01

The Silicon Vertex Tracker (SVT) for the STAR experiment at the Relativistic Heavy Ion Collider at Brookhaven National Laboratory has recently been completed and installed. First data were taken in July 2001. The SVT is based on a novel semi-conductor technology called Silicon Drift Detectors. 216 large area (6 by 6 cm) Silicon wafers were employed to build a three barrel device capable of vertexing and tracking in a high occupancy environment. Its intrinsic radiation hardness, its operation at room temperature and its excellent position resolution (better than 20 micron) in two dimensions with a one dimensional detector readout, make this technology very robust and inexpensive and thus a viable alternative to CCD, Silicon pixel and Silicon strip detectors in a variety of applications from fundamental research in high-energy and nuclear physics to astrophysics to medical imaging. I will describe the development that led to the STAR-SVT, its performance and possible applications for the near future

Optoelectronic enhancement of monocrystalline silicon solar cells by porous silicon-assisted mechanical grooving

Energy Technology Data Exchange (ETDEWEB)

Ben Rabha, Mohamed; Mohamed, Seifeddine Belhadj; Dimassi, Wissem; Gaidi, Mounir; Ezzaouia, Hatem; Bessais, Brahim [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, Technopole de Borj-Cedria, BP 95, 2050 Hammam-Lif (Tunisia)

2011-03-15

One of the most important factors influencing silicon solar cells performances is the front side reflectivity. Consequently, new methods for efficient reduction of this reflectivity are searched. This has always been done by creating a rough surface that enables incident light of being absorbed within the solar cell. Combination of texturization-porous silicon surface treatment was found to be an attractive technical solution for lowering the reflectivity of monocrystalline silicon (c-Si). The texturization of the monocrystalline silicon wafer was carried out by means of mechanical grooving. A specific etching procedure was then applied to form a thin porous silicon layer enabling to remove mechanical damages. This simple and low cost method reduces the total reflectivity from 29% to 7% in the 300 - 950 nm wavelength range and enhances the diffusion length of the minority carriers from 100 {mu}m to 790 {mu}m (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

DEFF Research Database (Denmark)

Rasmussen, Frank Engel; Frech, J.; Heschel, M.

2003-01-01

A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

Micro benchtop optics by bulk silicon micromachining

Science.gov (United States)

Lee, Abraham P.; Pocha, Michael D.; McConaghy, Charles F.; Deri, Robert J.

2000-01-01

Micromachining of bulk silicon utilizing the parallel etching characteristics of bulk silicon and integrating the parallel etch planes of silicon with silicon wafer bonding and impurity doping, enables the fabrication of on-chip optics with in situ aligned etched grooves for optical fibers, micro-lenses, photodiodes, and laser diodes. Other optical components that can be microfabricated and integrated include semi-transparent beam splitters, micro-optical scanners, pinholes, optical gratings, micro-optical filters, etc. Micromachining of bulk silicon utilizing the parallel etching characteristics thereof can be utilized to develop miniaturization of bio-instrumentation such as wavelength monitoring by fluorescence spectrometers, and other miniaturized optical systems such as Fabry-Perot interferometry for filtering of wavelengths, tunable cavity lasers, micro-holography modules, and wavelength splitters for optical communication systems.

SOI silicon on glass for optical MEMS

DEFF Research Database (Denmark)

Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

2003-01-01

and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

A repeatable and scalable fabrication method for sharp, hollow silicon microneedles

Science.gov (United States)

Kim, H.; Theogarajan, L. S.; Pennathur, S.

2018-03-01

Scalability and manufacturability are impeding the mass commercialization of microneedles in the medical field. Specifically, microneedle geometries need to be sharp, beveled, and completely controllable, difficult to achieve with microelectromechanical fabrication techniques. In this work, we performed a parametric study using silicon etch chemistries to optimize the fabrication of scalable and manufacturable beveled silicon hollow microneedles. We theoretically verified our parametric results with diffusion reaction equations and created a design guideline for a various set of miconeedles (80-160 µm needle base width, 100-1000 µm pitch, 40-50 µm inner bore diameter, and 150-350 µm height) to show the repeatability, scalability, and manufacturability of our process. As a result, hollow silicon microneedles with any dimensions can be fabricated with less than 2% non-uniformity across a wafer and 5% deviation between different processes. The key to achieving such high uniformity and consistency is a non-agitated HF-HNO3 bath, silicon nitride masks, and surrounding silicon filler materials with well-defined dimensions. Our proposed method is non-labor intensive, well defined by theory, and straightforward for wafer scale mass production, opening doors to a plethora of potential medical and biosensing applications.

Silicon microphotonic waveguides

International Nuclear Information System (INIS)

Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

2004-01-01

Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

Enhanced light emission in photonic crystal nanocavities with Erbium-doped silicon nanocrystals

International Nuclear Information System (INIS)

Makarova, Maria; Sih, Vanessa; Vuckovic, Jelena; Warga, Joe; Li Rui; Dal Negro, Luca

2008-01-01

Photonic crystal nanocavities are fabricated in silicon membranes covered by thermally annealed silicon-rich nitride films with Erbium-doped silicon nanocrystals. Silicon nitride films were deposited by sputtering on top of silicon on insulator wafers. The nanocavities were carefully designed in order to enhance emission from the nanocrystal sensitized Erbium at the 1540 nm wavelength. Experimentally measured quality factors of ∼6000 were found to be consistent theoretical predictions. The Purcell factor of 1.4 was estimated from the observed 20-fold enhancement of Erbium luminescence

Deep level transient spectroscopy and minority carrier lifetime study on Ga-doped continuous Czochralski silicon

Science.gov (United States)

Yoon, Yohan; Yan, Yixin; Ostrom, Nels P.; Kim, Jinwoo; Rozgonyi, George

2012-11-01

Continuous-Czochralski (c-Cz) crystal growth has been suggested as a viable technique for the fabrication of photovoltaic Si wafers due to its low resistivity variation of any dopant, independent of segregation, compared to conventional Cz. In order to eliminate light induced degradation due to boron-oxygen traps in conventional p-type silicon wafers, gallium doped wafers have been grown by c-Cz method and investigated using four point probe, deep level transient spectroscopy (DLTS), and microwave-photoconductance decay. Iron-gallium related electrically active defects were identified using DLTS as the main lifetime killers responsible for reduced non-uniform lifetimes in radial and axial positions of the c-Cz silicon ingot. A direct correlation between minority carrier lifetime and the concentration of electrically active Fe-Ga pairs was established.

Formation and properties of porous silicon layers

International Nuclear Information System (INIS)

Vitanov, P.; Kamenova, M.; Dimova-Malinovska, D.

1993-01-01

Preparation, properties and application of porous silicon films are investigated. Porous silicon structures were formed by an electrochemical etching process resulting in selective dissolution of the silicon substrate. The silicon wafers used with a resistivity of 5-10Ω.cm were doped with B to concentrations 6x10 18 -1x10 19 Ω.cm -3 in the temperature region 950 o C-1050 o C. The density of each porous films was determined from the weight loss during the anodization and it depends on the surface resistivity of the Si wafer. The density decreases with decreasing of the surface resistivity. The surface of the porous silicon layers was studied by X-ray photoelectron spectroscopy which indicates the presence of SiF 4 . The kinetic dependence of the anode potential and the porous layer thickness on the time of anodization in a galvanostatic regime for the electrolytes with various HF concentration were studied. In order to compare the properties of the resulting porous layers and to establish the dependence of the porosity on the electrolyte, three types of electrolytes were used: concentrated HF, diluted HF:H 2 O=1:1 and ethanol-hydrofluoric solutions HF:C 2 H 5 OH:H 2 O=2:1:1. High quality uniform and reproducible layers were formed using aqueous-ethanol-hydrofluoric electrolyte. Both Kikuchi's line and ring patterns were observed by TEM. The porous silicon layer was single crystal with the same orientation as the substrate. The surface shows a polycrystalline structure only. The porous silicon layers exhibit visible photoluminescence (PL) at room temperature under 480 nm Ar + laser line excitation. The peak of PL was observed at about 730 nm with FWHM about 90 nm. Photodiodes was made with a W-porous silicon junction. The current voltage and capacity voltage characteristics were similar to those of an isotype heterojunction diode. (orig.)

Superacid Passivation of Crystalline Silicon Surfaces.

Science.gov (United States)

Bullock, James; Kiriya, Daisuke; Grant, Nicholas; Azcatl, Angelica; Hettick, Mark; Kho, Teng; Phang, Pheng; Sio, Hang C; Yan, Di; Macdonald, Daniel; Quevedo-Lopez, Manuel A; Wallace, Robert M; Cuevas, Andres; Javey, Ali

2016-09-14

The reduction of parasitic recombination processes commonly occurring within the silicon crystal and at its surfaces is of primary importance in crystalline silicon devices, particularly in photovoltaics. Here we explore a simple, room temperature treatment, involving a nonaqueous solution of the superacid bis(trifluoromethane)sulfonimide, to temporarily deactivate recombination centers at the surface. We show that this treatment leads to a significant enhancement in optoelectronic properties of the silicon wafer, attaining a level of surface passivation in line with state-of-the-art dielectric passivation films. Finally, we demonstrate its advantage as a bulk lifetime and process cleanliness monitor, establishing its compatibility with large area photoluminescence imaging in the process.

Black silicon with black bus-bar strings

DEFF Research Database (Denmark)

Davidsen, Rasmus Schmidt; Tang, Peter Torben; Mizushima, Io

2016-01-01

We present the combination of black silicon texturing and blackened bus-bar strings as a potential method for obtaining all-black solar panels, while using conventional, front-contacted solar cells. Black silicon was realized by mask-less reactive ion etching resulting in total, average reflectance...... below 0.5% across a 156x156 mm2 silicon wafer. Black bus-bars were realized by oxidized copper resulting in reflectance below 3% in the entire visible wavelength range. The combination of these two technologies may result in aesthetic, all-black panels based on conventional, front-contacted solar cells...

Investigating reliability attributes of silicon photovoltaic cells - An overview

Science.gov (United States)

Royal, E. L.

1982-01-01

Reliability attributes are being developed on a wide variety of advanced single-crystal silicon solar cells. Two separate investigations: cell-contact integrity (metal-to-silicon adherence), and cracked cells identified with fracture-strength-reducing flaws are discussed. In the cell-contact-integrity investigation, analysis of contact pull-strength data shows that cell types made with different metallization technologies, i.e., vacuum, plated, screen-printed and soldered, have appreciably different reliability attributes. In the second investigation, fracture strength was measured using Czochralski wafers and cells taken at various stages of processing and differences were noted. Fracture strength, which is believed to be governed by flaws introduced during wafer sawing, was observed to improve (increase) after chemical polishing and other process steps that tend to remove surface and edge flaws.

A silicon-based electrochemical sensor for highly sensitive, specific, label-free and real-time DNA detection

International Nuclear Information System (INIS)

Guo, Yuanyuan; Su, Shao; Wei, Xinpan; Zhong, Yiling; Su, Yuanyuan; He, Yao; Huang, Qing; Fan, Chunhai

2013-01-01

We herein present a new kind of silicon-based electrochemical sensor using a gold nanoparticles-decorated silicon wafer (AuNPs@Si) as a high-performance electrode, which is facilely prepared via in situ AuNPs growth on a silicon wafer. Particularly significantly, the resultant electrochemical sensor is efficacious for label-free DNA detection with high sensitivity due to the unique merits of the prepared silicon-based electrode. Typically, DNA at remarkably low concentrations (1–10 fM) could be readily detected without requiring additional signal-amplification procedures, which is better than or comparable to the lowest DNA concentration ever detected via well-studied signal-amplification-assisted electrochemical sensors. Moreover, the silicon-based sensor features high specificity, allowing unambiguous discrimination of single-based mismatches. We further show that real-time DNA assembly is readily monitored via recording the intensity changes of current signals due to the robust thermal stability of the silicon-based electrode. The unprecedented advantages of the silicon-based electrochemical sensor would offer new opportunities for myriad sensing applications. (paper)

Doping of silicon by carbon during laser ablation process

Science.gov (United States)

Raciukaitis, G.; Brikas, M.; Kazlauskiene, V.; Miskinis, J.

2007-04-01

Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

Doping of silicon by carbon during laser ablation process

International Nuclear Information System (INIS)

Raciukaitis, G; Brikas, M; Kazlauskiene, V; Miskinis, J

2007-01-01

Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting

Signal development in irradiated silicon detectors

CERN Document Server

Kramberger, Gregor; Mikuz, Marko

2001-01-01

This work provides a detailed study of signal formation in silicon detectors, with the emphasis on detectors with high concentration of irradiation induced defects in the lattice. These defects give rise to deep energy levels in the band gap. As a consequence, the current induced by charge motion in silicon detectors is signifcantly altered. Within the framework of the study a new experimental method, Charge correction method, based on transient current technique (TCT) was proposed for determination of effective electron and hole trapping times in irradiated silicon detectors. Effective carrier trapping times were determined in numerous silicon pad detectors irradiated with neutrons, pions and protons. Studied detectors were fabricated on oxygenated and non-oxygenated silicon wafers with different bulk resistivities. Measured effective carrier trapping times were found to be inversely proportional to fuence and increase with temperature. No dependence on silicon resistivity and oxygen concentration was observ...

Sidewall patterning - A new wafer-scale method for accurate patterning of vertical silicon structures

NARCIS (Netherlands)

Westerik, P. J.; Vijselaar, W. J.C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G.E.

2018-01-01

For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that

Silicon microstrip detectors on 6'' technology

CERN Document Server

Bölla, G; Günther, M; Martignon, G; Bacchetta, N; Bisello, D; Leonardi, G L; Lucas, T; Wilburn, C

1999-01-01

The fabrication of microstrip detectors on 4'' high-resistivity wafers that allow for a maximum workable area of about 42 cm sup 2 has been well established. Using 6'' wafers the workable area increases up to 100 cm sup 2 (more than twice the area of a 4'' wafer) allowing a larger number of detectors to be processed at the same time on the same wafer resulting in a sizable reduction of cost. After a prototyping stage, the CDF silicon tracker upgrade is now receiving final production sensors from Micron Semiconductor Ltd. The performance of double-sided single-metal small stereo angle sensors for the CDF SVXII and ISL detectors has been studied. Results include probe station measurements and test beam results. The problems encountered from prototyping to the final devices are described. A brief overview of the response of the sensors to irradiation with gamma-rays and p sup + up to a dose of 0.5 Mrad (well above the doses expected during Run II of the Tevatron) is included. (author)

Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

Science.gov (United States)

Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

2017-10-01

Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

Trace analysis for 300 MM wafers and processes with TXRF

International Nuclear Information System (INIS)

Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

2000-01-01

Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

Covalent biofunctionalization of silicon nitride surfaces

NARCIS (Netherlands)

Arafat, A.; Giesbers, M.; Rosso, M.; Sudhölter, E.J.R.; Schroën, C.G.P.H.; White, R.G.; Li Yang,; Linford, M.R.; Zuilhof, H.

2007-01-01

Covalently attached organic monolayers on etched silicon nitride (SixN4; x 3) surfaces were prepared by reaction of SixN4-coated wafers with neat or solutions of 1-alkenes and 1-alkynes in refluxing mesitylene. The surface modification was monitored by measurement of the static water contact angle,

Study on photon sensitivity of silicon diodes related to materials used for shielding

International Nuclear Information System (INIS)

Moiseev, T.

1999-01-01

Large area silicon diodes used in electronic neutron dosemeters have a significant over-response to X- and gamma-rays, highly non-linear at photon energies below 200 keV. This over-response to photons is proportional to the diode's active area and strongly affects the neutron sensitivity of such dosemeters. Since silicon diodes are sensitive to light and electromagnetic fields, most diode detector assemblies are provided with a shielding, sometimes also used as radiation filter. In this paper, the influence of materials covering the diode's active area is investigated using the MCNP-4A code by estimating the photon induced pulses in a typical silicon wafer (300 μm thickness and 1 cm diameter) when provided with a front case cover. There have been simulated small-size diode front covers made of several materials with low neutron interaction cross-sections like aluminium, TEFLON, iron and lead. The estimated number of induced pulses in the silicon wafer is calculated for each type of shielding at normal photon incidence for several photon energies from 9.8 keV up to 1.15 MeV and compared with that in a bare silicon wafer. The simulated pulse height spectra show the origin of the photon-induced pulses in silicon for each material used as protective cover: the photoelectric effect for low Z front case materials at low-energy incident photons (up to about 65 keV) and the Compton and build-up effects for high Z case materials at higher photon energies. A simple means to lower and flatten the photon response of silicon diodes over an extended X- and gamma rays energy range is proposed by designing a composed photon filter. (author)

Study on Photon Sensitivity of Silicon Diodes Related to Materials Used for Shielding

International Nuclear Information System (INIS)

Moiseev, T.

2000-01-01

Large area Silicon diodes used in electronic neutron dosemeters have a significant over-response to X and gamma rays, highly non-linear at photon energies below 200 keV. This over-response to photons is proportional to the diodes active area and strongly affects the neutron sensitivity of such dosemeters. Since Silicon diodes are sensitive to light and electromagnetic fields, most diode detector assemblies are provided with a shielding, sometimes also used as radiation filter. In this paper, the influence of materials covering the diode's active area is investigated using the MCNP-4A code by estimating the photon induced pulses in a typical silicon wafer (300 μm thickness and 1 cm diameter) when provided with a front case cover. There have been simulated small-size diode front covers made of several materials with low neutron interaction cross-sections like aluminium, TEFLON, iron and lead. The estimated number of induced pulses in the silicon wafer is calculated for each type of shielding at normal photon incidence for several photon energies from 9.8 keV up to 1.15 MeV and compared with that in a bare silicon wafer. The simulated pulse height spectra show the origin of the photon induced pulses in silicon for each material used as protective cover: the photoelectric effect for low Z front case materials at low energy incident photons (up to about 65 keV) and the Compton and build-up effects for high Z case materials at higher photon energies. A simple means to lower and flatten the photon response of silicon diodes over an extended X and gamma rays energy range is proposed by designing a composed photon filter. (author)

Improved surface quality of anisotropically etched silicon {111} planes for mm-scale optics

International Nuclear Information System (INIS)

Cotter, J P; Hinds, E A; Zeimpekis, I; Kraft, M

2013-01-01

We have studied the surface quality of millimetre-scale optical mirrors produced by etching CZ and FZ silicon wafers in potassium hydroxide to expose the {111} planes. We find that the FZ surfaces have four times lower noise power at spatial frequencies up to 500 mm −1 . We conclude that mirrors made using FZ wafers have higher optical quality. (technical note)

Analysis of temperature profiles and the mechanism of silicon substrate plastic deformation under epitaxial growth

International Nuclear Information System (INIS)

Mirkurbanov, H.A.; Sazhnev, S.V.; Timofeev, V.N.

2004-01-01

Full text: Thermal treatment of silicon wafers holds one of the major place in the manufacturing of semi-conductor devices. Thermal treatment includes wafer annealing, thermal oxidation, epitaxial growing etc. Quality of wafers in the high-temperature processes (900-1200 deg C) is estimated by the density of structural defects, including areas of plastic deformation, which are shown as the slip lines appearance. Such areas amount to 50-60 % of total wafer surface. The plastic deformation is caused by the thermal stresses. Experimental and theoretical researches allowed to determine thermal balance and to construct a temperature profiles throughout the plate surface. Thermal stresses are caused by temperature drop along the radius of a wafer and at the basic peripheral ring. The threshold temperature drop between center f a wafer and its peripherals (ΔT) for slip lines appearance, amounts to 15-17 deg. C. At the operating temperature of 900-1200 deg. C and ΔT>20 deg. C, the stresses reach the silicon yield point. According to the results of the researches of structure and stress profiles in a wafer, the mechanism of slip lines formation has been constructed. A source of dislocations is the rear broken layer of thickness 8-10 microns, formed after polishing. The micro-fissures with a density 10 5 -10 6 cm -2 are the sources of dislocations. Dislocations move on a surface of a wafer into a slip plane (111). On a wafer surface with orientation (111) it is possible to allocate zones where the tangential stress vector is most favorably directed with respect to a slip plane leaving on a surface, i.e. the shift stresses are maximal in the slip plane. The way to eliminate plastic deformation is to lower the temperature drop to a level of <15 deg. C and elimination of the broken layer in wafer

Numerical simulation of signals of photothermal radiometry in silicon monocrystals; Simulacion numerica de senales de radiometria fototermica en mono cristales de silicio

Energy Technology Data Exchange (ETDEWEB)

Campos C, I. [Facultad de Ciencias, Universidad Autonoma de San Luis Potosi, 78000 San Luis Potosi (Mexico); Rodriguez, M.E. [Fisica Aplicada y Tecnologia Avanzada, Universidad Nacional Autonoma de Mexico, 76000 Juriquilla, Queretaro (Mexico); Ruiz, F. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Av. Carranza 2425-A, 78210 San Luis Potosi (Mexico)

2002-07-01

By using the theoretical model proposed by Mandelis et al. and a numerical simulations. We have analysed the generation of photoinduced black body radiation (photothermal radiometry signal) on monocrystalline silicon wafers. We report the particular role of each one of the main parameters involved on the photothermal signal. The parameter values were taken of the reported values for industrial silicon wafers. We show a discuss the obtained results. (Author)

Impact of SiO2 on Al–Al thermocompression wafer bonding

International Nuclear Information System (INIS)

Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

2015-01-01

Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

Morphological and optical properties of n-type porous silicon

Indian Academy of Sciences (India)

type silicon wafer have been reported in the present article. Method of PS fabrication is by photo-assisted electrochemical etching with different etching current densities ( J ). Porosity and PS layer thickness, obtained by the gravimetric method, ...

Micromachining of buried micro channels in silicon

NARCIS (Netherlands)

de Boer, Meint J.; Tjerkstra, R.W.; Berenschot, Johan W.; Jansen, Henricus V.; Burger, G.J.; Burger, G.J.; Gardeniers, Johannes G.E.; Elwenspoek, Michael Curt; van den Berg, Albert

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the

The chemo-mechanical effect of cutting fluid on material removal in diamond scribing of silicon

Science.gov (United States)

Kumar, Arkadeep; Melkote, Shreyes N.

2017-07-01

The mechanical integrity of silicon wafers cut by diamond wire sawing depends on the damage (e.g., micro-cracks) caused by the cutting process. The damage type and extent depends on the material removal mode, i.e., ductile or brittle. This paper investigates the effect of cutting fluid on the mode of material removal in diamond scribing of single crystal silicon, which simulates the material removal process in diamond wire sawing of silicon wafers. We conducted scribing experiments with a diamond tipped indenter in the absence (dry) and in the presence of a water-based cutting fluid. We found that the cutting mode is more ductile when scribing in the presence of cutting fluid compared to dry scribing. We explain the experimental observations by the chemo-mechanical effect of the cutting fluid on silicon, which lowers its hardness and promotes ductile mode material removal.

Flexible and semi-transparent thermoelectric energy harvesters from low cost bulk silicon (100)

KAUST Repository

Sevilla, Galo T.

2013-07-09

Flexible and semi-transparent high performance thermoelectric energy harvesters are fabricated on low cost bulk mono-crystalline silicon (100) wafers. The released silicon is only 3.6% as thick as bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. This generic batch processing is a pragmatic way of transforming traditional silicon circuitry for extremely deformable high-performance integrated electronics. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flexible and semi-transparent thermoelectric energy harvesters from low cost bulk silicon (100)

KAUST Repository

Sevilla, Galo T.; Inayat, Salman Bin; Rojas, Jhonathan Prieto; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2013-01-01

Flexible and semi-transparent high performance thermoelectric energy harvesters are fabricated on low cost bulk mono-crystalline silicon (100) wafers. The released silicon is only 3.6% as thick as bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. This generic batch processing is a pragmatic way of transforming traditional silicon circuitry for extremely deformable high-performance integrated electronics. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Subsurface oxidation for micropatterning silicon (SOMS).

Science.gov (United States)

Zhang, Feng; Sautter, Ken; Davis, Robert C; Linford, Matthew R

2009-02-03

Here we present a straightforward patterning technique for silicon: subsurface oxidation for micropatterning silicon (SOMS). In this method, a stencil mask is placed above a silicon surface. Radio-frequency plasma oxidation of the substrate creates a pattern of thicker oxide in the exposed regions. Etching with HF or KOH produces very shallow or much higher aspect ratio features on silicon, respectively, where patterning is confirmed by atomic force microscopy, scanning electron microscopy, and optical microscopy. The oxidation process itself is studied under a variety of reaction conditions, including higher and lower oxygen pressures (2 and 0.5 Torr), a variety of powers (50-400 W), different times and as a function of reagent purity (99.5 or 99.994% oxygen). SOMS can be easily executed in any normal chemistry laboratory with a plasma generator. Because of its simplicity, it may have industrial viability.

Sol-gel derived antireflective coatings for silicon

Energy Technology Data Exchange (ETDEWEB)

Brinker, C J; Harrington, M S

1981-08-01

The preparation of TiO2-SiO2 AR coatings, containing from 30 to 95 mol % TiO2, from alkoxide precursor solutions (titanium tetraethoxide and silicon tetraethoxide) by a sol-gel process is presented. The preparation of the solutions is described, which involves the separate partial hydrolysis of one or both alkoxides prior to their mixing (Yoldas, 1980). The solutions are applied to polished, circular (1 and 2 in. diameter) silicon wafers by a spinning process. The coated wafers are successively heated in air at each of the following temperatures: 200, 300, 350, 400, and 450 C, and optical measurements are performed on them after each heat treatment. The durability of 90 and 95% TiO2 coatings is evaluated in both acidic and basic environments, and reflectivity, film thickness, and refractive index are measured as a function of exposure time. It is shown that sol-gel films applied at 400 C reveal broad regions of antireflectance compared to other titanium-based films.

Micro filtration membrane sieve with silicon micro machining for industrial and biomedical applications

NARCIS (Netherlands)

van Rijn, C.J.M.; Elwenspoek, Michael Curt

1995-01-01

With the use of silicon micromachining an inorganic membrane sieve for microfiltration is constructed, having a siliconnitride membrane layer with thickness typically 1 pm and perforations typically between 0.5 pm and 10 pm in diameter. As a support a -silicon wafer with openings of loo0 pm in

Silicon-photonics light source realized by III-V/Si grating-mirror laser

DEFF Research Database (Denmark)

Chung, Il-Sug; Mørk, Jesper

2010-01-01

waveguide are made in the Si layer of a silicon-on-insulator wafer by using Si-electronics-compatible processing. The HCG works as a highly-reflective mirror for vertical resonance and at the same time routes light to the in-plane output waveguide. Numerical simulations show superior performance compared...... to existing silicon light sources....

High throughput batch wafer handler for 100 to 200 mm wafers

International Nuclear Information System (INIS)

Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

1989-01-01

A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

Doping of silicon with carbon during laser ablation process

Science.gov (United States)

Račiukaitis, G.; Brikas, M.; Kazlauskienė, V.; Miškinis, J.

2006-12-01

The effect of laser ablation on properties of remaining material in silicon was investigated. It was found that laser cutting of wafers in the air induced the doping of silicon with carbon. The effect was more distinct when using higher laser power or UV radiation. Carbon ions created bonds with silicon atoms in the depth of the material. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion to clarify its depth profile in silicon was performed. Photochemical reactions of such type changed the structure of material and could be the reason of the reduced machining quality. The controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires

International Nuclear Information System (INIS)

Ozdemir, Baris; Unalan, Husnu Emrah; Kulakci, Mustafa; Turan, Rasit

2011-01-01

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 μm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires.

Science.gov (United States)

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Unalan, Husnu Emrah

2011-04-15

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires

Science.gov (United States)

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Emrah Unalan, Husnu

2011-04-01

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Method of fabricating porous silicon carbide (SiC)

Science.gov (United States)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

The status of silicon ribbon growth technology for high-efficiency silicon solar cells

Science.gov (United States)

Ciszek, T. F.

1985-01-01

More than a dozen methods have been applied to the growth of silicon ribbons, beginning as early as 1963. The ribbon geometry has been particularly intriguing for photovoltaic applications, because it might provide large area, damage free, nearly continuous substrates without the material loss or cost of ingot wafering. In general, the efficiency of silicon ribbon solar cells has been lower than that of ingot cells. The status of some ribbon growth techniques that have achieved laboratory efficiencies greater than 13.5% are reviewed, i.e., edge-defined, film-fed growth (EFG), edge-supported pulling (ESP), ribbon against a drop (RAD), and dendritic web growth (web).

IR and UV laser-induced morphological changes in silicon surface under oxygen atmosphere

Energy Technology Data Exchange (ETDEWEB)

Jimenez-Jarquin, J.; Fernandez-Guasti, M.; Haro-Poniatowski, E.; Hernandez-Pozos, J.L. [Laboratorio de Optica Cuantica, Departamento de Fisica, Universidad Autonoma Metropolitana-Iztapalapa, Av. San Rafael Atlixco No. 186, Col. Vicentina, C.P. 09340, Mexico D.F. (Mexico)

2005-08-01

We irradiated silicon (100) wafers with IR (1064 nm) and UV (355 nm) nanosecond laser pulses with energy densities within the ablation regime and used scanning electron microscopy to analyze the morphological changes induced on the Si surface. The changes in the wafer morphology depend both on the incident radiation wavelength and the environmental atmosphere. We have patterned Si surfaces with a single focused laser spot and, in doing the experiments with IR or UV this reveals significant differences in the initial surface cracking and pattern formation, however if the experiment is carried out in O{sub 2} the final result is an array of microcones. We also employed a random scanning technique to irradiate the silicon wafer over large areas, in this case the microstructure patterns consist of a ''semi-ordered'' array of micron-sized cones. (copyright 2005 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

Science.gov (United States)

Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

2015-08-01

Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F-) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F-, smaller azimuth angle of Fsbnd Ag(T4)sbnd Si, shorter bond length of Fsbnd Si compared with Fsbnd Ag. As F- was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF4 when it bonded with enough F- while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F- to Si.

A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

International Nuclear Information System (INIS)

Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

1990-01-01

The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

Transistors using crystalline silicon devices on glass

Science.gov (United States)

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Fabrication of silicon condenser microphones using single wafer technology

NARCIS (Netherlands)

Scheeper, P.R.; van der Donk, A.G.H.; Olthuis, Wouter; Bergveld, Piet

1992-01-01

A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-¿m plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm2), covered with a thin

Analysis of the silicon market: Will thin films profit?

International Nuclear Information System (INIS)

Sark, W.G.J.H.M. van; Brandsen, G.W.; Fleuster, M.; Hekkert, M.P.

2007-01-01

The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010

Analysis of the silicon market: Will thin films profit?

Energy Technology Data Exchange (ETDEWEB)

Sark, W.G.J.H.M. van; Brandsen, G.W. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Science, Technology and Society; Fleuster, M. [Solland Solar Energy, Heerlen (Netherlands); Hekkert, M.P. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Innovation Studies

2007-06-15

The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010. (author)

Effect of Processing Parameters on Thickness of Columnar Structured Silicon Wafers Directly Grown from Silicon Melts

Directory of Open Access Journals (Sweden)

Jin-Seok Lee

2012-01-01

Full Text Available In order to obtain optimum growth conditions for desired thickness and more effective silicon feedstock usage, effects of processing parameters such as preheated substrate temperatures, time intervals, moving velocity of substrates, and Ar gas blowing rates on silicon ribbon thickness were investigated in the horizontal growth process. Most of the parameters strongly affected in the control of ribbon thickness with columnar grain structure depended on the solidification rate. The thickness of the silicon ribbon decreased with an increasing substrate temperature, decreasing time interval, and increasing moving velocity of the substrate. However, the blowing of Ar gas onto a liquid layer existing on the surface of solidified ribbon contributed to achieving smooth surface roughness but did not closely affect the change of ribbon thickness in the case of a blowing rate of ≥0.65 Nm3/h because the thickness of the solidified layer was already determined by the exit height of the reservoir.

Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

Energy Technology Data Exchange (ETDEWEB)

Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

1997-11-30

This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

Electrodeposition of three-dimensionally assembled platinum spheres on a gold-coated silicon wafer, and its application to nonenzymatic sensing of glucose

International Nuclear Information System (INIS)

Roh, Seongjin; Kim, Jongwon

2015-01-01

We report on a method of single-step electrodeposition of three-dimensionally (3-D) assembled Pt spheres on a gold-coated silicon wafer. The 3-D interconnected Pt spheres could be electrodeposited by applying a negative potential (−0.8 V, vs. Ag/AgCl) in neutral electrolytes containing KClO 4 . The application of such a negative potential is not possible in acidic solutions because of the formation of hydrogen. Scanning electron microscopy revealed that the seed Pt particles first grew to a certain size, and then form Pt spheres interconnected in multiple layers. The resulting 3-D assembled Pt sphere structures warrants a high surface area, and this property was utilized for the selective and sensitive amperometric determination of glucose at a working potential of 0.4 V (vs. Ag/AgCl), at near neutral pH values and in the presence of 0.1 M chloride. This straightforward method for the fabrication of 3-D assembled Pt sphere structures offers new opportunities for electroanalytical and electrocatalytic sensing based on porous Pt surfaces (author)

Optimizing shape uniformity and increasing structure heights of deep reactive ion etched silicon x-ray lenses

DEFF Research Database (Denmark)

Stöhr, Frederik; Wright, Jonathan; Simons, Hugh

2015-01-01

Line-focusing compound silicon x-ray lenses with structure heights exceeding 300 μm were fabricated using deep reactive ion etching. To ensure profile uniformity over the full height, a new strategy was developed in which the perimeter of the structures was defined by trenches of constant width....... The remaining sacrificial material inside the lens cavities was removed by etching through the silicon wafer. Since the wafers become fragile after through-etching, they were then adhesively bonded to a carrier wafer. Individual chips were separated using laser micro machining and the 3D shape of fabricated...... analysis, where a slight bowing of the lens sidewalls and an insufficiently uniform apex region are identified as resolution-limiting factors. Despite these, the proposed fabrication route proved a viable approach for producing x-ray lenses with large structure heights and provides the means to improve...

The effect of porosity on energetic porous silicon solid propellant micro-propulsion

International Nuclear Information System (INIS)

Churaman, Wayne A; Morris, Christopher J; Ramachandran, Raghav; Bergbreiter, Sarah

2015-01-01

Energetic porous silicon is investigated as an actuator for micro-propulsion based on thrust and impulse measurements for a variety of porous silicon porosity conditions. Porosity of 2 mm diameter, porous silicon microthruster devices was varied by changing the concentration of hydrofluoric acid and ethanol in an etch solution, by changing porous silicon etch depth, and by changing the resistivity of silicon wafers used for the etch process. The porosity varied from 30% to 75% for these experiments. The highest mean thrust and impulse values measured with a calibrated Kistler 9215 force sensor were 674 mN and 271 μN s, respectively, with a 73% porosity, 2 mm diameter porous silicon device etched in a 3 : 1 etch solution on a 3.6 Ω cm wafer to a target etch depth of 30 μm. As a result of changing porosity, a 23×  increase in thrust performance and a 36×  increase in impulse performance was demonstrated. Impulse values were also validated using a pendulum experiment in which the porous silicon microthruster was unconstrained, but several non-linearities in the pendulum experimental setup resulted in less consistent data than when measured by the force sensor for microthrusters at this size scale. These thrust and impulse results complement previous work in determining the effect of porosity on other porous silicon reaction metrics such as flame speed. (paper)

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

International Nuclear Information System (INIS)

Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

2014-01-01

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

Science.gov (United States)

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

77 GHz MEMS antennas on high-resistivity silicon for linear and circular polarization

KAUST Repository

Sallam, M. O.

2011-07-01

Two new MEMS antennas operating at 77 GHz are presented in this paper. The first antenna is linearly polarized. It possesses a vertical silicon wall that carries a dipole on top of it. The wall is located on top of silicon substrate covered with a ground plane. The other side of the substrate carries a microstrip feeding network in the form of U-turn that causes 180 phase shift. This phase-shifter feeds the arms of the dipole antenna via two vertical Through-Silicon Vias (TSVs) that go through the entire wafer. The second antenna is circularly polarized and formed using two linearly polarized antennas spatially rotated with respect to each other by 90 and excited with 90 phase shift. Both antennas are fabricated using novel process flow on a single high-resistivity silicon wafer via bulk micromachining. Only three processing steps are required to fabricate these antennas. The proposed antennas have appealing characteristics, such as high polarization purity, high gain, and high radiation efficiency. © 2011 IEEE.

Porous silicon in solar cell structures : a review of achievements and modern directions of further use

NARCIS (Netherlands)

Yerokhov, VY; Melnyk, [No Value

1999-01-01

Porous silicon, which is being obtained by electrochemical etching of silicon wafers in electrolytes on the base of hydrofluoric acid, recently attracted the attention of specialists in photovoltaics even more due to a number of its unique properties. However, at present, acceptable results are

X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

Energy Technology Data Exchange (ETDEWEB)

Anon.

2014-09-15

The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

The determination of gold depth distribution in semiconductor silicon-potential interferences inherent in NAA by radiation damages

International Nuclear Information System (INIS)

Rudolph, P.; Lange, A.; Flachowsky, J.

1986-01-01

Gold is used quite extensively to control the charge storage time of high speed diodes and transistors. Therefore, the diffusion of gold into silicon wafers of finite thickness is important in the design and fabrication of these devices. Therefore it is necessary to estimate exactly concentration and depth distribution of gold formed by gold doping. Usually, gold content and depth distribution has been estimate by neutron activation analysis with step by step etching techniques. But during the irradiation in a nuclear fuel reactor the silicon wafers undergo minute or pronounced radiation damages which may affect the depth profiles of gold concentration. (author)

(Preoxidation cleaning optimization for crystalline silicon)

Energy Technology Data Exchange (ETDEWEB)

1991-01-01

A series of controlled experiments has been performed in Sandia's Photovoltaic Device Fabrication Laboratory to evaluate the effect of various chemical surface treatments on the recombination lifetime of crystalline silicon wafers subjected to a high-temperature dry oxidation. From this series of experiments we have deduced a relatively simple yet effective cleaning sequence. We have also evaluated the effect of different chemical damage-removal etches for improving the recombination lifetime and surface smoothness of mechanically lapped wafers. This paper presents the methodology used, the experimental results obtained, and our experience with using this process on a continuing basis over a period of many months. 7 refs., 4 figs., 1 tab.

VCSELs and silicon light sources exploiting SOI grating mirrors

DEFF Research Database (Denmark)

Chung, Il-Sug; Mørk, Jesper

2012-01-01

In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI...... the Bragg reflector. Numerical simulations show that both the silicon light source and the VCSEL exploiting SOI grating mirrors have superior performances, compared to existing silicon light sources and long wavelength VCSELs. These devices are highly adequate for chip-level optical interconnects as well...

Self-diffusion in single crystalline silicon nanowires

Science.gov (United States)

Südkamp, T.; Hamdana, G.; Descoins, M.; Mangelinck, D.; Wasisto, H. S.; Peiner, E.; Bracht, H.

2018-04-01

Self-diffusion experiments in single crystalline isotopically controlled silicon nanowires with diameters of 70 and 400 nm at 850 and 1000 °C are reported. The isotope structures were first epitaxially grown on top of silicon substrate wafers. Nanowires were subsequently fabricated using a nanosphere lithography process in combination with inductively coupled plasma dry reactive ion etching. Three-dimensional profiling of the nanosized structure before and after diffusion annealing was performed by means of atom probe tomography (APT). Self-diffusion profiles obtained from APT analyses are accurately described by Fick's law for self-diffusion. Data obtained for silicon self-diffusion in nanowires are equal to the results reported for bulk silicon crystals, i.e., finite size effects and high surface-to-volume ratios do not significantly affect silicon self-diffusion. This shows that the properties of native point defects determined from self-diffusion in bulk crystals also hold for nanosized silicon structures with diameters down to 70 nm.

Towards micro-assembly of hybrid MOEMS components on a reconfigurable silicon free-space micro-optical bench

International Nuclear Information System (INIS)

Bargiel, S; Gorecki, C; Rabenorosoa, K; Clévy, C; Lutz, P

2010-01-01

The 3D integration of hybrid chips is a viable approach for the micro-optical technologies to reduce the costs of assembly and packaging. In this paper a technology platform for the hybrid integration of MOEMS components on a reconfigurable silicon free-space micro-optical bench (FS-MOB) is presented. In this approach a desired optical component (e.g. micromirror, microlens) is integrated with a removable and adjustable silicon holder which can be manipulated, aligned and fixed in the precisely etched rail of the silicon baseplate by use of a robotic micro-assembly station. An active-based gripping system allows modification of the holder position on the baseplate with nanometre precision. The fabrication processes of the micromachined parts of the micro-optical bench, based on bulk micromachining of standard silicon wafer and SOI wafer, are described. The successful assembly of the holders, equipped with a micromirror and a refractive glass ball microlens, on the baseplate rail is demonstrated.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.; Rojas, Jhonathan Prieto; Ahmed, Sally; Hussain, Aftab M.; Inayat, Salman Bin; Hussain, Muhammad Mustafa

2013-01-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.

2013-06-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

Wafer scale oblique angle plasma etching

Science.gov (United States)

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Rapid diffusion of molybdenum trace contamination in silicon

International Nuclear Information System (INIS)

Tobin, S.P.; Greenwald, A.C.; Wolfson, R.G.; Meier, D.L.; Drevinsky, P.J.

1985-01-01

Molybdenum contamination has been detected in silicon epitaxial layers and substrate wafers after processing in any one of several epitaxial silicon reactors. Greatly reduced minority carrier diffusion lengths and lifetimes are consistent with Mo concentrations measured by DLTS in the 10 12 and 10 13 cm -3 ranges. Depth profiling of diffusion length and the Mo deep level show much greater penetration than expected from previous reports of Mo as a slow diffuser. The data indicate a lower limit of 10 -8 cm 2 /sec for the diffusion coefficient of Mo in silicon at 1200 0 C, consistent with high diffusivities measured for other transition metals

Radiation hardness of silicon detectors manufactured on wafers from various sources

International Nuclear Information System (INIS)

Dezillie, B.; Bates, S.; Glaser, M.; Lemeilleur, F.; Leroy, C.

1997-01-01

Impurity concentrations in the initial silicon material are expected to play an important role for the radiation hardness of silicon detectors, during their irradiation and for their evolution with time after irradiation. This work reports on the experimental results obtained with detectors manufactured using various float-zone (FZ) and epitaxial-grown material. Preliminary results comparing the changes in leakage current and full depletion voltage of FZ and epitaxial detectors as a function of fluence and of time after 10 14 cm -2 proton irradiation are given. The measurement of charge collection efficiency for epitaxial detectors is also presented. (orig.)

Possibility of whole-surface analysis of a silicon wafer with ordinary straight TXRF

International Nuclear Information System (INIS)

Mori, Y.; Uemura, K.; Iizuka, Y.

2000-01-01

For the analysis of average metal concentration on a semiconductor surface, we customarily use the wet techniques (AAS, typically), that require skilled operators or expensive automated machines for sample pretreatment. The straight TXRF require no pretreatment, on the other hand. However, its detection area is too small (1-2 cm 2 ) to conduct a whole-surface analysis. In fact, it takes more than one day per one wafer (500 s/point x 100-300 points) for a complete mapping. Therefore it has been believed that the whole-surface analysis with straight TXRF is impracticable. It should be noted that the absolute lower limit of detection (LLD) of the straight TXRF is superior to AAS. As an example, the absolute LLD of TXRF for Fe is 0.2 pg (500 s integration), while that of AAS is l0 pg. The required integration time for TXRF to obtain the same LLD of AAS is calculated to be only 0.2 s. This means, in principle, that the whole-surface contamination can be measured in some ten seconds by accumulating 0.2 s mapping. But actually, the adjustment of glancing angle requires several ten seconds per one point, so the above mapping still takes several hours. That is why such a measurement has not been applied to daily analysis so far. However, the influence of glancing angle errors is expected to be reduced through the multi-point measurement. Figure 1 shows an accumulated spectrum of 20 s x 25 points mapping for an IAP wafer doped with Ni. In this measurement, glancing angles were not precisely controlled (the error of glancing angle is ±15 %). A spectrum of 500 s x 1 point measurement for the same wafer is shown in Figure 2. Figures 1 and 2 are almost identical. This suggests that the reduction of glancing angle errors actually works well through multi-points measurement. This method is expected to give better results by increasing the number of measuring points. The overall variation for the final measurement value obtained by multi-point measurement can be assessed by the

Roadmap for integration of InP based photonics and silicon electronics

NARCIS (Netherlands)

Williams, K.A.

2015-01-01

We identify the synergies and a roadmap for the intimate integration of InP photonic integrated circuits and Silicon electronic ICs using wafer-scale processes. Advantages are foreseen in terms of bandwidth, energy savings and package simplification.

Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

Science.gov (United States)

Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

Science.gov (United States)

Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Chattopadhyay, Goutam (Inventor); Perez, Jose Vicente Siles (Inventor); Lin, Robert H. (Inventor); Mehdi, Imran (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Poly(3-hexylthiophene) films by electrospray deposition for crystalline silicon/organic hybrid junction solar cells

Energy Technology Data Exchange (ETDEWEB)

Hiate, Taiga; Miyauchi, Naoto; Tang, Zeguo; Ishikawa, Ryo; Ueno, Keiji; Shirai, Hajime [Graduate School of Science and Engineering, Saitama University, 255 Shimo-Okubo, Sakura, Saitama 858-3676 (Japan)

2012-10-15

The electrospray deposition (ESD) of poly(3-hexylthiophene) (P3HT) and conductive poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) on P3HT for use in crystalline silicon/organic hybrid heterojunction solar cells on CZ crystalline silicon (c-Si) (100) wafer was investigated using real-time characterization by spectroscopic ellipsometry (SE). In contrast to the nonuniform deposition of products frequently obtained by conventional spin-coating, a uniform deposition of P3HT and PEDOT:PSS films were achieved on flat and textured hydrophobic c-Si(100) wafers by adjusting the deposition conditions. The c-Si/P3HT/PEDOT:PSS heterojunction solar cells exhibited efficiencies of 4.1 and 6.3% on flat and textured c-Si(100) wafers, respectively. These findings suggest that ESD is a promising method for the uniform deposition of P3HT and PEDOT:PSS films on flat and textured hydrophobic substrates. (copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Carbon dioxide capture using resin-wafer electrodeionization

Science.gov (United States)

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Investigation the effect of porosity on corrosion of macroporous silicon in 1.0 M sodium hydroxide solution using weight loss measurements, electrochemical methods and scanning electron microscope

International Nuclear Information System (INIS)

Lai, Chuan; Xiang, Zhen

2015-01-01

Highlights: • The dissolution of silicon wafers conforms Faraday’s laws of electrolysis. • The porosity effect on macroporous silicon corrosion was investigated. • The corrosion rate increase linearly with porosity increasing. • The porosity effect on activation parameters was obtained. - Abstract: In this study, the macroporous silicon has been fabricated by electrochemical anodization. The dissolution of n-type silicon wafers in etching solution conforms Faraday’s laws of electrolysis. The fabricated macroporous silicon with different porosity corrosion in 1.0 M NaOH was systemically investigated by weight loss measurements, electrochemical methods and scanning electron microscope. Results show that with the porosity increasing, the corrosion rate of macroporous silicon in 1.0 M NaOH increases linearly. In addition, the increase of corrosion rate of macroporous silicon with relative higher porosity was determined by the pre-exponential factor.

Mechanical grooving of oxidized porous silicon to reduce the reflectivity of monocrystalline silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Zarroug, A.; Dimassi, W.; Ouertani, R.; Ezzaouia, H. [Laboratoire de Photovoltaique, Centre des Recherches et des Technologies de l' Energie, BP. 95, Hammam-Lif 2050 (Tunisia)

2012-10-15

In this work, we are interested to use oxidized porous silicon (ox-PS) as a mask. So, we display the creating of a rough surface which enhances the absorption of incident light by solar cells and reduces the reflectivity of monocrystalline silicon (c-Si). It clearly can be seen that the mechanical grooving enables us to elaborate the texturing of monocrystalline silicon wafer. Results demonstrated that the application of a PS layer followed by a thermal treatment under O2 ambient easily gives us an oxide layer of uniform size which can vary from a nanometer to about ten microns. In addition, the Fourier transform infrared (FTIR) spectroscopy investigations of the PS layer illustrates the possibility to realize oxide layer as a mask for porous silicon. We found also that this simple and low cost method decreases the total reflectivity (copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Silicon-based metallic micro grid for electron field emission

International Nuclear Information System (INIS)

Kim, Jaehong; Jeon, Seok-Gy; Kim, Jung-Il; Kim, Geun-Ju; Heo, Duchang; Shin, Dong Hoon; Sun, Yuning; Lee, Cheol Jin

2012-01-01

A micro-scale metal grid based on a silicon frame for application to electron field emission devices is introduced and experimentally demonstrated. A silicon lattice containing aperture holes with an area of 80 × 80 µm 2 and a thickness of 10 µm is precisely manufactured by dry etching the silicon on one side of a double-polished silicon wafer and by wet etching the opposite side. Because a silicon lattice is more rigid than a pure metal lattice, a thin layer of Au/Ti deposited on the silicon lattice for voltage application can be more resistant to the geometric stress caused by the applied electric field. The micro-fabrication process, the images of the fabricated grid with 88% geometric transparency and the surface profile measurement after thermal feasibility testing up to 700 °C are presented. (paper)

Effect of Current Density on Thermal and Optical Properties of p-Type Porous Silicon

International Nuclear Information System (INIS)

Kasra Behzad; Wan Mahmood Mat Yunus; Zainal Abidin Talib; Azmi Zakaria; Afarin Bahrami

2011-01-01

The different parameters of the porous silicon (PSi) can be tuned by changing some parameters in preparation process. We have chosen the anodization as formation method, so the related parameters should be changed. In this study the porous silicon (PSi) layers were formed on p-type Si wafer. The samples were anodized electrically in a fixed etching time under some different current densities. The structural and optical properties of porous silicon (PSi) on silicon (Si) substrates were investigated using photoluminescence (PL) and Photoacoustic Spectroscopy (PAS). (author)

Development of AC-coupled, poly-silicon biased, p-on-n silicon strip detectors in India for HEP experiments

Science.gov (United States)

Jain, Geetika; Dalal, Ranjeet; Bhardwaj, Ashutosh; Ranjan, Kirti; Dierlamm, Alexander; Hartmann, Frank; Eber, Robert; Demarteau, Marcel

2018-02-01

P-on-n silicon strip sensors having multiple guard-ring structures have been developed for High Energy Physics applications. The study constitutes the optimization of the sensor design, and fabrication of AC-coupled, poly-silicon biased sensors of strip width of 30 μm and strip pitch of 55 μm. The silicon wafers used for the fabrication are of 4 inch n-type, having an average resistivity of 2-5 k Ω cm, with a thickness of 300 μm. The electrical characterization of these detectors comprises of: (a) global measurements of total leakage current, and backplane capacitance; (b) strip and voltage scans of strip leakage current, poly-silicon resistance, interstrip capacitance, interstrip resistance, coupling capacitance, and dielectric current; and (c) charge collection measurements using ALiBaVa setup. The results of the same are reported here.

Methane production using resin-wafer electrodeionization

Science.gov (United States)

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Comparison of laser chemical processing and lasermicrojet for structuring and cutting silicon substrates

Energy Technology Data Exchange (ETDEWEB)

Hopman, Sybille; Fell, Andreas; Mayer, Kuno; Mesec, Matthias; Rodofili, Andreas; Kray, Daniel [Fraunhofer Institute for Solar Energy Systems ISE, Freiburg (Germany)

2009-06-15

This paper deals with the development of a new cutting method for thin silicon solar wafers with liquid-jet-guided lasers (lasermicrojet {sup registered}, LMJ, and laser chemical processing, LCP). Several laser systems with different wavelengths were tested to find the optimum laser system and processing parameters in terms of efficient material removal and deep laser cutting. Water and potassium hydroxide were used as carrier liquids to enhance laser ablation. The ablation efficiency was defined as a target parameter and experimentally determined by performing single laser grooves. It is demonstrated that the ablation process of LMJ is mainly affected by silicon melting and then removing by the liquid-jet momentum for single laser grooves. Best result for deep laser grooves is achieved if evaporation dominates the ablation process. Better surface quality referred to laser-induced crystalline damage is presented for a cut wafer with LMJ in comparison to a standard multiwire slurry saw. This shows a great potential of wafering with liquid-jet-guided lasers although no optimal liquid media was used. (orig.)

Model of the recrystallization mechanism of amorphous silicon layers created by ion implantation

International Nuclear Information System (INIS)

Drosd, R.M.

1979-11-01

The recrystallization behavior during annealing of thin films of amorphous (α) silicon, in contact with a single crystal silicon substrate (referred to as C), has been studied in the transmission electron microscope (TEM). The amorphous film is created during high dose phosphorus ion implantation at 100 keV. It was found that the crystal substrate orientation and the implantation temperature have dramatic effects on the recrystallizaton rate, and the defect microstructure produced during annealing. Specifically, (100) wafers implanted at 77 0 K contain only a low density of dislocation loops, but when the same wafer is implanted at room temperature the dislocation density is increased drastically. (111) wafers, when implanted at 77 0 K show a high density of microtwins, but as the implantation temperature is increased a gradual increase in the density of dislocation loops is observed along with a reduction of the microtwins. At an implantation temperature of about 100 0 C both orientations give an identical defect microstructure when annealed, which is a dense tangle of dislocations

Formation of array microstructures on silicon by multibeam interfered femtosecond laser pulses

International Nuclear Information System (INIS)

Zhao Quanzhong; Qiu Jianrong; Zhao Chongjun; Jiang Xiongwei; Zhu Congshan

2005-01-01

We report on an optical interference method to fabricate array microstructures on the surface of silicon wafers by means of five-beam interference of femtosecond laser pulses. Optical microscope and scanning electron microscope observations revealed microstructures with micrometer-order were fabricated. The diffraction characteristics of the fabricated structures were evaluated. The present technique allows one-step realization of functional optoelectronic devices on silicon surface

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

Directory of Open Access Journals (Sweden)

Kenji Okabe

2015-12-01

Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

Science.gov (United States)

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Laser process for extended silicon thin film solar cells

International Nuclear Information System (INIS)

Hessmann, M.T.; Kunz, T.; Burkert, I.; Gawehns, N.; Schaefer, L.; Frick, T.; Schmidt, M.; Meidel, B.; Auer, R.; Brabec, C.J.

2011-01-01

We present a large area thin film base substrate for the epitaxy of crystalline silicon. The concept of epitaxial growth of silicon on large area thin film substrates overcomes the area restrictions of an ingot based monocrystalline silicon process. Further it opens the possibility for a roll to roll process for crystalline silicon production. This concept suggests a technical pathway to overcome the limitations of silicon ingot production in terms of costs, throughput and completely prevents any sawing losses. The core idea behind these thin film substrates is a laser welding process of individual, thin silicon wafers. In this manuscript we investigate the properties of laser welded monocrystalline silicon foils (100) by micro-Raman mapping and spectroscopy. It is shown that the laser beam changes the crystalline structure of float zone grown silicon along the welding seam. This is illustrated by Raman mapping which visualizes compressive stress as well as tensile stress in a range of - 147.5 to 32.5 MPa along the welding area.

Light-Induced Degradation of Thin Film Silicon Solar Cells

International Nuclear Information System (INIS)

Hamelmann, F U; Weicht, J A; Behrens, G

2016-01-01

Silicon-wafer based solar cells are still domination the market for photovoltaic energy conversion. However, most of the silicon is used only for mechanical stability, while only a small percentage of the material is needed for the light absorption. Thin film silicon technology reduces the material demand to just some hundred nanometer thickness. But even in a tandem stack (amorphous and microcrystalline silicon) the efficiencies are lower, and light-induced degradation is an important issue. The established standard tests for characterisation are not precise enough to predict the performance of thin film silicon solar cells under real conditions, since many factors do have an influence on the degradation. We will show some results of laboratory and outdoor measurements that we are going to use as a base for advanced modelling and simulation methods. (paper)

A silicon pixel detector with routing for external VLSI read-out

International Nuclear Information System (INIS)

Thomas, S.L.; Seller, P.

1988-07-01

A silicon pixel detector with an array of 32 by 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector. The detailed design of the pixels, their layout and method of read-out are discussed. A number of test structures have been incorporated onto the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future. (author)

Waveguide silicon nitride grating coupler

Science.gov (United States)

Litvik, Jan; Dolnak, Ivan; Dado, Milan

2016-12-01

Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

Laser desorption ionization and peptide sequencing on laser induced silicon microcolumn arrays

Science.gov (United States)

Vertes, Akos [Reston, VA; Chen, Yong [San Diego, CA

2011-12-27

The present invention provides a method of producing a laser-patterned silicon surface, especially silicon wafers for use in laser desorption ionization (LDI-MS) (including MALDI-MS and SELDI-MS), devices containing the same, and methods of testing samples employing the same. The surface is prepared by subjecting a silicon substrate to multiple laser shots from a high-power picosecond or femtosecond laser while in a processing environment, e.g., underwater, and generates a remarkable homogenous microcolumn array capable of providing an improved substrate for LDI-MS.

Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2013-01-01

(100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

Silicon-Film(TM) Solar Cells by a Flexible Manufacturing System: Final Report, 16 April 1998 -- 31 March 2001

Energy Technology Data Exchange (ETDEWEB)

Rand, J.

2002-02-01

This report describes the overall goal to engineer and develop flexible manufacturing methods and equipment to process Silicon-Film solar cells and modules. Three major thrusts of this three-year effort were to: develop a new larger-area (208 mm x 208 mm) Silicon-Film solar cell, the APx-8; construct and operate a new high-throughput wafer-making system; and develop a 15-MW single-thread manufacturing process. Specific technical accomplishments from this period are: Increase solar cell area by 80%, increase the generation capacity of a Silicon-Film wafer-making system by 350%, use a new in-line HF etch system in solar cell production, design and develop an in-line NaOH etch system, eliminate cassettes in solar cell processing, and design a new family of module products.

Highly nonlinear sub-micron silicon nitride trench waveguide coated with gold nanoparticles

Science.gov (United States)

Huang, Yuewang; Zhao, Qiancheng; Sharac, Nicholas; Ragan, Regina; Boyraz, Ozdal

2015-05-01

We demonstrate the fabrication of a highly nonlinear sub-micron silicon nitride trench waveguide coated with gold nanoparticles for plasmonic enhancement. The average enhancement effect is evaluated by measuring the spectral broadening effect caused by self-phase-modulation. The nonlinear refractive index n2 was measured to be 7.0917×10-19 m2/W for a waveguide whose Wopen is 5 μm. Several waveguides at different locations on one wafer were measured in order to take the randomness of the nanoparticle distribution into consideration. The largest enhancement is measured to be as high as 10 times. Fabrication of this waveguide started with a MEMS grade photomask. By using conventional optical lithography, the wide linewidth was transferred to a wafer. Then the wafer was etched anisotropically by potassium hydroxide (KOH) to engrave trapezoidal trenches with an angle of 54.7º. Side wall roughness was mitigated by KOH etching and thermal oxidation that was used to generate a buffer layer for silicon nitride waveguide. The guiding material silicon nitride was then deposited by low pressure chemical vapor deposition. The waveguide was then patterned with a chemical template, with 20 nm gold particles being chemically attached to the functionalized poly(methyl methacrylate) domains. Since the particles attached only to the PMMA domains, they were confined to localized regions, therefore forcing the nanoparticles into clusters of various numbers and geometries. Experiments reveal that the waveguide has negligible nonlinear absorption loss, and its nonlinear refractive index can be greatly enhanced by gold nano clusters. The silicon nitride trench waveguide has large nonlinear refractive index, rendering itself promising for nonlinear applications.

Photoconductance-calibrated photoluminescence lifetime imaging of crystalline silicon

International Nuclear Information System (INIS)

Herlufsen, Sandra; Schmidt, Jan; Hinken, David; Bothe, Karsten; Brendel, Rolf

2008-01-01

We use photoluminescence (PL) measurements by a silicon charge-coupled device camera to generate high-resolution lifetime images of multicrystalline silicon wafers. Absolute values of the excess carrier density are determined by calibrating the PL image by means of contactless photoconductance measurements. The photoconductance setup is integrated in the camera-based PL setup and therefore identical measurement conditions are realised. We demonstrate the validity of this method by comparison with microwave-detected photoconductance decay measurements. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (Abstract Copyright [2008], Wiley Periodicals, Inc.)

Silicon pore optics for future x-ray telescopes

DEFF Research Database (Denmark)

Wille, Eric; Bavdaz, Marcos; Wallace, Kotska

2017-01-01

arcsec or better. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is being developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor...... industry. We present the recent upgrades made to the manufacturing processes and equipment, ranging from the manufacture of single mirror plates towards complete focusing mirror modules mounted in flight configuration, and results from first vibration tests. The performance of the mirror modules is tested...

MOS structures containing silicon nanoparticles for memory device applications

International Nuclear Information System (INIS)

Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S

2008-01-01

Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability

Ultra-low reflection porous silicon nanowires for solar cell applications

KAUST Repository

Najar, Adel; Charrier, Joë l; Pirasteh, Parastesh; Sougrat, Rachid

2012-01-01

% reflectivity of the starting silicon wafer drops to 0.1% recorded for more than 10 μm long PSiNWs. Models based on cone shape of nanowires located in a circular and rectangular bases were used to calculate the reflectance employing the Transfert Matrix

A continuous Czochralski silicon crystal growth system

Science.gov (United States)

Wang, C.; Zhang, H.; Wang, T. H.; Ciszek, T. F.

2003-03-01

Demand for large silicon wafers has driven the growth of silicon crystals from 200 to 300 mm in diameter. With the increasing silicon ingot sizes, melt volume has grown dramatically. Melt flow becomes more turbulent as melt height and volume increase. To suppress turbulent flow in a large silicon melt, a new Czochralski (CZ) growth furnace has been designed that has a shallow melt. In this new design, a crucible consists of a shallow growth compartment in the center and a deep feeding compartment around the periphery. Two compartments are connected with a narrow annular channel. A long crystal may be continuously grown by feeding silicon pellets into the dedicated feeding compartment. We use our numerical model to simulate temperature distribution and velocity field in a conventional 200-mm CZ crystal growth system and also in the new shallow crucible CZ system. By comparison, advantages and disadvantages of the proposed system are observed, operating conditions are determined, and the new system is improved.

Performance characteristics and radiation damage results from the Fermilab E706 silicon microstrip detector system

Energy Technology Data Exchange (ETDEWEB)

Engels, E Jr; Mani, S; Orris, D; Shepard, P F; Weerasundara, P D; Choudhary, B C; Joshi, U; Kapoor, V; Shivpuri, R; Baker, W

1989-07-01

A charged particle spectrometer containing a 7120-channel silicon microstrip detector system, one component of Fermilab experiment E706 to study direct photon production in hadron-hadron collisions, was utilized in a run in which 6 million events were recorded. We describe the silicon system, provide early results of track and vertex reconstruction, and present data on the radiation damage to the silicon wafers resulting from the narrow high intensity beam. (orig.).

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Directory of Open Access Journals (Sweden)

Gammon P.M.

2017-01-01

Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

The intrinsic gettering in neutron irradiation Czochralski-silicon

CERN Document Server

Li Yang Xian; Niu Ping Juan; Liu Cai Chi; Xu Yue Sheng; Yang Deren; Que Duan Lin

2002-01-01

The intrinsic gettering in neutron irradiated Czochralski-silicon is studied. The result shows that a denuded zone at the surface of the neutron irradiated Czochralski-silicon wafer may be formed through one-step short-time annealing. The width of the denuded zone is dependent on the annealing temperature and the dose of neutron irradiation, while it is irrelated to the annealing time in case the denuded zone is formed. The authors conclude that the interaction between the defects induced by neutron irradiation and the oxygen in the silicon accelerates the oxygen precipitation in the bulk, and becomes the dominating factor of the quick formation of intrinsic gettering. It makes the effect of thermal history as the secondary factor

Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding