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Sample records for thick plzt wafers

  1. PLZT Film Capacitors for Power Electronics and Energy Storage Applications

    Energy Technology Data Exchange (ETDEWEB)

    Ma, Beihai; Hu, Zhongqiang; Koritala, Rachel E.; Lee, Tae H.; Dorris, Stephen E.; Balachandran, Uthamalingam

    2015-12-01

    Ceramic film capacitors with high dielectric constant and high breakdown strength hold special promise for applications demanding high power density. By means of chemical solution deposition, we deposited ≈2-μm-thick films of lanthanum-doped lead zirconate titanate (PLZT) on LaNiO3-buffered Ni (LNO/Ni) foils and platinized silicon (PtSi) substrates. The dielectric properties and energy storage performance of the resulting samples were determined under a high level of applied electric field. X-ray diffraction stress analysis revealed that PLZT on LNO/Ni bears a compressive stress of ≈370 MPa while PLZT on PtSi endures a tensile stress of ≈250 MPa. Compressive stress was found to lead to heightened polarization, improved tunability, increased irreversible domain wall motion, and enhanced breakdown strength for PLZT deposited on the LNO/Ni as compared with the PtSi substrate. We observed a tunability of ≈55 and ≈40 % at room temperature under 100 kV/cm applied field, remanent polarization of ≈23.5 and ≈7.4 µC/cm^2, coercive electric field of ≈25.6 and ≈21.1 kV/cm, and dielectric breakdown strength of ≈2.6 and ≈1.5 MV/cm for PLZT deposited on LNO/Ni foils and PtSi substrates, respectively. A high recoverable energy density of ≈85 J/cm^3 and energy conversion efficiency of ≈65 % were measured on the PLZT film grown on LNO/Ni.

  2. Effect of diffraction and film-thickness gradients on wafer-curvature measurements of thin-film stress

    International Nuclear Information System (INIS)

    Breiland, W.G.; Lee, S.R.; Koleske, D.D.

    2004-01-01

    When optical measurements of wafer curvature are used to determine thin-film stress, the laser beams that probe the sample are usually assumed to reflect specularly from the curved surface of the film and substrate. Yet, real films are not uniformly thick, and unintended thickness gradients produce optical diffraction effects that steer the laser away from the ideal specular condition. As a result, the deflection of the laser in wafer-curvature measurements is actually sensitive to both the film stress and the film-thickness gradient. We present a Fresnel-Kirchhoff optical diffraction model of wafer-curvature measurements that provides a unified description of these combined effects. The model accurately simulates real-time wafer-curvature measurements of nonuniform GaN films grown on sapphire substrates by vapor-phase epitaxy. During thin-film growth, thickness gradients cause the reflected beam to oscillate asymmetrically about the ideal position defined by the stress-induced wafer curvature. This oscillating deflection has the same periodicity as the reflectance of the growing film, and the deflection amplitude is a function of the film-thickness gradient, the mean film thickness, the wavelength distribution of the light source, the illuminated spot size, and the refractive indices of the film and substrate. For typical GaN films grown on sapphire, misinterpretation of these gradient-induced oscillations can cause stress-measurement errors that approach 10% of the stress-thickness product; much greater errors occur in highly nonuniform films. Only transparent films can exhibit substantial gradient-induced deflections; strongly absorbing films are immune

  3. Coprecipitation-assisted hydrothermal synthesis of PLZT hollow nanospheres

    International Nuclear Information System (INIS)

    Zhu, Renqiang; Zhu, Kongjun; Qiu, Jinhao; Bai, Lin; Ji, Hongli

    2010-01-01

    Lanthanum-modified lead zirconate titanate Pb 1-x La x (Zr 1-y Ti y )O 3 (PLZT) hollow nanospheres have been successfully prepared via a template-free hydrothermal method using the well-mixed coprecipitated precursors and the KOH mineralizer. The structure, composition, and morphology of the PLZT hollow nanospheres were characterized by XRD (X-ray diffraction), ICP (inductive coupled plasma emission spectrometer), FTIR (Fourier transform infrared spectra), TG/DTA (thermogravimetric analysis and differential thermal analysis), TEM (transmission electron microscopy) and SEAD (selected area diffraction). The results show that the composition and the morphology control of the PLZT products are determined by the KOH concentration. The PLZT hollow nanospheres with uniform size of about 4 nm were synthesized in the presence of 5 M KOH. The crystalline nanoparticles can be prepared at dilute KOH, in contrast to the amorphous powders prepared at concentrated KOH. Formation mechanisms of the PLZT hollow nanospheres are also discussed.

  4. PLZT capacitor on glass substrate

    Science.gov (United States)

    Fairchild, M. Ray; Taylor, Ralph S.; Berlin, Carl W.; Wong, Celine W. K.; Ma, Beihai; Balachandran, Uthamalingam

    2016-01-05

    A lead-lanthanum-zirconium-titanate (PLZT) capacitor on a substrate formed of glass. The first metallization layer is deposited on a top side of the substrate to form a first electrode. The dielectric layer of PLZT is deposited over the first metallization layer. The second metallization layer deposited over the dielectric layer to form a second electrode. The glass substrate is advantageous as glass is compatible with an annealing process used to form the capacitor.

  5. Improvement of the thickness distribution of a quartz crystal wafer by numerically controlled plasma chemical vaporization machining

    International Nuclear Information System (INIS)

    Shibahara, Masafumi; Yamamura, Kazuya; Sano, Yasuhisa; Sugiyama, Tsuyoshi; Endo, Katsuyoshi; Mori, Yuzo

    2005-01-01

    To improve the thickness uniformity of thin quartz crystal wafer, a new machining process that utilizes an atmospheric pressure plasma was developed. In an atmospheric pressure plasma process, since the kinetic energy of ions that impinge to the wafer surface is small and the density of the reactive species is large, high-efficiency machining without damage is realized, and the thickness distribution is corrected by numerically controlled scanning of the quartz wafer to the localized high-density plasma. By using our developed machining process, the thickness distribution of an AT cut wafer was improved from 174 nm [peak to valley (p-v)] to 67 nm (p-v) within 94 s. Since there are no unwanted spurious modes in the machined quartz wafer, it was proved that the developed machining method has a high machining efficiency without any damage

  6. Develop techniques for ion implantation of PLZT [lead-lanthanum-zirconate-titanate] for adaptive optics

    International Nuclear Information System (INIS)

    Batishko, C.R.; Brimhall, J.L.; Pawlewicz, W.T.; Stahl, K.A.; Toburen, L.H.

    1987-09-01

    Research was conducted at Pacific Northwest Laboratory to develop high photosensitivity adaptive optical elements utilizing ion implanted lanthanum-doped lead-zirconate-titanate (PLZT). One centimeter square samples were prepared by implanting ferroelectric and anti-ferroelectric PLZT with a variety of species or combinations of species. These included Ne, O, Ni, Ne/Cr, Ne/Al, Ne/Ni, Ne/O, and Ni/O, at a variety of energies and fluences. An indium-tin oxide (ITO) electrode coating was designed to give a balance of high conductivity and optical transmission at near uv to near ir wavelengths. Samples were characterized for photosensitivity; implanted layer thickness, index of refraction, and density; electrode (ITO) conductivity; and in some cases, residual stress curvature. Thin film anti-ferroelectric PLZT was deposited in a preliminary experiment. The structure was amorphous with x-ray diffraction showing the beginnings of a structure at substrate temperatures of approximately 550 0 C. This report summarizes the research and provides a sampling of the data taken during the report period

  7. Ultraviolet-light-induced multi-physics behaviors of 0–3 polarized transparent PLZT plates: II. Finite element analysis and validation

    International Nuclear Information System (INIS)

    Luo, Quantian; Tong, Liyong

    2011-01-01

    This paper presents a novel finite element formulation for 0–3 polarized PbLaZrTi (PLZT) plates and a comparison of the predicted and measured bending displacements. The coupled multi-physics fields and Hamilton's principle for piezoelectric (PZT) materials are first extended to PLZT ceramics by including the anomalous photovoltaic and photo-thermal effects. The photo-induced non-uniform electrical field and mechanical strains across the thickness are modeled in the present finite element formulation for 0–3 polarized PLZT plates, and the associated actuator and sensor equations are derived. The transverse displacements of a 0–3 polarized PLZT plate are predicted using the present finite element formulation and compared with the measured data given in part I. A reasonably good correlation is noted for the transverse displacements at the ten measurement points

  8. PLZT capacitor and method to increase the dielectric constant

    Science.gov (United States)

    Taylor, Ralph S.; Fairchild, Manuel Ray; Balachjandran, Uthamalingam; Lee, Tae H.

    2017-12-12

    A ceramic-capacitor includes a first electrically-conductive-layer, a second electrically-conductive-layer arranged proximate to the first electrically-conductive-layer, and a dielectric-layer interposed between the first electrically-conductive-layer and the second electrically-conductive-layer. The dielectric-layer is formed of a lead-lanthanum-zirconium-titanate material (PLZT), wherein the PLZT is characterized by a dielectric-constant greater than 125, when measured at 25 degrees Celsius and zero Volts bias, and an excitation frequency of ten-thousand Hertz (10 kHz). A method for increasing a dielectric constant of the lead-lanthanum-zirconium-titanate material (PLZT) includes the steps of depositing PLZT to form a dielectric-layer of a ceramic-capacitor, and heating the ceramic-capacitor to a temperature not greater than 300.degree. C.

  9. Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

    Science.gov (United States)

    Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

    2018-05-01

    Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

  10. Development of a helmet-mounted PLZT thermal/flash protection system

    International Nuclear Information System (INIS)

    Harris, J.O. Jr.; Cutchen, J.T.; Pfoff, B.J.

    1976-01-01

    Sandia Laboratories is developing PLZT thermal/flash protective devices (TFPD's) goggles to prevent exposure and resultant eye damage from nuclear weapon detonations. The primary emphasis of the present program is to transfer technology and establish production capability for helmet-mounted PLZT/TFPD goggles for USAF flight crews, with a non-helmet-mounted configuration to follow. The first production units are anticipated in the fall of 1977. The operating principles of the PLZT/TFPD goggle device are briefly outlined, and the device configuration and operational characteristics are described

  11. The effect of physiologic aqueous solutions on the perovskite material lead-lanthanum-zirconium titanate (PLZT)

    Science.gov (United States)

    Foster, William J.; Meen, James K.; Fox, Donald A.

    2016-01-01

    Context Perovskite compounds, including Lead-Lanthanum-Zirconium Titanate (PLZT), have wide technological application because of their unique physical properties. The use of PLZT in neuro-prosthetic systems, such as retinal implants, have been discussed in a number of publications. Since inorganic lead is a retinotoxic compound that produces retinal degeneration, the long-term stability of PLZT in aqueous biological solutions must be determined. Objective We evaluated the stability and effects of prolonged immersion of a PLZT-coated crystal in a buffered balanced salt solution. Materials and Methods Scanning Electron Microscopy and Electron Dispersive Spectroscopy (EDS) using a JEOL JSM 5410 microscope equipped with EDS were utilized to evaluate the samples before and after prolonged immersion. Results We found that lead and other constituents of PLZT leached into the surrounding aqueous medium. Discussion By comparing the unit cell of PLZT with that of CaTiO3, which has been found to react with aqueous fluids, Lead is in the same site in PLZT as Ca is in CaTiO3. It is thus reasonable that PLZT will react with aqueous solutions. Conclusion The results suggest that PLZT must either be coated with a protective layer or is not appropriate for long-term in vivo or in vitro biological applications. PMID:22697294

  12. Ion-implanted PLZT ceramics: a new high-sensitivity image storage medium

    International Nuclear Information System (INIS)

    Peercy, P.S.; Land, C.E.

    1980-01-01

    Results were presented of our studies of photoferroelectric (PFE) image storage in H- and He-ion implanted PLZT (lead lanthanum zirconate titanate) ceramics which demonstrate that the photosensitivity of PLZT can be significantly increased by ion implantation in the ceramic surface to be exposed to image light. More recently, implantations of Ar and Ar + Ne into the PLZT surface have produced much greater photosensitivity enhancement. For example, the photosensitivity after implantation with 1.5 x 10 14 350 keV Ar/cm 2 + 1 x 10 15 500 keV Ne/cm 2 is increased by about four orders of magnitude over that of unimplanted PLZT. Measurements indicate that the photosensitivity enhancement in ion-implanted PLZT is controlled by implantation-produced disorder which results in marked decreases in dielectric constant and dark conductivity and changes in photoconductivity of the implanted layer. The effects of Ar- and Ar + Ne-implantation are presented along with a phenomenological model which describes the enhancement in photosensitivity obtained by ion implantation. This model takes into account both light- and implantation-induced changes in conductivity and gives quantitative agreement with the measured changes in the coercive voltage V/sub c/ as a function of near-uv light intensity for both unimplanted and implanted PLZT. The model, used in conjunction with calculations of the profiles of implantation-produced disorder, has provided the information needed for co-implanting ions of different masses, e.g., Ar and Ne, to improve photosensitivity

  13. Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

    International Nuclear Information System (INIS)

    Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

    2006-01-01

    The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

  14. A new approach to integrate PLZT thin films with micro-cantilevers

    Indian Academy of Sciences (India)

    Home; Journals; Sadhana; Volume 34; Issue 4. A new approach to integrate PLZT thin films with micro-cantilevers ... Different types of cantilever beams incorporating PLZT films have been successfully fabricated using 'lift-off' process and bulk micromachining technology. The proposed process can be advantageously ...

  15. The effect of physiologic aqueous solutions on the perovskite material lead-lanthanum-zirconium titanate (PLZT): potential retinotoxicity.

    Science.gov (United States)

    Foster, William J; Meen, James K; Fox, Donald A

    2013-03-01

    Perovskite compounds, including lead-lanthanum-zirconium titanate (PLZT), have wide technological application because of their unique physical properties. The use of PLZT in neuro-prosthetic systems, such as retinal implants, has been discussed in a number of publications. Since inorganic lead is a retinotoxic compound that produces retinal degeneration, the long-term stability of PLZT in aqueous biological solutions must be determined. We evaluated the stability and effects of prolonged immersion of a PLZT-coated crystal in a buffered balanced salt solution. Scanning Electron Microscopy and Electron Dispersive Spectroscopy (EDS) using a JEOL JSM 5410 microscope equipped with EDS were utilized to evaluate the samples before and after prolonged immersion. We found that lead and other constituents of PLZT leached into the surrounding aqueous medium. By comparing the unit cell of PLZT with that of CaTiO(3), which has been found to react with aqueous fluids, Lead is in the same site in PLZT as Ca is in CaTiO(3). It is thus reasonable that PLZT will react with aqueous solutions. The results suggest that PLZT must either be coated with a protective layer or is not appropriate for long-term in vivo or in vitro biological applications.

  16. Simulation and experimental determination of the macro-scale layer thickness distribution of electrodeposited Cu-line patterns on a wafer substrate

    DEFF Research Database (Denmark)

    Pantleon, Karen; Bossche, Bart van den; Purcar, Marius

    2005-01-01

    The impact of adjacent patterned zones with different active area densities on the current density and electrodeposited layer thickness distribution over a wafer substrate is examined, both by experiment and numerical simulation. The experiments consist in running an acid copper plating process o......) approach to compute the current density distribution over the electrodes. Experimental and computed layer thickness distributions are in very good agreement.......The impact of adjacent patterned zones with different active area densities on the current density and electrodeposited layer thickness distribution over a wafer substrate is examined, both by experiment and numerical simulation. The experiments consist in running an acid copper plating process...... on the patterned wafer, and layer thickness measurements by means of X-ray fluorescence (XRF) and atomic force microscopy (AFM). The simulations are based on a potential model approach taking into account electrolyte ohmic drop and electrode polarization effects, combined to a boundary element method (BEM...

  17. PLZT-based photovoltaic Piezoelectric Transformer with light feedback

    Energy Technology Data Exchange (ETDEWEB)

    Kozielski, L [University of Silesia, Dep. Materials Sc, 2, Sniezna St. Sosnowiec, 41-200 Poland (Poland); Adamczyk, M [University of Silesia, Institute Phys., 4, Uniwersytecka St. Katowice, 40-007 Poland (Poland); Erhart, J, E-mail: lucjan.kozielski@us.edu.pl [Technical University of Liberec, Studencka St. 2, CZ-461 17 Liberec (Czech Republic)

    2011-10-29

    Piezoelectric Transformer (PT) converts an electrical AC input voltage into ultrasonic vibrations and reconverts back to an output as AC voltage. Hard lead zirconate titanate (PZT) ceramics is typically used for fabrications of such devices. In case of lanthaniun ion La{sup 3+} addition in PZT solid solution we can achieve piezoelectric ceramics with good transparency exhibiting both optical Pockels and Kerr effects. Values of these coefficients in the PLZT system are much bigger than in LiNbO{sub 3} or SBN single crystals. Among the various PLZT compositions 8/65/35, near the morphotropic boundary, exhibit large electrooptic effect and thus have found applications in light shutters and displays. In the present study we have investigated radial mode piezoelectric transformer based on optically transparent PLZT8/65/35 ceramics. The effect of the UV light generated photovoltage and photostriction on the efficiency and voltage step-up ratio of piezoelectric transformer have been demonstrated. Novel functions of this device is proposed by superimposing two sophistically coupled effects of piezoelectricity and photostriction.

  18. Stacking effect on the ferroelectric properties of PZT/PLZT multilayer thin films formed by photochemical metal-organic deposition

    International Nuclear Information System (INIS)

    Park, Hyeong-Ho; Park, Hyung-Ho; Hill, Ross H.

    2004-01-01

    The ferroelectric properties of lead zirconate titanate (PZT) and lanthanum-doped lead zirconate titanate (PLZT) multilayer films formed by photochemical metal-organic deposition (PMOD) using photosensitive precursors have been characterized. The substitution of La for Pb was reported to induce improved ferroelectric properties, especially fatigue resistance, through the reduction of oxygen vacancies. The relation between La-substitution and the ferroelectric properties was investigated by characterization of the effect of the order of stacking four ferroelectric layers of PZT or PLZT in the multilayer films 4-PZT, PZT/2-PLZT/PZT, PLZT/2-PZT/PLZT, and 4-PLZT. The films with the PLZT layer at the top and bottom showed an improvement in the fatigue resistance. It was revealed that defect dipole such as O vacancy was reduced at the ferroelectric/Pt interface by doping with La. Also, the bottom layer, just on Pt substrate had a significant influence on the surface microstructure and growth orientation of ferroelectric film

  19. Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

    Science.gov (United States)

    Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

    2018-06-01

    Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

  20. Coherent spin transport through a 350 micron thick silicon wafer.

    Science.gov (United States)

    Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

    2007-10-26

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  1. Excimer Laser Deposition of PLZT Thin Films

    National Research Council Canada - National Science Library

    Petersen, GAry

    1991-01-01

    .... In order to integrate these devices into optical systems, the production of high quality thin films with high transparency and perovskite crystal structure is desired. This requires development of deposition technologies to overcome the challenges of depositing and processing PLZT thin films.

  2. PLZT thermal/flash protective goggles: device concepts and constraints

    International Nuclear Information System (INIS)

    Cutchen, J.T.

    1979-01-01

    In 1975 Sandia Laboratories began the design and development of PLZT Goggles for the US Air Force to provide protection from temporary flashblindness and permanent retinal burns caused by the brilliant flash of nuclear explosions. The user requirements, system and physical constraints, and use/storage environments were all considered in arriving at the final design goals. When the program began, there was no industrial capability to manufacture large-aperture PLZT materials or bonded lens assemblies. The technology has been established from a laboratory baseline in a brief period, and operational testing and evaluation by the Air Force has been completed. The goggles, identified as the EEU-2/P,, are now in production

  3. Preliminary Investigation of an Active PLZT Lens

    Science.gov (United States)

    Lightsey, W. D.; Peters, B. R.; Reardon, P. J.; Wong, J. K.

    2001-01-01

    The design, analysis and preliminary testing of a prototype Adjustable Focus Optical Correction Lens (AFOCL) is described. The AFOCL is an active optical component composed of solid state lead lanthanum-modified zirconate titanate (PLZT) ferroelectric ceramic with patterned indium tin oxide (ITO) transparent surface electrodes that modulate the refractive index of the PLZT to function as an electro-optic lens. The AFOCL was developed to perform optical re-alignment and wavefront correction to enhance the performance of Ultra-Lightweight Structures and Space Observatories (ULSSO). The AFOCL has potential application as an active optical component within a larger optical system. As such, information from a wavefront sensor would be processed to provide input to the AFOCL to drive the sensed wavefront to the desired shape and location. While offering variable and rapid focussing capability (controlled wavefront manipulation) similar to liquid crystal based spatial light modulators (SLM), the AFOCL offers some potential advantages because it is a solid-state, stationary, low-mass, rugged, and thin optical element that can produce wavefront quality comparable to the solid refractive lens it replaces. The AFOCL acts as a positive or negative lens by producing a parabolic phase-shift in the PLZT material through the application of a controlled voltage potential across the ITO electrodes. To demonstrate the technology, a 4 mm diameter lens was fabricated to produce 5-waves of optical power operating at 2.051 micrometer wavelength. Optical metrology was performed on the device to measure focal length, optical quality, and efficiency for a variety of test configurations. The data was analyzed and compared to theoretical data available from computer-based models of the AFOCL.

  4. The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

    Directory of Open Access Journals (Sweden)

    Gnilenko A. B.

    2012-02-01

    Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

  5. Frequency Invariability of (Pb,La)(Zr,Ti)O₃ Antiferroelectric Thick-Film Micro-Cantilevers.

    Science.gov (United States)

    An, Kun; Jin, Xuechen; Meng, Jiang; Li, Xiao; Ren, Yifeng

    2018-05-13

    Micro-electromechanical systems comprising antiferroelectric layers can offer both actuation and transduction to integrated technologies. Micro-cantilevers based on the (Pb 0.97 La 0.02 )(Zr 0.95 Ti 0.05 )O₃ (PLZT) antiferroelectric thick film are fabricated by the micro-nano manufacturing process, to utilize the effect of phase transition induced strain and sharp phase switch of antiferroelectric materials. When micro-cantilevers made of antiferroelectric thick films were driven by sweep voltages, there were two resonant peaks corresponding to the natural frequency shift from 27.8 to 27.0 kHz, before and after phase transition. This is the compensation principle for the PLZT micro-cantilever to tune the natural frequency by the amplitude modulation of driving voltage, rather than of frequency modulation. Considering the natural frequency shift about 0.8 kHz and the frequency tuning ability about 156 Hz/V before the phase transition, this can compensate the frequency shift caused by increasing temperature by tuning only the amplitude of driving voltage, when the ultrasonic micro-transducer made of antiferroelectric thick films works for such a long period. Therefore, antiferroelectric thick films with hetero-structures incorporated into PLZT micro-cantilevers not only require a lower driving voltage (no more than 40 V) than rival bulk piezoelectric ceramics, but also exhibit better performance of frequency invariability, based on the amplitude modulation.

  6. Scalable Active Optical Access Network Using Variable High-Speed PLZT Optical Switch/Splitter

    Science.gov (United States)

    Ashizawa, Kunitaka; Sato, Takehiro; Tokuhashi, Kazumasa; Ishii, Daisuke; Okamoto, Satoru; Yamanaka, Naoaki; Oki, Eiji

    This paper proposes a scalable active optical access network using high-speed Plumbum Lanthanum Zirconate Titanate (PLZT) optical switch/splitter. The Active Optical Network, called ActiON, using PLZT switching technology has been presented to increase the number of subscribers and the maximum transmission distance, compared to the Passive Optical Network (PON). ActiON supports the multicast slot allocation realized by running the PLZT switch elements in the splitter mode, which forces the switch to behave as an optical splitter. However, the previous ActiON creates a tradeoff between the network scalability and the power loss experienced by the optical signal to each user. It does not use the optical power efficiently because the optical power is simply divided into 0.5 to 0.5 without considering transmission distance from OLT to each ONU. The proposed network adopts PLZT switch elements in the variable splitter mode, which controls the split ratio of the optical power considering the transmission distance from OLT to each ONU, in addition to PLZT switch elements in existing two modes, the switching mode and the splitter mode. The proposed network introduces the flexible multicast slot allocation according to the transmission distance from OLT to each user and the number of required users using three modes, while keeping the advantages of ActiON, which are to support scalable and secure access services. Numerical results show that the proposed network dramatically reduces the required number of slots and supports high bandwidth efficiency services and extends the coverage of access network, compared to the previous ActiON, and the required computation time for selecting multicast users is less than 30msec, which is acceptable for on-demand broadcast services.

  7. Formation of cross-cutting structures with different porosity on thick silicon wafers

    Directory of Open Access Journals (Sweden)

    Vera A. Yuzova

    2017-06-01

    The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

  8. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    Science.gov (United States)

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  9. Direct thermal to electrical energy conversion using 9.5/65/35 PLZT ceramics in the ergodic relaxor phase.

    Science.gov (United States)

    Chin, Thomas K; Lee, Felix Y; McKinley, Ian M; Goljahi, Sam; Lynch, Christopher S; Pilon, Laurent

    2012-11-01

    This paper reports on direct thermal to electrical energy conversion by performing the Olsen cycle on 9.5/65/35 lead lanthanum zirconate titanate (PLZT). The Olsen cycle consists of two isothermal and two isoelectric field processes in the electric displacement versus electric field diagram. It was performed by alternatively dipping the material in hot and cold dielectric fluid baths under specified electric fields. The effects of applied electric field, sample thickness, electrode material, operating temperature, and cycle frequency on the energy and power densities were investigated. A maximum energy density of 637 ± 20 J/L/cycle was achieved at 0.054 Hz with a 250-μm-thick sample featuring Pt electrodes and coated with a silicone conformal coating. The operating temperatures varied between 3°C and 140°C and the electric field was cycled between 0.2 and 6.0 MV/m. A maximum power density of 55 ± 8 W/L was obtained at 0.125 Hz under the same operating temperatures and electric fields. The dielectric strength of the material, and therefore the energy and power densities generated, increased when the sample thickness decreased from 500 to 250 μm. Furthermore, the electrode material was found to have no significant effect on the energy and power densities for samples subject to the same operating temperatures and electric fields. However, samples with electrode material possessing thermal expansion coefficients similar to that of PLZT were capable of withstanding larger temperature swings. Finally, a fatigue test showed that the power generation gradually degraded when the sample was subject to repeated thermoelectrical loading.

  10. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  11. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  12. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Science.gov (United States)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  13. PLZT light transmittance memory driven with an asymmetric voltage pulse

    International Nuclear Information System (INIS)

    Inoue, Kazuhiko; Morita, Takeshi

    2010-01-01

    PLZT is a ferroelectric electro-optic material, which has been operated with a constant voltage supply to keep a certain optical property. In this study, we propose an optical transmittance memory effect by controlling the domain conditions. The keypoint is to use an asymmetric voltage pulse. In the positive direction, a sufficiently-large voltage is applied to align the polarization directions. After this operation, a relatively small light transmittance is memorized even after removing the electric field. On the other hand, in the negative direction, the amplitude of the voltage is adjusted to the coercive electric field. In this condition, the domain structure is almost the same as the depolarization state. With this voltage supply, the maximum light transmittance can be kept after removing the electric field. Using these voltage operations, the PLZT can obtain two light transmittance states depending on the domain structure. This memory effect should be useful for innovative optical scanners or shutters in the future.

  14. PLZT (9/65/35) sintering and characterization through the Pechini and partial oxalate processes

    International Nuclear Information System (INIS)

    Cerqueira, Marinalva; Nasar, Ricardo Silveira; Leite, Edson Roberto; Longo, Elson; Varela, Jode Arana

    1996-01-01

    Zr Ti O 4 obtained by the Pechini method was used as precursor for obtaining PLZT. An aqueous solution of oxalic acid was prepared with ZT, Pb (NO 3 ) 2 and La 2 O 3 particles. After the Pb C 2 O 4 and La 2 O 3 precipitation on ZT, the material was calcined and x-ray diffraction (XRD) showed the cubic phase of PLZT. This material was sintered in two steps and density about 8.0 g/cm 3 were obtained. After second sintering XRD showed the occurrence of tetragonal and rhombohedral phases. This was caused by an estequiometric deviation, however the material showed a high optical transparency. (author)

  15. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  16. Development of thin film measurement program of wafer for spin etcher

    International Nuclear Information System (INIS)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  17. Development of thin film measurement program of wafer for spin etcher

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  18. High frequency guided wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  19. Rhombohedral PLZT piezoelectric microfibers: a combined Raman and X-ray diffraction study

    Science.gov (United States)

    Kozielski, Lucjan; Buixaderas, Elena; Clemens, Frank

    2014-11-01

    A combination of micro- and macro-scale structural characterization methods was implemented for clarification of the influence of different sintering atmospheres on the structural properties of Pb1-xLax(ZryTi1-y)O3 (PLZT) fibers. Three powders, PbZrO3 and ZrO2 (PZ + Z), PbZrO3 (PZ), and PbZrO3 + PbO (PZ + P), were used for the generation of protective atmospheres. Vibrations corresponding to the rhombohedral phase in (Pb0.93La0.07)(Zr0.65Ti0.35)O3 fibers were measured and mapped along the section of the fibers by micro-Raman spectroscopy. Comparison of the Raman data with the evolution of the unit cell parameters indicates that the PZ + Z protective atmosphere ensures the best properties during the PLZT sintering at the temperature of 1250 °C for 6 hours.

  20. Thickness effect on the structure, grain size, and local piezoresponse of self-polarized lead lanthanum zirconate titanate thin films

    Energy Technology Data Exchange (ETDEWEB)

    Melo, M.; Araújo, E. B., E-mail: eudes@dfq.feis.unesp.br [Departamento de Física e Química, Faculdade de Engenharia de Ilha Solteira, UNESP—Univ. Estadual Paulista, 15385-000 Ilha Solteira, SP (Brazil); Shvartsman, V. V. [Institute for Materials Science, University Duisburg-Essen, 45141 Essen (Germany); Shur, V. Ya. [Institute of Natural Sciences, Ural Federal University, 620000 Ekaterinburg (Russian Federation); Kholkin, A. L. [Institute of Natural Sciences, Ural Federal University, 620000 Ekaterinburg (Russian Federation); Department of Physics and CICECO—Aveiro Institute of Materials, University of Aveiro, 3810-193 Aveiro (Portugal)

    2016-08-07

    Polycrystalline lanthanum lead zirconate titanate (PLZT) thin films were deposited on Pt/TiO{sub 2}/SiO{sub 2}/Si substrates to study the effects of the thickness and grain size on their structural and piezoresponse properties at nanoscale. Thinner PLZT films show a slight (100)-orientation tendency that tends to random orientation for the thicker film, while microstrain and crystallite size increases almost linearly with increasing thickness. Piezoresponse force microscopy and autocorrelation function technique were used to demonstrate the existence of local self-polarization effect and to study the thickness dependence of correlation length. The obtained results ruled out the bulk mechanisms and suggest that Schottky barriers near the film-substrate are likely responsible for a build-in electric field in the films. Larger correlation length evidence that this build-in field increases the number of coexisting polarization directions in larger grains leading to an alignment of macrodomains in thinner films.

  1. Rhombohedral PLZT piezoelectric microfibers: a combined Raman and X ray diffraction study

    Czech Academy of Sciences Publication Activity Database

    Kozielski, L.; Buixaderas, Elena; Clemens, F.

    2014-01-01

    Roč. 87, 10-11 (2014), s. 982-991 ISSN 0141-1594 R&D Projects: GA ČR GA13-15110S Institutional support: RVO:68378271 Keywords : Raman scattering * X-ray difraccion * piezoelectrics * microfibers * PLZT * extrusion method Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 0.954, year: 2014

  2. Magnetron target designs to improve wafer edge trench filling in ionized metal physical vapor deposition

    International Nuclear Information System (INIS)

    Lu Junqing; Yoon, Jae-Hong; Shin, Keesam; Park, Bong-Gyu; Yang Lin

    2006-01-01

    Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed. The model was validated based on the agreement between the model predictions and the reported experimental values for the asymmetric metal deposition at trench sidewalls near the wafer edge for a 200 mm wafer. This model could predict the thickness of the metal deposits across the wafer, the symmetry of the deposits on the trench sidewalls at any wafer location, and the angular distributions of the metal fluxes arriving at any wafer location. The model predictions for the 300 mm wafer indicate that as the target-to-wafer distance is shortened, the deposit thickness increases and the asymmetry decreases, however the overall uniformity decreases. Up to reasonable limits, increasing the target size and the sputtering intensity for the outer target portion significantly improves the uniformity across the wafer and the symmetry on the trench sidewalls near the wafer edge

  3. Raman spectroscopy and effective dielectric function in PLZT x/40/60

    Czech Academy of Sciences Publication Activity Database

    Buixaderas, Elena; Gregora, Ivan; Kamba, Stanislav; Petzelt, Jan; Kosec, M.

    2008-01-01

    Roč. 20, č. 34 (2008), 345229/1-345229/10 ISSN 0953-8984 R&D Projects: GA AV ČR IAA100100701; GA AV ČR KAN301370701; GA ČR(CZ) GA202/06/0403 Institutional research plan: CEZ:AV0Z10100520 Keywords : PLZT * Raman and Infrared spectroscopies * phonons * effective medium approximation Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 1.900, year: 2008

  4. PZT/PLZT - elastomer composites with improved piezoelectric voltage coefficient

    Science.gov (United States)

    Harikrishnan, K.; Bavbande, D. V.; Mohan, Dhirendra; Manoharan, B.; Prasad, M. R. S.; Kalyanakrishnan, G.

    2018-02-01

    Lead Zirconate Titanate (PZT) and Lanthanum-modified Lead Zirconate Titanate (PLZT) ceramic sensor materials are widely used because of their excellent piezoelectric coefficients. These materials are brittle, high density and have low achievable piezoelectric voltage coefficients. The density of the sintered ceramics shall be reduced by burnable polymeric sponge method. The achievable porosity level in this case is nearly 60 - 90%. However, the porous ceramic structure with 3-3 connectivity produced by this method is very fragile in nature. The strength of the porous structure is improved with Sylgard®-184 (silicone elastomer) by vacuum impregnation method maintaining the dynamic vacuum level in the range of -650 mm Hg. The elastomer Sylgard®-184 is having low density, low dielectric constant and high compliance (as a resultant stiffness of the composites is increased). To obtain a net dipole moment, the impregnated ceramic composites were subjected to poling treatment with varying conditions of D.C. field and temperature. The properties of the poled PZT/PLZT - elastomer composites were characterized with LCR meter for measuring the dielectric constant values (k), d33 meter used for measuring piezo-electric charge coefficient values (d33) and piezo-electric voltage coefficient (g33) values which were derived from d33 values. The voltage coefficient (g33) values of these composites are increased by 10 fold as compared to the conventional solid ceramics demonstrates that it is possible to fabricate a conformable detector.

  5. Energy-storage properties and electrocaloric effect of Pb(1-3x/2)LaxZr0.85Ti0.15O3 antiferroelectric thick films.

    Science.gov (United States)

    Zhao, Ye; Hao, Xihong; Zhang, Qi

    2014-07-23

    Antiferroelectric (AFE) thick (1 μm) films of Pb(1-3x/2)LaxZr0.85Ti0.15O3 (PLZT) with x = 0.08, 0.10, 0.12, and 0.14 were deposited on LaNiO3/Si (100) substrates by a sol-gel method. The dielectric properties, energy-storage performance, electrocaloric effect, and leakage current behavior were investigated in detail. With increasing La content, dielectric constant and saturated polarizations of the thick films were gradually decreased. A maximum recoverable energy-storage density of 38 J/cm(3) and efficiency of 71% were achieved in the thick films with x = 0.12 at room temperature. A large reversible adiabatic temperature change of ΔT = 25.0 °C was presented in the thick films with x = 0.08 at 127 °C at 990 kV/cm. Moreover, all the samples had a lower leakage current density below 10(-6) A/cm(2) at room temperature. These results indicated that the PLZT AFE thick films could be a potential candidate for applications in high energy-storage density capacitors and cooling devices.

  6. Controlling dielectric and relaxor-ferroelectric properties for energy storage by tuning Pb0.92La0.08Zr0.52Ti0.48O3 film thickness.

    Science.gov (United States)

    Brown, Emery; Ma, Chunrui; Acharya, Jagaran; Ma, Beihai; Wu, Judy; Li, Jun

    2014-12-24

    The energy storage properties of Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films grown via pulsed laser deposition were evaluated at variable film thickness of 125, 250, 500, and 1000 nm. These films show high dielectric permittivity up to ∼1200. Cyclic I-V measurements were used to evaluate the dielectric properties of these thin films, which not only provide the total electric displacement, but also separate contributions from each of the relevant components including electric conductivity (D1), dielectric capacitance (D2), and relaxor-ferroelectric domain switching polarization (P). The results show that, as the film thickness increases, the material transits from a linear dielectric to nonlinear relaxor-ferroelectric. While the energy storage per volume increases with the film thickness, the energy storage efficiency drops from ∼80% to ∼30%. The PLZT films can be optimized for different energy storage applications by tuning the film thickness to optimize between the linear and nonlinear dielectric properties and energy storage efficiency.

  7. Method of bistable optical information storage using antiferroelectric phase PLZT ceramics

    Science.gov (United States)

    Land, Cecil E.

    1990-01-01

    A method for bistable storage of binary optical information includes an antiferroelectric (AFE) lead lanthanum zirconate titanate (PLZT) layer having a stable antiferroelectric first phase and a ferroelectric (FE) second phase obtained by applying a switching electric field across the surface of the device. Optical information is stored by illuminating selected portions of the layer to photoactivate an FE to AFE transition in those portions. Erasure of the stored information is obtained by reapplying the switching field.

  8. A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

    International Nuclear Information System (INIS)

    Tang, Jiajie; Sun, Xiaowei; Luo, Le

    2011-01-01

    A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz

  9. Nonlinear analysis of 0-3 polarized PLZT microplate based on the new modified couple stress theory

    Science.gov (United States)

    Wang, Liming; Zheng, Shijie

    2018-02-01

    In this study, based on the new modified couple stress theory, the size- dependent model for nonlinear bending analysis of a pure 0-3 polarized PLZT plate is developed for the first time. The equilibrium equations are derived from a variational formulation based on the potential energy principle and the new modified couple stress theory. The Galerkin method is adopted to derive the nonlinear algebraic equations from governing differential equations. And then the nonlinear algebraic equations are solved by using Newton-Raphson method. After simplification, the new model includes only a material length scale parameter. In addition, numerical examples are carried out to study the effect of material length scale parameter on the nonlinear bending of a simply supported pure 0-3 polarized PLZT plate subjected to light illumination and uniform distributed load. The results indicate the new model is able to capture the size effect and geometric nonlinearity.

  10. SiC epitaxial layer growth in a novel multi-wafer VPE reactor

    Energy Technology Data Exchange (ETDEWEB)

    Burk, A.A. Jr.; O`Loughlin, M.J. [Northrop Grumman Advanced Technology Lab., Baltimore, MD (United States); Mani, S.S. [Northrop Grumman Science and Technology Center, Pittsburgh, PA (United States)

    1998-06-01

    Preliminary results are presented for SiC epitaxial layer growth employing a unique planetary SiC-VPE reactor. The high-throughput, multi-wafer (7 x 2-inch) reactor, was designed for atmospheric and reduced pressure operation at temperatures up to and exceeding 1600 C. Specular epitaxial layers have been grown in the reactor at growth rates from 3-5 {mu}m/hr. The thickest layer grown to data was 42 {mu}m. The layers exhibit minimum unintentional n-type doping of {proportional_to}1 x 10{sup 15} cm{sup -3}, room temperature mobilities of {proportional_to}1000 cm{sup 2}/Vs, and intentional n-type doping from {proportional_to}5 x 10{sup 15} cm{sup -3} to >1 x 10{sup 19} cm{sup -3}. Intrawafer thickness and doping uniformities of 4% and 7% (standard deviation/mean) have been obtained, respectively, on 35 mm diameter substrates. Recently, 3% thickness uniformity has been demonstrated on a 50 mm substrate. Within a run, wafer-to-wafer thickness deviation is {proportional_to}4-14%. Doping variation is currently larger, ranging as much as a factor of two from the highest to the lowest doped wafer. Continuing efforts to improve the susceptor temperature uniformity and reduce unintentional hydrocarbon generation to improve layer uniformity and reproducibility, are presented. (orig.) 18 refs.

  11. Comparative Performance of PLZT and PVDF Pyroelectric Sensors Used to the Thermal Characterization of Liquid Samples

    Directory of Open Access Journals (Sweden)

    Gemima Lara Hernandez

    2013-01-01

    Full Text Available Among the photothermal methods, the photopyroelectric (PPE technique is a suitable method to determine thermal properties of different kinds of samples ranging from solids to liquids and gases. Polyvinylidene difluoride (PVDF is one of the most frequently used pyroelectric sensors in PPE technique but has the disadvantage that it can be easily deformed by the sample weight. This deformation could add a piezoelectric effect to the thermal parameters assessment; also PVDF has a narrow temperature operation range when compared with ceramic pyroelectric sensors. In order to minimize possible piezoelectric effects due to sensor deformation, a ceramic of lanthanum modified lead zirconate (PLZT was used as pyroelectric sensor in the PPE technique. Then, thermal diffusivity of some liquid samples was measured, by using the PPE configuration that denominated the thermal wave resonator cavity (TWRC, with a PLZT ceramic as pyroelectric detector. The performance obtained with the proposed ceramic in the TWRC configuration was compared with that obtained with PVDF by using the same configuration.

  12. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  13. Influence of Si wafer thinning processes on (sub)surface defects

    Energy Technology Data Exchange (ETDEWEB)

    Inoue, Fumihiro, E-mail: fumihiro.inoue@imec.be [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Uedono, Akira [Division of Applied Physics, Faculty of Pure and Applied Science, University of Tsukuba, Tsukuba, Ibaraki 305-8573 (Japan)

    2017-05-15

    Highlights: • Mono-vacancy free Si-thinning can be accomplished by combining several thinning techniques. • The grinding damage needs to be removed prior to dry etching, otherwise vacancies remain in the Si at a depth around 0.5 to 2 μm after Si wafer thickness below 5 μm. • The surface of grinding + CMP + dry etching is equivalent mono vacancy level as that of grinding + CMP. - Abstract: Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5–2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in

  14. Physical model of evolution of oxygen subsystem of PLZT-ceramics at neutron irradiation and annealing

    CERN Document Server

    Kulikov, D V; Trushin, Y V; Veber, K V; Khumer, K; Bitner, R; Shternberg, A R

    2001-01-01

    The physical model of evolution of the oxygen subsystem defects of the ferroelectric PLZT-ceramics by the neutron irradiation and isochrone annealing is proposed. The model accounts for the effect the lanthanum content on the material properties. The changes in the oxygen vacancies concentration, calculated by the proposed model, agree well with the polarization experimental behavior by the irradiated material annealing

  15. Edge printability: techniques used to evaluate and improve extreme wafer edge printability

    Science.gov (United States)

    Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

    2004-05-01

    The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

  16. Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

    Science.gov (United States)

    Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

    This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

  17. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

    Science.gov (United States)

    Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

    2013-11-22

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  18. Homogeneity analysis of high yield manufacturing process of mems-based pzt thick film vibrational energy harvesters

    DEFF Research Database (Denmark)

    Lei, Anders; Xu, Ruichao; Pedersen, C.M.

    2011-01-01

    This work presents a high yield wafer scale fabrication of MEMS-based unimorph silicon/PZT thick film vibrational energy harvesters aimed towards vibration sources with peak frequencies in the range of a few hundred Hz. By combining KOH etching with mechanical front side protection, SOI wafer...... to accurately define the thickness of the silicon part of the harvester and a silicon compatible PZT thick film screen-printing technique, we are able to fabricate energy harvesters on wafer scale with a yield higher than 90%. The characterization of the fabricated harvesters is focused towards the full wafer....../mass-production aspect; hence the analysis of uniformity in harvested power and resonant frequency....

  19. A mathematical model for predicting photo-induced voltage and photostriction of PLZT with coupled multi-physics fields and its application

    International Nuclear Information System (INIS)

    Huang, J H; Wang, X J; Wang, J

    2016-01-01

    The primary purpose of this paper is to propose a mathematical model of PLZT ceramic with coupled multi-physics fields, e.g. thermal, electric, mechanical and light field. To this end, the coupling relationships of multi-physics fields and the mechanism of some effects resulting in the photostrictive effect are analyzed theoretically, based on which a mathematical model considering coupled multi-physics fields is established. According to the analysis and experimental results, the mathematical model can explain the hysteresis phenomenon and the variation trend of the photo-induced voltage very well and is in agreement with the experimental curves. In addition, the PLZT bimorph is applied as an energy transducer for a photovoltaic–electrostatic hybrid actuated micromirror, and the relation of the rotation angle and the photo-induced voltage is discussed based on the novel photostrictive mathematical model. (paper)

  20. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  1. Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

    Science.gov (United States)

    Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

    2017-11-01

    Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

  2. Semi-infinite photocarrier radiometric model for the characterization of semiconductor wafer

    International Nuclear Information System (INIS)

    Liu Xianming; Li Bincheng; Huang Qiuping

    2010-01-01

    The analytical expression is derived to describe the photocarrier radiometric (PCR) signal for a semi-infinite semiconductor wafer excited by a square-wave modulated laser. For comparative study, the PCR signals are calculated by the semi-infinite model and the finite thickness model with several thicknesses. The fitted errors of the electronic transport properties by semi-infinite model are analyzed. From these results it is evident that for thick samples or at high modulation frequency, the semiconductor can be considered as semi-infinite.

  3. Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

    Science.gov (United States)

    Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

    2018-03-01

    In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

  4. Determination of the thickness distribution of a graphene layer grown on a 2″ SiC wafer by means of Auger electron spectroscopy depth profiling

    International Nuclear Information System (INIS)

    Kotis, L.; Gurban, S.; Pecz, B.; Menyhard, M.; Yakimova, R.

    2014-01-01

    Highlights: • The thickness of graphene grown on SiC was determined by AES depth profiling. • The AES depth profiling verified the presence of buffer layer on SiC. • The presence of unsaturated Si bonds in the buffer layer has been shown. • Using multipoint analysis thickness distribution of the graphene on the wafer was determined. - Abstract: Auger electron spectroscopy (AES) depth profiling was applied for determination of the thickness of a macroscopic size graphene sheet grown on 2 in. 6H-SiC (0 0 0 1) by sublimation epitaxy. The measured depth profile deviated from the expected exponential form showing the presence of an additional, buffer layer. The measured depth profile was compared to the simulated one which allowed the derivation of the thicknesses of the graphene and buffer layers and the Si concentration of buffer layer. It has been shown that the graphene-like buffer layer contains about 30% unsaturated Si. The depth profiling was carried out in several points (diameter 50 μm), which permitted the constructing of a thickness distribution characterizing the uniformity of the graphene sheet

  5. Temperature Uniformity of Wafer on a Large-Sized Susceptor for a Nitride Vertical MOCVD Reactor

    International Nuclear Information System (INIS)

    Li Zhi-Ming; Jiang Hai-Ying; Han Yan-Bin; Li Jin-Ping; Yin Jian-Qin; Zhang Jin-Cheng

    2012-01-01

    The effect of coil location on wafer temperature is analyzed in a vertical MOCVD reactor by induction heating. It is observed that the temperature distribution in the wafer with the coils under the graphite susceptor is more uniform than that with the coils around the outside wall of the reactor. For the case of coils under the susceptor, we find that the thickness of the susceptor, the distance from the coils to the susceptor bottom and the coil turns significantly affect the temperature uniformity of the wafer. An optimization process is executed for a 3-inch susceptor with this kind of structure, resulting in a large improvement in the temperature uniformity. A further optimization demonstrates that the new susceptor structure is also suitable for either multiple wafers or large-sized wafers approaching 6 and 8 inches

  6. Wafer-scale synthesis of monolayer and few-layer MoS2 via thermal vapor sulfurization

    Science.gov (United States)

    Robertson, John; Liu, Xue; Yue, Chunlei; Escarra, Matthew; Wei, Jiang

    2017-12-01

    Monolayer molybdenum disulfide (MoS2) is an atomically thin, direct bandgap semiconductor crystal potentially capable of miniaturizing optoelectronic devices to an atomic scale. However, the development of 2D MoS2-based optoelectronic devices depends upon the existence of a high optical quality and large-area monolayer MoS2 synthesis technique. To address this need, we present a thermal vapor sulfurization (TVS) technique that uses powder MoS2 as a sulfur vapor source. The technique reduces and stabilizes the flow of sulfur vapor, enabling monolayer wafer-scale MoS2 growth. MoS2 thickness is also controlled with great precision; we demonstrate the ability to synthesize MoS2 sheets between 1 and 4 layers thick, while also showing the ability to create films with average thickness intermediate between integer layer numbers. The films exhibit wafer-scale coverage and uniformity, with electrical quality varying depending on the final thickness of the grown MoS2. The direct bandgap of grown monolayer MoS2 is analyzed using internal and external photoluminescence quantum efficiency. The photoluminescence quantum efficiency is shown to be competitive with untreated exfoliated MoS2 monolayer crystals. The ability to consistently grow wafer-scale monolayer MoS2 with high optical quality makes this technique a valuable tool for the development of 2D optoelectronic devices such as photovoltaics, detectors, and light emitters.

  7. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  8. Wafer scale lead zirconate titanate film preparation by sol-gel method using stress balance layer

    International Nuclear Information System (INIS)

    Lu Jian; Kobayashi, Takeshi; Yi Zhang; Maeda, Ryutaro; Mihara, Takashi

    2006-01-01

    In this paper, platinum/titanium (Pt/Ti) film was introduced as a residual stress balance layer into wafer scale thick lead zirconate titanate (PZT) film fabrication by sol-gel method. The stress developing in PZT film's bottom electrode as well as in PZT film itself during deposition were analyzed; the wafer curvatures, PZT crystallizations and PZT electric properties before and after using Pt/Ti stress balance layer were studied and compared. It was found that this layer is effective to balance the residual stress in PZT film's bottom electrode induced by thermal expansion coefficient mismatch and Ti diffusion, thus can notably reduce the curvature of 4-in. wafer from - 40.5 μm to - 12.9 μm after PZT film deposition. This stress balance layer was also found effective to avoid the PZT film cracking even when annealed by rapid thermal annealing with heating-rate up to 10.5 deg. C/s. According to X-ray diffraction analysis and electric properties characterization, crack-free uniform 1-μm-thick PZT film with preferred pervoskite (001) orientation, excellent dielectric constant, as high as 1310, and excellent remanent polarization, as high as 39.8 μC/cm 2 , can be obtained on 4-in. wafer

  9. Contacting graphene in a 200 mm wafer silicon technology environment

    Science.gov (United States)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  10. Boron impurity at the Si/SiO2 interface in SOI wafers and consequences for piezoresistive MEMS devices

    International Nuclear Information System (INIS)

    Nafari, A; Karlen, D; Enoksson, P; Rusu, C; Svensson, K

    2009-01-01

    In this work, the electrical performance of piezoresistive devices fabricated on thinned SOI wafers has been investigated. Specifically, SOI wafers manufactured with the standard bond-and-etch back method (BESOI), commonly used for MEMS fabrication, have been studied. Results from electrical measurements and SIMS characterization show the presence of a boron impurity close to the buried oxide, even on unprocessed wafers. If the boron impurity overlaps with the piezoresistors on the device, it can create non-defined pn-junctions and thus allow conduction through the substrate, leading to stray connections and excessive noise. The thickness of the boron impurity can extend up to several µm, thus setting a thickness limit for the thinnest parts of a MEMS device. This work shows how this impurity can fundamentally affect the functionality of piezoresistive devices. Design rules of how to avoid this are presented

  11. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  12. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    International Nuclear Information System (INIS)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  13. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  14. P/N InP solar cells on Ge wafers

    Science.gov (United States)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

  15. A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

    Energy Technology Data Exchange (ETDEWEB)

    Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

    2016-12-15

    In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  16. A PLZT Novel Sensor with Pt Implanted for Biomedical Application: Cardiac Micropulses Detection on Human Skin

    Directory of Open Access Journals (Sweden)

    Carlos O. González-Morán

    2017-01-01

    Full Text Available Advances in sensors for biomedical applications have been a great motivation. In this research, a PLZT (lead lanthanum zirconate titanate novel sensor with platinum wire implanted in its longitudinal section was developed through of the synthesis process based on powder technology. The raw materials as lead (PbO, lanthanum (La2O3, zircon (ZrO2, and titanium (TiO2 were used in the formation of the chemical composition (62.8% PbO, 4.5% La2O3, 24.2% ZrO2, and 8.5% TiO2. Then, these powders were submitted to mix-mechanical milling at high energy; cylindrical samples with the implant of the platinum wire were obtained with the load application. Finally, the compacted samples were sintered at 1200°C for 2 hours, then followed by a polarization potential of 1500 V/mm at 60°C to obtain a novel sensor. The density and porosity were evaluated using the Archimedes’ principle, while the mechanical properties such as fracture toughness value and Young’s modulus were determined by indentation and ultrasonic methods, respectively. A microscopic examination was also carried out to investigate the structural properties of the material. The PLZT novel sensor is electronically arranged for monitoring the cardiac pulses through a data acquisition system. The results obtained in this research are analyzed and discussed.

  17. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  18. Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

    Directory of Open Access Journals (Sweden)

    Shisheng Cai

    2017-03-01

    Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

  19. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    International Nuclear Information System (INIS)

    Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

  20. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  1. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    Science.gov (United States)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  2. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  3. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Science.gov (United States)

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  4. InGaAs-OI Substrate Fabrication on a 300 mm Wafer

    Directory of Open Access Journals (Sweden)

    Sebastien Sollier

    2016-09-01

    Full Text Available In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs wafer on insulator (InGaAs-OI substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM, scanning acoustic microscopy (SAM, and HR-XRD, to insure the crystalline quality of the post transferred layer.

  5. Mathematical model for predicting molecular-beam epitaxy growth rates for wafer production

    International Nuclear Information System (INIS)

    Shi, B.Q.

    2003-01-01

    An analytical mathematical model for predicting molecular-beam epitaxy (MBE) growth rates is reported. The mathematical model solves the mass-conservation equation for liquid sources in conical crucibles and predicts the growth rate by taking into account the effect of growth source depletion on the growth rate. Assumptions made for deducing the analytical model are discussed. The model derived contains only one unknown parameter, the value of which can be determined by using data readily available to MBE growers. Procedures are outlined for implementing the model in MBE production of III-V compound semiconductor device wafers. Results from use of the model to obtain targeted layer compositions and thickness of InP-based heterojunction bipolar transistor wafers are presented

  6. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  7. Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

    Energy Technology Data Exchange (ETDEWEB)

    Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

    1997-11-30

    This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

  8. Relation between film character and wafer alignment: critical alignment issues on HV device for VLSI manufacturing

    Science.gov (United States)

    Lo, Yi-Chuan; Lee, Chih-Hsiung; Lin, Hsun-Peng; Peng, Chiou-Shian

    1998-06-01

    Several continuous splits for wafer alignment target topography conditions to improve epitaxy film alignment were applied. The alignment evaluation among former layer pad oxide thickness (250 angstrom - 500 angstrom), drive oxide thickness (6000 angstrom - 10000 angstrom), nitride film thickness (600 angstrom - 1500 angstrom), initial oxide etch (fully wet etch, fully dry etch and dry plus wet etch) will be split to this experiment. Also various epitaxy deposition recipe such as: epitaxy source (SiHCl2 or SiCHCl3) and growth rate (1.3 micrometer/min approximately 2.0 micrometer/min) will be used to optimize the process window for alignment issue. All the reflectance signal and cross section photography of alignment target during NIKON stepper alignment process will be examined. Experimental results show epitaxy recipe plays an important role to wafer alignment. Low growth rate with good performance conformity epitaxy lead to alignment target avoid washout, pattern shift and distortion. All the results (signal monitor and film character) combined with NIKON's stepper standard laser scanning alignment system will be discussed in this paper.

  9. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  10. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  11. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  12. Homogeneity Analysis of a MEMS-based PZT Thick Film Vibration Energy Harvester Manufacturing Process

    DEFF Research Database (Denmark)

    Lei, Anders; Xu, Ruichao; Borregaard, Louise M.

    2012-01-01

    This paper presents a homogeneity analysis of a high yield wafer scale fabrication of MEMS-based unimorph silicon/PZT thick film vibration energy harvesters aimed towards vibration sources with peak vibrations in the range of around 300Hz. A wafer with a yield of 91% (41/45 devices) has been...

  13. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  14. Determination of wafer bonding mechanisms for plasma activated SiN films with x-ray reflectivity

    Energy Technology Data Exchange (ETDEWEB)

    Hayashi, S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Sandhu, R [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Wojtowicz, M [Northrop Grumman Space Technology, Redondo Beach, CA 90278 (United States); Sun, Y [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Hicks, R [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Goorsky, M S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States)

    2005-05-21

    Specular and diffuse x-ray reflectivity measurements were employed for wafer bonding studies of surface and interfacial reactions in {approx}800 A thick SiN films deposited on III-V substrates. CuK{sub {alpha}}{sub 1} radiation was employed for these measurements. The as-deposited films show very low surface roughness and uniform, high density SiN. Reflectivity measurements show that an oxygen plasma treatment converts the nitride surface to a somewhat porous SiO{sub x} layer (67 A thick, at 80% of SiO{sub 2} density), with confirmation of the oxide formation from x-ray photoelectron spectroscopy. Reactions at the bonded interface of two oxygen plasma treated SiN layers were examined using a bonded structure from which one of the III-V wafers is removed. Reflectivity measurements of bonded structures annealed at 150 deg. C and 300 deg. C show an increase in the SiO{sub x} layer density and thickness and even a density gradient across this interface. The increase in density is correlated with an increase in bond strength, where after the 300 deg. C anneal, a high interfacial bond strength, exceeding the bulk strength, was achieved.

  15. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    Science.gov (United States)

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  16. Carbon dioxide capture using resin-wafer electrodeionization

    Science.gov (United States)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  17. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  18. Tests of a silicon wafer based neutron collimator

    International Nuclear Information System (INIS)

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  19. Tests of a silicon wafer based neutron collimator

    CERN Document Server

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  20. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  1. A new method for wafer quality monitoring using semiconductor process big data

    Science.gov (United States)

    Sohn, Younghoon; Lee, Hyun; Yang, Yusin; Jun, Chungsam

    2017-03-01

    In this paper we proposed a new semiconductor quality monitoring methodology - Process Sensor Log Analysis (PSLA) - using process sensor data for the detection of wafer defectivity and quality monitoring. We developed exclusive key parameter selection algorithm and user friendly system which is able to handle large amount of big data very effectively. Several production wafers were selected and analyzed based on the risk analysis of process driven defects, for example alignment quality of process layers. Thickness of spin-coated material can be measured using PSLA without conventional metrology process. In addition, chip yield impact was verified by matching key parameter changes with electrical die sort (EDS) fail maps at the end of the production step. From this work, we were able to determine that process robustness and product yields could be improved by monitoring the key factors in the process big data.

  2. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  3. Stabilisation of a thin crystalline Si wafer solar cell using glass substrate; Duenne kristalline Silizium Wafer-Solarzelle mit Glastraeger stabilisiert

    Energy Technology Data Exchange (ETDEWEB)

    Muehlbauer, Maria

    2009-07-01

    An attempt was made to stabilise ultrathin crystalline silicon wafers (< 100 {mu}m) by a support material (BOROFLOAT33 by Schott Glas). It was found that the total serial resistance results mainly from the specific resistance of the back contact, and that especially the ultrathin solar cells have high recombination in the back. The ultrathin Si wafers also are slightly corrugated, which results in uneven joining of the Si wafer with the glass support. For optimisation, the solar cells of this specific types, with different thicknesses, were modelled in the one-dimensional simulation code PC1D, including all material-specific and electric properties. It was found that a slight reduction of the serial resistance will be enough for a significant improvement of the efficiency of the stabilized solar cell. With this knowledge, selective optimisation of the stabilised solar cells was possible, with the following results: 1. The improved temperature-time profile of the RTP step will improve the solar cell parameters for all Si thicknesses, which is assumed to be the result of better quality of the Al/Si back contact. 2. Thicker aluminium layers improved passivation on the back of solar cells with a thickness of 300 {mu}m and 120 {mu}m. In thinner stabilised solar cells, this measure resulted in enhanced formation of shunts and did not reduce the recombination rate on the back of the solar cell. 3. An additional optimisation step was the introduction of the so-called 'combined method' in which part of the aluminium layer is replaced by silkscreen paste. This combination, with adequate preparation, ensures uniform joining of the ultrathin silicon to the glass carrier. The resulting intermediate layers are highly homogeneous and have good fill factors and current densities for thin solar cells with a si thickness of 60 {mu}m. A decisive argument for the combined method is its near-100% reproducibility. [German] Ziel dieser Arbeit ist es sehr duenne kristalline

  4. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  5. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  6. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    Science.gov (United States)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  7. Imposition of defined states of stress on thin films by a wafer-curvature method; validation and application to aging Sn films

    Energy Technology Data Exchange (ETDEWEB)

    Stein, J., E-mail: Jendrik.Stein@de.bosch.com [Max Planck Institute for Intelligent Systems (formerly Max Planck Institute for Metals Research), Heisenbergstr. 3, 70569 Stuttgart (Germany); Robert Bosch GmbH, Automotive Electronics/Engineering Assembly and Interconnect Technology (AE/EAI2), Robert-Bosch-Str. 2, 71701 Schwieberdingen (Germany); Pascher, M. [Institute for Materials Science, University of Stuttgart, Pfaffenwaldring 55, 70569 Stuttgart (Germany); Welzel, U. [Max Planck Institute for Intelligent Systems (formerly Max Planck Institute for Metals Research), Heisenbergstr. 3, 70569 Stuttgart (Germany); Huegel, W. [Robert Bosch GmbH, Automotive Electronics/Engineering Assembly and Interconnect Technology (AE/EAI2), Robert-Bosch-Str. 2, 71701 Schwieberdingen (Germany); Mittemeijer, E.J. [Max Planck Institute for Intelligent Systems (formerly Max Planck Institute for Metals Research), Heisenbergstr. 3, 70569 Stuttgart (Germany); Institute for Materials Science, University of Stuttgart, Pfaffenwaldring 55, 70569 Stuttgart (Germany)

    2014-10-01

    A wafer-curvature method has been developed to subject thin films, deposited on (Si) substrates, to well defined and controllable loads in a contact-free manner. To this end, a custom-made glass pan (i.e. a roof-less cylinder with a connection piece for vacuum tubes) connected to a needle valve, a vacuum pump and a pressure gauge has been used as an experimental setup. By fixing the coated Si wafer on top of the glass cylinder and evacuating the glass cylinder to a defined low-pressure, a state of stress is imposed in the thin film due to bending of the wafer. It has been shown that the (initial) stress state of a film and its change, due to its bending with the help of the wafer-curvature method, can be analyzed accurately close to the wafer center by application of one of two independent X-ray diffraction techniques: i) conventional X-ray diffraction stress analysis (i.e. application of the well known sin{sup 2}ψ-method) to reflections originating from the film and ii) determination of the radii of curvature by rocking curve measurements utilizing reflections originating from the substrate. The validation of this stress-imposition method has been carried out with a tungsten film of 500 nm thickness, since tungsten is known to be (practically) intrinsically elastically isotropic. Further, the method has been applied to an electro-deposited, potentially whiskering, aging Sn film of 3 μm thickness where a combination of both stress-measurement techniques is essential for the determination of initial and (by wafer bending) imposed stresses. The results of the aging experiment of the Sn film under load have been discussed with respect to the current whisker-growth model. - Highlights: • A wafer-curvature method has been developed to subject thin films to defined loads. • Two X-ray diffraction techniques were employed for the analysis of stresses. • The wafer-curvature method was validated by application to a W film. • Application to a potentially whiskering

  8. Imposition of defined states of stress on thin films by a wafer-curvature method; validation and application to aging Sn films

    International Nuclear Information System (INIS)

    Stein, J.; Pascher, M.; Welzel, U.; Huegel, W.; Mittemeijer, E.J.

    2014-01-01

    A wafer-curvature method has been developed to subject thin films, deposited on (Si) substrates, to well defined and controllable loads in a contact-free manner. To this end, a custom-made glass pan (i.e. a roof-less cylinder with a connection piece for vacuum tubes) connected to a needle valve, a vacuum pump and a pressure gauge has been used as an experimental setup. By fixing the coated Si wafer on top of the glass cylinder and evacuating the glass cylinder to a defined low-pressure, a state of stress is imposed in the thin film due to bending of the wafer. It has been shown that the (initial) stress state of a film and its change, due to its bending with the help of the wafer-curvature method, can be analyzed accurately close to the wafer center by application of one of two independent X-ray diffraction techniques: i) conventional X-ray diffraction stress analysis (i.e. application of the well known sin 2 ψ-method) to reflections originating from the film and ii) determination of the radii of curvature by rocking curve measurements utilizing reflections originating from the substrate. The validation of this stress-imposition method has been carried out with a tungsten film of 500 nm thickness, since tungsten is known to be (practically) intrinsically elastically isotropic. Further, the method has been applied to an electro-deposited, potentially whiskering, aging Sn film of 3 μm thickness where a combination of both stress-measurement techniques is essential for the determination of initial and (by wafer bending) imposed stresses. The results of the aging experiment of the Sn film under load have been discussed with respect to the current whisker-growth model. - Highlights: • A wafer-curvature method has been developed to subject thin films to defined loads. • Two X-ray diffraction techniques were employed for the analysis of stresses. • The wafer-curvature method was validated by application to a W film. • Application to a potentially whiskering Sn

  9. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Science.gov (United States)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  10. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  11. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  12. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  13. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  14. Noncontact sheet resistance measurement technique for wafer inspection

    Science.gov (United States)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  15. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  16. Thick resist for MEMS processing

    Science.gov (United States)

    Brown, Joe; Hamel, Clifford

    2001-11-01

    The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging

  17. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  18. Process induced sub-surface damage in mechanically ground silicon wafers

    International Nuclear Information System (INIS)

    Yang Yu; De Munck, Koen; Teixeira, Ricardo Cotrin; Swinnen, Bart; De Wolf, Ingrid; Verlinden, Bert

    2008-01-01

    Micro-Raman spectroscopy, scanning electron microcopy, atomic force microscopy and preferential etching were used to characterize the sub-surface damage induced by the rough and fine grinding steps used to make ultra-thin silicon wafers. The roughly and ultra-finely ground silicon wafers were examined on both the machined (1 0 0) planes and the cross-sectional (1 1 0) planes. They reveal similar multi-layer damage structures, consisting of amorphous, plastically deformed and elastically stressed layers. However, the thickness of each layer in the roughly ground sample is much higher than its counterpart layers in the ultra-finely ground sample. The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30 MPa, respectively. In each case, the top amorphous layer is believed to be the result of sequential phase transformations (Si-I to Si-II to amorphous Si). These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in rough grinding, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks

  19. Thickness determination of large-area films of yttria-stabilized zirconia produced by pulsed laser deposition

    DEFF Research Database (Denmark)

    Pryds, N.; Christensen, Bo Toftmann; Bilde-Sørensen, Jørgen

    2006-01-01

    of the attenuation for various values of film thickness with the program CASINO. These results have been compared with direct measurements in the SEM of the film thickness on a cross-section on one of the wafers. The results of these measurements demonstrate the ability of this technique to accurately determine...

  20. Wafer-level packaging with compression-controlled seal ring bonding

    Science.gov (United States)

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  1. On the design and implementation of a wafer yield editor

    NARCIS (Netherlands)

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  2. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  3. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    Science.gov (United States)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  4. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  5. Chemical polishing of epitoxial silicon wafer

    International Nuclear Information System (INIS)

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  6. Wafer edge overlay control solution for N7 and beyond

    Science.gov (United States)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  7. Automated reticle inspection data analysis for wafer fabs

    Science.gov (United States)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  8. Thickness determination of large-area films of yttria-stabilized zirconia produced by pulsed laser deposition

    Energy Technology Data Exchange (ETDEWEB)

    Pryds, N. [Materials Research Department, Riso National Laboratory, DK-4000 Roskilde (Denmark)]. E-mail: nini.pryds@risoe.dk; Toftmann, B. [Department of Optics and Plasma Research, Riso National Laboratory, DK-4000 Roskilde (Denmark); Bilde-Sorensen, J.B. [Materials Research Department, Riso National Laboratory, DK-4000 Roskilde (Denmark); Schou, J. [Department of Optics and Plasma Research, Riso National Laboratory, DK-4000 Roskilde (Denmark); Linderoth, S. [Materials Research Department, Riso National Laboratory, DK-4000 Roskilde (Denmark)

    2006-04-30

    Films of yttria-stabilized zirconia (YSZ) on a polished silicon substrate of diameter up to 125 mm have been produced in a large-area pulsed laser deposition (PLD) setup under typical PLD conditions. The film thickness over the full film area has been determined by energy-dispersive X-ray spectrometry in a scanning electron microscope (SEM) with use of a method similar to one described by Bishop and Poole. The attenuation of the electron-induced X-rays from the Si wafer by the film was monitored at a number of points along a diameter and the thickness was determined by Monte Carlo simulations of the attenuation for various values of film thickness with the program CASINO. These results have been compared with direct measurements in the SEM of the film thickness on a cross-section on one of the wafers. The results of these measurements demonstrate the ability of this technique to accurately determine the thickness of a large film, i.e. up to diameters of 125 mm, in a relatively short time, without destroying the substrate, without the need of a standard sample and without the need of a flat substrate. We have also demonstrated that by controlling the deposition parameters large-area YSZ films with uniform thickness can be produced.

  9. Thickness determination of large-area films of yttria-stabilized zirconia produced by pulsed laser deposition

    International Nuclear Information System (INIS)

    Pryds, N.; Toftmann, B.; Bilde-Sorensen, J.B.; Schou, J.; Linderoth, S.

    2006-01-01

    Films of yttria-stabilized zirconia (YSZ) on a polished silicon substrate of diameter up to 125 mm have been produced in a large-area pulsed laser deposition (PLD) setup under typical PLD conditions. The film thickness over the full film area has been determined by energy-dispersive X-ray spectrometry in a scanning electron microscope (SEM) with use of a method similar to one described by Bishop and Poole. The attenuation of the electron-induced X-rays from the Si wafer by the film was monitored at a number of points along a diameter and the thickness was determined by Monte Carlo simulations of the attenuation for various values of film thickness with the program CASINO. These results have been compared with direct measurements in the SEM of the film thickness on a cross-section on one of the wafers. The results of these measurements demonstrate the ability of this technique to accurately determine the thickness of a large film, i.e. up to diameters of 125 mm, in a relatively short time, without destroying the substrate, without the need of a standard sample and without the need of a flat substrate. We have also demonstrated that by controlling the deposition parameters large-area YSZ films with uniform thickness can be produced

  10. Physical mechanisms of Cu-Cu wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  11. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  12. Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

    OpenAIRE

    Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

    2018-01-01

    Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

  13. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  14. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    International Nuclear Information System (INIS)

    Mou, Chun-Yueh; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-01-01

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate

  15. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mou, Chun-Yueh, E-mail: cymou165@gmail.com; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-06-30

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate.

  16. Guided ultrasonic wave beam skew in silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  17. Thermoelectric properties of boron and boron phosphide CVD wafers

    Energy Technology Data Exchange (ETDEWEB)

    Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

    1997-10-01

    Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

  18. Critical thickness of atomically ordered III-V alloys

    Energy Technology Data Exchange (ETDEWEB)

    France, R. M.; McMahon, W. E.; Guthrey, H. L. [National Renewable Energy Laboratory, 15013 Denver West Parkway, Golden, Colorado 80401 (United States)

    2015-10-12

    The critical thickness model is modified with a general boundary energy that describes the change in bulk energy as a dislocation regularly alters the atomic structure of an ordered material. The model is evaluated for dislocations gliding through CuPt-ordered GaInP and GaInAs, where the boundary energy is negative and the boundary is stable. With ordering present, the critical thickness is significantly lowered and remains finite as the mismatch strain approaches zero. The reduction in critical thickness is most significant when the order parameter is greatest and the amount of misfit energy is low. The modified model is experimentally validated for low-misfit GaInP epilayers with varying order parameters using in situ wafer curvature and ex situ cathodoluminescence. With strong ordering, relaxation begins at a lower thickness and occurs at a greater rate, which is consistent with a lower critical thickness and increased glide force. Thus, atomic ordering is an important consideration for the stability of lattice-mismatched devices.

  19. Dislocation behavior of surface-oxygen-concentration controlled Si wafers

    International Nuclear Information System (INIS)

    Asazu, Hirotada; Takeuchi, Shotaro; Sannai, Hiroya; Sudo, Haruo; Araki, Koji; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira

    2014-01-01

    We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer. - Highlights: • Surface-oxygen-concentration controlled Si wafers have been made. • The oxygen concentration was controlled by high temperature rapid thermal oxidation. • Dislocation behavior in the surface area of the Si wafers has been investigated. • Rosette size decreased with increasing of interstitial oxygen atoms. • The interstitial oxygen atoms have a pinning effect of dislocations at the surface

  20. Cohesive zone model for direct silicon wafer bonding

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  1. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  2. Evaluation of the viscoelastic behaviour and glass/mould interface friction coefficient in the wafer based precision glass moulding

    DEFF Research Database (Denmark)

    Sarhadi, Ali; Hattel, Jesper Henri; Hansen, Hans Nørgaard

    2014-01-01

    -placements, internal diameter and thickness of the rings are measured during the tests. Viscoelastic andstructural relaxation behaviour of the glass are implemented into the ABAQUS FEM software through aFORTRAN material subroutine (UMAT) and the FE model is validated with a sandwich seal test. Then, byFE simulation...... of the ring compression test and comparison of the experimental creep with the simulatedone in an iterative procedure, viscoelastic parameters of the glass material are characterized. Finally,interfacial glass/mould friction coefficients at different temperatures are determined through FEM basedfriction...... curves combined with experimental data points. The obtained viscoelastic parameters and inter-facial friction coefficients can later be employed for prediction of the final shape/size as well as the stressdistribution in the glass wafer during a real wafer based precision glass moulding process. © 2014...

  3. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  4. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Science.gov (United States)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  5. Homogeneous transparent conductive ZnO:Ga by ALD for large LED wafers

    Energy Technology Data Exchange (ETDEWEB)

    Szabó, Zoltán; Baji, Zsófia [MTA EK Institute of Technical Physics and Materials Science, Konkoly Thege M. út 29-33, 1121 Budapest (Hungary); Basa, Péter [Semilab Semiconductor Physics Laboratory Co. Ltd., Prielle K. u. 2, H-1117 Budapest (Hungary); Czigány, Zsolt; Bársony, István [MTA EK Institute of Technical Physics and Materials Science, Konkoly Thege M. út 29-33, 1121 Budapest (Hungary); Wang, Hsin-Ying [Epistar corporation No 5, Li-hsin 5th Rd., Hsinchu Science Park, Hsinchu 300, Taiwan (China); Volk, János, E-mail: volk@mfa.kfki.hu [MTA EK Institute of Technical Physics and Materials Science, Konkoly Thege M. út 29-33, 1121 Budapest (Hungary)

    2016-08-30

    Highlights: • Highly conductive, transparent GZO layers were deposited by ALD. • The ALD layers show superior thickness and sheet resistance homogeneity for 4” wafers. • A two-step ALD deposition technique was proposed and demonstrated to improve the quality of GZO/p-GaN interface. - Abstract: Highly conductive and uniform Ga doped ZnO (GZO) films were prepared by atomic layer deposition (ALD) as transparent conductive layers for InGaN/GaN LEDs. The optimal Ga doping concentration was found to be 3 at%. Even for 4” wafers, the TCO layer shows excellent homogeneity of film resistivity (0.8 %) according to Eddy current and spectroscopic ellipsometry mapping. This makes ALD a favourable technique over concurrent methods like MBE and PLD where the up-scaling is problematic. In agreement with previous studies, it was found that by an annealing treatment the quality of the GZO/p-GaN interface can be improved, although it causes the degradation of TCO conductivity. Therefore, a two-step ALD deposition technique was proposed and demonstrated: a “buffer layer” deposited and annealed first was followed by a second deposition step to maintain the high conductivity of the top layer.

  6. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Directory of Open Access Journals (Sweden)

    N. Daix

    2014-08-01

    Full Text Available We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  7. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Energy Technology Data Exchange (ETDEWEB)

    Daix, N., E-mail: dai@zurich.ibm.com; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J. [IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Hartmann, J. M. [CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France); Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D. [IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  8. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Science.gov (United States)

    Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  9. Reticle variation influence on manufacturing line and wafer device performance

    Science.gov (United States)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  10. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  11. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  12. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    International Nuclear Information System (INIS)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  13. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    Science.gov (United States)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  14. Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

    Science.gov (United States)

    Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

    2013-01-02

    Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

  15. Preparation of 2-in.-diameter (001) β-Ga2O3 homoepitaxial wafers by halide vapor phase epitaxy

    Science.gov (United States)

    Thieu, Quang Tu; Wakimoto, Daiki; Koishikawa, Yuki; Sasaki, Kohei; Goto, Ken; Konishi, Keita; Murakami, Hisashi; Kuramata, Akito; Kumagai, Yoshinao; Yamakoshi, Shigenobu

    2017-11-01

    The homoepitaxial growth of thick β-Ga2O3 layers on 2-in.-diameter (001) wafers was demonstrated by halide vapor phase epitaxy. Growth rates of 3 to 4 µm/h were confirmed for growing intentionally Si-doped n-type layers. A homoepitaxial layer with an average thickness and carrier concentration of 10.9 µm and 2.7 × 1016 cm-3 showed standard deviations of 1.8 µm (16.5%) and 0.5 × 1016 cm-3 (19.7%), respectively. Ni Schottky barrier diodes fabricated directly on a 5.3-µm-thick homoepitaxial layer with a carrier concentration of 3.4 × 1016 cm-3 showed reasonable reverse and forward characteristics, i.e., breakdown voltages above 200 V and on-resistances of 3.8-7.7 mΩ cm2 at room temperature.

  16. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    Science.gov (United States)

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  17. Study of Si wafer surfaces irradiated by gas cluster ion beams

    International Nuclear Information System (INIS)

    Isogai, H.; Toyoda, E.; Senda, T.; Izunome, K.; Kashima, K.; Toyoda, N.; Yamada, I.

    2007-01-01

    The surface structures of Si (1 0 0) wafers subjected to gas cluster ion beam (GCIB) irradiation have been analyzed by cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM). GCIB irradiation is a promising technique for both precise surface etching and planarization of Si wafers. However, it is very important to understand the crystalline structure of Si wafers after GCIB irradiation. An Ar-GCIB used for the physically sputtering of Si atoms and a SF 6 -GCIB used for the chemical etching of the Si surface are also analyzed. The GCIB irradiation increases the surface roughness of the wafers, and amorphous Si layers are formed on the wafer surface. However, when the Si wafers are annealed in hydrogen at a high temperature after the GCIB irradiation, the surface roughness decreases to the same level as that before the irradiation. Moreover, the amorphous Si layers disappear completely

  18. Dielectric properties of PLZT-x/65/35 (2≤x≤13 under mechanical stress, electric field and temperature loading

    Directory of Open Access Journals (Sweden)

    K. Pytel

    2013-01-01

    Full Text Available We investigated the effect of uniaxial pressure (0÷1000 bars applied parallely to the ac electric field on dielectric properties of PLZT-x/65/35 (2≤x≤13 ceramics. There was revealed a significant effect of the external stress on these properties. The application of uniaxial pressure leads to the change of the peak intensity of the electric permittivity (ϵ, of the frequency dispersion as well as of the dielectric hysteresis. The peak intensity ϵ becomes diffused/sharpened and shifts to a higher/lower temperatures with increasing the pressure. It was concluded that the application of uniaxial pressure induces similar effects as increasing the Ti ion concentration in PZT system. We interpreted our results based on the domain switching processes under the action of combined electromechanical loading.

  19. Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

    Science.gov (United States)

    Norris, D J; Myronov, M; Leadley, D R; Walther, T

    2017-12-01

    We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

  20. Wafer Cakes of Improved Amino Acid Structure

    Directory of Open Access Journals (Sweden)

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  1. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  2. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  3. Effect of Processing Parameters on Thickness of Columnar Structured Silicon Wafers Directly Grown from Silicon Melts

    Directory of Open Access Journals (Sweden)

    Jin-Seok Lee

    2012-01-01

    Full Text Available In order to obtain optimum growth conditions for desired thickness and more effective silicon feedstock usage, effects of processing parameters such as preheated substrate temperatures, time intervals, moving velocity of substrates, and Ar gas blowing rates on silicon ribbon thickness were investigated in the horizontal growth process. Most of the parameters strongly affected in the control of ribbon thickness with columnar grain structure depended on the solidification rate. The thickness of the silicon ribbon decreased with an increasing substrate temperature, decreasing time interval, and increasing moving velocity of the substrate. However, the blowing of Ar gas onto a liquid layer existing on the surface of solidified ribbon contributed to achieving smooth surface roughness but did not closely affect the change of ribbon thickness in the case of a blowing rate of ≥0.65 Nm3/h because the thickness of the solidified layer was already determined by the exit height of the reservoir.

  4. Lamb wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  5. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    Directory of Open Access Journals (Sweden)

    Zhuhao Gong

    2018-02-01

    Full Text Available A radio-frequency micro-electro-mechanical system (RF MEMS wafer-level packaging (WLP method using pre-patterned benzo-cyclo-butene (BCB polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100–400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz.

  6. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  7. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  8. I-line stepper based overlay evaluation method for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  9. Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

    International Nuclear Information System (INIS)

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

    2013-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

  10. MEMS-based thick film PZT vibrational energy harvester

    DEFF Research Database (Denmark)

    Lei, Anders; Xu, Ruichao; Thyssen, Anders

    2011-01-01

    We present a MEMS-based unimorph silicon/PZT thick film vibrational energy harvester with an integrated proof mass. We have developed a process that allows fabrication of high performance silicon based energy harvesters with a yield higher than 90%. The process comprises a KOH etch using a mechan......We present a MEMS-based unimorph silicon/PZT thick film vibrational energy harvester with an integrated proof mass. We have developed a process that allows fabrication of high performance silicon based energy harvesters with a yield higher than 90%. The process comprises a KOH etch using...... a mechanical front side protection of an SOI wafer with screen printed PZT thick film. The fabricated harvester device produces 14.0 μW with an optimal resistive load of 100 kΩ from 1g (g=9.81 m s-2) input acceleration at its resonant frequency of 235 Hz....

  11. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  12. Making Porous Luminescent Regions In Silicon Wafers

    Science.gov (United States)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  13. Residual stress in thick low-pressure chemical-vapor deposited polycrystalline SiC coatings on Si substrates

    Science.gov (United States)

    Choi, D.; Shinavski, R. J.; Steffier, W. S.; Spearing, S. M.

    2005-04-01

    Residual stress in thick coatings of polycrystalline chemical-vapor deposited SiC on Si substrates is a key variable that must be controlled if SiC is to be used in microelectromechanical systems. Studies have been conducted to characterize the residual stress level as a function of deposition temperature, Si wafer and SiC coating thickness, and the ratios of methyltrichlorosilane to hydrogen and hydrogen chloride. Wafer curvature was used to monitor residual stress in combination with a laminated plate analysis. Compressive intrinsic (growth) stresses were measured with magnitudes in the range of 200-300MPa; however, these can be balanced with the tensile stress due to the thermal-expansion mismatch to leave near-zero stress at room temperature. The magnitude of the compressive intrinsic stress is consistent with previously reported values of surface stress in combination with the competition between grain-boundary energy and elastic strain energy.

  14. Wafer plane inspection for advanced reticle defects

    Science.gov (United States)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  15. Uniform fabrication of thick SU-8 patterns on small-sized wafers for micro-optics applications

    Science.gov (United States)

    Abada, S.; Reig, B.; Daran, E.; Doucet, JB; Camps, T.; Charlot, S.; Bardinal, V.

    2014-05-01

    This paper reports on an alternative method for precise and uniform fabrication of 100μm-thick SU-8 microstructures on small-sized or non-circular samples. Standard spin-coating of high-viscosity resists is indeed known to induce large edge beads, leading to an air gap between the mask and the SU-8 photo-resist surface during UV photolithography. This results in a non uniform thickness deposition and in a poor pattern definition. This problem becomes highly critical in the case of small-sized samples. To overcome it, we have developed a soft thermal imprint method based on the use of a nano-imprint equipment and applicable whatever sample fragility, shape and size (from 2cm to 6 inches). After final photolithography, the SU8 pattern thickness variation profile is measured. Thickness uniformity is improved from 30% to 5% with a 5μm maximal deviation to the target value over 2cm-long samples.

  16. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  17. 120 mm Single-crystalline perovskite and wafers: towards viable applications

    Institute of Scientific and Technical Information of China (English)

    Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

    2017-01-01

    As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75% RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

  18. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  19. Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding

    Directory of Open Access Journals (Sweden)

    Xiaoqing Wang

    2016-12-01

    Full Text Available This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs by wafer direct bonding, which utilizes both the wet chemical and O2plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC substrates.

  20. Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2013-04-01

    Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

  1. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  2. Complete Fabrication of a Traversable 3 µm Thick NbN Film Superconducting Coil with Cu plated layer of 42m in Length in a Spiral Three-Storied Trench Engraved in a Si Wafer of 76.2 mm in Diameter Formed by MEMS Technology for a Compact SMES with High Energy Storage Volume Density

    Science.gov (United States)

    Suzuki, Yasuhiro; Iguchi, Nobuhiro; Adachi, Kazuhiro; Ichiki, Akihisa; Hioki, Tatsumi; Hsu, Che-Wei; Sato, Ryoto; Kumagai, Shinya; Sasaki, Minoru; Noh, Joo-Hyong; Sakurahara, Yuuske; Okabe, Kyohei; Takai, Osamu; Honma, Hideo; Watanabe, Hideo; Sakoda, Hitoshi; Sasagawa, Hiroaki; Doy, Hideyuki; Zhou, Shuliang; Hori, H.; Nishikawa, Shigeaki; Nozaki, Toshihiro; Sugimoto, Noriaki; Motohiro, Tomoyoshi

    2017-09-01

    Based on the concept of a novel approach to make a compact SMES unit composed of a stack of Si wafers using MEMS process proposed previously, a complete fabrication of a traversable 3 µam thick NbN film superconducting coil lined with Cu plated layer of 42m in length in a spiral three-storied trench engraved in and extended over a whole Si-wafer of 76.2 mm in diameter was attained for the first time. With decrease in temperature, the DC resistivity showed a metallic decrease indicating the current pass was in the Cu plated layer and then made a sudden fall to residual contact resistance indicating the shift of current pass from the Cu plated layer to the NbN film at the critical temperature Tc of 15.5K by superconducting transition. The temperature dependence of I-V curve showed the increase in the critical current with decrease in the temperature and the highest critical current measured was 220 mA at 4K which is five times as large as that obtained in the test fabrication as the experimental proof of concept presented in the previous report. This completion of a one wafer superconducting NbN coil is an indispensable step for the next proof of concept of fabrication of series-connected two wafer coils via superconductive joint which will read to series connected 600 wafer coils finally, and for replacement of NbN by high Tc superconductor such as YBa2Cu3O7-x for operation under the cold energy of liquid hydrogen or liquid nitrogen.

  3. Wafer-shape metrics based foundry lithography

    Science.gov (United States)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  4. Ferroelectric and Piezoelectric properties of (111) oriented lanthanum modified lead zirconate titanate film

    International Nuclear Information System (INIS)

    Dutta, Soma; Antony Jeyaseelan, A.; Sruthi, S.

    2014-01-01

    Lanthanum modified lead zirconate titanate (PLZT) thick film with molecular formula of Pb 0.92 La 0.08 (Zr 0.52 Ti 0.48 ) 0.98 O 3 was grown preferentially along (111) direction on Pt/SiO 2 /Si (platinum/silicon oxide/silicon) substrate by spin coating of chemical solution. The directional growth of the film was facilitated by platinum (Pt) (111) template and rapid thermal annealing. X-ray diffraction pattern and atomic force microscopy revealed the preferential growth of the PLZT film. The film was characterized for ferroelectric and detailed piezoelectric properties in a parallel plate capacitor (metal–PLZT–metal) configuration. Ferroelectric characterization of the film showed saturated hysteresis loop with remanent polarization and coercive electric field values of 10.14 μC/cm 2 and 42 kV/cm, respectively, at an applied field of 300 kV/cm. Longitudinal piezoelectric coefficient (d 33,f ) was measured by employing converse piezoelectric effect where electrical charge response and displacement were measured with electrical voltage excitation on the sample electrodes. The effective transverse piezoelectric coefficient (e 31,f ) was derived from charge measurement with an applied mechanical excitation strain by using the four point bending method. d 33,f and e 31,f coefficients of PLZT films were found to be 380 pm/V and − 0.831 C/m 2 respectively. - Highlights: • PLZT (111) film is prepared by spin coating of chemical sol on Pt (111) template. • Piezoelectric d 33 value (380 pm/V) of PLZT film is found 20% higher than PZT. • Transverse piezocoefficient e 31,f of PLZT film is reported for the first time

  5. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Science.gov (United States)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  6. Pulse plating of Pt on n-GaAs (1 0 0) wafer surfaces: Synchrotron induced photoelectron spectroscopy and XPS of wet fabrication processes

    International Nuclear Information System (INIS)

    Ensling, D.; Hunger, R.; Kraft, D.; Mayer, Th.; Jaegermann, W.; Rodriguez-Girones, M.; Ichizli, V.; Hartnagel, H.L.

    2003-01-01

    Preparation steps of Pt/n-GaAs Schottky contacts as applied in the fabrication process of varactor diode arrays for THz applications are analysed by photoelectron spectroscopy. Pulsed cathodic deposition of Pt onto GaAs (1 0 0) wafer surfaces from acidic solution has been studied by core level photoelectron spectroscopy using different excitation energies. A laboratory AlKα source as well as synchrotron radiation of hν=130 and 645 eV at BESSY was used. Chemical analyses and semiquantitative estimates of layer thickness are given for the natural oxide of an untreated wafer surface, a surface conditioning NH 3 etching step, and stepwise pulse plating of Pt. The structural arrangement of the detected species and interface potentials are considered

  7. Wafer-Level Vacuum Packaging of Smart Sensors

    OpenAIRE

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging...

  8. A study of UO2 wafer fuel for very high-power research reactors

    International Nuclear Information System (INIS)

    Hsieh, T.C.; Jankus, V.Z.; Rest, J.; Billone, M.C.

    1983-01-01

    The Reduced Enrichment Research and Test Reactor Program is aimed at reducing fuel enrichment to 2 caramel fuel is one of the most promising new types of reduced-enrichment fuel for use in research reactors with very high power density. Parametric studies have been carried out to determine the maximum specific power attainable without significant fission-gas release for UO 2 wafers ranging from 0.75 to 1.50 mm in thickness. The results indicate that (1) all the fuel designs considered in this study are predicted not to fail under full power operation up to a burnup, of 1.9x10 21 fis/cm 3 ; (2) for all fuel designs, failure is predicted at approximately the same fuel centerline temperature for a given burnup; (3) the thinner the wafer, the wider the margin for fuel specific power between normal operation and increased-power operation leading to fuel failure; (4) increasing the coolant pressure in the reactor core could improve fuel performance by maintaining the fuel at a higher power level without failure for a given burnup; and (5) for a given power level, fuel failure will occur earlier at a higher cladding surface temperature and/or under power-cycling conditions. (author)

  9. Fabrication of an integrated ΔE-E-silicon detector by wafer bonding using cobalt disilicide

    International Nuclear Information System (INIS)

    Thungstroem, G.; Veldhuizen, E.J. van; Westerberg, L.; Norlin, L.-O.; Petersson, C.S.

    1997-01-01

    The problem concerning mechanical stability of thin self-supporting ΔE detector in a ΔE-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The ΔE-detector has a thickness of 6.5 μm and the E detector 290 μm with an area of 24.8 mm 2 . The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.)

  10. Fabrication of an integrated {Delta}E-E-silicon detector by wafer bonding using cobalt disilicide

    Energy Technology Data Exchange (ETDEWEB)

    Thungstroem, G. [Mid-Sweden Univ., Sundsvall (Sweden). Dept. of Inf. Technol.]|[Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden); Veldhuizen, E.J. van [Uppsala University, Department of Radiation Science, Box 535, S-751 21 Uppsala (Sweden); Westerberg, L. [Uppsala University, The Svedberg Laboratory, Box 533, S-751 21 Uppsala (Sweden); Norlin, L.-O. [Royal Institute of Technology, Department of Physics, Frescativaegen 24, S-104 05 Stockholm (Sweden); Petersson, C.S. [Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden)

    1997-06-01

    The problem concerning mechanical stability of thin self-supporting {Delta}E detector in a {Delta}E-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The {Delta}E-detector has a thickness of 6.5 {mu}m and the E detector 290 {mu}m with an area of 24.8 mm{sup 2}. The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.).

  11. Wafer size effect on material removal rate in copper CMP process

    Energy Technology Data Exchange (ETDEWEB)

    Yuh, Minjong; Jang, Soocheon; Park, Inho; Jeong, Haedo [Pusan National University, Busan (Korea, Republic of)

    2017-06-15

    The semiconductor industry has employed the Chemical mechanical planarization (CMP) to enable surface topography control. Copper has been used to build interconnects because of its low-resistivity and high-electromigration. In this study, the effect of wafer size on the Material removal rate (MRR) in copper CMP process was investigated. CMP experiments were conducted using copper blanket wafers with diameter of 100, 150, 200 and 300 mm, while temperature and friction force were measured by infrared and piezoelectric sen-sors. The MRR increases with an increase in wafer size under the same process conditions. The wafer size increased the sliding distance of pad, resulting in an increase in the process temperature. This increased the process temperature, accelerating the chemical etching rate and the dynamic etch rate. The sliding distance of the pad was proportional to the square of the wafer radius; it may be used to predict CMP results and design a CMP machine.

  12. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  13. Improved process control, lowered costs and reduced risks through the use of non-destructive mobility and sheet carrier density measurements on GaAs and GaN wafers

    Science.gov (United States)

    Nguyen, D.; Hogan, K.; Blew, A.; Cordes, M.

    2004-12-01

    Improved process control, lowered costs and reduced risks can be realized through the use of non-destructive mobility and sheet charge density measurements during the fabrication of GaAs and GaN wafers. The results from this microwave-based technique are shown to agree with destructive van der Pauw Hall testing results to within ±5%. In addition, it has the ability to map wafer uniformity and provide separated 2DEG data for thick cap or multi-layered structures. As a result, this technique provides an efficient and cost-effective alternative to current process control metrology methods, while providing the user with important process control data.

  14. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  15. Large Out-of-Plane Displacement Bistable Electromagnetic Microswitch on a Single Wafer.

    Science.gov (United States)

    Miao, Xiaodan; Dai, Xuhan; Huang, Yi; Ding, Guifu; Zhao, Xiaolin

    2016-05-05

    This paper presents a bistable microswitch fully batch-fabricated on a single glass wafer, comprising of a microactuator, a signal transformer, a microspring and a permanent magnet. The bistable mechanism of the microswitch with large displacement of 160 μm depends on the balance of the magnetic force and elastic force. Both the magnetic force and elastic force were optimized by finite-element simulation to predict the reliable of the device. The prototype was fabricated and characterized. By utilizing thick laminated photoresist sacrificial layer, the large displacement was obtained to ensure the insulation of the microswitch. The testing results show that the microswitch realized the bistable mechanism at a 3-5 V input voltage and closed in 0.96 ms, which verified the simulation.

  16. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  17. Wafer-scale fabrication of polymer distributed feedback lasers

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

    2006-01-01

    The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

  18. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Science.gov (United States)

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  19. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  20. Nonuniformities of electrical resistivity in undoped 6H-SiC wafers

    International Nuclear Information System (INIS)

    Li, Q.; Polyakov, A.Y.; Skowronski, M.; Sanchez, E.K.; Loboda, M.J.; Fanton, M.A.; Bogart, T.; Gamble, R.D.

    2005-01-01

    Chemical elemental analysis, temperature-dependent Hall measurements, deep-level transient spectroscopy, and contactless resistivity mapping were performed on undoped semi-insulating (SI) and lightly nitrogen-doped conducting 6H-SiC crystals grown by physical vapor transport (PVT). Resistivity maps of commercial semi-insulating SiC wafers revealed resistivity variations across the wafers between one and two orders of magnitude. Two major types of variations were identified. First is the U-shape distribution with low resistivity in the center and high in the periphery of the wafer. The second type had an inverted U-shape distribution. Secondary-ion-mass spectrometry measurements of the distribution of nitrogen concentration along the growth axis and across the wafers sliced from different locations of lightly nitrogen-doped 6H-SiC boules were conducted. The measured nitrogen concentration gradually decreased along the growth direction and from the center to the periphery of the wafers. This change gives rise to the U-like distribution of resistivity in wafers of undoped SI-SiC. The concentrations of deep electron traps exhibited similar dependence. Compensation of nitrogen donors by these traps can result in the inverted U-like distribution of resistivity. Possible reasons for the observed nonuniformities include formation of a (0001) facet in PVT growth coupled with orientation-dependent nitrogen incorporation, systematic changes of the gas phase composition, and increase of the deposition temperature during boule growth

  1. A wafer mapping technique for residual stress in surface micromachined films

    International Nuclear Information System (INIS)

    Schiavone, G; Murray, J; Smith, S; Walton, A J; Desmulliez, M P Y; Mount, A R

    2016-01-01

    The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements. (paper)

  2. Ferroelectric and Piezoelectric properties of (111) oriented lanthanum modified lead zirconate titanate film

    Energy Technology Data Exchange (ETDEWEB)

    Dutta, Soma, E-mail: som@nal.res.in; Antony Jeyaseelan, A.; Sruthi, S.

    2014-07-01

    Lanthanum modified lead zirconate titanate (PLZT) thick film with molecular formula of Pb{sub 0.92}La{sub 0.08}(Zr{sub 0.52}Ti{sub 0.48}){sub 0.98}O{sub 3} was grown preferentially along (111) direction on Pt/SiO{sub 2}/Si (platinum/silicon oxide/silicon) substrate by spin coating of chemical solution. The directional growth of the film was facilitated by platinum (Pt) (111) template and rapid thermal annealing. X-ray diffraction pattern and atomic force microscopy revealed the preferential growth of the PLZT film. The film was characterized for ferroelectric and detailed piezoelectric properties in a parallel plate capacitor (metal–PLZT–metal) configuration. Ferroelectric characterization of the film showed saturated hysteresis loop with remanent polarization and coercive electric field values of 10.14 μC/cm{sup 2} and 42 kV/cm, respectively, at an applied field of 300 kV/cm. Longitudinal piezoelectric coefficient (d{sub 33,f}) was measured by employing converse piezoelectric effect where electrical charge response and displacement were measured with electrical voltage excitation on the sample electrodes. The effective transverse piezoelectric coefficient (e{sub 31,f}) was derived from charge measurement with an applied mechanical excitation strain by using the four point bending method. d{sub 33,f} and e{sub 31,f} coefficients of PLZT films were found to be 380 pm/V and − 0.831 C/m{sup 2} respectively. - Highlights: • PLZT (111) film is prepared by spin coating of chemical sol on Pt (111) template. • Piezoelectric d{sub 33} value (380 pm/V) of PLZT film is found 20% higher than PZT. • Transverse piezocoefficient e{sub 31,f} of PLZT film is reported for the first time.

  3. Simultaneous reflectometry and interferometry for measuring thin-film thickness and curvature

    Science.gov (United States)

    Arends, A. A.; Germain, T. M.; Owens, J. F.; Putnam, S. A.

    2018-05-01

    A coupled reflectometer-interferometer apparatus is described for thin-film thickness and curvature characterization in the three-phase contact line region of evaporating fluids. Validation reflectometry studies are provided for Au, Ge, and Si substrates and thin-film coatings of SiO2 and hydrogel/Ti/SiO2. For interferometry, liquid/air and solid/air interferences are studied, where the solid/air samples consisted of glass/air/glass wedges, cylindrical lenses, and molded polydimethylsiloxane lenses. The liquid/air studies are based on steady-state evaporation experiments of water and isooctane on Si and SiO2/Ti/SiO2 wafers. The liquid thin-films facilitate characterization of both (i) the nano-scale thickness of the absorbed fluid layer and (ii) the macro-scale liquid meniscus thickness, curvature, and curvature gradient profiles. For our validation studies with commercial lenses, the apparatus is shown to measure thickness profiles within 4.1%-10.8% error.

  4. TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Wobrauschek, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Kregsamer, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Ladisich, W [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Streli, C [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Pahlke, S [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Fabry, L [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Garbe, S [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Haller, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Knoechel, A [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Radtke, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany)

    1995-09-11

    SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.).

  5. TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

    International Nuclear Information System (INIS)

    Wobrauschek, P.; Kregsamer, P.; Ladisich, W.; Streli, C.; Pahlke, S.; Fabry, L.; Garbe, S.; Haller, M.; Knoechel, A.; Radtke, M.

    1995-01-01

    SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.)

  6. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  7. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

    2014-01-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  8. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  9. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  10. Determination of wafer center position during the transfer process by using the beam-breaking method

    International Nuclear Information System (INIS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-01-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human–machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions. (paper)

  11. High Energy Storage Density and Impedance Response of PLZT2/95/5 Antiferroelectric Ceramics.

    Science.gov (United States)

    Li, Bi; Liu, Qiuxiang; Tang, Xingui; Zhang, Tianfu; Jiang, Yanping; Li, Wenhua; Luo, Jie

    2017-02-08

    (Pb 0.97 La 0.02 )(Zr 0.95 Ti 0.05 )O₃ (PLZT2/95/5) ceramics were successfully prepared via a solid-state reaction route. The dielectric properties were investigated in the temperature region of 26-650 °C. The dielectric diffuse anomaly in the dielectric relaxation was found in the high temperature region of 600-650 °C with increasing the measuring frequency, which was related to the dynamic thermal process of ionized oxygen vacancies generated in the high temperature. Two phase transition points were detected during heating, which were found to coexist from 150 to 200 °C. Electric field induced ferroelectric to antiferroelectric phase transition behavior of the (Pb 0.97 La 0.02 )(Zr 0.95 Ti 0.05 )O₃ ceramics was investigated in this work with an emphasis on energy storage properties. A recoverable energy-storage density of 0.83 J/cm³ and efficiency of 70% was obtained in (Pb 0.97 La 0.02 )(Zr 0.95 Ti 0.05 )O₃ ceramics at 55 kV/cm. Based on these results, (Pb 0.97 La 0.02 )(Zr 0.95 Ti 0.05 )O₃ ceramics with a large recoverable energy-storage density could be a potential candidate for the applications in high energy-storage density ceramic capacitors.

  12. High Energy Storage Density and Impedance Response of PLZT2/95/5 Antiferroelectric Ceramics

    Directory of Open Access Journals (Sweden)

    Bi Li

    2017-02-01

    Full Text Available (Pb0.97La0.02(Zr0.95Ti0.05O3 (PLZT2/95/5 ceramics were successfully prepared via a solid-state reaction route. The dielectric properties were investigated in the temperature region of 26–650 °C. The dielectric diffuse anomaly in the dielectric relaxation was found in the high temperature region of 600–650 °C with increasing the measuring frequency, which was related to the dynamic thermal process of ionized oxygen vacancies generated in the high temperature. Two phase transition points were detected during heating, which were found to coexist from 150 to 200 °C. Electric field induced ferroelectric to antiferroelectric phase transition behavior of the (Pb0.97La0.02(Zr0.95Ti0.05O3 ceramics was investigated in this work with an emphasis on energy storage properties. A recoverable energy-storage density of 0.83 J/cm3 and efficiency of 70% was obtained in (Pb0.97La0.02(Zr0.95Ti0.05O3 ceramics at 55 kV/cm. Based on these results, (Pb0.97La0.02(Zr0.95Ti0.05O3 ceramics with a large recoverable energy-storage density could be a potential candidate for the applications in high energy-storage density ceramic capacitors.

  13. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Directory of Open Access Journals (Sweden)

    Lim SCB

    2013-04-01

    Full Text Available Stephen CB Lim,1,3 Michael J Paech,2 Bruce Sunderland,3 Yandi Liu3 1Pharmacy Department, Armadale Health Service, Armadale, 2School of Medicine and Pharmacology, University of Western Australia, and Department of Anaesthesia and Pain Medicine, King Edward Memorial Hospital for Women, Subiaco, 3School of Pharmacy, Curtin Health Innovation Research Institute, Curtin University, Perth, WA, Australia Background: The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods: The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results: In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion: These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. Keywords: absolute bioavailability, fentanyl wafer, in vitro dissolution, in vivo study, pharmacokinetics, sublingual

  14. 450mm wafer patterning with jet and flash imprint lithography

    Science.gov (United States)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  15. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

    Science.gov (United States)

    Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

    2018-05-01

    In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

  16. Preparation and characterisation of immobilised humic acid on silicon wafer

    International Nuclear Information System (INIS)

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  17. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  18. A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

    Science.gov (United States)

    Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

    2013-03-01

    The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

  19. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  20. Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

    NARCIS (Netherlands)

    Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

    2001-01-01

    Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

  1. InP-based photonic integrated circuit platform on SiC wafer.

    Science.gov (United States)

    Takenaka, Mitsuru; Takagi, Shinichi

    2017-11-27

    We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

  2. Physical mechanisms of copper-copper wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.; Hingerl, K.

    2015-01-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing

  3. Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

    Science.gov (United States)

    Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

    2018-05-01

    Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

  4. Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

    Science.gov (United States)

    Egelkrout, D. W.

    1981-01-01

    Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

  5. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    Science.gov (United States)

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  6. Control of cavitation using dissolved carbon dioxide for damage-free megasonic cleaning of wafers

    Science.gov (United States)

    Kumari, Sangita

    equilibria revealed that the loss of released CO2(aq) upon increase in pH can be compensated by moderate increase in added NH4HCO3. Using this method, simultaneous control of SL and solution pH was demonstrated in two systems, NH4HCO3/HCl and NH4OH/CO2, at two nominal pH values; 5.7 and 7.0. Damage studies were performed on wafer samples with line/space patterns donated by IMEC and FSI International bearing Si/metal/a-Si gate stacks of thickness ~36 nm and Si/Poly-Si gate stacks of thickness ~67 nm, respectively. A single wafer spin cleaning tool MegPieRTM was used for the generation of megasonic energy for inducing damage to the structures. It was demonstrated that CO2 dissolution in DI water suppresses damage to the gate stacks in a dose-dependent manner. Together, these studies establish a systematic and strong correlation between CO2(aq) concentration, SL suppression and damage suppression. Significant damage reduction (~50 % to ~90 %) was observed at [CO2(aq)] > ~300 ppm. It was also demonstrated that CO2(aq) suppresses damage under alkaline pH condition too. This demonstration was made possible by the successful design of two new cleaning systems NH4HCO3/NH4OH and CO2/NH 4OH that could generate CO2(aq) under alkaline conditions. Damage suppressing ability of the newly designed cleaning systems were compared to the standard cleaning system NH4OH at pH 8.2 and it was found that NH4HCO3/NH4OH and CO2/NH 4OH systems were 80 % more efficient in suppressing damage compared to the standard NH4OH cleaning system. Finally, megasonic cleaning studies were conducted in the same single wafer spin cleaning tool MegPieRTM, using SiO2 particles (size 185 nm) deposited on 200 mm oxide Si wafers, as the contaminant. It was found that the standard cleaning chemical, NH4OH, pH 8.2, was effective in achieving > 95 % particle removal for 2 min irradiation of megasonic energy at power densities > 0.7 W/cm2. Based on these results, a new system, NH4HCO3/NH4OH, was designed with an aim to

  7. Surface etching technologies for monocrystalline silicon wafer solar cells

    Science.gov (United States)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  8. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  9. Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

    Energy Technology Data Exchange (ETDEWEB)

    Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

    2012-09-15

    We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

  10. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  11. Application Of Light Valves For Continuous-Tone Printing

    Science.gov (United States)

    Vergona, Albert B.

    1989-07-01

    New opportunities are emerging in the graphic-arts pre-press market stimulated by the need for digitally created images. To meet this need, we have designed a cost-effective three-color digital printer using PLZT light valves. Transparent lead lanthanum zirconate titanate (PLZT) ceramic crystals when used as a linear modulator offer a number of significant benefits. The primary advantage is that the light valve is an efficient modulator of incoherent light providing a broad spectral output ranging from 400nm to well into the infrared region. In addition, light valves offer the advantages of being small, low cost, have a wide dynamic range (>1000 to 1), and can be used with simple optical designs. The characteristics of the PLZT material plays an important role in the performance of the light valve. A number of variables such as ceramic composition, electrode spacing, and ceramic thickness can be altered to affect its quadratic electrooptic behavior. Additionally, the modulator design requires a closed-loop servo to eliminate the errors caused by the device's remanent polarization and nonlinear behavior.

  12. Mechanics of wafer bonding: Effect of clamping

    Science.gov (United States)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  13. X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

    Science.gov (United States)

    Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); King, Glen C. (Inventor); Choi, Sang Hyouk (Inventor)

    2017-01-01

    An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

  14. Design and implementation of a S-parameter wafer defect scanner

    International Nuclear Information System (INIS)

    Naik, P.S.; Beling, C.D.; Fung, S.

    2004-01-01

    We describe the design and implementation of a real-time automated scanning system that gives an S-parameter image of a semiconductor wafer, thus allowing the density of vacancy type defects to be shown as a function of position on the wafer. A conventional 22 Na positron source of 0.5 mm diameter rasters across 5 x 5 cm 2 region of two times per hour in rectilinear motion. Gamma ray energies E γ are processed using a standard HP Ge spectroscopy system and a 14 bit nuclear ADC. Over a period of 1-2 days a high resolution 128 x 128 pixel image with 256 colours (scaled to the S-parameter range) can be formed as a wafer defect map. The system is reliable, interactive and user-friendly (patent pending 2003). (orig.)

  15. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    Science.gov (United States)

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  16. Accurate characterization of wafer bond toughness with the double cantilever specimen

    Science.gov (United States)

    Turner, Kevin T.; Spearing, S. Mark

    2008-01-01

    The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

  17. The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

    International Nuclear Information System (INIS)

    Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

    2004-01-01

    We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

  18. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  19. Scatterometry on pelliclized masks: an option for wafer fabs

    Science.gov (United States)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  20. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    International Nuclear Information System (INIS)

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  1. Wafer plane inspection with soft resist thresholding

    Science.gov (United States)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  2. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  3. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  4. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Science.gov (United States)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  5. Effect of GaN cap thickness on carrier dynamics in InGaN quantum wells

    DEFF Research Database (Denmark)

    Kopylov, Oleksii; Shirazi, Roza; Svensk, O.

    2012-01-01

    We have studied optical properties of single In0.1Ga0.9N quantum wells with GaN barriers in close proximity to the wafer surface (... thickness of 3nm for achieving highest brightness emitters. At low temperature, we observe a behaviour that suggests that some surface states act as trapping centres for carriers rather than as a non-radiative recombination channel. Temperature dependence of the photoluminescence decay curves shows...

  6. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  7. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    International Nuclear Information System (INIS)

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  8. Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

    Science.gov (United States)

    Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

    2017-10-01

    Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

  9. Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

    Science.gov (United States)

    Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

    2018-03-01

    The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

  10. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    Science.gov (United States)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  11. A modified occlusal wafer for managing partially dentate orthognathic patients--a case series.

    Science.gov (United States)

    Soneji, Bhavin Kiritkumar; Esmail, Zaid; Sharma, Pratik

    2015-03-01

    A multidisciplinary approach is essential in orthognathic surgery to achieve stable and successful outcomes. The model surgery planning is an important aspect in achieving the desired aims. An occlusal wafer used at the time of surgery aids the surgeon during correct placement of the jaws. When dealing with partially dentate patients, the design of the occlusal wafer requires modification to appropriately position the jaw. Two cases with partially dentate jaws are presented in which the occlusal wafer has been modified to provide stability at the time of surgery.

  12. Palladium-based on-wafer electroluminescence studies of GaN-based LED structures

    Energy Technology Data Exchange (ETDEWEB)

    Salcianu, C.O.; Thrush, E.J.; Humphreys, C.J. [Department of Materials Science and Metallurgy, University of Cambridge, Pembroke Street, Cambridge CB2 3QZ (United Kingdom); Plumb, R.G. [Centre for Photonic Systems, Department of Engineering, University of Cambridge, Cambridge CB3 0FD (United Kingdom); Boyd, A.R.; Rockenfeller, O.; Schmitz, D.; Heuken, M. [AIXTRON AG, Kackertstr. 15-17, 52072 Aachen (Germany)

    2008-07-01

    Electroluminescence (EL) testing of Light Emitting Diode (LED) structures is usually done at the chip level. Assessing the optical and electrical properties of LED structures at the wafer scale prior to their processing would improve the cost effectiveness of producing LED-lamps. A non-destructive method for studying the luminescence properties of the structure at the wafer-scale is photoluminescence (PL). However, the relationship between the on-wafer PL data and the final device EL can be less than straightforward (Y. H Aliyu et al., Meas. Sci. Technol. 8, 437 (1997)) as the two techniques employ different carrier injection mechanisms. This paper provides an overview of some different techniques in which palladium is used as a contact in order to obtain on-wafer electroluminescence information which could be used to screen wafers prior to processing into final devices. Quick mapping of the electrical and optical characteristics was performed using either palladium needle electrodes directly, or using the latter in conjunction with evaporated palladium contacts to inject both electrons and holes into the active region via the p-type capping layer of the structure. For comparison, indium was also used to make contact to the n-layer so that electrons could be directly injected into that layer. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  13. Computational Modeling in Plasma Processing for 300 mm Wafers

    Science.gov (United States)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  14. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  15. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  16. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    NARCIS (Netherlands)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  17. Effect of film thickness, type of buffer layer, and substrate temperature on the morphology of dicyanovinyl-substituted sexithiophene films

    Energy Technology Data Exchange (ETDEWEB)

    Levin, Alexandr A., E-mail: alexander.levin@iapp.de [Institut fuer Angewandte Photophysik, Technische Universitaet Dresden, 01062 Dresden (Germany); Levichkova, Marieta [Institut fuer Angewandte Photophysik, Technische Universitaet Dresden, 01062 Dresden (Germany); Heliatek GmbH, 01187 Dresden (Germany); Hildebrandt, Dirk; Klisch, Marina; Weiss, Andre [Heliatek GmbH, 01187 Dresden (Germany); Wynands, David; Elschner, Chris [Institut fuer Angewandte Photophysik, Technische Universitaet Dresden, 01062 Dresden (Germany); Pfeiffer, Martin [Heliatek GmbH, 01187 Dresden (Germany); Leo, Karl; Riede, Moritz [Institut fuer Angewandte Photophysik, Technische Universitaet Dresden, 01062 Dresden (Germany)

    2012-01-31

    The influence of film thickness, type of buffer underlayer, and deposition substrate temperature on the crystal structure, microstructure, and morphology of the films of dicyanovinyl-substituted sexithiophene with four butyl-chains (DCV6T-Bu{sub 4}) is investigated by means of X-ray diffraction (XRD) and X-ray reflectivity methods. A neat Si wafer or a Si wafer covered by a 15 nm buffer underlayer of fullerene C{sub 60} or 9,9-Bis[4-(N,N-bis-biphenyl-4-yl-amino)phenyl]-9H-fluorene (BPAPF) is used as a substrate. The crystalline nature and ordered molecular arrangement of the films are recorded down to 6 nm film thickness. By using substrates heated up to 90 Degree-Sign C during the film deposition, the size of the DCV6T-Bu{sub 4} crystallites in direction perpendicular to the film surface increases up to value of the film thickness. With increasing deposition substrate temperature or film thickness, the DCV6T-Bu{sub 4} film relaxes, resulting in reducing the interplane distances closer to the bulk values. For the films of the same thickness deposited at the same substrate temperature, the DCV6T-Bu{sub 4} film relaxes for growth on Si to BPAPF to C{sub 60}. Thicker films grown at heated substrates are characterized by smaller density, higher roughness and crystallinity and better molecular ordering. A thin (up to about 6 nm-thick) intermediate layer with linear density-gradient is formed at the C{sub 60}/DCV6T-Bu{sub 4} interface for the films with buffer C{sub 60} layer. The XRD pattern of the DCV6T-Bu{sub 4} powder is indexed using triclinic unit cell parameters.

  18. Prediction of etching-shape anomaly due to distortion of ion sheath around a large-scale three-dimensional structure by means of on-wafer monitoring technique and computer simulation

    International Nuclear Information System (INIS)

    Kubota, Tomohiro; Ohtake, Hiroto; Araki, Ryosuke; Yanagisawa, Yuuki; Samukawa, Seiji; Iwasaki, Takuya; Ono, Kohei; Miwa, Kazuhiro

    2013-01-01

    A system for predicting distortion of a profile during plasma etching was developed. The system consists of a combination of measurement and simulation. An ‘on-wafer sheath-shape sensor’ for measuring the plasma-sheath parameters (sheath potential and thickness) on the stage of the plasma etcher was developed. The sensor has numerous small electrodes for measuring sheath potential and saturation ion-current density, from which sheath thickness can be calculated. The results of the measurement show reasonable dependence on source power, bias power and pressure. Based on self-consistent calculation of potential distribution and ion- and electron-density distributions, simulation of the sheath potential distribution around an arbitrary 3D structure and the trajectory of incident ions from the plasma to the structure was developed. To confirm the validity of the distortion prediction by comparing it with experimentally measured distortion, silicon trench etching under chlorine inductively coupled plasma (ICP) was performed using a sample with a vertical step. It was found that the etched trench was distorted when the distance from the step was several millimetres or less. The distortion angle was about 20° at maximum. Measurement was performed using the on-wafer sheath-shape sensor in the same plasma condition as the etching. The ion incident angle, calculated as a function of distance from the step, successfully reproduced the experimentally measured angle, indicating that the combination of measurement by the on-wafer sheath-shape sensor and simulation can predict distortion of an etched structure. This prediction system will be useful for designing devices with large-scale 3D structures (such as those in MEMS) and determining the optimum etching conditions to obtain the desired profiles. (paper)

  19. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  20. Macrodefect-free, large, and thick GaN bulk crystals for high-quality 2–6 in. GaN substrates by hydride vapor phase epitaxy with hardness control

    Science.gov (United States)

    Fujikura, Hajime; Konno, Taichiro; Suzuki, Takayuki; Kitamura, Toshio; Fujimoto, Tetsuji; Yoshida, Takehiro

    2018-06-01

    On the basis of a novel crystal hardness control, we successfully realized macrodefect-free, large (2–6 in.) and thick +c-oriented GaN bulk crystals by hydride vapor phase epitaxy. Without the hardness control, the introduction of macrodefects including inversion domains and/or basal-plane dislocations seemed to be indispensable to avoid crystal fracture in GaN growth with millimeter thickness. However, the presence of these macrodefects tended to limit the applicability of the GaN substrate to practical devices. The present technology markedly increased the GaN crystal hardness from below 20 to 22 GPa, thus increasing the available growth thickness from below 1 mm to over 6 mm even without macrodefect introduction. The 2 and 4 in. GaN wafers fabricated from these crystals had extremely low dislocation densities in the low- to mid-105 cm‑2 range and low off-angle variations (2 in.: <0.1° 4 in.: ∼0.2°). The realization of such high-quality 6 in. wafers is also expected.

  1. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  2. Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

    Science.gov (United States)

    Bakhshizadeh, N.; Sivoththaman, S.

    2017-12-01

    Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

  3. Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

    Science.gov (United States)

    Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

    2011-01-01

    Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

  4. Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

    International Nuclear Information System (INIS)

    Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

    2006-01-01

    A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

  5. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  6. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  7. development and evaluation of lyophilized thiolated-chitosan wafers

    African Journals Online (AJOL)

    User

    THIOLATED-CHITOSAN WAFERS FOR BUCCAL DELIVERY. OF PROTEIN ... of the thiolated polymer incorporating per polymer weight, 10 % each of glycerol as plasticizer, D-mannitol as ..... delivery systems: in vitro stability, in vivo fate, and ...

  8. Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

    International Nuclear Information System (INIS)

    Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

    2003-01-01

    Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

  9. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    International Nuclear Information System (INIS)

    Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

    2014-01-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  10. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  11. A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

    Science.gov (United States)

    Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

    2018-03-01

    In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the

  12. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    Science.gov (United States)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  13. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    Science.gov (United States)

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  14. Sample pretreatment for the determination of metal impurities in silicon wafer

    International Nuclear Information System (INIS)

    Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

    1999-01-01

    The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

  15. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    International Nuclear Information System (INIS)

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  16. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  17. Industrial Silicon Wafer Solar Cells

    OpenAIRE

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  18. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  19. Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

    Science.gov (United States)

    Wang, Shing-Dar; Chen, Ting-Wei

    2018-06-01

    In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

  20. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    DEFF Research Database (Denmark)

    Mackenzie, David; Buron, Jonas Christian Due; Whelan, Patrick Rebsdorf

    2015-01-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140......-effect mobility, doping level, on–off ratio, and conductance minimum before and after laser ablation fabrication....

  1. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  2. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    Science.gov (United States)

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

  3. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    Science.gov (United States)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  4. Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

    Directory of Open Access Journals (Sweden)

    Liu Haijun

    2015-12-01

    Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

  5. Automatic Semiconductor Wafer Image Segmentation for Defect Detection Using Multilevel Thresholding

    Directory of Open Access Journals (Sweden)

    Saad N.H.

    2016-01-01

    Full Text Available Quality control is one of important process in semiconductor manufacturing. A lot of issues trying to be solved in semiconductor manufacturing industry regarding the rate of production with respect to time. In most semiconductor assemblies, a lot of wafers from various processes in semiconductor wafer manufacturing need to be inspected manually using human experts and this process required full concentration of the operators. This human inspection procedure, however, is time consuming and highly subjective. In order to overcome this problem, implementation of machine vision will be the best solution. This paper presents automatic defect segmentation of semiconductor wafer image based on multilevel thresholding algorithm which can be further adopted in machine vision system. In this work, the defect image which is in RGB image at first is converted to the gray scale image. Median filtering then is implemented to enhance the gray scale image. Then the modified multilevel thresholding algorithm is performed to the enhanced image. The algorithm worked in three main stages which are determination of the peak location of the histogram, segmentation the histogram between the peak and determination of first global minimum of histogram that correspond to the threshold value of the image. The proposed approach is being evaluated using defected wafer images. The experimental results shown that it can be used to segment the defect correctly and outperformed other thresholding technique such as Otsu and iterative thresholding.

  6. Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

    Science.gov (United States)

    Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

    2018-05-01

    Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

  7. External self-gettering of nickel in float zone silicon wafers

    Science.gov (United States)

    Gay, N.; Martinuzzi, S.

    1997-05-01

    During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

  8. Novel SU-8 based vacuum wafer-level packaging for MEMS devices

    DEFF Research Database (Denmark)

    Murillo, Gonzalo; Davis, Zachary James; Keller, Stephan Urs

    2010-01-01

    This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability and versa......This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability...

  9. Formation of III–V-on-insulator structures on Si by direct wafer bonding

    International Nuclear Information System (INIS)

    Yokoyama, Masafumi; Iida, Ryo; Ikku, Yuki; Kim, Sanghyeon; Takenaka, Mitsuru; Takagi, Shinichi; Takagi, Hideki; Yasuda, Tetsuji; Yamada, Hisashi; Ichikawa, Osamu; Fukuhara, Noboru; Hata, Masahiko

    2013-01-01

    We have studied the formation of III–V-compound-semiconductors-on-insulator (III–V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III–V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O 2 plasma-assisted DWB process with ECR sputtered SiO 2 BOX layers and a DWB process based on atomic-layer-deposition Al 2 O 3 (ALD-Al 2 O 3 ) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO 2 and ALD-Al 2 O 3 BOX layers are desorption of Ar and H 2 O gas, respectively. In order to suppress micro-void generation in the ECR-SiO 2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al 2 O 3 BOX layers to increase the deposition temperature of the ALD-Al 2 O 3 BOX layers. It is also another possible solution to deposit ALD-Al 2 O 3 BOX layers on thermally oxidized SiO 2 layers, which can absorb the desorption gas from ALD-Al 2 O 3 BOX layers. (invited paper)

  10. Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating

    International Nuclear Information System (INIS)

    Gu, Changdong; Zhang, Tong-Yi; Xu, Hui

    2009-01-01

    This study aims to fabricate high aspect ratio through-wafer copper interconnects by a simple reverse pulse electroplating technique. High aspect-ratio (∼18) through-wafer holes obtained by a two-step deep reactive ion etching (DRIE) process exhibit a taper profile, which might automatically optimize the local current density distribution during the electroplating process, thereby achieving void-free high aspect-ratio copper vias

  11. High-κ Al{sub 2}O{sub 3} material in low temperature wafer-level bonding for 3D integration application

    Energy Technology Data Exchange (ETDEWEB)

    Fan, J., E-mail: fanji@hust.edu.cn; Tu, L. C. [MOE Key Laboratory of Fundamental Physical Quantities Measurement, School of Physics, Huazhong University of Science and Technology, Wuhan 430074 (China); Tan, C. S. [School of Electrical and Electronics Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2014-03-15

    This work systematically investigated a high-κ Al{sub 2}O{sub 3} material for low temperature wafer-level bonding for potential applications in 3D microsystems. A clean Si wafer with an Al{sub 2}O{sub 3} layer thickness of 50 nm was applied as our experimental approach. Bonding was initiated in a clean room ambient after surface activation, followed by annealing under inert ambient conditions at 300 °C for 3 h. The investigation consisted of three parts: a mechanical support study using the four-point bending method, hermeticity measurements using the helium bomb test, and thermal conductivity analysis for potential heterogeneous bonding. Compared with samples bonded using a conventional oxide bonding material (SiO{sub 2}), a higher interfacial adhesion energy (∼11.93 J/m{sup 2}) and a lower helium leak rate (∼6.84 × 10{sup −10} atm.cm{sup 3}/sec) were detected for samples bonded using Al{sub 2}O{sub 3}. More importantly, due to the excellent thermal conductivity performance of Al{sub 2}O{sub 3}, this technology can be used in heterogeneous direct bonding, which has potential applications for enhancing the performance of Si photonic integrated devices.

  12. A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers

    Science.gov (United States)

    2018-04-01

    AFRL-RY-WP-TR-2018-0030 A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS Subramanian S. Iyer University of California...Final 13 June 2016 – 13 December 2017 4. TITLE AND SUBTITLE A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS 5a. CONTRACT

  13. Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2006-03-01

    Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

  14. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  15. Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

    2014-02-07

    Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

  16. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  17. Wafer defect detection by a polarization-insensitive external differential interference contrast module.

    Science.gov (United States)

    Nativ, Amit; Feldman, Haim; Shaked, Natan T

    2018-05-01

    We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

  18. A new fabrication process for uniform SU-8 thick photoresist structures by simultaneously removing edge bead and air bubbles

    International Nuclear Information System (INIS)

    Lee, Hun; Lee, Kangsun; Ahn, Byungwook; Xu, Jing; Xu, Linfeng; Oh, Kwang W

    2011-01-01

    This paper proposes a new SU-8 fabrication process to simultaneously remove edge bead and tiny air bubbles by spraying out edge bead removal (EBR) fluid over the entire surface of photoresist. In particular, the edge bead and air bubbles can cause an air gap between a film mask and a photoresist surface during UV exposure. The diffraction effect of UV light by the air gap leads to inaccurate and non-uniform SU-8 patterns. In this study, we demonstrate a simple method using EBR treatment to simultaneously eliminate the edge bead at the edge of wafer and tiny air bubbles inside SU-8. The profiles of thickness variation of SU-8 films with/without the EBR treatment are measured. The results show that the proposed EBR treatment can successfully remove the edge bead and air bubbles over the entire SU-8 films. The average pattern uniformity of SU-8 is improved from 50.5% to 11.3% in the case of 200 µm thickness. This method is simple and inexpensive, compared to a standard EBR process, because it does not require specialized equipment and it can be applied regardless of substrate geometry (e.g. circular wafer and rectangular slide glass).

  19. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  20. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  1. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  2. Laser generated guided waves and finite element modeling for the thickness gauging of thin layers.

    Science.gov (United States)

    Lefevre, F; Jenot, F; Ouaftouh, M; Duquennoy, M; Ourak, M

    2010-03-01

    In this paper, nondestructive testing has been performed on a thin gold layer deposited on a 2 in. silicon wafer. Guided waves were generated and studied using a laser ultrasonic setup and a two-dimensional fast Fourier transform technique was employed to obtain the dispersion curves. A gold layer thickness of 1.33 microm has been determined with a +/-5% margin of error using the shape of the two first propagating modes, assuming for the substrate and the layer an uncertainty on the elastic parameters of +/-2.5%. A finite element model has been implemented to validate the data post-treatment and the experimental results. A good agreement between the numerical simulation, the analytical modeling and the experimentations has been observed. This method was considered suitable for thickness layer higher than 0.7 microm.

  3. A study for anticorrosion and tribological behaviors of thin/thick diamond-like carbon films in seawater

    Science.gov (United States)

    Ye, Yewei; Jia, Shujuan; Zhang, Dawei; Liu, Wei; Zhao, Haichao

    2018-03-01

    The thin and thick diamond-like carbon (DLC) films were prepared by unbalanced magnetron sputtering technique on 304L stainless steels and (100) silicon wafers. Microstructure, mechanical, corrosion and tribological properties were systematically investigated by SEM, Raman, nanoindenter, scratch tester, modulab electrochemical workstation and R-tec multifunctional tribological tester. Results showed that the adhesion force presented a descending trend with the growth in soaking time. The adhesion force of the thin DLC film with high residual compressive stress (‑3.72 GPa) was higher than that of the thick DLC film (‑2.96 GPa). During the corrosion test, the thick DLC film showed a higher impendence and a lower corrosion current density than the thin DLC film, which is attributed to the barrier action of large thickness. Compared to bare 304L substrate, the friction coefficients and wear rates of DLC films in seawater were obviously decreased. Meanwhile, the thin DLC film with ideal residual compressive stress, super adhesion force and good plastic deformation resistance revealed an excellent anti-wear ability in seawater.

  4. Effects of gas-flow structures on radical and etch-product density distributions on wafers in magnetomicrowave plasma etching reactors

    International Nuclear Information System (INIS)

    Ikegawa, Masato; Kobayashi, Jun'ichi; Fukuyama, Ryoji

    2001-01-01

    To achieve high etch rate, uniformity, good selectivity, and etch profile control across large diameter wafers, the distributions of ions, radicals, and etch products in magnetomicrowave high-etch-rate plasma etching reactors must be accurately controlled. In this work the effects of chamber heights, a focus ring around the wafer, and gas supply structures (or gas flow structures) on the radicals and etch products flux distribution onto the wafer were examined using the direct simulation Monte Carlo method and used to determine the optimal reactor geometry. The pressure uniformity on the wafer was less than ±1% when the chamber height was taller than 60 mm. The focus ring around the wafer produced uniform radical and etch-product fluxes but increased the etch-product flux on the wafer. A downward-flow gas-supply structure (type II) produced a more uniform radical distribution than that produced by a radial gas-supply structure (type I). The impact flow of the type II structure removed etch products from the wafer effectively and produced a uniform etch-product distribution even without the focus ring. Thus the downward-flow gas-supply structure (type II) was adopted in the design for the second-generation of a magnetomicrowave plasma etching reactor with a higher etching rate

  5. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  6. Xe{sup +} ion beam induced rippled structures on Si miscut wafers

    Energy Technology Data Exchange (ETDEWEB)

    Hanisch, Antje; Grenzer, Joerg [Forschungszentrum Dresden-Rossendorf, Dresden (Germany); Biermanns, Andreas; Pietsch, Ullrich [Institute of Physics, University of Siegen (Germany)

    2009-07-01

    We report on the influence of the initial roughness and crystallography of the substrate on the formation of self-organized ripple structures on semiconductors surfaces by noble gas ion bombardment. The Bradley-Harper theory predicts that an initial roughness is most important for starting the sputtering process which in the ends leads to the evolution of regular patterns. We produced periodic structures with intermediate Xe{sup +} ion energies (5-70 keV) at different incidence and azimuthal angles which lead to the assumption that also crystallography plays a role at the beginning of ripple evolution. Most of the previous investigations started from the original roughness of a polished silicon wafer. We used (001) silicon wafers with a miscut angle of 1 , 5 and 10 towards[110]. We studied the ripple formation keeping the ion beam parallel to the[111],[-1-11] or[-111] direction, i.e. parallel, antiparallel or perpendicular to the miscut direction[110]. The parallel and antiparallel case implies a variation of the incidence angle with increased roughness over the surface step terraces. The perpendicular orientation means almost no roughness. The results were compared to normal Si(001) and Si(111) wafers.

  7. The role of Gliadel wafers in the treatment of newly diagnosed GBM: a meta-analysis

    Directory of Open Access Journals (Sweden)

    Xing WK

    2015-06-01

    Full Text Available Wei-kang Xing,1 Chuan Shao,2 Zhen-yu Qi,1 Chao Yang,1 Zhong Wang1 1Department of Neurosurgery, The First Affiliated Hospital of Soochow University, Suzhou, Jiangsu, 2Department of Neurosurgery, The Second Clinical Medical College of North Sichuan Medical College, Nanchong, Sichuan, People’s Republic of China Background: Standard treatment for high-grade glioma (HGG includes surgery followed by radiotherapy and/or chemotherapy. Insertion of carmustine wafers into the resection cavity as a treatment for malignant glioma is currently a controversial topic among neurosurgeons. Our meta-analysis focused on whether carmustine wafer treatment could significantly benefit the survival of patients with newly diagnosed glioblastoma multiforme (GBM.Method: We searched the PubMed and Web of Science databases without any restrictions on language using the keywords “Gliadel wafers”, “carmustine wafers”, “BCNU wafers”, or “interstitial chemotherapy” in newly diagnosed GBM for the period from January 1990 to March 2015. Randomized controlled trials (RCTs and cohort studies/clinical trials that compared treatments designed with and without carmustine wafers and which reported overall survival or hazard ratio (HR or survival curves were included in this study. Moreover, the statistical analysis was conducted by the STATA 12.0 software.Results: Six studies including two RCTs and four cohort studies, enrolling a total of 513 patients (223 with and 290 without carmustine wafers, matched the selection criteria. Carmustine wafers showed a strong advantage when pooling all the included studies (HR =0.63, 95% confidence interval (CI =0.49–0.81; P=0.019. However, the two RCTs did not show a statistical increase in survival in the group with carmustine wafer compared to the group without it (HR =0.51, 95% CI =0.18–1.41; P=0.426, while the cohort studies demonstrated a significant survival increase (HR =0.59, 95% CI =0.44–0.79; P<0.0001.Conclusion

  8. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    Directory of Open Access Journals (Sweden)

    Prithviraj Chakraborty

    2013-01-01

    Full Text Available Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR. Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A, and lactose monohydrate as ingredient, of hydrophilic matrix former (B on the bioadhesive force, disintegration time, percent (% swelling index, and time taken for 70% drug release (t70%. The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design.

  9. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    Science.gov (United States)

    Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

    2013-01-01

    Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t 70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

  10. EM Simulation Accuracy Enhancement for Broadband Modeling of On-Wafer Passive Components

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Jiang, Chenhui; Hadziabdic, Dzenan

    2007-01-01

    This paper describes methods for accuracy enhancement in broadband modeling of on-wafer passive components using electromagnetic (EM) simulation. It is shown that standard excitation schemes for integrated component simulation leads to poor correlation with on-wafer measurements beyond the lower...... GHz frequency range. We show that this is due to parasitic effects and higher-order modes caused by the excitation schemes. We propose a simple equivalent circuit for the parasitic effects in the well-known ground ring excitation scheme. An extended L-2L calibration method is shown to improve...

  11. Aberration-corrected transmission electron microscopy analyses of GaAs/Si interfaces in wafer-bonded multi-junction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Häussler, Dietrich [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Houben, Lothar [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Essig, Stephanie [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Kurttepeli, Mert [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Dimroth, Frank [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Dunin-Borkowski, Rafal E. [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Jäger, Wolfgang, E-mail: wolfgang.jaeger@tf.uni-kiel.de [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany)

    2013-11-15

    Aberration-corrected scanning transmission electron microscopy (STEM) and electron energy loss spectroscopy (EELS) investigations have been applied to investigate the structure and composition fluctuations near interfaces in wafer-bonded multi-junction solar cells. Multi-junction solar cells are of particular interest since efficiencies well above 40% have been obtained for concentrator solar cells which are based on III-V compound semiconductors. In this methodologically oriented investigation, we explore the potential of combining aberration-corrected high-angle annular dark-field STEM imaging (HAADF-STEM) with spectroscopic techniques, such as EELS and energy-dispersive X-ray spectroscopy (EDXS), and with high-resolution transmission electron microscopy (HR-TEM), in order to analyze the effects of fast atom beam (FAB) and ion beam bombardment (IB) activation treatments on the structure and composition of bonding interfaces of wafer-bonded solar cells on Si substrates. Investigations using STEM/EELS are able to measure quantitatively and with high precision the widths and the fluctuations in element distributions within amorphous interface layers of nanometer extensions, including those of light elements. Such measurements allow the control of the activation treatments and thus support assessing electrical conductivity phenomena connected with impurity and dopant distributions near interfaces for optimized performance of the solar cells. - Highlights: • Aberration-corrected TEM and EELS reveal structural and elemental profiles across GaAs/Si bond interfaces in wafer-bonded GaInP/GaAs/Si - multi-junction solar cells. • Fluctuations in elemental concentration in nanometer-thick amorphous interface layers, including the disrubutions of light elements, are measured using EELS. • The projected widths of the interface layers are determined on the atomic scale from STEM-HAADF measurements. • The effects of atom and ion beam activation treatment on the bonding

  12. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    OpenAIRE

    Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

    2018-01-01

    A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

  13. Single crystalline silicon solar cells with rib structure

    Directory of Open Access Journals (Sweden)

    Shuhei Yoshiba

    2017-02-01

    Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  14. Prediction of thermo-mechanical reliability of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; van Driel, W.D.; Hoofman, R.J.O.M.; Ernst, L.J.

    2004-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  15. Prediction of thermo-mechanical integrity of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; Hoofman, R.J.O.M.; Ernst, L.J.; Ernst, L.J.

    2003-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  16. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    International Nuclear Information System (INIS)

    Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

    2010-01-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  17. Analysis of borophosphosilicate glass layers on silicon wafers by X-ray emission from photon and electron excitation

    International Nuclear Information System (INIS)

    Elgersma, O.; Borstrok, J.J.M.

    1989-01-01

    Phosphorus and oxygen concentrations in the homogeneous layer of borosilicate glass (BPSG) deposited on Si-integrated circuits are determined by X-ray fluorescence from photon excitation. The X-ray emission from electron excitation in an open X-ray tube instrument yields a sufficiently precise determination of the boron content. The thickness of the layer can be derived from silicon Kα-fluorescence. A calibration model is proposed for photon as well as for electron excitation. The experimentally determined parameters in this model well agree with those derived from fundamental parameters for X-ray absorption and emission. The chemical surrounding of silicon affects strongly the peak profile of the silicon Kβ-emission. This enables to distinguish emission from the silicon atoms in the wafer and from the silicon atoms in the silicon oxide complexes of the BPSG-layer. (author)

  18. Reliable four-point flexion test and model for die-to-wafer direct bonding

    Energy Technology Data Exchange (ETDEWEB)

    Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.; Moriceau, H. [Univ. Grenoble Alpes, F-38000 Grenoble, France and CEA, LETI, MINATEC Campus, F-38054 Grenoble (France)

    2015-07-07

    For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, both D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.

  19. Optimization of corn, rice and buckwheat formulations for gluten-free wafer production.

    Science.gov (United States)

    Dogan, Ismail Sait; Yildiz, Onder; Meral, Raciye

    2016-07-01

    Gluten-free baked products for celiac sufferers are essential for healthy living. Cereals having gluten such as wheat and rye must be removed from the diet for the clinical and histological improvement. The variety of gluten-free foods should be offered for the sufferers. In the study, gluten-free wafer formulas were optimized using corn, rice and buckwheat flours, xanthan and guar gum blend as an alternative product for celiac sufferers. Wafer sheet attributes and textural properties were investigated. Considering all wafer sheet properties in gluten-free formulas, better results were obtained by using 163.5% water, 0.5% guar and 0.1% xanthan in corn formula; 173.3% water, 0.45% guar and 0.15% xanthan gum in rice formula; 176% water, 0.1% guar and 0.5% xanthan gum in buckwheat formula. Average desirability values in gluten-free formulas were between 0.86 and 0.91 indicating they had similar visual and textural profiles to control sheet made with wheat flour. © The Author(s) 2015.

  20. Improving scanner wafer alignment performance by target optimization

    Science.gov (United States)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  1. The Evolution of Wafer Bonding Moving from the back-end further to the front-end

    Institute of Scientific and Technical Information of China (English)

    Thomas Glinsner; Peter Hangweier

    2009-01-01

    @@ 1 Introduction As the nanoscale era progresses, innovative new materials and processes continue to be developed and implemented as a means of keeping the industry on the path of Moore's Law. Wafer bonding - literally, the temporary or permanent joining of two wafers or substrates using a suitable combination of process technologies, chemicals and adhesives - is one such innovation.

  2. Improvements to the solar cell efficiency and production yields of low-lifetime wafers with effective phosphorus gettering

    International Nuclear Information System (INIS)

    Lu, Jiunn-Chenn; Chen, Ping-Nan; Chen, Chih-Min; Wu, Chung-Han

    2013-01-01

    Highlights: • Variable-temperature gettering improves efficiencies when the wafer quality is poor. • High-quality wafers need not be used for variable-temperature gettering. • The proposed gettering method is based on an existing diffusion process. • It has a potential interest for hot-spot prevention. -- Abstract: This research focuses on the improvement of solar cell efficiencies in low-lifetime wafers by implementing an appropriate gettering method of the diffusion process. The study also considers a reduction in the value of the reverse current at −12 V, an important electrical parameter related to the hot-spot heating of solar cells and modules, to improve the product's quality during commercial mass production. A practical solar cell production case study is examined to illustrate the use of the proposed method. The results of this case study indicate that variable-temperature gettering significantly improves solar cell efficiencies by 0.14% compared to constant-temperature methods when the wafer quality is poor. Moreover, this study finds that variable-temperature gettering raises production yields of low quality wafers by more than 30% by restraining the measurement value of the reverse current at −12 V during solar cell manufacturing

  3. Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

    Institute of Scientific and Technical Information of China (English)

    潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

    2011-01-01

    Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95% active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

  4. Bonding of Si wafers by surface activation method for the development of high efficiency high counting rate radiation detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo; Yamashita, Makoto; Onabe, Hideaki

    2006-01-01

    Si wafers with two different resistivities ranging over two orders of magnitude were bonded by the surface activation method. The resistivities of bonded Si wafers were measured as a function of annealing temperature. Using calculations based on a model, the interface resistivities of bonded Si wafers were estimated as a function of the measured resistivities of bonded Si wafers. With thermal treatment from 500degC to 900degC, all interfaces showed high resistivity, with behavior that was close to that of an insulator. Annealing at 1000degC decreased the interface resistivity and showed close to ideal bonding after thermal treatment at 1100degC. (author)

  5. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.

    2018-01-02

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  6. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.; Kutbee, Arwa T.; Khan, Sherjeel M.; Sepulveda, Adrian C.; Wicaksono, Irmandy; Nour, Maha A.; Wehbe, Nimer; Almislem, Amani Saleh Saad; Ghoneim, Mohamed T.; Sevilla, Galo T.; Syed, Ahad; Shaikh, Sohail F.; Hussain, Muhammad Mustafa

    2018-01-01

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  7. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    International Nuclear Information System (INIS)

    Zhou Linsong; Rao Haibo; Wang Wei; Wan Xianlong; Liao Junyuan; Wang Xuemei; Zhou Da; Lei Qiaolin

    2013-01-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP. (semiconductor devices)

  8. Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

    Science.gov (United States)

    Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

    2016-03-01

    With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

  9. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    International Nuclear Information System (INIS)

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  10. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  11. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    Science.gov (United States)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  12. Prediction of UV spectra and UV-radiation damage in actual plasma etching processes using on-wafer monitoring technique

    International Nuclear Information System (INIS)

    Jinnai, Butsurin; Fukuda, Seiichi; Ohtake, Hiroto; Samukawa, Seiji

    2010-01-01

    UV radiation during plasma processing affects the surface of materials. Nevertheless, the interaction of UV photons with surface is not clearly understood because of the difficulty in monitoring photons during plasma processing. For this purpose, we have previously proposed an on-wafer monitoring technique for UV photons. For this study, using the combination of this on-wafer monitoring technique and a neural network, we established a relationship between the data obtained from the on-wafer monitoring technique and UV spectra. Also, we obtained absolute intensities of UV radiation by calibrating arbitrary units of UV intensity with a 126 nm excimer lamp. As a result, UV spectra and their absolute intensities could be predicted with the on-wafer monitoring. Furthermore, we developed a prediction system with the on-wafer monitoring technique to simulate UV-radiation damage in dielectric films during plasma etching. UV-induced damage in SiOC films was predicted in this study. Our prediction results of damage in SiOC films shows that UV spectra and their absolute intensities are the key cause of damage in SiOC films. In addition, UV-radiation damage in SiOC films strongly depends on the geometry of the etching structure. The on-wafer monitoring technique should be useful in understanding the interaction of UV radiation with surface and in optimizing plasma processing by controlling UV radiation.

  13. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    International Nuclear Information System (INIS)

    Montoya, Angela C.; Maji, Arup K.

    2010-01-01

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  14. Pb(Zr,Ti)O3-Pb(Mn1/3Nb2/3)O3 piezoelectric thick films by aerosol deposition

    International Nuclear Information System (INIS)

    Ryu, Jungho; Choi, Jong-Jin; Hahn, Byung-Dong; Yoon, Woon-Ha; Lee, Byoung-Kuk; Choi, Joon Hwan; Park, Dong-Soo

    2010-01-01

    Piezoelectric thick films of Pb(Zr,Ti)O 3 -Pb(Mn 1/3 Nb 2/3 )O 3 (PZT-PMnN) with Zr:Ti ratios ranging from 0.45:0.55 to 0.60:0.40 were fabricated on a platinized silicon wafer by aerosol deposition (AD). All the films were deposited with a thickness of 10 μm with high density. By adding PMnN to 57:43 PZT, a dielectric constant as low as ∼660 was achieved while the effective piezoelectric constant was over 140 pC/N. PZT-PMnN with a Zr:Ti ratio of 57:43 thus showed a maximum piezoelectric voltage constant (g 33 ) of 23.8 x 10 -3 Vm/N and is a good candidate for high quality thick films for application to high-energy density or high sensitivity, piezoelectric energy harvesters and sensors.

  15. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  16. Detection of trace contamination of copper on a silicon wafer with TXRF

    International Nuclear Information System (INIS)

    Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

    2000-01-01

    The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

  17. Thickness dependent structural, optical and electrical properties of Se85In12Bi3 nanochalcogenide thin films

    Science.gov (United States)

    Tripathi, Ravi P.; Zulfequar, M.; Khan, Shamshad A.

    2018-04-01

    Our aim is to study the thickness dependent effects on structure, electrical and optical properties of Se85In12Bi3 nanochalcogenide thin films. Bulk alloy of Se85In12Bi3 was synthesized by melt-quenching technique. The amorphous as well as glassy nature of Se85In12Bi3 chalcogenide was confirmed by non-isothermal Differential Scanning Calorimetry (DSC) measurements. The nanochalcogenide thin films of thickness 30, 60 and 90 nm were prepared on glass/Si wafer substrate using Physical Vapour Condensation Technique (PVCT). From XRD studies it was found that thin films have amorphous texture. The surface morphology and particle size of films were studied by Field Emission Scanning Electron Microscope (FESEM). From optical studies, different optical parameters were estimated for Se85In12Bi3 thin films at different thickness. It was found that the absorption coefficient (α) and extinction coefficient (k) increases with photon energy and decreases with film thickness. The optical absorption process followed the rule of indirect transitions and optical band gap were found to be increase with film thickness. The value of Urbach energy (Et) and steepness parameter (σ) were also calculated for different film thickness. For electrical studies, dc-conductivity measurement was done at different temperature and activation energy (ΔEc) were determined and found to be increase with film thickness.

  18. Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell

    Directory of Open Access Journals (Sweden)

    Michael J. Schöning

    2006-04-01

    Full Text Available A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor is realised by means of integration of a specifically designedcapillary electrochemical micro-droplet cell into a commercial wafer prober-station. Thedeveloped system allows the identification and selection of “good” ISFETs at the earlieststage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. Thedeveloped system is also feasible for wafer-level characterisation of ISFETs in terms ofsensitivity, hysteresis and response time. Additionally, the system might be also utilised forwafer-level testing of further electrochemical sensors.

  19. Effects of Thickness, Pulse Duration, and Size of Strip Electrode on Ferroelectric Electron Emission of Lead Zirconate Titanate Films

    Science.gov (United States)

    Yaseen, Muhammad; Ren, Wei; Chen, Xiaofeng; Feng, Yujun; Shi, Peng; Wu, Xiaoqing

    2018-02-01

    Sol-gel-derived lead zirconate titanate (PZT) thin-film emitters with thickness up to 9.8 μm have been prepared on Pt/TiO2/SiO2/Si wafer via chemical solution deposition with/without polyvinylpyrrolidone (PVP) modification, and the relationship between the film thickness and electron emission investigated. Notable electron emission was observed on application of a trigger voltage of 120 V for PZT film with thickness of 1.1 μm. Increasing the film thickness decreased the threshold field to initiate electron emission for non-PVP-modified films. In contrast, the electron emission behavior of PVP-modified films did not show significant dependence on film thickness, probably due to their porous structure. The emission current increased with decreasing strip width and space between strips. Furthermore, it was observed that increasing the duration of the applied pulse increased the magnitude of the emission current. The stray field on the PZT film thickness was also calculated and found to increase with increasing ferroelectric sample thickness. The PZT emitters were found to be fatigue free up to 105 emission cycles. Saturated emission current of around 25 mA to 30 mA was achieved for the electrode pattern used in this work.

  20. RBS-study of GexSi1-x Compounds Formed by Variable Dose Ge Implantation into Si Wafers

    Directory of Open Access Journals (Sweden)

    Ramírez A.

    2002-01-01

    Full Text Available Amorphous and relaxed epitaxial GeSi films are prepared by Ge-implantation into Si(111 wafers of both 60 keV and 200 keV energetic Ge+-ions with appropriate dose, followed by post-implantation thermal annealing, comprising a single final annealing at a temperature of 900 °C. The implantation dose was varied between 10(14 and 10(17 atoms cm-2. Rutherford backscattering (RBS and channeling analysis was applied in order to explore the formation of a single crystalline Si-Ge compound layer, both prior and after the thermal treatment. The depth and the thickness of the implanted layer, as well as their molar composition and crystalline quality was determined, and it was found that a single crystalline Si-Ge alloy layer was created, with both depth and mole fraction depending on the ion energy and the ion dose.

  1. Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

    International Nuclear Information System (INIS)

    Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

    2012-01-01

    Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

  2. Investigation of Surface Pre-Treatment Methods for Wafer-Level Cu-Cu Thermo-Compression Bonding

    Directory of Open Access Journals (Sweden)

    Koki Tanaka

    2016-12-01

    Full Text Available To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS measurement of the H2/Ar plasma–treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.

  3. High quality single atomic layer deposition of hexagonal boron nitride on single crystalline Rh(111) four-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Hemmi, A.; Bernard, C.; Cun, H.; Roth, S.; Klöckner, M.; Kälin, T.; Osterwalder, J.; Greber, T., E-mail: greber@physik.uzh.ch [Physik-Institut, Universität Zürich, CH-8057 Zürich (Switzerland); Weinl, M.; Gsell, S.; Schreck, M. [Institut für Physik, Universität Augsburg, D-86135 Augsburg (Germany)

    2014-03-15

    The setup of an apparatus for chemical vapor deposition (CVD) of hexagonal boron nitride (h-BN) and its characterization on four-inch wafers in ultra high vacuum (UHV) environment is reported. It provides well-controlled preparation conditions, such as oxygen and argon plasma assisted cleaning and high temperature annealing. In situ characterization of a wafer is accomplished with target current spectroscopy. A piezo motor driven x-y stage allows measurements with a step size of 1 nm on the complete wafer. To benchmark the system performance, we investigated the growth of single layer h-BN on epitaxial Rh(111) thin films. A thorough analysis of the wafer was performed after cutting in atmosphere by low energy electron diffraction, scanning tunneling microscopy, and ultraviolet and X-ray photoelectron spectroscopies. The apparatus is located in a clean room environment and delivers high quality single layers of h-BN and thus grants access to large area UHV processed surfaces, which had been hitherto restricted to expensive, small area single crystal substrates. The facility is versatile enough for customization to other UHV-CVD processes, e.g., graphene on four-inch wafers.

  4. In situ beam angle measurement in a multi-wafer high current ion implanter

    International Nuclear Information System (INIS)

    Freer, B.S.; Reece, R.N.; Graf, M.A.; Parrill, T.; Polner, D.

    2005-01-01

    Direct, in situ measurement of the average angle and angular content of an ion beam in a multi-wafer ion implanter is reported for the first time. A new type of structure and method are described. The structures are located on the spinning disk, allowing precise angular alignment to the wafers. Current that passes through the structures is known to be within a range of angles and is detected behind the disk. By varying the angle of the disk around two axes, beam current versus angle is mapped and the average angle and angular spread are calculated. The average angle measured in this way is found to be consistent with that obtained by other techniques, including beam centroid offset and wafer channeling methods. Average angle of low energy beams, for which it is difficult to use other direct methods, is explored. A 'pencil beam' system is shown to give average angle repeatability of 0.13 deg. (1σ) or less, for two low energy beams under normal tuning variations, even though no effort was made to control the angle

  5. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    Science.gov (United States)

    Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  6. Simplified nonplanar wafer bonding for heterogeneous device integration

    Science.gov (United States)

    Geske, Jon; Bowers, John E.; Riley, Anton

    2004-07-01

    We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

  7. The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

    Science.gov (United States)

    Lee, Jeffrey; McGarvey, Steve

    2013-04-01

    The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

  8. Application of a layout/material handling design method to a furnace area in a 300 mm wafer fab

    NARCIS (Netherlands)

    Hesen, P.M.C.; Renders, P.J.J.; Rooda, J.E.

    2001-01-01

    For many years, material handling within the semiconductor industry has become increasingly important. With the introduction of 300 mm wafer production, ergonomics and product safety become more critical. Therefore, the manufacturers of semiconductor wafer fabs are considering the automation of

  9. Improved delivery of the anticancer agent citral using BSA nanoparticles and polymeric wafers

    Directory of Open Access Journals (Sweden)

    White B

    2017-12-01

    Full Text Available Benjamin White,1 Anna Evison,1 Eszter Dombi,1 Helen E Townley1,2 1Nuffield Department of Obstetrics and Gynaecology, Women’s Centre, John Radcliffe Hospital, 2Department of Engineering Science, Oxford University, Oxford, UK Abstract: Rhabdomyosarcoma (RMS is the most common soft tissue sarcoma in children, with a 5-year survival rate of between 30 and 65%. Standard treatment involves surgery, radiation treatment, and chemotherapy. However, there is a high recurrence rate, particularly from locoregional spread. We investigated the use of the natural compound citral (3,7-dimethyl-2,6-octadienal, which can be found in a number of plants, but is particularly abundant in lemon grass (Cymbopogon citratus oil, for activity against immortalized RMS cells. Significant cancer cell death was seen at concentrations above 150 μM citral, and mitochondrial morphological changes were seen after incubation with 10 μM citral. However, since citral is a highly volatile molecule, we prepared albumin particles by a desolvation method to encapsulate citral, as a means of stabilization. We then further incorporated the loaded nanoparticles into a biodegradable polyanhydride wafer to generate a slow release system. The wafers were shown to degrade by 50% over the course of 25 days and to release the active compound. We therefore propose the use of the citral-nanoparticle-polymer wafers for implantation into the tumor bed after surgical removal of a sarcoma as a means to control locoregional spread due to any remaining cancerous cells. Keywords: citral, nanoparticle, wafer, biodegradable, mitochondria, toroidal, cancer, rhabdomyosarcoma, Cymbopogon citratus

  10. ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

    Science.gov (United States)

    Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

    2016-05-01

    At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts

  11. Role of the SiO2 buffer layer thickness in the formation of Si/SiO2/nc-Ge/SiO2 structures by dry oxidation

    International Nuclear Information System (INIS)

    Kling, A.; Ortiz, M.I.; Prieto, A.C.; Rodriguez, A.; Rodriguez, T.; Jimenez, J.; Ballesteros, C.; Soares, J.C.

    2006-01-01

    Nanomemories, containing Ge-nanoparticles in a SiO 2 matrix, can be produced by dry thermal oxidation of a SiGe layer deposited onto a Si-wafer with a barrier SiO 2 layer on its top. Rutherford backscattering spectrometry has been used to characterize the kinetics of the oxidation process, the composition profile of the growing oxide, the Ge-segregation and its diffusion into the barrier oxide in samples with thin and thick barrier oxide layers. The Ge segregated during the oxidation of the SiGe layer diffuses into the barrier oxide. In the first case the diffusion through the thin oxide is enhanced by the proximity of the substrate that acts as a sink for the Ge, resulting in the formation of a low Ge concentration SiGe layer in the surface of the Si-wafer. In the second case, the Ge-diffusion progresses as slowly as in bulk SiO 2 . Since barrier oxide layers as thin as possible are favoured for device fabrication, the structures should be oxidized at lower temperatures and the initial SiGe layer thickness reduced to minimize the Ge-diffusion

  12. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  13. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  14. Research Update: Enhanced energy storage density and energy efficiency of epitaxial Pb0.9La0.1(Zr0.52Ti0.48O3 relaxor-ferroelectric thin-films deposited on silicon by pulsed laser deposition

    Directory of Open Access Journals (Sweden)

    Minh D. Nguyen

    2016-08-01

    Full Text Available Pb0.9La0.1(Zr0.52Ti0.48O3 (PLZT relaxor-ferroelectric thin films were grown on SrRuO3/SrTiO3/Si substrates by pulsed laser deposition. A large recoverable storage density (Ureco of 13.7 J/cm3 together with a high energy efficiency (η of 88.2% under an applied electric field of 1000 kV/cm and at 1 kHz frequency was obtained in 300-nm-thick epitaxial PLZT thin films. These high values are due to the slim and asymmetric hysteresis loop when compared to the values in the reference undoped epitaxial lead zirconate titanate Pb(Zr0.52Ti0.48O3 ferroelectric thin films (Ureco = 9.2 J/cm3 and η = 56.4% which have a high remanent polarization and a small shift in the hysteresis loop, under the same electric field.

  15. Multiproject wafers: not just for million-dollar mask sets

    Science.gov (United States)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  16. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    Science.gov (United States)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  17. Serial section scanning electron microscopy (S3EM) on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Science.gov (United States)

    Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

    2012-01-01

    High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3)EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3) volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3)EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3)EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  18. Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Directory of Open Access Journals (Sweden)

    Heinz Horstmann

    Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  19. Spatially resolved localized vibrational mode spectroscopy of carbon in liquid encapsulated Czochralski grown gallium arsenide wafers

    International Nuclear Information System (INIS)

    Yau, Waifan.

    1988-04-01

    Substitutional carbon on an arsenic lattice site is the shallowest and one of the most dominant acceptors in semi-insulating Liquid Encapsulated Czochralski (LEC) GaAs. However, the role of this acceptor in determining the well known ''W'' shape spatial variation of neutral EL2 concentration along the diameter of a LEC wafer is not known. In this thesis, we attempt to clarify the issue of the carbon acceptor's effect on this ''W'' shaped variation by measuring spatial profiles of this acceptor along the radius of three different as-grown LEC GaAs wafers. With localized vibrational mode absorption spectroscopy, we find that the profile of the carbon acceptor is relatively constant along the radius of each wafer. Average values of concentration are 8 x 10E15 cm -3 , 1.1 x 10E15 cm -3 , and 2.2 x 10E15 cm -3 , respectively. In addition, these carbon acceptor LVM measurements indicate that a residual donor with concentration comparable to carbon exists in these wafers and it is a good candidate for the observed neutral EL2 concentration variation. 22 refs., 39 figs

  20. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

    Science.gov (United States)

    Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

    2018-07-01

    This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

  1. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Directory of Open Access Journals (Sweden)

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  2. Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

    International Nuclear Information System (INIS)

    Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

    2004-01-01

    Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

  3. Fusion bonding of Si wafers investigated by x ray diffraction

    DEFF Research Database (Denmark)

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

  4. Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

    Science.gov (United States)

    Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

    2016-11-01

    The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

  5. Investigation of room-temperature wafer bonded GaInP/GaAs/InGaAsP triple-junction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Wen-xian; Dai, Pan; Ji, Lian; Tan, Ming; Wu, Yuan-yuan [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Uchida, Shiro [Department of Mechanical Science and Engineering Faculty of Engineering, Chiba Institute of Technology, 2-17-1, Tsudanuma, Narashino, Chiba 275-0016 (Japan); Lu, Shu-long, E-mail: sllu2008@sinano.ac.cn [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Yang, Hui [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China)

    2016-12-15

    Highlights: • High quality InGaAsP material with a bandgap of 1.0 eV was grown by MBE. • Room-temperature wafer-bonded GaInP/GaAs/InGaAsP SCs were fabricated. • An efficiency of 30.3% of wafer-bonded triple-junction SCs was obtained. - Abstract: We report on the fabrication of III–V compound semiconductor multi-junction solar cells using the room-temperature wafer bonding technique. GaInP/GaAs dual-junction solar cells on GaAs substrate and InGaAsP single junction solar cell on InP substrate were separately grown by all-solid state molecular beam epitaxy (MBE). The two cells were then bonded to a triple-junction solar cell at room-temperature. A conversion efficiency of 30.3% of GaInP/GaAs/InGaAsP wafer-bonded solar cell was obtained at 1-sun condition under the AM1.5G solar simulator. The result suggests that the room-temperature wafer bonding technique and MBE technique have a great potential to improve the performance of multi-junction solar cell.

  6. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  7. Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

    International Nuclear Information System (INIS)

    Moslehi, M.M.; Davis, C.

    1989-01-01

    Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

  8. Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

    Science.gov (United States)

    Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

    2013-08-20

    To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

  9. Eutectic and solid-state wafer bonding of silicon with gold

    International Nuclear Information System (INIS)

    Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

    2012-01-01

    Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  10. Analysis of different coating thickness on new type of planar interdigital sensors for endotoxin detection

    KAUST Repository

    Syaifudin, A. R Mohd

    2013-05-01

    New types of planar interdigital sensors have been fabricated on Silicon/Silicon Dioxide (Si/SiO2) wafers. The sensors were coated with pre-cursor silica functionalized with APTES (3-aminopropyltrietoxysilane) at different thicknesses. All sensors were then immobilized with Polymyxin, B (PmB). PmB is an antimicrobial peptide produced by the Gram-positive bacterium-Bacillus, has been immobilized on the coated sensors because of its specific binding properties to endotoxin. Studies were conducted to analyze the effect of different thicknesses of coatings on the sensitivity and selectivity of the sensors. It was observed sensors coated with 3 layers of coating has better sensitivity and selectivity to the target molecules (endotoxin) compared to sensors with 5 layers of coating. The repeatability and stability of the coated sensors were tested by multiple standard endotoxin measurement and it was observed that the sensors give a good reproducibility and stability up to six continuous measurements before the coating degrades. © 2013 IEEE.

  11. High-throughput characterization of stresses in thin film materials libraries using Si cantilever array wafers and digital holographic microscopy

    International Nuclear Information System (INIS)

    Lai, Y. W.; Ludwig, A.; Hamann, S.; Ehmann, M.

    2011-01-01

    We report the development of an advanced high-throughput stress characterization method for thin film materials libraries sputter-deposited on micro-machined cantilever arrays consisting of around 1500 cantilevers on 4-inch silicon-on-insulator wafers. A low-cost custom-designed digital holographic microscope (DHM) is employed to simultaneously monitor the thin film thickness, the surface topography and the curvature of each of the cantilevers before and after deposition. The variation in stress state across the thin film materials library is then calculated by Stoney's equation based on the obtained radii of curvature of the cantilevers and film thicknesses. DHM with nanometer-scale out-of-plane resolution allows stress measurements in a wide range, at least from several MPa to several GPa. By using an automatic x-y translation stage, the local stresses within a 4-inch materials library are mapped with high accuracy within 10 min. The speed of measurement is greatly improved compared with the prior laser scanning approach that needs more than an hour of measuring time. A high-throughput stress measurement of an as-deposited Fe-Pd-W materials library was evaluated for demonstration. The fast characterization method is expected to accelerate the development of (functional) thin films, e.g., (magnetic) shape memory materials, whose functionality is greatly stress dependent.

  12. Comparative study on the predictability of statistical models (RSM and ANN) on the behavior of optimized buccoadhesive wafers containing Loratadine and their in vivo assessment.

    Science.gov (United States)

    Chakraborty, Prithviraj; Parcha, Versha; Chakraborty, Debarupa D; Ghosh, Amitava

    2016-01-01

    Buccoadhesive wafer dosage form containing Loratadine is formulated utilizing Formulation by Design (FbD) approach incorporating sodium alginate and lactose monohydrate as independent variable employing solvent casting method. The wafers were statistically optimized using Response Surface Methodology (RSM) and Artificial Neural Network algorithm (ANN) for predicting physicochemical and physico-mechanical properties of the wafers as responses. Morphologically wafers were tested using SEM. Quick disintegration of the samples was examined employing Optical Contact Angle (OCA). The comparison of the predictability of RSM and ANN showed a high prognostic capacity of RSM model over ANN model in forecasting mechanical and physicochemical properties of the wafers. The in vivo assessment of the optimized buccoadhesive wafer exhibits marked increase in bioavailability justifying the administration of Loratadine through buccal route, bypassing hepatic first pass metabolism.

  13. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  14. Ellipsometry measurements of thickness of oxide and water layers on spherical and flat silicon surfaces

    International Nuclear Information System (INIS)

    Kenny, M.J.; Netterfield, R.; Wielunski, L.S.

    1998-01-01

    Full text: Ellipsometry has been used to measure the thickness of oxide layers on single crystal silicon surfaces, both flat and spherical and also to measure the extent of adsorption of moisture on the surface as a function of partial water vapour pressure. The measurements form part of an international collaborative project to make a precise determination of the Avogadro constant (ΔN A /N A -8 ) which will then be used to obtain an absolute definition of the kilogram, rather than one in terms of an artefact. Typically the native oxide layer on a cleaned silicon wafer is about 2 nm thick. On a polished sphere this oxide layer is typically 8 to 10 nm thick, the increased thickness being attributed to parameters related to the polishing process. Ellipsometry measurements on an 89 mm diameter polished silicon sphere at both VUW and CSIRO indicated a SiO 2 layer at 7 to 10 nm thick. It was observed that this thickness varied regularly. The crystal orientation of the sphere was determined using electron patterns generated from an electron microscope and the oxide layer was then measured through 180 arcs of great circles along (110) and (100) planes. It was observed that the thickness varied systematically with orientation. The minimum thickness was 7.4 nm at the axis (softest direction in silicon) and the greatest thickness was 9.5 nm at the axis (hardest direction in silicon). This is similar to an orientation dependent cubic pattern which has been observed to be superimposed on polished silicon spheres. At VUW, the sphere was placed in an evacuated bell jar and the ellipsometry signal was observed as the water vapour pressure was progressively increased up to saturation. The amount of water vapour adsorbed at saturation was one or two monolayers, indicating that the sphere does not wet

  15. Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

    Science.gov (United States)

    Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

    2013-04-01

    In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

  16. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Science.gov (United States)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  17. Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

    Science.gov (United States)

    Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

    2003-12-01

    Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

  18. Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

    Science.gov (United States)

    Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

    2018-06-01

    Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

  19. Voltage-assisted polymer wafer bonding

    International Nuclear Information System (INIS)

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  20. Wafer-scale integration of piezoelectric actuation capabilities in nanoelectromechanical systems resonators

    OpenAIRE

    DEZEST, Denis; MATHIEU, Fabrice; MAZENQ, Laurent; SOYER, Caroline; COSTECALDE, Jean; REMIENS, Denis; THOMAS, Olivier; DEÜ, Jean-François; NICU, Liviu

    2013-01-01

    In this work, we demonstrate the integration of piezoelectric actuation means on arrays of nanocantilevers at the wafer scale. We use lead titanate zirconate (PZT) as piezoelectric material mainly because of its excellent actuation properties even when geometrically constrained at extreme scale

  1. A facility for plastic deformation of germanium single-crystal wafers

    DEFF Research Database (Denmark)

    Lebech, B.; Theodor, K.; Breiting, B.

    1998-01-01

    . All movements and temperature changes are done by a robot via a PLC-control system. Two nine-crystal focusing monochromators (54 x 116 and 70 x 116 mm(2)) made from 100 wafers with average mosaicity similar to 13' have been constructed. Summaries of the test results are presented. (C) 1998 Elsevier...

  2. Enlarging photovoltaic effect: combination of classic photoelectric and ferroelectric photovoltaic effects.

    Science.gov (United States)

    Zhang, Jingjiao; Su, Xiaodong; Shen, Mingrong; Dai, Zhihua; Zhang, Lingjun; He, Xiyun; Cheng, Wenxiu; Cao, Mengyu; Zou, Guifu

    2013-01-01

    Converting light energy to electrical energy in photovoltaic devices relies on the photogenerated electrons and holes separated by the built-in potential in semiconductors. Photo-excited electrons in metal electrodes are usually not considered in this process. Here, we report an enhanced photovoltaic effect in the ferroelectric lanthanum-modified lead zirconate titanate (PLZT) by using low work function metals as the electrodes. We believe that electrons in the metal with low work function could be photo-emitted into PLZT and form the dominant photocurrent in our devices. Under AM1.5 (100 mW/cm²) illumination, the short-circuit current and open-circuit voltage of Mg/PLZT/ITO are about 150 and 2 times of those of Pt/PLZT/ITO, respectively. The photovoltaic response of PLZT capacitor was expanded from ultraviolet to visible spectra, and it may have important impact on design and fabrication of high performance photovoltaic devices based on ferroelectric materials.

  3. Effect of La doping on crystalline orientation, microstructure and dielectric properties of PZT thin films

    Energy Technology Data Exchange (ETDEWEB)

    Xu, Wencai; Li, Qi; Wang, Xing [Dalian Univ. of Technology, Dalian (China). School of Mechanical Engineering; Yin, Zhifu [Jilin Univ., Changchun (China). Faculty of the School of Mechanical Science and Engineering; Zou, Helin [Dalian Univ. of Technology, Dalian (China). Key Lab. for Micro/Nano Systems and Technology

    2017-11-01

    Lanthanum (La)-modified lead zirconate titanate (PLZT) thin films with doping concentration from 0 to 5 at.-% have been fabricated by sol-gel methods to investigate the effects of La doping on crystalline orientation, microstructure and dielectric properties of the modified films. The characterization of PLZT thin films were performed by X-ray diffractometry (XRD), scanning electron microscopy (SEM) and precision impedance analysis. XRD analysis showed that PLZT films with La doping concentration below 4 at.-% exhibited (100) preferred orientation. SEM results indicated that PLZT films presented dense and columnar microstructures when La doping concentration was less than 3 at.-%, while the others showed columnar microstructures only at the bottom of the cross section. The maximum dielectric constant (1502.59 at 100 Hz) was obtained in a 2 at.-% La-doped film, which increased by 53.9 % compared with undoped film. Without introducing a seed layer, (100) oriented PLZT thin films were prepared by using conventional heat treatment process and adjusting La doping concentration.

  4. Synchrotron radiation induced TXRF of low Z elements on Si wafer surfaces at SSRL-comparison of excitation geometries and condition

    International Nuclear Information System (INIS)

    Streli, C.; Wobrauschek, P.; Kregsamer, P.; Pepponi, G.; Pianetta, P.; Pahlke, S.; Fabry, L.

    2000-01-01

    The determination of low Z elements, like Na and Al at ultra trace levels on Si wafer surfaces is demanded by semiconductor industry. SR-TXRF is a promising method to fulfill the task, if a special energy dispersive detector with an ultra thin window is used. Synchrotron radiation is the ideal suited excitation source for TXRF of low Z elements due to its intensive, natural collimated and linear polarized radiation with wide spectral range down to low energies even below 1 keV. TXRF offers some advantages for wafer surface analysis like nondestructive investigation and mapping capability. Experiments have been performed at SSRL beamline 3-4, a bending magnet beamline using white (<3 keV) and monochromatic radiation, as well as on beamline 3-3, using a crystal monochromator as well as a multilayer monochromator. A comparison of excitation detection geometries was performed, using a sidelooking detector with vertical positioned wafer as well as a downlooking detector with a horizontally arranged wafer. The advantages and disadvantages of the various geometries and excitation conditions are presented and the results compared. Detection limits are in the 100 fg range for Na, determined with droplet samples on Si wafer surfaces. (author)

  5. An Improved Dispatching Method (a-HPDB for Automated Material Handling System with Active Rolling Belt for 450 mm Wafer Fabrication

    Directory of Open Access Journals (Sweden)

    Chia-Nan Wang

    2017-07-01

    Full Text Available The semiconductor industry is facing the transition from 300 mm to 450 mm wafer fabrication. Due to the increased size and weight, 450 mm wafers will pose unprecedented challenges on semiconductor wafer fabrication. To better handle and transport 450 mm wafers, an advanced Automated Material Handling System (AMHS is definitely required. Though conveyor-based AMHS is expected to be suitable for 450 mm wafer fabrication, still it faces two main problems, traffic-jam problem and lot-prioritization. To address the two problems, in this research we have proposed an improved dispatching method, termed Heuristic Preemptive Dispatching Method using Activated Roller Belt (a-HPDB. We have developed some effective rules for the a-HPDB based on Activated Roller Belt (ARB. In addition, we have conducted experiments to investigate its effectiveness. Compared with the HPDB and R-HPD, two dispatching rules proposed in previous studies, our experimental results showed the a-HPDB had a better performance in terms of average lot delivery time (ALDT. For hot lots and normal lots, the a-HPDB had advantages of 4.14% and 8.92% over the HPDB and advantages of 4.89% and 8.52% over R-HPD, respectively.

  6. Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

    2016-02-15

    Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

  7. Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2013-01-01

    Full Text Available Ultrathin body (UTB and nanoscale body (NSB SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

  8. A full-wafer fabrication process for glass microfluidic chips with integrated electroplated electrodes by direct bonding of dry film resist

    International Nuclear Information System (INIS)

    Vulto, Paul; Urban, G A; Huesgen, Till; Albrecht, Björn

    2009-01-01

    A full-wafer process is presented for fast and simple fabrication of glass microfluidic chips with integrated electroplated electrodes. The process employs the permanent dry film resist (DFR) Ordyl SY300 to create microfluidic channels, followed by electroplating of silver and subsequent chlorination. The dry film resist is bonded directly to a second substrate, without intermediate gluing layers, only by applying pressure and moderate heating. The process of microfluidic channel fabrication, electroplating and wafer bonding can be completed within 1 day, thus making it one of the fastest and simplest full-wafer fabrication processes. (note)

  9. Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

    Science.gov (United States)

    Tanake, Katsuaki

    InP/Si substrates for bulk InP in the fabrication of such a four-junction solar cell could significantly reduce the substrate cost since the current prices for commercial InP substrates are much higher than those for Si substrates by two orders of magnitude. Direct heteroepitaxial growth of InP thin films on Si substrates has not produced the low dislocation-density high quality layers required for active InGaAs/InP in optoelectronic devices due to the ˜8% lattice mismatch between InP and Si. We successfully fabricated InP/Si substrates by He implantation of InP prior to bonding to a thermally oxidized Si substrate and annealing to exfoliate an InP thin film. The thickness of the exfoliated InP films was only 900 nm, which means hundreds of the InP/Si substrates could be prepared from a single InP wafer in principle. The photovoltaic current-voltage characteristics of the In0.53Ga0.47As cells fabricated on the wafer-bonded InP/Si substrates were comparable to those synthesized on commercially available epi-ready InP substrates, and had a ˜20% higher short-circuit current which we attribute to the high reflectivity of the InP/SiO2/Si bonding interface. This work provides an initial demonstration of wafer-bonded InP/Si substrates as an alternative to bulk InP substrates for solar cell applications. We have observed photocurrent enhancements up to 260% at 900 nm for a GaAs cell with a dense array of Ag nanoparticles with 150 nm diameter and 20 nm height deposited through porous alumina membranes by thermal evaporation on top of the cell, relative to reference GaAs cells with no metal nanoparticle array. This dramatic photocurrent enhancement is attributed to the effect of metal nanoparticles to scatter the incident light into photovoltaic layers with a wide range of angles to increase the optical path length in the absorber layer. GaAs solar cells with metallic structures at the bottom of the photovoltaic active layers, not only at the top, using semiconductor

  10. Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

    Energy Technology Data Exchange (ETDEWEB)

    Ayari, Taha; Li, Xin; Voss, Paul L.; Ougazzaden, Abdallah, E-mail: aougazza@georgiatech-metz.fr [School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332 (United States); Georgia Tech Lorraine, UMI 2958, Georgia Tech-CNRS, 57070 Metz (France); Sundaram, Suresh; El Gmili, Youssef [Georgia Tech Lorraine, UMI 2958, Georgia Tech-CNRS, 57070 Metz (France); Salvestrini, Jean Paul [Georgia Tech Lorraine, UMI 2958, Georgia Tech-CNRS, 57070 Metz (France); Université de Lorraine, LMOPS, EA 4423, 57070 Metz (France)

    2016-04-25

    Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure to be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.

  11. Integrated optical MEMS using through-wafer vias and bump-bonding.

    Energy Technology Data Exchange (ETDEWEB)

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  12. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  13. Characterization and control of wafer charging effects during high-current ion implantation

    International Nuclear Information System (INIS)

    Current, M.I.; Lukaszek, W.; Dixon, W.; Vella, M.C.; Messick, C.; Shideler, J.; Reno, S.

    1994-02-01

    EEPROM-based sense and memory devices provide direct measures of the charge flow and potentials occurring on the surface of wafers during ion beam processing. Sensor design and applications for high current ion implantation are discussed

  14. Regression Methods for Virtual Metrology of Layer Thickness in Chemical Vapor Deposition

    DEFF Research Database (Denmark)

    Purwins, Hendrik; Barak, Bernd; Nagi, Ahmed

    2014-01-01

    The quality of wafer production in semiconductor manufacturing cannot always be monitored by a costly physical measurement. Instead of measuring a quantity directly, it can be predicted by a regression method (Virtual Metrology). In this paper, a survey on regression methods is given to predict...... average Silicon Nitride cap layer thickness for the Plasma Enhanced Chemical Vapor Deposition (PECVD) dual-layer metal passivation stack process. Process and production equipment Fault Detection and Classification (FDC) data are used as predictor variables. Various variable sets are compared: one most...... algorithm, and Support Vector Regression (SVR). On a test set, SVR outperforms the other methods by a large margin, being more robust towards changes in the production conditions. The method performs better on high-dimensional multivariate input data than on the most predictive variables alone. Process...

  15. Influence of the Molecular Adhesion Force on the Indentation Depth of a Particle into the Wafer Surface in the CMP Process

    Directory of Open Access Journals (Sweden)

    Zhou Jianhua

    2014-01-01

    Full Text Available By theoretical calculation, the external force on the particle conveyed by pad asperities and the molecular adhesion force between particle and wafer are compared and analyzed quantitatively. It is confirmed that the molecular adhesion force between particle and wafer has a great influence on the chemical mechanical polishing (CMP material removal process. Considering the molecular adhesion force between particle and wafer, a more precise model for the indentation of a particle into the wafer surface is developed in this paper, and the new model is compared with the former model which neglected the molecular adhesion force. Through theoretical analyses, an approach and corresponding critical values are applied to estimate whether the molecular adhesion force in CMP can be neglected. These methods can improve the precision of the material removal model of CMP.

  16. Radiation imaging detectors made by wafer post-processing of CMOS chips

    NARCIS (Netherlands)

    Blanco Carballo, V.M.

    2009-01-01

    In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

  17. Wafer bowing control of free-standing heteroepitaxial diamond (100) films grown on Ir(100) substrates via patterned nucleation growth

    International Nuclear Information System (INIS)

    Yoshikawa, Taro; Kodama, Hideyuki; Kono, Shozo; Suzuki, Kazuhiro; Sawabe, Atsuhito

    2015-01-01

    The potential of patterned nucleation growth (PNG) technique to control the wafer bowing of free-standing heteroepitaxial diamond films was investigated. The heteroepitaxial diamond (100) films were grown on an Ir(100) substrate via PNG technique with different patterns of nucleation regions (NRs), which were dot-arrays with 8 or 13 μm pitch aligned to < 100 > or < 110 > direction of the Ir(100) substrate. The wafer bows and the local stress distributions of the free-standing films were measured using a confocal micro-Raman spectrometer. For each NR pattern, the stress evolutions within the early stage of diamond growth were also studied together with a scanning electron microscopic observation of the coalescing diamond particles. These investigations revealed that the NR pattern, in terms of pitch and direction of dot-array, strongly affects the compressive stress on the nucleation side of the diamond film and dominantly contributes to the elastic deformation of the free-standing film. This indicates that the PNG technique with an appropriate NR pattern is a promising solution to fabricate free-standing heteroepitaxial diamond films with extremely small bows. - Highlights: • Wafer bowing control of free-standing heteroepitaxial diamond (100) films • Effect of patterned nucleation and growth (PNG) technique on wafer bowing reduction • Influence of nucleation region patterns of PNG on wafer bowing • Internal stress analysis of PNG films via confocal micro-Raman spectroscopy

  18. Study of the semiconductor properties by irradiation, 8. Study of trapping center by. gamma. -ray on Si wafer

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Koji; Shioya, Hitoshi; Nagamatsu, Yasuhiko; Ogura, Shoji [Miyazaki Univ. (Japan). Faculty of Engineering

    1983-08-01

    In order to know the effects of ..gamma..-ray irradiation on n-type Si-wafers, the author did ..gamma..-ray irradiation experiments on n-type Si-wafers. They then observed the trapping center by using DLTS and ICTS equipments. The trapping center level, which is produced by ..gamma..-ray, is about 0.49 eV. In addition, the authors discuss the recombination rate.

  19. An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

    International Nuclear Information System (INIS)

    Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

    2007-01-01

    The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

  20. Thermal modelling of the multi-stage heating system with variable boundary conditions in the wafer based precision glass moulding process

    DEFF Research Database (Denmark)

    Sarhadi, Ali; Hattel, Jesper Henri; Hansen, Hans Nørgaard

    2012-01-01

    pressures. Finally, the three-dimensional modelling of the multi-stage heating system in the wafer based glass moulding process is simulated with the FEM software ABAQUS for a particular industrial application for mobile phone camera lenses to obtain the temperature distribution in the glass wafer...

  1. Use of acoustic waves and x-ray radiation for determination of small deformations in monocrystalline Si wafers

    International Nuclear Information System (INIS)

    Gavrilov, V.N.; Myasishchev, D.E.; Raitman, E.A.

    2006-01-01

    The paper describes a new method for determination of inhomogeneous deformations in monocrystalline semiconductor wafers. The physical basis of the method is dynamical scattering of X-rays by ultra-sound waves in the presence of static stresses in the crystal. By solving approximately a modified Takagi-Taupin equation the expressions have been obtained that describe relative variations of the diffraction intensity depending on the deformation gradient, the amplitude of ultra-sound wave and its frequency. The paper exemplifies the use of the method for analyzing the deformations and their distribution near the wafer surface in almost 'perfect' crystals and in oxidized wafers with etched windows. It is shown that the new method of nondestructive control, along with its relative simplicity, possesses high sensitivity allowing relative deformations of crystalline lattice of the order of 10-4-10-5 to be determined. (Authors)

  2. Comparison of on-wafer calibrations using the concept of reference impedance

    OpenAIRE

    Purroy Martín, Francesc; Pradell i Cara, Lluís

    1993-01-01

    A novel method that allows to compare different calibration techniques has been developed. It is based on determining the reference impedance of a given Network Analyzer calibration from the reflection coefficient measurement of a physical open circuit. The method has been applied to several on-wafer calibrations. Peer Reviewed

  3. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  4. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Science.gov (United States)

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  5. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  6. Wafer Surface Charge Reversal as a Method of Simplifying Nanosphere Lithography for Reactive Ion Etch Texturing of Solar Cells

    Directory of Open Access Journals (Sweden)

    Daniel Inns

    2007-01-01

    Full Text Available A simplified nanosphere lithography process has been developed which allows fast and low-waste maskings of Si surfaces for subsequent reactive ion etching (RIE texturing. Initially, a positive surface charge is applied to a wafer surface by dipping in a solution of aluminum nitrate. Dipping the positive-coated wafer into a solution of negatively charged silica beads (nanospheres results in the spheres becoming electrostatically attracted to the wafer surface. These nanospheres form an etch mask for RIE. After RIE texturing, the reflection of the surface is reduced as effectively as any other nanosphere lithography method, while this batch process used for masking is much faster, making it more industrially relevant.

  7. Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

    2012-03-01

    Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

  8. High-throughput characterization of stresses in thin film materials libraries using Si cantilever array wafers and digital holographic microscopy.

    Science.gov (United States)

    Lai, Y W; Hamann, S; Ehmann, M; Ludwig, A

    2011-06-01

    We report the development of an advanced high-throughput stress characterization method for thin film materials libraries sputter-deposited on micro-machined cantilever arrays consisting of around 1500 cantilevers on 4-inch silicon-on-insulator wafers. A low-cost custom-designed digital holographic microscope (DHM) is employed to simultaneously monitor the thin film thickness, the surface topography and the curvature of each of the cantilevers before and after deposition. The variation in stress state across the thin film materials library is then calculated by Stoney's equation based on the obtained radii of curvature of the cantilevers and film thicknesses. DHM with nanometer-scale out-of-plane resolution allows stress measurements in a wide range, at least from several MPa to several GPa. By using an automatic x-y translation stage, the local stresses within a 4-inch materials library are mapped with high accuracy within 10 min. The speed of measurement is greatly improved compared with the prior laser scanning approach that needs more than an hour of measuring time. A high-throughput stress measurement of an as-deposited Fe-Pd-W materials library was evaluated for demonstration. The fast characterization method is expected to accelerate the development of (functional) thin films, e.g., (magnetic) shape memory materials, whose functionality is greatly stress dependent. © 2011 American Institute of Physics

  9. Wafer-Scale Hierarchical Nanopillar Arrays Based on Au Masks and Reactive Ion Etching for Effective 3D SERS Substrate

    Directory of Open Access Journals (Sweden)

    Dandan Men

    2018-02-01

    Full Text Available Two-dimensional (2D periodic micro/nanostructured arrays as SERS substrates have attracted intense attention due to their excellent uniformity and good stability. In this work, periodic hierarchical SiO2 nanopillar arrays decorated with Ag nanoparticles (NPs with clean surface were prepared on a wafer-scale using monolayer Au NP arrays as masks, followed by reactive ion etching (RIE, depositing Ag layer and annealing. For the prepared SiO2 nanopillar arrays decorated with Ag NPs, the size of Ag NPs was tuned from ca. 24 to 126 nanometers by controlling the deposition thickness of Ag film. Importantly, the SiO2 nanopillar arrays decorated with Ag NPs could be used as highly sensitive SERS substrate for the detection of 4-aminothiophenol (4-ATP and rhodamine 6G (R6G due to the high loading of Ag NPs and a very uniform morphology. With a deposition thickness of Ag layer of 30 nm, the SiO2 nanopillar arrays decorated with Ag NPs exhibited the best sensitive SERS activity. The excellent SERS performance of this substrate is mainly attributed to high-density “hotspots” derived from nanogaps between Ag NPs. Furthermore, this strategy might be extended to synthesize other nanostructured arrays with a large area, which are difficult to be prepared only via conventional wet-chemical or physical methods.

  10. Wafer-Scale Hierarchical Nanopillar Arrays Based on Au Masks and Reactive Ion Etching for Effective 3D SERS Substrate.

    Science.gov (United States)

    Men, Dandan; Wu, Yingyi; Wang, Chu; Xiang, Junhuai; Yang, Ganlan; Wan, Changjun; Zhang, Honghua

    2018-02-04

    Two-dimensional (2D) periodic micro/nanostructured arrays as SERS substrates have attracted intense attention due to their excellent uniformity and good stability. In this work, periodic hierarchical SiO₂ nanopillar arrays decorated with Ag nanoparticles (NPs) with clean surface were prepared on a wafer-scale using monolayer Au NP arrays as masks, followed by reactive ion etching (RIE), depositing Ag layer and annealing. For the prepared SiO₂ nanopillar arrays decorated with Ag NPs, the size of Ag NPs was tuned from ca. 24 to 126 nanometers by controlling the deposition thickness of Ag film. Importantly, the SiO₂ nanopillar arrays decorated with Ag NPs could be used as highly sensitive SERS substrate for the detection of 4-aminothiophenol (4-ATP) and rhodamine 6G (R6G) due to the high loading of Ag NPs and a very uniform morphology. With a deposition thickness of Ag layer of 30 nm, the SiO₂ nanopillar arrays decorated with Ag NPs exhibited the best sensitive SERS activity. The excellent SERS performance of this substrate is mainly attributed to high-density "hotspots" derived from nanogaps between Ag NPs. Furthermore, this strategy might be extended to synthesize other nanostructured arrays with a large area, which are difficult to be prepared only via conventional wet-chemical or physical methods.

  11. Characterization of Si pixel detectors of different thickness

    International Nuclear Information System (INIS)

    Bisogni, M.G.; Boscardin, M.; Dalla Betta, G.F.; Delogu, P.; Fantacci, M.E.; Gregori, P.; Linsalata, S.; Novelli, M.; Piemonte, C.; Quattrocchi, M.; Rosso, V.; Stefanini, A.; Zorzi, N.; Zucca, S.

    2004-01-01

    Tests on silicon pixel detector in the mammographic energy range have shown good imaging performances so, in order to improve the efficiency in this energy range, we have designed thicker detectors of the p + /n type. The detectors have been fabricated by ITC-IRST (Trento, Italy) in high resistivity silicon substrates (300 and 525 μm thick). A TCAD simulation work has been carried out to optimize the electric field distribution and to enhance the breakdown voltage. Very low leakage current and high breakdown voltage characteristics have been measured on detectors in preliminary on-wafer tests. After that, detectors have been bump-bonded to a dedicated VLSI electronic chips, realizing an assembly. Choosing the best set-up condition and using a standard mammographic tube, we have acquired a large area image (8x8 cm 2 ) of the RMI 156 phantom, recommended for mammographic quality checks. In order to cover the whole surface, we have acquired different images translating the phantom over the assembly. We present some selected results for these assemblies both for the electrical characteristics and for the imaging performances

  12. Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process

    International Nuclear Information System (INIS)

    Tseng, Sheng-Hsiang; Lu, Michael S-C; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

    2012-01-01

    This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm 2 , and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G −1 with a standard deviation of 2.5 mV G −1 . The measured output noise floor is 354 µG Hz −1/2 , corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C −1 below 85 °C. (paper)

  13. DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

    Directory of Open Access Journals (Sweden)

    V. A. Solodukha

    2016-01-01

    Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

  14. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  15. Annealing of hydrogen-induced defects in RF-plasma-treated Si wafers: ex situ and in situ transmission electron microscopy studies

    International Nuclear Information System (INIS)

    Ghica, C; Nistor, L C; Vizireanu, S; Dinescu, G

    2011-01-01

    The smart-cut(TM) process is based on inducing and processing structural defects below the free surface of semiconductor wafers. The necessary defects are currently induced by implantation of light elements such as hydrogen or helium. An alternative softer way to induce shallow subsurface defects is by RF-plasma hydrogenation. To facilitate the smart-cut process, the wafers containing the induced defects need to be subjected to an appropriate thermal treatment. In our experiments, (0 0 1) Si wafers are submitted to 200 and 50 W hydrogen RF-plasma and are subsequently annealed. The samples are studied by transmission electron microscopy (TEM), before and after annealing. The plasma-introduced defects are {1 1 1} and {1 0 0} planar-like defects and nanocavities, all of them involving hydrogen. Many nanocavities are aligned into strings almost parallel to the wafer surface. The annealing is performed either by furnace thermal treatment at 550 deg. C, or by in situ heating in the electron microscope at 450, 650 and 800 deg. C during the TEM observations. The TEM microstructural studies indicate a partial healing of the planar defects and a size increase of the nanometric cavities by a coalescence process of the small neighbouring nanocavities. By annealing, the lined up nanometric voids forming chains in the as-hydrogenated sample coalesced into well-defined cracks, mostly parallel to the wafer surface.

  16. Fabrication of Through via Holes in Ultra-Thin Fused Silica Wafers for Microwave and Millimeter-Wave Applications

    Directory of Open Access Journals (Sweden)

    Xiao Li

    2018-03-01

    Full Text Available Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave circuits and 3D integration. In this work, etching through via holes in ultra-thin fused silica wafers using deep reactive-ion etching (DRIE and laser ablation was developed and analyzed. The experimental setup and process parameters for both methods are presented and compared. For DRIE, three types of mask materials including KMPR 1035 (Nippon Kayaku, Tokyo, Japan photoresist, amorphous silicon and chromium—with their corresponding optimized processing recipes—were tested, aiming at etching through a 100 μm fused silica wafer. From the experiments, we concluded that using chromium as the masking material is the best choice when using DRIE. However, we found that the laser ablation method with a laser pulse fluence of 2.89 J/cm2 and a pulse overlap of 91% has advantages over DRIE. The laser ablation method has a simpler process complexity, while offering a fair etching result. In particular, the sidewall profile angle is measured to be 75° to the bottom surface of the wafer, which is ideal for the subsequent metallization process. As a demonstration, a two-inch wafer with 624 via holes was processed using both technologies, and the laser ablation method showed better efficiency compared to DRIE.

  17. Propagation of resist heating mask error to wafer level

    Science.gov (United States)

    Babin, S. V.; Karklin, Linard

    2006-10-01

    As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

  18. Increasing reticle inspection efficiency and reducing wafer print-checks using automated defect classification and simulation

    Science.gov (United States)

    Ryu, Sung Jae; Lim, Sung Taek; Vacca, Anthony; Fiekowsky, Peter; Fiekowsky, Dan

    2013-09-01

    IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs. Fortunately, a software program has been developed which automates defect classification with simulated printability measurement greatly reducing requal cycle time and improving overall disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in both engineering and high-volume production environments with very successful results. In this paper, data is presented supporting significant reduction for costly wafer print checks, improved inspection area productivity, and minimized risk of misclassified yield limiting defects.

  19. Reliability assessment of ultra-thin HfO{sub 2} films deposited on silicon wafer

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Wei-En [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Chang, Chia-Wei [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Chang, Yong-Qing [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Yao, Chih-Kai [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Liao, Jiunn-Der, E-mail: jdliao@mail.ncku.edu.tw [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China)

    2012-09-01

    Highlights: Black-Right-Pointing-Pointer Nano-mechanical properties on annealed ultra-thin HfO{sub 2} film are studied. Black-Right-Pointing-Pointer By AFM analysis, hardness of the crystallized HfO{sub 2} film significantly increases. Black-Right-Pointing-Pointer By nano-indention, the film hardness increases with less contact stiffness. Black-Right-Pointing-Pointer Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO{sub 2}) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO{sub 2} films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO{sub 2} films deposited on silicon wafers (HfO{sub 2}/SiO{sub 2}/Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO{sub 2} (nominal thickness Almost-Equal-To 10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO{sub 2} phases for the atomic layer deposited HfO{sub 2}. The HfSi{sub x}O{sub y} complex formed at the interface between HfO{sub 2} and SiO{sub 2}/Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO{sub 2} film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically

  20. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  1. Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

    Directory of Open Access Journals (Sweden)

    Di Di

    2014-01-01

    Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

  2. Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

    Directory of Open Access Journals (Sweden)

    Azrul Azlan Hamzah

    2008-11-01

    Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

  3. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    International Nuclear Information System (INIS)

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  4. Chemical strategies for modifications of the solar cell process, from wafering to emitter diffusion; Chemische Ansaetze zur Neuordnung des Solarzellenprozesses ausgehend vom Wafering bis hin zur Emitterdiffusion

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, Kuno

    2009-11-06

    The paper describes the classic standard industrial solar cell based on monocrystalline silicon and describes new methods of fabrication. The first is an alternative wafering concept using laser microjet cutting instead of multiwire cutting. This method originally uses pure, deionized water; it was modified so that the liquid jet will not only be a liquid light conductor but also a transport medium for etching fluids supporting thermal abrasion of silicon by the laser jet. Two etching fluids were tested experimentally; it was found that water-free fluids based on perfluorinated solvents with very slight additions of gaseous chlorine are superior to all other options. In the second section, the wet chemical process steps between wafering and emitter diffusion (i.e. the first high-temperature step) was to be modified. Alternatives to 2-propanol were to be found in the experimental part. Purification after texturing was to be rationalized in order to reduce the process cost, either by using less chemical substances or by achieving shorter process times. 1-pentanol and p-toluolsulfonic acid were identified as two potential alternatives to 2-propanol as texture additives. Finally, it could be shown that wire-cut substrates processed with the new texturing agents have higher mechanical stabilities than substrates used with the classic texturing agent 2-propanol. [German] Im ersten Kapitel wird die klassische Standard-Industrie-Solarzelle auf der Basis monokristallinen Siliziums vorgestellt. Der bisherige Herstellungsprozess der Standard-Industrie-Solarzelle, der in wesentlichen Teilen darauf abzielt, diese Verluste zu minimieren, dient als Referenz fuer die Entwicklung neuer Fertigungsverfahren, wie sie in dieser Arbeit vorgestellt werden. Den ersten thematischen Schwerpunkt bildet die Entwicklung eines alternativen Wafering-Konzeptes zum Multi-Drahtsaegen. Die Basis des neuen, hier vorgestellten Wafering-Prozesses bildet das Laser-Micro-Jet-Verfahren. Dieses System

  5. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  6. Epitaxial growth of 100-μm thick M-type hexaferrite crystals on wide bandgap semiconductor GaN/Al{sub 2}O{sub 3} substrates

    Energy Technology Data Exchange (ETDEWEB)

    Hu, Bolin; Su, Zhijuan; Bennett, Steve; Chen, Yajie, E-mail: y.chen@neu.edu; Harris, Vincent G. [Center for Microwave Magnetic Materials and Integrated Circuits and Department of Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts 02115 (United States)

    2014-05-07

    Thick barium hexaferrite BaFe{sub 12}O{sub 19} (BaM) films having thicknesses of ∼100 μm were epitaxially grown on GaN/Al{sub 2}O{sub 3} substrates from a molten-salt solution by vaporizing the solvent. X-ray diffraction measurement verified the growth of BaM (001) textured growth of thick films. Saturation magnetization, 4πM{sub s}, was measured for as-grown films to be 4.6 ± 0.2 kG and ferromagnetic resonance measurements revealed a microwave linewidth of ∼100 Oe at X-band. Scanning electron microscopy indicated clear hexagonal crystals distributed on the semiconductor substrate. These results demonstrate feasibility of growing M-type hexaferrite crystal films on wide bandgap semiconductor substrates by using a simple powder melting method. It also presents a potential pathway for the integration of ferrite microwave passive devices with active semiconductor circuit elements creating system-on-a-wafer architectures.

  7. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    Science.gov (United States)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  8. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    International Nuclear Information System (INIS)

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  9. Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

    Directory of Open Access Journals (Sweden)

    Ali Attaran

    2014-01-01

    Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

  10. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate

    DEFF Research Database (Denmark)

    Buron, Jonas Due; Mackenzie, David M. A.; Petersen, Dirch Hjorth

    2015-01-01

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (mu(drift)), carrier density (N-S), DC sheet conductance (sigma(dc)), and carrier scattering time (tau(SC)) in CVD graphene, using spatially resolved terahertz time-domain conductance...

  11. Polymer-based 2D/3D wafer level heterogeneous integration for SSL module

    NARCIS (Netherlands)

    Yuan, C.; Wei, J.; Ye, H.; Koh, S.; Harianto, S.; Nieuwenhof, M.A. van den; Zhang, G.Q.

    2012-01-01

    This paper demonstrates a heterogeneous integration of solid state lighting (SSL) module, including light source (LED) and driver/control components. Such integration has been realized by the polymer-based reconfigured wafer level package technologies and such structure has been prototyped and

  12. Underling modification in ion beam induced Si wafers

    International Nuclear Information System (INIS)

    Hazra, S.; Chini, T.K.; Sanyal, M.K.; Grenzer, J.; Pietsch, U.

    2005-01-01

    Subsurface (amorphous-crystalline interface) structure of keV ion beam modified Si(001) wafers was studied for the first time using non-destructive technique and compared with that of the top one. Ion-beam modifications of the Si samples were done using state-of-art high-current ion implanter facility at Saha Institute of Nuclear Physics by changing energy, dose and angle of incidence of the Ar + ion beam. To bring out the underlying modification depth-resolved x-ray grazing incidence diffraction has been carried out using synchrotron radiation facility, while the structure of the top surface was studied through atomic force microscopy

  13. Coaxial twin-shaft magnetic fluid seals applied in vacuum wafer-handling robot

    Science.gov (United States)

    Cong, Ming; Wen, Haiying; Du, Yu; Dai, Penglei

    2012-07-01

    Compared with traditional mechanical seals, magnetic fluid seals have unique characters of high airtightness, minimal friction torque requirements, pollution-free and long life-span, widely used in vacuum robots. With the rapid development of Integrate Circuit (IC), there is a stringent requirement for sealing wafer-handling robots when working in a vacuum environment. The parameters of magnetic fluid seals structure is very important in the vacuum robot design. This paper gives a magnetic fluid seal device for the robot. Firstly, the seal differential pressure formulas of magnetic fluid seal are deduced according to the theory of ferrohydrodynamics, which indicate that the magnetic field gradient in the sealing gap determines the seal capacity of magnetic fluid seal. Secondly, the magnetic analysis model of twin-shaft magnetic fluid seals structure is established. By analyzing the magnetic field distribution of dual magnetic fluid seal, the optimal value ranges of important parameters, including parameters of the permanent magnetic ring, the magnetic pole tooth, the outer shaft, the outer shaft sleeve and the axial relative position of two permanent magnetic rings, which affect the seal differential pressure, are obtained. A wafer-handling robot equipped with coaxial twin-shaft magnetic fluid rotary seals and bellows seal is devised and an optimized twin-shaft magnetic fluid seals experimental platform is built. Test result shows that when the speed of the two rotational shafts ranges from 0-500 r/min, the maximum burst pressure is about 0.24 MPa. Magnetic fluid rotary seals can provide satisfactory performance in the application of wafer-handling robot. The proposed coaxial twin-shaft magnetic fluid rotary seal provides the instruction to design high-speed vacuum robot.

  14. Electron multibeam technology for mask and wafer writing at 0.1 nm address grid

    Science.gov (United States)

    Platzgummer, Elmar; Klein, Christof; Loeschner, Hans

    2013-07-01

    IMS Nanofabrication realized a 50 keV electron multibeam proof-of-concept (POC) tool confirming writing principles with 0.1 nm address grid and lithography performance capability. The POC system achieves the predicted 5 nm 1 sigma blur across the 82 μm×82 μm array of 512×512 (262,144) programmable 20 nm beams. 24-nm half pitch (HP) has been demonstrated and complex patterns have been written in scanning stripe exposure mode. The first production worthy system for the 11-nm HP mask node is scheduled for 2014 (Alpha), 2015 (Beta), and first-generation high-volume manufacturing multibeam mask writer (MBMW) tools in 2016. In these MBMW systems the max beam current through the column is 1 μA. The new architecture has also the potential for 1× mask (master template) writing. Substantial further developments are needed for maskless e-beam direct write (EBDW) applications as a beam current of >2 mA is needed to achieve 100 wafer per hour industrial targets for 300 mm wafer size. Necessary productivity enhancements of more than three orders of magnitude are only possible by shrinking the multibeam optics such that 50 to 100 subcolumns can be placed on the area of a 300 mm wafer and by clustering 10 to 20 multicolumn tools. An overview of current EBDW efforts is provided.

  15. Nondestructive evaluation of differently doped InP wafers by time-resolved four-wave mixing technique

    International Nuclear Information System (INIS)

    Kadys, A.; Sudzius, M.; Jarasiunas, K.; Mao Luhong; Sun Niefeng

    2006-01-01

    Photoelectric properties of semi-insulating, differently doped, and undoped indium phosphide wafers, grown by the liquid encapsulation Czochralski method, have been investigated by time-resolved picosecond four-wave mixing technique. Deep defect related carrier generation, recombination, and transport properties were investigated experimentally by measuring four-wave mixing kinetics and exposure characteristics. The presence of deep donor states in undoped InP was confirmed by a pronounced effect of a space charge electric field to carrier transport. On the other hand, the recharging dynamics of electrically active residual impurities was observed in undoped and Fe-doped InP through the process of efficient trapping of excess carriers. The bipolar diffusion coefficients and mobilities were determined for the all wafers

  16. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  17. A reliable control system for measurement on film thickness in copper chemical mechanical planarization system

    Energy Technology Data Exchange (ETDEWEB)

    Li, Hongkai; Qu, Zilian; Zhao, Qian; Tian, Fangxin; Zhao, Dewen; Meng, Yonggang; Lu, Xinchun [State Key Laboratory of Tribology, Tsinghua University, Beijing 100084 (China)

    2013-12-15

    In recent years, a variety of film thickness measurement techniques for copper chemical mechanical planarization (CMP) are subsequently proposed. In this paper, the eddy-current technique is used. In the control system of the CMP tool developed in the State Key Laboratory of Tribology, there are in situ module and off-line module for measurement subsystem. The in situ module can get the thickness of copper film on wafer surface in real time, and accurately judge when the CMP process should stop. This is called end-point detection. The off-line module is used for multi-points measurement after CMP process, in order to know the thickness of remained copper film. The whole control system is structured with two levels, and the physical connection between the upper and the lower is achieved by the industrial Ethernet. The process flow includes calibration and measurement, and there are different algorithms for two modules. In the process of software development, C++ is chosen as the programming language, in combination with Qt OpenSource to design two modules’ GUI and OPC technology to implement the communication between the two levels. In addition, the drawing function is developed relying on Matlab, enriching the software functions of the off-line module. The result shows that the control system is running stably after repeated tests and practical operations for a long time.

  18. Porosity and thickness effect of porous silicon layer on photoluminescence spectra

    Science.gov (United States)

    Husairi, F. S.; Eswar, K. A.; Guliling, Muliyadi; Khusaimi, Z.; Rusop, M.; Abdullah, S.

    2018-05-01

    The porous silicon nanostructures was prepared by electrochemical etching of p-type silicon wafer. Porous silicon prepared by using different current density and fix etching time with assistance of halogen lamp. The physical structure of porous silicon measured by the parameters used which know as experimental factor. In this work, we select one of those factors to correlate which optical properties of porous silicon. We investigated the surface morphology by using Surface Profiler (SP) and photoluminescence using Photoluminescence (PL) spectrometer. Different physical characteristics of porous silicon produced when current density varied. Surface profiler used to measure the thickness of porous and the porosity calculated using mass different of silicon. Photoluminescence characteristics of porous silicon depend on their morphology because the size and distribution of pore its self will effect to their exciton energy level. At J=30 mA/cm2 the shorter wavelength produced and it followed the trend of porosity with current density applied.

  19. Investigating electro-mechanical signals from collocated piezoelectric wafers for the reference-free damage diagnosis of a plate

    International Nuclear Information System (INIS)

    Kim, Eun Jin; Park, Hyun Woo; Kim, Min Koo; Sohn, Hoon

    2011-01-01

    The electro-mechanical (EM) signals from piezoelectric (PZT) wafers are investigated for reference-free damage diagnosis so that a notch in a plate can be detected without requiring direct comparison with a baseline EM signal. Two identical PZT wafers collocated on both surfaces of a plate are utilized for extracting the mode-converted Lamb wave signals created by a notch. As harmonic input voltage signals are exerted on the collocated PZT wafers, the corresponding mode-converted Lamb wave signals become steady-state in the presence of damage. Applying fast Fourier transform to these mode-converted Lamb wave signals followed by a proper normalization, the EM signals associated with the mode conversion can be obtained. The theoretical finding of this paper is validated through spectral element simulations of a cantilever beam with a notch. The effects of the size and the location of the notch on the mode-converted EM signals are investigated as well. Finally, the applicability of the decomposed EM signals to reference-free damage diagnosis is discussed

  20. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Xianshu eLuo

    2015-04-01

    Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

  1. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    International Nuclear Information System (INIS)

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  2. Characterization of Si pixel detectors of different thickness

    Energy Technology Data Exchange (ETDEWEB)

    Bisogni, M.G.; Boscardin, M.; Dalla Betta, G.F.; Delogu, P.; Fantacci, M.E.; Gregori, P.; Linsalata, S.; Novelli, M. E-mail: marzia.novelli@pi.infn.it; Piemonte, C.; Quattrocchi, M.; Rosso, V.; Stefanini, A.; Zorzi, N.; Zucca, S

    2004-02-01

    Tests on silicon pixel detector in the mammographic energy range have shown good imaging performances so, in order to improve the efficiency in this energy range, we have designed thicker detectors of the p{sup +}/n type. The detectors have been fabricated by ITC-IRST (Trento, Italy) in high resistivity silicon substrates (300 and 525 {mu}m thick). A TCAD simulation work has been carried out to optimize the electric field distribution and to enhance the breakdown voltage. Very low leakage current and high breakdown voltage characteristics have been measured on detectors in preliminary on-wafer tests. After that, detectors have been bump-bonded to a dedicated VLSI electronic chips, realizing an assembly. Choosing the best set-up condition and using a standard mammographic tube, we have acquired a large area image (8x8 cm{sup 2}) of the RMI 156 phantom, recommended for mammographic quality checks. In order to cover the whole surface, we have acquired different images translating the phantom over the assembly. We present some selected results for these assemblies both for the electrical characteristics and for the imaging performances.

  3. Flip chip assembly of thinned chips for hybrid pixel detector applications

    CERN Document Server

    Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

  4. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Science.gov (United States)

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  5. Benefits of on-wafer calibration standards fabricated in membrane technology

    Science.gov (United States)

    Rohland, M.; Arz, U.; Büttgenbach, S.

    2011-07-01

    In this work we compare on-wafer calibration standards fabricated in membrane technology with standards built in conventional thin-film technology. We perform this comparison by investigating the propagation of uncertainties in the geometry and material properties to the broadband electrical properties of the standards. For coplanar waveguides used as line standards the analysis based on Monte Carlo simulations demonstrates an up to tenfold reduction in uncertainty depending on the electromagnetic waveguide property we look at.

  6. CCD Development Progress at Lawrence Berkeley National Laboratory

    OpenAIRE

    Kolbe, W.F.; Holland, S.E.; Bebek, C.J.

    2006-01-01

    P-channel CCD imagers, 200-300um thick, fully depleted, and back-illuminat ed are being developed for scientific applications including ground- and space-based astronomy and x-ray detection. These thick devices have extended IR response, good point-spread function (PSF) and excellent radiation tolerance. Initially, these CCDs were made in-house at LBNL using 100 mm diameter wafers. Fabrication on high-resistivity 150 mm wafers is now proceeding according to a model in which the wafers are fir...

  7. MIMO feed-forward design in wafer scanners using a gradient approximation-based algorithm

    NARCIS (Netherlands)

    Heertjes, M.F.; Hennekens, D.W.T.; Steinbuch, M.

    2010-01-01

    An experimental demonstration is given of a data-based multi-input multi-output (MIMO) feed-forward control design applied to the motion systems of a wafer scanner. Atop a nominal single-input single-output (SISO) feed-forward controller, a MIMO controller is designed having a finite impulse

  8. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  9. Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.

    Science.gov (United States)

    Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

    2015-02-01

    We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (supercapacitors are formed on an ultrathin (~20 μm) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications.

  10. Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

    Science.gov (United States)

    Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

    Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

  11. Polifeprosan 20, 3.85% carmustine slow release wafer in malignant glioma: patient selection and perspectives on a low-burden therapy

    Directory of Open Access Journals (Sweden)

    Kleinberg L

    2016-11-01

    Full Text Available Lawrence Kleinberg Department of Radiation Oncology and Molecular Radiation Sciences, Johns Hopkins University, Baltimore, MD, USA Abstract: Polifeprosan 20 with carmustine (GLIADEL® polymer implant wafer is a biodegradable compound containing 3.85% carmustine (BCNU, bischloroethylnitrosourea implanted in the brain at the time of planned tumor surgery, which then slowly degrades to release the BCNU chemotherapy directly into the brain thereby bypassing the blood–brain barrier. Carmustine implant wafers were demonstrated to improve survival in randomized placebo-controlled trials in patients undergoing a near total resection of newly diagnosed or recurrent malignant glioma. Based on these trials and other supporting data, carmustine wafer therapy was approved for use for newly diagnosed and recurrent malignant glioma in the United States and the European Union. Adverse events are uncommon, and as this therapy is placed at the time of surgery, it does not add to patient treatment burden. Nevertheless, this therapy appears to be underutilized. This article reviews the evidence for a favorable therapeutic ratio for the patient and the potential barriers. Consideration of these issues is important for optimal use of this therapeutic approach and may be important as this technology and other local therapies are further developed in the future. Keywords: carmustine, wafer, gliadel, glioblastoma

  12. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments

    NARCIS (Netherlands)

    Bomer, Johan G.; Prokofyev, A.V.; van den Berg, Albert; le Gac, Severine

    2014-01-01

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the

  13. Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

    Science.gov (United States)

    Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

    2016-10-01

    Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

  14. Aqueous-based thick photoresist removal for bumping applications

    Science.gov (United States)

    Moore, John C.; Brewer, Alex J.; Law, Alman; Pettit, Jared M.

    2015-03-01

    Cleaning processes account for over 25% of processing in microelectronic manufacturing [1], suggesting electronics to be one of the most chemical intensive markets in commerce. Industry roadmaps exist to reduce chemical exposure, usage, and waste [2]. Companies are encouraged to create a safer working environment, or green factory, and ultimately become certified similar to LEED in the building industry [3]. A significant step in this direction is the integration of aqueous-based photoresist (PR) strippers which eliminate regulatory risks and cut costs by over 50%. One of the largest organic solvent usages is based upon thick PR removal during bumping processes [4-6]. Using market projections and the benefits of recycling, it is estimated that over 1,000 metric tons (mt) of residuals originating from bumping processes are incinerated or sent to a landfill. Aqueous-based stripping would eliminate this disposal while also reducing the daily risks to workers and added permitting costs. Positive-tone PR dissolves in aqueous strippers while negative-tone systems are lifted-off from the substrate, bumps, pillars, and redistribution layers (RDL). While the wafers are further processed and rinsed, the lifted-off PR is pumped from the tank, collected onto a filter, and periodically back-flushed to the trash. The PR solids become a non-hazardous plastic waste while the liquids are mixed with the developer stream, neutralized, filtered, and in most cases, disposed to the sewer. Regardless of PR thickness, removal processes may be tuned to perform in <15min, performing at rates nearly 10X faster than solvents with higher bath lives. A balanced formula is safe for metals, dielectrics, and may be customized to any fab.

  15. Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

    Science.gov (United States)

    Weatherwax Scott, Caroline; Tsareff, Christopher R.

    1990-06-01

    One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles

  16. Worker exposure to methanol vapors during cleaning of semiconductor wafers in a manufacturing setting.

    Science.gov (United States)

    Gaffney, Shannon; Moody, Emily; McKinley, Meg; Knutsen, Jeffrey; Madl, Amy; Paustenbach, Dennis

    2008-05-01

    An exposure simulation was conducted to characterize methanol exposure of workers who cleaned wafers in quality control departments within the semiconductor industry. Short-term (15 min) and long-term (2-4 hr) personal and area samples (at distances of 1 m and 3-6 m from the source) were collected during the 2-day simulation. On the first day, 45 mL of methanol were used per hour by a single worker washing wafers in a 102 m(3) room with a ventilation rate of about 10 air changes per hour (ACH). Virtually all methanol volatilized. To assess exposures under conditions associated with higher productivity, on the second day, two workers cleaned wafers simultaneously, together using methanol at over twice the rate of the first day (95 mL/hr). On this day, the ventilation rate was halved (5 ACH). Personal concentrations on the first day averaged 60 ppm (SD = 46 ppm) and ranged from 10-140 ppm. On the second day, personal concentrations for both workers averaged 118 ppm (SD = 50 ppm; range: 64-270 ppm). Area concentrations measured on the first day at 1 m from the source and throughout the balance of the room averaged 29 ppm (SD = 19 ppm; range: 4-83 ppm) and 18 ppm (SD = 12 ppm; range: 3-42 ppm), respectively. As expected, area concentrations measured on the second day were higher than the first and averaged 73 ppm (SD = 25 ppm; range: 27-140 ppm) at 1 meter and 48 ppm (SD = 13 ppm; range: 21-67 ppm) throughout the balance of the room. The results of this simulation suggest that the use of methanol to clean semiconductor wafers without the use of local exhaust ventilation and with relatively low room ventilation rates is unlikely to result in worker exposures exceeding the current ACGIH(R) threshold limit value of 200 ppm. This study also confirmed prior studies suggesting that when a relatively volatile chemical is located within arm's length (near field), breathing zone concentrations will be about two- to threefold greater than the room concentration when the air

  17. Clean solutions to the incoming wafer quality impact on lithography process yield limits in a dynamic copper/low-k research and development environment

    Science.gov (United States)

    Lysaght, Patrick S.; Ybarra, Israel; Sax, Harry; Gupta, Gaurav; West, Michael; Doros, Theodore G.; Beach, James V.; Mello, Jim

    2000-06-01

    The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N2) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan IIITM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface

  18. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  19. Joint Research on Scatterometry and AFM Wafer Metrology

    Science.gov (United States)

    Bodermann, Bernd; Buhr, Egbert; Danzebrink, Hans-Ulrich; Bär, Markus; Scholze, Frank; Krumrey, Michael; Wurm, Matthias; Klapetek, Petr; Hansen, Poul-Erik; Korpelainen, Virpi; van Veghel, Marijn; Yacoot, Andrew; Siitonen, Samuli; El Gawhary, Omar; Burger, Sven; Saastamoinen, Toni

    2011-11-01

    Supported by the European Commission and EURAMET, a consortium of 10 participants from national metrology institutes, universities and companies has started a joint research project with the aim of overcoming current challenges in optical scatterometry for traceable linewidth metrology. Both experimental and modelling methods will be enhanced and different methods will be compared with each other and with specially adapted atomic force microscopy (AFM) and scanning electron microscopy (SEM) measurement systems in measurement comparisons. Additionally novel methods for sophisticated data analysis will be developed and investigated to reach significant reductions of the measurement uncertainties in critical dimension (CD) metrology. One final goal will be the realisation of a wafer based reference standard material for calibration of scatterometers.

  20. Sidewall patterning - A new wafer-scale method for accurate patterning of vertical silicon structures

    NARCIS (Netherlands)

    Westerik, P. J.; Vijselaar, W. J.C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G.E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that

  1. Single wafer rapid thermal multiprocessing

    International Nuclear Information System (INIS)

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  2. A Reuse Evaluation for Solar-Cell Silicon Wafers via Shift Revolution and Tool Rotation Using Magnetic Assistance in Ultrasonic Electrochemical Micromachining

    Directory of Open Access Journals (Sweden)

    P. S. Pa

    2013-01-01

    Full Text Available A new reuse fabrication using a tool module with rotation and revolution through a process of magnetic assistance in ultrasonic electrochemical micromachining (UEMM for removal of the surface layers from silicon wafers of solar cells is demonstrated. The target of the proposed reuse fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach to removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. The high revolution speed of the shift with the high rotation speed of the designed tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. High frequency and high power of ultrasonic with large electrolyte flow rate and high magnetic strengths with a small distance between the two magnets provide a large discharge effect and good removal; only a short period of time is required to remove the epoxy film and Si3N4 layer easily and cleanly.

  3. Increasing reticle inspection efficiency and reducing wafer printchecks at 14nm using automated defect classification and simulation

    Science.gov (United States)

    Paracha, Shazad; Goodman, Eliot; Eynon, Benjamin G.; Noyes, Ben F.; Ha, Steven; Kim, Jong-Min; Lee, Dong-Seok; Lee, Dong-Heok; Cho, Sang-Soo; Ham, Young M.; Vacca, Anthony D.; Fiekowsky, Peter J.; Fiekowsky, Daniel I.

    2014-10-01

    IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect's printability under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the results of both AIMS optical simulation and to actual wafer prints.

  4. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    NARCIS (Netherlands)

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  5. Preparation of immobilized glucose oxidase wafer enzyme on calcium-bentonite modified by surfactant

    Science.gov (United States)

    Widi, R. K.; Trisulo, D. C.; Budhyantoro, A.; Chrisnasari, R.

    2017-07-01

    Wafer glucose oxidase (GOx) enzymes was produced by addition of PAH (Poly-Allyamine Hydrochloride) polymer into immobilized GOx enzyme on modified-Tetramethylammonium Hydroxide (TMAH) 5%-calsium-bentonite. The use of surfactant molecul (TMAH) is to modify the surface properties and pore size distribution of the Ca-bentonite. These properties are very important to ensure GOx molecules can be bound on the Ca-bentonit surface to be immobilized. The addition of the polymer (PAH) is expected to lead the substrates to be adsorbed onto the enzyme. In this study, wafer enzymes were made in various concentration ratio (Ca-bentonite : PAH) which are 1:0, 1:1, 1:2 and 1:3. The effect of PAH (Poly-Allyamine Hydrochloride) polymer added with various ratios of concentrations can be shown from the capacitance value on LCR meter and enzyme activity using DNS method. The addition of the polymer (PAH) showed effect on the activity of GOx, it can be shown from the decreasing of capacitance value by increasing of PAH concentration.

  6. Big data driven cycle time parallel prediction for production planning in wafer manufacturing

    Science.gov (United States)

    Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

    2018-07-01

    Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

  7. Wafer-Level Patterned and Aligned Polymer Nanowire/Micro- and Nanotube Arrays on any Substrate

    KAUST Repository

    Morber, Jenny Ruth

    2009-05-25

    A study was conducted to fabricate wafer-level patterned and aligned polymer nanowire (PNW), micro- and nanotube arrays (PNT), which were created by exposing the polymer material to plasma etching. The approach for producing wafer-level aligned PNWs involved a one-step inductively coupled plasma (ICP) reactive ion etching process. The polymer nanowire array was fabricated in an ICP reactive ion milling chamber with a pressure of 10mTorr. Argon (Ar), O 2, and CF4 gases were released into the chamber as etchants at flow rates of 15 sccm, 10 sccm, and 40 sccm. Inert gasses, such as Ar-form positive ions were incorporated to serve as a physical component to assist in the material degradation process. One power source (400 W) was used to generate dense plasma from the input gases, while another power source applied a voltage of approximately 600V to accelerate the plasma toward the substrate.

  8. Mathematical model and characteristic analysis of hybrid photovoltaic/piezoelectric actuation mechanism

    Science.gov (United States)

    Jiang, Jing; Li, Xiaonan; Ding, Jincheng; Yue, Honghao; Deng, Zongquan

    2016-12-01

    Photovoltaic materials can turn light energy into electric energy directly, and thus have the advantages of high electrical output voltages and the ability to realize remote or non-contact control. When high-energy ultraviolet light illuminates polarized PbLaZrTi (PLZT) materials, high photovoltages will be generated along the spontaneous polarization direction due to the photovoltaic effect. In this paper, a novel hybrid photovoltaic/piezoelectric actuation mechanism is proposed. PLZT ceramics are used as a photovoltaic generator to drive a piezoelectric actuator. A mathematical model is established to define the time history of the actuation voltage between two electrodes of the piezoelectric actuator, which is experimentally validated by the test results of a piezoelectric actuator with different geometrical parameters under irradiation at different light intensities. Some important characteristics of this novel actuation mechanism are analyzed and it can be concluded that (1) it is experimentally validated that there is no hysteresis between voltage and deformation which exists in a PLZT actuator; (2) the saturated voltage and response speed can be improved by using a multi-patch PLZT generator to drive the piezoelectric actuator; and (3) the initial voltage of the piezoelectric actuator can be acquired by controlling the logical switch between the PLZT and the piezoelectric actuator while the initial voltages increase with the rise of light intensity.

  9. Narrow thermal hysteresis of NiTi shape memory alloy thin films with submicrometer thickness

    Energy Technology Data Exchange (ETDEWEB)

    Hou, Huilong; Hamilton, Reginald F., E-mail: rfhamilton@psu.edu; Horn, Mark W. [Department of Engineering Science and Mechanics, The Pennsylvania State University, University Park, Pennsylvania 16802 (United States)

    2016-09-15

    NiTi shape memory alloy (SMA) thin films were fabricated using biased target ion beam deposition (BTIBD), which is a new technique for fabricating submicrometer-thick SMA thin films, and the capacity to exhibit shape memory behavior was investigated. The thermally induced shape memory effect (SME) was studied using the wafer curvature method to report the stress-temperature response. The films exhibited the SME in a temperature range above room temperature and a narrow thermal hysteresis with respect to previous reports. To confirm the underlying phase transformation, in situ x-ray diffraction was carried out in the corresponding phase transformation temperature range. The B2 to R-phase martensitic transformation occurs, and the R-phase transformation is stable with respect to the expected conversion to the B19′ martensite phase. The narrow hysteresis and stable R-phase are rationalized in terms of the unique properties of the BTIBD technique.

  10. Ultrathin, wafer-scale hexagonal boron nitride on dielectric surfaces by diffusion and segregation mechanism

    Science.gov (United States)

    Sonde, Sushant; Dolocan, Andrei; Lu, Ning; Corbet, Chris; Kim, Moon J.; Tutuc, Emanuel; Banerjee, Sanjay K.; Colombo, Luigi

    2017-06-01

    Chemical vapor deposition (CVD) of two-dimensional (2D) hexagonal boron nitride (h-BN) is at the center of numerous studies for its applications in novel electronic devices. However, a clear understanding of the growth mechanism is lacking for its wider industrial adoption on technologically relevant substrates such as SiO2. Here, we demonstrate a controllable growth method of thin, wafer scale h-BN films on arbitrary substrates. We also clarify the growth mechanism to be diffusion and surface segregation (D-SS) of boron (B) and nitrogen (N) in Ni and Co thin films on SiO2/Si substrates after exposure to diborane and ammonia precursors at high temperature. The segregation was found to be independent of the cooling rates employed in this report, and to our knowledge has not been found nor reported for 2D h-BN growth so far, and thus provides an important direction for controlled growth of h-BN. This unique segregation behavior is a result of a combined effect of high diffusivity, small film thickness and the inability to achieve extremely high cooling rates in CVD systems. The resulting D-SS h-BN films exhibit excellent electrical insulating behavior with an optical bandgap of about 5.8 eV. Moreover, graphene-on-h-BN field effect transistors using the as-grown D-SS h-BN films show a mobility of about 6000 cm2 V-1 s-1 at room temperature.

  11. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    Energy Technology Data Exchange (ETDEWEB)

    Qiusheng, Y., E-mail: qsyan@gdut.edu.cn; Senkai, C., E-mail: senkite@sina.com; Jisheng, P., E-mail: panjisheng@gdut.edu.cn [School of Electromechanical Engineering, Guangdong University of Technology, Guangzhou, 510006 (China)

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  12. Examination of optimum test conditions for a 3-point bending and cutting test to evaluate sound emission of wafer during deformation

    Directory of Open Access Journals (Sweden)

    Erdem Carsanba

    2018-04-01

    Full Text Available The purpose of this study was to investigate optimum test conditions of acoustical-mechanical measurement of wafer analysed by Acoustic Envelope Detector attached to the Texture Analyser. Force-displacement and acoustic signals were simultaneously recorded applying two different methods (3-point bending and cutting test. In order to study acoustical-mechanical behaviour of wafers, the parameters “maximum sound pressure”, “total count peaks” and “mean sound value” were used and optimal test conditions of microphone position and test speed were examined. With a microphone position of 45° angle and 1 cm distance and at a low test speed of 0.5 mm/s wafers of different quality could be distinguished best. The angle of microphone did not have significant effect on acoustic results and the number of peaks of the force and acoustic signal decreased with increasing distance and test speed.

  13. Electrothermal evaluation of thick GaN epitaxial layers and AlGaN/GaN high-electron-mobility transistors on large-area engineered substrates

    Science.gov (United States)

    Anderson, Travis J.; Koehler, Andrew D.; Tadjer, Marko J.; Hite, Jennifer K.; Nath, Anindya; Mahadik, Nadeemullah A.; Aktas, Ozgur; Odnoblyudov, Vladimir; Basceri, Cem; Hobart, Karl D.; Kub, Francis J.

    2017-12-01

    AlGaN/GaN high-electron-mobility transistor (HEMT) device layers were grown by metal organic chemical vapor deposition (MOCVD) on commercial engineered QST™ substrates to demonstrate a path to scalable, cost-effective foundry processing while supporting the thick epitaxial layers required for power HEMT structures. HEMT structures on 150 mm Si substrates were also evaluated. The HEMTs on engineered substrates exhibited material quality, DC performance, and forward blocking performance superior to those of the HEMT on Si. GaN device layers up to 15 µm were demonstrated with a wafer bow of 1 µm, representing the thickest films grown on 150-mm-diameter substrates with low bow to date.

  14. Sliding-mode control combined with improved adaptive feedforward for wafer scanner

    Science.gov (United States)

    Li, Xiaojie; Wang, Yiguang

    2018-03-01

    In this paper, a sliding-mode control method combined with improved adaptive feedforward is proposed for wafer scanner to improve the tracking performance of the closed-loop system. Particularly, In addition to the inverse model, the nonlinear force ripple effect which may degrade the tracking accuracy of permanent magnet linear motor (PMLM) is considered in the proposed method. The dominant position periodicity of force ripple is determined by using the Fast Fourier Transform (FFT) analysis for experimental data and the improved feedforward control is achieved by the online recursive least-squares (RLS) estimation of the inverse model and the force ripple. The improved adaptive feedforward is given in a general form of nth-order model with force ripple effect. This proposed method is motivated by the motion controller design of the long-stroke PMLM and short-stroke voice coil motor for wafer scanner. The stability of the closed-loop control system and the convergence of the motion tracking are guaranteed by the proposed sliding-mode feedback and adaptive feedforward methods theoretically. Comparative experiments on a precision linear motion platform can verify the correctness and effectiveness of the proposed method. The experimental results show that comparing to traditional method the proposed one has better performance of rapidity and robustness, especially for high speed motion trajectory. And, the improvements on both tracking accuracy and settling time can be achieved.

  15. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    CERN Document Server

    Bronuzzi, J.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

  16. Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

    International Nuclear Information System (INIS)

    Takahara, Hikari; Mori, Yoshihiro; Shibata, Harumi; Shimazaki, Ayako; Shabani, Mohammad B.; Yamagami, Motoyuki; Yabumoto, Norikuni; Nishihagi, Kazuo; Gohshi, Yohichi

    2013-01-01

    Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10 9 and 5 × 10 10 atoms/cm 2 Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO 2 , silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10 10 atoms/cm 2 . • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies

  17. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Science.gov (United States)

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  18. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    Science.gov (United States)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  19. Ion implanters contamination on wafer surface analyzed by ToF-SIMS and SPV analytical techniques

    International Nuclear Information System (INIS)

    Ricciari, R.; Bertini, M.; Ferlito, E.P.; Pizzo, G.; Anastasi, G.; Mello, D.; Franco, G.

    2007-01-01

    In ULSI processes, metallic contamination controls are very important issues. For the ion implantation process it is known that several sources of contaminations still need to be controlled: metals from sputtering of the apertures or wafer holders, Na + contaminations from filament impurities and messy maintenance procedure. ToF-SIMS is one of the most promising candidates to perform in-line surface analysis due to its high sensitivity. It is very common to use surface photo-voltage (SPV) techniques to control ion implanter equipments but this kind of analysis is an indirect measure for metallic contamination. The aim of this work is to study the possibility to use ToF-SIMS instead of SPV for in line equipment contamination monitoring. For this reason a comparison between SPV and ToF-SIMS data occurred. Good correlation between the data is shown; moreover ToF-SIMS spectra give detailed information about the other contaminations present on the wafer surface

  20. Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

    Science.gov (United States)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-30

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  1. Full reflector thickness and isolation thickness on neutron transport

    International Nuclear Information System (INIS)

    Sakai, Tomohiro; Naito, Yoshitaka; Komuro, Yuichi.

    1988-08-01

    A method to determine ''full reflector thickness'' and ''isolation thickness'', which is utilized for criticality safety evaluation on nuclear fuel facilities, was proposed in this paper. Firstly, a calculation was tryed to obtain the two kinds of thicknesses from the result of criticality calculations for a specific case. Then, two simple equations which calculates the two kinds of thicknesses were made from the relation between reflector (or isolator) thickness and k eff , and one-group diffusion theory. Finally, we proposed a new method to determine the thicknesses. From the method we proposed, ''full reflector thickness'' and ''isolation thickness'' can be obtain using the equations and migration length of the reflector (or isolator) and infinite and effective multiplication factor of the fuel. (author)

  2. Synchronizing decentralized control loops for overall performance enhancement : a Youla framework applied to a wafer scanner

    NARCIS (Netherlands)

    Evers, E.; van de Wal, M.M.J.; Oomen, T.A.E.

    2017-01-01

    Manufacturing equipment often consists of multiple subsystems. For instance, in lithographic IC manufacturing, both a reticle stage and a wafer stage move synchronously. Traditionally, these subsystems are divided into manageable subproblems, at the expense of a suboptimal overall solution. The aim

  3. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

    Science.gov (United States)

    Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

    2014-12-07

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated.

  4. Nanomechanical properties of thick porous silicon layers grown on p- and p+-type bulk crystalline Si

    International Nuclear Information System (INIS)

    Charitidis, C.A.; Skarmoutsou, A.; Nassiopoulou, A.G.; Dragoneas, A.

    2011-01-01

    Highlights: → The nanomechanical properties of bulk crystalline Si. → The nanomechanical properties of porous Si. → The elastic-plastic deformation of porous Si compared to bulk crystalline quantified by nanoindentation data analysis. - Abstract: The nanomechanical properties and the nanoscale deformation of thick porous Si (PSi) layers of two different morphologies, grown electrochemically on p-type and p+-type Si wafers were investigated by the depth-sensing nanoindentation technique over a small range of loads using a Berkovich indenter and were compared with those of bulk crystalline Si. The microstructure of the thick PSi layers was characterized by field emission scanning electron microscopy. PSi layers on p+-type Si show an anisotropic mesoporous structure with straight vertical pores of diameter in the range of 30-50 nm, while those on p-type Si show a sponge like mesoporous structure. The effect of the microstructure on the mechanical properties of the layers is discussed. It is shown that the hardness and Young's modulus of the PSi layers exhibit a strong dependence on their microstructure. In particular, PSi layers with the anisotropic straight vertical pores show higher hardness and elastic modulus values than sponge-like layers. However, sponge-like PSi layers reveal less plastic deformation and higher wear resistance compared with layers with straight vertical pores.

  5. Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

    Directory of Open Access Journals (Sweden)

    Kwang Hong Lee

    2015-01-01

    Full Text Available A method to remove the misfit dislocations and reduce the threading dislocations density (TDD in the germanium (Ge epilayer growth on a silicon (Si substrate is presented. The Ge epitaxial film is grown directly on the Si (001 donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001 handle wafer to form a germanium-on-insulator (GOI substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

  6. Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

    Science.gov (United States)

    Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

    2013-05-06

    Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

  7. Impact of SiO2 on Al–Al thermocompression wafer bonding

    International Nuclear Information System (INIS)

    Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

    2015-01-01

    Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

  8. Electro-optic study of PZT ferroelectric ceramics using modulation of reflected light

    Science.gov (United States)

    Kniazkov, A. V.

    2016-04-01

    Electro-optic coefficients of variations in the refractive index of PZT and PLZT ceramic materials induced by ac electric field are estimated using modulation of reflected light. The electro-optic coefficients of PLZT ceramics measured with the aid of conventional birefringence using the phase shift of transmitted radiation and the proposed method of birefringence using the modulation of reflected light are compared.

  9. Effect of La and W dopants on dielectric and ferroelectric properties of PZT thin films prepared by sol-gel process

    International Nuclear Information System (INIS)

    Xiao, Mi; Zhang, Zebin; Zhang, Weikang; Zhang, Ping

    2018-01-01

    La or W-doped lead zirconate titanate thin films (PLZT or PZTW) were prepared on platinized silicon substrates by sol-gel process. The effects of La or W dopant on the phase development, microstructure, dielectric and ferroelectric characteristics of films were studied. For PLZT films, the optimum doping concentration was found to be 2 mol%. While for PZTW films, the dielectric and ferroelectric properties were found to be improved as the doping concentration increased. The fatigue properties of PLZT and PZTW thin films were also investigated, the results showed that A- or B-site donor doping could improve the fatigue properties of PZT thin films. The theory of oxygen vacancy was used to explain the performance improvement caused by donor doping. (orig.)

  10. Effect of La and W dopants on dielectric and ferroelectric properties of PZT thin films prepared by sol-gel process

    Science.gov (United States)

    Xiao, Mi; Zhang, Zebin; Zhang, Weikang; Zhang, Ping

    2018-01-01

    La or W-doped lead zirconate titanate thin films (PLZT or PZTW) were prepared on platinized silicon substrates by sol-gel process. The effects of La or W dopant on the phase development, microstructure, dielectric and ferroelectric characteristics of films were studied. For PLZT films, the optimum doping concentration was found to be 2 mol%. While for PZTW films, the dielectric and ferroelectric properties were found to be improved as the doping concentration increased. The fatigue properties of PLZT and PZTW thin films were also investigated, the results showed that A- or B-site donor doping could improve the fatigue properties of PZT thin films. The theory of oxygen vacancy was used to explain the performance improvement caused by donor doping.

  11. Non-catalytic direct synthesis of graphene on Si (111) wafers by using inductively-coupled plasma chemical vapor deposition

    Science.gov (United States)

    Hwang, Sung Won; Shin, Hyunho; Lee, Bongsoo; Choi, Suk-Ho

    2016-08-01

    We employ inductively-coupled plasma chemical vapor deposition for non-catalytic growth of graphene on a Si (111) wafer or glass substrate, which is useful for practical device applications of graphene without transfer processes. At a RF power (P) of 500 W under C2H2 flow, defect-free 3 ˜ 5-layer graphene is grown on Si (111) wafers, but on glass substrate, the layer is thicker and defective, as characterized by Raman spectroscopy and electron microscopy. The graphene is produced on Si (111) for P down to 190 W whereas it is almost not formed on glass for P < 250 W, possibly resulting from the weak catalytic-reaction-like effect on glass. These results are discussed based on possible growth mechanisms.

  12. Nanowire decorated, ultra-thin, single crystalline silicon for photovoltaic devices.

    Science.gov (United States)

    Aurang, Pantea; Turan, Rasit; Unalan, Husnu Emrah

    2017-10-06

    Reducing silicon (Si) wafer thickness in the photovoltaic industry has always been demanded for lowering the overall cost. Further benefits such as short collection lengths and improved open circuit voltages can also be achieved by Si thickness reduction. However, the problem with thin films is poor light absorption. One way to decrease optical losses in photovoltaic devices is to minimize the front side reflection. This approach can be applied to front contacted ultra-thin crystalline Si solar cells to increase the light absorption. In this work, homojunction solar cells were fabricated using ultra-thin and flexible single crystal Si wafers. A metal assisted chemical etching method was used for the nanowire (NW) texturization of ultra-thin Si wafers to compensate weak light absorption. A relative improvement of 56% in the reflectivity was observed for ultra-thin Si wafers with the thickness of 20 ± 0.2 μm upon NW texturization. NW length and top contact optimization resulted in a relative enhancement of 23% ± 5% in photovoltaic conversion efficiency.

  13. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

    Directory of Open Access Journals (Sweden)

    Nuno Brito

    2016-09-01

    Full Text Available The uniqueness of microelectromechanical system (MEMS devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr, quality factor (Q, and pull-in voltage (Vpi within 1.5 s with repeatability better than 5 ppt (parts per thousand. A full-wafer with 420 devices under test (DUTs has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

  14. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  15. Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

    Science.gov (United States)

    Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

    2005-01-01

    Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

  16. Characterization of 150 $\\mu$m thick epitaxial silicon detectors from different producers after proton irradiation

    CERN Document Server

    Hoedlmoser, H; Haerkoenen, J; Kronberger, M; Trummer, J; Rodeghiero, P

    2007-01-01

    Epitaxial (EPI) silicon has recently been investigated for the development of radiation tolerant detectors for future high-luminosity HEP experiments. A study of 150 mm thick EPI silicon diodes irradiated with 24GeV=c protons up to a fluence of 3 1015 p=cm2 has been performed by means of Charge Collection Efficiency (CCE) measurements, investigations with the Transient Current Technique (TCT) and standard CV=IV characterizations. The aim of the work was to investigate the impact of radiation damage as well as the influence of the wafer processing on the material performance by comparing diodes from different manufacturers. The changes of CCE, full depletion voltage and leakage current as a function of fluence are reported. While the generation of leakage current due to irradiation is similar in all investigated series of detectors, a difference in the effective doping concentration can be observed after irradiation. In the CCE measurements an anomalous drop in performance was found even for diodes exposed to ...

  17. Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

    International Nuclear Information System (INIS)

    Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

    1993-01-01

    The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

  18. Modeling film uniformity and symmetry in ionized metal physical vapor deposition with cylindrical targets

    International Nuclear Information System (INIS)

    Lu Junqing; Yang Lin; Yoon, Jae Hong; Cho, Tong Yul; Tao Guoqing

    2008-01-01

    Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed to investigate deposition uniformity and symmetry for cylindrical target sputtering in low pressure (below 0.1 Pa) ionized Cu physical vapor deposition. The model predictions indicate that as the distance from the cylindrical target to wafer increases, the metal film thickness becomes more uniform across the wafer and the asymmetry of the metal deposits at the wafer edge increases significantly. These trends are similar to those for planar targets. To minimize the asymmetry, the height of the cylindrical target should be kept at a minimum. For cylindrical targets, the outward-facing sidewall of the trench could receive more direct Cu fluxes than the inward-facing one when the target to wafer distance is short. The predictions also indicate that increasing the diameter of the cylindrical target could significantly reduce the asymmetry in metal deposits at the wafer edge and make the film thickness more uniform across the wafer

  19. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    NARCIS (Netherlands)

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  20. Low temperature spalling of silicon: A crack propagation study

    Energy Technology Data Exchange (ETDEWEB)

    Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

    2017-06-08

    Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.