Economic testing of large integrated switching circuits - a challenge to the test engineer

International Nuclear Information System (INIS)

Kreinberg, W.

1978-01-01

With reference to large integrated switching circuits, one can use an incoming standard programme test or the customer's switching circuits. The author describes the development of suitable, extensive and economical test programmes. (orig.) [de

Test Structures For Bumpy Integrated Circuits

Science.gov (United States)

Buehler, Martin G.; Sayah, Hoshyar R.

1989-01-01

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Optimal planning of series resistor to control time constant of test circuit for high-voltage AC circuit-breakers

OpenAIRE

Yoon-Ho Kim; Jung-Hyeon Ryu; Jin-Hwan Kim; Kern-Joong Kim

2016-01-01

The equivalent test circuit that can deliver both short-circuit current and recovery voltage is used to verify the performance of high-voltage circuit breakers. Most of the parameters in this circuit can be obtained by using a simple calculation or a simulation program. The ratings of the circuit breaker include rated short-circuit breaking current, rated short-circuit making current, rated operating sequence of the circuit breaker and rated short-time current. Among these ratings, the short-...

A new circuit for at-speed scan SoC testing

International Nuclear Information System (INIS)

Lin Wei; Shi Wenlong

2013-01-01

It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. (semiconductor integrated circuits)

Test generation for digital circuits using parallel processing

Science.gov (United States)

Hartmann, Carlos R.; Ali, Akhtar-Uz-Zaman M.

1990-12-01

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

In situ testing of the Shippingport Atomic Power Station electrical circuits

International Nuclear Information System (INIS)

Dinsel, M.R.; Donaldson, M.R.; Soberano, F.T.

1987-04-01

This report discusses the results of electrical in situ testing of selected circuits and components at the Shippingport Atomic Power Station in Shippingport, Pennsylvania. Testing was performed by EG and G Idaho in support of the United States Nuclear Regulatory Commission (USNRC) Nuclear Plant Aging Research (NPAR) Program. The goal was to determine the extent of aging or degradation of various circuits from the original plant, and the two major coreplant upgrades (representing three distinct age groups), as well as to evaluate previously developed surveillance technology. The electrical testing was performed using the Electrical Circuit Characterization and Diagnostic (ECCAD) system developed by EG and G for the US Department of Energy to use at TMI-2. Testing included measurements of voltage, effective series capacitance, effective series inductance, impedance, effective series resistance, dc resistance, insulation resistance and time domain reflectometry (TDR) parameters. The circuits evaluated included pressurizer heaters, control rod position indicator cables, miscellaneous primary system Resistance Temperature Detectors (RTDs), nuclear instrumentation cables, and safety injection system motor operated valves. It is to be noted that the operability of these circuits was tested after several years had elapsed because plant operations had concluded at Shippingport. There was no need following plant shutdown to retain the circuits in working condition, so no effort was expended for that purpose. The in situ measurements and analysis of the data confirmed the effectiveness of the ECCAD system for detecting degradation of circuit connections and splices because of high resistance paths, with most of the problems caused by corrosion. Results indicate a correlation between the chronological age of circuits and circuit degradation

Laser system for testing radiation imaging detector circuits

Science.gov (United States)

Zubrzycka, Weronika; Kasinski, Krzysztof

2015-09-01

Performance and functionality of radiation imaging detector circuits in charge and position measurement systems need to meet tight requirements. It is therefore necessary to thoroughly test sensors as well as read-out electronics. The major disadvantages of using radioactive sources or particle beams for testing are high financial expenses and limited accessibility. As an alternative short pulses of well-focused laser beam are often used for preliminary tests. There are number of laser-based devices available on the market, but very often their applicability in this field is limited. This paper describes concept, design and validation of laser system for testing silicon sensor based radiation imaging detector circuits. The emphasis is put on keeping overall costs low while achieving all required goals: mobility, flexible parameters, remote control and possibility of carrying out automated tests. The main part of the developed device is an optical pick-up unit (OPU) used in optical disc drives. The hardware includes FPGA-controlled circuits for laser positioning in 2 dimensions (horizontal and vertical), precision timing (frequency and number) and amplitude (diode current) of short ns-scale (3.2 ns) light pulses. The system is controlled via USB interface by a dedicated LabVIEW-based application enabling full manual or semi-automated test procedures.

Oscillation-based test in mixed-signal circuits

CERN Document Server

Sánchez, Gloria Huertas; Rueda, Adoración Rueda

2007-01-01

This book presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short. The results presented here assert, not only from a theoretical point of view, but also based on a wide experimental support, that OBT is an efficient defect-oriented test solution, complementing the existing functional test techniques for mixed-signal circuits.

Digital logic circuit test

Energy Technology Data Exchange (ETDEWEB)

Yun, Gil Jung; Yang, Hong Young

2011-03-15

This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

Science.gov (United States)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Optimization of the powering tests of the LHC superconducting circuits

CERN Document Server

Bellesia, B; Denz, R; Fernandez-Robles, C; Pojer, M; Saban, R; Schmidt, R; Solfaroli Camillocci, M; Thiesen, H; Vergara Fernández, A

2010-01-01

The Large Hadron Collider has (LHC) 1572 superconducting circuits which are distributed along the eight 3.5 km LHC sectors [1]. Time and resources during the commissioning of the LHC technical systems were mostly consumed by the powering tests of each circuit. The tests consisted in carrying out several powering cycles at different current levels for each superconducting circuit. The Hardware Commissioning Coordination was in charge of planning, following up and piloting the execution of the test program. The first powering test campaign was carried out in summer 2007 for sector 7-8 with an expected duration of 12 weeks. The experience gained during these tests was used by the commissioning team for minimising the duration of the following powering campaigns to comply with the stringent LHC project deadlines. Improvements concerned several areas: strategy, procedures, control tools, automatization, and resource allocation led to an average daily test rate increase from 25 to 200 tests per day. This paper desc...

Test results and in-orbit operation of the Infrared Astronomical Satellite circumvention circuit

Science.gov (United States)

Long, E. C.; Langford, D.

1984-01-01

The IRAS circumvention circuit (CC) eliminates the unwanted charged-particle pulses from the IR signal. The operation of the CC along with preflight and in-orbit testing is described. Ground testing of the brassboard circuit using a simulated preamplifier output showed that the CC would perform the circumvention function as designed. When all flight detectors and preamplifiers became available, the CC was tested using a gamma source to simulate charged-particle sources; with the low energy deposited in the detectors (20 keV average) the noise was reduced by up to 5 times with the CC turned on. In-orbit results show that the CC decreases the unwanted charged-particle background noise by up to two orders of magnitude. The difference in the results with the CC on and off is so great that the science team has recommended that no data be taken with the CC off.

Short Circuit Tests First Step of LHC Hardware Commissioning Completion

CERN Document Server

Barbero-Soto, E; Bordry, Frederick; Casas Lino, M P; Coelingh, G J; Cumer, G; Dahlerup-Petersen, K; Guillaume, J C; Inigo-Golfin, J; Montabonnet, V; Nisbet, D; Pojer, M; Principe, R; Rodríguez-Mateos, F; Saban, R; Schmidt, R; Thiesen, H; Vergara-Fernández, A; Zerlauth, M; Castaneda Serra, A; Romera Ramirez, I

2008-01-01

For the two counter rotating beams in the Large Hadron Collider (LHC) about 8000 magnets (main dipole and quadrupole magnets, corrector magnets, separation dipoles, matching section quadrupoles etc.) are powered in about 1500 superconducting electrical circuits. The magnets are powered by power converters that have been designed for the LHC with a current between 60 and 13000A. Between October 2005 and September 2007 the so-called Short Circuit Tests were carried-out in 15 underground zones where the power converters of the superconducting circuits are placed. The tests aimed to qualify the normal conducting equipments of the circuits such as power converters and normal conducting high current cables. The correct operation of interlock and energy extraction systems was validated. The infrastructure systems including AC distribution, water and air cooling and the control systems was also commissioned. In this paper the results of the two year test campaign are summarized with particular attention to problems e...

Testing and verification of a novel single-channel IGBT driver circuit

OpenAIRE

Lukić, Milan; Ninković, Predrag

2016-01-01

This paper presents a novel single-channel IGBT driver circuit together with a procedure for testing and verification. It is based on a specialized integrated circuit with complete range of protective functions. Experiments are performed to test and verify its behaviour. Experimental results are presented in the form of oscilloscope recordings. It is concluded that the new driver circuit is compatible with modern IGBT transistors and power converter demands and that it can be applied in new d...

LHC Report: superconducting circuit powering tests

CERN Multimedia

Mirko Pojer

2015-01-01

After the long maintenance and consolidation campaign carried out during LS1, the machine is getting ready to start operation with beam at 6.5 TeV… the physics community can’t wait! Prior to this, all hardware and software systems have to be tested to assess their correct and safe operation.   Most of the cold circuits (those with high current/stored energy) possess a sophisticated magnet protection system that is crucial to detect a transition of the coil from the superconducting to the normal state (a quench) and safely extract the energy stored in the circuits (about 1 GJ per dipole circuit at nominal current). LHC operation relies on 1232 superconducting dipoles with a field of up to 8.33 T operating in superfluid helium at 1.9 K, along with more than 500 superconducting quadrupoles operating at 4.2 or 1.9 K. Besides, many other superconducting and normal resistive magnets are used to guarantee the possibility of correcting all beam parameters, for a total of mo...

Automatic test pattern generation for stuck-at and delay faults in combinational circuits

International Nuclear Information System (INIS)

Kim, Dae Sik

1998-02-01

defined as the rising/falling transition. The existence of hazard leads to the invalidation of a nonrobust delay test. This 19-valued logic can avoid the conflict and unnecessary implications in generating the test set that it detects as many delay faults as possible by a single test. The calculation of the 19-valued algebra has a forward procedure, whereas that of the DF concept has a backward procedure. The proposed ATG program for stuck-at faults is applied to generate the test for stuck-at fault in a 3-input and a 4 input circuits of a universal card (UV Card). In addition, the proposed ATG program for delay faults is applied to generate the test for stuck-at fault in a 3-input and a 4 input circuits of a universal card (UV Card), and ISCAS85 benchmark circuits. The UV Card is a NPP digital input/output solid state protection system card [KEPCRC 88], and the ISCAS85 circuits are the combinational benchmark circuits [Brglez 85]. The experiment results on ISCAS85 benchmark circuits show the compactness of using DF concept and 19-valued algebra in increasing the average number of faults that are covered by single test

Approaching Repetitive Short Circuit Tests on MW-Scale Power Modules by means of an Automatic Testing Setup

DEFF Research Database (Denmark)

Reigosa, Paula Diaz; Wang, Huai; Iannuzzo, Francesco

2016-01-01

An automatic testing system to perform repetitive short-circuit tests on megawatt-scale IGBT power modules is pre-sented and described in this paper, pointing out the advantages and features of such testing approach. The developed system is based on a non-destructive short-circuit tester, which has...

Testing and verification of a novel single-channel IGBT driver circuit

Directory of Open Access Journals (Sweden)

Lukić Milan

2016-01-01

Full Text Available This paper presents a novel single-channel IGBT driver circuit together with a procedure for testing and verification. It is based on a specialized integrated circuit with complete range of protective functions. Experiments are performed to test and verify its behaviour. Experimental results are presented in the form of oscilloscope recordings. It is concluded that the new driver circuit is compatible with modern IGBT transistors and power converter demands and that it can be applied in new designs. It is a part of new 20kW industrial-grade boost converter.

Minimizing time for test in integrated circuit

OpenAIRE

Andonova, A. S.; Dimitrov, D. G.; Atanasova, N. G.

2004-01-01

The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimisation algorithm. A prototype of the proposed approach was tested on 1SCAS standard benchmarks and theexperimental results s...

A high frequency test bench for rapid single-flux-quantum circuits

International Nuclear Information System (INIS)

Engseth, H; Intiso, S; Rafique, M R; Tolkacheva, E; Kidiyarova-Shevchenko, A

2006-01-01

We have designed and experimentally verified a test bench for high frequency testing of rapid single-flux-quantum (RSFQ) circuits. This test bench uses an external tunable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift register. The clock pattern is consequently shifted out at high speed and split to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed read-out electronics. The test bench consists of 158 Josephson junctions and the occupied area is 3300 x 660 μm 2 . It was experimentally verified up to 33 GHz with ± 21.7% margins on the global bias supply current

Testing Fixture For Microwave Integrated Circuits

Science.gov (United States)

Romanofsky, Robert; Shalkhauser, Kurt

1989-01-01

Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

Directory of Open Access Journals (Sweden)

C. Wu

2011-06-01

Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.

Secondary coolant circuit operation tests: steam generator feedwater supply

International Nuclear Information System (INIS)

Beroux, M.

1985-01-01

No one important accident occurred during the start-up tests of the 1300MWe P4 series, concerning the feedwater system of steam generators (SG). This communication comments on some incidents, that the tests allowed to detect very soon and which had no consequences on the operation of units: 1) Water hammer in feedwater tubes, and incidents met in the emergency steam generator water supply circuit. The technological differences between SG 900 and 1300 are pointed out, and the measures taken to prevent this problem are presented. 2) Incidents met on the emergency feedwater supply circuit of steam generators; mechanical or functional modifications involved by these incidents [fr

Test and verification of a reactor protection system application-specific integrated circuit

International Nuclear Information System (INIS)

Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.

1997-01-01

Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing

A Discrete Event System Approach to Online Testing of Speed Independent Circuits

Directory of Open Access Journals (Sweden)

P. K. Biswal

2015-01-01

Full Text Available With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature.

RF and microwave integrated circuit development technology, packaging and testing

CERN Document Server

Gamand, Patrice; Kelma, Christophe

2018-01-01

RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

Design and test of a capacitance detection circuit based on a transimpedance amplifier

International Nuclear Information System (INIS)

Mu Linfeng; Zhang Wendong; He Changde; Zhang Rui; Song Jinlong; Xue Chenyang

2015-01-01

This paper presents a transimpedance amplifier (TIA) capacitance detection circuit aimed at detecting micro-capacitance, which is caused by ultrasonic stimulation applied to the capacitive micro-machined ultrasonic transducer (CMUT). In the capacitance interface, a TIA is adopted to amplify the received signal with a center frequency of 400 kHz, and finally detect ultrasound pressure. The circuit has a strong anti-stray property and this paper also studies the calculation of compensation capacity in detail. To ensure high resolution, noise analysis is conducted. After optimization, the detected minimum ultrasound pressure is 2.1 Pa, which is two orders of magnitude higher than the former. The test results showed that the circuit was sensitive to changes in ultrasound pressure and the distance between the CMUT and stumbling block, which also successfully demonstrates the functionality of the developed TIA of the analog-front-end receiver. (paper)

Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

International Nuclear Information System (INIS)

Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

1992-01-01

Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

A Low Speed BIST Framework for High Speed Circuit Testing

NARCIS (Netherlands)

Speek, H.; Kerkhoff, Hans G.; Shashaani, M.; Sachdev, M.

2000-01-01

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high

E-learning platform for automated testing of electronic circuits using signature analysis method

Science.gov (United States)

Gherghina, Cǎtǎlina; Bacivarov, Angelica; Bacivarov, Ioan C.; Petricǎ, Gabriel

2016-12-01

Dependability of electronic circuits can be ensured only through testing of circuit modules. This is done by generating test vectors and their application to the circuit. Testability should be viewed as a concerted effort to ensure maximum efficiency throughout the product life cycle, from conception and design stage, through production to repairs during products operating. In this paper, is presented the platform developed by authors for training for testability in electronics, in general and in using signature analysis method, in particular. The platform allows highlighting the two approaches in the field namely analog and digital signature of circuits. As a part of this e-learning platform, it has been developed a database for signatures of different electronic components meant to put into the spotlight different techniques implying fault detection, and from this there were also self-repairing techniques of the systems with this kind of components. An approach for realizing self-testing circuits based on MATLAB environment and using signature analysis method is proposed. This paper analyses the benefits of signature analysis method and simulates signature analyzer performance based on the use of pseudo-random sequences, too.

Analysis of a PCB In-Circuit Test and Its Optimized Cycle

International Nuclear Information System (INIS)

Chi, Moon Goo; Lee, Eun Chan; Bae, Yeon Kyoung

2011-01-01

KHNP performs subcomponent performance tests of the PCBs (Printed Circuit Boards) installed in safety-related systems or plant trip-related systems with every outage. The characteristics of each subcomponent are measured by test equipment. The tests are known as an ICT (In-Circuit Test). If a degraded condition is detected by this test, the affected subcomponents are replaced. This test has been conducted for 17 years, since 1994, and its results have been compiled into a test system database. As part of the reliability improvement plan of critical PCBs, KHNP developed a program that analyzes the performance of various key PCBs based on this test data. Thus, it became possible to evaluate the performance trends related to PCBs by tracing the test history of the PCB subcomponents through the ICT over many years. The present study also estimates an optimized ICT cycle that can be implemented to prevent the degradation of PCBs before they fail due to aging

A miniature microcontroller curve tracing circuit for space flight testing transistors.

Science.gov (United States)

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Test and Diagnosis of Integrated Circuits

OpenAIRE

Bosio , Alberto

2015-01-01

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

Thirteen years test experience with short-circuit withstand capability of large power transformers

NARCIS (Netherlands)

Smeets, R.P.P.; Paske, te L.H.; Leufkens, P.P.; Fogelberg, T.

2009-01-01

The ability to withstand a short circuit is recognised more and more as an essential characteristic of power transformers. IEC and IEEE Standards, as well as other national standards specify short-circuit testing and how to check the withstand capability. Unfortunately, however, there is extensive

A study on the development of an automatic fault diagnosis system for testing NPP digital electronic circuits

International Nuclear Information System (INIS)

Kim, Dae Sik

1993-02-01

This paper describes a study on the development of an automatic fault diagnosis system for testing digital electronic circuits of nuclear power plants. Compared with the other conventional fault diagnosis systems, the system described in this paper uses Artificial Intelligence technique of model based reasoning and corroboration, which makes fault diagnosis much more efficient. In order to reduce the testing time, an optimal testing set which means a minimal testing set to determine whether or not the circuit is fault-free and to locate the faulty gate was derived. Compared with the testing using an exhaustive testing set, the testing using the optimal testing set makes fault diagnosis much more fast. Since the system diagnoses the circuit boards bases only on input and output signals, it can be further developed for on-line testing. The system was implemented on a microprocessor and was applied for Universal Circuit board testing of the Solid State protection System in nuclear power plants

Hard alloys testing-machine for values of PWR primary coolant circuits

International Nuclear Information System (INIS)

Campan, J.L.; Sauze, A.

1980-01-01

Testing of valve parts or material used in valve fabrication and particularly seizing conditions in friction of plane surfaces coated with hard alloys of the type stellite. The testing equipment called Marguerite is composed of a hot pressurized water loop in conditions similar to PWR primary coolant circuits (320 0 C, 150 bars) and a testing-machine with measuring instruments. Testing conditions and samples are described [fr

Highly focused ion beams in integrated circuit testing

International Nuclear Information System (INIS)

Horn, K.M.; Dodd, P.E.; Doyle, B.L.

1996-01-01

The nuclear microprobe has proven to be a useful tool in radiation testing of integrated circuits. This paper reviews single event upset (SEU) and ion beam induced charge collection (IBICC) imaging techniques, with special attention to damage-dependent effects. Comparisons of IBICC measurements with three-dimensional charge transport simulations of charge collection are then presented for isolated p-channel field effect transistors under conducting and non-conducting bias conditions

Digital circuit testing a guide to DFT and other techniques

CERN Document Server

Wong, Francis C

1991-01-01

Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to

Integrated circuit test-port architecture and method and apparatus of test-port generation

Science.gov (United States)

Teifel, John

2016-04-12

A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.

Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

International Nuclear Information System (INIS)

Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

2010-01-01

A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

Test methods of total dose effects in very large scale integrated circuits

International Nuclear Information System (INIS)

He Chaohui; Geng Bin; He Baoping; Yao Yujuan; Li Yonghong; Peng Honglun; Lin Dongsheng; Zhou Hui; Chen Yusheng

2004-01-01

A kind of test method of total dose effects (TDE) is presented for very large scale integrated circuits (VLSI). The consumption current of devices is measured while function parameters of devices (or circuits) are measured. Then the relation between data errors and consumption current can be analyzed and mechanism of TDE in VLSI can be proposed. Experimental results of 60 Co γ TDEs are given for SRAMs, EEPROMs, FLASH ROMs and a kind of CPU

Method of boundary testing of the electric circuits and its application for calculating electric tolerances. [electric equipment tests

Science.gov (United States)

Redkina, N. P.

1974-01-01

Boundary testing of electric circuits includes preliminary and limiting tests. Preliminary tests permit determination of the critical parameters causing the greatest deviation of the output parameter of the system. The boundary tests offer the possibility of determining the limits of the fitness of the system with simultaneous variation of its critical parameters.

Aging evaluation of electrical circuits using the ECCAD [Electrical Circuit Characterization and Diagnostic] system

International Nuclear Information System (INIS)

Edson, J.L.

1988-01-01

As a part of the Nuclear Regulatory Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport Atomic Power Station Decommissioning Project. The objective of this work was to evaluate the effectiveness of the Electrical Circuit Characterization and Diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

Developing 300°C Ceramic Circuit Boards

Energy Technology Data Exchange (ETDEWEB)

Normann, Randy A

2015-02-15

This paper covers the development of a geothermal ceramic circuit board technology using 3D traces in a machinable ceramic. Test results showing the circuit board to be operational to at least 550°C. Discussion on producing this type of board is outlined along with areas needing improvement.

Development of data acquisition system for test circuit for the Thermo-Hydraulic Laboratory of CDTN

International Nuclear Information System (INIS)

Corrade, Thales Jose Rodrigues; Mesquita, Amir Zacarias; Santos, Andre Augusto Campagnole dos

2013-01-01

The Circuit Water-Air (CWA), present in the Laboratorio de Termo-Hidraulica of the Centro de Desenvolvimento da Tecnologia Nuclear/Comissao Nacional de Energia Nuclear (CDTN / CNEN), has been used to evaluate devices present in nuclear fuel elements of a PWR (Pressurized Water Reactor). Currently, a segment of 5x5 beam simulators grids with spacer bars is being tested, serving one of the activities under the Project FUJB / FINEP / INB - 'Development of New Generation of Nuclear Fuel Element '. For the measurements of pressure drop along this beam, a system of data acquisition based on Basic language was created. Although this system is efficient and robust, their resources are very limited. Therefore, it was decided to use the software LabVIEW® implementing a more versatile and modern system. This article describes the new data acquisition system, and presents some results. The main parameters are monitored: temperature, density, dynamic viscosity, Reynolds number. The values of standard deviation, mean and uncertainty of an arbitrary channel are calculated. The system was installed and tested in the circuit under experimental conditions and showed satisfactory results.

Apparatus and method for defect testing of integrated circuits

Science.gov (United States)

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Science.gov (United States)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

The short-circuit test results of 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer

International Nuclear Information System (INIS)

Tomioka, A.; Otonari, T.; Ogata, T.; Iwakuma, M.; Okamoto, H.; Hayashi, H.; Iijima, Y.; Saito, T.; Gosho, Y.; Tanabe, K.; Izumi, T.; Shiohara, Y.

2011-01-01

The 6.9 kV/2.3 kV 400 kVA-class single-phase YBCO model transformer with the YBCO tape with copper tape was manufactured for short-circuit current test. Short-circuit test was performed and the short-circuit current of primary winding was 346 A which was about six times larger than the rated current. The I-V characteristics of the winding did not change before and after the test. The transformer withstood short-circuit current. We are planning to turn the result into a consideration of a 66 kV/6.9 kV-20 MVA-class three-phase superconducting transformer. We are developing an elemental technology for 66 kV/6.9 kV 20 MVA-class power transformer with YBCO conductors. The protection of short-circuit technology is one of the elemental technologies for HTS transformer. Since short-circuit current is much higher than critical current of YBCO tape, there is a possibility that superconducting characteristics may be damaged during short-circuit period. We made a conductor to compose the YBCO tape with copper tape. We manufactured 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer using this conductor and performed short-circuit current test. The short-circuit current of primary winding was 346 A which was about six times larger than the rated current. The I-V characteristics of the winding did not change before and after the test. We may consider this conductor withstands short-circuit current.

Heavy ions testing experimental results on programmable integrated circuits

International Nuclear Information System (INIS)

Velazco, R.; Provost-Grellier, A.

1988-01-01

The natural radiation environment in space has been shown to produce anomalies in satellite-borne microelectronics. It becomes then mandatory to define qualification strategies allowing to choose the less vulnerable circuits. In this paper, is presented a strategy devoted to one of the most critical effects, the soft errors (so called upset). The method addresses programmable integrated circuits i.e. circuits able to execute an instruction or command set. Experimental results on representative circuits will illustrate the approach. 11 refs [fr

Testing of interposer-based 2.5D integrated circuits

CERN Document Server

Wang, Ran

2017-01-01

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and dela...

Effects of smoke on functional circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1997-10-01

Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs

Sodium corrosion tests in the ML 1 circuit

International Nuclear Information System (INIS)

Borgstedt, H.U.

1977-01-01

In the ML-1 circuit of the 'Juan Vigon' research centre in Madrid, sodium corrosion tests are being carried out on the austenitic steels DIN 1.4970 (X10NiCrMoTiB1515) and DIN 1.4301 (X5CrNi189) at temperatures between 500 and 700 0 C. The exposure time of the samples amounts to 6,000 h by now. Every 1,000 h, the samples were weighed in order to measure corrosion and deposition effects. After 3,000 and 6,000 h, some selected samples were destroyed for inspection. The results are given. (GSC) [de

Integrated circuit implementation of fuzzy controllers

OpenAIRE

Huertas Díaz, José Luis; Sánchez Solano, Santiago; Baturone Castillo, María Iluminada; Barriga Barros, Ángel

1996-01-01

This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno’s method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these...

Test and diagnosis of analogue, mixed-signal and RF integrated circuits the system on chip approach

CERN Document Server

Sun, Yichuang

2008-01-01

This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective.

Development of a Three-Tier Test to Assess Misconceptions about Simple Electric Circuits

Science.gov (United States)

Pesman, Haki; Eryilmaz, Ali

2010-01-01

The authors aimed to propose a valid and reliable diagnostic instrument by developing a three-tier test on simple electric circuits. Based on findings from the interviews, open-ended questions, and the related literature, the test was developed and administered to 124 high school students. In addition to some qualitative techniques for…

Measurements of the Effects of Smoke on Active Circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1999-01-01

Smoke has long been recognized as the most common source of fire damage to electrical equipment; however, most failures have been analyzed after the fire was out and the smoke vented. The effects caused while the smoke is still in the air have not been explored. Such effects have implications for new digital equipment being installed in nuclear reactors. The U.S. Nuclear Regulatory Commission is sponsoring work to determine the impact of smoke on digital instrumentation and control. As part of this program, Sandia National Laboratories has tested simple active circuits to determine how smoke affects them. These tests included the study of three possible failure modes on a functional board: (1) circuit bridging, (2) corrosion (metal loss), and (3) induction of stray capacitance. The performance of nine different circuits was measured continuously on bare and conformably coated boards during smoke exposures lasting 1 hour each and continued for 24 hours after the exposure started. The circuit that was most affected by smoke (100% change in measured values) was the one most sensitive to circuit bridging. Its high impedance (50 MOmega) was shorted during the exposure, but in some cases recovered after the smoke was vented. The other two failure modes, corrosion and induced stray capacitance, caused little change in the function of the circuits. The smoke permanently increased resistance of the circuit tested for corrosion, implying that the cent acts were corroded. However, the change was very small (< 2%). The stray-capacitance test circuit showed very little change after a smoke exposure in either the short or long term. The results of the tests suggest that conformal coatings and type of circuit are major considerations when designing digital circuitry to be used in critical control systems

Measurements of the effects of smoke on active circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1998-01-01

Smoke has long been recognized as the most common source of fire damage to electrical equipment; however, most failures have been analyzed after the fire was out and the smoke vented. The effects caused while the smoke is still in the air have not been explored. Such effects have implications for new digital equipment being installed in nuclear reactors. The US Nuclear Regulatory Commission is sponsoring work to determine the impact of smoke on digital instrumentation and control. As part of this program, Sandia National Laboratories has tested simple active circuits to determine how smoke affects them. These tests included the study of three possible failure modes on a functional board: (1) circuit bridging, (2) corrosion (metal loss), and (3) induction of stray capacitance. The performance of nine different circuits was measured continuously on bare and conformally coated boards during smoke exposures lasting 1 hour each and continued for 24 hours after the exposure started. The circuit that was most affected by smoke (100% change in measured values) was the one most sensitive to circuit bridging. Its high impedance (50 Mohm) was shorted during the exposure, but in some cases recovered after the smoke was vented. The other two failure modes, corrosion and induced stray capacitance, caused little change in the function of the circuits. The smoke permanently increased resistance of the circuit tested for corrosion, implying that the contacts were corroded. However, the change was very small (< 2%). The stray capacitance test circuit showed very little change after a smoke exposure in either the short or long term. The results of the tests suggest that conformal coatings and type of circuit are major considerations when designing digital circuitry to be used in critical control systems

Testing methods of gaseous admixtures in HLMC circuits

International Nuclear Information System (INIS)

Shelemet'ev, V.M.; Martynov, P.N.; Askhadullin, R.Sh.; Storozhenko, A.N.; Sadovnichij, R.P.; Ivanov, I.I.

2014-01-01

Control of gas phase is the effective method for state diagnostics of circuit of nuclear power facilities with heavy liquid metal coolants. Use of developing in IPPE solid electrolyte and conductometric oxygen and hydrogen sensors, which are set directly in gas system of the primary circuit, allows to maintain continuously control of oxygen and hydrogen content as well as operational efficiency and accuracy of these parameters determination under various situations related with oxygen and hydrogen insertion into circuit. Sensors ensure long-term safe operation under extreme conditions of high temperatures, pressures, humidity, etc., and are advanced devices for application in nuclear power facilities with heavy liquid metal coolants [ru

Manufacturing experience and test results of the PS prototype flexible hybrid circuit for the CMS Tracker Upgrade

CERN Document Server

Kovacs, Mark Istvan; Gadek, Tomasz; Honma, Alan; Vasey, Francois

2017-01-01

The CMS Tracker Phase-2 Upgrade for HL-LHC requires High Density Interconnect (HDI) flexible hybrid circuits to build modules with low mass and high granularity. The hybrids are carbon fibre reinforced flexible circuits with flip-chips and passives. Three different manufacturers produced prototype hybrids for the Pixel-Strip type modules. The first part of the presentation will focus on the design challenges of this state of the art circuit. Afterwards, the difficulties and experience related to the circuit manufacturing and assembly are presented. The description of quality inspection methods with comprehensive test results will lead to the conclusion.

Short-circuit tests of 1650 and 96 MVA transformers for 1300 MW french nuclear power plants

International Nuclear Information System (INIS)

Mailhot, M.

1989-01-01

Power evacuation and feeding of the auxiliaries directly from the 400 kV grid are sensitive points governing the security of 1300 MW PWR Nuclear Power Plants of the French Program. These two different functions are provided by two specific types of transformers. - Banks of 3 single-phase 550 MVA - 400 kV/20 kV transformers. - Three-phase 96 MVA - 400 kV / 3 x 6.8 kV transformers. These passive elements must have a never failing reliability and assure a continuous service in spite of electric, thermal and mechanical stresses that may occur during the lifetime of the power plant. Dielectric and thermal tests carried out in the manufacturers test floors insure these stresses withstand capabilities of transformers. In France, high short-circuit power for the 400 kV network added to often low impedance voltages for transformers impose on them very high stresses during short-circuits. Calculation and experimentation on scale or partial models are not sufficient to insure short-circuit currents withstand capabilities of transformers. The margin of uncertainty dependent on obligatory extrapolations for this kind of complex systems [steel, magnetic sheets, copper, oil, paper and transformerboard] can be reduced in a significant way only by real scale tests on prototypes. These tests that need both high power and voltage cannot be performed in manufacturers test floors. So, in France they are carried out at the EDF Les Renardieres Laboratory. Following paper deals with SHELL TYPE TRANSFORMERS which, particularly thanks to their interleaved rectangular windings display a great resistance to short-circuit stresses

Geometrical considerations in the transient ionization testing of digital logic circuits

International Nuclear Information System (INIS)

Johnston, A.

1982-01-01

Mechanisms are identified that can cause the transient response of digital logic circuits to depend on the logic state in which they are irradiated. Several of these mechanisms depend on surface topology, and for these cases the sensitive logic states can be determined by examining the topology. General approaches for transient radiation testing are also discussed for several MSI and LSI device technologies

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

Science.gov (United States)

Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

2015-11-01

We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80-120%, with respect to the designed bias currents.

Development of the automatic test pattern generation for NPP digital electronic circuits using the degree of freedom concept

International Nuclear Information System (INIS)

Kim, D.S.; Seong, P.H.

1995-01-01

In this paper, an improved algorithm for automatic test pattern generation (ATG) for nuclear power plant digital electronic circuits--the combinational type of logic circuits is presented. For accelerating and improving the ATG process for combinational circuits the presented ATG algorithm has the new concept--the degree of freedom (DF). The DF, directly computed from the system descriptions such as types of gates and their interconnections, is the criterion to decide which among several alternate lines' logic values required along each path promises to be the most effective in order to accelerate and improve the ATG process. Based on the DF the proposed ATG algorithm is implemented in the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, it is shown that the AFDS using the ATG algorithm makes Universal Card (UV Card) testing much faster than the present testing practice or by using exhaustive testing sets

Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

International Nuclear Information System (INIS)

Estreich, D.B.

1978-11-01

A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

Physically based arc-circuit interaction

International Nuclear Information System (INIS)

Zhong-Lie, L.

1984-01-01

An integral arc model is extended to study the interaction of the gas blast arc with the test circuit in this paper. The deformation in the waveshapes of arc current and voltage around the current zero has been formulated to first approximation by using a simple model of arc voltage based on the arc core energy conservation. By supplementing with the time scale for the radiation, the time rates of arc processes were amended. Both the contributions of various arc processes and the influence of circuit parameters to the arc-circuit interaction have been estimated by this theory. Analysis generated a new method of calculating test circuit parameters which improves the accurate simulation of arc-circuit interaction. The new method agrees with the published experimental results

Modeling a verification test system for mixed-signal circuits

NARCIS (Netherlands)

San Segundo Bello, D.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.

In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block

Influence of different open circuit voltage tests on state of charge online estimation for lithium-ion batteries

International Nuclear Information System (INIS)

Zheng, Fangdan; Xing, Yinjiao; Jiang, Jiuchun; Sun, Bingxiang; Kim, Jonghoon; Pecht, Michael

2016-01-01

Highlights: • Two common tests for observing battery open circuit voltage performance are compared. • The temperature dependency of the OCV-SOC relationship is investigated. • Two estimators are evaluated in terms of accuracy and robustness for estimating battery SOC. • The incremental OCV test is better to predetermine the OCV-SOCs for SOC online estimation. - Abstract: Battery state of charge (SOC) estimation is a crucial function of battery management systems (BMSs), since accurate estimated SOC is critical to ensure the safety and reliability of electric vehicles. A widely used technique for SOC estimation is based on online inference of battery open circuit voltage (OCV). Low-current OCV and incremental OCV tests are two common methods to observe the OCV-SOC relationship, which is an important element of the SOC estimation technique. In this paper, two OCV tests are run at three different temperatures and based on which, two SOC estimators are compared and evaluated in terms of tracking accuracy, convergence time, and robustness for online estimating battery SOC. The temperature dependency of the OCV-SOC relationship is investigated and its influence on SOC estimation results is discussed. In addition, four dynamic tests are presented, one for estimator parameter identification and the other three for estimator performance evaluation. The comparison results show that estimator 2 (based on the incremental OCV test) has higher tracking accuracy and is more robust against varied loading conditions and different initial values of SOC than estimator 1 (based on the low-current OCV test) with regard to ambient temperature. Therefore, the incremental OCV test is recommended for predetermining the OCV-SOCs for battery SOC online estimation in BMSs.

Comminution circuits for compact itabirites

Directory of Open Access Journals (Sweden)

Pedro Ferreira Pinto

Full Text Available Abstract In the beneficiation of compact Itabirites, crushing and grinding account for major operational and capital costs. As such, the study and development of comminution circuits have a fundamental importance for feasibility and optimization of compact Itabirite beneficiation. This work makes a comparison between comminution circuits for compact Itabirites from the Iron Quadrangle. The circuits developed are: a crushing and ball mill circuit (CB, a SAG mill and ball mill circuit (SAB and a single stage SAG mill circuit (SSSAG. For the SAB circuit, the use of pebble crushing is analyzed (SABC. An industrial circuit for 25 million tons of run of mine was developed for each route from tests on a pilot scale (grinding and industrial scale. The energy consumption obtained for grinding in the pilot tests was compared with that reported by Donda and Bond. The SSSAG route had the lowest energy consumption, 11.8kWh/t and the SAB route had the highest energy consumption, 15.8kWh/t. The CB and SABC routes had a similar energy consumption of 14.4 kWh/t and 14.5 kWh/t respectively.

30 CFR 57.6407 - Circuit testing.

Science.gov (United States)

2010-07-01

...) Continuity of each electric detonator in the blasthole prior to stemming and connection to the blasting line... connection of electric detonator series; and (4) Total blasting circuit resistance prior to connection to the...) Continuity of blasting lines prior to the connection of electric detonators. Nonelectric Blasting—Surface and...

Fault Modeling and Testing for Analog Circuits in Complex Space Based on Supply Current and Output Voltage

Directory of Open Access Journals (Sweden)

Hongzhi Hu

2015-01-01

Full Text Available This paper deals with the modeling of fault for analog circuits. A two-dimensional (2D fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional (3D complex space is proposed, which achieves a far better fault detection ratio (FDR against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT method. By adding redundant bypassing-components in the circuit under test (CUT, this method achieves excellent fault isolation ratio (FIR in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.

The life test of a DC circuit breaker of tokamak device JT-60 for a nuclear fusion research

International Nuclear Information System (INIS)

Shimada, Ryuichi; Tani, Keiji; Kishimoto, Hiroshi; Tamura, Sanae; Yanabu, Satoru.

1979-01-01

In the Tokamak devices for nuclear fusion research, the construction of the current transformer circuits having plasma as the secondary circuit and the change of the primary circuit current are necessary for generating current in the plasma. This is considered to be fairly difficult in practice if conventional methods using capacitor discharge and iron core coils are employed. Considering such circumstances, it was decided for JT-60 to use an air-core current transformer coil and to employ the method of storing energy in the form of current in the coil inductance instead of a capacitor. For this reason, a DC circuit breaker is required to interrupt coil current. The authors improved an AV vacuum breaker, which had been developed as the vacuum breaker of longitudinal magnetic field type applying a magnetic field in parallel with an arc, to get the one for DC circuit for the purpose of applying it to JT-60. In this paper, the operational characteristic of the DC breaker is described, the construction and function of the life test circuit is explained, and the test results are reported. Finally, interruptions of 10,000 times at 20 kA were carried out. It is successful that the restrike of arc occurring during tens of milli-seconds after interruptions was improved to 0.05% or less for 10,000 times operations. Further, it was found that the generation of arc restrike can be reduced practically to zero with two breakers in series. (Wakatsuki, Y.)

Test model of the fast thyristor circuit breaker, for TORE SUPRA

International Nuclear Information System (INIS)

Bareyt, B.; Leloup, C.; Rijnoudt, E.

1984-01-01

The tokamak TORE SUPRA, permits, owing to the toroidal superconducting coils and to the poloidal field system performances, long discharges (30 s and more), for a plasma current of typically 2 MA. The poloidal field system uses the magnetic energy initially stored, for the ignition and the fast rise of the plasma current, by forcing the primary current to flow through a resistor after breaking the main rectifier current by a fast thyristor circuit breaker. In order to test the technical capabilities of such a breaker system made of fast thyristors, in series and in parallel, after a single thyristor test model T1 the series arrangement was studied on a 24 thyristor test model T2 and the parallel arrangement problems, led the manufacturer CGEE Alsthom, to build a new test model T3. (author)

WindoWorks: A flexible program for computerized testing of accelerator control system electronic circuit boards

International Nuclear Information System (INIS)

Utterback, J.

1993-09-01

Since most accelerator control system circuit boards reside in a commercial bus architecture, such as CAMAC or VMEbus, a computerized test station is needed for exercising the boards. This test station is needed for the development of newly designed prototypes, for commissioning newly manufactured boards, for diagnosing boards which have failed in service, and for long term testing of boards with intermittent failure problems. WindoWorks was created to address these needs. It is a flexible program which runs on a PC compatible computer and uses a PC to bus crate interface. WindoWorks was designed to give the user a flexible way to test circuit boards. Each test is incapsulated into a window. By bringing up several different windows the user can run several different tests simultaneously. The windows are sizable, and moveable. They have data entry boxes so that the test can be customized to the users preference. The windows can be used in conjunction with each other in order to create supertests. There are several windows which are generic. They can be used to test basic functions on any VME (or CAMAC) board. There are other windows which have been created to test specific boards. New windows for testing specific boards can be easily created by a Pascal programmer using the WindoWorks framework

Model Comparison Exercise Circuit Training Game and Circuit Ladder Drills to Improve Agility and Speed

Directory of Open Access Journals (Sweden)

Susilaturochman Hendrawan Koestanto

2017-11-01

Full Text Available The purpose of this study was to compare: (1 the effect of circuit training game and circuit ladder drill for the agility; (2 the effect of circuit training game and circuit ladder drill on speed; (3 the difference effect of circuit training game and circuit ladder drill for the speed (4 the difference effect of circuit training game and circuit ladder drill on agility. The type of this research was quantitative with quasi-experimental methods. The design of this research was Factorial Design, with analysing data using ANOVA. The process of data collection was done by using 30 meters sprint speed test and shuttle run test during the pretest and posttest. Furthermore, the data was analyzed by using SPSS 22.0 series. Result: The circuit training game exercise program and circuit ladder drill were significant to increase agility and speed (sig 0.000 < α = 0.005 Group I, II, III had significant differences (sig 0.000 < α = 0.005. The mean of increase in speed of group I = 0.20 seconds, group II = 0.31 seconds, and group III = 0.11 seconds. The average increase agility to group I = 0.34 seconds group II = 0.60 seconds, group III = 0.13 seconds. Based on the analysis above, it could be concluded that there was an increase in the speed and agility of each group after being given a training.

High accuracy digital aging monitor based on PLL-VCO circuit

International Nuclear Information System (INIS)

Zhang Yuejun; Jiang Zhidi; Wang Pengjun; Zhang Xuelong

2015-01-01

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm 2 . After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%. (semiconductor integrated circuits)

Proposed minimum requirements for the operational characteristics and testing of closed circuit life support system control electronics.

Science.gov (United States)

Kirk, J C

1998-01-01

The popularization and transformation of scuba diving into a broadly practiced sport has served to ignite the interest of technically oriented divers into ever more demanding areas. This, along with the gradual release of military data, equipment, and techniques of closed circuit underwater breathing apparatus, has resulted in a virtual explosion of semiclosed and closed circuit systems for divers. Although many of these systems have been carefully thought out by capable designers, the impulse to rush to market with equipment that has not been fully developed and carefully tested is irresistible to marketers. In addition, the presence of systems developed by well-intentioned and otherwise competent designers who are, nonetheless, inexperienced in the field of life support can result in the sale of failure-prone equipment to divers who lack the knowledge and skills to identify deficiencies before disaster occurs. For this reason, a set of industry standards establishing minimum requirements and testing is needed to guide the designers of this equipment, and to protect the user community from incomplete or inadequate design. Many different technologies go into the development of closed circuit scuba. One key area is the design of electronics to monitor and maintain the critical gas mixtures of the closed circuit loop. Much of the system reliability and inherent danger is resident in the design of the circuitry and the software (if any) that runs it. This article will present a set of proposed minimum requirements, with the goal of establishing a dialog for the creation of guidelines for the classification, rating, design, and testing of embedded electronics for life support systems used in closed circuit applications. These guidelines will serve as the foundation for the later creation of a set of industry specifications.

Cell short circuit, preshort signature

Science.gov (United States)

Lurie, C.

1980-01-01

Short-circuit events observed in ground test simulations of DSCS-3 battery in-orbit operations are analyzed. Voltage signatures appearing in the data preceding the short-circuit event are evaluated. The ground test simulation is briefly described along with performance during reconditioning discharges. Results suggest that a characteristic signature develops prior to a shorting event.

General Voltage Feedback Circuit Model in the Two-Dimensional Networked Resistive Sensor Array

Directory of Open Access Journals (Sweden)

JianFeng Wu

2015-01-01

Full Text Available To analyze the feature of the two-dimensional networked resistive sensor array, we firstly proposed a general model of voltage feedback circuits (VFCs such as the voltage feedback non-scanned-electrode circuit, the voltage feedback non-scanned-sampling-electrode circuit, and the voltage feedback non-scanned-sampling-electrode circuit. By analyzing the general model, we then gave a general mathematical expression of the effective equivalent resistor of the element being tested in VFCs. Finally, we evaluated the features of VFCs with simulation and test experiment. The results show that the expression is applicable to analyze the VFCs’ performance of parameters such as the multiplexers’ switch resistors, the nonscanned elements, and array size.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

International Nuclear Information System (INIS)

Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

2015-01-01

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

Energy Technology Data Exchange (ETDEWEB)

Yamada, Takahiro, E-mail: yamada-takahiro@aist.go.jp [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Maezawa, Masaaki [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Urano, Chiharu [National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Central 3, Umezono 1-1-1, Tsukuba, Ibaraki 305-8563 (Japan)

2015-11-15

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Scale model test on a novel 400 kV double-circuit composite pylon

DEFF Research Database (Denmark)

Wang, Qian; Bak, Claus Leth; Silva, Filipe Miguel Faria da

This paper investigates lightning shielding performance of a novel 400 kV double-circuit composite pylon, with the method of scale model test. Lightning strikes to overhead lines were simulated by long-gap discharges between a high voltage electrode with an impulse voltage and equivalent conductors...... around the pylon is discussed. Combined test results and striking distance equation in electro-geometric model, the approximate maximum lightning current that can lead to shielding failure is calculated. Test results verify that the unusual negative shielding angle of - 60° in the composite pylon meets...... requirement and the shielding wires provide acceptable protection from lightning strikes....

Aging evaluation of electrical circuits using the ECCAD system

International Nuclear Information System (INIS)

Edson, J.L.

1988-01-01

As a part of the Nuclear Regulator Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport atomic power station decommissioning project. The objective of this work was to evaluate the effectiveness of the electrical circuit characterization and diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

The Plateau de Bure ASTEP Platform Test in natural radiation environment of electronic components and circuits

International Nuclear Information System (INIS)

Autran, J.L.; Munteanu, D.; Sauze, S.; Roche, Ph.; Gasiot, G.; Borel, J.

2010-01-01

Reducing the size of microelectronic devices and increasing the integration density of circuits lead (following the famous Moore's law) to an increased sensitivity of circuits to natural terrestrial radiation environment. - Such sensitivity to atmospheric particles (mainly neutrons) can cause non-destructive (soft-errors) or destructive (latch-up) failures in most electronic circuits, including volatile static memories (SRAM), object of the research work carried out since 2004 on the European Test Platform ASTER. - This paper presents in details the ASTEP platform, its location, the instruments (neutron monitor of the Plateau de Bure) and the experiences (memory tester) currently installed on the Plateau de Bure. In a second part, we also report a synthesis of the key results concerning the natural radiation sensitivity of SRAM fabricated in 130 nm and 65 nm bulk silicon technologies. (authors)

A proposed hardness assurance test methodology for bipolar linear circuits and devices in a space ionizing radiation environment

International Nuclear Information System (INIS)

Pease, R.L.; Brown, D.B.; Cohn, L.

1997-01-01

A hardness assurance test approach has been developed for bipolar linear circuits and devices in space. It consists of a screen for dose rate sensitivity and a characterization test method to develop the conditions for a lot acceptance test at high dose rate

Testing of 800 and 1200 kV class circuit breakers

NARCIS (Netherlands)

Smeets, R.P.P.; Kuivenhoven, S.; Hofstee, A.B.

2011-01-01

The most critical transient a circuit breaker has to endure during its operation is the transient recovery voltage (TRV), initiated by the electric power system as a natural reaction on current interruption. For circuit breakers intended to operate in ultra-high voltage systems (with rated voltage

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

Design and experimental results of coaxial circuits for gyroklystron amplifiers

International Nuclear Information System (INIS)

Flaherty, M.K.E.; Lawson, W.; Cheng, J.; Calame, J.P.; Hogan, B.; Latham, P.E.; Granatstein, V.L.

1994-01-01

At the University of Maryland high power microwave source development for use in linear accelerator applications continues with the design and testing of coaxial circuits for gyroklystron amplifiers. This presentation will include experimental results from a coaxial gyroklystron that was tested on the current microwave test bed, and designs for second harmonic coaxial circuits for use in the next generation of the gyroklystron program. The authors present test results for a second harmonic coaxial circuit. Similar to previous second harmonic experiments the input cavity resonated at 9.886 GHz and the output frequency was 19.772 GHz. The coaxial insert was positioned in the input cavity and drift region. The inner conductor consisted of a tungsten rod with copper and ceramic cylinders covering its length. Two tungsten rods that bridged the space between the inner and outer conductors supported the whole assembly. The tube produced over 20 MW of output power with 17% efficiency. Beam interception by the tungsten rods resulted in minor damage. Comparisons with previous non-coaxial circuits showed that the coaxial configuration increased the parameter space over which stable operation was possible. Future experiments will feature an upgraded modulator and beam formation system capable of producing 300 MW of beam power. The fundamental frequency of operation is 8.568 GHz. A second harmonic coaxial gyroklystron circuit was designed for use in the new system. A scattering matrix code predicts a resonant frequency of 17.136 GHz and Q of 260 for the cavity with 95% of the outgoing microwaves in the desired TE032 mode. Efficiency studies of this second harmonic output cavity show 20% expected efficiency. Shorter second harmonic output cavity designs are also being investigated with expected efficiencies near 34%

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

Development, testing, and demonstration of an optimal fine coal cleaning circuit

International Nuclear Information System (INIS)

Mishra, M.; Placha, M.; Bethell, P.

1995-01-01

The overall objective of this project is to improve the efficiency of fine coal cleaning. The project will be completed in two phases: bench-scale testing and demonstration of four advanced flotation cells and; in-plant proof-of-concept (POC) pilot plant testing of two flotation cells individually and in two-stage combinations. The goal is to ascertain if a two-stage circuit can result in reduced capital and operating costs while achieving improved separation efficiency. The plant selected for this project, Cyprus Emerald Coal Preparation plant, cleans 1200 tph of raw coal. The plant produces approximately 4 million tonnes of clean coal per year at an average as received energy content of 30.2 MJ/Kg (13,000 Btu/lb)

Development, testing, and demonstration of an optimal fine coal cleaning circuit

Energy Technology Data Exchange (ETDEWEB)

Mishra, M.; Placha, M.; Bethell, P. [and others

1995-11-01

The overall objective of this project is to improve the efficiency of fine coal cleaning. The project will be completed in two phases: bench-scale testing and demonstration of four advanced flotation cells and; in-plant proof-of-concept (POC) pilot plant testing of two flotation cells individually and in two-stage combinations. The goal is to ascertain if a two-stage circuit can result in reduced capital and operating costs while achieving improved separation efficiency. The plant selected for this project, Cyprus Emerald Coal Preparation plant, cleans 1200 tph of raw coal. The plant produces approximately 4 million tonnes of clean coal per year at an average as received energy content of 30.2 MJ/Kg (13,000 Btu/lb).

Nuclear code case development of printed-circuit heat exchangers with thermal and mechanical performance testing

Energy Technology Data Exchange (ETDEWEB)

Aakre, Shaun R. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering; Jentz, Ian W. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering; Anderson, Mark H. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering

2018-03-27

The U.S. Department of Energy has agreed to fund a three-year integrated research project to close technical gaps involved with compact heat exchangers to be used in nuclear applications. This paper introduces the goals of the project, the research institutions, and industrial partners working in collaboration to develop a draft Boiler and Pressure Vessel Code Case for this technology. Heat exchanger testing, as well as non-destructive and destructive evaluation, will be performed by researchers across the country to understand the performance of compact heat exchangers. Testing will be performed using coolants and conditions proposed for Gen IV Reactor designs. Preliminary observations of the mechanical failure mechanisms of the heat exchangers using destructive and non-destructive methods is presented. Unit-cell finite element models assembled to help predict the mechanical behavior of these high-temperature components are discussed as well. Performance testing methodology is laid out in this paper along with preliminary modeling results, an introduction to x-ray and neutron inspection techniques, and results from a recent pressurization test of a printed-circuit heat exchanger. The operational and quality assurance knowledge gained from these models and validation tests will be useful to developers of supercritical CO₂ systems, which commonly employ printed-circuit heat exchangers.

Optimal testing input sets for reduced diagnosis time of nuclear power plant digital electronic circuits

International Nuclear Information System (INIS)

Kim, D.S.; Seong, P.H.

1994-01-01

This paper describes the optimal testing input sets required for the fault diagnosis of the nuclear power plant digital electronic circuits. With the complicated systems such as very large scale integration (VLSI), nuclear power plant (NPP), and aircraft, testing is the major factor of the maintenance of the system. Particularly, diagnosis time grows quickly with the complexity of the component. In this research, for reduce diagnosis time the authors derived the optimal testing sets that are the minimal testing sets required for detecting the failure and for locating of the failed component. For reduced diagnosis time, the technique presented by Hayes fits best for the approach to testing sets generation among many conventional methods. However, this method has the following disadvantages: (a) it considers only the simple network (b) it concerns only whether the system is in failed state or not and does not provide the way to locate the failed component. Therefore the authors have derived the optimal testing input sets that resolve these problems by Hayes while preserving its advantages. When they applied the optimal testing sets to the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, they found that the fault diagnosis using the optimal testing sets makes testing the digital electronic circuits much faster than that using exhaustive testing input sets; when they applied them to test the Universal (UV) Card which is a nuclear power plant digital input/output solid state protection system card, they reduced the testing time up to about 100 times

Circuits on Cylinders

DEFF Research Database (Denmark)

Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V

2006-01-01

We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching pro...

Simulation of worst-case operating conditions for integrated circuits operating in a total dose environment

International Nuclear Information System (INIS)

Bhuva, B.L.

1987-01-01

Degradations in the circuit performance created by the radiation exposure of integrated circuits are so unique and abnormal that thorough simulation and testing of VLSI circuits is almost impossible, and new ways to estimate the operating performance in a radiation environment must be developed. The principal goal of this work was the development of simulation techniques for radiation effects on semiconductor devices. The mixed-mode simulation approach proved to be the most promising. The switch-level approach is used to identify the failure mechanisms and critical subcircuits responsible for operational failure along with worst-case operating conditions during and after irradiation. For precise simulations of critical subcircuits, SPICE is used. The identification of failure mechanisms enables the circuit designer to improve the circuit's performance and failure-exposure level. Identification of worst-case operating conditions during and after irradiation reduces the complexity of testing VLSI circuits for radiation environments. The results of test circuits for failure simulations using a conventional simulator and the new simulator showed significant time savings using the new simulator. The savings in simulation time proved to be circuit topology-dependent. However, for large circuits, the simulation time proved to be orders of magnitude smaller than simulation time for conventional simulators

Low Pressure Circuit Control and adjust System Test

International Nuclear Information System (INIS)

Rubio, R.O; Brendstrup, C.J; Ocampo, A.C

2000-01-01

The hydraulic mechanism (MSAC) is a system that will be employed in the movement of the control rods of the CAREM-25 reactor.In this report, the experimental work on a prototype of MSAC in a low pressure circuit is presented: also the methodology and conclusions.Basic thermalhydraulic data from the MSAC was obtained, and the most relevant control parameters were determined.The response of the mechanism to changes in the control parameters was also evaluated. In conclusion, the response of the MSAC fulfills the aspects of reliability and repetitive movement with water flow pulses control, in the low pressure circuit at the Laboratorio de Mecanica, Materiales y Mediciones of INVAP S.E

Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients

Directory of Open Access Journals (Sweden)

Michael Auer

2009-02-01

Full Text Available The aim of this work is to develop a simultaneous multi user access system – READ (Remote ASIC Design and Test that allows users to perform test and measurements remotely via clients running on mobile devices as well as on standard PCs. The system also facilitates the remote design of circuits with the PAC-Designer The system is controlled by LabVIEW and was implemented using a Data Acquisition Card from National instruments. Such systems are specially suited for manufacturing process monitoring and control. The performance of the simultaneous access was tested under load with a variable number of users. The server implements a queue that processes user’s commands upon request.

The online sealing performance test of the primary circuit pressure boundary check valve in nuclear power plants

International Nuclear Information System (INIS)

Yang Yunfei; Huang Huimin

2013-01-01

The primary circuit pressure boundary check valves of 320 MW pressurized water reactor is a nuclear grade I key equipment. The sealing demand is very high, which is directly related to the internal leakage rate of the primary circuit system. After the welding check valve is repaired, the sealing performance is judged by color printing checks. If there is water or humid vapor in the pipe, it will affect the accuracy of the color printing checks. For the particularity of the online check valve tightness test, online detecting device is designed by the hydraulic pressure drop method in other nuclear power plants, but the method has some shortcomings and restrictions. In this paper, we design a reliable and portable test equipment by the low-pressure gas seal test flow measurement, which make accurate and quantitative judgment of sealing property after the pressure boundary check valves are repaired. (authors)

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

Science.gov (United States)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Circuit Design of Surface Acoustic Wave Based Micro Force Sensor

Directory of Open Access Journals (Sweden)

Yuanyuan Li

2014-01-01

Full Text Available Pressure sensors are commonly used in industrial production and mechanical system. However, resistance strain, piezoresistive sensor, and ceramic capacitive pressure sensors possess limitations, especially in micro force measurement. A surface acoustic wave (SAW based micro force sensor is designed in this paper, which is based on the theories of wavelet transform, SAW detection, and pierce oscillator circuits. Using lithium niobate as the basal material, a mathematical model is established to analyze the frequency, and a peripheral circuit is designed to measure the micro force. The SAW based micro force sensor is tested to show the reasonable design of detection circuit and the stability of frequency and amplitude.

Duffing–van der Pol oscillator type dynamics in Murali–Lakshmanan–Chua (MLC) circuit

International Nuclear Information System (INIS)

Srinivasan, K.; Chandrasekar, V.K.; Venkatesan, A.; Raja Mohamed, I.

2016-01-01

Highlights: • Proposed an electronic circuit with diode based nonlinear element equivalent to a well known Murali–Lakshmanan–Chua (MLC) circuit. • For chosen circuit parameters this circuit admits familiar MLC type attractor and also Duffing–van der Pol circuit type chaotic attractor. • The performance of the circuit is investigated by means of explicit laboratory experiments, numerical simulations and analytical studies. - Abstract: We have constructed a simple second-order dissipative nonautonomous circuit exhibiting ordered and chaotic behaviour. This circuit is the well known Murali–Lakshmanan–Chua(MLC) circuit but with diode based nonlinear element. For chosen circuit parameters this circuit admits familiar MLC type attractor and also Duffing–van der Pol circuit type chaotic attractors. It is interesting to note that depending upon the circuit parameters the circuit shows both period doubling route to chaos and quasiperiodic route to chaos. In our study we have constructed two-parameter bifurcation diagrams in the forcing amplitude–frequency plane, one parameter bifurcation diagrams, Lyapunov exponents, 0–1 test and phase portrait. The performance of the circuit is investigated by means of laboratory experiments, numerical integration of appropriate mathematical model and explicit analytic studies.

Tester Detects Steady-Short Or Intermittent-Open Circuits

Science.gov (United States)

Anderson, Bobby L.

1990-01-01

Momentary open circuits or steady short circuits trigger buzzer. Simple, portable, lightweight testing circuit sounds long-duration alarm when it detects steady short circuit or momentary open circuit in coaxial cable or other two-conductor transmission line. Tester sensitive to discontinuities lasting 10 microseconds or longer. Used extensively for detecting intermittent open shorts in accelerometer and extensometer cables. Also used as ordinary buzzer-type continuity checker to detect steady short or open circuits.

Development of a pulse shape discrimination circuit

International Nuclear Information System (INIS)

Ye Bangjiao; Fan Wei; Fan Yangmei; Yu Xiaoqi; Mei Wen; Wang Zhongmin; Han Rongdian; Xiao Zhenxi

1994-01-01

A pulse shape discrimination circuit was designed and used in an experiment measuring double-differential cross sections of (n, charged particle) reaction; to identify p, α and γ. The performance of the circuit was tested. With this circuit, excellent identification of p, α and γ was obtained. ((orig.))

Digital circuit boards mach 1 GHz

CERN Document Server

Morrison, Ralph

2012-01-01

A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

Life testing of a low voltage air circuit breaker

International Nuclear Information System (INIS)

Subudhi, M.

1991-01-01

ADS-416 low voltage air circuit breaker manufacture by Westinghouse was mechanically cycled to identify age-related degradation in various breaker subcomponents, in particular, the power-operating mechanism. This accelerated aging test was performed on one breaker unit for over 36,000 cycles. Three separate pole shafts, one with a 60 degree weld, one with a 120 degree weld and one with a 180 degree weld in the third pole lever were used to characterize the cracking in these welds. In addition, during the testing, three different operating mechanisms and several other parts were replaced as they degraded to an inoperable condition. Of the seven welds on the pole shaft, two were found to be the critical ones whose fracture can result in misalignment problems of the pole levers. These failures, in turn can lead to many other problems with the operating mechanism including the burn-out of coils, excessive wear in certain parts and over-stressed linkages. Furthermore, the limiting service life of a number of subcomponents of the power-operated mechanism, including the operating mechanism itself, were assessed. 1 ref., 3 figs

Simulation of TunneLadder traveling-wave tube cold-test characteristics: Implementation of the three-dimensional, electromagnetic circuit analysis code micro-SOS

Science.gov (United States)

Kory, Carol L.; Wilson, Jeffrey D.

1993-01-01

The three-dimensional, electromagnetic circuit analysis code, Micro-SOS, can be used to reduce expensive time-consuming experimental 'cold-testing' of traveling-wave tube (TWT) circuits. The frequency-phase dispersion characteristics and beam interaction impedance of a TunneLadder traveling-wave tube slow-wave structure were simulated using the code. When reasonable dimensional adjustments are made, computer results agree closely with experimental data. Modifications to the circuit geometry that would make the TunneLadder TWT easier to fabricate for higher frequency operation are explored.

Experimental Study of WBFC method for testing electromagnetic immunity of integrated circuits

OpenAIRE

香川, 直己; カガワ, ナオキ; Naoki, KAGAWA

2004-01-01

The author made a workbench faraday cage, WBFC, in order to estimate performance of the WBFC method for the measurement of common mode noise immunity of integrated circuits. In this report, characteristics of the constructed workbench faraday cage and results of experimental study of effects of the common mode noise on a circuit board including an electronic device are shown. Selected DUT, LM324 is popular operational amplifier for electrical circuits in vehicles.

An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

Science.gov (United States)

Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

1991-01-01

Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

The Maplin electronic circuits handbook

CERN Document Server

Tooley, Michael

1990-01-01

The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

Developing a Domain Model for Relay Circuits

DEFF Research Database (Denmark)

Haxthausen, Anne Elisabeth

2009-01-01

In this paper we stepwise develop a domain model for relay circuits as used in railway control systems. First we provide an abstract, property-oriented model of networks consisting of components that can be glued together with connectors. This model is strongly inspired by a network model...... for railways madeby Bjørner et.al., however our model is more general: the components can be of any kind and can later be refined to e.g. railway components or circuit components. Then we show how the abstract network model can be refined into an explicit model for relay circuits. The circuit model describes...... the statics as well as the dynamics of relay circuits, i.e. how a relay circuit can be composed legally from electrical components as well as how the components may change state over time. Finally the circuit model is transformed into an executable model, and we show how a concrete circuit can be defined...

Radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

Derbenwick, G.F.; Hughes, R.C.

1977-01-01

Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

Dimensioning of optimal probe circuits for the non-destructive testing of materials by eddy-current using Buschbeck-Meinke chart

International Nuclear Information System (INIS)

Ott, A.

1982-01-01

By application of a modified form of the Buschbeck-Meinke-diagram, known from conduction theory, easy-to use dimensioning rules can be given for the probe circuits of single-frequency eddy-current test instruments. Dimensioning is found for circuits that work with amplitude or phase measurements, that suppress optimal the disturbance parameters in certain regions. In a similar way one can determine dimensioning, with which the measurement quantity causes the highest possible signal charge. (orig.) [de

Crossed SMPS MOSFET-based protection circuit for high frequency ultrasound transceivers and transducers.

Science.gov (United States)

Choi, Hojong; Shung, K Kirk

2014-06-12

The ultrasonic transducer is one of the core components of ultrasound systems, and the transducer's sensitivity is significantly related the loss of electronic components such as the transmitter, receiver, and protection circuit. In an ultrasonic device, protection circuits are commonly used to isolate the electrical noise between an ultrasound transmitter and transducer and to minimize unwanted discharged pulses in order to protect the ultrasound receiver. However, the performance of the protection circuit and transceiver obviously degrade as the operating frequency or voltage increases. We therefore developed a crossed SMPS (Switching Mode Power Supply) MOSFET-based protection circuit in order to maximize the sensitivity of high frequency transducers in ultrasound systems.The high frequency pulse signals need to trigger the transducer, and high frequency pulse signals must be received by the transducer. We therefore selected the SMPS MOSFET, which is the main component of the protection circuit, to minimize the loss in high frequency operation. The crossed configuration of the protection circuit can drive balanced bipolar high voltage signals from the pulser and transfer the balanced low voltage echo signals from the transducer. The equivalent circuit models of the SMPS MOSFET-based protection circuit are shown in order to select the proper device components. The schematic diagram and operation mechanism of the protection circuit is provided to show how the protection circuit is constructed. The P-Spice circuit simulation was also performed in order to estimate the performance of the crossed MOSFET-based protection circuit. We compared the performance of our crossed SMPS MOSFET-based protection circuit with a commercial diode-based protection circuit. At 60 MHz, our expander and limiter circuits have lower insertion loss than the commercial diode-based circuits. The pulse-echo test is typical method to evaluate the sensitivity of ultrasonic transducers

Analog Circuit Design Optimization Based on Evolutionary Algorithms

Directory of Open Access Journals (Sweden)

Mansour Barari

2014-01-01

Full Text Available This paper investigates an evolutionary-based designing system for automated sizing of analog integrated circuits (ICs. Two evolutionary algorithms, genetic algorithm and PSO (Parswal particle swarm optimization algorithm, are proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through specific electrical simulation, to the optimization system in the MATLAB environment, for the selected topology. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met. Comparisons with available methods like genetic algorithms show that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.

F-Paris: integrated electronic circuits [Tender

CERN Multimedia

2003-01-01

"Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods

Directory of Open Access Journals (Sweden)

Hai Au Huynh

2015-01-01

Full Text Available Direct power injection (DPI and bulk current injection (BCI methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC. The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.

Calorimeter Preamplifier Hybrid Circuit Test Jig

Energy Technology Data Exchange (ETDEWEB)

Abraham, B.M.; /Fermilab

1999-04-19

There are two ways in which the testing may be initiated, remotely or locally. If the remote operation is desired, an external TTL level signal must be provided to the test jig with the remotellocal switch on the side of the test jig switched to remote. A logic high will initiate the test. A logic low will terminate the test. In the event that an external signal is connected to the test jig while local operation occurs, the local control takes precedence over remote control. Once a DVT has been locked in the ZIF socket and the DIP switches are selected, the Push-to-Test button may be depressed. Momentarily depressing the button will initiate a test with a minimum 400 ms duration. At the same time a PBCLOCK and PBLATCH pulses will be initiated and the power rails +12V, +8V, and -6V will be ramped to full voltage. The time at which the power rails reach the full voltage is about 13 ms and it is synchronized with bypass capacitors placed on COMP input of U20 and U22 and on the output of U23 voltage regulators. The voltage rails are supplied to a {+-}10% window comparator. A red LED indicates the rail is below or above 10% of the design value. A green LED indicates the rail is within acceptable limits. For DDT with a 5 pF and 10 pF feed back capacitor, the +12V and +8V rails are current-regulated to 19rnA and 22 rnA respectively and the -6V rail is short-circuit protected within the regulator. For DUT with a 22 pF feed back capacitor the current regulation is the same as above except that the +8V rail is current regulated to 43 rnA. The power rails are supplied to the DUT via a 10 {Omega} resistor. The voltage drop across this resistor is sensed by a differential amplifier AD620 and amplified by a gain of 10. An external BNC connection is provided from this point to allow for current measurements by the vendor. The current value for each rail is calculated by measuring the voltage value at this point and divided by (10*10{Omega}). The next stage inverts and amplifies

Calorimeter Preamplifier Hybrid Circuit Test Jig

International Nuclear Information System (INIS)

Abraham, B.M.

1999-01-01

There are two ways in which the testing may be initiated, remotely or locally. If the remote operation is desired, an external TTL level signal must be provided to the test jig with the remotellocal switch on the side of the test jig switched to remote. A logic high will initiate the test. A logic low will terminate the test. In the event that an external signal is connected to the test jig while local operation occurs, the local control takes precedence over remote control. Once a DVT has been locked in the ZIF socket and the DIP switches are selected, the Push-to-Test button may be depressed. Momentarily depressing the button will initiate a test with a minimum 400 ms duration. At the same time a PBCLOCK and PBLATCH pulses will be initiated and the power rails +12V, +8V, and -6V will be ramped to full voltage. The time at which the power rails reach the full voltage is about 13 ms and it is synchronized with bypass capacitors placed on COMP input of U20 and U22 and on the output of U23 voltage regulators. The voltage rails are supplied to a ±10% window comparator. A red LED indicates the rail is below or above 10% of the design value. A green LED indicates the rail is within acceptable limits. For DDT with a 5 pF and 10 pF feed back capacitor, the +12V and +8V rails are current-regulated to 19rnA and 22 rnA respectively and the -6V rail is short-circuit protected within the regulator. For DUT with a 22 pF feed back capacitor the current regulation is the same as above except that the +8V rail is current regulated to 43 rnA. The power rails are supplied to the DUT via a 10 (Omega) resistor. The voltage drop across this resistor is sensed by a differential amplifier AD620 and amplified by a gain of 10. An external BNC connection is provided from this point to allow for current measurements by the vendor. The current value for each rail is calculated by measuring the voltage value at this point and divided by (10*10(Omega)). The next stage inverts and amplifies the

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built

Energy-efficient neuron, synapse and STDP integrated circuits.

Science.gov (United States)

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

30 CFR 56.6402 - Deenergized circuits near detonators.

Science.gov (United States)

2010-07-01

... Electric Blasting § 56.6402 Deenergized circuits near detonators. Electrical distribution circuits within 50 feet of electric detonators at the blast site shall be deenergized. Such circuits need not be deenergized between 25 to 50 feet of the electric detonators if stray current tests, conducted as frequently...

30 CFR 57.6402 - Deenergized circuits near detonators.

Science.gov (United States)

2010-07-01

... Electric Blasting-Surface and Underground § 57.6402 Deenergized circuits near detonators. Electrical distribution circuits within 50 feet of electric detonators at the blast site shall be deenergized. Such circuits need not be deenergized between 25 to 50 feet of the electric detonators if stray current tests...

Experimental study on short-circuit characteristics of the new protection circuit of insulated gate bipolar transistor

International Nuclear Information System (INIS)

Ji, In-Hwan; Choi, Young-Hwan; Ha, Min-Woo; Han, Min-Koo; Choi, Yearn-Ik

2006-01-01

A new protection circuit employing the collector to emitter voltage (V CE ) sensing scheme for short-circuit withstanding capability of the insulated gate bipolar transistor (IGBT) is proposed and verified by experimental results. Because the current path between the gate and collector can be successfully eliminated in the proposed protection circuit, the power consumption can be reduced and the gate input impedance can be increased. Previous study is limited to dc characteristics. However, experimental results show that the proposed protection circuit successfully reduces the over-current of main IGBT by 80.4% under the short-circuit condition

Analog front end circuit design of CSNS beam loss monitor system

International Nuclear Information System (INIS)

Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

2013-01-01

The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

Design and testing of a low impedance transceiver circuit for nitrogen-14 nuclear quadrupole resonance.

Science.gov (United States)

Sato-Akaba, Hideo

2014-01-01

A low impedance transceiver circuit consisting of a transmit-receive switch circuit, a class-D amplifier and a transimpedance amplifier (TIA) was newly designed and tested for a nitrogen-14 NQR. An NQR signal at 1.37MHz from imidazole was successfully observed with the dead time of ~85µs under the high Q transmission (Q~120) and reception (Q~140). The noise performance of the low impedance TIA with an NQR probe was comparable with a commercial low noise 50Ω amplifier (voltage input noise: 0.25 nV/Hz) which was also connected to the probe. The protection voltage for the pre-amplifier using the low impedance transceiver was ~10 times smaller than that for the pre-amplifier using a 50Ω conventional transceiver, which is suitable for NQR remote sensing applications. Copyright © 2014 Elsevier Inc. All rights reserved.

Commutation circuit for an HVDC circuit breaker

Science.gov (United States)

Premerlani, William J.

1981-01-01

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

Short-circuit experiments on a high Tc-superconducting cable conductor

DEFF Research Database (Denmark)

Tønnesen, Ole; Jensen, E.H.; Traholt, C.

2002-01-01

A high temperature superconductor (HTS) cable conductor (CC) with a critical current of 2.1 kA was tested over a range of short-circuit currents up to 20 kA. The duration of the short-circuit currents is 1 s. Between each short-circuit test the critical current of the HTS CC was measured in order...

The Automated DC Parameter Testing of GaAs MESFETs Using the Singer Automatic Integrated Circuit Test System.

Science.gov (United States)

1980-09-01

USING THE SINGER AUTOMATIC INTEGRATED CIRCUIT TEST SYSTEM, THOMAS L. HARPER AFIT/EE/GE/80- 7 Ist LT USAF -- -- - - __ AFIT/EE/GE/80-7 THE AUTOMATED DC...THOMAS L. HARPER ist Lt USAF Graduate Electrical Engineering September 1980 it’ Codes A _ _ _ J PREFACE This report is in support of the ongoing effort in...8217.-- I *t -1 ,p - tUel-, ir. ( /.s , j Yf) L) b ..... l P i:. +’ ,T i~: ",,’+l l L V i i ,’b : O Iil r, P V 47 C’+t ( ’ I ViH 47 V ’L 4 £, ,.;l 1 , h

Development of data acquisition system for test circuit for the Thermo-Hydraulic Laboratory of CDTN; Desenvolvimento de sistema de aquisicao de dados para circuito de testes do Laboratorio de Termo-Hidraulica do CDTN

Energy Technology Data Exchange (ETDEWEB)

Corrade, Thales Jose Rodrigues; Mesquita, Amir Zacarias; Santos, Andre Augusto Campagnole dos, E-mail: thalescorrade@hotmail.com, E-mail: amir@cdtn.br, E-mail: aacs@cdtn.br [Centro de Desenvolvimento da Tecnologia Nuclear (CDTN/CNEN-MG), Belo Horizonte, MG (Brazil). Servico de Tecnologia de Reatores

2013-07-01

The Circuit Water-Air (CWA), present in the Laboratorio de Termo-Hidraulica of the Centro de Desenvolvimento da Tecnologia Nuclear/Comissao Nacional de Energia Nuclear (CDTN / CNEN), has been used to evaluate devices present in nuclear fuel elements of a PWR (Pressurized Water Reactor). Currently, a segment of 5x5 beam simulators grids with spacer bars is being tested, serving one of the activities under the Project FUJB / FINEP / INB - 'Development of New Generation of Nuclear Fuel Element '. For the measurements of pressure drop along this beam, a system of data acquisition based on Basic language was created. Although this system is efficient and robust, their resources are very limited. Therefore, it was decided to use the software LabVIEW® implementing a more versatile and modern system. This article describes the new data acquisition system, and presents some results. The main parameters are monitored: temperature, density, dynamic viscosity, Reynolds number. The values of standard deviation, mean and uncertainty of an arbitrary channel are calculated. The system was installed and tested in the circuit under experimental conditions and showed satisfactory results.

A novel readout integrated circuit for ferroelectric FPA detector

Science.gov (United States)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Oscillator circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

Measuring circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

Development of electron beam deflection circuit

International Nuclear Information System (INIS)

Leo Kwee Wah; Lojius Lombigit; Abu Bakar Ghazali; Azaman

2007-01-01

This paper describes a development of a power supply circuit to deflect and move the electron beam across the window of the Baby electron beam machine. It comprises a discussion of circuit design, its assembly and the test results. A variety of input and output conditions have been tested and it was found that the design is capable to supply 1.0 A with 50Hz on X-axis coil and 0.4A with 500Hz on Y-axis coil. (Author)

Migraine patients consistently show abnormal vestibular bedside tests.

Science.gov (United States)

Maranhão, Eliana Teixeira; Maranhão-Filho, Péricles; Luiz, Ronir Raggio; Vincent, Maurice Borges

2016-01-01

Migraine and vertigo are common disorders, with lifetime prevalences of 16% and 7% respectively, and co-morbidity around 3.2%. Vestibular syndromes and dizziness occur more frequently in migraine patients. We investigated bedside clinical signs indicative of vestibular dysfunction in migraineurs. To test the hypothesis that vestibulo-ocular reflex, vestibulo-spinal reflex and fall risk (FR) responses as measured by 14 bedside tests are abnormal in migraineurs without vertigo, as compared with controls. Cross-sectional study including sixty individuals - thirty migraineurs, 25 women, 19-60 y-o; and 30 gender/age healthy paired controls. Migraineurs showed a tendency to perform worse in almost all tests, albeit only the Romberg tandem test was statistically different from controls. A combination of four abnormal tests better discriminated the two groups (93.3% specificity). Migraine patients consistently showed abnormal vestibular bedside tests when compared with controls.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

Science.gov (United States)

Spry, David; Neudeck, Phil; Chen, Liangyu; Chang, Carl; Lukco, Dorothy; Beheim, Glenn M

2016-01-01

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

Induced over voltage test on transformers using enhanced Z-source inverter based circuit

Science.gov (United States)

Peter, Geno; Sherine, Anli

2017-09-01

The normal life of a transformer is well above 25 years. The economical operation of the distribution system has its roots in the equipments being used. The economy being such, that it is financially advantageous to replace transformers with more than 15 years of service in the second perennial market. Testing of transformer is required, as its an indication of the extent to which a transformer can comply with the customers specified requirements and the respective standards (IEC 60076-3). In this paper, induced over voltage testing on transformers using enhanced Z source inverter is discussed. Power electronic circuits are now essential for a whole array of industrial electronic products. The bulky motor generator set, which is used to generate the required frequency to conduct the induced over voltage testing of transformers is nowadays replaced by static frequency converter. First conventional Z-source inverter, and second an enhanced Z source inverter is being used to generate the required voltage and frequency to test the transformer for induced over voltage test, and its characteristics is analysed.

The design of charge measurement circuit of MWPC

International Nuclear Information System (INIS)

Guan Xiaolei; Xiang Haisheng; Sheng Huayi; Zhao Yubin; Zhao Pingping; Zhang Hongyu; Jiang Xiaoshan; Zhao Jingwei; Zhao Dongxu

2010-01-01

It introduces the design of charge measurement (MQ) circuit of MWPC, including how MQ works in the whole MWPC readout electronic system, the architecture of MQ circuit, and the logic and algorithm design of FPGA. MQ circuit can also be applied to readout systems for other detectors. The test results in different working modes are provided. (authors)

Circuit bridging of components by smoke

International Nuclear Information System (INIS)

Tanaka, T.J.; Nowlen, S.P.; Anderson, D.J.

1996-10-01

Smoke can adversely affect digital electronics; in the short term, it can lead to circuit bridging and in the long term to corrosion of metal parts. This report is a summary of the work to date and component-level tests by Sandia National Laboratories for the Nuclear Regulatory Commission to determine the impact of smoke on digital instrumentation and control equipment. The component tests focused on short-term effects such as circuit bridging in typical components and the factors that can influence how much the smoke will affect them. These factors include the component technology and packaging, physical board protection, and environmental conditions such as the amount of smoke, temperature of burn, and humidity level. The likelihood of circuit bridging was tested by measuring leakage currents and converting those currents to resistance in ohms. Hermetically sealed ceramic packages were more resistant to smoke than plastic packages. Coating the boards with an acrylic spray provided some protection against circuit bridging. The smoke generation factors that affect the resistance the most are humidity, fuel level, and burn temperature. The use of CO 2 as a fire suppressant, the presence of galvanic metal, and the presence of PVC did not significantly affect the outcome of these results

Life testing of a low voltage air circuit breaker

International Nuclear Information System (INIS)

Subudhi, M.; Aggarwal, S.

1992-01-01

A DS-416 low voltage air circuit breaker manufactured by Westinghouse was mechanically cycled to identify age-related degradation in the various breaker subcomponents, specifically the power-operated mechanism. This accelerated aging test was performed on one breaker unit for over 36,000 cycles. Three separate pole shafts, one with a 60-degree weld, one with a 120-degree weld, and one with a 180-degree weld in the third pole lever were used to characterize cracking in the welds. In addition, during the testing three different operating mechanisms and several other parts were replaced as they became inoperable. Among the seven welds on the pole shaft, number-sign 1 and number-sign 3 were found to be critical ones whose fracture can result in misalignment of the pole levers. This can lead to problems with the operating mechanism, including the burning of coils, excessive wear in certain parts, and overstressed linkages. Furthermore, the limiting service life of a number of subcomponents of the power-operated mechanism, including the operating mechanism itself, were assessed. Based on these findings, suggestions are provided to alleviate the age-related degradation that could occur as a result of normal closing and opening of the breaker contacts during its service life. Also, cause and effect analyses of various age-related degradation in various breaker parts are discussed

Migraine patients consistently show abnormal vestibular bedside tests

Directory of Open Access Journals (Sweden)

Eliana Teixeira Maranhão

2015-01-01

Full Text Available Migraine and vertigo are common disorders, with lifetime prevalences of 16% and 7% respectively, and co-morbidity around 3.2%. Vestibular syndromes and dizziness occur more frequently in migraine patients. We investigated bedside clinical signs indicative of vestibular dysfunction in migraineurs.Objective To test the hypothesis that vestibulo-ocular reflex, vestibulo-spinal reflex and fall risk (FR responses as measured by 14 bedside tests are abnormal in migraineurs without vertigo, as compared with controls.Method Cross-sectional study including sixty individuals – thirty migraineurs, 25 women, 19-60 y-o; and 30 gender/age healthy paired controls.Results Migraineurs showed a tendency to perform worse in almost all tests, albeit only the Romberg tandem test was statistically different from controls. A combination of four abnormal tests better discriminated the two groups (93.3% specificity.Conclusion Migraine patients consistently showed abnormal vestibular bedside tests when compared with controls.

Resonance circuits for adiabatic circuits

Directory of Open Access Journals (Sweden)

C. Schlachta

2003-01-01

Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

Logic circuits from zero forcing.

Science.gov (United States)

Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

Improved equivalent circuit for twin slot terahertz receivers

Science.gov (United States)

McGrath, W. R.

2002-01-01

Series-fed coplanar waveguide embedding circuits are being developed for terahertz mixers using, in particular, submicron-sized superconducting devices, such as hot electron bolometers as the nonlinear element. Although these mixers show promising performance, they usually also show a considerable downward shift in the center frequency, when compared with simulations obtained by using simplified models. This makes it very difficult to design low-noise mixers for a given THz frequency. This shiftis principally caused by parasitics due to the extremely small details (in terms of wavelength) of the device, and by the electrical properties of the RF choke filter in the DC/IF line. In this paper, we present an improved equivalent network model of such mixer circuits which agrees with measured results at THz frequencies and we propose a new set of THz bolometric mixers that have been fabricated and are currently being tested.

Testing of SF6- and vacuum generator circuit breakers

NARCIS (Netherlands)

Smeets, R.P.P.; Paske, te L.H.

2011-01-01

Generator circuit breakers differ in various aspects from standard distribution breakers. One of the main differences is in the electrical stresses during fault current interruption. This situation will be discussed in the present contribution, along with the standardization status and the

Graphene radio frequency receiver integrated circuit.

Science.gov (United States)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Short-circuit testing of monofilar Bi-2212 coils connected in series and in parallel

International Nuclear Information System (INIS)

Polasek, A; Dias, R; Serra, E T; Filho, O O; Niedu, D

2010-01-01

Superconducting Fault Current Limiters (SCFCL's) are one of the most promising technologies for fault current limitation. In the present work, resistive SCFCL components based on Bi-2212 monofilar coils are subjected to short-circuit testing. These SCFCL components can be easily connected in series and/or in parallel by using joints and clamps. This allows a considerable flexibility to developing larger SCFCL devices, since the configuration and size of the whole device can be easily adapted to the operational conditions. The single components presented critical current (Ic) values of 240-260 A, at 77 K. Short-circuits during 40-120 ms were applied. A single component can withstand a voltage drop of 126-252 V (0.3-0.6 V/cm). Components connected in series withstand higher voltage levels, whereas parallel connection allows higher rated currents during normal operation, but the limited current is also higher. Prospective currents as high as 10-40 kA (peak value) were limited to 3-9 kA (peak value) in the first half cycle.

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Science.gov (United States)

Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris

2000-01-01

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency

BACTERIAL COLONY GROWTH IN THE VENTILATOR CIRCUIT OF THE INTENSIVE OBSERVATION UNIT AT RSUD DR. SOETOMO SURABAYA

Directory of Open Access Journals (Sweden)

Fajar Perdhana

2016-09-01

Full Text Available Ventilator-associated pneumonia (VAP remains a problem with the highest cos, morbidity and mortalityt in the Intensive Care Unit (ICU. The correlation between mechanical ventilation and pneumonia is considered as common sense, yet scientific evidence to support this statement is still needed. This research aims to analyze the bacterial colony grows in mechanical ventilation circuit and those grew in the patient’s sputum culture. We performed an observational study. Samples for bacterial culture were taken from ventilator circuit and patient sputum on Day-0, Day-3 and Day-7. Sputum samplings are collected using double catheter tracheal aspiration technique; Results are then analyzed with Chi-square test. While the similarity of bacteria species in ventilator circuit to patient’s sputum is analyzed with Binomial test. Two samples are dropped out immediately due to the rate of bacterial growth on Day-0. Bacterial colony growth in ventilator circuit shows a significant difference on Day-3 and Day-7 at 50% and 92% respectively (p = 0.05. A comparison for the bacterial similarity of the ventilator circuit and patient’s sputum shows that the bacterial growth on Day-3 is 7 out of 14 (50% and 3 with more than 105 CFU/ml colony; while on Day-7, there are 13 out of 14 positive bacterial growth, both in the circuit and the patient’s sputum. Among them, 5 out of 14 (35% of the bacterial colony which grow in the circuit have the same species as those grow in patient’s sputum. The recent study shows that there is bacteria colony growth in the ventilator circuit after Day-3 and a significant increase on Day-7. Almost half of the colony illustrates similar species from both ventilator circuit and patient’s sputum. This suggests that the bacterial growth on Day-7 in the ventilator circuit might be related to those growth in patient’s sputum.

Silicon integrated circuit process

International Nuclear Information System (INIS)

Lee, Jong Duck

1985-12-01

This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

Silicon integrated circuit process

Energy Technology Data Exchange (ETDEWEB)

Lee, Jong Duck

1985-12-15

This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

Variational integrators for electric circuits

International Nuclear Information System (INIS)

Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

2013-01-01

In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

Project Circuits in a Basic Electric Circuits Course

Science.gov (United States)

Becker, James P.; Plumb, Carolyn; Revia, Richard A.

2014-01-01

The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

Single-event effects in analog and mixed-signal integrated circuits

International Nuclear Information System (INIS)

Turflinger, T.L.

1996-01-01

Analog and mixed-signal integrated circuits are also susceptible to single-event effects, but they have rarely been tested. Analog circuit single-particle transients require modified test techniques and data analysis. Existing work is reviewed and future concerns are outlined

High-Temperature Test of 800HT Printed Circuit Heat Exchanger in HELP

International Nuclear Information System (INIS)

Kim, Chan Soo; Hong, Sung-Deok; Kim, Min Hwan; Shim, Jaesool

2014-01-01

Korea Atomic Energy Research Institute has developed high-temperature Printed Circuit Heat Exchangers (PCHE) for a Very High Temperature gas-cooled Reactor and operated a very high temperature Helium Experimental LooP (HELP) to verify the performance of the high temperature heat exchanger at the component level environment. PCHE is one of the candidates for the intermediate heat exchanger in a VHTR, because its design temperature and pressure are larger than any other compact heat exchanger types. High temperature PCHEs in HELP consist of an alloy617 PCHE and an 800HT PCHE. This study presents the high temperature test of an 800HT PCHE in HELP. The experimental data include the pressure drops, the overall heat transfer coefficients, and the surface temperature distributions under various operating conditions. The experimental data are compared with the thermo-hydraulic analysis from COMSOL. In addition, the single channel tests are performed to quantify the friction factor under normal nitrogen and helium inlet conditions. (author)

SUPER-CAPACITOR APPLICATION IN ELECTRICAL POWER CABLE TESTING FACILITIES IN THERMAL ENDURANCE AND MECHANICAL BRACING TESTS

Directory of Open Access Journals (Sweden)

I. V. Oleksyuk

2015-01-01

Full Text Available The current-carrying cores of the electrical power cables should be resistant to effects of short-circuit currents whose values depend on the material of the core, its cross-sectional area, cable insulation properties, environment temperature, and the duration of the short-circuit current flow (1 and 3–4 sec. when tested for thermal endurance and mechanical bracing. The facilities for testing the 10 kV aluminum core cables with short-circuit current shall provide mechanical-bracing current 56,82 kA and thermal endurance current 11,16 kA. Although capacitors provide such values of the testing currents to the best advantage, utilizing conventional capacitor-units will involve large expenditures for erecting and  running a separate building. It is expedient to apply super-capacitors qua the electric power supply for testing facilities, as they are capacitors with double-electrical layer and involve the current values of tens of kilo-amperes.The insulation voltage during short-circuit current testing being not-standardized, it is not banned to apply voltages less than 10 kV when performing short-circuit thermal endurance and mechanical bracing tests for electrical power cables of 10 kV. The super-capacitor voltage variation-in-time graph consists of two regions: capacitive and resistive. The capacitive part corresponds to the voltage change consequent on the energy change in the super-capacitors. The resistive part shows the voltage variation due to the active resistance presence in the super-capacitor.The author offers the algorithm determining the number of super capacitors requisite for testing 10 kV-electrical power cables with short-circuit currents for thermal endurance and mechanical bracing. The paper shows that installation of super-capacitors in the facilities testing the cables with short-circuit currents reduces the area needed for the super-capacitors in comparison with conventional capacitors more than by one order of magnitude.

FUZZY NEURAL NETWORK FOR OBJECT IDENTIFICATION ON INTEGRATED CIRCUIT LAYOUTS

Directory of Open Access Journals (Sweden)

A. A. Doudkin

2015-01-01

Full Text Available Fuzzy neural network model based on neocognitron is proposed to identify layout objects on images of topological layers of integrated circuits. Testing of the model on images of real chip layouts was showed a highеr degree of identification of the proposed neural network in comparison to base neocognitron.

Research on laser detonation pulse circuit with low-power based on super capacitor

Science.gov (United States)

Wang, Hao-yu; Hong, Jin; He, Aifeng; Jing, Bo; Cao, Chun-qiang; Ma, Yue; Chu, En-yi; Hu, Ya-dong

2018-03-01

According to the demand of laser initiating device miniaturization and low power consumption of weapon system, research on the low power pulse laser detonation circuit with super capacitor. Established a dynamic model of laser output based on super capacitance storage capacity, discharge voltage and programmable output pulse width. The output performance of the super capacitor under different energy storage capacity and discharge voltage is obtained by simulation. The experimental test system was set up, and the laser diode of low power pulsed laser detonation circuit was tested and the laser output waveform of laser diode in different energy storage capacity and discharge voltage was collected. Experiments show that low power pulse laser detonation based on super capacitor energy storage circuit discharge with high efficiency, good transient performance, for a low power consumption requirement, for laser detonation system and low power consumption and provide reference light miniaturization of engineering practice.

Exploration and design of smart home circuit based on ZigBee

Science.gov (United States)

Luo, Huirong

2018-05-01

To apply ZigBee technique in smart home circuit design, in the hardware design link of ZigBee node, TI Company's ZigBee wireless communication chip CC2530 was used to complete the design of ZigBee RF module circuit and peripheral circuit. In addition, the function demand and the overall scheme of the intelligent system based on smart home furnishing were proposed. Finally, the smart home system was built by combining ZigBee network and intelligent gateway. The function realization, reliability and power consumption of ZigBee network were tested. The results showed that ZigBee technology was applied to smart home system, making it have some advantages in terms of flexibility, scalability, power consumption and indoor aesthetics. To sum up, the system has high application value.

Novel technique for reliability testing of silicon integrated circuits

NARCIS (Netherlands)

Le Minh, P.; Wallinga, Hans; Woerlee, P.H.; van den Berg, Albert; Holleman, J.

2001-01-01

We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon

Study of recursive model for pole-zero cancellation circuit

International Nuclear Information System (INIS)

Zhou Jianbin; Zhou Wei; Hong Xu; Hu Yunchuan; Wan Xinfeng; Du Xin; Wang Renbo

2014-01-01

The output of charge sensitive amplifier (CSA) is a negative exponential signal with long decay time which will result in undershoot after C-R differentiator. Pole-zero cancellation (PZC) circuit is often applied to eliminate undershoot in many radiation detectors. However, it is difficult to use a zero created by PZC circuit to cancel a pole in CSA output signal accurately because of the influences of electronic components inherent error and environmental factors. A novel recursive model for PZC circuit is presented based on Kirchhoff's Current Law (KCL) in this paper. The model is established by numerical differentiation algorithm between the input and the output signal. Some simulation experiments for a negative exponential signal are carried out using Visual Basic for Application (VBA) program and a real x-ray signal is also tested. Simulated results show that the recursive model can reduce the time constant of input signal and eliminate undershoot. (authors)

A Method for Automatic Inspection of Printed Circuit Boards by Using the Thermal Signature

International Nuclear Information System (INIS)

Amer, H.H.; Zekry, A.A.; Elaraby, S.; Ghareeb, K.E.

2012-01-01

This paper aims to design a system for automating inspection of the printed circuit boards (PCBs) by using the thermal signature of the different integrated circuits (I.C). The proposed inspection system consists of the inspection circuit, data acquisition system (DAS) and personal computer. Inspection is done by comparing the thermal signature of normally operated circuit with the thermal signature of circuit under test. One thermistor is assigned to each component in the circuit. The thermistor must touch tightly the surface of the I.C. to sense its temperature during the inspection process. Matlab software is used to represent the thermal signature through different colors. The Turbo C software is used to develop a program for acquiring and comparing the thermal signature of the circuit under the test with the reference circuit. If the colors of the two thermal signatures for the same I.C. are same then the circuit under test is fault free and does not contain any defect. On the other side, if the colors of the two thermal signatures for the same I.C. are different then the circuit under test is defective

A chopper circuit for energy transfer between superconducting magnets

International Nuclear Information System (INIS)

Onishi, Toshitada; Tateishi, Hiroshi; Takeda, Masatoshi; Matsuura, Toshiaki; Nakatani, Toshio.

1986-01-01

It has been suggested that superconducting magnets could provide a medium for storing energy and supplying the large energy pulses needed by experimental nuclear-fusion equipment and similar loads. Based on this concept, tests on energy transfer between superconducting magnets are currently being conducted at the Agency of Industrial Science and Technology's Electrotechnical Laboratory. Mitsubishi Electric has pioneered the world's first chopper circuit for this application. The circuit has the advantages of being simple and permitting high-speed, bipolar energy transfer. The article describes this circuit and its testing. (author)

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Science.gov (United States)

Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

2000-01-01

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

A new approach of optimization procedure for superconducting integrated circuits

International Nuclear Information System (INIS)

Saitoh, K.; Soutome, Y.; Tarutani, Y.; Takagi, K.

1999-01-01

We have developed and tested a new circuit simulation procedure for superconducting integrated circuits which can be used to optimize circuit parameters. This method reveals a stable operation region in the circuit parameter space in connection with the global bias margin by means of a contour plot of the global bias margin versus the circuit parameters. An optimal set of parameters with margins larger than these of the initial values has been found in the stable region. (author)

First-year university Physics students’ knowledge about direct current circuits: probing improvement in understanding as a function of teaching and learning interventions

Science.gov (United States)

Newman, Richard; van der Ventel, Brandon; Hanekom, Crischelle

2017-07-01

post-test. The students’ average score on the post-test was found to be ~25% higher than their pre-test score. The results of the iPad use survey show that the majority of students felt that the iCircuit app enhanced their learning of DC circuits.

Internal short circuit and accelerated rate calorimetry tests of lithium-ion cells: Considerations for methane-air intrinsic safety and explosion proof/flameproof protection methods.

Science.gov (United States)

Dubaniewicz, Thomas H; DuCarme, Joseph P

2016-09-01

Researchers with the National Institute for Occupational Safety and Health (NIOSH) studied the potential for lithium-ion cell thermal runaway from an internal short circuit in equipment for use in underground coal mines. In this third phase of the study, researchers compared plastic wedge crush-induced internal short circuit tests of selected lithium-ion cells within methane (CH 4 )-air mixtures with accelerated rate calorimetry tests of similar cells. Plastic wedge crush test results with metal oxide lithium-ion cells extracted from intrinsically safe evaluated equipment were mixed, with one cell model igniting the chamber atmosphere while another cell model did not. The two cells models exhibited different internal short circuit behaviors. A lithium iron phosphate (LiFePO 4 ) cell model was tolerant to crush-induced internal short circuits within CH 4 -air, tested under manufacturer recommended charging conditions. Accelerating rate calorimetry tests with similar cells within a nitrogen purged 353-mL chamber produced ignitions that exceeded explosion proof and flameproof enclosure minimum internal pressure design criteria. Ignition pressures within a 20-L chamber with 6.5% CH 4 -air were relatively low, with much larger head space volume and less adiabatic test conditions. The literature indicates that sizeable lithium thionyl chloride (LiSOCl 2 ) primary (non rechargeable) cell ignitions can be especially violent and toxic. Because ignition of an explosive atmosphere is expected within explosion proof or flameproof enclosures, there is a need to consider the potential for an internal explosive atmosphere ignition in combination with a lithium or lithium-ion battery thermal runaway process, and the resulting effects on the enclosure.

Active Match Load Circuit Intended for Testing Piezoelectric Transformers

DEFF Research Database (Denmark)

Andersen, Thomas; Rødgaard, Martin Schøler; Andersen, Michael A. E.

2012-01-01

An adjustable high voltage active load circuit for voltage amplitudes above 100 volts, especially intended for resistive matching the output impedance of a piezoelectric transformer (PT) is proposed in this paper. PTs have been around for over 50 years, were C. A. Rosen is common known for his...

Development of large-scale thyristor dc circuit breaker

International Nuclear Information System (INIS)

Kobayashi, S.; Tanoue, Y.; Ikegame, H.; Matushita, T.; Sato, Y.

1981-01-01

A study for developing a thyristor dc circuit breaker that is applicable to the Tokamak device for engineering feasibility is presented. The design and test of a unit circuit breaker consisting of 4kV-3kA thyristors connected 2 in series and 12 in parallel are described. And based on the results a 50kV-24kA thyristor dc circuit breaker is conceptually designed

The elusive memristor: properties of basic electrical circuits

Energy Technology Data Exchange (ETDEWEB)

Joglekar, Yogesh N; Wolf, Stephen J [Department of Physics, Indiana University Purdue University Indianapolis, Indianapolis, IN 46202 (United States)], E-mail: yojoglek@iupui.edu

2009-07-15

We present an introduction to and a tutorial on the properties of the recently discovered ideal circuit element, a memristor. By definition, a memristor M relates the charge q and the magnetic flux {phi} in a circuit and complements a resistor R, a capacitor C and an inductor L as an ingredient of ideal electrical circuits. The properties of these three elements and their circuits are a part of the standard curricula. The existence of the memristor as the fourth ideal circuit element was predicted in 1971 based on symmetry arguments, but was clearly experimentally demonstrated just last year. We present the properties of a single memristor, memristors in series and parallel, as well as ideal memristor-capacitor (MC), memristor-inductor (ML) and memristor-capacitor-inductor (MCL) circuits. We find that the memristor has hysteretic current-voltage characteristics. We show that the ideal MC (ML) circuit undergoes non-exponential charge (current) decay with two time scales and that by switching the polarity of the capacitor, an ideal MCL circuit can be tuned from overdamped to underdamped. We present simple models which show that these unusual properties are closely related to the memristor's internal dynamics. This tutorial complements the pedagogy of ideal circuit elements (R, C and L) and the properties of their circuits, and is aimed at undergraduate physics and electrical engineering students.

The elusive memristor: properties of basic electrical circuits

International Nuclear Information System (INIS)

Joglekar, Yogesh N; Wolf, Stephen J

2009-01-01

We present an introduction to and a tutorial on the properties of the recently discovered ideal circuit element, a memristor. By definition, a memristor M relates the charge q and the magnetic flux φ in a circuit and complements a resistor R, a capacitor C and an inductor L as an ingredient of ideal electrical circuits. The properties of these three elements and their circuits are a part of the standard curricula. The existence of the memristor as the fourth ideal circuit element was predicted in 1971 based on symmetry arguments, but was clearly experimentally demonstrated just last year. We present the properties of a single memristor, memristors in series and parallel, as well as ideal memristor-capacitor (MC), memristor-inductor (ML) and memristor-capacitor-inductor (MCL) circuits. We find that the memristor has hysteretic current-voltage characteristics. We show that the ideal MC (ML) circuit undergoes non-exponential charge (current) decay with two time scales and that by switching the polarity of the capacitor, an ideal MCL circuit can be tuned from overdamped to underdamped. We present simple models which show that these unusual properties are closely related to the memristor's internal dynamics. This tutorial complements the pedagogy of ideal circuit elements (R, C and L) and the properties of their circuits, and is aimed at undergraduate physics and electrical engineering students

The single-event effect evaluation technology for nano integrated circuits

International Nuclear Information System (INIS)

Zheng Hongchao; Zhao Yuanfu; Yue Suge; Fan Long; Du Shougang; Chen Maoxin; Yu Chunqing

2015-01-01

Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally. (paper)

Test Time Reduction for BIST by Parallel Divide-and-Conquer Method

Energy Technology Data Exchange (ETDEWEB)

Choi, Byung Gu; Kim, Dong Wook [Kwangwoon University (Korea)

2000-06-01

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C{sup ++} language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2{sup 1}51 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI. (author). 15 refs., 7 figs., 5 tabs.

Circuit bridging of digital equipment caused by smoke from a cable fire

International Nuclear Information System (INIS)

Tanaka, T.J.; Anderson, D.J.

1997-01-01

Advanced reactor systems are likely to use protection systems with digital electronics that ideally should be resistant to environmental hazards, including smoke from possible cable fires. Previous smoke tests have shown that digital safety systems can fail even at relatively low levels of smoke density and that short-term failures are likely to be caused by circuit bridging. Experiments were performed to examine these failures, with a focus on component packaging and protection schemes. Circuit bridging, which causes increased leakage currents and arcs, was gauged by measuring leakage currents among the leads of component packages. The resistance among circuit leads typically varies over a wide range, depending on the nature of the circuitry between the pins, bias conditions, circuit board material, etc. Resistance between leads can be as low as 20 kΩ and still be good, depending on the component. For these tests, the authors chose a printed circuit board and components that normally have an interlead resistance above 10 12 Ω, but if the circuit is exposed to smoke, circuit bridging causes the resistance to fall below 10 3 Ω. Plated-through-hole (PTH) and surface-mounted (SMT) packages were exposed to a series of different smoke environments using a mixture of environmentally qualified cables for fuel. Conformal coatings and enclosures were tested as circuit protection methods. High fuel levels, high humidity, and high flaming burns were the conditions most likely to cause circuit bridging. The inexpensive conformal coating that was tested - an acrylic spray - reduced leakage currents, but enclosure in a chassis with a fan did not. PTH packages were more resistant to smoke-induced circuit bridging than SMT packages. Active components failed most often in tests where the leakage currents were high, but failure did not always accompany high leakage currents

Utilization of process TEG for fabrication of HTS circuits

International Nuclear Information System (INIS)

Hato, T.; Okada, Y.; Maruyama, M.; Suzuki, H.; Wakana, H.; Adachi, S.; Kawabe, U.; Tanabe, K.

2006-01-01

We improved the fabrication process of high-temperature superconducting (HTS) sampler circuits with multilayer structures by utilizing a test elements group (TEG). Among a lot of difficulties in the HTS circuit fabrication process, loss of oxygen is one of the most significant problems. Since the film transition temperature (T c ) has a strong relationship with the resistance at room temperature, we fabricated a test pattern on the same wafer of the circuits and measured the resistance at room temperature by using a prober to estimate the T c of each layer. By introducing the measurement of the normal resistance after each process, we found better process conditions without a T c drop. Moreover, we constructed a low-temperature probing system, in which we can measure the junction TEG. The system enabled feedback of the fabrication condition soon after the junction process. The utilization of the process TEG contributed to reproducible fabrication of HTS circuits and that is a promising advance of the HTS circuit technology

Small circuits for cryptography.

Energy Technology Data Exchange (ETDEWEB)

Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

2005-10-01

This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

The short-circuit test results of 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer with fault current limiting function

International Nuclear Information System (INIS)

Tomioka, A.; Bohno, T.; Kakami, S.; Isozaki, M.; Watanabe, K.; Toyama, K.; Sugiyama, S.; Konno, M.; Gosho, Y.; Okamoto, H.; Hayashi, H.; Tsutsumi, T.; Iwakuma, M.; Saito, T.; Tanabe, K.; Shiohara, Y.

2013-01-01

Highlights: ► We manufactured the 400 kV A-class YBCO model transformer with FCL function. ► Short-circuit test was performed by applying 6.9 kV on primary side. ► The short-circuit current was limited to 174 A for a prospective current of 559 A. ► It agreed with the design and we also confirmed the I c did not degrade. ► The results suggest the possibility to design YBCO transformers with FCL function. -- Abstract: We are developing an elemental technology for 66/6.9 kV 20 MVA-class superconducting power transformer with fault current limiting function. In order to obtain the characteristics of YBCO conductor when the AC over current supplied to the conductor, the model coils were manufactured with YBCO tapes and tested. Based on these results, we manufactured the 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer with fault current limiting function and performed short-circuit test. At the 0.25 s after short-circuit, the short-circuit current of primary winding was limited to about 174 A for a prospective current of 559 A. It was consistent with the design. The I–V characteristics of the winding did not change before and after the test. We consider the model transformer to be able to withstand AC over-current with the function of current limiting. The results suggest the possibility to design YBCO superconducting transformers with fault current limiting function for practical power grid

Integrated Circuit Immunity

Science.gov (United States)

Sketoe, J. G.; Clark, Anthony

2000-01-01

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

Ultra-low power integrated circuit design circuits, systems, and applications

CERN Document Server

Li, Dongmei; Wang, Zhihua

2014-01-01

This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

Switchless charge-discharge circuit for electrical capacitance tomography

International Nuclear Information System (INIS)

Kryszyn, J; Smolik, W T; Radzik, B; Olszewski, T; Szabatin, R

2014-01-01

The main factor limiting the performance of electrical capacitance tomography (ECT) is an extremely low value of inter-electrode capacitances. The charge-discharge circuit is a well suited circuit for a small capacitance measurement due to its immunity to noise and stray capacitance, although it has a problem associated with a charge injected by the analogue switches, which results in a dc offset. This paper presents a new diode-based circuit for capacitance measurement in which a charge transfer method is realized without switches. The circuit was built and tested in one channel configuration with 16 multiplexed electrodes. The performance of the elaborated circuit and a comparison with a classic charge-discharge circuit are presented. The elaborated circuit can be used for sensors with inter-electrode capacitances not lower than 10 fF. The presented approach allows us to obtain a similar performance to the classic charge-discharge circuit, but has a simplified design. A lack of the need to synchronize the analogue switches in the transmitter and the receiver part of this circuit could be a desirable feature in the design of measurement systems integrated with electrodes. (paper)

Secondary School Students' Misconceptions about Simple Electric Circuits

Science.gov (United States)

Küçüközer, Hüseyin; Kocakülah, Sabri

2007-01-01

The aim of this study is to reveal secondary school students' misconceptions about simple electric circuits and to define whether specific misconceptions peculiar to Turkish students exist within those identified. Data were obtained with a conceptual understanding test for simple electric circuits and semi-structured interviews. Conceptual…

Compiling quantum circuits to realistic hardware architectures using temporal planners

Science.gov (United States)

Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy

2018-04-01

To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.

Electronic circuit encyclopedia 2

Energy Technology Data Exchange (ETDEWEB)

Park, Sun Ho

1992-10-15

This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

Electronic circuit encyclopedia 2

International Nuclear Information System (INIS)

Park, Sun Ho

1992-10-01

This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

Thermoacoustic and thermoreflectance imaging of biased integrated circuits: Voltage and temperature maps

Energy Technology Data Exchange (ETDEWEB)

Hernández-Rosales, E.; Cedeño, E. [Gleb Wataghin Physics Institute, University of Campinas - Unicamp, 13083-859 Campinas, SP (Brazil); Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); Hernandez-Wong, J. [Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); CONACYT, México, DF, México (Mexico); Rojas-Trigos, J. B.; Marin, E. [Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); Gandra, F. C. G.; Mansanares, A. M., E-mail: manoel@ifi.unicamp.br [Gleb Wataghin Physics Institute, University of Campinas - Unicamp, 13083-859 Campinas, SP (Brazil)

2016-07-25

In this work a combined thermoacoustic and thermoreflectance set-up was designed for imaging biased microelectronic circuits. In particular, it was used with polycrystalline silicon resistive tracks grown on a monocrystalline Si substrate mounted on a test chip. Thermoreflectance images, obtained by scanning a probe laser beam on the sample surface, clearly show the regions periodically heated by Joule effect, which are associated to the electric current distribution in the circuit. The thermoacoustic signal, detected by a pyroelectric/piezoelectric sensor beneath the chip, also discloses the Joule contribution of the whole sample. However, additional information emerges when a non-modulated laser beam is focused on the sample surface in a raster scan mode allowing imaging of the sample. The distribution of this supplementary signal is related to the voltage distribution along the circuit.

A microcontroller-based interface circuit for lossy capacitive sensors

International Nuclear Information System (INIS)

Reverter, Ferran; Casas, Òscar

2010-01-01

This paper introduces and analyses a low-cost microcontroller-based interface circuit for lossy capacitive sensors, i.e. sensors whose parasitic conductance (G x ) is not negligible. Such a circuit relies on a previous circuit also proposed by the authors, in which the sensor is directly connected to a microcontroller without using either a signal conditioner or an analogue-to-digital converter in the signal path. The novel circuit uses the same hardware, but it performs an additional measurement and executes a new calibration technique. As a result, the sensitivity of the circuit to G x decreases significantly (a factor higher than ten), but not completely due to the input capacitances of the port pins of the microcontroller. Experimental results show a relative error in the capacitance measurement below 1% for G x x ) shows the effectiveness of the circuit

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Chang, Carl W.; Lukco, Dorothy; Beheim, Glenn M.

2016-01-01

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Solid-state circuits

CERN Document Server

Pridham, G J

2013-01-01

Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

Automatic design of digital synthetic gene circuits.

Directory of Open Access Journals (Sweden)

Mario A Marchisio

2011-02-01

Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

Substrate Effects in Wideband SiGe HBT Mixer Circuits

DEFF Research Database (Denmark)

Johansen, Tom Keinicke; Vidkjær, Jens; Krozer, Viktor

2005-01-01

are also applied to predict short distance substrate coupling effects. Simulation results using extracted equivalent circuit models and substrate coupling networks are compared with experimental results obtained on a wideband mixer circuit implemented in a 0.35 μm, 60 GHz ft SiGe HBT BiCMOS process.......In this paper, the influence from substrate effects on the performance of wideband SiGe HBT mixer circuits is investigated. Equivalent circuit models including substrate networks are extracted from on-wafer test structures and compared with electromagnetic simulations. Electromagnetic simulations...

Integrated circuit design using design automation

International Nuclear Information System (INIS)

Gwyn, C.W.

1976-09-01

Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

Collective of mechatronics circuit

International Nuclear Information System (INIS)

1987-02-01

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

Collective of mechatronics circuit

Energy Technology Data Exchange (ETDEWEB)

NONE

1987-02-15

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

Universal programmable quantum circuit schemes to emulate an operator

Energy Technology Data Exchange (ETDEWEB)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)

2012-12-21

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Universal programmable quantum circuit schemes to emulate an operator

International Nuclear Information System (INIS)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre

2012-01-01

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Instrumentation for Sodium Circuits; Instrumentation des Circuits de Sodium

Energy Technology Data Exchange (ETDEWEB)

Cambillard, E. [CEA, Centre d' Etudes Nucleaires de Fontenay-aux-Roses (France); Lions, N. [CEA, Centre d' Etudes Nucleaires de Cadarache (France)

1967-06-15

Electromagnetic flow meters, level gauges and differential pressure gauges are among the main measurement instruments designed and tested at the Commissariat a l'Energie Atomique (CEA) for sodium reactors. The main characteristics of the flow meters used with RAPSODIE are indicated. The instruments used in this connection are of the permanent -magnet or electromagnet type (in the primary circuits). A description is given of the calibration methods employed - use is made of diaphragms or Venturi tubes as standard flow meters - and information is given on the results measured for maximum sodium flows of 400 m{sup 3}/h. Three types of continuous level gauge have been studied. Resistance gauge. Two varieties used for the 1 - and 10-MW test circuits of RAPSODIE are described. In one there is a compensation resistance along the whole height of the measuring element (the continuous gauges used with the RAPSODIE reactor are at present of this type). In the other type of gauge a device is incorporated to heat the measurement element and prevent the formation of conducting deposits (prototype sodium tests have been completed). Induction gauge. This type has two coupled coils and is fitted with a device to compensate for temperature effects. A description is given of a prototype which has been built and the results obtained in the course of sodium tests are described. Ultrasonic gauge. With this type, a transmitter is fitted on top of the outside of the sodium container; there is also a vertical wave guide, the bottom of which is immersed in the liquid metal and possesses a reflector system which returns the ultrasonic beam towards the surface. Fixed reference marks provide a permanent means of calibration and the whole apparatus is welded. This type of gauge is now being constructed. The differential pressure gauges that have been built, and used in particular with Venturi tube flow meters, are modified versions of the devices employed with the 1 - and 10-MW test circuits of

Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

OpenAIRE

石橋, 孝昭

2012-01-01

This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

Experimental study of natural circulation circuit

Energy Technology Data Exchange (ETDEWEB)

Lemos, Wanderley F.; Su, Jian, E-mail: wlemos@lasme.coppe.ufrj.br, E-mail: sujian@lasme.coppe.ufrj.br [Coordenacao dos Programas de Pos-Graduacao de Engenharia (LASME/COPPE/UFRJ), Rio de Janeiro, RJ (Brazil). Lab. de Simulacao e Metodos Numericos; Faccini, Jose L.H., E-mail: faccini@ien.gov.br [Instituto de Engenharia Nuclear (LTE/IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Lab. de Termo-Hidraulica Experimental

2011-07-01

This work presents an experimental study about fluid flows behavior in natural circulation, under conditions of single-phase flow. The experiment was performed through experimental thermal-hydraulic circuit built at IEN. This test equipment has performance similar to passive system of residual heat removal present in Advanced Pressurized Water Reactors (APWR). This experimental study aims to observing and analyzing the natural circulation phenomenon, using this experimental circuit that was dimensioned and built based on concepts of similarity and scale. This philosophy allows the analysis of natural circulation behavior in single-phase flow conditions proportionally to the functioning real conditions of a nuclear reactor. The experiment was performed through procedures to initialization of hydraulic feeding of primary and secondary circuits and electrical energizing of resistors installed inside heater. Power controller has availability to adjust values of electrical power to feeding resistors, in order to portray several conditions of energy decay of nuclear reactor in a steady state. Data acquisition system allows the measurement and monitoring of the evolution of the temperature in various points through thermocouples installed in strategic points along hydraulic circuit. The behavior of the natural circulation phenomenon was monitored by graphical interface on computer screen, showing the temperature evolutions of measuring points and results stored in digital spreadsheets. The results stored in digital spreadsheets allowed the getting of data to graphic construction and discussion about natural circulation phenomenon. Finally, the calculus of Reynolds number allowed the establishment for a correlation of friction in function of geometric scales of length, heights and cross section of tubing, considering a natural circulation flow throughout in the region of hot leg. (author)

Experimental study of natural circulation circuit

International Nuclear Information System (INIS)

Lemos, Wanderley F.; Su, Jian; Faccini, Jose L.H.

2011-01-01

This work presents an experimental study about fluid flows behavior in natural circulation, under conditions of single-phase flow. The experiment was performed through experimental thermal-hydraulic circuit built at IEN. This test equipment has performance similar to passive system of residual heat removal present in Advanced Pressurized Water Reactors (APWR). This experimental study aims to observing and analyzing the natural circulation phenomenon, using this experimental circuit that was dimensioned and built based on concepts of similarity and scale. This philosophy allows the analysis of natural circulation behavior in single-phase flow conditions proportionally to the functioning real conditions of a nuclear reactor. The experiment was performed through procedures to initialization of hydraulic feeding of primary and secondary circuits and electrical energizing of resistors installed inside heater. Power controller has availability to adjust values of electrical power to feeding resistors, in order to portray several conditions of energy decay of nuclear reactor in a steady state. Data acquisition system allows the measurement and monitoring of the evolution of the temperature in various points through thermocouples installed in strategic points along hydraulic circuit. The behavior of the natural circulation phenomenon was monitored by graphical interface on computer screen, showing the temperature evolutions of measuring points and results stored in digital spreadsheets. The results stored in digital spreadsheets allowed the getting of data to graphic construction and discussion about natural circulation phenomenon. Finally, the calculus of Reynolds number allowed the establishment for a correlation of friction in function of geometric scales of length, heights and cross section of tubing, considering a natural circulation flow throughout in the region of hot leg. (author)

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Circuit reliability boosted by soldering pins of disconnect plugs to sockets

Science.gov (United States)

Pierce, W. B.

1964-01-01

Where disconnect pins must be used for wiring and testing a circuit, improved system reliability is obtained by making a permanent joint between pins and sockets of the disconnect plug. After the circuit has been tested, contact points may be fused through soldering, brazing, or welding.

SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

Science.gov (United States)

Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

2010-05-01

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

Design, construction and tests of the power crowbar and predischarge circuit of the SPICA II experiment

International Nuclear Information System (INIS)

Ingen, A.M. van; Manintveld, P.; Sterk, A.B.

1983-01-01

A 28 Farad, 1.8 MJ electrolytic capacitor power-crowbar battery and a flexible predischarge circuit for the SPICA II screw-pinch experiment is described. The battery is capable of delivering the toroidal and poloidal currents of more than 2.5 MA, during at least 1 ms after crowbarring of the high-voltage capacitor banks. To obtain a low short-circuit impedance a very compact construction was chosen, which resulted in seven modules of about 1 m 3 each, Rsub(i) = 100 μΩ, Lsub(i) = 7 nH, connected by plate systems to the main circuit. The predischarge circuit consists of a fast capacitor bank to start the predischarge and a slow circuit with a clamp switch to preheat the discharge. (author)

Coplanar strips for Josephson voltage standard circuits

International Nuclear Information System (INIS)

Schubert, M.; May, T.; Wende, G.; Fritzsch, L.; Meyer, H.-G.

2001-01-01

We present a microwave circuit for Josephson voltage standards. Here, the Josephson junctions are integrated in a microwave transmission line designed as coplanar strips (CPS). The new layout offers the possibility of achieving a higher scale of integration and to considerably simplify the fabrication technology. The characteristic impedance of the CPS is about 50 Ω, and this should be of interest for programmable Josephson voltage standard circuits with SNS or SINIS junctions. To demonstrate the function of the microwave circuit design, conventional 10 V Josephson voltage standard circuits with 17000 Nb/AlO x /Nb junctions were prepared and tested. Stable Shapiro steps at the 10 V level were generated. Furthermore, arrays of 1400 SINIS junctions in this microwave layout exhibited first-order Shapiro steps. Copyright 2001 American Institute of Physics

Multiplication circuit for particle identification

International Nuclear Information System (INIS)

Gerlier, Jean

1962-01-01

After having commented some characteristics of the particles present in a cyclotron, and their interactions, this report addresses the development and the implementation of a method and a device for selecting and counting particles. The author presents the principle and existing techniques of selection. In comparison with an existing device, the proportional counter and the scintillator are replaced by junctions: a surface barrier type junction (a silicon N layer with a very thin oxygen layer playing the role of the P layer), and lithium-based junction (a silicon P type layer made intrinsic by migration of lithium). The author then describes the developed circuit and assembly (background of the choice of a multiplication circuit), and their operation. In the next part, he presents the performed tests and discuses the obtained results. He finally outlines the benefits of the herein presented circuit [fr

New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

Energy Technology Data Exchange (ETDEWEB)

Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

1983-07-01

This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

Logic-type Schmitt circuit using multi-valued gates

Science.gov (United States)

Wakui, M.; Tanaka, M.

Logic-type Schmitt circuits (LTSCs) proposed in this paper by author's proposal are a new detector for a multi-valued multi-threshold logic circuit, and it realizes the high resolution with a little hysteresis or the high noise margin. The detector consists of the combinations of the multi-valued gates (MVGs) and a positive reaction device (PRD), and each circuit can be realized by the conventional elements. This paper shows their practical circuits, and describes the regions and the conditions for their operation.

Post-irradiation effects in CMOS integrated circuits

International Nuclear Information System (INIS)

Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

1988-01-01

The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80 0 C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105 0 C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80 0 C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal

Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

Science.gov (United States)

Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

2015-01-01

Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

Design of an improved RCD buffer circuit for full bridge circuit

Science.gov (United States)

Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

2017-05-01

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

Analog circuit design designing dynamic circuit response

CERN Document Server

Feucht, Dennis

2010-01-01

This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

Modernized CDTN's air-water experimental test circuit: initial results

International Nuclear Information System (INIS)

Pessoa, Mácio A.; Sobrinho, Mauricio R. da S.; Salomão, Eduardo A.; Ferreira, Arthur F.J.; Navarro, Moysés A.; Santos, André A. Campagnole dos

2017-01-01

The Counter Current Flow Limitation (CCFL) phenomenon, specifically the control that the gas exerts in a liquid flow in the opposite direction, is of real importance in the study of design and operation of various industrial sectors, particularly the nuclear industry. In nuclear engineering, such a phenomenon can occur in a loss of coolant accident (LOCA) of a Pressurized Water Reactor (PWR) when there is the need to re-flood the reactor core during an emergency cooling process. The CCFL phenomenon is being investigated at the Nuclear Technology Development Center (CDTN) thermo-hydraulics laboratory in order to better understand the flow and its limitations and thereby contribute to the improvement of its modeling for analysis of severe accidents. For this, a series of experiments were performed in CDTN in a reduced scale acrylic test section of the 'hot leg' of a PWR. The new proposed circuit is a closed loop and no water has to be discharged during the experiment. This is only possible due to the Python program, which is associated to the data acquisition system and can interface with the automated valves through the outputs of the data acquisition board to control the experiment. The trials compare the CCFL behavior for 500mm lengths of the horizontal section, for inclined duct slope 50° for a diameter of 54mm pipe's diameter. This paper describes the new tests in comparison to tests performed in the past. (author)

Modernized CDTN's air-water experimental test circuit: initial results

Energy Technology Data Exchange (ETDEWEB)

Pessoa, Mácio A.; Sobrinho, Mauricio R. da S.; Salomão, Eduardo A.; Ferreira, Arthur F.J.; Navarro, Moysés A.; Santos, André A. Campagnole dos, E-mail: marcioaraujopessoa@gmail.com, E-mail: mauricio.sobrinho223@gmail.com, E-mail: e.a.salomao@gmail.com, E-mail: arthur1303@gmail.com, E-mail: moysesnavarro@yahoo.com.br, E-mail: aacs@cdtn.br [Centro de Desenvolvimento da Tecnologia Nuclear (CDTN/CNEN-MG), Belo Horizonte, MG (Brazil)

2017-07-01

The Counter Current Flow Limitation (CCFL) phenomenon, specifically the control that the gas exerts in a liquid flow in the opposite direction, is of real importance in the study of design and operation of various industrial sectors, particularly the nuclear industry. In nuclear engineering, such a phenomenon can occur in a loss of coolant accident (LOCA) of a Pressurized Water Reactor (PWR) when there is the need to re-flood the reactor core during an emergency cooling process. The CCFL phenomenon is being investigated at the Nuclear Technology Development Center (CDTN) thermo-hydraulics laboratory in order to better understand the flow and its limitations and thereby contribute to the improvement of its modeling for analysis of severe accidents. For this, a series of experiments were performed in CDTN in a reduced scale acrylic test section of the 'hot leg' of a PWR. The new proposed circuit is a closed loop and no water has to be discharged during the experiment. This is only possible due to the Python program, which is associated to the data acquisition system and can interface with the automated valves through the outputs of the data acquisition board to control the experiment. The trials compare the CCFL behavior for 500mm lengths of the horizontal section, for inclined duct slope 50° for a diameter of 54mm pipe's diameter. This paper describes the new tests in comparison to tests performed in the past. (author)

Design and implementation of JOM-3 Overhauser magnetometer analog circuit

Science.gov (United States)

Zhang, Xiao; Jiang, Xue; Zhao, Jianchang; Zhang, Shuang; Guo, Xin; Zhou, Tingting

2017-09-01

Overhauser magnetometer, a kind of static-magnetic measurement system based on the Overhauser effect, has been widely used in archaeological exploration, mineral resources exploration, oil and gas basin structure detection, prediction of engineering exploration environment, earthquakes and volcanic eruotions, object magnetic measurement and underground buried booty exploration. Overhauser magnetometer plays an important role in the application of magnetic field measurement for its characteristics of small size, low power consumption and high sensitivity. This paper researches the design and the application of the analog circuit of JOM-3 Overhauser magnetometer. First, the Larmor signal output by the probe is very weak. In order to obtain the signal with high signal to noise rstio(SNR), the design of pre-amplifier circuit is the key to improve the quality of the system signal. Second, in this paper, the effectual step which could improve the frequency characters of bandpass filter amplifier circuit were put forward, and theoretical analysis was made for it. Third, the shaping circuit shapes the amplified sine signal into a square wave signal which is suitable for detecting the rising edge. Fourth, this design elaborated the optimized choice of tuning circuit, so the measurement range of the magnetic field can be covered. Last, integrated analog circuit testing system was formed to detect waveform of each module. By calculating the standard deviation, the sensitivity of the improved Overhauser magnetometer is 0.047nT for Earth's magnetic field observation. Experimental results show that the new magnetometer is sensitive to earth field measurement.

Neuromolecular Imaging Shows Temporal Synchrony Patterns between Serotonin and Movement within Neuronal Motor Circuits in the Brain

Directory of Open Access Journals (Sweden)

Patricia A. Broderick

2013-06-01

Full Text Available The present discourse links the electrical and chemical properties of the brain with neurotransmitters and movement behaviors to further elucidate strategies to diagnose and treat brain disease. Neuromolecular imaging (NMI, based on electrochemical principles, is used to detect serotonin in nerve terminals (dorsal and ventral striata and somatodendrites (ventral tegmentum of reward/motor mesocorticolimbic and nigrostriatal brain circuits. Neuronal release of serotonin is detected at the same time and in the same animal, freely moving and unrestrained, while open-field behaviors are monitored via infrared photobeams. The purpose is to emphasize the unique ability of NMI and the BRODERICK PROBE® biosensors to empirically image a pattern of temporal synchrony, previously reported, for example, in Aplysia using central pattern generators (CPGs, serotonin and cerebral peptide-2. Temporal synchrony is reviewed within the context of the literature on central pattern generators, neurotransmitters and movement disorders. Specifically, temporal synchrony data are derived from studies on psychostimulant behavior with and without cocaine while at the same time and continuously, serotonin release in motor neurons within basal ganglia, is detected. The results show that temporal synchrony between the neurotransmitter, serotonin and natural movement occurs when the brain is NOT injured via, e.g., trauma, addictive drugs or psychiatric illness. In striking contrast, in the case of serotonin and cocaine-induced psychostimulant behavior, a different form of synchrony and also asynchrony can occur. Thus, the known dysfunctional movement behavior produced by cocaine may well be related to the loss of temporal synchrony, the loss of the ability to match serotonin in brain with motor activity. The empirical study of temporal synchrony patterns in humans and animals may be more relevant to the dynamics of motor circuits and movement behaviors than are studies of

Neuromolecular Imaging Shows Temporal Synchrony Patterns between Serotonin and Movement within Neuronal Motor Circuits in the Brain.

Science.gov (United States)

Broderick, Patricia A

2013-06-21

The present discourse links the electrical and chemical properties of the brain with neurotransmitters and movement behaviors to further elucidate strategies to diagnose and treat brain disease. Neuromolecular imaging (NMI), based on electrochemical principles, is used to detect serotonin in nerve terminals (dorsal and ventral striata) and somatodendrites (ventral tegmentum) of reward/motor mesocorticolimbic and nigrostriatal brain circuits. Neuronal release of serotonin is detected at the same time and in the same animal, freely moving and unrestrained, while open-field behaviors are monitored via infrared photobeams. The purpose is to emphasize the unique ability of NMI and the BRODERICK PROBE® biosensors to empirically image a pattern of temporal synchrony, previously reported, for example, in Aplysia using central pattern generators (CPGs), serotonin and cerebral peptide-2. Temporal synchrony is reviewed within the context of the literature on central pattern generators, neurotransmitters and movement disorders. Specifically, temporal synchrony data are derived from studies on psychostimulant behavior with and without cocaine while at the same time and continuously, serotonin release in motor neurons within basal ganglia, is detected. The results show that temporal synchrony between the neurotransmitter, serotonin and natural movement occurs when the brain is NOT injured via, e.g., trauma, addictive drugs or psychiatric illness. In striking contrast, in the case of serotonin and cocaine-induced psychostimulant behavior, a different form of synchrony and also asynchrony can occur. Thus, the known dysfunctional movement behavior produced by cocaine may well be related to the loss of temporal synchrony, the loss of the ability to match serotonin in brain with motor activity. The empirical study of temporal synchrony patterns in humans and animals may be more relevant to the dynamics of motor circuits and movement behaviors than are studies of static parameters

Remote tuning of NMR probe circuits.

Science.gov (United States)

Kodibagkar, V D; Conradi, M S

2000-05-01

There are many circumstances in which the probe tuning adjustments cannot be located near the rf NMR coil. These may occur in high-temperature NMR, low-temperature NMR, and in the use of magnets with small diameter access bores. We address here circuitry for connecting a fixed-tuned probe circuit by a transmission line to a remotely located tuning network. In particular, the bandwidth over which the probe may be remotely tuned while keeping the losses in the transmission line acceptably low is considered. The results show that for all resonant circuit geometries (series, parallel, series-parallel), overcoupling of the line to the tuned circuit is key to obtaining a large tuning bandwidth. At equivalent extents of overcoupling, all resonant circuit geometries have nearly equal remote tuning bandwidths. Particularly for the case of low-loss transmission line, the tuning bandwidth can be many times the tuned circuit's bandwidth, f(o)/Q. Copyright 2000 Academic Press.

Communication and Sensing Circuits on Cellulose

Directory of Open Access Journals (Sweden)

Federico Alimenti

2015-06-01

Full Text Available This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT era.

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array.

Science.gov (United States)

Wu, Jian-Feng; Wang, Feng; Wang, Qi; Li, Jian-Qing; Song, Ai-Guo

2016-12-06

With one operational amplifier (op-amp) in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D) resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements' bypass currents, which were injected into array's non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT) with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC) was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT's measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately.

Study on Oscillations during Short Circuit of MW-Scale IGBT Power Modules by Means of a 6-kA/1.1-kV Nondestructive Testing System

DEFF Research Database (Denmark)

Wu, Rui; Diaz Reigosa, Paula; Iannuzzo, Francesco

2015-01-01

This paper uses a 6-kA/1.1-kV nondestructive testing system for the analysis of the short-circuit behavior of insulated-gate bipolar transistor (IGBT) power modules. A field-programmable gate array enables the definition of control signals to an accuracy of 10 ns. Multiple 1.7-kV/1-kA IGBT power...... modules displayed severe divergent oscillations, which were subsequently characterized. Experimental tests indicate that nonnegligible circuit stray inductance plays an important role in the divergent oscillations. In addition, the temperature dependence of the transconductance is proposed as an important...

Unit: Electric Circuits, Inspection Pack, National Trial Print.

Science.gov (United States)

Australian Science Education Project, Toorak, Victoria.

As a part of the unit materials in the series produced by the Australian Science Education Project, this teacher edition is primarily composed of a core relating to simple circuits, a test form, and options. Options are given under the headings: Your Invention; "How Long Does a Call Last?"; One, Two, Three Wires; Parallel Circuits; More…

Vertically integrated circuit development at Fermilab for detectors

International Nuclear Information System (INIS)

Yarema, R; Deptuch, G; Hoff, J; Khalid, F; Lipton, R; Shenai, A; Trimpl, M; Zimmerman, T

2013-01-01

Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

Estimating the short-circuit impedance

DEFF Research Database (Denmark)

Nielsen, Arne Hejde; Pedersen, Knud Ole Helgesen; Poulsen, Niels Kjølstad

1997-01-01

A method for establishing a complex value of the short-circuit impedance from naturally occurring variations in voltage and current is discussed. It is the symmetrical three phase impedance at the fundamental grid frequency there is looked for. The positive sequence components in voltage...... and current are derived each period, and the short-circuit impedance is estimated from variations in these components created by load changes in the grid. Due to the noisy and dynamic grid with high harmonic distortion it is necessary to threat the calculated values statistical. This is done recursively...... through a RLS-algorithm. The algorithms have been tested and implemented on a PC at a 132 kV substation supplying a rolling mill. Knowing the short-circuit impedance gives the rolling mill an opportunity to adjust the arc furnace operation to keep flicker below a certain level. Therefore, the PC performs...

Thermally-induced voltage alteration for integrated circuit analysis

Energy Technology Data Exchange (ETDEWEB)

Cole, E.I. Jr.

2000-06-20

A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

Multi-qubit circuit quantum electrodynamics

International Nuclear Information System (INIS)

Viehmann, Oliver

2013-01-01

Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

Multi-qubit circuit quantum electrodynamics

Energy Technology Data Exchange (ETDEWEB)

Viehmann, Oliver

2013-09-03

Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

Demodulation Radio Frequency Interference Effects in Operational Amplifier Circuits

Science.gov (United States)

Sutu, Yue-Hong

A series of investigations have been carried out to determine RFI effects in analog circuits using monolithic integrated operational amplifiers (op amps) as active devices. The specific RFI effect investigated is how amplitude-modulated (AM) RF signals are demodulated in op amp circuits to produce undesired low frequency responses at AM-modulation frequency. The undesired demodulation responses were shown to be characterized by a second-order nonlinear transfer function. Four representative op amp types investigated were the 741 bipolar op amp, the LM10 bipolar op amp, the LF355 JFET-Bipolar op amp, and the CA081 MOS-Bipolar op amp. Two op amp circuits were investigated. The first circuit was a noninverting unity voltage gain buffer circuit. The second circuit was an inverting op amp configuration. In the second circuit, the investigation includes the effects of an RFI suppression capacitor in the feedback path. Approximately 30 units of each op amp type were tested to determine the statistical variations of RFI demodulation effects in the two op amp circuits. The Nonlinear Circuit Analysis Program, NCAP, was used to simulate the demodulation RFI response. In the simulation, the op amp was replaced with its incremental macromodel. Values of macromodel parameters were obtained from previous investigations and manufacturer's data sheets. Some key results of this work are: (1) The RFI demodulation effects are 10 to 20 dB lower in CA081 and LF355 FET-bipolar op amp than in 741 and LM10 bipolar op amp except above 40 MHz where the LM10 RFI response begins to approach that of CA081. (2) The experimental mean values for 30 741 op amps show that RFI demodulation responses in the inverting amplifier with a 27 pF feedback capacitor were suppressed from 10 to 35 dB over the RF frequency range 0.1 to 150 MHz except at 0.15 MHz where only 3.5 dB suppression was observed. (3) The NCAP program can predict RFI demodulation responses in 741 and LF355 unity gain buffer circuits

Design, Fabrication and Integration of a NaK-Cooled Circuit

International Nuclear Information System (INIS)

Garber, Anne; Godfroy, Thomas

2006-01-01

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned for use with lithium. Due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped NaK circuit. (authors)

Simulation and experimental study on lithium ion battery short circuit

International Nuclear Information System (INIS)

Zhao, Rui; Liu, Jie; Gu, Junjie

2016-01-01

Highlights: • Both external and internal short circuit tests were performed on Li-ion batteries. • An electrochemical–thermal model with an additional nail site heat source is presented. • The model can accurately simulate the temperature variations of non-venting batteries. • The model is reliable in predicting the occurrence and start time of thermal runaway. • A hydrogel cooling system proves its strength in preventing battery thermal runaway. - Abstract: Safety is the first priority in lithium ion (Li-ion) battery applications. A large portion of electrical and thermal hazards caused by Li-ion battery is associated with short circuit. In this paper, both external and internal short circuit tests are conducted. Li-ion batteries and battery packs of different capacities are used. The results indicate that external short circuit is worse for smaller size batteries due to their higher internal resistances, and this type of short can be well managed by assembling fuses. In internal short circuit tests, higher chance of failure is found on larger capacity batteries. A modified electrochemical–thermal model is proposed, which incorporates an additional heat source from nail site and proves to be successful in depicting temperature changes in batteries. Specifically, the model is able to estimate the occurrence and approximate start time of thermal runaway. Furthermore, the effectiveness of a hydrogel based thermal management system in suppressing thermal abuse and preventing thermal runaway propagation is verified through the external and internal short tests on batteries and battery packs.

Simulation Approach for Timing Analysis of Genetic Logic Circuits

DEFF Research Database (Denmark)

Baig, Hasan; Madsen, Jan

2017-01-01

in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior...... of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits...

Inductive energy storage using high voltage vacuum circuit breakers

International Nuclear Information System (INIS)

McCann, R.B.; Woodson, H.H.; Mukutmoni, T.

1976-01-01

Controlled thermonuclear fusion experiments currently being planned require large amounts of pulsed energy. Inductive energy storage systems (IES) appear to be attractive for at least two applications in the fusion research program: high beta devices and those employing turbulent heating. The well-known roadblock to successful implementation of IES is the development of a reliable and cost-effective off-switch capable of handling high currents and withstanding high recovery voltages. The University of Texas at Austin has a program to explore the application of conventional vacuum circuit breakers designed for use in AC systems, in conjunction with appropriate counter pulse circuits, as off-switches in inductive energy storage systems. The present paper describes the IES employing vacuum circuit breakers as off-switches. Since the deionization property of these circuit breakers is of great importance to the design and the cost of the counter-pulse circuit, a synthetic test installation to test these breakers has been conceived, designed and is being installed in the Fusion Research Center, University of Texas at Austin. Some design aspects of the facility will be discussed here. Finally, the results of the study on a mathematical model developed and optimized to determine the least cost system which meets both the requirements of an off-switch for IES Systems and the ratings of circuit breakers used in power systems has been discussed. This analysis indicates that the most important factor with respect to the system cost is the derating of the circuit breakers to obtain satisfactory lifetimes

Performance of the Main Dipole Magnet Circuits of the LHC during Commissioning

CERN Document Server

Verweij, A; Ballarino, A; Bellesia, B; Bordry, Frederick; Cantone, A; Casas Lino, M; Castaneda Serra, A; Castillo Trello, C; Catalan-Lasheras, N; Charifoulline, Z; Coelingh, G; Dahlerup-Petersen, K; D'Angelo, G; Denz, R; Fehér, S; Flora, R; Gruwé, M; Kain, V; Khomenko, B; Kirby, G; MacPherson, A; Marqueta Barbero, A; Mess, K H; Modena, M; Mompo, R; Montabonnet, V; le Naour, S; Nisbet, D; Parma, V; Pojer, M; Ponce, L; Raimondo, A; Redaelli, S; Reymond, H; Richter, D; de Rijk, G; Rijllart, A; Romera Ramirez, I; Saban, R; Sanfilippo, S; Schmidt, R; Siemko, A; Solfaroli Camillocci, M; Thurel, Y; Thiessen, H; Venturini-Delsolaro, W; Vergara Fernandez, A; Wolf, R; Zerlauth, M

2008-01-01

During hardware commissioning of the Large Hadron Collider (LHC), 8 main dipole circuits are tested at 1.9 K and up to their nominal current. Each dipole circuit contains 154 magnets of 15 m length, and has a total stored energy of up to 1.3 GJ. All magnets are wound from Nb-Ti superconducting Rutherford cables, and contain heaters to quickly force the transition to the normal conducting state in case of a quench, and hence reduce the hot spot temperature. In this paper the performance of the first three of these circuits is presented, focussing on quench detection, heater performance, operation of the cold bypass diodes, and magnet-to-magnet quench propagation. The results as measured on the entire circuits will be compared to the test results obtained during the reception tests of the individual magnets.

Circuit analysis for dummies

CERN Document Server

Santiago, John

2013-01-01

Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

A Readout Integrated Circuit (ROIC) employing self-adaptive background current compensation technique for Infrared Focal Plane Array (IRFPA)

Science.gov (United States)

Zhou, Tong; Zhao, Jian; He, Yong; Jiang, Bo; Su, Yan

2018-05-01

A novel self-adaptive background current compensation circuit applied to infrared focal plane array is proposed in this paper, which can compensate the background current generated in different conditions. Designed double-threshold detection strategy is to estimate and eliminate the background currents, which could significantly reduce the hardware overhead and improve the uniformity among different pixels. In addition, the circuit is well compatible to various categories of infrared thermo-sensitive materials. The testing results of a 4 × 4 experimental chip showed that the proposed circuit achieves high precision, wide application and high intelligence. Tape-out of the 320 × 240 readout circuit, as well as the bonding, encapsulation and imaging verification of uncooled infrared focal plane array, have also been completed.

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array

Directory of Open Access Journals (Sweden)

Jian-Feng Wu

2016-12-01

Full Text Available With one operational amplifier (op-amp in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements’ bypass currents, which were injected into array’s non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT’s measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately.

Low cost design of microprocessor EDAC circuit

International Nuclear Information System (INIS)

Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

2015-01-01

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

Azerbaijan Technical University’s Experience in Teaching Linear Electrical Circuit Theory

Directory of Open Access Journals (Sweden)

G. A. Mamedov

2006-01-01

Full Text Available An experience in teaching linear electrical circuit theory at the Azerbaijan Technical University is presented in the paper. The paper describes structure of the Linear Electrical Circuit Theory course worked out by the authors that contains a section on electrical calculation of track circuits, information on electro-magnetic compatibility and typical tests for better understanding of the studied subject.

Current limiter circuit system

Science.gov (United States)

Witcher, Joseph Brandon; Bredemann, Michael V.

2017-09-05

An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

Accelerated test techniques for micro-circuits: Evaluation of high temperature (473 k - 573 K) accelerated life test techniques as effective microcircuit screening methods

Science.gov (United States)

Johnson, G. M.

1976-01-01

The application of high temperature accelerated test techniques was shown to be an effective method of microcircuit defect screening. Comprehensive microcircuit evaluations and a series of high temperature (473 K to 573 K) life tests demonstrated that a freak or early failure population of surface contaminated devices could be completely screened in thirty two hours of test at an ambient temperature of 523 K. Equivalent screening at 398 K, as prescribed by current Military and NASA specifications, would have required in excess of 1,500 hours of test. All testing was accomplished with a Texas Instruments' 54L10, low power triple-3 input NAND gate manufactured with a titanium- tungsten (Ti-W), Gold (Au) metallization system. A number of design and/or manufacturing anomalies were also noted with the Ti-W, Au metallization system. Further study of the exact nature and cause(s) of these anomalies is recommended prior to the use of microcircuits with Ti-W, Au metallization in long life/high reliability applications. Photomicrographs of tested circuits are included.

Characterization of a piezoelectric MEMS actuator surface toward motion-enabled reconfigurable RF circuits

Science.gov (United States)

Tellers, M. C.; Pulskamp, J. S.; Bedair, S. S.; Rudy, R. Q.; Kierzewski, I. M.; Polcawich, R. G.; Bergbreiter, S. E.

2018-03-01

As an alternative to highly constrained hard-wired reconfigurable RF circuits, a motion-enabled reconfigurable circuit (MERC) offers freedom from transmission line losses and homogeneous materials selection. The creation of a successful MERC requires a precise mechanical mechanism for relocating components. In this work, a piezoelectric MEMS actuator array is modeled and experimentally characterized to assess its viability as a solution to the MERC concept. Actuation and design parameters are evaluated, and the repeatability of high quality on-axis motion at greater than 1 mm s-1 is demonstrated with little positional error. Finally, an initial proof-of-concept circuit reconfiguration has been demonstrated using off-the-shelf RF filter components. Although initial feasibility tests show filter performance degradation with an additional insertion loss of 0.3 dB per contact, out-of-band rejection degradation as high as 10 dB, and ripple performance reduction from 0.25 dB to 1.5 dB, MERC is proven here as an alternative to traditional approaches used in reconfigurable RF circuit applications.

Synthesis of multivalued quantum logic circuits by elementary gates

Science.gov (United States)

Di, Yao-Min; Wei, Hai-Rui

2013-01-01

We propose the generalized controlled X (gcx) gate as the two-qudit elementary gate, and based on Cartan decomposition, we also give the one-qudit elementary gates. Then we discuss the physical implementation of these elementary gates and show that it is feasible with current technology. With these elementary gates many important qudit quantum gates can be synthesized conveniently. We provide efficient methods for the synthesis of various kinds of controlled qudit gates and greatly simplify the synthesis of existing generic multi-valued quantum circuits. Moreover, we generalize the quantum Shannon decomposition (QSD), the most powerful technique for the synthesis of generic qubit circuits, to the qudit case. A comparison of ququart (d=4) circuits and qubit circuits reveals that using ququart circuits may have an advantage over the qubit circuits in the synthesis of quantum circuits.

The voltage—current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

International Nuclear Information System (INIS)

Bao Bo-Cheng; Feng Fei; Dong Wei; Pan Sai-Hu

2013-01-01

A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage—current relationships (VCRs) between two parallel memristive circuits — a parallel memristor and capacitor circuit (the parallel MC circuit), and a parallel memristor and inductor circuit (the parallel ML circuit) — are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and experimental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

A novel charge pump drive circuit for power MOSFETs

International Nuclear Information System (INIS)

Wang Songlin; Zhou Bo; Wang Hui; Guo Wangrui; Ye Qiang

2010-01-01

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW. (semiconductor integrated circuits)

Quantum Effects of Mesoscopic Inductance and Capacity Coupling Circuits

International Nuclear Information System (INIS)

Liu Jianxin; Yan Zhanyuan; Song Yonghua

2006-01-01

Using the quantum theory for a mesoscopic circuit based on the discretenes of electric charges, the finite-difference Schroedinger equation of the non-dissipative mesoscopic inductance and capacity coupling circuit is achieved. The Coulomb blockade effect, which is caused by the discreteness of electric charges, is studied. Appropriately choose the components in the circuits, the finite-difference Schroedinger equation can be divided into two Mathieu equations in p-circumflex representation. With the WKBJ method, the currents quantum fluctuations in the ground states of the two circuits are calculated. The results show that the currents quantum zero-point fluctuations of the two circuits are exist and correlated.

Design and flight performance evaluation of the Mariners 6, 7, and 9 short-circuit current, open-circuit voltage transducers

Science.gov (United States)

Patterson, R. E.

1973-01-01

The purpose of the short-circuit voltage transducer is to provide engineering data to aid the evaluation of array performance during flight. The design, fabrication, calibration, and in-flight performance of the transducers onboard the Mariner 6, 7 and 9 spacecrafts are described. No significant differences were observed in the in-flight electrical performance of the three transducers. The transducers did experience significant losses due to coverslides or adhesive darkening, increased surface reflection, or spectral shifts within coverslide assembly. Mariner 6, 7 and 9 transducers showed non-cell current degradations of 3-1/2%, 3%, and 4%, respectively at Mars encounter and 6%, 3%, and 4-12%, respectively at end of mission. Mariner 9 solar Array Test 2 showed 3-12% current degradation while the transducer showed 4-12% degradation.

Open circuit voltage durability study and model of catalyst coated membranes at different humidification levels

Energy Technology Data Exchange (ETDEWEB)

Kundu, Sumit; Fowler, Michael W.; Simon, Leonardo C. [Department of Chemical Engineering, University of Waterloo, 200 University Avenue West, Waterloo, Ontario (Canada); Abouatallah, Rami; Beydokhti, Natasha [Hydrogenics Corporation, 5985 McLaughlin Road, Mississauga, Ontario (Canada)

2010-11-01

Fuel cell material durability is an area of extensive research today. Chemical degradation of the ionomer membrane is one important degradation mechanism leading to overall failure of fuel cells. This study examined the effects of relative humidity on the chemical degradation of the membrane during open circuit voltage testing. Five Gore trademark PRIMEA {sup registered} series 5510 catalyst coated membranes were degraded at 100%, 75%, 50%, and 20% RH. Open circuit potential and cumulative fluoride release were monitored over time. Additionally scanning electron microscopy images were taken at end of the test. The results showed that with decreasing RH fluoride release rate increased as did performance degradation. This was attributed to an increase in gas crossover with a decrease in RH. Further, it is also shown that interruptions in testing may heavily influence cumulative fluoride release measurements where frequent stoppages in testing will cause fluoride release to be underestimated. SEM analysis shows that degradation occurred in the ionomer layer close to the cathode catalyst. A chemical degradation model of the ionomer membrane was used to model the results. The model was able to predict fluoride release trends, including the effects of interruptions, showing that changes in gas crossover with RH could explain the experimental results. (author)

30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

Science.gov (United States)

2010-07-01

... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

Microcontroller based Integrated Circuit Tester

OpenAIRE

Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

2015-01-01

The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

Free-space coherent optical communication with orbital angular, momentum multiplexing/demultiplexing using a hybrid 3D photonic integrated circuit.

Science.gov (United States)

Guan, Binbin; Scott, Ryan P; Qin, Chuan; Fontaine, Nicolas K; Su, Tiehui; Ferrari, Carlo; Cappuzzo, Mark; Klemens, Fred; Keller, Bob; Earnshaw, Mark; Yoo, S J B

2014-01-13

We demonstrate free-space space-division-multiplexing (SDM) with 15 orbital angular momentum (OAM) states using a three-dimensional (3D) photonic integrated circuit (PIC). The hybrid device consists of a silica planar lightwave circuit (PLC) coupled to a 3D waveguide circuit to multiplex/demultiplex OAM states. The low excess loss hybrid device is used in individual and two simultaneous OAM states multiplexing and demultiplexing link experiments with a 20 Gb/s, 1.67 b/s/Hz quadrature phase shift keyed (QPSK) signal, which shows error-free performance for 379,960 tested bits for all OAM states.

30 CFR 18.51 - Electrical protection of circuits and equipment.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Electrical protection of circuits and equipment... TESTING, EVALUATION, AND APPROVAL OF MINING PRODUCTS ELECTRIC MOTOR-DRIVEN MINE EQUIPMENT AND ACCESSORIES Construction and Design Requirements § 18.51 Electrical protection of circuits and equipment. (a) An automatic...

30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

Science.gov (United States)

2010-07-01

... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

Electromagnetic Compatibility Design of the Computer Circuits

Science.gov (United States)

Zitai, Hong

2018-02-01

Computers and the Internet have gradually penetrated into every aspect of people’s daily work. But with the improvement of electronic equipment as well as electrical system, the electromagnetic environment becomes much more complex. Electromagnetic interference has become an important factor to hinder the normal operation of electronic equipment. In order to analyse the computer circuit compatible with the electromagnetic compatibility, this paper starts from the computer electromagnetic and the conception of electromagnetic compatibility. And then, through the analysis of the main circuit and system of computer electromagnetic compatibility problems, we can design the computer circuits in term of electromagnetic compatibility. Finally, the basic contents and methods of EMC test are expounded in order to ensure the electromagnetic compatibility of equipment.

Fractional-order RC and RL circuits

KAUST Repository

Radwan, Ahmed Gomaa

2012-05-30

This paper is a step forward to generalize the fundamentals of the conventional RC and RL circuits in fractional-order sense. The effect of fractional orders is the key factor for extra freedom, more flexibility, and novelty. The conditions for RC and RL circuits to act as pure imaginary impedances are derived, which are unrealizable in the conventional case. In addition, the sensitivity analyses of the magnitude and phase response with respect to all parameters showing the locations of these critical values are discussed. A qualitative revision for the fractional RC and RL circuits in the frequency domain is provided. Numerical and PSpice simulations are included to validate this study. © Springer Science+Business Media, LLC 2012.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

Science.gov (United States)

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

Volumetric and chemical control auxiliary circuit for a PWR primary circuit

International Nuclear Information System (INIS)

Costes, D.

1990-01-01

The volumetric and chemical control circuit has an expansion tank with at least one water-steam chamber connected to the primary circuit by a sampling pipe and a reinjection pipe. The sampling pipe feeds jet pumps controlled by valves. An action on these valves and pumps regulates the volume of the water in the primary circuit. A safety pipe controlled by a flap automatically injects water from the chamber into the primary circuit in case of ruptures. The auxiliary circuit has also systems for purifying the water and controlling the boric acid and hydrogen content [fr

Experimental and theoretical analysis of vacuum circuit breaker prestrike effect on a transformer

NARCIS (Netherlands)

Popov, M.; Smeets, R.P.P.; Van der Sluis, L.; De Herdt, H.; Declerq, J.

2009-01-01

The work presented in this paper deals with the investigation of circuit breaker prestrike effect that occurs during energizing a distribution transformer. An experimental test setup that consists of a supply transformer, a vacuum circuit breaker (VCB), a cable and a test transformer is built, and

Circuit modeling for electromagnetic compatibility

CERN Document Server

Darney, Ian B

2013-01-01

Very simply, electromagnetic interference (EMI) costs money, reduces profits, and generally wreaks havoc for circuit designers in all industries. This book shows how the analytic tools of circuit theory can be used to simulate the coupling of interference into, and out of, any signal link in the system being reviewed. The technique is simple, systematic and accurate. It enables the design of any equipment to be tailored to meet EMC requirements. Every electronic system consists of a number of functional modules interconnected by signal links and power supply lines. Electromagnetic interference

Real Time In-circuit Condition Monitoring of MOSFET in Power Converters

Directory of Open Access Journals (Sweden)

Shakeb A. Khan

2015-03-01

Full Text Available Abstract:This paper presents simple and low-cost, real time in-circuit condition monitoring of MOSFET in power electronic converters. Design metrics requirements like low cost, small size, high power factor, low percentage of total harmonic distortion etc. requires the power electronic systems to operate at high frequencies and at high power density. Failures of power converters are attributed largely by aging of power MOSFETs at high switching frequencies. Therefore, real time in-circuit prognostic of MOSFET needs to be done before their selection for power system design. Accelerated aging tests are performed in different circuits to determine the wear out failure of critical components based on their parametric degradation. In this paper, the simple and low-cost test beds are designed for real time in-circuit prognostics of power MOSFETs. The proposed condition monitoring scheme helps in estimating the condition of MOSFETs at their maximum rated operating condition and will aid the system designers to test their reliability and benchmark them before selecting in power converters.

A high speed, wide dynamic range digitizer circuit for photomultiplier tubes

Energy Technology Data Exchange (ETDEWEB)

Yarema, R.J.; Foster, G.W.; Knickerbocker, K.; Sarraj, M.; Tschirhart, R.; Whitmore, J.; Zimmerman, T. [Fermi National Accelerator Lab., Batavia, IL (United States); Lindgren, M. [Univ. of California, Los Angeles, CA (United States). Physics Dept.

1994-06-01

High energy physics experiments running at high interaction rates frequently require long record lengths for determining a level 1 trigger. The easiest way to provide a long event record is by digital means. In applications requiring wide dynamic range, however, digitization of an analog signal to obtain the digital record has been impossible due to lack of high speed, wide range FADCs. One such application is the readout of thousands of photomultiplier tubes in fixed target and colliding beam experiment calorimeters. A circuit has been designed for digitizing PMT signals over a wide dynamic range (17--18 bits) with 8 bits of resolution at rates up to 53 MHz. Output from the circuit is in a floating point format with a 4 bit exponent and an 8 bit mantissa. The heart of the circuit is a full custom integrated circuit called the QIE (Charge Integrator and Encoder). The design of the QIE and associated circuitry reported here permits operation over a 17 bit dynamic range. Tests of the circuit with a PMT input and a pulsed laser have provided respectable results with little off line correction. Performance of the circuit for demanding applications can be significantly enhanced with additional off line correction. Circuit design, packaging issues, and test results of a multirange device are presented for the first time.

Design and implementation of a programming circuit in radiation-hardened FPGA

International Nuclear Information System (INIS)

Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

2011-01-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

A high speed, wide dynamic range digitizer circuit for photomultiplier tubes

International Nuclear Information System (INIS)

Yarema, R.J.; Foster, G.W.; Knickerbocker, K.; Sarraj, M.; Tschirhart, R.; Whitmore, J.; Zimmerman, T.; Lindgren, M.

1994-06-01

High energy physics experiments running at high interaction rates frequently require long record lengths for determining a level 1 trigger. The easiest way to provide a long event record is by digital means. In applications requiring wide dynamic range, however, digitization of an analog signal to obtain the digital record has been impossible due to lack of high speed, wide range FADCs. One such application is the readout of thousands of photomultiplier tubes in fixed target and colliding beam experiment calorimeters. A circuit has been designed for digitizing PMT signals over a wide dynamic range (17--18 bits) with 8 bits of resolution at rates up to 53 MHz. Output from the circuit is in a floating point format with a 4 bit exponent and an 8 bit mantissa. The heart of the circuit is a full custom integrated circuit called the QIE (Charge Integrator and Encoder). The design of the QIE and associated circuitry reported here permits operation over a 17 bit dynamic range. Tests of the circuit with a PMT input and a pulsed laser have provided respectable results with little off line correction. Performance of the circuit for demanding applications can be significantly enhanced with additional off line correction. Circuit design, packaging issues, and test results of a multirange device are presented for the first time

Design and implementation of a programming circuit in radiation-hardened FPGA

Science.gov (United States)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Equivalent circuit and characteristic simulation of a brushless electrically excited synchronous wind power generator

Science.gov (United States)

Wang, Hao; Zhang, Fengge; Guan, Tao; Yu, Siyang

2017-09-01

A brushless electrically excited synchronous generator (BEESG) with a hybrid rotor is a novel electrically excited synchronous generator. The BEESG proposed in this paper is composed of a conventional stator with two different sets of windings with different pole numbers, and a hybrid rotor with powerful coupling capacity. The pole number of the rotor is different from those of the stator windings. Thus, an analysis method different from that applied to conventional generators should be applied to the BEESG. In view of this problem, the equivalent circuit and electromagnetic torque expression of the BEESG are derived on the basis of electromagnetic relation of the proposed generator. The generator is simulated and tested experimentally using the established equivalent circuit model. The experimental and simulation data are then analyzed and compared. Results show the validity of the equivalent circuit model.

Wiring Together Synthetic Bacterial Consortia to Create a Biological Integrated Circuit.

Science.gov (United States)

Perry, Nicolas; Nelson, Edward M; Timp, Gregory

2016-12-16

The promise of adapting biology to information processing will not be realized until engineered gene circuits, operating in different cell populations, can be wired together to express a predictable function. Here, elementary biological integrated circuits (BICs), consisting of two sets of transmitter and receiver gene circuit modules with embedded memory placed in separate cell populations, were meticulously assembled using live cell lithography and wired together by the mass transport of quorum-sensing (QS) signal molecules to form two isolated communication links (comlinks). The comlink dynamics were tested by broadcasting "clock" pulses of inducers into the networks and measuring the responses of functionally linked fluorescent reporters, and then modeled through simulations that realistically captured the protein production and molecular transport. These results show that the comlinks were isolated and each mimicked aspects of the synchronous, sequential networks used in digital computing. The observations about the flow conditions, derived from numerical simulations, and the biofilm architectures that foster or silence cell-to-cell communications have implications for everything from decontamination of drinking water to bacterial virulence.

Simulation Analysis of DC and Switching Impulse Superposition Circuit

Science.gov (United States)

Zhang, Chenmeng; Xie, Shijun; Zhang, Yu; Mao, Yuxiang

2018-03-01

Surge capacitors running between the natural bus and the ground are affected by DC and impulse superposition voltage during operation in the converter station. This paper analyses the simulation aging circuit of surge capacitors by PSCAD electromagnetic transient simulation software. This paper also analyses the effect of the DC voltage to the waveform of the impulse voltage generation. The effect of coupling capacitor to the test voltage waveform is also studied. Testing results prove that the DC voltage has little effect on the waveform of the output of the surge voltage generator, and the value of the coupling capacitor has little effect on the voltage waveform of the sample. Simulation results show that surge capacitor DC and impulse superimposed aging test is feasible.

Diagnosis of soft faults in analog integrated circuits based on fractional correlation

International Nuclear Information System (INIS)

Deng Yong; Shi Yibing; Zhang Wei

2012-01-01

Aiming at the problem of diagnosing soft faults in analog integrated circuits, an approach based on fractional correlation is proposed. First, the Volterra series of the circuit under test (CUT) decomposed by the fractional wavelet packet are used to calculate the fractional correlation functions. Then, the calculated fractional correlation functions are used to form the fault signatures of the CUT. By comparing the fault signatures, the different soft faulty conditions of the CUT are identified and the faults are located. Simulations of benchmark circuits illustrate the proposed method and validate its effectiveness in diagnosing soft faults in analog integrated circuits. (semiconductor integrated circuits)

Intuitive analog circuit design

CERN Document Server

Thompson, Marc

2013-01-01

Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

The circuit designer's companion

CERN Document Server

Williams, Tim

1991-01-01

The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1972-01-01

Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

Monolithic circuits for barium fluoride detectors used in nuclear physics experiments. CRADA final report

International Nuclear Information System (INIS)

Varner, R.L.; Blankenship, J.L.; Beene, J.R.; Todd, R.A.

1998-02-01

Custom monolithic electronic circuits have been developed recently for large detector applications in high energy physics where subsystems require tens of thousands of channels of signal processing and data acquisition. In the design and construction of these enormous detectors, it has been found that monolithic circuits offer significant advantages over discrete implementations through increased performance, flexible packaging, lower power and reduced cost per channel. Much of the integrated circuit design for the high energy physics community is directly applicable to intermediate energy heavy-ion and electron physics. This STTR project conducted in collaboration with researchers at the Holifield Radioactive Ion Beam Facility (HRIBF) at Oak Ridge National Laboratory, sought to develop a new integrated circuit chip set for barium fluoride (BaF 2 ) detector arrays based upon existing CMOS monolithic circuit designs created for the high energy physics experiments. The work under the STTR Phase 1 demonstrated through the design, simulation, and testing of several prototype chips the feasibility of using custom CMOS integrated circuits for processing signals from BaF 2 detectors. Function blocks including charge-sensitive amplifiers, comparators, one shots, time-to-amplitude converters, analog memory circuits and buffer amplifiers were implemented during Phase 1 effort. Experimental results from bench testing and laboratory testing with sources were documented

Signal sampling circuit

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2011-01-01

A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

Signal sampling circuit

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2010-01-01

A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

Circuit drawings in electrical energy technology. 6. rev. ed.

International Nuclear Information System (INIS)

Weinert, J.

1991-01-01

This book contains a survey of the most important standards for graphical symbols and circuit documents for the area of electrical energy technology; it explains the circuit symbols in their construction and in their material and mental contents of terms; it contains a comparison of the circuit symbols from the DIN standards and the new DINTEC symbols taken from harmonisation, produced by arrangement in the picture column with the addition of the letters IEC; it contains a selection of circuit symbols of the IEC, USA, Canada and Great Britain; it supplements the necessary standards for producing circuit documents by extracts and references; it shows examples for the symbols of electrical equipment by using circuit symbols; it develops and explains the various kinds of representation of electrical circuits by circuit diagrams; it leads to reading and understanding the functioning of circuits by descriptions of functions; it gives examples of applications for designing and producing circuit documents, as used in practice; it contributes to arranging electrical plant according to the 'recognised rules of electrical engineering' and increasing safety by reference to the DIN-VDE regulations connected with representation, and it is a great help in designing electrical energy plant by its technical and electrical data. (orig.) [de

Electric circuits essentials

CERN Document Server

REA, Editors of

2012-01-01

REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

Approximate circuits for increased reliability

Science.gov (United States)

Hamlet, Jason R.; Mayo, Jackson R.

2015-08-18

Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

Implementation of chaotic secure communication systems based on OPA circuits

International Nuclear Information System (INIS)

Huang, C.-K.; Tsay, S.-C.; Wu, Y.-R.

2005-01-01

In this paper, we proposed a novel three-order autonomous circuit to construct a chaotic circuit with double scroll characteristic. The design idea is to use RLC elements and a nonlinear resistor. The one of salient features of the chaotic circuit is that the circuit with two flexible breakpoints of nonlinear element, and the advantage of the flexible breakpoint is that it increased complexity of the dynamical performance. Here, if we take a large and suitable breakpoint value, then the chaotic state can masking a large input signal in the circuit. Furthermore, we proposed a secure communication hyperchaotic system based on the proposed chaotic circuits, where the chaotic communication system is constituted by a chaotic transmitter and a chaotic receiver. To achieve the synchronization between the transmitter and the receiver, we are using a suitable Lyapunov function and Lyapunov theorem to design the feedback control gain. Thus, the transmitting message masked by chaotic state in the transmitter can be guaranteed to perfectly recover in the receiver. To achieve the systems performance, some basic components containing OPA, resistor and capacitor elements are used to implement the proposed communication scheme. From the viewpoints of circuit implementation, this proposed chaotic circuit is superior to the Chua chaotic circuits. Finally, the test results containing simulation and the circuit measurement are shown to demonstrate that the proposed method is correct and feasible

Short-circuit logic

NARCIS (Netherlands)

Bergstra, J.A.; Ponse, A.

2010-01-01

Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of

Output-Conductance Transition-Free Method for Improving Radio-Frequency Linearity of SOI MOSFET Circuits

Directory of Open Access Journals (Sweden)

A. Daghighi

2013-09-01

Full Text Available In this article, a novel concept is introduced to improve the radio frequency (RF linearity of partially-depleted (PD silicon-on-insulator (SOI MOSFET circuits. The transition due to the non-zero body resistance (RBody in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown. 3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz low noise amplifier (LNA is analyzed. Mixed mode device-circuit analysis is carried out to simultaneously solve device transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third harmonic distortion (HD3 and total harmonic distortion (THD are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.

Insights into iodine behaviour and speciation in the Phébus primary circuit

International Nuclear Information System (INIS)

Girault, N.; Payot, F.

2013-01-01

Highlights: • Unexpectedly, gaseous iodine was transported in the circuit during some test periods. • The highest gaseous iodine fraction was measured in FPT3. • Several iodine vapours were evidenced in the hot leg, CsI being not predominant. • Equilibrium gas-phase chemistry do not explain the experimental iodine results. • Kinetic limitations in iodine reactions probably played a significant role. - Abstract: The Phébus FP integral test series studies a large spectrum of the phenomenology of severe accidents in water-cooled nuclear reactors. These tests represent a unique source of representative integral source term data, covering fuel rod degradation and behaviour of fission-products released via the coolant system into the containment. The present analysis concerns the behaviour of iodine in the test circuit representing the Reactor Coolant System (RCS) which reaches gas temperatures of nearly 1600 °C at the circuit entrance and descending to 150 °C before entry into the containment. The stake in the data analysis is a better understanding of iodine phenomenology in RCS. This is indeed all the more serious as iodine is one of the most radiological important fission products released from the fuel and may exist under highly volatile forms even within cold leg thermal– hydraulics conditions. Complex and coupled phenomena arise in the primary circuit during the tests as the temperature decreases (drops) from the inlet of the circuit to the outlet. These are respectively for the iodine vapours and aerosols: chemical transformation, condensation on walls/aerosols, homogeneous nucleation into aerosols and agglomeration, deposition by thermophoresis. Depending on the location in the primary circuit, a combination of these phenomena occurred simultaneously. The phenomenological behaviour of iodine in RCS will be appraised through the analyses of the iodine transport, retention, vapour speciation and gaseous occurrence in the Phébus FP primary circuit

Limonene hydroperoxide analogues show specific patch test reactions.

Science.gov (United States)

Christensson, Johanna Bråred; Hellsén, Staffan; Börje, Anna; Karlberg, Ann-Therese

2014-05-01

The fragrance terpene R-limonene is a very weak sensitizer, but forms allergenic oxidation products upon contact with air. The primary oxidation products of oxidized limonene, the hydroperoxides, have an important impact on the sensitizing potency of the oxidation mixture. One analogue, limonene-1-hydroperoxide, was experimentally shown to be a significantly more potent sensitizer than limonene-2-hydroperoxide in the local lymph node assay with non-pooled lymph nodes. To investigate the pattern of reactivity among consecutive dermatitis patients to two structurally closely related limonene hydroperoxides, limonene-1-hydroperoxide and limonene-2-hydroperoxide. Limonene-1-hydroperoxide, limonene-2-hydroperoxide, at 0.5% in petrolatum, and oxidized limonene 3.0% pet. were tested in 763 consecutive dermatitis patients. Of the tested materials, limonene-1-hydroperoxide gave most reactions, with 2.4% of the patients showing positive patch test reactions. Limonene-2-hydroperoxide and oxidized R-limonene gave 1.7% and 1.2% positive patch test reactions, respectively. Concomitant positive patch test reactions to other fragrance markers in the baseline series were frequently noted. The results are in accordance with the experimental studies, as limonene-1-hydroperoxide gave more positive patch test reactions in the tested patients than limonene-2-hydroperoxide. Furthermore, the results support the specificity of the allergenic activity of the limonene hydroperoxide analogues and the importance of oxidized limonene as a cause of contact allergy. © 2014 John Wiley & Sons A/S. Published by John Wiley & Sons Ltd.

Circuit, especially for digital nuclear gyroscope systems

International Nuclear Information System (INIS)

Lowdenslager, J.R.

1974-01-01

The circuit with at least one or two spin generator shows a digital phase synchronizing loop in solid-state construction without movable mechanical parts. It is stable, may be turned in one direction any number of times without saturation, and also remains phase-synchronized when input signals are turned off. For this purpose, crystal oscillators with certain resonance frequencies are used. The spin generators are coupled at the outled side with filtering, squaring, and differential connections generating control impulses synchronous to the spin generators. Step divider circuits are connected to the oscillators, which act upon flip-flop registers. This is controlled by the filtering, squaring, and differential connections. Furthermore, field proportional control circuits with registers, advancing and delay circuits are provided, the registers being connected at the outlet side with digital adders and subtractors. The digital adder serves inertial-related purposes. (DG) [de

Circuit of synchronous logic for the transmission of safety commands

International Nuclear Information System (INIS)

Uberschlag, J.

1969-01-01

The author reports the development of a control-command circuit for the transmission of binary commands related to the safety of nuclear reactors. He presents the main design criteria (operation safety, provided safety level, flexibility, technical adaptation), the definition of the operation principle (inputs, logical outputs), the properties of a logic system. He evokes redundancy issues, and presents the system structure, proposes a possible sketch of the logic circuit. He describes the possible options for intermediate circuits and logic outputs, and tests to be performed

A high speed, wide dynamic range digitizer circuit for photomultiplier tubes

International Nuclear Information System (INIS)

Yarema, R.J.; Foster, G.W.; Knickerbocker, K.; Sarraj, M.; Tschirhart, R.; Whitmore, J.; Zimmerman, T.; Lindgren, M.

1995-01-01

A circuit has been designed for digitizing PMT signals over a wide dynamic range (17-18 bits) with 8 bits of resolution at rates up to 53 MHz. Output from the circuit is in a floating point format with a 4 bit exponent and an 8 bit mantissa. The heart of the circuit is a full custom integrated circuit called the QIE (Charge Integrator and Encoder). The design of the QIE and associated circuitry reported here permits operation over a 17 bit dynamic range. Test results of a multirange device are presented for the first time. (orig.)

Time series analysis in chaotic diode resonator circuit

Energy Technology Data Exchange (ETDEWEB)

Hanias, M.P. [TEI of Chalkis, GR 34400, Evia, Chalkis (Greece)] e-mail: mhanias@teihal.gr; Giannaris, G. [TEI of Chalkis, GR 34400, Evia, Chalkis (Greece); Spyridakis, A. [TEI of Chalkis, GR 34400, Evia, Chalkis (Greece); Rigas, A. [TEI of Chalkis, GR 34400, Evia, Chalkis (Greece)

2006-01-01

A diode resonator chaotic circuit is presented. Multisim is used to simulate the circuit and show the presence of chaos. Time series analysis performed by the method proposed by Grasberger and Procaccia. The correlation and minimum embedding dimension {nu} and m {sub min}, respectively, were calculated. Also the corresponding Kolmogorov entropy was calculated.

Time series analysis in chaotic diode resonator circuit

International Nuclear Information System (INIS)

Hanias, M.P.; Giannaris, G.; Spyridakis, A.; Rigas, A.

2006-01-01

A diode resonator chaotic circuit is presented. Multisim is used to simulate the circuit and show the presence of chaos. Time series analysis performed by the method proposed by Grasberger and Procaccia. The correlation and minimum embedding dimension ν and m min , respectively, were calculated. Also the corresponding Kolmogorov entropy was calculated

CALCULATION OF CONTROL CIRCUITS IN TIME DOMAIN USING SCILAB / XCOS ENVIRONMENT

Directory of Open Access Journals (Sweden)

Chioncel Petru

2014-10-01

Full Text Available The paper presents the computing of control circuits in time domain, starting from the mathematical model of the control path described by differential equation’s with constant coefficients, whose solution can be obtained through Laplace transform and transfer functions. In the field of electric drives, the control circuits can be reduced to elements of PT1 and PT2 type, for which, the responses obtained from step and impulse function in the test process, are analyzed. The presented calculation, done in Scilab, highlights the test responses of the process and, the speed control circuit implemented as block diagrams in Xcos, reveals the improve of the process parameter through the control loop.

Computational aspects of feedback in neural circuits.

Directory of Open Access Journals (Sweden)

Wolfgang Maass

2007-01-01

Full Text Available It has previously been shown that generic cortical microcircuit models can perform complex real-time computations on continuous input streams, provided that these computations can be carried out with a rapidly fading memory. We investigate the computational capability of such circuits in the more realistic case where not only readout neurons, but in addition a few neurons within the circuit, have been trained for specific tasks. This is essentially equivalent to the case where the output of trained readout neurons is fed back into the circuit. We show that this new model overcomes the limitation of a rapidly fading memory. In fact, we prove that in the idealized case without noise it can carry out any conceivable digital or analog computation on time-varying inputs. But even with noise, the resulting computational model can perform a large class of biologically relevant real-time computations that require a nonfading memory. We demonstrate these computational implications of feedback both theoretically, and through computer simulations of detailed cortical microcircuit models that are subject to noise and have complex inherent dynamics. We show that the application of simple learning procedures (such as linear regression or perceptron learning to a few neurons enables such circuits to represent time over behaviorally relevant long time spans, to integrate evidence from incoming spike trains over longer periods of time, and to process new information contained in such spike trains in diverse ways according to the current internal state of the circuit. In particular we show that such generic cortical microcircuits with feedback provide a new model for working memory that is consistent with a large set of biological constraints. Although this article examines primarily the computational role of feedback in circuits of neurons, the mathematical principles on which its analysis is based apply to a variety of dynamical systems. Hence they may also

What is this chocolate milk in my circuit? A cause of acute clotting of a continuous renal replacement circuit: Questions.

Science.gov (United States)

Kakajiwala, Aadil; Chiotos, Kathleen; Brothers, Julie; Lederman, April; Amaral, Sandra

2016-12-01

One of the greatest problems associated with continuous renal replacement therapy (CRRT) is the early clotting of filters. A literature search revealed three case reports of lipemic blood causing recurrent clotting and reduced CRRT circuit survival time in adult patients, but no reports of cases in children. A 23-month-old male infant with Martinez-Frias syndrome and multivisceral transplant was admitted to the hospital with severe sepsis and hemolytic anemia. He developed acute kidney injury, fluid overload and electrolyte imbalances requiring CRRT and was also administered total parenteral nutrition (TPN) and fat emulsion. The first circuit lasted 60 h before routine change was required. The second circuit showed acute clotting after only 18 h, and brownish-milky fluid was found in the circuit tubing layered between the clotted blood. The patient's serum triglyceride levels were elevated at 988 mg/dL. The lipid infusion was stopped and CRRT restarted. Serum triglyceride levels improved to 363 mg/dL. The new circuit lasted 63 h before routine change was required. Clotting of CRRT circuits due to elevated triglyceride levels is rare and has not been reported in the pediatric population. Physicians should be mindful of this risk in patients receiving TPN who have unexpected clotting of CRRT circuits.

Safety of steel vessel Magnox pressure circuits

International Nuclear Information System (INIS)

Stokoe, T.Y.; Bolton, C.J.; Heffer, P.J.H.

1991-01-01

The maintenance of pressure circuit integrity is fundamental to nuclear safety at the steel vessel Magnox stations. To confirm continued pressure circuit integrity the CEGB, as part of the Long Term Safety Review, has carried out extensive assessment and inspection in recent years. The assessment methods and inspection techniques employed are based on the most modern available. Reactor pressure vessel integrity is confirmed by a combination of arguments including safety factors inferred from the successful pre-service overpressure test, leak-before-break analysis and probabilistic assessment. In the case of other parts of the pressure circuits that are more accessible, comprising the boiler shells and interconnecting gas duct work, in-service inspection is a major element of the safety substantiation. The assessment and inspection techniques and the materials property data have been underpinned for many years by extensive research and development programmes and in-reactor monitoring of representative samples has also been undertaken. The paper summarises the work carried out to demonstrate the long term integrity of the Magnox pressure circuits and provides examples of the results obtained. (author)

Synthesis of the System Modeling and Signal Detecting Circuit of a Novel Vacuum Microelectronic Accelerometer

Directory of Open Access Journals (Sweden)

Zhengguo Shang

2009-05-01

Full Text Available A novel high-precision vacuum microelectronic accelerometer has been successfully fabricated and tested in our laboratory. This accelerometer has unique advantages of high sensitivity, fast response, and anti-radiation stability. It is a prototype intended for navigation applications and is required to feature micro-g resolution. This paper briefly describes the structure and working principle of our vacuum microelectronic accelerometer, and the mathematical model is also established. The performances of the accelerometer system are discussed after Matlab modeling. The results show that, the dynamic response of the accelerometer system is significantly improved by choosing appropriate parameters of signal detecting circuit, and the signal detecting circuit is designed. In order to attain good linearity and performance, the closed-loop control mode is adopted. Weak current detection technology is studied, and integral T-style feedback network is used in I/V conversion, which will eliminate high-frequency noise at the front of the circuit. According to the modeling parameters, the low-pass filter is designed. This circuit is simple, reliable, and has high precision. Experiments are done and the results show that the vacuum microelectronic accelerometer exhibits good linearity over -1 g to +1 g, an output sensitivity of 543 mV/g, and a nonlinearity of 0.94 %.

Radiation-hardened CMOS/SOS LSI circuits

International Nuclear Information System (INIS)

Aubuchon, K.G.; Peterson, H.T.; Shumake, D.P.

1976-01-01

The recently developed technology for building radiation-hardened CMOS/SOS devices has now been applied to the fabrication of LSI circuits. This paper describes and presents results on three different circuits: an 8-bit adder/subtractor (Al gate), a 256-bit shift register (Si gate), and a polycode generator (Al gate). The 256-bit shift register shows very little degradation after 1 x 10 6 rads (Si), with an increase from 1.9V to 2.9V in minimum operating voltage, a decrease of about 20% in maximum frequency, and little or no change in quiescent current. The p-channel thresholds increase from -0.9V to -1.3V, while the n-channel thresholds decrease from 1.05 to 0.23V, and the n-channel leakage remains below 1nA/mil. Excellent hardening results were also obtained on the polycode generator circuit. Ten circuits were irradiated to 1 x 10 6 rads (Si), and all continued to function well, with an increase in minimum power supply voltage from 2.85V to 5.85V and an increase in quiescent current by a factor of about 2. Similar hardening results were obtained on the 8-bit adder, with the minimum power supply voltage increasing from 2.2V to 4.6V and the add time increasing from 270 to 350 nsec after 1 x 10 6 rads (Si). These results show that large CMOS/SOS circuits can be hardened to above 1 x 10 6 rads (Si) with either the Si gate or Al gate technology. The paper also discusses the relative advantages of the Si gate versus the Al gate technology

Investigation on the Short-Circuit Behavior of an Aged IGBT Module Through a 6 kA/1.1 kV Non-Destructive Testing Equipment

DEFF Research Database (Denmark)

Wu, Rui; Smirnova, Liudmila; Iannuzzo, Francesco

2014-01-01

This paper describes the design and development of a 6 kA/1.1 kV non-destructive testing system, which aims for short circuit testing of high-power IGBT modules. An ultralow stray inductance of 37 nH is achieved in the implementation of the tester. An 100 MHz FPGA supervising unit enables 10 ns...

Parallel sparse direct solver for integrated circuit simulation

CERN Document Server

Chen, Xiaoming; Yang, Huazhong

2017-01-01

This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulato...

A novel ternary logic circuit using Josephson junction

International Nuclear Information System (INIS)

Morisue, M.; Oochi, K.; Nishizawa, M.

1989-01-01

This paper describes a novel Josephson complementary ternary logic circuit named as JCTL. This fundamental circuit is constructed by combination of two SQUIDs, one of which is switched in the positive direction and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, NOT and Double NOT in ternary form. The principle of the operation and design criteria are described in detail. The results of the simulation show that the reliable operations of these circuits can be achieved with a high performance

Energy pumping in electrical circuits under avalanche noise.

Science.gov (United States)

Kanazawa, Kiyoshi; Sagawa, Takahiro; Hayakawa, Hisao

2014-07-01

We theoretically study energy pumping processes in an electrical circuit with avalanche diodes, where non-Gaussian athermal noise plays a crucial role. We show that a positive amount of energy (work) can be extracted by an external manipulation of the circuit in a cyclic way, even when the system is spatially symmetric. We discuss the properties of the energy pumping process for both quasistatic and finite-time cases, and analytically obtain formulas for the amounts of the work and the power. Our results demonstrate the significance of the non-Gaussianity in energetics of electrical circuits.

Timergenerator circuits manual

CERN Document Server

Marston, R M

2013-01-01

Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

30 CFR 75.601-1 - Short circuit protection; ratings and settings of circuit breakers.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit protection; ratings and settings... Trailing Cables § 75.601-1 Short circuit protection; ratings and settings of circuit breakers. Circuit breakers providing short circuit protection for trailing cables shall be set so as not to exceed the...

Capacitive short circuit detection in transformer core laminations

International Nuclear Information System (INIS)

Schulz, Carl A.; Duchesne, Stephane; Roger, Daniel; Vincent, Jean-Noel

2008-01-01

A capacitive measurement procedure is proposed that serves to detect burr-induced short circuits in transformer core laminations. The tests are conducted on stacks of transformer steel sheets as used for transformer core production and yield a short-circuit probability indicative of the additional eddy current losses to be expected. Applied during the assembly of transformer cores, the measurements can help to decide whether the burr treatment process is working efficiently or has to be readjusted

Circuit simulation and physical implementation for a memristor-based colpitts oscillator

Science.gov (United States)

Deng, Hongmin; Wang, Dongping

2017-03-01

This paper implements two kinds of memristor-based colpitts oscillators, namely, the circuit where the memristor is added into the feedback network of the oscillator in parallel and series, respectively. First, a MULTISIM simulation circuit for the memristive colpitts oscillator is built, where an emulator constructed by some off-the-shelf components is utilized to replace the memristor. Then the physical system is implemented in terms of the MULTISIM simulation circuit. Circuit simulation and experimental study show that this memristive colpitts oscillator can exhibit periodic, quasi-periodic, and chaotic behaviors with certain parameter's variances. Besides, in a sense, the circuit is robust with circuit parameters and device types.

Active quenching circuit for a InGaAs single-photon avalanche diode

International Nuclear Information System (INIS)

Zheng Lixia; Wu Jin; Xi Shuiqing; Shi Longxing; Liu Siyang; Sun Weifeng

2014-01-01

We present a novel gated operation active quenching circuit (AQC). In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I–V characteristic measurement results of the detector. The circuit integrated with aROIC (readout integrated circuit) is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications. (semiconductor integrated circuits)

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

Directory of Open Access Journals (Sweden)

Michael S. Hsiao

2002-01-01

Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

The laboratory testing system for radiation rsistance investigations of integrated circuits

International Nuclear Information System (INIS)

Wronski, W.; Wislowski, J.

1986-01-01

In order to evaluate the radiation tolerance of integrated circuits MCY 7102 type /MOS RAM/ two devices were built: isotope arrangement for irradiation, and portable tester registering every error of storage block which consists of 32 IC's. Principle of operation and construction of this devices is described. Exemplary results of investigations are shown. (author)

Pulsed laser-induced SEU in integrated circuits

International Nuclear Information System (INIS)

Buchner, S.; Kang, K.; Stapor, W.J.; Campbell, A.B.; Knudson, A.R.; McDonald, P.; Rivet, S.

1990-01-01

The authors have used a pulsed picosecond laser to measure the threshold for single event upset (SEU) and single event latchup (SEL) for two different kinds of integrated circuits. The relative thresholds show good agreement with published ion upset data. The consistency of the results together with the advantages of using a laser system suggest that the pulsed laser can be used for SEU/SEL hardness assurance of integrated circuits

Sequential circuit design for radiation hardened multiple voltage integrated circuits

Science.gov (United States)

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Classical verification of quantum circuits containing few basis changes

Science.gov (United States)

Demarie, Tommaso F.; Ouyang, Yingkai; Fitzsimons, Joseph F.

2018-04-01

We consider the task of verifying the correctness of quantum computation for a restricted class of circuits which contain at most two basis changes. This contains circuits giving rise to the second level of the Fourier hierarchy, the lowest level for which there is an established quantum advantage. We show that when the circuit has an outcome with probability at least the inverse of some polynomial in the circuit size, the outcome can be checked in polynomial time with bounded error by a completely classical verifier. This verification procedure is based on random sampling of computational paths and is only possible given knowledge of the likely outcome.

NRC Information No. 87-41: Failures of certain Brown Boveri Electric circuit breakers

International Nuclear Information System (INIS)

Rossi, C.E.

1992-01-01

On April 20, 1987, Duquesne Light Company, the Beaver Valley Unit 2 licensee, notified the NRC of the failure of a BBE Type 5HK Class IE 4-KV circuit breaker. When the circuit breaker was racked onto the bus and 125-V DC control power was applied to the breaker's control circuit, the closing spring charged and the circuit breaker immediately closed and opened several times before the control power could be turned off. The licensee determined by field testing that the closing coil was not being energized. Another problem with BBE circuit breakers occurred at River Bend and was reported March 6, 1987. On February 6, 1987, with the unit at full power, the Division I diesel generator 4.16-KV output circuit breaker (Gould-Brown Boveri Type 5HK) failed to close during a weekly surveillance test. The licensee's inspection of the output circuit breaker revealed that a mounting bolt had fallen out of the closing spring charging motor, rendering the motor inoperable. Further investigation revealed several other circuit breakers that contained loose or missing charging motor mounting bolts. The licensee also stated that the River Bend circuit breaker preventive maintenance program, which the licensee believes to be in accordance with the vendor's recommendations, did not detect this problem. The licensee believes the root cause of the problem to be insufficient torquing of the charging motor mounting bolts by the vendor

Synthetic Plasma Liquid Based Electronic Circuits Realization-A Novel Concept.

Science.gov (United States)

Pandya, Killol V; Kosta, ShivPrasad

2016-09-01

Biomedical research is contributing significant role in the field of biomedical engineering and applied science. It brings research and innovations to a different level. This study investigated artificial human blood -synthetic plasma liquid as conductive medium. Keeping in mind the conductivity of synthetic plasma, astable multivibrator as well as differential amplifier circuit were demonstrated. The circuits were given normal input voltages at regular temperature and ideal conditions. The result shows desired response which supports the novel concept. For both the circuits, phase shift of 180° achieved by analysing biological electronic circuits.

Circuit mismatch influence on performance of paralleling silicon carbide MOSFETs

DEFF Research Database (Denmark)

Li, Helong; Munk-Nielsen, Stig; Pham, Cam

2014-01-01

This paper focuses on circuit mismatch influence on performance of paralleling SiC MOSFETs. Power circuit mismatch and gate driver mismatch influences are analyzed in detail. Simulation and experiment results show the influence of circuit mismatch and verify the analysis. This paper aims to give...... suggestions on paralleling discrete SiC MOSFETs and designing layout of power modules with paralleled SiC MOSFETs dies....

Low latency asynchronous interface circuits

Science.gov (United States)

Sadowski, Greg

2017-06-20

In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

High resolution capacitance detection circuit for rotor micro-gyroscope

Directory of Open Access Journals (Sweden)

Ming-Yuan Ren

2014-03-01

Full Text Available Conventional methods for rotor position detection of micro-gyroscopes include common exciting electrodes (single frequency and common sensing electrodes (frequency multiplex, but they have encountered some problems. So we present a high resolution and low noise pick-off circuit for micro-gyroscopes which utilizes the time multiplex method. The detecting circuit adopts a continuous-time current sensing circuit for capacitance measurement, and its noise analysis of the charge amplifier is introduced. The equivalent output noise power spectral density of phase-sensitive demodulation is 120 nV/Hz1/2. Tests revealed that the whole circuitry has a relative capacitance resolution of 1 × 10−8.

Simplified slow anti-coincidence circuit for Compton suppression systems

International Nuclear Information System (INIS)

Al-Azmi, Darwish

2008-01-01

Slow coincidence circuits for the anti-coincidence measurements have been considered for use in Compton suppression technique. The simplified version of the slow circuit has been found to be fast enough, satisfactory and allows an easy system setup, particularly with the advantage of the automatic threshold setting of the low-level discrimination. A well-type NaI detector as the main detector surrounded by plastic guard detector has been arranged to investigate the performance of the Compton suppression spectrometer using the simplified slow circuit. The system has been tested to observe the improvement in the energy spectra for medium to high-energy gamma-ray photons from terrestrial and environmental samples

Determination of the necessary parameters for a protection insulation disk of sodium circuit weighing system for thermomechanical and small component tests

International Nuclear Information System (INIS)

Bloch, M.; Cesar, S.B.G.

1985-01-01

The parameters requisited for a plastic disk used as thermal insulation, between feeding tank and weghing system, where the tank is supported are defined. The tank and weghing system are component parts of sodium circuit for thermomechanical and small component tests. During the circuit operation the temperature at tank reaches 600 0 C, however the temperature at weghing system should not reach 50 0 C. The temperature distribution in insulation disk is obtained by finit element method in function of thickness and thermal conductivity of material. The results obtained indicate for thickness E = 32 mm should be K 0 C and for E = 48 mm the thermal conductivity should be K 0 C. In both cases the pressure is σ > 14.5 Kgf/mm 2 . (M.C.K.) [pt

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

On Demand Internal Short Circuit Device Enables Verification of Safer, Higher Performing Battery Designs

Energy Technology Data Exchange (ETDEWEB)

Darcy, Eric; Keyser, Matthew

2017-05-15

The Internal Short Circuit (ISC) device enables critical battery safety verification. With the aluminum interstitial heat sink between the cells, normal trigger cells cannot be driven into thermal runaway without excessive temperature bias of adjacent cells. With an implantable, on-demand ISC device, thermal runaway tests show that the conductive heat sinks protected adjacent cells from propagation. High heat dissipation and structural support of Al heat sinks show high promise for safer, higher performing batteries.

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Prospects of closed-circuit television in detecting surface defects

International Nuclear Information System (INIS)

Kaisler, L. et al.

The use is discussed of closed-circuit television for optical in-service testing of surface defects of nuclear reactors. Experience gained by UJV Rez with in-service testing of the WWR-S reactor is briefly reported. Main attention is devoted to recognizability of defects and to determining the fundamental conditions of the applicability and limitations of the closed-circuit television method. In experiments, resolution of the method was tested and the role of the human factor was assessed in evaluating the results. The need was stressed of thorough training of operators. Based on the experiments conducted, considerations are presented regarding modifications of the individual elements of the tv chain aimed at improved quality of information and a limited role of the observer. (B.S.)

Superconducting flux flow digital circuits

International Nuclear Information System (INIS)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.

1993-01-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic

A deadtime reduction circuit for thermal neutron coincidence counters with Amptek preamplifiers

International Nuclear Information System (INIS)

Bourret, S.C.; Krick, M.S.

1994-01-01

We have developed a deadtime reduction circuit for thermal neutron coincidence counters using Amptek preamplifier/amplifier/discriminator circuits. The principle is to remove the overlap between the output pulses from the Amptek circuits by adding a derandomizer between the Amptek circuits and the shift-register coincidence electronics. We implemented the derandomizer as an Actel programmable logic array; the derandomizer board is small and can be mounted in the high-voltage junction box with the Amptek circuits, if desired. Up to 32 Amptek circuits can be used with one derandomizer. The derandomizer has seven outputs: four groups of eight inputs, two groups of 16 inputs, and one group of 32 inputs. We selected these groupings to facilitate detector ring-ratio measurements. The circuit was tested with the five-ring research multiplicity counter, which has five output signals-one for each ring. The counter's deadtime was reduced from 70 to 30 ns

Piezoelectric drive circuit

Science.gov (United States)

Treu, C.A. Jr.

1999-08-31

A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

Improvement and qualification of ultrasonic testing of dissimilar welds in the primary circuit of NPPs

International Nuclear Information System (INIS)

Mitzscherling, Steffen; Barth, Enrico; Homann, Tobias; Prager, Jens; Goetschel, Sebastian; Weiser, Martin

2017-01-01

The austenitic and dissimilar welds found in the primary circuit of nuclear power plants are not only extremely relevant to safety but also place very high demands on material testing. In addition to limited accessibility, the macroscopic structure of the weld seam is of paramount importance for ultrasound testing. In order to reliably determine material errors in position and size, the grain orientations and the elastic constants of the anisotropic weld bead structure must be known. The following work steps are used for the imaging representation of possible material defects: First, the weld seam is sounded in order to be able to determine important weld seam parameters, such as, for example, the grain orientation, using an inverse method. On the basis of these parameters, the sound paths are simulated in the next step by means of raytracing (RT). Finally, this RT simulation is assigned the measurement data (A-scans) from different transmitter and receiver positions and superimposed according to the Synthetic Aperature Focusing Technique (SAFT) method. The combination of inverse process, RT and SAFT also ensures a correct visualization of the faults in anisotropic materials. We explain these three methods and present the test arrangement of test specimens with artificial test errors. Measurement data as well as their evaluation are compared with the results of a CIVA simulation. [de

Circuit simulation and physical implementation for a memristor-based colpitts oscillator

Directory of Open Access Journals (Sweden)

Hongmin Deng

2017-03-01

Full Text Available This paper implements two kinds of memristor-based colpitts oscillators, namely, the circuit where the memristor is added into the feedback network of the oscillator in parallel and series, respectively. First, a MULTISIM simulation circuit for the memristive colpitts oscillator is built, where an emulator constructed by some off-the-shelf components is utilized to replace the memristor. Then the physical system is implemented in terms of the MULTISIM simulation circuit. Circuit simulation and experimental study show that this memristive colpitts oscillator can exhibit periodic, quasi-periodic, and chaotic behaviors with certain parameter’s variances. Besides, in a sense, the circuit is robust with circuit parameters and device types.

Mixed signal learning by spike correlation propagation in feedback inhibitory circuits.

Directory of Open Access Journals (Sweden)

Naoki Hiratani

2015-04-01

Full Text Available The brain can learn and detect mixed input signals masked by various types of noise, and spike-timing-dependent plasticity (STDP is the candidate synaptic level mechanism. Because sensory inputs typically have spike correlation, and local circuits have dense feedback connections, input spikes cause the propagation of spike correlation in lateral circuits; however, it is largely unknown how this secondary correlation generated by lateral circuits influences learning processes through STDP, or whether it is beneficial to achieve efficient spike-based learning from uncertain stimuli. To explore the answers to these questions, we construct models of feedforward networks with lateral inhibitory circuits and study how propagated correlation influences STDP learning, and what kind of learning algorithm such circuits achieve. We derive analytical conditions at which neurons detect minor signals with STDP, and show that depending on the origin of the noise, different correlation timescales are useful for learning. In particular, we show that non-precise spike correlation is beneficial for learning in the presence of cross-talk noise. We also show that by considering excitatory and inhibitory STDP at lateral connections, the circuit can acquire a lateral structure optimal for signal detection. In addition, we demonstrate that the model performs blind source separation in a manner similar to the sequential sampling approximation of the Bayesian independent component analysis algorithm. Our results provide a basic understanding of STDP learning in feedback circuits by integrating analyses from both dynamical systems and information theory.

Feedback in analog circuits

CERN Document Server

Ochoa, Agustin

2016-01-01

This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

System and circuit models for microwave antennas

OpenAIRE

Sobhy, Mohammed; Sanz-Izquierdo, Benito; Batchelor, John C.

2007-01-01

This paper describes how circuit and system models are derived for antennas from measurement of the input reflection coefficient. Circuit models are used to optimize the antenna performance and to calculate the radiated power and the transfer function of the antenna. System models are then derived for transmitting and receiving antennas. The most important contribution of this study is to show how microwave structures can be integrated into the simulation of digital communication systems. Thi...

Quantum Effect in the Mesoscopic RLC Circuits with a Source

International Nuclear Information System (INIS)

Liu Jianxin; Yan Zhanyuan

2005-01-01

The research work on the quantum effects in mesoscopic circuits has undergone a rapid development recently, however the whole quantum theory of the mesoscopic circuits should consider the discreteness of the electric charge. In this paper, based on the fundamental fact that the electric charge takes discrete values, the finite-difference Schroedinger equation of the mesoscopic RLC circuit with a source is achieved. With a unitary transformation, the Schroedinger equation becomes the standard Mathieu equation, then the energy spectrum and the wave functions of the system are obtained. Using the WKBJ method, the average of currents and square of the current are calculated. The results show the existence of the current fluctuation, which causes noise in the circuits. This paper is an application of the whole quantum mesoscopic circuits theory to the fundamental circuits, and the results will shed light on the design of the miniation circuits, especially on the purpose of reducing quantum noise coherent controlling of the mesoscopic quantum states.

Spike timing precision of neuronal circuits.

Science.gov (United States)

Kilinc, Deniz; Demir, Alper

2018-04-17

Spike timing is believed to be a key factor in sensory information encoding and computations performed by the neurons and neuronal circuits. However, the considerable noise and variability, arising from the inherently stochastic mechanisms that exist in the neurons and the synapses, degrade spike timing precision. Computational modeling can help decipher the mechanisms utilized by the neuronal circuits in order to regulate timing precision. In this paper, we utilize semi-analytical techniques, which were adapted from previously developed methods for electronic circuits, for the stochastic characterization of neuronal circuits. These techniques, which are orders of magnitude faster than traditional Monte Carlo type simulations, can be used to directly compute the spike timing jitter variance, power spectral densities, correlation functions, and other stochastic characterizations of neuronal circuit operation. We consider three distinct neuronal circuit motifs: Feedback inhibition, synaptic integration, and synaptic coupling. First, we show that both the spike timing precision and the energy efficiency of a spiking neuron are improved with feedback inhibition. We unveil the underlying mechanism through which this is achieved. Then, we demonstrate that a neuron can improve on the timing precision of its synaptic inputs, coming from multiple sources, via synaptic integration: The phase of the output spikes of the integrator neuron has the same variance as that of the sample average of the phases of its inputs. Finally, we reveal that weak synaptic coupling among neurons, in a fully connected network, enables them to behave like a single neuron with a larger membrane area, resulting in an improvement in the timing precision through cooperation.

A novel integrated circuit for semiconductor radiation detectors with sparse readout

International Nuclear Information System (INIS)

Zhang Yacong; Chen Zhognjian; Lu Wengao; Zhao Baoying; Ji Lijiu

2008-01-01

A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 μ DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100 k/s per channel. (authors)

Effect of a Diagram on Primary Students' Understanding About Electric Circuits

Science.gov (United States)

Preston, Christine Margaret

2017-09-01

This article reports on the effect of using a diagram to develop primary students' conceptual understanding about electric circuits. Diagrammatic representations of electric circuits are used for teaching and assessment despite the absence of research on their pedagogical effectiveness with young learners. Individual interviews were used to closely analyse Years 3 and 5 (8-11-year-old) students' explanations about electric circuits. Data was collected from 20 students in the same school providing pre-, post- and delayed post-test dialogue. Students' thinking about electric circuits and changes in their explanations provide insights into the role of diagrams in understanding science concepts. Findings indicate that diagram interaction positively enhanced understanding, challenged non-scientific views and promoted scientific models of electric circuits. Differences in students' understanding about electric circuits were influenced by prior knowledge, meta-conceptual awareness and diagram conventions including a stylistic feature of the diagram used. A significant finding that students' conceptual models of electric circuits were energy rather than current based has implications for electricity instruction at the primary level.

The implication of frontostriatal circuits in young smokers: A resting-state study.

Science.gov (United States)

Yuan, Kai; Yu, Dahua; Bi, Yanzhi; Li, Yangding; Guan, Yanyan; Liu, Jixin; Zhang, Yi; Qin, Wei; Lu, Xiaoqi; Tian, Jie

2016-06-01

The critical roles of frontostriatal circuits had been revealed in addiction. With regard to young smokers, the implication of frontostriatal circuits resting-state functional connectivity (RSFC) in smoking behaviors and cognitive control deficits remains unclear. In this study, the volume of striatum subsets, i.e., caudate, putamen, and nucleus accumbens, and corresponding RSFC differences were investigated between young smokers (n1  = 60) and nonsmokers (n2  = 60), which were then correlated with cigarette smoking measures, such as pack_years-cumulative effect of smoking, Fagerström Test for Nicotine Dependence (FTND)-severity of nicotine addiction, Questionnaire on Smoking Urges (QSU)-craving state, and Stroop task performances. Additionally, mediation analysis was carried out to test whether the frontostriatal RSFC mediates the relationship between striatum morphometry and cognitive control behaviors in young smokers when applicable. We revealed increased volume of right caudate and reduced RSFC between caudate and dorsolateral prefrontal cortex (DLPFC), orbitofrontal cortex in young smokers. Significant positive correlation between right caudate volume and QSU as well as negative correlation between anterior cingulate cortex-right caudate RSFC and FTND were detected in young smokers. More importantly, DLPFC-caudate RSFC strength mediated the relationship between caudate volume and incongruent errors during Stroop task in young smokers. Our results demonstrated that young smokers showed abnormal interactions within frontostriatal circuits, which were associated with smoking behaviors and cognitive control impairments. It is hoped that our study focusing on frontostriatal circuits could provide new insights into the neural correlates and potential novel therapeutic targets for treatment of young smokers. Hum Brain Mapp 37:2013-2026, 2016. © 2016 Wiley Periodicals, Inc. © 2016 Wiley Periodicals, Inc.

Analog circuits cookbook

CERN Document Server

Hickman, Ian

2013-01-01

Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.

Experimental study of two-phase natural circulation circuit

Energy Technology Data Exchange (ETDEWEB)

Lemos, Wanderley Freitas; Su, Jian, E-mail: wlemos@lasme.coppe.ufrj.br, E-mail: sujian@nuclear.ufrj.br [Coordenacao dos Programas de Pos-Graduacao em Engenharia (COPPE/UFRJ), Rio de Janeiro, RJ (Brazil). Programa de Engenharia Nuclear; Faccini, Jose Luiz Horacio, E-mail: faccini@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), RIo de Janeiro, RJ (Brazil). Lab. de Termo-Hidraulica Experimental

2012-07-01

This paper reports an experimental study on the behavior of fluid flow in natural circulation under single-and two-phase flow conditions. The natural circulation circuit was designed based on concepts of similarity and scale in proportion to the actual operating conditions of a nuclear reactor. This test equipment has similar performance to the passive system for removal of residual heat presents in Advanced Pressurized Water Reactors (A PWR). The experiment was carried out by supplying water to primary and secondary circuits, as well as electrical power resistors installed inside the heater. Power controller has available to adjust the values for supply of electrical power resistors, in order to simulate conditions of decay of power from the nuclear reactor in steady state. Data acquisition system allows the measurement and control of the temperature at different points by means of thermocouples installed at several points along the circuit. The behavior of the phenomenon of natural circulation was monitored by a software with graphical interface, showing the evolution of temperature measurement points and the results stored in digital format spreadsheets. Besides, the natural circulation flow rate was measured by a flowmeter installed on the hot leg. A flow visualization technique was used the for identifying vertical flow regimes of two-phase natural circulation. Finally, the Reynolds Number was calculated for the establishment of a friction factor correlation dependent on the scale geometrical length, height and diameter of the pipe. (author)

Experimental study of two-phase natural circulation circuit

International Nuclear Information System (INIS)

Lemos, Wanderley Freitas; Su, Jian; Faccini, Jose Luiz Horacio

2012-01-01

This paper reports an experimental study on the behavior of fluid flow in natural circulation under single-and two-phase flow conditions. The natural circulation circuit was designed based on concepts of similarity and scale in proportion to the actual operating conditions of a nuclear reactor. This test equipment has similar performance to the passive system for removal of residual heat presents in Advanced Pressurized Water Reactors (A PWR). The experiment was carried out by supplying water to primary and secondary circuits, as well as electrical power resistors installed inside the heater. Power controller has available to adjust the values for supply of electrical power resistors, in order to simulate conditions of decay of power from the nuclear reactor in steady state. Data acquisition system allows the measurement and control of the temperature at different points by means of thermocouples installed at several points along the circuit. The behavior of the phenomenon of natural circulation was monitored by a software with graphical interface, showing the evolution of temperature measurement points and the results stored in digital format spreadsheets. Besides, the natural circulation flow rate was measured by a flowmeter installed on the hot leg. A flow visualization technique was used the for identifying vertical flow regimes of two-phase natural circulation. Finally, the Reynolds Number was calculated for the establishment of a friction factor correlation dependent on the scale geometrical length, height and diameter of the pipe. (author)

Breathing circuit compliance and accuracy of displayed tidal volume during pressure-controlled ventilation of infants: A quality improvement project.

Science.gov (United States)

Glenski, Todd A; Diehl, Carrie; Clopton, Rachel G; Friesen, Robert H

2017-09-01

Anesthesia machines have evolved to deliver desired tidal volumes more accurately by measuring breathing circuit compliance during a preuse self-test and then incorporating the compliance value when calculating expired tidal volume. The initial compliance value is utilized in tidal volume calculation regardless of whether the actual compliance of the breathing circuit changes during a case, as happens when corrugated circuit tubing is manually expanded after the preuse self-test but before patient use. We noticed that the anesthesia machine preuse self-test was usually performed on nonexpanded pediatric circuit tubing, and then the breathing circuit was subsequently expanded for clinical use. We aimed to demonstrate that performing the preuse self-test in that manner could lead to incorrectly displayed tidal volume on the anesthesia machine monitor. The goal of this quality improvement project was to change the usual practice and improve the accuracy of displayed tidal volume in infants undergoing general anesthesia. There were four stages of the project: (i) gathering baseline data about the performance of the preuse self-test and using infant and adult test lungs to measure discrepancies of displayed tidal volumes when breathing circuit compliance was changed after the initial preuse self-test; (ii) gathering clinical data during pressure-controlled ventilation comparing anesthesia machine displayed tidal volume with actual spirometry tidal volume in patients less than 10 kg before (machine preuse self-test performed while the breathing circuit was nonexpanded) and after an intervention (machine preuse self-test performed after the breathing circuit was fully expanded); (iii) performing department-wide education to help implement practice change; (iv) gathering postintervention data to determine the prevalence of proper machine preuse self-test. At constant pressure-controlled ventilation through fully expanded circuit tubing, displayed tidal volume was 83

Electric circuits and signals

CERN Document Server

Sabah, Nassir H

2007-01-01

Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...

[Shunt and short circuit].

Science.gov (United States)

Rangel-Abundis, Alberto

2006-01-01

Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

Methodology for the digital calibration of analog circuits and systems with case studies

CERN Document Server

Pastre, Marc

2006-01-01

Methodology for the Digital Calibration of Analog Circuits and Systems shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. A complete methodology is proposed, and three applications are detailed. To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional di...

Macromodels of digital integrated circuits for program packages of circuit engineering design

Science.gov (United States)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Instrumentation Cables Test Plan

Energy Technology Data Exchange (ETDEWEB)

Muna, Alice Baca [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); LaFleur, Chris Bensdotter [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2016-10-01

A fire at a nuclear power plant (NPP) has the potential to damage structures, systems, and components important to safety, if not promptly detected and suppressed. At Browns Ferry Nuclear Power Plant on March 22, 1975, a fire in the reactor building damaged electrical power and control systems. Damage to instrumentation cables impeded the function of both normal and standby reactor coolant systems, and degraded the operators’ plant monitoring capability. This event resulted in additional NRC involvement with utilities to ensure that NPPs are properly protected from fire as intended by the NRC principle design criteria (i.e., general design criteria 3, Fire Protection). Current guidance and methods for both deterministic and performance based approaches typically make conservative (bounding) assumptions regarding the fire-induced failure modes of instrumentation cables and those failure modes effects on component and system response. Numerous fire testing programs have been conducted in the past to evaluate the failure modes and effects of electrical cables exposed to severe thermal conditions. However, that testing has primarily focused on control circuits with only a limited number of tests performed on instrumentation circuits. In 2001, the Nuclear Energy Institute (NEI) and the Electric Power Research Institute (EPRI) conducted a series of cable fire tests designed to address specific aspects of the cable failure and circuit fault issues of concern1. The NRC was invited to observe and participate in that program. The NRC sponsored Sandia National Laboratories to support this participation, whom among other things, added a 4-20 mA instrumentation circuit and instrumentation cabling to six of the tests. Although limited, one insight drawn from those instrumentation circuits tests was that the failure characteristics appeared to depend on the cable insulation material. The results showed that for thermoset insulated cables, the instrument reading tended to drift

Circuit arrangement of an electronic component for the design of fail-safe protective circuits

International Nuclear Information System (INIS)

Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

1974-01-01

The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

Evolvable designs of experiments applications for circuits

CERN Document Server

Iordache, Octavian

2009-01-01

Adopting a groundbreaking approach, the highly regarded author shows how to design methods for planning increasingly complex experiments. He begins with a brief introduction to standard quality methods and the technology in standard electric circuits. The book then gives numerous examples of how to apply the proposed methodology in a series of real-life case studies. Although these case studies are taken from the printed circuit board industry, the methods are equally applicable to other fields of engineering.

Comparison of modified driver circuit and capacitor-transfer circuit in longitudinally excited N2 laser.

Science.gov (United States)

Uno, Kazuyuki; Akitsu, Tetsuya; Nakamura, Kenshi; Jitsuno, Takahisa

2013-04-01

We developed a modified driver circuit composed of a capacitance and a spark gap, called a direct-drive circuit, for a longitudinally excited gas laser. The direct-drive circuit uses a large discharge impedance caused by a long discharge length of the longitudinal excitation scheme and eliminates the buffer capacitance used in the traditional capacitor-transfer circuit. We compared the direct-drive circuit and the capacitor-transfer circuit in a longitudinally excited N2 laser (wavelength: 337 nm). Producing high output energy with the capacitor-transfer circuit requires a large storage capacitance and a discharge tube with optimum dimensions (an inner diameter of 4 mm and a length of 10 cm in this work); in contrast, the direct-drive circuit requires a high breakdown voltage, achieved with a small storage capacitance and a large discharge tube. Additionally, for the same input energy of 792 mJ, the maximum output energy of the capacitor-transfer circuit was 174.2 μJ, and that of the direct-drive circuit was 344.7 μJ.

Metal-clad switchgear with large capacity vacuum circuit breaker in two-tier arrangement for nuclear power plants

International Nuclear Information System (INIS)

Yoshikawa, Isao; Watanabe, Hideo; Sugitani, Shinji

1982-01-01

Accompanying the increase of main machinery capacity in nuclear power stations, the short-circuit capacity for 6.9 kV in-house auxiliary machinery circuit has increased, and a 63 kA circuit breaker has become necessary. Although magnetic breakers have been used as large capacity breakers so far, vacuum breakers which are more suitable for the recent environmental conditions of power stations have become employed. Hitachi Ltd. has developed the metal-clad switchboard with vacuum breakers of 7.2 kV, 1,200 to 3,000 A, and breaking current of 63 kA in two-tier arrangement. The main features of this breaker are small size, light weight, long life, labour-saving in maintenance and inspection, simple construction, easy handling, high reliability and safety. In addition, in this paper, the construction of the breaker and switchboard, aseismic property, and test results are described. The tests include the withstand voltage test, elevated temperature test, short period current test, short-circuit test, low current breaking test, continuous on-off test, on-off surge combination test and short-circuit breaking test under the condition of vacuum failure in one phase. The aseismic property is guaranteed by analyzing the vibration characteristics and the strength using computer-aided finite element method so that the performance required is satisfied. (Wakatsuki, Y.)

Free-Standing Organic Transistors and Circuits with Sub-Micron Thicknesses

Science.gov (United States)

Fukuda, Kenjiro; Sekine, Tomohito; Shiwaku, Rei; Morimoto, Takuya; Kumaki, Daisuke; Tokito, Shizuo

2016-01-01

The realization of wearable electronic devices with extremely thin and flexible form factors has been a major technological challenge. While substrates typically limit the thickness of thin-film electronic devices, they are usually necessary for their fabrication and functionality. Here we report on ultra-thin organic transistors and integrated circuits using device components whose substrates that have been removed. The fabricated organic circuits with total device thicknesses down to 350 nm have electrical performance levels close to those fabricated on conventional flexible substrates. Moreover, they exhibit excellent mechanical robustness, whereby their static and dynamic electrical characteristics do not change even under 50% compressive strain. Tests using systematically applied compressive strains reveal that these free-standing organic transistors possess anisotropic mechanical stability, and a strain model for a multilayer stack can be used to describe the strain in this sort of ultra-thin device. These results show the feasibility of ultimate-thin organic electronic devices using free-standing constructions. PMID:27278828

Circuit electromechanics with single photon strong coupling

Energy Technology Data Exchange (ETDEWEB)

Xue, Zheng-Yuan, E-mail: zyxue@scnu.edu.cn; Yang, Li-Na [Guangdong Provincial Key Laboratory of Quantum Engineering and Quantum Materials, and School of Physics and Telecommunication Engineering, South China Normal University, Guangzhou 510006 (China); Zhou, Jian, E-mail: jianzhou8627@163.com [Department of Electronic Communication Engineering, Anhui Xinhua University, Hefei 230088 (China); Guangdong Provincial Key Laboratory of Quantum Engineering and Quantum Materials, and School of Physics and Telecommunication Engineering, South China Normal University, Guangzhou 510006 (China)

2015-07-13

In circuit electromechanics, the coupling strength is usually very small. Here, replacing the capacitor in circuit electromechanics by a superconducting flux qubit, we show that the coupling among the qubit and the two resonators can induce effective electromechanical coupling which can attain the strong coupling regime at the single photon level with feasible experimental parameters. We use dispersive couplings among two resonators and the qubit while the qubit is also driven by an external classical field. These couplings form a three-wave mixing configuration among the three elements where the qubit degree of freedom can be adiabatically eliminated, and thus results in the enhanced coupling between the two resonators. Therefore, our work constitutes the first step towards studying quantum nonlinear effect in circuit electromechanics.

Circuit and bond polytopes on series–parallel graphs

OpenAIRE

Borne , Sylvie; Fouilhoux , Pierre; Grappe , Roland; Lacroix , Mathieu; Pesneau , Pierre

2015-01-01

International audience; In this paper, we describe the circuit polytope on series–parallel graphs. We first show the existence of a compact extended formulation. Though not being explicit, its construction process helps us to inductively provide the description in the original space. As a consequence, using the link between bonds and circuits in planar graphs, we also describe the bond polytope on series–parallel graphs.

Integrated neuron circuit for implementing neuromorphic system with synaptic device

Science.gov (United States)

Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

2018-02-01

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

Microwave RF antennas and circuits nonlinearity applications in engineering

CERN Document Server

Aluf, Ofer

2017-01-01

This book describes a new concept for analyzing RF/microwave circuits, which includes RF/microwave antennas. The book is unique in its emphasis on practical and innovative microwave RF engineering applications. The analysis is based on nonlinear dynamics and chaos models and shows comprehensive benefits and results. All conceptual RF microwave circuits and antennas are innovative and can be broadly implemented in engineering applications. Given the dynamics of RF microwave circuits and antennas, they are suitable for use in a broad range of applications. The book presents analytical methods for microwave RF antennas and circuit analysis, concrete examples, and geometric examples. The analysis is developed systematically, starting with basic differential equations and their bifurcations, and subsequently moving on to fixed point analysis, limit cycles and their bifurcations. Engineering applications include microwave RF circuits and antennas in a variety of topological structures, RFID ICs and antennas, micros...

Practical design of digital circuits basic logic to microprocessors

CERN Document Server

Kampel, Ian

1983-01-01

Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

Multi-Layer E-Textile Circuits

Science.gov (United States)

Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

2012-01-01

Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

Analog circuit design

CERN Document Server

Dobkin, Bob

2012-01-01

Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

Transient-induced latchup in CMOS integrated circuits

CERN Document Server

Ker, Ming-Dou

2009-01-01

"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

Complex Parts, Complex Data: Why You Need to Understand What Radiation Single Event Testing Data Does and Doesn't Show and the Implications Thereof

Science.gov (United States)

LaBel, Kenneth A.; Berg, Melanie D.

2015-01-01

Electronic parts (integrated circuits) have grown in complexity such that determining all failure modes and risks from single particle event testing is impossible. In this presentation, the authors will present why this is so and provide some realism on what this means. Its all about understanding actual risks and not making assumptions.

ESD analog circuits and design

CERN Document Server

Voldman, Steven H

2014-01-01

A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

Non-Destructive Investigation on Short Circuit Capability of Wind-Turbine-Scale IGBT Power Modules

DEFF Research Database (Denmark)

Wu, Rui; Iannuzzo, Francesco; Wang, Huai

2014-01-01

This paper presents a comprehensive investigation on the short circuit capability of wind-turbine-scale IGBT power modules by means of a 6 kA/1.1 kV non-destructive testing system. A Field Programmable Gate Array (FPGA) supervising unit is adpoted to achieve an accurate time control for short...... circuit test, which enables to define the driving signals with an accuracy of 10 ns. Thanks to the capability and the effectiveness of the constructed setup, oscillations appearing during short circuits of the new-generation 1.7 kV/1 kA IGBT power modules have been evidenced and characterized under...

A fast charge integrating and shaping circuit

International Nuclear Information System (INIS)

Kulka, Z.; Szoncso, F.

1990-01-01

The development of a low cost fast charge integrating and shaping circuit (FCISC) was motivated by the need for an interface between the photomultipliers of an existing hadronic calorimeter and recently developed new readout electronics designed to match the output of small ionization chambers for the upgraded UA1 detector at the CERN proton-antiproton collider. This paper describes the design principles of gated and ungated charge integrating and shaping circuits. An FCISC prototype using discrete components was made and its properties were determined with a computerized test setup. Finally an SMD implementation of the FCISC is presented and the performance is reported. (orig.)

Electromagnetic compatibility methods, analysis, circuits, and measurement

CERN Document Server

Weston, David A

2016-01-01

Revised, updated, and expanded, Electromagnetic Compatibility: Methods, Analysis, Circuits, and Measurement, Third Edition provides comprehensive practical coverage of the design, problem solving, and testing of electromagnetic compatibility (EMC) in electrical and electronic equipment and systems. This new edition provides novel information on theory, applications, evaluations, electromagnetic computational programs, and prediction techniques available. With sixty-nine schematics providing examples for circuit level electromagnetic interference (EMI) hardening and cost effective EMI problem solving, this book also includes 1130 illustrations and tables. Including extensive data on components and their correct implementation, the myths, misapplication, misconceptions, and fallacies that are common when discussing EMC/EMI will also be addressed and corrected.

Experiments and kinematics analysis of a hand rehabilitation exoskeleton with circuitous joints.

Science.gov (United States)

Zhang, Fuhai; Fu, Yili; Zhang, Qinchao; Wang, Shuguo

2015-01-01

Aiming at the hand rehabilitation of stroke patients, a wearable hand exoskeleton with circuitous joint is proposed. The circuitous joint adopts the symmetric pinion and rack mechanism (SPRM) with the parallel mechanism. The exoskeleton finger is a serial mechanism composed of three closed-chain SPRM joints in series. The kinematic equations of the open chain of the finger and the closed chains of the SPRM joints were built to analyze the kinematics of the hand rehabilitation exoskeleton. The experimental setup of the hand rehabilitation exoskeleton was built and the continuous passive motion (CPM) rehabilitation experiment and the test of human-robot interaction force measurement were conducted. Experiment results show that the mechanical design of the hand rehabilitation robot is reasonable and that the kinematic analysis is correct, thus the exoskeleton can be used for the hand rehabilitation of stroke patients.

Novel communication scheme based on chaotic Roessler circuits

International Nuclear Information System (INIS)

GarcIa-Lopez, J H; Jaimes-Reategui, R; Pisarchik, A N; MurguIa-Hernandez, A; Medina-Gutierrez, C; Valdivia-Hernadez, R; Villafana-Rauda, E

2005-01-01

We present a novel synchronization scheme for secure communication with two chaotic unidirectionally coupled Roessler circuits. The circuits are synchronized via one of the variables, while a signal is transmitted through another variable. We show that this scheme allows more stable communications. The system dynamics is studied numerically and experimentally in a wide range of a control parameter. The possibility of secure communications with an audio signal is demonstrated

Application of reliability analysis methods to the comparison of two safety circuits

International Nuclear Information System (INIS)

Signoret, J.-P.

1975-01-01

Two circuits of different design, intended for assuming the ''Low Pressure Safety Injection'' function in PWR reactors are analyzed using reliability methods. The reliability analysis of these circuits allows the failure trees to be established and the failure probability derived. The dependence of these results on test use and maintenance is emphasized as well as critical paths. The great number of results obtained may allow a well-informed choice taking account of the reliability wanted for the type of circuits [fr

Insulated transcriptional elements enable precise design of genetic circuits.

Science.gov (United States)

Zong, Yeqing; Zhang, Haoqian M; Lyu, Cheng; Ji, Xiangyu; Hou, Junran; Guo, Xian; Ouyang, Qi; Lou, Chunbo

2017-07-03

Rational engineering of biological systems is often complicated by the complex but unwanted interactions between cellular components at multiple levels. Here we address this issue at the level of prokaryotic transcription by insulating minimal promoters and operators to prevent their interaction and enable the biophysical modeling of synthetic transcription without free parameters. This approach allows genetic circuit design with extraordinary precision and diversity, and consequently simplifies the design-build-test-learn cycle of circuit engineering to a mix-and-match workflow. As a demonstration, combinatorial promoters encoding NOT-gate functions were designed from scratch with mean errors of 96% using our insulated transcription elements. Furthermore, four-node transcriptional networks with incoherent feed-forward loops that execute stripe-forming functions were obtained without any trial-and-error work. This insulation-based engineering strategy improves the resolution of genetic circuit technology and provides a simple approach for designing genetic circuits for systems and synthetic biology.Unwanted interactions between cellular components can complicate rational engineering of biological systems. Here the authors design insulated minimal promoters and operators that enable biophysical modeling of bacterial transcription without free parameters for precise circuit design.

Polymer solar cells with enhanced open-circuit voltage and efficiency

Science.gov (United States)

Chen, Hsiang-Yu; Hou, Jianhui; Zhang, Shaoqing; Liang, Yongye; Yang, Guanwen; Yang, Yang; Yu, Luping; Wu, Yue; Li, Gang

2009-11-01

Following the development of the bulk heterojunction structure, recent years have seen a dramatic improvement in the efficiency of polymer solar cells. Maximizing the open-circuit voltage in a low-bandgap polymer is one of the critical factors towards enabling high-efficiency solar cells. Study of the relation between open-circuit voltage and the energy levels of the donor/acceptor in bulk heterojunction polymer solar cells has stimulated interest in modifying the open-circuit voltage by tuning the energy levels of polymers. Here, we show that the open-circuit voltage of polymer solar cells constructed based on the structure of a low-bandgap polymer, PBDTTT, can be tuned, step by step, using different functional groups, to achieve values as high as 0.76 V. This increased open-circuit voltage combined with a high short-circuit current density results in a polymer solar cell with a power conversion efficiency as high as 6.77%, as certified by the National Renewable Energy Laboratory.

High school physics teacher forms of thought about simple electric circuits

International Nuclear Information System (INIS)

Kucukozer, H.

2005-01-01

According to some researches on students and on science teachers, they have same conceptual difficulties about simple electric circuits and these affect their further learning or/and teaching. [2], [5], [8], [9], [11], [13]. The main aim of this study was to investigate in-service high school physics teachers form of thought about simple electric circuits. In this purpose a test that was developed by Kucukozer [7], contains eight questions related to simple electric circuits was applied to in-service physics teachers (25 subjects) in various Anatolian Teacher High School in Turkey. After analyzing and evaluating of their data, it was found that, the physics teachers have conceptual difficulties about simple electric circuits, especially the concepts about source of stationary current and current usage

'Speedy' superconducting circuits

International Nuclear Information System (INIS)

Holst, T.

1994-01-01

The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1968-01-01

Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Unstable oscillators based hyperchaotic circuit

DEFF Research Database (Denmark)

Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.

1999-01-01

A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...

Circuits and electronics hands-on learning with analog discovery

CERN Document Server

Okyere Attia, John

2018-01-01

The book provides instructions on building circuits on breadboards, connecting the Analog Discovery wires to the circuit under test, and making electrical measurements. Various measurement techniques are described and used in this book, including: impedance measurements, complex power measurements, frequency response measurements, power spectrum measurements, current versus voltage characteristic measurements of diodes, bipolar junction transistors, and Mosfets. The book includes end-of-chapter problems for additional exercises geared towards hands-on learning, experimentation, comparisons between measured results and those obtained from theoretical calculations.

Fixation and mounting of porcine aortic valves for use in mock circuits.

Science.gov (United States)

Schlöglhofer, Thomas; Aigner, Philipp; Stoiber, Martin; Schima, Heinrich

2013-10-01

Investigations of the circulatory system in vitro use mock circuits that require valves to mimic the cardiac situation. Whereas mechanical valves increase water hammer effects due to inherent stiffness and do not allow the use of pressure lines or catheters, bioprosthetic valves are expensive and of limited durability in test fluids. Therefore, we developed a cheap, fast, alternative method to mount valves obtained from the slaughterhouse in mock circuits. Porcine aortic roots were obtained from the abattoir and used either in native condition or after fixation. Fixation was performed at a constant retrograde pressure to ensure closed valve position. Fixation time was 4 h in a 0.5%-glutaraldehyde phosphate buffer. The fixed valves were molded into a modular mock circulation connector using a fast curing silicone. Valve functionality was evaluated in a pulsatile setting (cardiac output = 4.7 l/min, heart rate = 80 beats/min) and compared before and after fixation. Leaflet motion was recorded with a high-speed camera and valve insufficiency was quantified by leakage flow under steady pressure application (80 mmHg). Under physiological conditions the aortic valves showed almost equal leaflet motion in native and fixed conditions. However, the leaflets of the native valves showed lower stiffness and more fluttering during systole than the fixed specimens. Under retrograde pressure, fresh and fixed valves showed small leakage flows of <30 ml/min. The new mounting and fixation procedure is a fast method to fabricate low cost biologic valves for the use in mock circuits.

An ADC-free adaptive interface circuit of resistive sensor for electronic nose system.

Science.gov (United States)

Chang, Chia-Lin; Chiu, Shih-Wen; Tang, Kea-Tiong

2013-01-01

The initial resistance of chemiresistive gas sensors could be affected by temperature, humidity, and background odors. In a sensing system, the traditional interface circuit always requires an ADC to convert analog signal to digital signal. In this paper, we propose an ADC-free adaptive interface circuit for a resistive gas sensor to read sensor signal and cancel the baseline drift. Furthermore, methanol was used to test the proposed interface circuit, which was connected with a FIGARO® gas sensor. This circuit was fabricated by TSMC 0.18 µm CMOS process, and consumed 86.41 µW under 1 V supply voltage.

Circuits and filters handbook

CERN Document Server

Chen, Wai-Kai

2003-01-01

A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

MOS integrated circuit design

CERN Document Server

Wolfendale, E

2013-01-01

MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

Security electronics circuits manual

CERN Document Server

MARSTON, R M

1998-01-01

Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

Many-body physics with circuit quantum electrodynamics

International Nuclear Information System (INIS)

Leib, Martin H.

2015-01-01

We present proposals to simulate many-body physics with superconducting circuits. The ''body'' to work with for superconducting circuits is the microwave photon and interaction is induced by the nonlinearity of the Josephson effect. We present two different approaches to simulate Bose-Hubbard physics, one based on a polariton scheme and another with nonlinear resonators. We also present a Dicke-model like simulator for ultrastrongly coupled Josephson junctions to a resonator and show a scheme for implementing long range interactions.

Changes to the shuttle circuits

CERN Multimedia

GS Department

2011-01-01

To fit with passengers expectation, there will be some changes to the shuttle circuits as from Monday 10 October. See details on http://cern.ch/ShuttleService (on line on 7 October). Circuit No. 5 is cancelled as circuit No. 1 also stops at Bldg. 33. In order to guarantee shorter travel times, circuit No. 1 will circulate on Meyrin site only and circuit No. 2, with departures from Bldg. 33 and 500, on Prévessin site only. Site Services Section

Troubleshooting analog circuits

CERN Document Server

Pease, Robert A

1991-01-01

Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other

Optoelectronics circuits manual

CERN Document Server

Marston, R M

2013-01-01

Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.

Pulse Detecting Genetic Circuit – A New Design Approach

Science.gov (United States)

Inniss, Mara; Iba, Hitoshi; Way, Jeffrey C.

2016-01-01

A robust cellular counter could enable synthetic biologists to design complex circuits with diverse behaviors. The existing synthetic-biological counters, responsive to the beginning of the pulse, are sensitive to the pulse duration. Here we present a pulse detecting circuit that responds only at the falling edge of a pulse–analogous to negative edge triggered electric circuits. As biological events do not follow precise timing, use of such a pulse detector would enable the design of robust asynchronous counters which can count the completion of events. This transcription-based pulse detecting circuit depends on the interaction of two co-expressed lambdoid phage-derived proteins: the first is unstable and inhibits the regulatory activity of the second, stable protein. At the end of the pulse the unstable inhibitor protein disappears from the cell and the second protein triggers the recording of the event completion. Using stochastic simulation we showed that the proposed design can detect the completion of the pulse irrespective to the pulse duration. In our simulation we also showed that fusing the pulse detector with a phage lambda memory element we can construct a counter which can be extended to count larger numbers. The proposed design principle is a new control mechanism for synthetic biology which can be integrated in different circuits for identifying the completion of an event. PMID:27907045

Integrated circuit and method of arbitration in a network on an integrated circuit.

NARCIS (Netherlands)

2011-01-01

The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input

Electronic Circuit Analysis Language (ECAL)

Science.gov (United States)

Chenghang, C.

1983-03-01

The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

The Solenarc circuit-breaker of high performance level

International Nuclear Information System (INIS)

Lehmann, J.M.

1983-01-01

After recalling the breaking principle involved in MV circuit-breakers manufactured by Merlin Gerin, it is showed how Solenarc technique enables specific problems to be solved that are set by the equipment of Eurodif plant at Tricastin and that represent constraints similar to those encountered with protective equipment for power station auxiliaries (high rated currents, long duration overloads, very high short-circuit currents, current breaks without natural passage through zero, etc.) [fr

The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

OpenAIRE

Artem Ganiyev; Jan Vitasek

2010-01-01

This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

Instrumentation in the Rapsodie test circuits of 1 and 10 MW - flow-meters, manometers, level indicators, blockage indicators; L'instrumentation dans les cilicuits d'essais rapsodie 1 et 10 MW - debitmetres, manometres, indicateurs de niveau, indicateurs de bouchage

Energy Technology Data Exchange (ETDEWEB)

Lisle, J.P. de; Lions, N [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1964-07-01

The main measuring instruments, which operate in the presence of liquid metals and which have been developed by the liquid metal section over the last few years, are electromagnetic flowmeters, differential manometers, level indicators and blockage indicators. We give here results obtained with these instruments during trial, in the 1 and 10 MW test circuits, together with the conclusions drawn about their possible use in the reactor Rapsodie, The flow rate measurements are carried out using electromagnetic flow meters with permanent magnets. We have studied more particularly the reliability of these instruments. The measurements matte show that the induction in the space between the poles is very constant with time and in the presence of the prevailing demagnetization phenomena to which the magnets are subjected. The differential manometers placed in the test circuits are very accurate. It is nevertheless necessary to carry out some technological modifications on them in order that they may operate satisfactorily over long periods. The continuous and discontinuous level-indicators tried out operate on the principle of a change in resistance. Studies carried out on the test loops of the reliability and of the accuracy of this equipment have shown the existence of phenomena convected with the condensation of sodium vapour on the upper parts of the reservoir, and have shown the importance of the condensed deposits when the oxygen content of the covering gas is appreciable. From the various blockage indicators tried out, the one chosen for equipping the reactor circuits is an automatic model with continuous recording. The development and testing of this apparatus has been going on for one year on an industrial scale circuit and has made it possible to show clearly an effect of a double blockage temperature. (authors) [French] Les principaux instruments de mesure, fonctionnant en presence de metal liquide, qui ont ete developpes et mis au point a la Section des Metaux

Peak reading detector circuit

International Nuclear Information System (INIS)

Courtin, E.; Grund, K.; Traub, S.; Zeeb, H.

1975-01-01

The peak reading detector circuit serves for picking up the instants during which peaks of a given polarity occur in sequences of signals in which the extreme values, their time intervals, and the curve shape of the signals vary. The signal sequences appear in measuring the foetal heart beat frequence from amplitude-modulated ultrasonic, electrocardiagram, and blood pressure signals. In order to prevent undesired emission of output signals from, e. g., disturbing intermediate extreme values, the circuit consists of the series connections of a circuit to simulate an ideal diode, a strong unit, a discriminator for the direction of charging current, a time-delay circuit, and an electronic switch lying in the decharging circuit of the storage unit. The time-delay circuit thereby causes storing of a preliminary maximum value being used only after a certain time delay for the emission of the output signal. If a larger extreme value occurs during the delay time the preliminary maximum value is cleared and the delay time starts running anew. (DG/PB) [de

Magnonic logic circuits

International Nuclear Information System (INIS)

Khitun, Alexander; Bao Mingqiang; Wang, Kang L

2010-01-01

We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

A new high-voltage level-shifting circuit for half-bridge power ICs

International Nuclear Information System (INIS)

Kong Moufu; Chen Xingbi

2013-01-01

In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well. (semiconductor integrated circuits)

The transfer function method for the evaluation of short-circuit tests and on-site diagnostics of power transformers; Die Uebertragungsfunktion als Methode zur Beurteilung der Stosskurzschlusspruefung und Vor-Ort-Isolationsdiagnose

Energy Technology Data Exchange (ETDEWEB)

Christian, J.; Feser, K. [Stuttgart Univ. (Germany). Inst. fuer Energieuebertragung und Hochspannungstechnik; Leibfried, T. [Siemens AG, Nuernberg (Germany). Geschaeftsgebiet Leistungstransformatoren; Jaeggi, F. [Aare-Tessin AG fuer Elektrizitaet, Olten (Switzerland)

1999-03-22

A short circuit test according to IEC 76-5 was performed on a 125 MVA, 245 kV/53 kV power transformer from the Siemens factory in Nuremberg at the Kema high power laboratory (Arnhem, Netherlands) in March 1997. Thereby, the transfer function method was examined as an additional method for evaluating the short-circuit test. The visual inspection of the transformer after returning to the Nuremberg factory carried out by engineers from Atel and Siemens and representatives of Kema showed no changes of the core and coil assembly. At the Flumenthal substation a second transformer of the same type was installed. Before commissioning, the transfer functions of both transformers have been measured. These measurements provide essential information concerning the comparability of measurements from different transformers and are the basis for measurements to be carried out in the future. (orig.) [Deutsch] Im Maerz 1997 wurde ein 125-MVA-Leistungstranformator aus dem Siemens Transformatorenwerk Nuernberg im Hochleistungslabor der Kema, Arnheim einer Stosskurzschlusspruefung unterzogen. Dabei wurde die Analyse der Uebertragungsfunktion des Transformators als zusaetzliche Methode zur Beurteilung der Stosskurzschlusspruefung untersucht. Der Aktivteil wurde danach im Herstellerwerk begutachtet. Dabei ergaben sich keine Beanstandungen. Im Umspannwerk Flumenthal wurde ein zweiter baugleicher Transformator installiert. Vor der Inbetriebnahme wurden zusaetzliche Vergleichsmessungen an den zwei baugleichen Transformatoren durchgefuehrt. (orig.)

Electrical Circuits and Water Analogies

Science.gov (United States)

Smith, Frederick A.; Wilson, Jerry D.

1974-01-01

Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

Optically controllable molecular logic circuits

International Nuclear Information System (INIS)

Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

2015-01-01

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

Pre-Service and In-Service Physics Teachers' Ideas about Simple Electric Circuits

Science.gov (United States)

Kucukozer, Huseyin; Demirci, Neset

2008-01-01

The aim of the study is to determine pre-service and high school physics teachers' ideas about simple electric circuits. In this study, a test containing eight questions related to simple electric circuits was given to the pre-service physics teachers (32 subjects) that had graduated from Balikesir University, Necatibey Faculty of Education, the…

Engine Tune-Up Service. Unit 4: Secondary Circuit. Posttests. Automotive Mechanics Curriculum.

Science.gov (United States)

Morse, David T.

This book of posttests is designed to accompany the Engine Tune-Up Service Student Guide for Unit 4, Secondary Circuit, available separately as CE 031 214. Focus of the posttests is testing and servicing the secondary ignition circuit. One multiple choice posttest is provided that covers the seven performance objectives contained in the unit. (No…

Interface Circuit For Printer Port

Science.gov (United States)

Tucker, Jerry H.; Yadlowsky, Ann B.

1991-01-01

Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

International Nuclear Information System (INIS)

Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

1996-01-01

In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

A novel on-chip high to low voltage power conversion circuit

International Nuclear Information System (INIS)

Wang Hui; Wang Songlin; Mou Zaixin; Guo Baolong; Lai Xinquan; Ye Qiang; Li Xianrui

2009-01-01

A novel power supply transform technique for high voltage IC based on the TSMC 0.6 μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm 2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/deg. C. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.

A novel on-chip high to low voltage power conversion circuit

Energy Technology Data Exchange (ETDEWEB)

Wang Hui; Wang Songlin; Mou Zaixin; Guo Baolong [Institute of Mechano-electronic Engineering, Xidian University, Xi' an 71007 (China); Lai Xinquan; Ye Qiang; Li Xianrui, E-mail: whui94@126.co [Institute of Electronic CAD, Xidian University, Xi' an 710071 (China)

2009-03-15

A novel power supply transform technique for high voltage IC based on the TSMC 0.6 mum BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm{sup 2} area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/deg. C. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.

Maximum Acceleration Recording Circuit

Science.gov (United States)

Bozeman, Richard J., Jr.

1995-01-01

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

Four-junction superconducting circuit

Science.gov (United States)

Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

2016-01-01

We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

On automatic synthesis of analog/digital circuits

Energy Technology Data Exchange (ETDEWEB)

Beiu, V.

1998-12-31

The paper builds on a recent explicit numerical algorithm for Kolmogorov`s superpositions, and will show that in order to synthesize minimum size (i.e., size-optimal) circuits for implementing any Boolean function, the nonlinear activation function of the gates has to be the identity function. Because classical and--or implementations, as well as threshold gate implementations require exponential size, it follows that size-optimal solutions for implementing arbitrary Boolean functions can be obtained using analog (or mixed analog/digital) circuits. Conclusions and several comments are ending the paper.

Control circuit for transformer relay

International Nuclear Information System (INIS)

Wyatt, G.A.

1984-01-01

A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

Chaotic behavior learning of Chua's circuit

International Nuclear Information System (INIS)

Sun Jian-Cheng

2012-01-01

Least-square support vector machines (LS-SVM) are applied for learning the chaotic behavior of Chua's circuit. The system is divided into three multiple-input single-output (MISO) structures and the LS-SVM are trained individually. Comparing with classical approaches, the proposed one reduces the structural complexity and the selection of parameters is avoided. Some parameters of the attractor are used to compare the chaotic behavior of the reconstructed and the original systems for model validation. Results show that the LS-SVM combined with the MISO can be trained to identify the underlying link among Chua's circuit state variables, and exhibit the chaotic attractors under the autonomous working mode

Modeling of Short-Circuit-Related Thermal Stress in Aged IGBT Modules

DEFF Research Database (Denmark)

Bahman, Amir Sajjad; Iannuzzo, Francesco; Uhrenfeldt, Christian

2017-01-01

In this paper, the thermal stress on bond wires of aged IGBT modules under short-circuit conditions has been studied with respect to different solder delamination levels. To ensure repeatable test conditions, ad-hoc DBC (direct bond copper) samples with delaminated solder layers have been purposely...... in the surface temperature distribution, which confirms the hypothesis that short-circuit events produce significantly uneven stresses on bond wires....

Prediction of Short-Circuit-Related Thermal Stress in Aged IGBT Modules

DEFF Research Database (Denmark)

Bahman, Amir Sajjad; Iannuzzo, Francesco; Uhrenfeldt, Christian

2016-01-01

In this paper, the thermal stress on bond wires of aged IGBT modules under short-circuit conditions has been studied with respect to different solder delamination levels. To ensure repeatable test conditions, ad-hoc DBC (direct bond copper) samples with delaminated solder layers have been purposely...... in the surface temperature distribution which confirms the hypothesis that short-circuit events produce significantly uneven stresses on bond wires....

Integrated coherent matter wave circuits

International Nuclear Information System (INIS)

Ryu, C.; Boshier, M. G.

2015-01-01

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

High voltage generator circuit with low power and high efficiency applied in EEPROM

International Nuclear Information System (INIS)

Liu Yan; Zhang Shilin; Zhao Yiqiang

2012-01-01

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

Science.gov (United States)

Burns, Bradley M.; Blalock, Norman N.

2010-01-01

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

30 CFR 77.506-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Science.gov (United States)

2010-07-01

... short circuit protection; minimum requirements. 77.506-1 Section 77.506-1 Mineral Resources MINE SAFETY...-1 Electric equipment and circuits; overload and short circuit protection; minimum requirements. Devices providing either short circuit protection or protection against overload shall conform to the...

Short-Circuit Robustness Assessment in Power Electronic Modules for Megawatt Applications

DEFF Research Database (Denmark)

Iannuzzo, Francesco

2016-01-01

In this paper, threats and opportunities in testing of megawatt power electronic modules under short circuit are presented and discussed, together with the introduction of some basic principles of non-destructive testing, a key technique to allow post-failure analysis. The non-destructive testing...