A high frequency test bench for rapid single-flux-quantum circuits

International Nuclear Information System (INIS)

Engseth, H; Intiso, S; Rafique, M R; Tolkacheva, E; Kidiyarova-Shevchenko, A

2006-01-01

We have designed and experimentally verified a test bench for high frequency testing of rapid single-flux-quantum (RSFQ) circuits. This test bench uses an external tunable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift register. The clock pattern is consequently shifted out at high speed and split to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed read-out electronics. The test bench consists of 158 Josephson junctions and the occupied area is 3300 x 660 μm 2 . It was experimentally verified up to 33 GHz with ± 21.7% margins on the global bias supply current

INTEGRATED SENSOR EVALUATION CIRCUIT AND METHOD FOR OPERATING SAID CIRCUIT

OpenAIRE

Krüger, Jens; Gausa, Dominik

2015-01-01

WO15090426A1 Sensor evaluation device and method for operating said device Integrated sensor evaluation circuit for evaluating a sensor signal (14) received from a sensor (12), having a first connection (28a) for connection to the sensor and a second connection (28b) for connection to the sensor. The integrated sensor evaluation circuit comprises a configuration data memory (16) for storing configuration data which describe signal properties of a plurality of sensor control signals (26a-c). T...

LS1 Report: short-circuit tests

CERN Multimedia

Katarina Anthony

2014-01-01

As the LS1 draws to an end, teams move from installation projects to a phase of intense testing. Among these are the so-called 'short-circuit tests'. Currently under way at Point 7, these tests verify the cables, the interlocks, the energy extraction systems, the power converters that provide current to the superconducting magnets and the cooling system.   Thermal camera images taken during tests at point 4 (IP4). Before putting beam into the LHC, all of the machine's hardware components need to be put to the test. Out of these, the most complicated are the superconducting circuits, which have a myriad of different failure modes with interlock and control systems. While these will be tested at cold - during powering tests to be done in August - work can still be done beforehand. "While the circuits in the magnets themselves cannot be tested at warm, what we can do is verify the power converter and the circuits right up to the place the cables go into the magn...

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Science.gov (United States)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

Power operated contact apparatus for superconductive circuit

Energy Technology Data Exchange (ETDEWEB)

Woods, D.C.; Efferson, K.R.

1989-10-10

This patent describes a power operated contact apparatus for extending and retracting one or more electrical leads into and out of a cryostat for making and breaking, at a cryogenic temperature, electrical contact with a superconductive circuit. It comprises at least one rigid elongated lead for extending into a cold space of the cryostat which is at or near a cryogenic temperature. The lead having an inner end and a outer end; a connector fixed at the inner end of the lead for making electrical contact in the cold space with a connector of the superconductive circuit; guide means journaling the lead for allowing the lead to move axially relative to the guide means and sealing against the lead; a foundation for sealed attachment to the cryostat and to the guide means so that the connector on the inner end of the lead is extendable into making electrical contact with the connector of the superconductive circuit in the cold space; power operated means mounted on the foundation and fixed to the outer end of the lead for extending and retracting the lead to and from making electrical contact with the superconductive circuit in the cold space; and means for de-icing the exterior of the leads and guide means when the leads are connected to the superconducting circuit.

Circuit breaker operation and potential failure modes during an earthquake

International Nuclear Information System (INIS)

Lambert, H.E.; Budnitz, R.J.

1987-01-01

This study addresses the effect of a strong-motion earthquake on circuit breaker operation. It focuses on the loss of offsite power (LOSP) transient caused by a strong-motion earthquake at the Zion Nuclear Power Plant. This paper also describes the operator action necessary to prevent core melt if the above circuit breaker failure modes occur simultaneously on three 4.16 KV buses. Numerous circuit breakers important to plant safety, such as circuit breakers to diesel generators and engineered safety systems (ESS), must open and/or close during this transient while strong motion is occurring. Potential seismically-induced circuit-breaker failures modes were uncovered while the study was conducted. These failure modes include: circuit breaker fails to close; circuit breaker trips inadvertently; circuit breaker fails to reclose after trip. The causes of these failure modes include: Relay chatter causes the circuit breaker to trip; Relay chatter causes anti-pumping relays to seal-in which prevents automatic closure of circuit breakers; Load sequencer failures. The incorporation of these failure modes as well as other instrumentation and control failures into a limited scope seismic probabilistic risk assessment is also discussed in this paper

FPGA based mixed-signal circuit novel testing techniques

International Nuclear Information System (INIS)

Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

2013-01-01

Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

A miniature microcontroller curve tracing circuit for space flight testing transistors.

Science.gov (United States)

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Testing methods of gaseous admixtures in HLMC circuits

International Nuclear Information System (INIS)

Shelemet'ev, V.M.; Martynov, P.N.; Askhadullin, R.Sh.; Storozhenko, A.N.; Sadovnichij, R.P.; Ivanov, I.I.

2014-01-01

Control of gas phase is the effective method for state diagnostics of circuit of nuclear power facilities with heavy liquid metal coolants. Use of developing in IPPE solid electrolyte and conductometric oxygen and hydrogen sensors, which are set directly in gas system of the primary circuit, allows to maintain continuously control of oxygen and hydrogen content as well as operational efficiency and accuracy of these parameters determination under various situations related with oxygen and hydrogen insertion into circuit. Sensors ensure long-term safe operation under extreme conditions of high temperatures, pressures, humidity, etc., and are advanced devices for application in nuclear power facilities with heavy liquid metal coolants [ru

E-learning platform for automated testing of electronic circuits using signature analysis method

Science.gov (United States)

Gherghina, Cǎtǎlina; Bacivarov, Angelica; Bacivarov, Ioan C.; Petricǎ, Gabriel

2016-12-01

Dependability of electronic circuits can be ensured only through testing of circuit modules. This is done by generating test vectors and their application to the circuit. Testability should be viewed as a concerted effort to ensure maximum efficiency throughout the product life cycle, from conception and design stage, through production to repairs during products operating. In this paper, is presented the platform developed by authors for training for testability in electronics, in general and in using signature analysis method, in particular. The platform allows highlighting the two approaches in the field namely analog and digital signature of circuits. As a part of this e-learning platform, it has been developed a database for signatures of different electronic components meant to put into the spotlight different techniques implying fault detection, and from this there were also self-repairing techniques of the systems with this kind of components. An approach for realizing self-testing circuits based on MATLAB environment and using signature analysis method is proposed. This paper analyses the benefits of signature analysis method and simulates signature analyzer performance based on the use of pseudo-random sequences, too.

Addressable-Matrix Integrated-Circuit Test Structure

Science.gov (United States)

Sayah, Hoshyar R.; Buehler, Martin G.

1991-01-01

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

30 CFR 56.6407 - Circuit testing.

Science.gov (United States)

2010-07-01

... series or the resistance of multiple balanced series to be connected in parallel prior to their... detonator series. (d) Total blasting circuit resistance prior to connection to the power source. Nonelectric... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit testing. 56.6407 Section 56.6407...

Test signal generation for analog circuits

Directory of Open Access Journals (Sweden)

B. Burdiek

2003-01-01

Full Text Available In this paper a new test signal generation approach for general analog circuits based on the variational calculus and modern control theory methods is presented. The computed transient test signals also called test stimuli are optimal with respect to the detection of a given fault set by means of a predefined merit functional representing a fault detection criterion. The test signal generation problem of finding optimal test stimuli detecting all faults form the fault set is formulated as an optimal control problem. The solution of the optimal control problem representing the test stimuli is computed using an optimization procedure. The optimization procedure is based on the necessary conditions for optimality like the maximum principle of Pontryagin and adjoint circuit equations.

The testing of generator circuit-breakers

NARCIS (Netherlands)

Smeets, R.P.P.; Linden, van der W.A.

1998-01-01

Generator circuit-breakers face much higher current and voltage stress than distribution switchgear. This has led to a special standard (ANSI C37.013). Strictly in accordance with this standard's requirements, test circuits and parameters for a 100 kA and 120 kA (25.3 kV) SF6 generator

Electric circuit breaker comprising a plurality of vacuum interrupters simultaneously operated by a common operator

Science.gov (United States)

Barkan, Philip; Imam, Imdad

1980-01-01

This circuit breaker comprises a plurality of a vacuum-type circuit interrupters, each having a movable contact rod. A common operating device for the interrupters comprises a linearly-movable operating member. The interrupters are mounted at one side of the operating member with their movable contact rods extending in a direction generally toward the operating member. Means is provided for mechanically coupling the operating member to the contact rods, and this means comprises a plurality of insulating operating rods, each connected at one end to the operating member and at its opposite end to one of the movable contact rods. The operating rods are of substantially equal length and have longitudinal axes that converge and intersect at substantially a common point.

Elements configuration of the open lead test circuit

International Nuclear Information System (INIS)

Fukuzaki, Yumi; Ono, Akira

2016-01-01

In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a test circuit in the past. This paper propose elements configuration of the test circuit.

Elements configuration of the open lead test circuit

Energy Technology Data Exchange (ETDEWEB)

Fukuzaki, Yumi, E-mail: 14514@sr.kagawa-nct.ac.jp [Advanced course of Electronics, Information and Communication Engineering, National Institute of Technology, Kagawa College, 551 Koda, Mitoyo, Kagawa (Japan); Ono, Akira [Department of Communication Network Engineering, National Institute of Technology, Kagawa College, 551 Koda, Mitoyo, Kagawa (Japan)

2016-07-06

In the field of electronics, small electronic devices are widely utilized because they are easy to carry. The devices have various functions by user’s request. Therefore, the lead’s pitch or the ball’s pitch have been narrowed and high-density printed circuit board has been used in the devices. Use of the ICs which have narrow lead pitch makes normal connection difficult. When logic circuits in the devices are fabricated with the state-of-the-art technology, some faults have occurred more frequently. It can be divided into types of open faults and short faults. We have proposed a new test method using a test circuit in the past. This paper propose elements configuration of the test circuit.

Operator Spreading in Random Unitary Circuits

Science.gov (United States)

Nahum, Adam; Vijay, Sagar; Haah, Jeongwan

2018-04-01

Random quantum circuits yield minimally structured models for chaotic quantum dynamics, which are able to capture, for example, universal properties of entanglement growth. We provide exact results and coarse-grained models for the spreading of operators by quantum circuits made of Haar-random unitaries. We study both 1 +1 D and higher dimensions and argue that the coarse-grained pictures carry over to operator spreading in generic many-body systems. In 1 +1 D , we demonstrate that the out-of-time-order correlator (OTOC) satisfies a biased diffusion equation, which gives exact results for the spatial profile of the OTOC and determines the butterfly speed vB. We find that in 1 +1 D , the "front" of the OTOC broadens diffusively, with a width scaling in time as t1 /2. We address fluctuations in the OTOC between different realizations of the random circuit, arguing that they are negligible in comparison to the broadening of the front within a realization. Turning to higher dimensions, we show that the averaged OTOC can be understood exactly via a remarkable correspondence with a purely classical droplet growth problem. This implies that the width of the front of the averaged OTOC scales as t1 /3 in 2 +1 D and as t0.240 in 3 +1 D (exponents of the Kardar-Parisi-Zhang universality class). We support our analytic argument with simulations in 2 +1 D . We point out that, in two or higher spatial dimensions, the shape of the spreading operator at late times is affected by underlying lattice symmetries and, in general, is not spherical. However, when full spatial rotational symmetry is present in 2 +1 D , our mapping implies an exact asymptotic form for the OTOC, in terms of the Tracy-Widom distribution. For an alternative perspective on the OTOC in 1 +1 D , we map it to the partition function of an Ising-like statistical mechanics model. As a result of special structure arising from unitarity, this partition function reduces to a random walk calculation which can be

Electrical short circuit and current overload tests on aircraft wiring

Science.gov (United States)

Cahill, Patricia

1995-01-01

The findings of electrical short circuit and current overload tests performed on commercial aircraft wiring are presented. A series of bench-scale tests were conducted to evaluate circuit breaker response to overcurrent and to determine if the wire showed any visible signs of thermal degradation due to overcurrent. Three types of wire used in commercial aircraft were evaluated: MIL-W-22759/34 (150 C rated), MIL-W-81381/12 (200 C rated), and BMS 1360 (260 C rated). A second series of tests evaluated circuit breaker response to short circuits and ticking faults. These tests were also meant to determine if the three test wires behaved differently under these conditions and if a short circuit or ticking fault could start a fire. It is concluded that circuit breakers provided reliable overcurrent protection. Circuit breakers may not protect wire from ticking faults but can protect wire from direct shorts. These tests indicated that the appearance of a wire subjected to a current that totally degrades the insulation looks identical to a wire subjected to a fire; however the 'fire exposed' conductor was more brittle than the conductor degraded by overcurrent. Preliminary testing indicates that direct short circuits are not likely to start a fire. Preliminary testing indicated that direct short circuits do not erode insulation and conductor to the extent that ticking faults did. Circuit breakers may not safeguard against the ignition of flammable materials by ticking faults. The flammability of materials near ticking faults is far more important than the rating of the wire insulation material.

Demodulation Radio Frequency Interference Effects in Operational Amplifier Circuits

Science.gov (United States)

Sutu, Yue-Hong

A series of investigations have been carried out to determine RFI effects in analog circuits using monolithic integrated operational amplifiers (op amps) as active devices. The specific RFI effect investigated is how amplitude-modulated (AM) RF signals are demodulated in op amp circuits to produce undesired low frequency responses at AM-modulation frequency. The undesired demodulation responses were shown to be characterized by a second-order nonlinear transfer function. Four representative op amp types investigated were the 741 bipolar op amp, the LM10 bipolar op amp, the LF355 JFET-Bipolar op amp, and the CA081 MOS-Bipolar op amp. Two op amp circuits were investigated. The first circuit was a noninverting unity voltage gain buffer circuit. The second circuit was an inverting op amp configuration. In the second circuit, the investigation includes the effects of an RFI suppression capacitor in the feedback path. Approximately 30 units of each op amp type were tested to determine the statistical variations of RFI demodulation effects in the two op amp circuits. The Nonlinear Circuit Analysis Program, NCAP, was used to simulate the demodulation RFI response. In the simulation, the op amp was replaced with its incremental macromodel. Values of macromodel parameters were obtained from previous investigations and manufacturer's data sheets. Some key results of this work are: (1) The RFI demodulation effects are 10 to 20 dB lower in CA081 and LF355 FET-bipolar op amp than in 741 and LM10 bipolar op amp except above 40 MHz where the LM10 RFI response begins to approach that of CA081. (2) The experimental mean values for 30 741 op amps show that RFI demodulation responses in the inverting amplifier with a 27 pF feedback capacitor were suppressed from 10 to 35 dB over the RF frequency range 0.1 to 150 MHz except at 0.15 MHz where only 3.5 dB suppression was observed. (3) The NCAP program can predict RFI demodulation responses in 741 and LF355 unity gain buffer circuits

Testing of 800 and 1200 kV class circuit breakers

NARCIS (Netherlands)

Smeets, R.P.P.; Kuivenhoven, S.; Hofstee, A.B.

2011-01-01

The most critical transient a circuit breaker has to endure during its operation is the transient recovery voltage (TRV), initiated by the electric power system as a natural reaction on current interruption. For circuit breakers intended to operate in ultra-high voltage systems (with rated voltage

Proposed minimum requirements for the operational characteristics and testing of closed circuit life support system control electronics.

Science.gov (United States)

Kirk, J C

1998-01-01

The popularization and transformation of scuba diving into a broadly practiced sport has served to ignite the interest of technically oriented divers into ever more demanding areas. This, along with the gradual release of military data, equipment, and techniques of closed circuit underwater breathing apparatus, has resulted in a virtual explosion of semiclosed and closed circuit systems for divers. Although many of these systems have been carefully thought out by capable designers, the impulse to rush to market with equipment that has not been fully developed and carefully tested is irresistible to marketers. In addition, the presence of systems developed by well-intentioned and otherwise competent designers who are, nonetheless, inexperienced in the field of life support can result in the sale of failure-prone equipment to divers who lack the knowledge and skills to identify deficiencies before disaster occurs. For this reason, a set of industry standards establishing minimum requirements and testing is needed to guide the designers of this equipment, and to protect the user community from incomplete or inadequate design. Many different technologies go into the development of closed circuit scuba. One key area is the design of electronics to monitor and maintain the critical gas mixtures of the closed circuit loop. Much of the system reliability and inherent danger is resident in the design of the circuitry and the software (if any) that runs it. This article will present a set of proposed minimum requirements, with the goal of establishing a dialog for the creation of guidelines for the classification, rating, design, and testing of embedded electronics for life support systems used in closed circuit applications. These guidelines will serve as the foundation for the later creation of a set of industry specifications.

Wafer-level testing and test during burn-in for integrated circuits

CERN Document Server

Bahukudumbi, Sudarshan

2010-01-01

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

Design, Analysis and Test of Logic Circuits Under Uncertainty

CERN Document Server

Krishnaswamy, Smita; Hayes, John P

2013-01-01

Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...

Device for testing continuity and/or short circuits in a cable

Science.gov (United States)

Hayhurst, Arthur R. (Inventor)

1995-01-01

A device for testing current paths is attachable to a conductor. The device automatically checks the current paths of the conductor for continuity of a center conductor, continuity of a shield and a short circuit between the shield and the center conductor. The device includes a pair of connectors and a circuit to provide for testing of the conductive paths of the cable. The pair of connectors electrically connects the conductive paths of a cable to be tested with the circuit paths of the circuit. The circuit paths in the circuit include indicators to simultaneously indicate the results of the testing.

Feedback analysis of transimpedance operational amplifier circuits

DEFF Research Database (Denmark)

Bruun, Erik

1993-01-01

The transimpedance or current feedback operational amplifier (CFB op-amp) is reviewed and compared to a conventional voltage mode op-amp using an analysis emphasizing the basic feedback characteristics of the circuit. With this approach the paradox of the constant bandwidth obtained from CFB op...

Economic testing of large integrated switching circuits - a challenge to the test engineer

International Nuclear Information System (INIS)

Kreinberg, W.

1978-01-01

With reference to large integrated switching circuits, one can use an incoming standard programme test or the customer's switching circuits. The author describes the development of suitable, extensive and economical test programmes. (orig.) [de

Integrated circuits and logic operations based on single-layer MoS2.

Science.gov (United States)

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

New reactor safety circuit for low-power-level operation

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

1978-01-01

In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

Life testing of a low voltage air circuit breaker

International Nuclear Information System (INIS)

Subudhi, M.

1991-01-01

ADS-416 low voltage air circuit breaker manufacture by Westinghouse was mechanically cycled to identify age-related degradation in various breaker subcomponents, in particular, the power-operating mechanism. This accelerated aging test was performed on one breaker unit for over 36,000 cycles. Three separate pole shafts, one with a 60 degree weld, one with a 120 degree weld and one with a 180 degree weld in the third pole lever were used to characterize the cracking in these welds. In addition, during the testing, three different operating mechanisms and several other parts were replaced as they degraded to an inoperable condition. Of the seven welds on the pole shaft, two were found to be the critical ones whose fracture can result in misalignment problems of the pole levers. These failures, in turn can lead to many other problems with the operating mechanism including the burn-out of coils, excessive wear in certain parts and over-stressed linkages. Furthermore, the limiting service life of a number of subcomponents of the power-operated mechanism, including the operating mechanism itself, were assessed. 1 ref., 3 figs

Test Structures For Bumpy Integrated Circuits

Science.gov (United States)

Buehler, Martin G.; Sayah, Hoshyar R.

1989-01-01

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Modeling a verification test system for mixed-signal circuits

NARCIS (Netherlands)

San Segundo Bello, D.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.

In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block

Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

Science.gov (United States)

Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

2012-10-21

Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

Apparatus and method for defect testing of integrated circuits

Science.gov (United States)

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Investigation on the Short Circuit Safe Operation Area of SiC MOSFET Power Modules

DEFF Research Database (Denmark)

Reigosa, Paula Diaz; Luo, Haoze; Iannuzzo, Francesco

2016-01-01

This paper gives a better insight of the short circuit capability of state-of-the-art SiC MOSFET power modules rated at 1.2 kV by highlighting the physical limits under different operating conditions. Two different failure mechanisms have been identified, both reducing the short-circuit capability...... of SiC power modules in respect to discrete SiC devices. Based on such failure mechanisms, two short circuit criteria (i.e., short circuit current-based criterion and gate voltage-based criterion) are proposed in order to ensure their robustness under short-circuit conditions. A Safe Operation Area (SOA...

Quantum circuits cannot control unknown operations

International Nuclear Information System (INIS)

Araújo, Mateus; Feix, Adrien; Costa, Fabio; Brukner, Časlav

2014-01-01

One of the essential building blocks of classical computer programs is the ‘if’ clause, which executes a subroutine depending on the value of a control variable. Similarly, several quantum algorithms rely on applying a unitary operation conditioned on the state of a control system. Here we show that this control cannot be performed by a quantum circuit if the unitary is completely unknown. The task remains impossible even if we allow the control to be done modulo a global phase. However, this no-go theorem does not prevent implementing quantum control of unknown unitaries in practice, as any physical implementation of an unknown unitary provides additional information that makes the control possible. We then argue that one should extend the quantum circuit formalism to capture this possibility in a straightforward way. This is done by allowing unknown unitaries to be applied to subspaces and not only to subsystems. (paper)

Designing reversible arithmetic, logic circuit to implement micro-operation in quantum computation

International Nuclear Information System (INIS)

Kalita, Gunajit; Saikia, Navajit

2016-01-01

The futuristic computing is desired to be more power full with low-power consumption. That is why quantum computing has been a key area of research for quite some time and is getting more and more attention. Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times. Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance. In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer. The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations. The quantum costs of these designs are comparable. Many of the implemented micro-operations are not seen in previous literatures. The performances of the proposed circuits are compared with existing designs wherever available. (paper)

Influence of Insulation Monitoring Devices on the Operation of DC Control Circuits

Energy Technology Data Exchange (ETDEWEB)

Olszowiec, Piotr, E-mail: olpio@o2.pl [Erea Polaniec (Poland)

2017-03-15

The insulation level of DC control circuits is an important safety-critical factor and, thus, should be subject to continuous and periodic monitoring. The methods used for monitoring the insulation in live circuits may, however, disturb the reliable operation of control relays. The risks of misoperation and failure to reset of relays posed by the operation of various insulation monitoring and fault location systems are evaluated.

A Current-Mode Common-Mode Feedback Circuit (CMFB) with Rail-to-Rail Operation

Science.gov (United States)

Suadet, Apirak; Kasemsuwan, Varakorn

2011-03-01

This paper presents a current-mode common-mode feedback (CMFB) circuit with rail-to-rail operation. The CMFB is a stand-alone circuit, which can be connected to any low voltage transconductor without changing or upsetting the existing circuit. The proposed CMFB employs current mirrors, operating as common-mode detector and current amplifier to enhance the loop gain of the CMFB. The circuit employs positive feedback to enhance the output impedance and gain. The circuit has been designed using a 0.18 μm CMOS technology under 1V supply and analyzed using HSPICE with BSIM3V3 device models. A pseudo-differential amplifier using two common sources and the proposed CMFB shows rail to rail output swing (± 0.7 V) with low common-mode gain (-36 dB) and power dissipation of 390 μW.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

Science.gov (United States)

Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

2015-11-01

We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80-120%, with respect to the designed bias currents.

Cell short circuit, preshort signature

Science.gov (United States)

Lurie, C.

1980-01-01

Short-circuit events observed in ground test simulations of DSCS-3 battery in-orbit operations are analyzed. Voltage signatures appearing in the data preceding the short-circuit event are evaluated. The ground test simulation is briefly described along with performance during reconditioning discharges. Results suggest that a characteristic signature develops prior to a shorting event.

Energy-efficient neuron, synapse and STDP integrated circuits.

Science.gov (United States)

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Test generation for digital circuits using parallel processing

Science.gov (United States)

Hartmann, Carlos R.; Ali, Akhtar-Uz-Zaman M.

1990-12-01

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

International Nuclear Information System (INIS)

Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

2015-01-01

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

Energy Technology Data Exchange (ETDEWEB)

Yamada, Takahiro, E-mail: yamada-takahiro@aist.go.jp [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Maezawa, Masaaki [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Urano, Chiharu [National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Central 3, Umezono 1-1-1, Tsukuba, Ibaraki 305-8563 (Japan)

2015-11-15

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions

Directory of Open Access Journals (Sweden)

Philip G. Neudeck

2016-12-01

Full Text Available The prolonged operation of semiconductor integrated circuits (ICs needed for long-duration exploration of the surface of Venus has proven insurmountably challenging to date due to the ∼ 460 °C, ∼ 9.4 MPa caustic environment. Past and planned Venus landers have been limited to a few hours of surface operation, even when IC electronics needed for basic lander operation are protected with heavily cumbersome pressure vessels and cooling measures. Here we demonstrate vastly longer (weeks electrical operation of two silicon carbide (4H-SiC junction field effect transistor (JFET ring oscillator ICs tested with chips directly exposed (no cooling and no protective chip packaging to a high-fidelity physical and chemical reproduction of Venus’ surface atmosphere. This represents more than 100-fold extension of demonstrated Venus environment electronics durability. With further technology maturation, such SiC IC electronics could drastically improve Venus lander designs and mission concepts, fundamentally enabling long-duration enhanced missions to the surface of Venus.

Life testing of a low voltage air circuit breaker

International Nuclear Information System (INIS)

Subudhi, M.; Aggarwal, S.

1992-01-01

A DS-416 low voltage air circuit breaker manufactured by Westinghouse was mechanically cycled to identify age-related degradation in the various breaker subcomponents, specifically the power-operated mechanism. This accelerated aging test was performed on one breaker unit for over 36,000 cycles. Three separate pole shafts, one with a 60-degree weld, one with a 120-degree weld, and one with a 180-degree weld in the third pole lever were used to characterize cracking in the welds. In addition, during the testing three different operating mechanisms and several other parts were replaced as they became inoperable. Among the seven welds on the pole shaft, number-sign 1 and number-sign 3 were found to be critical ones whose fracture can result in misalignment of the pole levers. This can lead to problems with the operating mechanism, including the burning of coils, excessive wear in certain parts, and overstressed linkages. Furthermore, the limiting service life of a number of subcomponents of the power-operated mechanism, including the operating mechanism itself, were assessed. Based on these findings, suggestions are provided to alleviate the age-related degradation that could occur as a result of normal closing and opening of the breaker contacts during its service life. Also, cause and effect analyses of various age-related degradation in various breaker parts are discussed

Laser system for testing radiation imaging detector circuits

Science.gov (United States)

Zubrzycka, Weronika; Kasinski, Krzysztof

2015-09-01

Performance and functionality of radiation imaging detector circuits in charge and position measurement systems need to meet tight requirements. It is therefore necessary to thoroughly test sensors as well as read-out electronics. The major disadvantages of using radioactive sources or particle beams for testing are high financial expenses and limited accessibility. As an alternative short pulses of well-focused laser beam are often used for preliminary tests. There are number of laser-based devices available on the market, but very often their applicability in this field is limited. This paper describes concept, design and validation of laser system for testing silicon sensor based radiation imaging detector circuits. The emphasis is put on keeping overall costs low while achieving all required goals: mobility, flexible parameters, remote control and possibility of carrying out automated tests. The main part of the developed device is an optical pick-up unit (OPU) used in optical disc drives. The hardware includes FPGA-controlled circuits for laser positioning in 2 dimensions (horizontal and vertical), precision timing (frequency and number) and amplitude (diode current) of short ns-scale (3.2 ns) light pulses. The system is controlled via USB interface by a dedicated LabVIEW-based application enabling full manual or semi-automated test procedures.

The life test of a DC circuit breaker of tokamak device JT-60 for a nuclear fusion research

International Nuclear Information System (INIS)

Shimada, Ryuichi; Tani, Keiji; Kishimoto, Hiroshi; Tamura, Sanae; Yanabu, Satoru.

1979-01-01

In the Tokamak devices for nuclear fusion research, the construction of the current transformer circuits having plasma as the secondary circuit and the change of the primary circuit current are necessary for generating current in the plasma. This is considered to be fairly difficult in practice if conventional methods using capacitor discharge and iron core coils are employed. Considering such circumstances, it was decided for JT-60 to use an air-core current transformer coil and to employ the method of storing energy in the form of current in the coil inductance instead of a capacitor. For this reason, a DC circuit breaker is required to interrupt coil current. The authors improved an AV vacuum breaker, which had been developed as the vacuum breaker of longitudinal magnetic field type applying a magnetic field in parallel with an arc, to get the one for DC circuit for the purpose of applying it to JT-60. In this paper, the operational characteristic of the DC breaker is described, the construction and function of the life test circuit is explained, and the test results are reported. Finally, interruptions of 10,000 times at 20 kA were carried out. It is successful that the restrike of arc occurring during tens of milli-seconds after interruptions was improved to 0.05% or less for 10,000 times operations. Further, it was found that the generation of arc restrike can be reduced practically to zero with two breakers in series. (Wakatsuki, Y.)

Oscillation-based test in mixed-signal circuits

CERN Document Server

Sánchez, Gloria Huertas; Rueda, Adoración Rueda

2007-01-01

This book presents the development and experimental validation of the structural test strategy called Oscillation-Based Test - OBT in short. The results presented here assert, not only from a theoretical point of view, but also based on a wide experimental support, that OBT is an efficient defect-oriented test solution, complementing the existing functional test techniques for mixed-signal circuits.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

Science.gov (United States)

Spry, David; Neudeck, Phil; Chen, Liangyu; Chang, Carl; Lukco, Dorothy; Beheim, Glenn M

2016-01-01

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

Digital logic circuit test

Energy Technology Data Exchange (ETDEWEB)

Yun, Gil Jung; Yang, Hong Young

2011-03-15

This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

Science.gov (United States)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Optimization of the powering tests of the LHC superconducting circuits

CERN Document Server

Bellesia, B; Denz, R; Fernandez-Robles, C; Pojer, M; Saban, R; Schmidt, R; Solfaroli Camillocci, M; Thiesen, H; Vergara Fernández, A

2010-01-01

The Large Hadron Collider has (LHC) 1572 superconducting circuits which are distributed along the eight 3.5 km LHC sectors [1]. Time and resources during the commissioning of the LHC technical systems were mostly consumed by the powering tests of each circuit. The tests consisted in carrying out several powering cycles at different current levels for each superconducting circuit. The Hardware Commissioning Coordination was in charge of planning, following up and piloting the execution of the test program. The first powering test campaign was carried out in summer 2007 for sector 7-8 with an expected duration of 12 weeks. The experience gained during these tests was used by the commissioning team for minimising the duration of the following powering campaigns to comply with the stringent LHC project deadlines. Improvements concerned several areas: strategy, procedures, control tools, automatization, and resource allocation led to an average daily test rate increase from 25 to 200 tests per day. This paper desc...

Testing and verification of a novel single-channel IGBT driver circuit

OpenAIRE

Lukić, Milan; Ninković, Predrag

2016-01-01

This paper presents a novel single-channel IGBT driver circuit together with a procedure for testing and verification. It is based on a specialized integrated circuit with complete range of protective functions. Experiments are performed to test and verify its behaviour. Experimental results are presented in the form of oscilloscope recordings. It is concluded that the new driver circuit is compatible with modern IGBT transistors and power converter demands and that it can be applied in new d...

Resonant magnetoelectric response of composite cantilevers: Theory of short vs. open circuit operation and layer sequence effects

Directory of Open Access Journals (Sweden)

Matthias C. Krantz

2015-11-01

Full Text Available The magnetoelectric effect in layered composite cantilevers consisting of strain coupled layers of magnetostrictive (MS, piezoelectric (PE, and substrate materials is investigated for magnetic field excitation at bending resonance. Analytic theories are derived for the transverse magnetoelectric (ME response in short and open circuit operation for three different layer sequences and results presented and discussed for the FeCoBSi-AlN-Si and the FeCoBSi-PZT-Si composite systems. Response optimized PE-MS layer thickness ratios are found to greatly change with operation mode shifting from near equal MS and PE layer thicknesses in the open circuit mode to near vanishing PE layer thicknesses in short circuit operation for all layer sequences. In addition the substrate layer thickness is found to differently affect the open and short circuit ME response producing shifts and reversal between ME response maxima depending on layer sequence. The observed rich ME response behavior for different layer thicknesses, sequences, operating modes, and PE materials can be explained by common neutral plane effects and different elastic compliance effects in short and open circuit operation.

Statistics for demodulation RFI in inverting operational amplifier circuits

Science.gov (United States)

Sutu, Y.-H.; Whalen, J. J.

An investigation was conducted with the objective to determine statistical variations for RFI demodulation responses in operational amplifier (op amp) circuits. Attention is given to the experimental procedures employed, a three-stage op amp LED experiment, NCAP (Nonlinear Circuit Analysis Program) simulations of demodulation RFI in 741 op amps, and a comparison of RFI in four op amp types. Three major recommendations for future investigations are presented on the basis of the obtained results. One is concerned with the conduction of additional measurements of demodulation RFI in inverting amplifiers, while another suggests the employment of an automatic measurement system. It is also proposed to conduct additional NCAP simulations in which parasitic effects are accounted for more thoroughly.

A Short-Circuit Safe Operation Area Identification Criterion for SiC MOSFET Power Modules

DEFF Research Database (Denmark)

Reigosa, Paula Diaz; Iannuzzo, Francesco; Luo, Haoze

2017-01-01

This paper proposes a new method for the investigation of the short-circuit safe operation area (SCSOA) of state-of-the-art SiC MOSFET power modules rated at 1.2 kV based on the variations in SiC MOSFET electrical parameters (e.g., short-circuit current and gate–source voltage). According...... to the experimental results, two different failure mechanisms have been identified, both reducing the short-circuit capability of SiC power modules with respect to discrete SiC devices. Based on such failure mechanisms, two short-circuit safety criteria have been formulated: 1) the short-circuit...

Approaching Repetitive Short Circuit Tests on MW-Scale Power Modules by means of an Automatic Testing Setup

DEFF Research Database (Denmark)

Reigosa, Paula Diaz; Wang, Huai; Iannuzzo, Francesco

2016-01-01

An automatic testing system to perform repetitive short-circuit tests on megawatt-scale IGBT power modules is pre-sented and described in this paper, pointing out the advantages and features of such testing approach. The developed system is based on a non-destructive short-circuit tester, which has...

Hydraulically-activated operating system for an electric circuit breaker

Science.gov (United States)

Imam, Imdad; Barkan, Philip

1979-01-01

This operating system comprises a fluid motor having a piston, a breaker-opening space at one side of the piston, and a breaker-closing space at its opposite side. An accumulator freely communicates with the breaker-opening space for supplying pressurized fluid thereto during a circuit-breaker opening operation. A normally-closed valve located on the breaker-closing-side of the piston is openable to release liquid from the breaker-closing space so that pressurized liquid in the breaker-opening space can drive the piston in an opening direction. Means is provided for restoring the valve to its closed position following the circuit-breaker opening operation. An impeded passage affords communication between the accumulator and the breaker-closing space to allow pressurized liquid to flow from the accumulator to the breaker-closing space and develop a pressure therein substantially equal to accumulator pressure when the valve is restored to closed position following breaker-opening. This passage is so impeded that the flow therethrough from the accumulator into the breaker-closing space is sufficiently low during initial opening motion of the piston through a substantial portion of its opening stroke as to avoid interference with said initial opening motion of the piston.

Testing and verification of a novel single-channel IGBT driver circuit

Directory of Open Access Journals (Sweden)

Lukić Milan

2016-01-01

Full Text Available This paper presents a novel single-channel IGBT driver circuit together with a procedure for testing and verification. It is based on a specialized integrated circuit with complete range of protective functions. Experiments are performed to test and verify its behaviour. Experimental results are presented in the form of oscilloscope recordings. It is concluded that the new driver circuit is compatible with modern IGBT transistors and power converter demands and that it can be applied in new designs. It is a part of new 20kW industrial-grade boost converter.

Minimizing time for test in integrated circuit

OpenAIRE

Andonova, A. S.; Dimitrov, D. G.; Atanasova, N. G.

2004-01-01

The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimisation algorithm. A prototype of the proposed approach was tested on 1SCAS standard benchmarks and theexperimental results s...

Experimental Study of WBFC method for testing electromagnetic immunity of integrated circuits

OpenAIRE

香川, 直己; カガワ, ナオキ; Naoki, KAGAWA

2004-01-01

The author made a workbench faraday cage, WBFC, in order to estimate performance of the WBFC method for the measurement of common mode noise immunity of integrated circuits. In this report, characteristics of the constructed workbench faraday cage and results of experimental study of effects of the common mode noise on a circuit board including an electronic device are shown. Selected DUT, LM324 is popular operational amplifier for electrical circuits in vehicles.

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Chang, Carl W.; Lukco, Dorothy; Beheim, Glenn M.

2016-01-01

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Modeling of electrical and mesoscopic circuits at quantum nanoscale from heat momentum operator

Science.gov (United States)

El-Nabulsi, Rami Ahmad

2018-04-01

We develop a new method to study electrical circuits at quantum nanoscale by introducing a heat momentum operator which reproduces quantum effects similar to those obtained in Suykens's nonlocal-in-time kinetic energy approach for the case of reversible motion. The series expansion of the heat momentum operator is similar to the momentum operator obtained in the framework of minimal length phenomenologies characterized by the deformation of Heisenberg algebra. The quantization of both LC and mesoscopic circuits revealed a number of motivating features like the emergence of a generalized uncertainty relation and a minimal charge similar to those obtained in the framework of minimal length theories. Additional features were obtained and discussed accordingly.

Development, testing, and demonstration of an optimal fine coal cleaning circuit

International Nuclear Information System (INIS)

Mishra, M.; Placha, M.; Bethell, P.

1995-01-01

The overall objective of this project is to improve the efficiency of fine coal cleaning. The project will be completed in two phases: bench-scale testing and demonstration of four advanced flotation cells and; in-plant proof-of-concept (POC) pilot plant testing of two flotation cells individually and in two-stage combinations. The goal is to ascertain if a two-stage circuit can result in reduced capital and operating costs while achieving improved separation efficiency. The plant selected for this project, Cyprus Emerald Coal Preparation plant, cleans 1200 tph of raw coal. The plant produces approximately 4 million tonnes of clean coal per year at an average as received energy content of 30.2 MJ/Kg (13,000 Btu/lb)

Development, testing, and demonstration of an optimal fine coal cleaning circuit

Energy Technology Data Exchange (ETDEWEB)

Mishra, M.; Placha, M.; Bethell, P. [and others

1995-11-01

The overall objective of this project is to improve the efficiency of fine coal cleaning. The project will be completed in two phases: bench-scale testing and demonstration of four advanced flotation cells and; in-plant proof-of-concept (POC) pilot plant testing of two flotation cells individually and in two-stage combinations. The goal is to ascertain if a two-stage circuit can result in reduced capital and operating costs while achieving improved separation efficiency. The plant selected for this project, Cyprus Emerald Coal Preparation plant, cleans 1200 tph of raw coal. The plant produces approximately 4 million tonnes of clean coal per year at an average as received energy content of 30.2 MJ/Kg (13,000 Btu/lb).

Simulation of TunneLadder traveling-wave tube cold-test characteristics: Implementation of the three-dimensional, electromagnetic circuit analysis code micro-SOS

Science.gov (United States)

Kory, Carol L.; Wilson, Jeffrey D.

1993-01-01

The three-dimensional, electromagnetic circuit analysis code, Micro-SOS, can be used to reduce expensive time-consuming experimental 'cold-testing' of traveling-wave tube (TWT) circuits. The frequency-phase dispersion characteristics and beam interaction impedance of a TunneLadder traveling-wave tube slow-wave structure were simulated using the code. When reasonable dimensional adjustments are made, computer results agree closely with experimental data. Modifications to the circuit geometry that would make the TunneLadder TWT easier to fabricate for higher frequency operation are explored.

Comminution circuits for compact itabirites

Directory of Open Access Journals (Sweden)

Pedro Ferreira Pinto

Full Text Available Abstract In the beneficiation of compact Itabirites, crushing and grinding account for major operational and capital costs. As such, the study and development of comminution circuits have a fundamental importance for feasibility and optimization of compact Itabirite beneficiation. This work makes a comparison between comminution circuits for compact Itabirites from the Iron Quadrangle. The circuits developed are: a crushing and ball mill circuit (CB, a SAG mill and ball mill circuit (SAB and a single stage SAG mill circuit (SSSAG. For the SAB circuit, the use of pebble crushing is analyzed (SABC. An industrial circuit for 25 million tons of run of mine was developed for each route from tests on a pilot scale (grinding and industrial scale. The energy consumption obtained for grinding in the pilot tests was compared with that reported by Donda and Bond. The SSSAG route had the lowest energy consumption, 11.8kWh/t and the SAB route had the highest energy consumption, 15.8kWh/t. The CB and SABC routes had a similar energy consumption of 14.4 kWh/t and 14.5 kWh/t respectively.

Equivalent Circuit for Magnetoelectric Read and Write Operations

Science.gov (United States)

Camsari, Kerem Y.; Faria, Rafatul; Hassan, Orchi; Sutton, Brian M.; Datta, Supriyo

2018-04-01

We describe an equivalent circuit model applicable to a wide variety of magnetoelectric phenomena and use spice simulations to benchmark this model against experimental data. We use this model to suggest a different mode of operation where the 1 and 0 states are represented not by states with net magnetization (like mx , my, or mz) but by different easy axes, quantitatively described by (mx2-my2), which switches from 0 to 1 through the write voltage. This change is directly detected as a read signal through the inverse effect. The use of (mx2-my2) to represent a bit is a radical departure from the standard convention of using the magnetization (m ) to represent information. We then show how the equivalent circuit can be used to build a device exhibiting tunable randomness and suggest possibilities for extending it to nonvolatile memory with read and write capabilities, without the use of external magnetic fields or magnetic tunnel junctions.

Design and development of improved ballscrew and control circuit for reactivity mechanisms of 220 MWe PHWR operating stations

International Nuclear Information System (INIS)

Jain, A.K.; Rama Mohan, N.; Mathew, Jimmy; Mathur, M.K.; Roy, S.; Ingle, V.J.; Ghoshal, B.; Ashok Kumar, B.; Patil, D.C.; Dwivedi, K.P.; Bhambra, H.S.

2006-01-01

There has been persistent failure of Ballscrews used for Reactivity Mechanism in standardised 220 MWe PHWR units. The detailed review of failures indicated that on one hand the number of demands for operation of Absorber Rod and Regulating Rod had increased due to use of digital circuit in the drive control system as compared analog circuits used earlier. On the other hand, the existing design of ballscrew had some inherent weaknesses to withstand the loads generated during starting and stopping of the regulating rods. To solve these problems two-pronged approach was adopted. The control problem was traced to overshooting of the servomotor of Absorber Rod and Regulating Rod to the full speed at the time of starting and thereafter, settling to the required speed. This sudden overshooting produces a jerk in the drive mechanism. A modified circuit has been evolved to solve this problem. Also, Changing the dead band and gain of control circuits have reduced the number of rod movements. A 'new design' of Ballscrew assembly was finalised by NPCIL with a view to withstand the severe loads generated during starting and stopping of the regulating rods and to achieve enhanced service life under water-lubrication condition. Based on this design, prototype assemblies were successfully manufactured by two Indian manufacturers. The design was cleared for manufacturing of the bulk production of Ballscrew assemblies after evaluation of its performance during rigorous 'Acceptance Testing'. Two ballscrews of new design were installed in the KGS-1 reactor and are operating since July 2005. This paper covers operational feedback including ballscrew failures in various units, Design/Development of Modified Reactivity Mechanism Ballscrews and Control Circuit based on analysis of underlying causes of failures and feedback on performance of new design. (author)

Test and verification of a reactor protection system application-specific integrated circuit

International Nuclear Information System (INIS)

Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.

1997-01-01

Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing

High-Temperature Test of 800HT Printed Circuit Heat Exchanger in HELP

International Nuclear Information System (INIS)

Kim, Chan Soo; Hong, Sung-Deok; Kim, Min Hwan; Shim, Jaesool

2014-01-01

Korea Atomic Energy Research Institute has developed high-temperature Printed Circuit Heat Exchangers (PCHE) for a Very High Temperature gas-cooled Reactor and operated a very high temperature Helium Experimental LooP (HELP) to verify the performance of the high temperature heat exchanger at the component level environment. PCHE is one of the candidates for the intermediate heat exchanger in a VHTR, because its design temperature and pressure are larger than any other compact heat exchanger types. High temperature PCHEs in HELP consist of an alloy617 PCHE and an 800HT PCHE. This study presents the high temperature test of an 800HT PCHE in HELP. The experimental data include the pressure drops, the overall heat transfer coefficients, and the surface temperature distributions under various operating conditions. The experimental data are compared with the thermo-hydraulic analysis from COMSOL. In addition, the single channel tests are performed to quantify the friction factor under normal nitrogen and helium inlet conditions. (author)

Short-circuit testing of monofilar Bi-2212 coils connected in series and in parallel

International Nuclear Information System (INIS)

Polasek, A; Dias, R; Serra, E T; Filho, O O; Niedu, D

2010-01-01

Superconducting Fault Current Limiters (SCFCL's) are one of the most promising technologies for fault current limitation. In the present work, resistive SCFCL components based on Bi-2212 monofilar coils are subjected to short-circuit testing. These SCFCL components can be easily connected in series and/or in parallel by using joints and clamps. This allows a considerable flexibility to developing larger SCFCL devices, since the configuration and size of the whole device can be easily adapted to the operational conditions. The single components presented critical current (Ic) values of 240-260 A, at 77 K. Short-circuits during 40-120 ms were applied. A single component can withstand a voltage drop of 126-252 V (0.3-0.6 V/cm). Components connected in series withstand higher voltage levels, whereas parallel connection allows higher rated currents during normal operation, but the limited current is also higher. Prospective currents as high as 10-40 kA (peak value) were limited to 3-9 kA (peak value) in the first half cycle.

Developing 300°C Ceramic Circuit Boards

Energy Technology Data Exchange (ETDEWEB)

Normann, Randy A

2015-02-15

This paper covers the development of a geothermal ceramic circuit board technology using 3D traces in a machinable ceramic. Test results showing the circuit board to be operational to at least 550°C. Discussion on producing this type of board is outlined along with areas needing improvement.

Sequential circuit design for radiation hardened multiple voltage integrated circuits

Science.gov (United States)

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

A Discrete Event System Approach to Online Testing of Speed Independent Circuits

Directory of Open Access Journals (Sweden)

P. K. Biswal

2015-01-01

Full Text Available With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature.

Integrated Circuit Design of 3 Electrode Sensing System Using Two-Stage Operational Amplifier

Science.gov (United States)

Rani, S.; Abdullah, W. F. H.; Zain, Z. M.; N, Aqmar N. Z.

2018-03-01

This paper presents the design of a two-stage operational amplifier(op amp) for 3-electrode sensing system readout circuits. The designs have been simulated using 0.13μm CMOS technology from Silterra (Malaysia) with Mentor graphics tools. The purpose of this projects is mainly to design a miniature interfacing circuit to detect the redox reaction in the form of current using standard analog modules. The potentiostat consists of several op amps combined together in order to analyse the signal coming from the 3-electrode sensing system. This op amp design will be used in potentiostat circuit device and to analyse the functionality for each module of the system.

RF and microwave integrated circuit development technology, packaging and testing

CERN Document Server

Gamand, Patrice; Kelma, Christophe

2018-01-01

RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

Oscillator circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

Measuring circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

Science.gov (United States)

Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

2011-01-01

Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

Nuclear code case development of printed-circuit heat exchangers with thermal and mechanical performance testing

Energy Technology Data Exchange (ETDEWEB)

Aakre, Shaun R. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering; Jentz, Ian W. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering; Anderson, Mark H. [Univ. of Wisconsin, Madison, WI (United States). Dept. of Mechanical Engineering

2018-03-27

The U.S. Department of Energy has agreed to fund a three-year integrated research project to close technical gaps involved with compact heat exchangers to be used in nuclear applications. This paper introduces the goals of the project, the research institutions, and industrial partners working in collaboration to develop a draft Boiler and Pressure Vessel Code Case for this technology. Heat exchanger testing, as well as non-destructive and destructive evaluation, will be performed by researchers across the country to understand the performance of compact heat exchangers. Testing will be performed using coolants and conditions proposed for Gen IV Reactor designs. Preliminary observations of the mechanical failure mechanisms of the heat exchangers using destructive and non-destructive methods is presented. Unit-cell finite element models assembled to help predict the mechanical behavior of these high-temperature components are discussed as well. Performance testing methodology is laid out in this paper along with preliminary modeling results, an introduction to x-ray and neutron inspection techniques, and results from a recent pressurization test of a printed-circuit heat exchanger. The operational and quality assurance knowledge gained from these models and validation tests will be useful to developers of supercritical CO₂ systems, which commonly employ printed-circuit heat exchangers.

A Low Speed BIST Framework for High Speed Circuit Testing

NARCIS (Netherlands)

Speek, H.; Kerkhoff, Hans G.; Shashaani, M.; Sachdev, M.

2000-01-01

Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a design-for-test methodology such that high

A new approach of optimization procedure for superconducting integrated circuits

International Nuclear Information System (INIS)

Saitoh, K.; Soutome, Y.; Tarutani, Y.; Takagi, K.

1999-01-01

We have developed and tested a new circuit simulation procedure for superconducting integrated circuits which can be used to optimize circuit parameters. This method reveals a stable operation region in the circuit parameter space in connection with the global bias margin by means of a contour plot of the global bias margin versus the circuit parameters. An optimal set of parameters with margins larger than these of the initial values has been found in the stable region. (author)

Optically controllable molecular logic circuits

International Nuclear Information System (INIS)

Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

2015-01-01

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

Circuit of synchronous logic for the transmission of safety commands

International Nuclear Information System (INIS)

Uberschlag, J.

1969-01-01

The author reports the development of a control-command circuit for the transmission of binary commands related to the safety of nuclear reactors. He presents the main design criteria (operation safety, provided safety level, flexibility, technical adaptation), the definition of the operation principle (inputs, logical outputs), the properties of a logic system. He evokes redundancy issues, and presents the system structure, proposes a possible sketch of the logic circuit. He describes the possible options for intermediate circuits and logic outputs, and tests to be performed

Analysis of a PCB In-Circuit Test and Its Optimized Cycle

International Nuclear Information System (INIS)

Chi, Moon Goo; Lee, Eun Chan; Bae, Yeon Kyoung

2011-01-01

KHNP performs subcomponent performance tests of the PCBs (Printed Circuit Boards) installed in safety-related systems or plant trip-related systems with every outage. The characteristics of each subcomponent are measured by test equipment. The tests are known as an ICT (In-Circuit Test). If a degraded condition is detected by this test, the affected subcomponents are replaced. This test has been conducted for 17 years, since 1994, and its results have been compiled into a test system database. As part of the reliability improvement plan of critical PCBs, KHNP developed a program that analyzes the performance of various key PCBs based on this test data. Thus, it became possible to evaluate the performance trends related to PCBs by tracing the test history of the PCB subcomponents through the ICT over many years. The present study also estimates an optimized ICT cycle that can be implemented to prevent the degradation of PCBs before they fail due to aging

Automatic test pattern generation for stuck-at and delay faults in combinational circuits

International Nuclear Information System (INIS)

Kim, Dae Sik

1998-02-01

The present studies are developed to propose the automatic test pattern generation (ATG) algorithms for combinational circuits. These ATG algorithms are realized in two ATG programs: One is the ATG program for stuck-at fault and the other one for delay faults. In order to accelerate the ATG process, these two ATG programs have a common feature (the search method based on the concept of the degree of freedom), whereas only ATG program for the delay fault utilizes the 19-valued logic, a type of composite valued logic. This difference between two ATG programs results from the difference of the target fault. Accelerating the ATG process is indispensable for improving the ATG algorithms. This acceleration is mainly achieved by reducing the number of the unnecessary backtrackings, making the earlier detection of the conflicts, and shortening the computation time between the implication. Because of this purpose, the developed ATG programs include the new search method based on the concept of the degree of freedom (DF). The DF concept, computed directly and easily from the system descriptions such as types of gates and their interconnections, is the criterion to decide which, among several alternate lines' logic values required along each path, promises to be the most effective in order to accelerate and improve the ATG process. This DF concept is utilized to develop and improve both of ATG programs for stuck-at and delay faults in combinational circuits. In addition to improving the ATG process, reducing number of test pattern is indispensable for testing the delay faults because the size of the delay faults grows rapidly as increasing the size of the circuit. In order to improve the compactness of the test set, 19-valued logic are derived. Unlike other TG logic systems, 19-valued logic is utilized to generate the robustly hazard-free test pattern. This is achieved by using the basic 5-valued logic, proposed in this work, where the transition with no hazard is

A new circuit for at-speed scan SoC testing

International Nuclear Information System (INIS)

Lin Wei; Shi Wenlong

2013-01-01

It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. (semiconductor integrated circuits)

Test and Diagnosis of Integrated Circuits

OpenAIRE

Bosio , Alberto

2015-01-01

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

Operational Experience from LCLS-II Cryomodule Testing

Energy Technology Data Exchange (ETDEWEB)

Wang, Renzhuo [Fermilab; Hansen, Benjamin [Fermilab; White, Michael [Fermilab; Hurd, Joseph [Fermilab; Atassi, Omar Al [Fermilab; Bossert, Richard [Fermilab; Pei, Liujin [Fermilab; Klebaner, Arkadiy [Fermilab; Makara, Jerry [Fermilab; Theilacker, Jay [Fermilab; Kaluzny, Joshua [Fermilab; Wu, Genfa [Fermilab; Harms, Elvin [Fermilab

2017-07-01

This paper describes the initial operational experience gained from testing Linac Coherent Light Source II (LCLS-II) cryomodules at Fermilab’s Cryomodule Test Facility (CMTF). Strategies for a controlled slow cooldown to 100 K and a fast cooldown past the niobium superconducting transition temperature of 9.2 K will be described. The test stand for the cryomodules at CMTF is sloped to match gradient in the LCLS-II tunnel at Stanford Linear Accelerator (SLAC) laboratory, which adds an additional challenge to stable liquid level control. Control valve regulation, Superconducting Radio-Frequency (SRF) power compensation, and other methods of stabilizing liquid level and pressure in the cryomodule 2.0 K SRF cavity circuit will be discussed. Several different pumping configurations using cold compressors and warm vacuum pumps have been used on the cryomodule 2.0 K return line and the associated results will be described.

Operational experience from LCLS-II cryomodule testing

Science.gov (United States)

Wang, R.; Hansen, B.; White, M.; Hurd, J.; Atassi, O. Al; Bossert, R.; Pei, L.; Klebaner, A.; Makara, J.; Theilacker, J.; Kaluzny, J.; Wu, G.; Harms, E.

2017-12-01

This paper describes the initial operational experience gained from testing Linac Coherent Light Source II (LCLS-II) cryomodules at Fermilab’s Cryomodule Test Facility (CMTF). Strategies for a controlled slow cooldown to 100 K and a fast cooldown past the niobium superconducting transition temperature of 9.2 K will be described. The test stand for the cryomodules at CMTF is sloped to match gradient in the LCLS-II tunnel at Stanford Linear Accelerator (SLAC) laboratory, which adds an additional challenge to stable liquid level control. Control valve regulation, Superconducting Radio-Frequency (SRF) power compensation, and other methods of stabilizing liquid level and pressure in the cryomodule 2.0 K SRF cavity circuit will be discussed. Several different pumping configurations using cold compressors and warm vacuum pumps have been used on the cryomodule 2.0 K return line and the associated results will be described.

High speed hydraulically-actuated operating system for an electric circuit breaker

Science.gov (United States)

Iman, Imdad

1983-06-07

This hydraulically-actuated operating system comprises a cylinder, a piston movable therein in an opening direction to open a circuit breaker, and an accumulator for supplying pressurized liquid to a breaker-opening piston-actuating space within the cylinder. A normally-closed valve between the accumulator and the actuating space is openable to allow pressurized liquid from the accumulator to flow through the valve into the actuating space to drive the piston in an opening direction. A dashpotting mechanism operating separately from the hydraulic actuating system is provided, thereby reducing flow restriction interference with breaker opening.

Fourteen years of test experience with short-circuit withstand capability of large power transformers

NARCIS (Netherlands)

Smeets, R.P.P.; Paske, te L.H.

2010-01-01

Experience is reported of short-circuit testing of large power transformers during the past 14 years by KEMA in the Netherlands. In total, 119 transformers > 25 MVA participated in the survey. KEMA shows that at initial access to standard IEC short-circuit tests, 28% failed initially in a wide range

Sixteen years of test experiences with short-circuit withstand capability of large power transformers

NARCIS (Netherlands)

Smeets, R.P.P.; Paske, te L.H.

2012-01-01

Experience is reported of short-circuit testing of large power transformers during the past 16 years by KEMA in the Netherlands. In total, 174 transformers > 25 MVA participated in the survey. KEMA shows that at initial access to standard IEC short-circuit tests, 24% failed initially in a wide range

Corrosion and indices of operating reliability of steam-water circuits of foreign NPP

International Nuclear Information System (INIS)

Martynova, O.I.

1983-01-01

Corrosion failures in circuits of foreign NPPs are considered. According to American statistics there are more corrosion failures in two-circuit NPPs than in NPPs with one circuit. Steam generators mostly suffer from ''corrosion denting''. Lately pitting corrosion becomes a potentially serious problem. Steam generator vertical tubes are maiply subjected to this corrosion type. Attention is drawn to intercrystalline corrosion. The causes of corrosion are described. The problem of optimization of structural materials is discussed to reduce corrosion failures as well as other methods of decreasing corrosion failures. Organization of nondestructive testing, increased requirements to water and steam purity are of great importance

Thirteen years test experience with short-circuit withstand capability of large power transformers

NARCIS (Netherlands)

Smeets, R.P.P.; Paske, te L.H.; Leufkens, P.P.; Fogelberg, T.

2009-01-01

The ability to withstand a short circuit is recognised more and more as an essential characteristic of power transformers. IEC and IEEE Standards, as well as other national standards specify short-circuit testing and how to check the withstand capability. Unfortunately, however, there is extensive

Ten years of sodium cooled steam generator tests on the C.G.V.S. Synthesis of the results obtained on these equipments and operation experiments of an industrial size test facility

International Nuclear Information System (INIS)

Fontaine, J.P.; Llory, M.; Quinet, J.L.

1984-04-01

From 1970 to 1980, Electricite de France carried out tests on four steam generators of the fast neutron reactor series on an industrial size testing equipment, the C.G.V.S. (large power testing Circuit for Steam Generators heated by Sodium). After a presentation of the testing installation, types of tests carried out and tested apparatus, a balance of lessons drawn from the circuit exploitation, and from the main results obtained on the tested equipments and on the means of calculation COPI and SICLE codes developed or adopted to simulate steam generator operation. 33 figs., 50 refs [fr

Automatic Analysis at the Commissioning of the LHC Superconducting Electrical Circuits

CERN Document Server

Reymond, H; Charrondiere, C; Rijllart, A; Zerlauth, M

2011-01-01

Since the beginning of 2010 the LHC has been operating in a routinely manner, starting with a commissioning phase and then an operation for physics phase. The commissioning of the superconducting electrical circuits requires rigorous test procedures before entering into operation. To maximize the beam operation time of the LHC, these tests should be done as fast as procedures allow. A full commissioning need 12000 tests and is required after circuits have been warmed above liquid nitrogen temperature. Below this temperature, after an end of year break of two months, commissioning needs about 6000 tests. As the manual analysis of the tests takes a major part of the commissioning time, we automated existing analysis tools. We present here how these LabVIEW™ applications were automated, the evaluation of the gain in commissioning time and reduction of experts on night shift observed during the LHC hardware commissioning campaign of 2011 compared to 2010. We end with an outlook at what can be further optimized.

Automatic analysis at the commissioning of the LHC superconducting electrical circuits

International Nuclear Information System (INIS)

Reymond, H.; Andreassen, O.O.; Charrondiere, C.; Rijllart, A.; Zerlauth, M.

2012-01-01

Since the beginning of 2010 the LHC has been operating in a routinely manner, starting with a commissioning phase and then an operation for physics phase. The commissioning of the superconducting electrical circuits requires rigorous test procedures before entering into operation. To maximize the beam operation time of the LHC, these tests should be done as fast as procedures allow. A full commissioning need 12000 tests and is required after circuits have been warmed above liquid nitrogen temperature. Below this temperature, after an end of year break of two months, commissioning needs about 6000 tests. As the manual analysis of the tests takes a major part of the commissioning time, we automated existing analysis tools. We present here how these LabVIEW TM applications were automated, the evaluation of the gain in commissioning time and reduction of experts on night shift observed during the LHC hardware commissioning campaign of 2011 compared to 2010. We end with an outlook at what can be further optimized. (authors)

Dangers of bypassing thermal overload relays in nuclear power plant motor operated valve circuits

International Nuclear Information System (INIS)

Baxter, F.D.

1980-01-01

Operation of motor operated valves is analyzed under various abnormal conditions such as frozen bearing, tight packing, mid-travel obstruction, torque switch failure, limit switch failure, and post-accident operation. Each condition has been reviewed to show that an adverse situation results if the thermal overload relays in the circuit are bypassed. In conclusion, there appears to be no technical basis for bypassing or oversizing the thermal overload relay provided it is selected correctly

Induced over voltage test on transformers using enhanced Z-source inverter based circuit

Science.gov (United States)

Peter, Geno; Sherine, Anli

2017-09-01

The normal life of a transformer is well above 25 years. The economical operation of the distribution system has its roots in the equipments being used. The economy being such, that it is financially advantageous to replace transformers with more than 15 years of service in the second perennial market. Testing of transformer is required, as its an indication of the extent to which a transformer can comply with the customers specified requirements and the respective standards (IEC 60076-3). In this paper, induced over voltage testing on transformers using enhanced Z source inverter is discussed. Power electronic circuits are now essential for a whole array of industrial electronic products. The bulky motor generator set, which is used to generate the required frequency to conduct the induced over voltage testing of transformers is nowadays replaced by static frequency converter. First conventional Z-source inverter, and second an enhanced Z source inverter is being used to generate the required voltage and frequency to test the transformer for induced over voltage test, and its characteristics is analysed.

A study on the development of an automatic fault diagnosis system for testing NPP digital electronic circuits

International Nuclear Information System (INIS)

Kim, Dae Sik

1993-02-01

This paper describes a study on the development of an automatic fault diagnosis system for testing digital electronic circuits of nuclear power plants. Compared with the other conventional fault diagnosis systems, the system described in this paper uses Artificial Intelligence technique of model based reasoning and corroboration, which makes fault diagnosis much more efficient. In order to reduce the testing time, an optimal testing set which means a minimal testing set to determine whether or not the circuit is fault-free and to locate the faulty gate was derived. Compared with the testing using an exhaustive testing set, the testing using the optimal testing set makes fault diagnosis much more fast. Since the system diagnoses the circuit boards bases only on input and output signals, it can be further developed for on-line testing. The system was implemented on a microprocessor and was applied for Universal Circuit board testing of the Solid State protection System in nuclear power plants

Real Time In-circuit Condition Monitoring of MOSFET in Power Converters

Directory of Open Access Journals (Sweden)

Shakeb A. Khan

2015-03-01

Full Text Available Abstract:This paper presents simple and low-cost, real time in-circuit condition monitoring of MOSFET in power electronic converters. Design metrics requirements like low cost, small size, high power factor, low percentage of total harmonic distortion etc. requires the power electronic systems to operate at high frequencies and at high power density. Failures of power converters are attributed largely by aging of power MOSFETs at high switching frequencies. Therefore, real time in-circuit prognostic of MOSFET needs to be done before their selection for power system design. Accelerated aging tests are performed in different circuits to determine the wear out failure of critical components based on their parametric degradation. In this paper, the simple and low-cost test beds are designed for real time in-circuit prognostics of power MOSFETs. The proposed condition monitoring scheme helps in estimating the condition of MOSFETs at their maximum rated operating condition and will aid the system designers to test their reliability and benchmark them before selecting in power converters.

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

Effects of smoke on functional circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1997-10-01

Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs

Hard alloys testing-machine for values of PWR primary coolant circuits

International Nuclear Information System (INIS)

Campan, J.L.; Sauze, A.

1980-01-01

Testing of valve parts or material used in valve fabrication and particularly seizing conditions in friction of plane surfaces coated with hard alloys of the type stellite. The testing equipment called Marguerite is composed of a hot pressurized water loop in conditions similar to PWR primary coolant circuits (320 0 C, 150 bars) and a testing-machine with measuring instruments. Testing conditions and samples are described [fr

Calorimeter Preamplifier Hybrid Circuit Test Jig

Energy Technology Data Exchange (ETDEWEB)

Abraham, B.M.; /Fermilab

1999-04-19

There are two ways in which the testing may be initiated, remotely or locally. If the remote operation is desired, an external TTL level signal must be provided to the test jig with the remotellocal switch on the side of the test jig switched to remote. A logic high will initiate the test. A logic low will terminate the test. In the event that an external signal is connected to the test jig while local operation occurs, the local control takes precedence over remote control. Once a DVT has been locked in the ZIF socket and the DIP switches are selected, the Push-to-Test button may be depressed. Momentarily depressing the button will initiate a test with a minimum 400 ms duration. At the same time a PBCLOCK and PBLATCH pulses will be initiated and the power rails +12V, +8V, and -6V will be ramped to full voltage. The time at which the power rails reach the full voltage is about 13 ms and it is synchronized with bypass capacitors placed on COMP input of U20 and U22 and on the output of U23 voltage regulators. The voltage rails are supplied to a {+-}10% window comparator. A red LED indicates the rail is below or above 10% of the design value. A green LED indicates the rail is within acceptable limits. For DDT with a 5 pF and 10 pF feed back capacitor, the +12V and +8V rails are current-regulated to 19rnA and 22 rnA respectively and the -6V rail is short-circuit protected within the regulator. For DUT with a 22 pF feed back capacitor the current regulation is the same as above except that the +8V rail is current regulated to 43 rnA. The power rails are supplied to the DUT via a 10 {Omega} resistor. The voltage drop across this resistor is sensed by a differential amplifier AD620 and amplified by a gain of 10. An external BNC connection is provided from this point to allow for current measurements by the vendor. The current value for each rail is calculated by measuring the voltage value at this point and divided by (10*10{Omega}). The next stage inverts and amplifies

Calorimeter Preamplifier Hybrid Circuit Test Jig

International Nuclear Information System (INIS)

Abraham, B.M.

1999-01-01

There are two ways in which the testing may be initiated, remotely or locally. If the remote operation is desired, an external TTL level signal must be provided to the test jig with the remotellocal switch on the side of the test jig switched to remote. A logic high will initiate the test. A logic low will terminate the test. In the event that an external signal is connected to the test jig while local operation occurs, the local control takes precedence over remote control. Once a DVT has been locked in the ZIF socket and the DIP switches are selected, the Push-to-Test button may be depressed. Momentarily depressing the button will initiate a test with a minimum 400 ms duration. At the same time a PBCLOCK and PBLATCH pulses will be initiated and the power rails +12V, +8V, and -6V will be ramped to full voltage. The time at which the power rails reach the full voltage is about 13 ms and it is synchronized with bypass capacitors placed on COMP input of U20 and U22 and on the output of U23 voltage regulators. The voltage rails are supplied to a ±10% window comparator. A red LED indicates the rail is below or above 10% of the design value. A green LED indicates the rail is within acceptable limits. For DDT with a 5 pF and 10 pF feed back capacitor, the +12V and +8V rails are current-regulated to 19rnA and 22 rnA respectively and the -6V rail is short-circuit protected within the regulator. For DUT with a 22 pF feed back capacitor the current regulation is the same as above except that the +8V rail is current regulated to 43 rnA. The power rails are supplied to the DUT via a 10 (Omega) resistor. The voltage drop across this resistor is sensed by a differential amplifier AD620 and amplified by a gain of 10. An external BNC connection is provided from this point to allow for current measurements by the vendor. The current value for each rail is calculated by measuring the voltage value at this point and divided by (10*10(Omega)). The next stage inverts and amplifies the

Crossed SMPS MOSFET-based protection circuit for high frequency ultrasound transceivers and transducers.

Science.gov (United States)

Choi, Hojong; Shung, K Kirk

2014-06-12

The ultrasonic transducer is one of the core components of ultrasound systems, and the transducer's sensitivity is significantly related the loss of electronic components such as the transmitter, receiver, and protection circuit. In an ultrasonic device, protection circuits are commonly used to isolate the electrical noise between an ultrasound transmitter and transducer and to minimize unwanted discharged pulses in order to protect the ultrasound receiver. However, the performance of the protection circuit and transceiver obviously degrade as the operating frequency or voltage increases. We therefore developed a crossed SMPS (Switching Mode Power Supply) MOSFET-based protection circuit in order to maximize the sensitivity of high frequency transducers in ultrasound systems.The high frequency pulse signals need to trigger the transducer, and high frequency pulse signals must be received by the transducer. We therefore selected the SMPS MOSFET, which is the main component of the protection circuit, to minimize the loss in high frequency operation. The crossed configuration of the protection circuit can drive balanced bipolar high voltage signals from the pulser and transfer the balanced low voltage echo signals from the transducer. The equivalent circuit models of the SMPS MOSFET-based protection circuit are shown in order to select the proper device components. The schematic diagram and operation mechanism of the protection circuit is provided to show how the protection circuit is constructed. The P-Spice circuit simulation was also performed in order to estimate the performance of the crossed MOSFET-based protection circuit. We compared the performance of our crossed SMPS MOSFET-based protection circuit with a commercial diode-based protection circuit. At 60 MHz, our expander and limiter circuits have lower insertion loss than the commercial diode-based circuits. The pulse-echo test is typical method to evaluate the sensitivity of ultrasonic transducers

Highly focused ion beams in integrated circuit testing

International Nuclear Information System (INIS)

Horn, K.M.; Dodd, P.E.; Doyle, B.L.

1996-01-01

The nuclear microprobe has proven to be a useful tool in radiation testing of integrated circuits. This paper reviews single event upset (SEU) and ion beam induced charge collection (IBICC) imaging techniques, with special attention to damage-dependent effects. Comparisons of IBICC measurements with three-dimensional charge transport simulations of charge collection are then presented for isolated p-channel field effect transistors under conducting and non-conducting bias conditions

Low-power operation using self-timed circuits and adaptive scaling of the supply voltage

DEFF Research Database (Denmark)

Nielsen, Lars Skovby; Niessen, C.; Sparsø, Jens

1994-01-01

Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may be obtained by combining the self......-timed circuits with a mechanism that adaptively adjusts the supply voltage to the smallest possible, while maintaining the performance requirements. This paper describes such a mechanism, analyzes the possible power savings, and presents a demonstrator chip that has been fabricated and tested. The idea...... of voltage scaling has been used previously in synchronous circuits, and the contributions of the present paper are: 1) the combination of supply scaling and self-timed circuitry which has some unique advantages, and 2) the thorough analysis of the power savings that are possible using this technique.>...

Digital circuit testing a guide to DFT and other techniques

CERN Document Server

Wong, Francis C

1991-01-01

Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to

Integrated circuit test-port architecture and method and apparatus of test-port generation

Science.gov (United States)

Teifel, John

2016-04-12

A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.

The laboratory testing system for radiation rsistance investigations of integrated circuits

International Nuclear Information System (INIS)

Wronski, W.; Wislowski, J.

1986-01-01

In order to evaluate the radiation tolerance of integrated circuits MCY 7102 type /MOS RAM/ two devices were built: isotope arrangement for irradiation, and portable tester registering every error of storage block which consists of 32 IC's. Principle of operation and construction of this devices is described. Exemplary results of investigations are shown. (author)

Why we can talk, debate, and change our minds: neural circuits, basal ganglia operations, and transcriptional factors.

Science.gov (United States)

Lieberman, Philip

2014-12-01

Ackermann et al. disregard attested knowledge concerning aphasia, Parkinson disease, cortical-to-striatal circuits, basal ganglia, laryngeal phonation, and other matters. Their dual-pathway model cannot account for "what is special about the human brain." Their human cortical-to-laryngeal neural circuit does not exist. Basal ganglia operations, enhanced by mutations on FOXP2, confer human motor-control, linguistic, and cognitive capabilities.

Test methods of total dose effects in very large scale integrated circuits

International Nuclear Information System (INIS)

He Chaohui; Geng Bin; He Baoping; Yao Yujuan; Li Yonghong; Peng Honglun; Lin Dongsheng; Zhou Hui; Chen Yusheng

2004-01-01

A kind of test method of total dose effects (TDE) is presented for very large scale integrated circuits (VLSI). The consumption current of devices is measured while function parameters of devices (or circuits) are measured. Then the relation between data errors and consumption current can be analyzed and mechanism of TDE in VLSI can be proposed. Experimental results of 60 Co γ TDEs are given for SRAMs, EEPROMs, FLASH ROMs and a kind of CPU

A Method for Automatic Inspection of Printed Circuit Boards by Using the Thermal Signature

International Nuclear Information System (INIS)

Amer, H.H.; Zekry, A.A.; Elaraby, S.; Ghareeb, K.E.

2012-01-01

This paper aims to design a system for automating inspection of the printed circuit boards (PCBs) by using the thermal signature of the different integrated circuits (I.C). The proposed inspection system consists of the inspection circuit, data acquisition system (DAS) and personal computer. Inspection is done by comparing the thermal signature of normally operated circuit with the thermal signature of circuit under test. One thermistor is assigned to each component in the circuit. The thermistor must touch tightly the surface of the I.C. to sense its temperature during the inspection process. Matlab software is used to represent the thermal signature through different colors. The Turbo C software is used to develop a program for acquiring and comparing the thermal signature of the circuit under the test with the reference circuit. If the colors of the two thermal signatures for the same I.C. are same then the circuit under test is fault free and does not contain any defect. On the other side, if the colors of the two thermal signatures for the same I.C. are different then the circuit under test is defective

The CRESST-III iStick veto. Stable operation of multiple transition edge sensors in one readout circuit

Energy Technology Data Exchange (ETDEWEB)

Rothe, Johannes [Max-Planck-Institut f. Physik (Werner-Heisenberg-Institut) (Germany); Ludwig-Maximilians-Universitaet Muenchen (Germany); Collaboration: CRESST-Collaboration

2016-07-01

To enable complete rejection of holder-related events in the upcoming CRESST-III dark matter search experiment, the scintillating target crystals are held by calcium tungstate sticks (iSticks) instrumented with tungsten transition edge sensors (TESs). Since the iStick signals are used exclusively for vetoing, it is sufficient to register if an event happened in any stick, without knowing which one. This allows the operation of all iSticks in a single readout circuit, requiring just one SQUID magnetometer. The talk describes the effect of bias current heating and corresponding hysteresis phenomena known in single-TES circuits, and the resulting conditions for stability in multiple-TES circuits. The fundamentally different behaviour of parallel and series circuits and resulting design choices are explored.

Multiplication circuit for particle identification

International Nuclear Information System (INIS)

Gerlier, Jean

1962-01-01

After having commented some characteristics of the particles present in a cyclotron, and their interactions, this report addresses the development and the implementation of a method and a device for selecting and counting particles. The author presents the principle and existing techniques of selection. In comparison with an existing device, the proportional counter and the scintillator are replaced by junctions: a surface barrier type junction (a silicon N layer with a very thin oxygen layer playing the role of the P layer), and lithium-based junction (a silicon P type layer made intrinsic by migration of lithium). The author then describes the developed circuit and assembly (background of the choice of a multiplication circuit), and their operation. In the next part, he presents the performed tests and discuses the obtained results. He finally outlines the benefits of the herein presented circuit [fr

A study on the short-circuit test by fault angle control and the recovery characteristics of the fault current limiter using coated conductor

International Nuclear Information System (INIS)

Park, D.K.; Kim, Y.J.; Ahn, M.C.; Yang, S.E.; Seok, B.-Y.; Ko, T.K.

2007-01-01

Superconducting fault current limiters (SFCLs) have been developed in many countries, and they are expected to be used in the recent electric power systems, because of their great efficiency for operating these power system stably. It is necessary for resistive FCLs to generate resistance immediately and to have a fast recovery characteristic after the fault clearance, because of re-closing operation. Short-circuit tests are performed to obtained current limiting operational and recovery characteristics of the FCL by a fault controller using a power switching device. The power switching device consists of anti-parallel connected thyristors. The fault occurs at the desired angle by controlling the firing angle of thyristors. Resistive SFCLs have different current limiting characteristics with respect to the fault angle in the first swing during the fault. This study deals with the short-circuit characteristic of FCL coils using two different YBCO coated conductors (CCs), 344 and 344s, by controlling the fault angle and experimental studies on the recovery characteristic by a small current flowing through the SFCL after the fault clearance. Tests are performed at various voltages applied to the SFCL in a saturated liquid nitrogen cooling system

Method of boundary testing of the electric circuits and its application for calculating electric tolerances. [electric equipment tests

Science.gov (United States)

Redkina, N. P.

1974-01-01

Boundary testing of electric circuits includes preliminary and limiting tests. Preliminary tests permit determination of the critical parameters causing the greatest deviation of the output parameter of the system. The boundary tests offer the possibility of determining the limits of the fitness of the system with simultaneous variation of its critical parameters.

Chemical operational experience with the water/steam-circuit at KNK II; Presentation at the meeting on Experience exchange on operational experience of fast breeder reactors, Karlsruhe/Bensberg/Kalkar, June 18. - 22. 1990

International Nuclear Information System (INIS)

Grumer, U.

1990-06-01

The availability of sodium cooled reactors depends essentially from the safety and reliability of the sodium heated steam generator. The transition from experimental plants with 12-20 MW electrical power to larger plants with 600 MW (BN-600) or 1200 MW (Superphenix) required the change from modular components to larger and compact steam generators with up to 800 MW. Defects of these large components cause extreme losses in availability of the plant and have to be avoided. In view of this request, a comprehensive test program has been performed at KNK II in addition to the normal control of the water/steam-circuit to compile all operational data on the water and steam side of the sodium heated steam generator. This paper describes the plant and the water/steam-circuit with its mode of operation. The experience with the surveillance and different methods of the conditioning are discussed in detail in this presentation

Aging evaluation of electrical circuits using the ECCAD [Electrical Circuit Characterization and Diagnostic] system

International Nuclear Information System (INIS)

Edson, J.L.

1988-01-01

As a part of the Nuclear Regulatory Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport Atomic Power Station Decommissioning Project. The objective of this work was to evaluate the effectiveness of the Electrical Circuit Characterization and Diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

Accelerating functional verification of an integrated circuit

Science.gov (United States)

Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

2015-10-27

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Estimating the short-circuit impedance

DEFF Research Database (Denmark)

Nielsen, Arne Hejde; Pedersen, Knud Ole Helgesen; Poulsen, Niels Kjølstad

1997-01-01

A method for establishing a complex value of the short-circuit impedance from naturally occurring variations in voltage and current is discussed. It is the symmetrical three phase impedance at the fundamental grid frequency there is looked for. The positive sequence components in voltage...... and current are derived each period, and the short-circuit impedance is estimated from variations in these components created by load changes in the grid. Due to the noisy and dynamic grid with high harmonic distortion it is necessary to threat the calculated values statistical. This is done recursively...... through a RLS-algorithm. The algorithms have been tested and implemented on a PC at a 132 kV substation supplying a rolling mill. Knowing the short-circuit impedance gives the rolling mill an opportunity to adjust the arc furnace operation to keep flicker below a certain level. Therefore, the PC performs...

A high speed, wide dynamic range digitizer circuit for photomultiplier tubes

International Nuclear Information System (INIS)

Yarema, R.J.; Foster, G.W.; Knickerbocker, K.; Sarraj, M.; Tschirhart, R.; Whitmore, J.; Zimmerman, T.; Lindgren, M.

1995-01-01

A circuit has been designed for digitizing PMT signals over a wide dynamic range (17-18 bits) with 8 bits of resolution at rates up to 53 MHz. Output from the circuit is in a floating point format with a 4 bit exponent and an 8 bit mantissa. The heart of the circuit is a full custom integrated circuit called the QIE (Charge Integrator and Encoder). The design of the QIE and associated circuitry reported here permits operation over a 17 bit dynamic range. Test results of a multirange device are presented for the first time. (orig.)

Open-circuit fault detection and tolerant operation for a parallel-connected SAB DC-DC converter

DEFF Research Database (Denmark)

Park, Kiwoo; Chen, Zhe

2014-01-01

This paper presents an open-circuit fault detection method and its tolerant control strategy for a Parallel-Connected Single Active Bridge (PCSAB) dc-dc converter. The structural and operational characteristics of the PCSAB converter lead to several advantages especially for high power applicatio...

A programmable CCD driver circuit for multiphase CCD operation

International Nuclear Information System (INIS)

Ewin, A.J.; Reed, K.V.

1989-01-01

A programmable CCD driver circuit was designed to drive CCD's in multiphased modes. The purpose of the drive electronics was to operate developmental CCD imaging arrays for NASA's Moderate Resolution Imaging Spectrometer - Tiltable (MODIS-T). Five prototype arrays were designed. Valid's Graphics Editor (GED) was used to design the driver. With this driver design, any of the five arrays can be readout. Designing the driver with GED allowed functional simulation, timing verification, and certain packaging analyses to be done on the design before fabrication. The driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400 Kpixels/sec. Timing and packaging parameters were verified. the design uses 54 TTL component chips

Performance of the Main Dipole Magnet Circuits of the LHC during Commissioning

CERN Document Server

Verweij, A; Ballarino, A; Bellesia, B; Bordry, Frederick; Cantone, A; Casas Lino, M; Castaneda Serra, A; Castillo Trello, C; Catalan-Lasheras, N; Charifoulline, Z; Coelingh, G; Dahlerup-Petersen, K; D'Angelo, G; Denz, R; Fehér, S; Flora, R; Gruwé, M; Kain, V; Khomenko, B; Kirby, G; MacPherson, A; Marqueta Barbero, A; Mess, K H; Modena, M; Mompo, R; Montabonnet, V; le Naour, S; Nisbet, D; Parma, V; Pojer, M; Ponce, L; Raimondo, A; Redaelli, S; Reymond, H; Richter, D; de Rijk, G; Rijllart, A; Romera Ramirez, I; Saban, R; Sanfilippo, S; Schmidt, R; Siemko, A; Solfaroli Camillocci, M; Thurel, Y; Thiessen, H; Venturini-Delsolaro, W; Vergara Fernandez, A; Wolf, R; Zerlauth, M

2008-01-01

During hardware commissioning of the Large Hadron Collider (LHC), 8 main dipole circuits are tested at 1.9 K and up to their nominal current. Each dipole circuit contains 154 magnets of 15 m length, and has a total stored energy of up to 1.3 GJ. All magnets are wound from Nb-Ti superconducting Rutherford cables, and contain heaters to quickly force the transition to the normal conducting state in case of a quench, and hence reduce the hot spot temperature. In this paper the performance of the first three of these circuits is presented, focussing on quench detection, heater performance, operation of the cold bypass diodes, and magnet-to-magnet quench propagation. The results as measured on the entire circuits will be compared to the test results obtained during the reception tests of the individual magnets.

Insulated transcriptional elements enable precise design of genetic circuits.

Science.gov (United States)

Zong, Yeqing; Zhang, Haoqian M; Lyu, Cheng; Ji, Xiangyu; Hou, Junran; Guo, Xian; Ouyang, Qi; Lou, Chunbo

2017-07-03

Rational engineering of biological systems is often complicated by the complex but unwanted interactions between cellular components at multiple levels. Here we address this issue at the level of prokaryotic transcription by insulating minimal promoters and operators to prevent their interaction and enable the biophysical modeling of synthetic transcription without free parameters. This approach allows genetic circuit design with extraordinary precision and diversity, and consequently simplifies the design-build-test-learn cycle of circuit engineering to a mix-and-match workflow. As a demonstration, combinatorial promoters encoding NOT-gate functions were designed from scratch with mean errors of 96% using our insulated transcription elements. Furthermore, four-node transcriptional networks with incoherent feed-forward loops that execute stripe-forming functions were obtained without any trial-and-error work. This insulation-based engineering strategy improves the resolution of genetic circuit technology and provides a simple approach for designing genetic circuits for systems and synthetic biology.Unwanted interactions between cellular components can complicate rational engineering of biological systems. Here the authors design insulated minimal promoters and operators that enable biophysical modeling of bacterial transcription without free parameters for precise circuit design.

Electromagnetic Compatibility Design of the Computer Circuits

Science.gov (United States)

Zitai, Hong

2018-02-01

Computers and the Internet have gradually penetrated into every aspect of people’s daily work. But with the improvement of electronic equipment as well as electrical system, the electromagnetic environment becomes much more complex. Electromagnetic interference has become an important factor to hinder the normal operation of electronic equipment. In order to analyse the computer circuit compatible with the electromagnetic compatibility, this paper starts from the computer electromagnetic and the conception of electromagnetic compatibility. And then, through the analysis of the main circuit and system of computer electromagnetic compatibility problems, we can design the computer circuits in term of electromagnetic compatibility. Finally, the basic contents and methods of EMC test are expounded in order to ensure the electromagnetic compatibility of equipment.

Compiling quantum circuits to realistic hardware architectures using temporal planners

Science.gov (United States)

Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy

2018-04-01

To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.

DIADEME: A computer code to assess in operation defective fuel characteristics and primary circuit contamination

Energy Technology Data Exchange (ETDEWEB)

Genin, J.B. [DEN/DEC/S3C, CEA Cadarache, 13 - Saint-Paul-lez-Durance (France); Harrer, A. [EdF/SEPTEN, 69 - Villeurbanne (France); Musante, Y. [FRAMATOME-ANP, 69 - Lyon (France)

2002-07-01

DIADEME is a computer code developed within the framework of R and D cooperation between the French Atomic Energy Commission (CEA), Electricite de France (EdF) and FRAMATOME-ANP. Its aim is to assess in operation defective fuel characteristics and primary circuit contamination for actinides and long half-life fission products involved in health physics problems as well as in waste and decommissioning studies. DIADEME has been developed and qualified for the EDF nuclear power plants. For many years, both theoretical and experimental studies have been carried out at the CEA on the release of fission products and actinides out of defective fuel rods in operation, their migration and deposition in PWR primary circuits. These studies have allowed defect characteristic diagnosis methods to be developed, based on radiochemical measurements of the primary coolant. These methods are generally used along with gamma spectrometry measurements on primary water sampling. In order to be completely efficient, these methods can also be used in connection with an on-line primary water gamma spectrometry device. This permits to obtain the most comprehensive data on fission product activity evolutions at steady state and during operation transients, and allows the on-line characterization of the defective fuel assemblies. For long half-life fission products and for actinides, DIADEME is also able to assess the activities of soluble and insoluble forms in the primary water and in the chemical and voluminal control system (CVCS) filters and resins, as well as those activities deposited on primary circuit surfaces. (author)

DIADEME: A computer code to assess in operation defective fuel characteristics and primary circuit contamination

International Nuclear Information System (INIS)

Genin, J.B.; Harrer, A.; Musante, Y.

2002-01-01

DIADEME is a computer code developed within the framework of R and D cooperation between the French Atomic Energy Commission (CEA), Electricite de France (EdF) and FRAMATOME-ANP. Its aim is to assess in operation defective fuel characteristics and primary circuit contamination for actinides and long half-life fission products involved in health physics problems as well as in waste and decommissioning studies. DIADEME has been developed and qualified for the EDF nuclear power plants. For many years, both theoretical and experimental studies have been carried out at the CEA on the release of fission products and actinides out of defective fuel rods in operation, their migration and deposition in PWR primary circuits. These studies have allowed defect characteristic diagnosis methods to be developed, based on radiochemical measurements of the primary coolant. These methods are generally used along with gamma spectrometry measurements on primary water sampling. In order to be completely efficient, these methods can also be used in connection with an on-line primary water gamma spectrometry device. This permits to obtain the most comprehensive data on fission product activity evolutions at steady state and during operation transients, and allows the on-line characterization of the defective fuel assemblies. For long half-life fission products and for actinides, DIADEME is also able to assess the activities of soluble and insoluble forms in the primary water and in the chemical and voluminal control system (CVCS) filters and resins, as well as those activities deposited on primary circuit surfaces. (author)

Thermionic integrated circuits: electronics for hostile environments

International Nuclear Information System (INIS)

Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

1985-01-01

Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

Directory of Open Access Journals (Sweden)

C. Wu

2011-06-01

Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.

Hydraulically-actuated operating system for an electric circuit breaker

Science.gov (United States)

Barkan, Philip; Imam, Imdad

1978-01-01

This hydraulically-actuated operating system comprises a cylinder, a piston movable therein in an opening direction to open a circuit breaker, and an accumulator for supplying pressurized liquid to a piston-actuating space within the cylinder. A normally-closed valve between the accumulator and the actuating space is openable to allow pressurized liquid from the accumulator to flow through the valve into the actuating space to drive the piston in an opening direction. A vent is located hydraulically between the actuating space and the valve for affording communication between said actuating space and a low pressure region. Flow control means is provided for restricting leakage through said vent to a rate that prevents said leakage from substantially detracting from the development of pressure within said actuatng space during the period from initial opening of the valve to the time when said piston has moved through most of its opening stroke. Following such period and while the valve is still open, said flow control means allows effective leakage through said vent. The accumulator has a limited capacity that results in the pressure within said actuating space decaying promptly to a low value as a result of effective leakage through said vent after the piston has moved through a circuit-breaker opening stroke and while the valve is in its open state. Means is provided for resetting the valve to its closed state in response to said pressure decay in the actuating space.

Ripple gate drive circuit for fast operation of series connected IGBTs

Science.gov (United States)

Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.

2005-09-20

A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.

High-precision analog circuit technology for power supply integrated circuits; Dengen IC yo koseido anarogu kairo gijutsu

Energy Technology Data Exchange (ETDEWEB)

Nakamori, A.; Suzuki, T.; Mizoe, K. [Fuji Electric Corporate Research and Development,Ltd., Kanagawa (Japan)

2000-08-10

With the recent rapid spread of portable electronic appliances, specification requirements such as compact power supply and long operation with batteries have become severer. Power supply ICs (integrated circuits) are required to reduce power consumption in the circuit and perform high-precision control. To meet these requirements, Fuji Electric develops high-precision CMOS (complementary metal-oxide semiconductor) analog technology. This paper describes three analog circuit technologies of a voltage reference, an operational amplifier and a comparator as circuit components particularly important for the precision of power supply ICs. (author)

Design, Fabrication and Integration of a NaK-Cooled Circuit

International Nuclear Information System (INIS)

Garber, Anne; Godfroy, Thomas

2006-01-01

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned for use with lithium. Due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped NaK circuit. (authors)

Estimation of Operating Condition of Appliances Using Circuit Current Data on Electric Distribution Boards

Science.gov (United States)

Iwafune, Yumiko; Ogimoto, Kazuhiko; Yagita, Yoshie

The Energy management systems (EMS) on demand sides are expected as a method to enhance the capability of supply and demand balancing of a power system under the anticipated penetration of renewable energy generation such as Photovoltaics (PV). Elucidation of energy consumption structure in a building is one of important elements for realization of EMS and contributes to the extraction of potential energy saving. In this paper, we propose the estimation method of operating condition of household appliances using circuit current data on an electric distribution board. Circuit current data are broken down by their shape using a self-organization map method and aggregated by appliance based on customers' information of appliance possessed. Proposed method is verified using residential energy consumption measurement survey data.

Design and experimental results of coaxial circuits for gyroklystron amplifiers

International Nuclear Information System (INIS)

Flaherty, M.K.E.; Lawson, W.; Cheng, J.; Calame, J.P.; Hogan, B.; Latham, P.E.; Granatstein, V.L.

1994-01-01

At the University of Maryland high power microwave source development for use in linear accelerator applications continues with the design and testing of coaxial circuits for gyroklystron amplifiers. This presentation will include experimental results from a coaxial gyroklystron that was tested on the current microwave test bed, and designs for second harmonic coaxial circuits for use in the next generation of the gyroklystron program. The authors present test results for a second harmonic coaxial circuit. Similar to previous second harmonic experiments the input cavity resonated at 9.886 GHz and the output frequency was 19.772 GHz. The coaxial insert was positioned in the input cavity and drift region. The inner conductor consisted of a tungsten rod with copper and ceramic cylinders covering its length. Two tungsten rods that bridged the space between the inner and outer conductors supported the whole assembly. The tube produced over 20 MW of output power with 17% efficiency. Beam interception by the tungsten rods resulted in minor damage. Comparisons with previous non-coaxial circuits showed that the coaxial configuration increased the parameter space over which stable operation was possible. Future experiments will feature an upgraded modulator and beam formation system capable of producing 300 MW of beam power. The fundamental frequency of operation is 8.568 GHz. A second harmonic coaxial gyroklystron circuit was designed for use in the new system. A scattering matrix code predicts a resonant frequency of 17.136 GHz and Q of 260 for the cavity with 95% of the outgoing microwaves in the desired TE032 mode. Efficiency studies of this second harmonic output cavity show 20% expected efficiency. Shorter second harmonic output cavity designs are also being investigated with expected efficiencies near 34%

The short-circuit test results of 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer

International Nuclear Information System (INIS)

Tomioka, A.; Otonari, T.; Ogata, T.; Iwakuma, M.; Okamoto, H.; Hayashi, H.; Iijima, Y.; Saito, T.; Gosho, Y.; Tanabe, K.; Izumi, T.; Shiohara, Y.

2011-01-01

The 6.9 kV/2.3 kV 400 kVA-class single-phase YBCO model transformer with the YBCO tape with copper tape was manufactured for short-circuit current test. Short-circuit test was performed and the short-circuit current of primary winding was 346 A which was about six times larger than the rated current. The I-V characteristics of the winding did not change before and after the test. The transformer withstood short-circuit current. We are planning to turn the result into a consideration of a 66 kV/6.9 kV-20 MVA-class three-phase superconducting transformer. We are developing an elemental technology for 66 kV/6.9 kV 20 MVA-class power transformer with YBCO conductors. The protection of short-circuit technology is one of the elemental technologies for HTS transformer. Since short-circuit current is much higher than critical current of YBCO tape, there is a possibility that superconducting characteristics may be damaged during short-circuit period. We made a conductor to compose the YBCO tape with copper tape. We manufactured 6.9 kV/2.3 kV 400 kVA-class YBCO model transformer using this conductor and performed short-circuit current test. The short-circuit current of primary winding was 346 A which was about six times larger than the rated current. The I-V characteristics of the winding did not change before and after the test. We may consider this conductor withstands short-circuit current.

Heavy ions testing experimental results on programmable integrated circuits

International Nuclear Information System (INIS)

Velazco, R.; Provost-Grellier, A.

1988-01-01

The natural radiation environment in space has been shown to produce anomalies in satellite-borne microelectronics. It becomes then mandatory to define qualification strategies allowing to choose the less vulnerable circuits. In this paper, is presented a strategy devoted to one of the most critical effects, the soft errors (so called upset). The method addresses programmable integrated circuits i.e. circuits able to execute an instruction or command set. Experimental results on representative circuits will illustrate the approach. 11 refs [fr

Testing of interposer-based 2.5D integrated circuits

CERN Document Server

Wang, Ran

2017-01-01

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and dela...

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1968-01-01

Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

Breaker Maintenance: Volume 3, Molded-Case circuit breakers

International Nuclear Information System (INIS)

Davis, E.L.; Funk, D.L.

1991-09-01

Modeled-case circuit breakers (MCCBs) provide power and circuit protection in nuclear plant electrical distribution systems. Thus, their proper operation is essential to the safe and reliable operation of plant electrical distribution systems. This guide for both nuclear and non-nuclear power generating facilities will help improve the maintenance and reliability of MCCBs. The authors developed this guide to establish a working-level understanding of hardware performance trends, reliability, and failure modes from which maintenance practices could be specified. The first step in preparing this guide was an in-depth review of available operating experience and failure data, which was obtained from nuclear information sources such as EPRI's Nuclear Maintenance Applications Center. In addition, they evaluated some nonnuclear reliability data. Next, they investigated current industry practices, including a review of manufacturer's recommendations and numerous industry standards. Finally, they used the collective information to develop programmatic recommendations and, where appropriate, detailed inspection and test guidance. This guide offers many recommendations applicable to MCCB maintenance, such as an engineering description of MCCBs and their operation; an overview of reliability and failure data; programmatic recommendations, including inspection and test periodicity; detailed inspection and test guidance; and corrective maintenance recommendations. Supplementary information includes an overview of industry standards, a discussion of regulatory issues, and sample data sheets. An evaluation of operating experience indicates that a maintenance program need not be overly complicated to detect the predominant failure modes associated with MCCBs. Those implementating an MCCB maintenance and testing program, however, must recognize the inherent limitations associated with field-testing of these devices. 42 refs., 17 figs., 7 tabs

10-Qubit Entanglement and Parallel Logic Operations with a Superconducting Circuit

Science.gov (United States)

Song, Chao; Xu, Kai; Liu, Wuxin; Yang, Chui-ping; Zheng, Shi-Biao; Deng, Hui; Xie, Qiwei; Huang, Keqiang; Guo, Qiujiang; Zhang, Libo; Zhang, Pengfei; Xu, Da; Zheng, Dongning; Zhu, Xiaobo; Wang, H.; Chen, Y.-A.; Lu, C.-Y.; Han, Siyuan; Pan, Jian-Wei

2017-11-01

Here we report on the production and tomography of genuinely entangled Greenberger-Horne-Zeilinger states with up to ten qubits connecting to a bus resonator in a superconducting circuit, where the resonator-mediated qubit-qubit interactions are used to controllably entangle multiple qubits and to operate on different pairs of qubits in parallel. The resulting 10-qubit density matrix is probed by quantum state tomography, with a fidelity of 0.668 ±0.025 . Our results demonstrate the largest entanglement created so far in solid-state architectures and pave the way to large-scale quantum computation.

Sodium corrosion tests in the ML 1 circuit

International Nuclear Information System (INIS)

Borgstedt, H.U.

1977-01-01

In the ML-1 circuit of the 'Juan Vigon' research centre in Madrid, sodium corrosion tests are being carried out on the austenitic steels DIN 1.4970 (X10NiCrMoTiB1515) and DIN 1.4301 (X5CrNi189) at temperatures between 500 and 700 0 C. The exposure time of the samples amounts to 6,000 h by now. Every 1,000 h, the samples were weighed in order to measure corrosion and deposition effects. After 3,000 and 6,000 h, some selected samples were destroyed for inspection. The results are given. (GSC) [de

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

Science.gov (United States)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Prospects of closed-circuit television in detecting surface defects

International Nuclear Information System (INIS)

Kaisler, L. et al.

The use is discussed of closed-circuit television for optical in-service testing of surface defects of nuclear reactors. Experience gained by UJV Rez with in-service testing of the WWR-S reactor is briefly reported. Main attention is devoted to recognizability of defects and to determining the fundamental conditions of the applicability and limitations of the closed-circuit television method. In experiments, resolution of the method was tested and the role of the human factor was assessed in evaluating the results. The need was stressed of thorough training of operators. Based on the experiments conducted, considerations are presented regarding modifications of the individual elements of the tv chain aimed at improved quality of information and a limited role of the observer. (B.S.)

Test and diagnosis of analogue, mixed-signal and RF integrated circuits the system on chip approach

CERN Document Server

Sun, Yichuang

2008-01-01

This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective.

Modernized CDTN's air-water experimental test circuit: initial results

International Nuclear Information System (INIS)

Pessoa, Mácio A.; Sobrinho, Mauricio R. da S.; Salomão, Eduardo A.; Ferreira, Arthur F.J.; Navarro, Moysés A.; Santos, André A. Campagnole dos

2017-01-01

The Counter Current Flow Limitation (CCFL) phenomenon, specifically the control that the gas exerts in a liquid flow in the opposite direction, is of real importance in the study of design and operation of various industrial sectors, particularly the nuclear industry. In nuclear engineering, such a phenomenon can occur in a loss of coolant accident (LOCA) of a Pressurized Water Reactor (PWR) when there is the need to re-flood the reactor core during an emergency cooling process. The CCFL phenomenon is being investigated at the Nuclear Technology Development Center (CDTN) thermo-hydraulics laboratory in order to better understand the flow and its limitations and thereby contribute to the improvement of its modeling for analysis of severe accidents. For this, a series of experiments were performed in CDTN in a reduced scale acrylic test section of the 'hot leg' of a PWR. The new proposed circuit is a closed loop and no water has to be discharged during the experiment. This is only possible due to the Python program, which is associated to the data acquisition system and can interface with the automated valves through the outputs of the data acquisition board to control the experiment. The trials compare the CCFL behavior for 500mm lengths of the horizontal section, for inclined duct slope 50° for a diameter of 54mm pipe's diameter. This paper describes the new tests in comparison to tests performed in the past. (author)

Modernized CDTN's air-water experimental test circuit: initial results

Energy Technology Data Exchange (ETDEWEB)

Pessoa, Mácio A.; Sobrinho, Mauricio R. da S.; Salomão, Eduardo A.; Ferreira, Arthur F.J.; Navarro, Moysés A.; Santos, André A. Campagnole dos, E-mail: marcioaraujopessoa@gmail.com, E-mail: mauricio.sobrinho223@gmail.com, E-mail: e.a.salomao@gmail.com, E-mail: arthur1303@gmail.com, E-mail: moysesnavarro@yahoo.com.br, E-mail: aacs@cdtn.br [Centro de Desenvolvimento da Tecnologia Nuclear (CDTN/CNEN-MG), Belo Horizonte, MG (Brazil)

2017-07-01

The Counter Current Flow Limitation (CCFL) phenomenon, specifically the control that the gas exerts in a liquid flow in the opposite direction, is of real importance in the study of design and operation of various industrial sectors, particularly the nuclear industry. In nuclear engineering, such a phenomenon can occur in a loss of coolant accident (LOCA) of a Pressurized Water Reactor (PWR) when there is the need to re-flood the reactor core during an emergency cooling process. The CCFL phenomenon is being investigated at the Nuclear Technology Development Center (CDTN) thermo-hydraulics laboratory in order to better understand the flow and its limitations and thereby contribute to the improvement of its modeling for analysis of severe accidents. For this, a series of experiments were performed in CDTN in a reduced scale acrylic test section of the 'hot leg' of a PWR. The new proposed circuit is a closed loop and no water has to be discharged during the experiment. This is only possible due to the Python program, which is associated to the data acquisition system and can interface with the automated valves through the outputs of the data acquisition board to control the experiment. The trials compare the CCFL behavior for 500mm lengths of the horizontal section, for inclined duct slope 50° for a diameter of 54mm pipe's diameter. This paper describes the new tests in comparison to tests performed in the past. (author)

Determination of the necessary parameters for a protection insulation disk of sodium circuit weighing system for thermomechanical and small component tests

International Nuclear Information System (INIS)

Bloch, M.; Cesar, S.B.G.

1985-01-01

The parameters requisited for a plastic disk used as thermal insulation, between feeding tank and weghing system, where the tank is supported are defined. The tank and weghing system are component parts of sodium circuit for thermomechanical and small component tests. During the circuit operation the temperature at tank reaches 600 0 C, however the temperature at weghing system should not reach 50 0 C. The temperature distribution in insulation disk is obtained by finit element method in function of thickness and thermal conductivity of material. The results obtained indicate for thickness E = 32 mm should be K 0 C and for E = 48 mm the thermal conductivity should be K 0 C. In both cases the pressure is σ > 14.5 Kgf/mm 2 . (M.C.K.) [pt

Development of a Three-Tier Test to Assess Misconceptions about Simple Electric Circuits

Science.gov (United States)

Pesman, Haki; Eryilmaz, Ali

2010-01-01

The authors aimed to propose a valid and reliable diagnostic instrument by developing a three-tier test on simple electric circuits. Based on findings from the interviews, open-ended questions, and the related literature, the test was developed and administered to 124 high school students. In addition to some qualitative techniques for…

Aluminum nitride nanophotonic circuits operating at ultraviolet wavelengths

Energy Technology Data Exchange (ETDEWEB)

Stegmaier, M.; Ebert, J.; Pernice, W. H. P., E-mail: wolfram.pernice@kit.edu [Institute of Nanotechnology, Karlsruhe Institute of Technology, 76133 Karlsruhe (Germany); Meckbach, J. M.; Ilin, K.; Siegel, M. [Institute of Micro- und Nanoelectronic Systems, Karlsruhe Institute of Technology, 76187 Karlsruhe (Germany)

2014-03-03

Aluminum nitride (AlN) has recently emerged as a promising material for integrated photonics due to a large bandgap and attractive optical properties. Exploiting the wideband transparency, we demonstrate waveguiding in AlN-on-Insulator circuits from near-infrared to ultraviolet wavelengths using nanophotonic components with dimensions down to 40 nm. By measuring the propagation loss over a wide spectral range, we conclude that both scattering and absorption of AlN-intrinsic defects contribute to strong attenuation at short wavelengths, thus providing guidelines for future improvements in thin-film deposition and circuit fabrication.

Automatic circuit analysis based on mask information

International Nuclear Information System (INIS)

Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.

1976-01-01

The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program

Interface Circuit For Printer Port

Science.gov (United States)

Tucker, Jerry H.; Yadlowsky, Ann B.

1991-01-01

Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

Current-mode minimax circuit

NARCIS (Netherlands)

Wassenaar, R.F.

1992-01-01

The minimum-maximum (minimax) circuit selects the minimum and maximum of two input currents. Four transistors in matched pairs are operated in the saturation region. Because the behavior of the circuit is based on matched devices and is independent of the relationship between the drain current and

Test report - caustic addition system operability test procedure

International Nuclear Information System (INIS)

Parazin, R.E.

1995-01-01

This Operability Test Report documents the test results of test procedure WHC-SD-WM-OTP-167 ''Caustic Addition System Operability Test Procedure''. The Objective of the test was to verify the operability of the 241-AN-107 Caustic Addition System. The objective of the test was met

Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields

International Nuclear Information System (INIS)

Inoue, Kenta; Narama, Tatsuya; Yamanashi, Yuki; Yoshikawa, Nobuyuki; Takeuchi, Naoki

2015-01-01

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells. (paper)

The Fault Detection, Localization, and Tolerant Operation of Modular Multilevel Converters with an Insulated Gate Bipolar Transistor (IGBT Open Circuit Fault

Directory of Open Access Journals (Sweden)

Wei Li

2018-04-01

Full Text Available Reliability is one of the critical issues for a modular multilevel converter (MMC since it consists of a large number of series-connected power electronics submodules (SMs. In this paper, a complete control strategy including fault detection, localization, and tolerant operation is proposed for the MMC under an insulated gate bipolar transistor (IGBT open circuit fault. According to the output characteristics of the SM with the open-circuit fault of IGBT, a fault detection method based on the circulating current and output current observation is used. In order to further precisely locate the position of the faulty SM, a fault localization method based on the SM capacitor voltage observation is developed. After the faulty SM is isolated, the continuous operation of the converter is ensured by adopting the fault-tolerant strategy based on the use of redundant modules. To verify the proposed fault detection, fault localization, and fault-tolerant operation strategies, a 900 kVA MMC system under the conditions of an IGBT open circuit is developed in the Matlab/Simulink platform. The capabilities of rapid detection, precise positioning, and fault-tolerant operation of the investigated detection and control algorithms are also demonstrated.

Manufacturing experience and test results of the PS prototype flexible hybrid circuit for the CMS Tracker Upgrade

CERN Document Server

Kovacs, Mark Istvan; Gadek, Tomasz; Honma, Alan; Vasey, Francois

2017-01-01

The CMS Tracker Phase-2 Upgrade for HL-LHC requires High Density Interconnect (HDI) flexible hybrid circuits to build modules with low mass and high granularity. The hybrids are carbon fibre reinforced flexible circuits with flip-chips and passives. Three different manufacturers produced prototype hybrids for the Pixel-Strip type modules. The first part of the presentation will focus on the design challenges of this state of the art circuit. Afterwards, the difficulties and experience related to the circuit manufacturing and assembly are presented. The description of quality inspection methods with comprehensive test results will lead to the conclusion.

Circuit arrangement of an electronic component for the design of fail-safe protective circuits

International Nuclear Information System (INIS)

Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

1974-01-01

The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

Equivalent Electrical Circuits of Thermoelectric Generators under Different Operating Conditions

Directory of Open Access Journals (Sweden)

Saima Siouane

2017-03-01

Full Text Available Energy harvesting has become a promising and alternative solution to conventional energy generation patterns to overcome the problem of supplying autonomous electrical systems. More particularly, thermal energy harvesting technologies have drawn a major interest in both research and industry. Thermoelectric Generators (TEGs can be used in two different operating conditions, under constant temperature gradient or constant heat flow. The commonly used TEG electrical model, based on a voltage source in series with an electrical resistance, shows its limitations especially under constant heat flow conditions. Here, the analytical electrical modeling, taking into consideration the internal and contact thermal resistances of a TEG under constant temperature gradient and constant heat flow conditions, is first given. To give further insight into the electrical behavior of a TEG module in different operating conditions, we propose a new and original way of emulating the above analytical expressions with usual electronics components (voltage source, resistors, diode, whose values are determined with the TEG’s parameters. Note that such a TEG emulation is particularly suited when designing the electronic circuitry commonly associated to the TEG, to realize both Maximum Power Point Tracking and output voltage regulation. First, the proposed equivalent electrical circuits are validated through simulation with a SPICE environment in static operating conditions using only one value of either temperature gradient or heat flow. Then, they are also analyzed in dynamic operating conditions where both temperature gradient and heat flow are considered as time-varying functions.

Short-circuit tests of 1650 and 96 MVA transformers for 1300 MW french nuclear power plants

International Nuclear Information System (INIS)

Mailhot, M.

1989-01-01

Power evacuation and feeding of the auxiliaries directly from the 400 kV grid are sensitive points governing the security of 1300 MW PWR Nuclear Power Plants of the French Program. These two different functions are provided by two specific types of transformers. - Banks of 3 single-phase 550 MVA - 400 kV/20 kV transformers. - Three-phase 96 MVA - 400 kV / 3 x 6.8 kV transformers. These passive elements must have a never failing reliability and assure a continuous service in spite of electric, thermal and mechanical stresses that may occur during the lifetime of the power plant. Dielectric and thermal tests carried out in the manufacturers test floors insure these stresses withstand capabilities of transformers. In France, high short-circuit power for the 400 kV network added to often low impedance voltages for transformers impose on them very high stresses during short-circuits. Calculation and experimentation on scale or partial models are not sufficient to insure short-circuit currents withstand capabilities of transformers. The margin of uncertainty dependent on obligatory extrapolations for this kind of complex systems [steel, magnetic sheets, copper, oil, paper and transformerboard] can be reduced in a significant way only by real scale tests on prototypes. These tests that need both high power and voltage cannot be performed in manufacturers test floors. So, in France they are carried out at the EDF Les Renardieres Laboratory. Following paper deals with SHELL TYPE TRANSFORMERS which, particularly thanks to their interleaved rectangular windings display a great resistance to short-circuit stresses

Treatment of Wastewater from Electroplating, Metal Finishing and Printed Circuit Board Manufacturing. Operation of Wastewater Treatment Plants Volume 4.

Science.gov (United States)

California State Univ., Sacramento. Dept. of Civil Engineering.

One of four manuals dealing with the operation of wastewater plants, this document was designed to address the treatment of wastewater from electroplating, metal finishing, and printed circuit board manufacturing. It emphasizes how to operate and maintain facilities which neutralize acidic and basic waters; treat waters containing metals; destroy…

Bulk-assay calorimeter: Part 1. System design and operation. Part 2. Calibration and testing

International Nuclear Information System (INIS)

Perry, R.B.; Roche, C.T.; Harkness, A.L.; Winslow, G.H.; Youngdahl, G.A.; Lewis, R.N.; Jung, E.A.

1982-01-01

The Bulk-Assay Calorimeter is designed to measure the thermal power emitted by plutonium-containing samples. The sample power range of the instrument is 1.4 to 22.4 W. The instrument package consists of the calorimeter measurement chamber, the control circuit power bin, and the data acquisition system. Two sample preheating chambers and five calorimeter canisters for containing the samples are included. A set of 32 test points which monitor voltages at points within the calorimeter and its control circuitry are accessed by the data acquisition system. The use of the test points is described. System start-up and checkout are described. Sample assay and preheater operation procedures are given. The data acquisition system and data analysis software are described. The calorimeter was calibrated at 23 points with heat sources from 1.4 to 22.4 watts. The combined measurement error varied with sample power from 1.4% to 0.1% over the range of calibration measurements. Circuit diagrams for the calorimeter and schematics for the data acquisition system are included

Geometrical considerations in the transient ionization testing of digital logic circuits

International Nuclear Information System (INIS)

Johnston, A.

1982-01-01

Mechanisms are identified that can cause the transient response of digital logic circuits to depend on the logic state in which they are irradiated. Several of these mechanisms depend on surface topology, and for these cases the sensitive logic states can be determined by examining the topology. General approaches for transient radiation testing are also discussed for several MSI and LSI device technologies

Optimizing Performance of SABC Comminution Circuit of the Wushan Porphyry Copper Mine—A Practical Approach

Directory of Open Access Journals (Sweden)

Wei Zhang

2016-12-01

Full Text Available This research is focused on the Phase I SABC milling circuit of the Wushan porphyry copper mine. Improvements to the existing circuit were targeted without any significant alterations to existing equipment or the SABC circuit. JKSimMet simulations were used to test various operating and design conditions to improve the comminution process. Modifications to the SABC comminution circuit included an increase in the SAG mill ball charge from 8% to 10% v/v; an increase in the mill ball charge from 23% v/v to 27% v/v; an increase in the maximum operating power draw in the ball mill to 5800 kW; the replacement of the HP Series pebble crusher with a TC84 crusher; and the addition of a pebble bin. Following these improvements, an increase in circuit throughput, a reduction in energy consumption, and an increase in profitability were obtained.

Design and test of a capacitance detection circuit based on a transimpedance amplifier

International Nuclear Information System (INIS)

Mu Linfeng; Zhang Wendong; He Changde; Zhang Rui; Song Jinlong; Xue Chenyang

2015-01-01

This paper presents a transimpedance amplifier (TIA) capacitance detection circuit aimed at detecting micro-capacitance, which is caused by ultrasonic stimulation applied to the capacitive micro-machined ultrasonic transducer (CMUT). In the capacitance interface, a TIA is adopted to amplify the received signal with a center frequency of 400 kHz, and finally detect ultrasound pressure. The circuit has a strong anti-stray property and this paper also studies the calculation of compensation capacity in detail. To ensure high resolution, noise analysis is conducted. After optimization, the detected minimum ultrasound pressure is 2.1 Pa, which is two orders of magnitude higher than the former. The test results showed that the circuit was sensitive to changes in ultrasound pressure and the distance between the CMUT and stumbling block, which also successfully demonstrates the functionality of the developed TIA of the analog-front-end receiver. (paper)

49 CFR 236.721 - Circuit, control.

Science.gov (United States)

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Circuit, control. 236.721 Section 236.721..., MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Definitions § 236.721 Circuit, control. An electrical circuit between a source of electric energy and a device which it operates. ...

Radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

Derbenwick, G.F.; Hughes, R.C.

1977-01-01

Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

SPECTR System Operational Test Report

International Nuclear Information System (INIS)

Landman, W.H. Jr.

2011-01-01

This report overviews installation of the Small Pressure Cycling Test Rig (SPECTR) and documents the system operational testing performed to demonstrate that it meets the requirements for operations. The system operational testing involved operation of the furnace system to the design conditions and demonstration of the test article gas supply system using a simulated test article. The furnace and test article systems were demonstrated to meet the design requirements for the Next Generation Nuclear Plant. Therefore, the system is deemed acceptable and is ready for actual test article testing.

A high speed, wide dynamic range digitizer circuit for photomultiplier tubes

Energy Technology Data Exchange (ETDEWEB)

Yarema, R.J.; Foster, G.W.; Knickerbocker, K.; Sarraj, M.; Tschirhart, R.; Whitmore, J.; Zimmerman, T. [Fermi National Accelerator Lab., Batavia, IL (United States); Lindgren, M. [Univ. of California, Los Angeles, CA (United States). Physics Dept.

1994-06-01

High energy physics experiments running at high interaction rates frequently require long record lengths for determining a level 1 trigger. The easiest way to provide a long event record is by digital means. In applications requiring wide dynamic range, however, digitization of an analog signal to obtain the digital record has been impossible due to lack of high speed, wide range FADCs. One such application is the readout of thousands of photomultiplier tubes in fixed target and colliding beam experiment calorimeters. A circuit has been designed for digitizing PMT signals over a wide dynamic range (17--18 bits) with 8 bits of resolution at rates up to 53 MHz. Output from the circuit is in a floating point format with a 4 bit exponent and an 8 bit mantissa. The heart of the circuit is a full custom integrated circuit called the QIE (Charge Integrator and Encoder). The design of the QIE and associated circuitry reported here permits operation over a 17 bit dynamic range. Tests of the circuit with a PMT input and a pulsed laser have provided respectable results with little off line correction. Performance of the circuit for demanding applications can be significantly enhanced with additional off line correction. Circuit design, packaging issues, and test results of a multirange device are presented for the first time.

Design and implementation of a programming circuit in radiation-hardened FPGA

International Nuclear Information System (INIS)

Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Chen, Stanley L.

2011-01-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 x 10 5 rad(Si), dose rate survivability of 1.5 x 10 11 rad(Si)/s and neutron fluence immunity of 1 x 10 14 n/cm 2 .

A high speed, wide dynamic range digitizer circuit for photomultiplier tubes

International Nuclear Information System (INIS)

Yarema, R.J.; Foster, G.W.; Knickerbocker, K.; Sarraj, M.; Tschirhart, R.; Whitmore, J.; Zimmerman, T.; Lindgren, M.

1994-06-01

High energy physics experiments running at high interaction rates frequently require long record lengths for determining a level 1 trigger. The easiest way to provide a long event record is by digital means. In applications requiring wide dynamic range, however, digitization of an analog signal to obtain the digital record has been impossible due to lack of high speed, wide range FADCs. One such application is the readout of thousands of photomultiplier tubes in fixed target and colliding beam experiment calorimeters. A circuit has been designed for digitizing PMT signals over a wide dynamic range (17--18 bits) with 8 bits of resolution at rates up to 53 MHz. Output from the circuit is in a floating point format with a 4 bit exponent and an 8 bit mantissa. The heart of the circuit is a full custom integrated circuit called the QIE (Charge Integrator and Encoder). The design of the QIE and associated circuitry reported here permits operation over a 17 bit dynamic range. Tests of the circuit with a PMT input and a pulsed laser have provided respectable results with little off line correction. Performance of the circuit for demanding applications can be significantly enhanced with additional off line correction. Circuit design, packaging issues, and test results of a multirange device are presented for the first time

Design and implementation of a programming circuit in radiation-hardened FPGA

Science.gov (United States)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Synchronization circuit for shaping electron beam picosecond pulses

International Nuclear Information System (INIS)

Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.

1985-01-01

A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes

Control circuit for transformer relay

International Nuclear Information System (INIS)

Wyatt, G.A.

1984-01-01

A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

ESCRIME: testing bench for advanced operator workstations in future plants

International Nuclear Information System (INIS)

Poujol, A.; Papin, B.

1994-01-01

The problem of optimal task allocation between man and computer for the operation of nuclear power plants is of major concern for the design of future plants. As the increased level of automation induces the modification of the tasks actually devoted to the operator in the control room, it is very important to anticipate these consequences at the plant design stage. The improvement of man machine cooperation is expected to play a major role in minimizing the impact of human errors on plant safety. The CEA has launched a research program concerning the evolution of the plant operation in order to optimize the efficiency of the human/computer systems for a better safety. The objective of this program is to evaluate different modalities of man-machine share of tasks, in a representative context. It relies strongly upon the development of a specific testing facility, the ESCRIME work bench, which is presented in this paper. It consists of an EDF 1300MWe PWR plant simulator connected to an operator workstation. The plant simulator model presents at a significant level of details the instrumentation and control of the plant and the main connected circuits. The operator interface is based on the generalization of the use of interactive graphic displays, and is intended to be consistent to the tasks to be performed by the operator. The functional architecture of the workstation is modular, so that different cooperation mechanisms can be implemented within the same framework. It is based on a thorough analysis and structuration of plant control tasks, in normal as well as in accident situations. The software architecture design follows the distributed artificial intelligence approach. Cognitive agents cooperate in order to operate the process. The paper presents the basic principles and the functional architecture of the test bed and describes the steps and the present status of the program. (author)

Stability of operation versus temperature of a three-phase clock-driven chaotic circuit

International Nuclear Information System (INIS)

Zhou Ji-Chao; Son Hyunsik; Song Han Jung; Kim Namtae

2013-01-01

We evaluate the influence of temperature on the behavior of a three-phase clock-driven metal—oxide—semiconductor (MOS) chaotic circuit. The chaotic circuit consists of two nonlinear functions, a level shifter, and three sample and hold blocks. It is necessary to analyze a CMOS-based chaotic circuit with respect to variation in temperature for stability because the circuit is sensitive to the behavior of the circuit design parameters. The temperature dependence of the proposed chaotic circuit is investigated via the simulation program with integrated circuit emphasis (SPICE) using 0.6-μm CMOS process technology with a 5-V power supply and a 20-kHz clock frequency. The simulation results demonstrate the effects of temperature on the chaotic dynamics of the proposed chaotic circuit. The time series, frequency spectra, bifurcation phenomena, and Lyapunov exponent results are provided. (general)

Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

International Nuclear Information System (INIS)

Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

1992-01-01

Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

Development of the automatic test pattern generation for NPP digital electronic circuits using the degree of freedom concept

International Nuclear Information System (INIS)

Kim, D.S.; Seong, P.H.

1995-01-01

In this paper, an improved algorithm for automatic test pattern generation (ATG) for nuclear power plant digital electronic circuits--the combinational type of logic circuits is presented. For accelerating and improving the ATG process for combinational circuits the presented ATG algorithm has the new concept--the degree of freedom (DF). The DF, directly computed from the system descriptions such as types of gates and their interconnections, is the criterion to decide which among several alternate lines' logic values required along each path promises to be the most effective in order to accelerate and improve the ATG process. Based on the DF the proposed ATG algorithm is implemented in the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, it is shown that the AFDS using the ATG algorithm makes Universal Card (UV Card) testing much faster than the present testing practice or by using exhaustive testing sets

A novel ternary logic circuit using Josephson junction

International Nuclear Information System (INIS)

Morisue, M.; Oochi, K.; Nishizawa, M.

1989-01-01

This paper describes a novel Josephson complementary ternary logic circuit named as JCTL. This fundamental circuit is constructed by combination of two SQUIDs, one of which is switched in the positive direction and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, NOT and Double NOT in ternary form. The principle of the operation and design criteria are described in detail. The results of the simulation show that the reliable operations of these circuits can be achieved with a high performance

Magnonic logic circuits

International Nuclear Information System (INIS)

Khitun, Alexander; Bao Mingqiang; Wang, Kang L

2010-01-01

We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

Operational Excellence through Schedule Optimization and Production Simulation of Application Specific Integrated Circuits.

Energy Technology Data Exchange (ETDEWEB)

Flory, John Andrew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Padilla, Denise D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gauthier, John H. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Zwerneman, April Marie [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Miller, Steven P [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2016-05-01

Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performance evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.

Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

International Nuclear Information System (INIS)

Estreich, D.B.

1978-11-01

A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

Physically based arc-circuit interaction

International Nuclear Information System (INIS)

Zhong-Lie, L.

1984-01-01

An integral arc model is extended to study the interaction of the gas blast arc with the test circuit in this paper. The deformation in the waveshapes of arc current and voltage around the current zero has been formulated to first approximation by using a simple model of arc voltage based on the arc core energy conservation. By supplementing with the time scale for the radiation, the time rates of arc processes were amended. Both the contributions of various arc processes and the influence of circuit parameters to the arc-circuit interaction have been estimated by this theory. Analysis generated a new method of calculating test circuit parameters which improves the accurate simulation of arc-circuit interaction. The new method agrees with the published experimental results

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

49 CFR 236.587 - Departure test.

Science.gov (United States)

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Departure test. 236.587 Section 236.587..., Train Control and Cab Signal Systems Inspection and Tests; Locomotive § 236.587 Departure test. (a) The...: (1) Operation over track elements; (2) Operation over test circuit; (3) Use of portable test...

A 35fJ/Step differential successive approximation capacitive sensor readout circuit with quasi-dynamic operation

KAUST Repository

Omran, Hesham

2016-10-06

We propose a successive-approximation capacitive sensor readout circuit that achieves 35fJ/Step energy efficiency FoM, which represents 4× improvement over the state-of-the-art. A fully differential architecture is employed to provide robustness against common mode noise and errors. An inverter-based amplifier with near-threshold biasing provides robust, fast, and energy-efficient operation. Quasi-dynamic operation is used to maintain the energy efficiency for a scalable sample rate. A hybrid coarse-fine capacitive DAC achieves 11.7bit effective resolution in a compact area. © 2016 IEEE.

Robustness to Faults Promotes Evolvability: Insights from Evolving Digital Circuits.

Science.gov (United States)

Milano, Nicola; Nolfi, Stefano

2016-01-01

We demonstrate how the need to cope with operational faults enables evolving circuits to find more fit solutions. The analysis of the results obtained in different experimental conditions indicates that, in absence of faults, evolution tends to select circuits that are small and have low phenotypic variability and evolvability. The need to face operation faults, instead, drives evolution toward the selection of larger circuits that are truly robust with respect to genetic variations and that have a greater level of phenotypic variability and evolvability. Overall our results indicate that the need to cope with operation faults leads to the selection of circuits that have a greater probability to generate better circuits as a result of genetic variation with respect to a control condition in which circuits are not subjected to faults.

Fast frequency divider circuit using combinational logic

Science.gov (United States)

Helinski, Ryan

2017-05-30

The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.

Analog front end circuit design of CSNS beam loss monitor system

International Nuclear Information System (INIS)

Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

2013-01-01

The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

Self-powered 'AND' logic circuit of dynamic type with positive safety and application of said 'AND' circuit

International Nuclear Information System (INIS)

Lefebvre, Claude; Therond, J.P.

1974-01-01

The present invention relates to a self-powered 'AND' logic circuit of dynamic type with positive safety, which delivers on duty operation an output signal equal to the logic product of the input logic signals. The invention relates also to the use of said 'AND' logic circuits in developing n/m logics also of dynamic types with positive safety, delivering on duty operation a zero valued signal when, at least n of the m input signals have the value zero. This type of logics can be inserted in nuclear reactor protection systems; when the value of the reactor operating physical characteristics go out of the safety margins, or true trouble affects 'AND' circuits the value of the output signal is zero, that triggers off the safety absorber drap, for instance [fr

Heavy ion tests on programmable VLSI

International Nuclear Information System (INIS)

Provost-Grellier, A.

1989-11-01

The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

Corrosion product behaviour in the primary circuit of the KNK nuclear reactor facility

International Nuclear Information System (INIS)

Stamm, H.H.; Stade, K.Ch.

1976-01-01

During nuclear operation of the KNK facility from 1972 until September 1974 the composition and behaviour of radionuclides occuring in the primary circuit were investigated. Besides traces of 140 Ba/ 140 La, no fission product activity was detectable in the KNK primary circuit. The fuel element purification from sodium deposits (prior to transport to the reprocessing plant) did not yield any indication of a fuel element failure during KNK-I operation. The activity inventory of the primary loop was exclusively made up of activated corrosion products and 22 Na. The main activity was due to 65 Zn, followed by 54 Mn, 22 Na, sup(110m)Ag, 182 Ta, 60 Co and 124 Sb. It was found that the sorption of 65 Zn and 54 Mn on crucibles made from nickel was condiserably higher than on vessels made from other materials. This observation was confirmed both in tests with material samples from the primary circuit and for disks of gate valves of the primary circuit. sup(110m)Ag did hardly exhibit any sorption effects and had been dissolved largely homogeneously in the hot primary coolant. In the first primary cold trap which was removed from the circuit after some 20,000 hours of operation, only 65 Zn and 54 Mn were detected in addition to traces of 60 Co and 182 Ta. (author)

30 CFR 57.6407 - Circuit testing.

Science.gov (United States)

2010-07-01

...) Continuity of each electric detonator in the blasthole prior to stemming and connection to the blasting line... connection of electric detonator series; and (4) Total blasting circuit resistance prior to connection to the...) Continuity of blasting lines prior to the connection of electric detonators. Nonelectric Blasting—Surface and...

Seeking a unified framework for cerebellar function and dysfunction: from circuit operations to cognition

Directory of Open Access Journals (Sweden)

Egidio eD‘Angelo

2013-01-01

Full Text Available Following the fundamental recognition of its involvement in sensory-motor coordination and learning, the cerebellum is now also believed to take part in the processing of cognition and emotion. This hypothesis is recurrent in numerous papers reporting anatomical and functional observations, and it requires an explanation. We argue that a similar circuit structure in all cerebellar areas may carry out various operations using a common computational scheme. On the basis of a broad review of anatomical data, it is conceivable that the different roles of the cerebellum lie in the specific connectivity of the cerebellar modules, with motor, cognitive and emotional functions (at least partially segregated into different cerebro-cerebellar loops. We here develop a conceptual and operational framework based on multiple interconnected levels (a meta-levels hypothesis: from cellular/molecular to network mechanisms leading to generation of computational primitives, thence to high-level cognitive/emotional processing, and finally to the sphere of mental function and dysfunction. The main concept explored is that of intimate interplay between timing and learning (reminiscent of the timing and learning machine capabilities long attributed to the cerebellum, which reverberates from cellular to circuit mechanisms. Subsequently, integration within large-scale brain loops could generate the disparate cognitive/emotional and mental functions in which the cerebellum has been implicated. We propose, therefore, that the cerebellum operates as a general-purpose co-processor, whose effects depend on the specific brain centers to which individual modules are connected. Abnormal functioning in these loops could eventually contribute to the pathogenesis of major brain pathologies including not just ataxia but also dyslexia, autism, schizophrenia and depression.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit includes a light emitting diode which from time to time illuminates a photo-transistor, the photo-transistor serving when its output reaches a predetermined value to operate a trigger circuit. In order to allow for aging of the components, the current flow through the diode is increased when the output from the transistor falls below a known level. Conveniently, this is achieved by having a transistor in parallel with the diode, and turning the transistor off when the output from the phototransistor becomes too low. The circuit is designed to control the ignition system in an automobile engine.

Fault Modeling and Testing for Analog Circuits in Complex Space Based on Supply Current and Output Voltage

Directory of Open Access Journals (Sweden)

Hongzhi Hu

2015-01-01

Full Text Available This paper deals with the modeling of fault for analog circuits. A two-dimensional (2D fault model is first proposed based on collaborative analysis of supply current and output voltage. This model is a family of circle loci on the complex plane, and it simplifies greatly the algorithms for test point selection and potential fault simulations, which are primary difficulties in fault diagnosis of analog circuits. Furthermore, in order to reduce the difficulty of fault location, an improved fault model in three-dimensional (3D complex space is proposed, which achieves a far better fault detection ratio (FDR against measurement error and parametric tolerance. To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT method. By adding redundant bypassing-components in the circuit under test (CUT, this method achieves excellent fault isolation ratio (FIR in ambiguity group isolation. The efficacy of the proposed model and testing method is validated through experimental results provided in this paper.

Pulse generator circuit triggerable by nuclear radiation

International Nuclear Information System (INIS)

Fredrickson, P.B.

1980-01-01

A pulse generator circuit triggerable by a pulse of nuclear radiation is described. The pulse generator circuit includes a pair of transistors arranged, together with other electrical components, in the topology of a standard monostable multivibrator circuit. The circuit differs most significantly from a standard monostable multivibrator circuit in that the circuit is adapted to be triggered by a pulse of nuclear radiation rather than electrically and the transistors have substantially different sensitivities to radiation, due to different physical and electrical characteristics and parameters. One of the transistors is employed principally as a radiation detector and is in a normally non-conducting state and the other transistor is normally in a conducting state. When the circuit is exposed to a pulse of nuclear radiation, currents are induced in the collector-base junctions of both transistors but, due to the different radiation sensitivities of the transistors, the current induced in the collector-base junction of the radiation-detecting transistor is substantially greater than that induced in the collector-base junction of the other transistor. The pulse of radiation causes the radiation-detecting transistor to operate in its conducting state, causing the other transistor to operate in its non-conducting state. As the radiation-detecting transistor operates in its conducting state, an output signal is produced at an output terminal connected to the radiation-detecting transistor indicating the presence of a predetermined intensity of nuclear radiation

Logarithmic circuit with wide dynamic range

Science.gov (United States)

Wiley, P. H.; Manus, E. A. (Inventor)

1978-01-01

A circuit deriving an output voltage that is proportional to the logarithm of a dc input voltage susceptible to wide variations in amplitude includes a constant current source which forward biases a diode so that the diode operates in the exponential portion of its voltage versus current characteristic, above its saturation current. The constant current source includes first and second, cascaded feedback, dc operational amplifiers connected in negative feedback circuit. An input terminal of the first amplifier is responsive to the input voltage. A circuit shunting the first amplifier output terminal includes a resistor in series with the diode. The voltage across the resistor is sensed at the input of the second dc operational feedback amplifier. The current flowing through the resistor is proportional to the input voltage over the wide range of variations in amplitude of the input voltage.

Mechanisms governing the physico-chemical processes of transfer in NPP circuits

International Nuclear Information System (INIS)

Brusakov, V.P.; Sedov, V.M.; Khitrov, Yu.A.; Rybalchenko, I.L.

1983-01-01

The paper deals with the theoretical physico-chemical processes of corrosion products and their radionuclide transport in NPS circuits by thermoelectromotive and electromotive forces of microgalvanic couples. The laboratory and rig test results as well as the NPP operating experience data confirm the developed theoretical concept validity

NRC Information No. 90-41: Potential failure of General Electric Magne-Blast circuit breakers and AK circuit breakers

International Nuclear Information System (INIS)

Rossi, C.E.

1992-01-01

This information notice is intended to alert addressees to potential safety concerns that may result from failures of GE vertical lift (AM) and horizontal draw-out (AMH) Magne-Blast circuit breakers utilizing ML-13 operating mechanisms to open or close them and AK circuit breakers. The particular breaker failures reported herein were caused by operating problems with prop springs, snap rings and lubricating grease. GE Nuclear Energy has informed the NRC that it is aware of these problems and that GE routinely checks and corrects them if the circuit breakers are serviced at one of the four GE nuclear service centers in the US. However, the NRC is aware that some utilities may have their circuit breakers repaired or serviced at facilities other than the four GE nuclear service centers

Testing device for control rod drives

International Nuclear Information System (INIS)

Hayakawa, Toshifumi.

1992-01-01

A testing device for control rod drives comprises a logic measuring means for measuring an output signal from a control rod drive logic generation circuit, a control means for judging the operation state of a control rod and a man machine interface means for outputting the result of the judgement. A driving instruction outputted from the control rod operation device is always monitored by the control means, and if the operation instruction is stopped, a testing signal is outputted to the control rod control device to simulate a control rod operation. In this case, the output signal of the control rod drive logic generation circuit is held in a control rod drive memory means and intaken into a logic analysis means for measurement and an abnormality is judged by the control means. The stopping of the control rod drive instruction is monitored and the operation abnormality of the control rod is judged, to mitigate the burden of an operator. Further, the operation of the control rod drive logic generation circuit can be confirmed even during a nuclear plant operation by holding the control rod drive instruction thereby enabling to improve maintenance efficiency. (N.H.)

Integrated optical switch circuit operating under FPGA control

NARCIS (Netherlands)

Stabile, R.; Zal, M.; Williams, K.A.; Bienstman, P.; Morthier, G.; Roelkens, G.; et al., xx

2011-01-01

Integrated photonic circuits are enabling an abrupt step change in networking systems providing massive bandwidth and record transmission. The increasing complexity of high connectivity photonic integrated switches requires sophisticated control planes and more intimate high speed electronics. Here

Test model of the fast thyristor circuit breaker, for TORE SUPRA

International Nuclear Information System (INIS)

Bareyt, B.; Leloup, C.; Rijnoudt, E.

1984-01-01

The tokamak TORE SUPRA, permits, owing to the toroidal superconducting coils and to the poloidal field system performances, long discharges (30 s and more), for a plasma current of typically 2 MA. The poloidal field system uses the magnetic energy initially stored, for the ignition and the fast rise of the plasma current, by forcing the primary current to flow through a resistor after breaking the main rectifier current by a fast thyristor circuit breaker. In order to test the technical capabilities of such a breaker system made of fast thyristors, in series and in parallel, after a single thyristor test model T1 the series arrangement was studied on a 24 thyristor test model T2 and the parallel arrangement problems, led the manufacturer CGEE Alsthom, to build a new test model T3. (author)

Arithmetic circuits for DSP applications

CERN Document Server

Stouraitis, Thanos

2017-01-01

Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

Installations having pressurised fluid circuits

International Nuclear Information System (INIS)

Rigg, S.; Grant, J.

1977-01-01

Reference is made to nuclear installations having pressurised coolant flow circuits. Breaches in such circuits may quickly result in much damage to the plant. Devices such as non-return valves, orifice plates, and automatically operated shut-off valves have been provided to prevent or reduce fluid flow through a breached pipe line, but such devices have several disadvantages; they may present large restrictions to normal flow of coolant, and may depend on the operation of ancillary equipment, with consequent delay in bringing them into operation in an emergency. Other expedients that have been adopted to prevent or reduce reverse flow through an upstream breach comprise various forms of hydraulic counter flow brakes. The arrangement described has at least one variable fluid brake comprising a fluidic device connected into a duct in the pressurised circuit, the device having an inlet, an outlet, a vortex chamber between the inlet and outlet, a control jet for introducing fluid into the vortex chamber, connections communicating the inlet and the outlet into one part of the circuit and the control jet into another region at a complementary pressure so that, in the event of a breach in the circuit in one region, fluid passes from the other region to enter the vortex chamber to stimulate pressure to create a flow restricting vortex in the chamber that reduces flow through the breach. The system finds particular application to stream generating pressure tube reactors, such as the steam generating heavy water reactor at UKAEA, Winfrith. (U.K.)

Short-Circuit Characterization of 10 kV 10A 4H-SiC MOSFET

DEFF Research Database (Denmark)

Eni, Emanuel-Petre; Beczkowski, Szymon; Munk-Nielsen, Stig

2016-01-01

The short-circuit capability of a power device is highly relevant for converter design and fault protection. In this paper a 10kV 10A 4H-SiC MOSFET is characterized and its short circuit withstand capability is studied and analyzed at 6 kV DC-link voltage. The test setup for this study is also...... introduced as its design, especially the inductance in the switching loop, can affect the experimental results. The study aims to present insights specific to the device which are different from that of silicon (Si) based devices. During the short-circuit operation, MOSFET saturation current, ID...

Irradiation of electronic components and circuits at the Portuguese Research Reactor: Lessons learned

Energy Technology Data Exchange (ETDEWEB)

Marques, J.G.; Ramos, A.R.; Fernandes, A.C.; Santos, J.P. [Centro de Ciencias e Tecnologias Nucleares, Instituto Superior Tecnico, Universidade de Lisboa, Estrada Nacional 10, 2695-066 Bobadela LRS (Portugal)

2015-07-01

The behavior of electronic components and circuits under radiation is a concern shared by the nuclear industry, the space community and the high-energy physics community. Standard commercial components are used as much as possible instead of radiation hard components, since they are easier to obtain and allow a significant reduction of costs. However, these standard components need to be tested in order to determine their radiation tolerance. The Portuguese Research Reactor (RPI) is a 1 MW pool-type reactor, operating since 1961. The irradiation of electronic components and circuits is one area where a 1 MW reactor can be competitive, since the fast neutron fluences required for testing are in most cases well below 10{sup 16} n/cm{sup 2}. A program was started in 1999 to test electronics components and circuits for the LHC facility at CERN, initially using a dedicated in-pool irradiation device and later a beam line with tailored neutron and gamma filters. Neutron filters are essential to reduce the intensity of the thermal neutron flux, which does not produce significant defects in electronic components but produces unwanted radiation from activation of contacts and packages of integrated circuits and also of the printed circuit boards. In irradiations performed within the line-of-sight of the core of a fission reactor there is simultaneous gamma radiation which complicates testing in some cases. Filters can be used to reduce its importance and separate testing with a pure gamma radiation source can contribute to clarify some irradiation results. Practice has shown the need to introduce several improvements to the procedures and facilities over the years. We will review improvements done in the following areas: - Optimization of neutron and gamma filters; - Dosimetry procedures in mixed neutron / gamma fields; - Determination of hardness parameter and 1 MeV-equivalent neutron fluence; - Temperature measurement and control during irradiation; - Follow-up of reactor

WindoWorks: A flexible program for computerized testing of accelerator control system electronic circuit boards

International Nuclear Information System (INIS)

Utterback, J.

1993-09-01

Since most accelerator control system circuit boards reside in a commercial bus architecture, such as CAMAC or VMEbus, a computerized test station is needed for exercising the boards. This test station is needed for the development of newly designed prototypes, for commissioning newly manufactured boards, for diagnosing boards which have failed in service, and for long term testing of boards with intermittent failure problems. WindoWorks was created to address these needs. It is a flexible program which runs on a PC compatible computer and uses a PC to bus crate interface. WindoWorks was designed to give the user a flexible way to test circuit boards. Each test is incapsulated into a window. By bringing up several different windows the user can run several different tests simultaneously. The windows are sizable, and moveable. They have data entry boxes so that the test can be customized to the users preference. The windows can be used in conjunction with each other in order to create supertests. There are several windows which are generic. They can be used to test basic functions on any VME (or CAMAC) board. There are other windows which have been created to test specific boards. New windows for testing specific boards can be easily created by a Pascal programmer using the WindoWorks framework

Model Comparison Exercise Circuit Training Game and Circuit Ladder Drills to Improve Agility and Speed

Directory of Open Access Journals (Sweden)

Susilaturochman Hendrawan Koestanto

2017-11-01

Full Text Available The purpose of this study was to compare: (1 the effect of circuit training game and circuit ladder drill for the agility; (2 the effect of circuit training game and circuit ladder drill on speed; (3 the difference effect of circuit training game and circuit ladder drill for the speed (4 the difference effect of circuit training game and circuit ladder drill on agility. The type of this research was quantitative with quasi-experimental methods. The design of this research was Factorial Design, with analysing data using ANOVA. The process of data collection was done by using 30 meters sprint speed test and shuttle run test during the pretest and posttest. Furthermore, the data was analyzed by using SPSS 22.0 series. Result: The circuit training game exercise program and circuit ladder drill were significant to increase agility and speed (sig 0.000 < α = 0.005 Group I, II, III had significant differences (sig 0.000 < α = 0.005. The mean of increase in speed of group I = 0.20 seconds, group II = 0.31 seconds, and group III = 0.11 seconds. The average increase agility to group I = 0.34 seconds group II = 0.60 seconds, group III = 0.13 seconds. Based on the analysis above, it could be concluded that there was an increase in the speed and agility of each group after being given a training.

Non-unitary probabilistic quantum computing circuit and method

Science.gov (United States)

Williams, Colin P. (Inventor); Gingrich, Robert M. (Inventor)

2009-01-01

A quantum circuit performing quantum computation in a quantum computer. A chosen transformation of an initial n-qubit state is probabilistically obtained. The circuit comprises a unitary quantum operator obtained from a non-unitary quantum operator, operating on an n-qubit state and an ancilla state. When operation on the ancilla state provides a success condition, computation is stopped. When operation on the ancilla state provides a failure condition, computation is performed again on the ancilla state and the n-qubit state obtained in the previous computation, until a success condition is obtained.

RF Circuit Design in Nanometer CMOS

NARCIS (Netherlands)

Nauta, Bram

2007-01-01

With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

14 CFR 33.51 - Operation test.

Science.gov (United States)

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Operation test. 33.51 Section 33.51... STANDARDS: AIRCRAFT ENGINES Block Tests; Reciprocating Aircraft Engines § 33.51 Operation test. The operation test must include the testing found necessary by the Administrator to demonstrate backfire...

Suppression of the high-frequency disturbances in low-voltage circuits caused by disconnector operation in high-voltage open-air substations

Energy Technology Data Exchange (ETDEWEB)

Savic, M.S.

1986-07-01

The switching off and on of small capacitive currents charging busbar capacitances, connection conductors and open circuit breakers with disconnectors causes high-frequency transients in high-voltage networks. In low voltage circuits, these transient processes induce dangerous overvoltages for the electronic equipment in the substation. A modified construction of the disconnector with a damping resistor was investigated. Digital simulation of the transient process in a high-voltage network during the arcing period between the disconnector contacts with and without damping resistor were performed. A significant decrease of the arcing duration and the decrease of the electromagnetic field magnitude in the vicinity of the operating disconnector were noticed. In the low voltage circuit protected with the surge arrester, the overvoltage magnitude was not affected by the damping resistor due to the arrester protection effect.

Solution of multiple circuits of steam cycle HTR system

International Nuclear Information System (INIS)

Li, Fu; Wang, Dengying; Hao, Chen; Zheng, Yanhua

2014-01-01

In order to analyze the dynamic operation performance and safety characteristics of the steam cycle high temperature gas cooled reactor (HTR) systems, it is necessary to find the solution of the whole HTR systems with all coupled circuits, including the primary circuit, the secondary circuit, and the residual heat removal system (RHRS). Considering that those circuits have their own individual fluidity and characteristics, some existing code packages for independent circuits themselves have been developed, for example THEMRIX and TINTE code for the primary circuit of the pebble bed reactor, BLAST for once through steam generator. To solve the coupled steam cycle HTR systems, a feasible way is to develop coupling method to integrate these independent code packages. This paper presents several coupling methods, e.g. the equivalent component method between the primary circuit and steam generator which reflect the close coupling relationship, the overlapping domain decomposition method between the primary circuit and the passive RHRS which reflects the loose coupling relationship. Through this way, the whole steam cycle HTR system with multiple circuits can be easily and efficiently solved by integration of several existing code packages. Based on this methodology, a code package TINTE–BLAST–RHRS was developed. Using this code package, some operation performance of HTR–PM was analyzed, such as the start-up process of the plant, and the depressurized loss of forced cooling accident when different number of residual heat removal trains is operated

14 CFR 33.89 - Operation test.

Science.gov (United States)

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Operation test. 33.89 Section 33.89... STANDARDS: AIRCRAFT ENGINES Block Tests; Turbine Aircraft Engines § 33.89 Operation test. (a) The operation test must include testing found necessary by the Administrator to demonstrate— (1) Starting, idling...

Scale model test on a novel 400 kV double-circuit composite pylon

DEFF Research Database (Denmark)

Wang, Qian; Bak, Claus Leth; Silva, Filipe Miguel Faria da

This paper investigates lightning shielding performance of a novel 400 kV double-circuit composite pylon, with the method of scale model test. Lightning strikes to overhead lines were simulated by long-gap discharges between a high voltage electrode with an impulse voltage and equivalent conductors...... around the pylon is discussed. Combined test results and striking distance equation in electro-geometric model, the approximate maximum lightning current that can lead to shielding failure is calculated. Test results verify that the unusual negative shielding angle of - 60° in the composite pylon meets...... requirement and the shielding wires provide acceptable protection from lightning strikes....

Design and validation of a high-voltage levitation circuit for electrostatic accelerometers

Energy Technology Data Exchange (ETDEWEB)

Li, G.; Wu, S. C.; Zhou, Z. B.; Bai, Y. Z.; Hu, M.; Luo, J. [MOE Key Laboratory of Fundamental Physical Quantities Measurements, School of Physics, Huazhong University of Science and Technology, Wuhan, Hubei 430074 (China)

2013-12-15

A simple high-voltage circuit with a voltage range of 0 to 900 V and an open-loop bandwidth of 11 kHz is realized by using an operational amplifier and a MOSFET combination. The circuit is used for the levitation of a test mass of 71 g, suspended below the top-electrodes with a gap distance of 57 μm, so that the performance of an electrostatic accelerometer can be tested on the ground. The translation noise of the accelerometer, limited by seismic noise, is about 4 × 10{sup −8} m/s{sup 2}/Hz{sup 1/2} at 0.1 Hz, while the high-voltage coupling noise is one-order of magnitude lower.

Aging evaluation of electrical circuits using the ECCAD system

International Nuclear Information System (INIS)

Edson, J.L.

1988-01-01

As a part of the Nuclear Regulator Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport atomic power station decommissioning project. The objective of this work was to evaluate the effectiveness of the electrical circuit characterization and diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

Graphene radio frequency receiver integrated circuit.

Science.gov (United States)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Single-event transients (SET) in analog circuits

International Nuclear Information System (INIS)

Chen Panxun; Zhou Kaiming

2006-01-01

A new phenomenon of single- event upset is introduced. The transient signal is produced in the output of analog circuits after a heavy ion strikes. The transient upset can influence the circuit connected with the output of analog circuits. For example, the output of operational amplifier can be connected with the input of a digital counter, and the pulse of sufficiently high transient output induced by an ion can increase counts of the counter. On the other hand, the transient voltage signal at the output of analog circuits can change the stage of other circuits. (authors)

Development of an Economical Interfacing Circuit for Upgrading of SEM Data Printing System

International Nuclear Information System (INIS)

Punnachaiya, S.; Thong-Aram, D.

2002-01-01

The operating conditions of a Scanning Electron Microscope (SEM) i.e., magnification, accelerating voltage, micron mark and film identification labeling, are very important for the accurate interpretation of a micrograph picture. In the old model SEM, the built-in data printing system for film identification can be inputted only the numerical number. This will be made a confusing problems when various operating conditions were applied in routine work. An economical interfacing circuit, therefore, was developed to upgrade the data printing system for capable of alphanumerical labeling. The developed circuit was tested on both data printing systems of JSM-T220 and JSM-T330 (JEOL SEM). It was found that the interfacing function worked properly and easily installed

An analysis of the operation of a single-pole relay integrated circuit device with a controlled reset ratio

Energy Technology Data Exchange (ETDEWEB)

Reshetov, N.E.

1980-01-01

Relay equipment using semiconductor components (such as those containing gates using planar transformers, and a relay in networks which control the operational time of a relay) are widely used in the automation equipment of electric power systems. A scheme where a gate in the form of an integrated circuit is used is given.

Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2016-01-01

This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

The Plateau de Bure ASTEP Platform Test in natural radiation environment of electronic components and circuits

International Nuclear Information System (INIS)

Autran, J.L.; Munteanu, D.; Sauze, S.; Roche, Ph.; Gasiot, G.; Borel, J.

2010-01-01

Reducing the size of microelectronic devices and increasing the integration density of circuits lead (following the famous Moore's law) to an increased sensitivity of circuits to natural terrestrial radiation environment. - Such sensitivity to atmospheric particles (mainly neutrons) can cause non-destructive (soft-errors) or destructive (latch-up) failures in most electronic circuits, including volatile static memories (SRAM), object of the research work carried out since 2004 on the European Test Platform ASTER. - This paper presents in details the ASTEP platform, its location, the instruments (neutron monitor of the Plateau de Bure) and the experiences (memory tester) currently installed on the Plateau de Bure. In a second part, we also report a synthesis of the key results concerning the natural radiation sensitivity of SRAM fabricated in 130 nm and 65 nm bulk silicon technologies. (authors)

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

Directory of Open Access Journals (Sweden)

Huan-Yuan Chen

2017-09-01

Full Text Available This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

Science.gov (United States)

Chen, Huan-Yuan; Chen, Chih-Chang

2017-01-01

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

Four-terminal circuit element with photonic core

Science.gov (United States)

Sampayan, Stephen

2017-08-29

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated based on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.

Project W-320, operational test procedure OTP-320-003 test report

International Nuclear Information System (INIS)

Bevins, R.R.

1998-01-01

This report documents and summarizes the results of OTP-320-003 Project W-320 Operational Testing of the WRSS Supernate Transfer System. Project W-320 Operational Test OTP-320-003 was performed to verify components of the Waste Retrieval Sluicing System (WRSS) supernate transfer system functioned as designed following construction completion and turnover to operations. All equipment operation was performed by Tank Farms Operations personnel following the operational test procedure and referenced operating procedures. Supernate Transfer line Flushing System Testing was completed over the course of approximately 4 weeks as tank farm conditions and configuration, equipment availability, and operations resources allowed. All testing was performed with the 702-AZ ventilation system and the 296-P-16 ventilation systems in operation. Test procedure OTP-320-003 required two revisions during testing to incorporate Procedure Changes Authorizations (PCAs) necessary to facilitate testing. Various sections of testing are documented on each procedure revision. The completed test procedure is included as Attachment A. Exception Reports generated during the course of testing are included as Attachment B

A proposed hardness assurance test methodology for bipolar linear circuits and devices in a space ionizing radiation environment

International Nuclear Information System (INIS)

Pease, R.L.; Brown, D.B.; Cohn, L.

1997-01-01

A hardness assurance test approach has been developed for bipolar linear circuits and devices in space. It consists of a screen for dose rate sensitivity and a characterization test method to develop the conditions for a lot acceptance test at high dose rate

Triple inverter pierce oscillator circuit suitable for CMOS

Science.gov (United States)

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

Computer controlled motor vehicle battery circuit

Energy Technology Data Exchange (ETDEWEB)

Krueger, W.R.; McAuiliffe, G.N.; Schlageter, G.A.

1986-04-01

This patent consists of a motor vehicle having a DC motor, a pedal biased to a released position and depressed by the driver to increase speed. An alternate switching means affects the vehicle speed control, a foot switch is operated by the pedal and operative when the pedal is depressed to close a circuit enabling energization of the alternate switching means. A microprocessor includes a program for controlling operation of the alternate switching means, the foot switch is operative when the pedal is released to open the enabling circuit. The program includes a register which is incremented with each passage of the logic and is responsive to the incremented count in the register to instruct a change in position of the alternate switching means.

A novel sourceline voltage compensation circuit for embedded NOR flash memory

International Nuclear Information System (INIS)

Zhang Shengbo; Yang Guangjun; Hu Jian; Xiao Jun

2014-01-01

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data “0”. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data “0” are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process. (semiconductor integrated circuits)

Method for determining the optimum mode of operation of the chemical water regime in the water-steam-circuit of power plants

International Nuclear Information System (INIS)

Sommerfeldt, P.; Reisner, H.; Hartmann, G.; Kulicke, P.

1988-01-01

The method aims at increasing the lifetime of secondary coolant circuit components in nuclear power plants through the determination of the optimum mode of operation of the chemical water regime by help of radioisotopes

A fast circuit analysis program based on microcomputer

International Nuclear Information System (INIS)

Hu Guoji

1988-01-01

A fast circuit analysis program (FCAP) is introduced. The program may be used to analyse DC operating point, frequency and transient response of fast circuit. The feature is that the model of active element is not specified. Users may choose one of many equivalent circuits. Written in FORTRAN 77, FCAP can be run on IBM PC and its compatible computers. It can be used as an assistant tool of analysis and design for fast circuits

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

Implementation of Chua's circuit using simulated inductance

Science.gov (United States)

Gopakumar, K.; Premlet, B.; Gopchandran, K. G.

2011-05-01

In this study we describe how to build an inductorless version of the classic Chua's circuit. A suitable inductor for Chua's circuit is often hard to procure. The required inductor for the circuit is designed using simple circuit elements such as resistors, capacitors and operational amplifiers. The complete circuit can be implemented by using off-the-shelf components, and it can readily be integrated on a single chip. This design of Chua's circuit allows the original dynamics to be slowed down to just a few hertz, enabling implementation of sophisticated control schemes without severe time restrictions. Another novel feature of the circuit is that losses associated with capacitors due to leakages can easily be compensated by providing negative resistance using the same setup. The chaotic behaviour of the circuit is verified by PSpice and Multisim simulation and also by experimental study on a circuit breadboard. The results give excellent agreement with each other and with the results of previous investigators.

Operational test report for LERF Basin 242AL-44 integrity test

International Nuclear Information System (INIS)

Galioto, T.M.

1994-01-01

This operational test report documents the results of LERF operational testing per operational test procedure (OTP) TFPE-WP-0231, ''LERF Basin Integrity Testing.'' The primary purpose of the OTP was to resolve test exceptions generated as a result of TFPE-WP-0184. The TOP was prepared and performed in accordance with WHC-SD-534-OTP-002, ''Operational Test Plan for the 242-A Evaporator Upgrades and the Liquid Effluent Retention Facility.'' WHC-S-086, ''Specification for Operational Testing of the Liquid Effluent Retention Facility, Basin Integrity Testing,'' identified the test requirements and acceptance criteria. The completed, signed-off test procedure is contained in Appendix A. The test log is contained in Appendix B. Section 2.1 describes all the test exceptions written during performance of the Operational Test Procedure. The test revisions generated during the testing are discussed in Section 2.2. The dispositioned test exception forms are contained in Appendix C

Control circuits in power electronics practical issues in design and implementation

CERN Document Server

Castilla, Miguel

2016-01-01

Control circuits are a key element in the operation and performance of power electronics converters. This book describes practical issues related to the design and implementation of these control circuits, and is divided into three parts - analogue control circuits, digital control circuits, and new trends in control circuits.

Optimal testing input sets for reduced diagnosis time of nuclear power plant digital electronic circuits

International Nuclear Information System (INIS)

Kim, D.S.; Seong, P.H.

1994-01-01

This paper describes the optimal testing input sets required for the fault diagnosis of the nuclear power plant digital electronic circuits. With the complicated systems such as very large scale integration (VLSI), nuclear power plant (NPP), and aircraft, testing is the major factor of the maintenance of the system. Particularly, diagnosis time grows quickly with the complexity of the component. In this research, for reduce diagnosis time the authors derived the optimal testing sets that are the minimal testing sets required for detecting the failure and for locating of the failed component. For reduced diagnosis time, the technique presented by Hayes fits best for the approach to testing sets generation among many conventional methods. However, this method has the following disadvantages: (a) it considers only the simple network (b) it concerns only whether the system is in failed state or not and does not provide the way to locate the failed component. Therefore the authors have derived the optimal testing input sets that resolve these problems by Hayes while preserving its advantages. When they applied the optimal testing sets to the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, they found that the fault diagnosis using the optimal testing sets makes testing the digital electronic circuits much faster than that using exhaustive testing input sets; when they applied them to test the Universal (UV) Card which is a nuclear power plant digital input/output solid state protection system card, they reduced the testing time up to about 100 times

Performance of the Superconducting Corrector Magnet Circuits during the Commissioning of the LHC

International Nuclear Information System (INIS)

Venturini Delsolaro, W.; Baggiolini, V.; Ballarino, A.; Bellesia, B.; Bordry, F.; Cantone, A.; Casas Lino, M.P.; CastilloTrello, C.; Catalan-Lasheras, N.; Charifoulline, Zinour; Charrondiere, C.; CERN; Madrid, CIEMAT; Fermilab

2008-01-01

The LHC is a complex machine requiring more than 7400 superconducting corrector magnets distributed along a circumference of 26.7 km. These magnets are powered in 1446 different electrical circuits at currents ranging from 60 A up to 600 A. Among the corrector circuits the 600 A corrector magnets form the most diverse and differentiated group. All together, about 60000 high current connections had to be made. A fault in a circuit or one of the superconducting connections would have severe consequences for the accelerator operation. All magnets are wound from various types of Nb-Ti superconducting strands, and many contain parallel protection resistors to by-pass the current still flowing in the other magnets of the same circuit when they quench. In this paper the performance of these magnet circuits is presented, focusing on the quench behavior of the magnets. Quench detection and the performance of the electrical interconnects will be dealt with. The results as measured on the entire circuits are compared to the test results obtained at the reception of the individual magnets

Operator performance in non-destructive testing: A study of operator performance in a performance test

Energy Technology Data Exchange (ETDEWEB)

Enkvist, J.; Edland, A.; Svenson, Ola [Stockholm Univ. (Sweden). Dept. of Psychology

2000-05-15

In the process industries there is a need of inspecting the integrity of critical components without disrupting the process. Such in-service inspections are typically performed with non-destructive testing (NDT). In NDT the task of the operator is to (based on diagnostic information) decide if the component can remain in service or not. The present study looks at the performance in NDT. The aim is to improve performance, in the long run, by exploring the operators' decision strategies and other underlying factors and to this way find out what makes some operators more successful than others. Sixteen operators performed manual ultrasonic inspections of four test pieces with the aim to detect (implanted) cracks. In addition to these performance demonstration tests (PDT), the operators performed independent ability tests and filled out questionnaires. The results show that operators who trust their gut feeling more than the procedure (when the two come to different results) and that at the same time have a positive attitude towards the procedure have a higher PDT performance. These results indicate the need for operators to be motivated and confident when performing NDT. It was also found that the operators who performed better rated more decision criteria higher in the detection phase than the operators who performed worse. For characterizing it was the other way around. Also, the operators who performed better used more time, both detecting and characterizing, than the operators who performed worse.

Operator performance in non-destructive testing: A study of operator performance in a performance test

International Nuclear Information System (INIS)

Enkvist, J.; Edland, A.; Svenson, Ola

2000-05-01

In the process industries there is a need of inspecting the integrity of critical components without disrupting the process. Such in-service inspections are typically performed with non-destructive testing (NDT). In NDT the task of the operator is to (based on diagnostic information) decide if the component can remain in service or not. The present study looks at the performance in NDT. The aim is to improve performance, in the long run, by exploring the operators' decision strategies and other underlying factors and to this way find out what makes some operators more successful than others. Sixteen operators performed manual ultrasonic inspections of four test pieces with the aim to detect (implanted) cracks. In addition to these performance demonstration tests (PDT), the operators performed independent ability tests and filled out questionnaires. The results show that operators who trust their gut feeling more than the procedure (when the two come to different results) and that at the same time have a positive attitude towards the procedure have a higher PDT performance. These results indicate the need for operators to be motivated and confident when performing NDT. It was also found that the operators who performed better rated more decision criteria higher in the detection phase than the operators who performed worse. For characterizing it was the other way around. Also, the operators who performed better used more time, both detecting and characterizing, than the operators who performed worse

Choreographer Pre-Testing Code Analysis and Operational Testing.

Energy Technology Data Exchange (ETDEWEB)

Fritz, David J. [Sandia National Laboratories (SNL-CA), Livermore, CA (United States); Harrison, Christopher B. [Sandia National Laboratories (SNL-CA), Livermore, CA (United States); Perr, C. W. [Sandia National Laboratories (SNL-CA), Livermore, CA (United States); Hurd, Steven A [Sandia National Laboratories (SNL-CA), Livermore, CA (United States)

2014-07-01

Choreographer is a "moving target defense system", designed to protect against attacks aimed at IP addresses without corresponding domain name system (DNS) lookups. It coordinates actions between a DNS server and a Network Address Translation (NAT) device to regularly change which publicly available IP addresses' traffic will be routed to the protected device versus routed to a honeypot. More details about how Choreographer operates can be found in Section 2: Introducing Choreographer. Operational considerations for the successful deployment of Choreographer can be found in Section 3. The Testing & Evaluation (T&E) for Choreographer involved 3 phases: Pre-testing, Code Analysis, and Operational Testing. Pre-testing, described in Section 4, involved installing and configuring an instance of Choreographer and verifying it would operate as expected for a simple use case. Our findings were that it was simple and straightforward to prepare a system for a Choreographer installation as well as configure Choreographer to work in a representative environment. Code Analysis, described in Section 5, consisted of running a static code analyzer (HP Fortify) and conducting dynamic analysis tests using the Valgrind instrumentation framework. Choreographer performed well, such that only a few errors that might possibly be problematic in a given operating situation were identified. Operational Testing, described in Section 6, involved operating Choreographer in a representative environment created through Emulytics^TM . Depending upon the amount of server resources dedicated to Choreographer vis-á-vis the amount of client traffic handled, Choreographer had varying degrees of operational success. In an environment with a poorly resourced Choreographer server and as few as 50-100 clients, Choreographer failed to properly route traffic over half the time. Yet, with a well-resourced server, Choreographer handled over 1000 clients without missrouting. Choreographer

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

Science.gov (United States)

Burns, Bradley M.; Blalock, Norman N.

2010-01-01

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

Analysis of the flow imbalance in the KSTAR PF cryo-circuit

International Nuclear Information System (INIS)

Lee, Hyun-Jung; Park, Dong-Seong; Kwag, Sang-Woo; Joo, Jae-Jun; Moon, Kyung-Mo; Kim, Nam-Won; Lee, Young-Joo; Park, Young-Min; Yang, Hyung-Lyeol

2015-01-01

Highlights: • Investigate of flow imbalance trend for the KSTAR PF superconducting magnet. • Flow imbalance is compared with individual magnet test and integration magnet test. • Intensifying of flow imbalance is proven from the flow monitoring in the KSTAR PF circuit. • Flow behavior is analyzed during magnet charging in the circulator circuit. • Variation of magnet outlet temperature is analyzed due to flow imbalance. - Abstract: The KSTAR PF cryo-circuit is a quasi-closed circulation system in which more than 370 g/s of supercritical helium (SHe) is circulated using a SHe circulator. The heated helium from superconducting magnet is cooled through sub cooler (4.3 K). The circulator is operated at 4.5 K and 6.5 bar, and the pressure drop of the circuit is kept at 2 bar in order to maintain the supercritical state and circulator stability. The circuit is connected with helium refrigerator system, distribution system, and supercritical magnet system. It has a hundred branches to supply supercritical helium to the poloidal field superconducting magnet. The branch was designed to optimize the operation conditions and they are grouped for one cryogenic valve has the same length within the cardinal principle of the optimization. Five cryogenic valves are installed to control the mass flow rate, and seven orifice mass flow meters, differential pressure gauges and temperature sensors were installed in front of the magnet in the distribution because upper magnet and lower magnet is symmetric theoretically. The cryogenic pipe line was manufactured with elevation about 10 m between upper magnet and lower magnet. The inlet and outlet helium feed-through were installed at the coil inside in case of KSTAR PF1–PF5 upper magnet and lower magnet. The flow imbalance is caused by void fraction and it could be changed due to manufacturing process even if it has the same length of cooling channel. This creates an imbalance among cooling channels and temperatures are

Operational amplifiers

CERN Document Server

Dostal, Jiri

1993-01-01

This book provides the reader with the practical knowledge necessary to select and use operational amplifier devices. It presents an extensive treatment of applications and a practically oriented, unified theory of operational circuits.Provides the reader with practical knowledge necessary to select and use operational amplifier devices. Presents an extensive treatment of applications and a practically oriented, unified theory of operational circuits

Low Pressure Circuit Control and adjust System Test

International Nuclear Information System (INIS)

Rubio, R.O; Brendstrup, C.J; Ocampo, A.C

2000-01-01

The hydraulic mechanism (MSAC) is a system that will be employed in the movement of the control rods of the CAREM-25 reactor.In this report, the experimental work on a prototype of MSAC in a low pressure circuit is presented: also the methodology and conclusions.Basic thermalhydraulic data from the MSAC was obtained, and the most relevant control parameters were determined.The response of the mechanism to changes in the control parameters was also evaluated. In conclusion, the response of the MSAC fulfills the aspects of reliability and repetitive movement with water flow pulses control, in the low pressure circuit at the Laboratorio de Mecanica, Materiales y Mediciones of INVAP S.E

In-service diagnostics of main circulating circuit pipes of WWER nuclear power plants

International Nuclear Information System (INIS)

Svoboda, V.; Merta, J.; Merta, V.

1982-01-01

The application is discussed of the acoustic emission method for testing the integrity of the components of the main circulating circuit of the WWER 440 nuclear power plant. A description is given of the main circulating circuit and a stress analysis on the basis of strength computations considering operating modes is presented. An analysis is also presented of the possible damage of the pipe material as related to the application of the acoustic emission method for in-service inspection of the pipes. Certain practical problems of application are discussed. (author)

Operating history report for the Peach Bottom HTGR. Volume I. Reactor operating history

International Nuclear Information System (INIS)

Scheffel, W.J.; Baldwin, N.L.; Tomlin, R.W.

1976-01-01

The operating history for the Peach Bottom-1 Reactor is presented for the years 1966 through 1975. Information concerning general chemistry data, general physics data, location of sensing elements in the primary helium circuit, and postirradiation examination and testing of reactor components is presented

Integrated Circuits for Analog Signal Processing

CERN Document Server

2013-01-01

  This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

Simulation of electronic circuit sensitivity towards humidity using electrochemical data on water layer

DEFF Research Database (Denmark)

Joshy, Salil; Verdingovas, Vadimas; Jellesen, Morten Stendahl

2015-01-01

Climatic conditions like temperature and humidity have direct influence on the operation of electronic circuits. The effects of temperature on the operation of electronic circuits have been widely investigated, while the effect of humidity and solder flux residues are not well understood including...... the effect on circuit and PCBA (printed circuit board assembly) layout design. This paper elucidates a methodology for analyzing the sensitivity of an electronic circuit based on parasitic circuit analysis using data on electrical property of the water layer formed under humid as well as contaminated...

A Practical Circuit-based Model for State of Health Estimation of Li-ion Battery Cells in Electric Vehicles

Energy Technology Data Exchange (ETDEWEB)

Lam, Long

2011-08-23

In this thesis the development of the state of health of Li-ion battery cells under possible real-life operating conditions in electric cars has been characterised. Furthermore, a practical circuit-based model for Li-ion cells has been developed that is capable of modelling the cell voltage behaviour under various operating conditions. The Li-ion cell model can be implemented in simulation programs and be directly connected to a model of the rest of the electronic system in electric vehicles. Most existing battery models are impractical for electric vehicle system designers and require extensive background knowledge of electrochemistry to be implemented. Furthermore, many models do not take the effect of regenerative braking into account and are obtained from testing fully charged cells. However, in real-life applications electric vehicles are not always fully charged and utilise regenerative braking to save energy. To obtain a practical circuit model based on real operating conditions and to model the state of health of electric vehicle cells, numerous 18650 size LiFePO4 cells have been tested under possible operating conditions. Capacity fading was chosen as the state of health parameter, and the capacity fading of different cells was compared with the charge processed instead of cycles. Tests have shown that the capacity fading rate is dependent on temperature, charging C-rate, state of charge and depth of discharge. The obtained circuit model is capable of simulating the voltage behaviour under various temperatures and C-rates with a maximum error of 14mV. However, modelling the effect of different temperatures and C-rates increases the complexity of the model. The model is easily adjustable and the choice is given to the electric vehicle system designer to decide which operating conditions to take into account. By combining the test results for the capacity fading and the proposed circuit model, recommendations to optimise the battery lifetime are proposed.

Synthetic Biology: A Unifying View and Review Using Analog Circuits.

Science.gov (United States)

Teo, Jonathan J Y; Woo, Sung Sik; Sarpeshkar, Rahul

2015-08-01

We review the field of synthetic biology from an analog circuits and analog computation perspective, focusing on circuits that have been built in living cells. This perspective is well suited to pictorially, symbolically, and quantitatively representing the nonlinear, dynamic, and stochastic (noisy) ordinary and partial differential equations that rigorously describe the molecular circuits of synthetic biology. This perspective enables us to construct a canonical analog circuit schematic that helps unify and review the operation of many fundamental circuits that have been built in synthetic biology at the DNA, RNA, protein, and small-molecule levels over nearly two decades. We review 17 circuits in the literature as particular examples of feedforward and feedback analog circuits that arise from special topological cases of the canonical analog circuit schematic. Digital circuit operation of these circuits represents a special case of saturated analog circuit behavior and is automatically incorporated as well. Many issues that have prevented synthetic biology from scaling are naturally represented in analog circuit schematics. Furthermore, the deep similarity between the Boltzmann thermodynamic equations that describe noisy electronic current flow in subthreshold transistors and noisy molecular flux in biochemical reactions has helped map analog circuit motifs in electronics to analog circuit motifs in cells and vice versa via a `cytomorphic' approach. Thus, a body of knowledge in analog electronic circuit design, analysis, simulation, and implementation may also be useful in the robust and efficient design of molecular circuits in synthetic biology, helping it to scale to more complex circuits in the future.

Designing of all optical generalized circuit for two-input binary and multi-valued logical operations

Science.gov (United States)

Bhowmik, Panchatapa; Roy, Jitendra Nath; Chattopadhyay, Tanay

2014-11-01

This paper presents a generalized all optical circuit of two-input logical operation (both binary and multi-valued), using an optical nonlinear material (OPNLM) based switch. The inputs of the logic gates are represented by different polarization states of light. This model is simple, practical and very much useful for future all optical information processing. Proposed scheme can work for different wavelengths and for different materials. The simulation result with the nonlinear material gold nanoparticle embedded in optically transparent matrices alumina (Al2O3) is also presented in the paper.

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

Science.gov (United States)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the

Electronic circuits fundamentals & applications

CERN Document Server

Tooley, Mike

2015-01-01

Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The

Operation amplifier

NARCIS (Netherlands)

Tetsuya, Saito; Nauta, Bram

2008-01-01

To provide an operation amplifier which improves power source voltage removal ratios while assuring phase compensation characteristics, and therefore can be realized with a small-scale circuit and low power consumption. SOLUTION: The operation amplifier comprises: a differential amplifier circuit 1;

Logic-type Schmitt circuit using multi-valued gates

Science.gov (United States)

Wakui, M.; Tanaka, M.

Logic-type Schmitt circuits (LTSCs) proposed in this paper by author's proposal are a new detector for a multi-valued multi-threshold logic circuit, and it realizes the high resolution with a little hysteresis or the high noise margin. The detector consists of the combinations of the multi-valued gates (MVGs) and a positive reaction device (PRD), and each circuit can be realized by the conventional elements. This paper shows their practical circuits, and describes the regions and the conditions for their operation.

Effects of Genetic Variation on the E. coli Host-Circuit Interface

Directory of Open Access Journals (Sweden)

Stefano Cardinale

2013-07-01

Full Text Available Predictable operation of engineered biological circuitry requires the knowledge of host factors that compete or interfere with designed function. Here, we perform a detailed analysis of the interaction between constitutive expression from a test circuit and cell-growth properties in a subset of genetic variants of the bacterium Escherichia coli. Differences in generic cellular parameters such as ribosome availability and growth rate are the main determinants (89% of strain-specific differences of circuit performance in laboratory-adapted strains but are responsible for only 35% of expression variation across 88 mutants of E. coli BW25113. In the latter strains, we identify specific cell functions, such as nitrogen metabolism, that directly modulate circuit behavior. Finally, we expose aspects of carbon metabolism that act in a strain- and sequence-specific manner. This method of dissecting interactions between host factors and heterologous circuits enables the discovery of mechanisms of interference necessary for the development of design principles for predictable cellular engineering.

Sludge stabilization operability test report

International Nuclear Information System (INIS)

Lewis, W.S.

1994-01-01

Document provides the results of the Operability Test Procedure performed to test the operability of the HC-21C thermal stabilization process for sludge. The OTP assured all equipment functioned properly and established the baseline temperature profile for glovebox HC-21C

Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

International Nuclear Information System (INIS)

Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

2010-01-01

A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

A new integrated microwave SQUID circuit design

International Nuclear Information System (INIS)

Erne, S.N.; Finnegan, T.F.

1980-01-01

In this paper we consider the design and operation of a planar thin-film rf-SQUID circuit which can be realized via microwave-integrated-circuit (MIC) techniques and which differs substantially from pervious microwave SQUID configurations involving either mechanical point-contact or cylindrical thin-film micro-bridge geometries. (orig.)

Operating experience and design criteria of sodium valves

International Nuclear Information System (INIS)

Markford, D.

1974-01-01

The information presented refers to sodium valve development for KNK and SNR-300 as well as for sodium test facilities on the INTERATOM site at Bensberg. Well in advance of KNK-I a number of sodium test facilities have been operated containing small and medium size valves of different design and manufacturer. The more stringent requirements for long range safe and reliable operation in KNK-I put forth a development program for the main primary and secondary circuit sodium valves. Operational experience gave rise to modification of the stem seal arrangement mainly, so KNK-II (which is the fast core for KNK reactor) will be run with modified sodium valves. Main pipe diameters in SNR-300 are in the range of 600 mm. Valve designs with rising shafts would require excessive space in the primary circuit cavities, therefore efforts have been directed towards introduction of different type valves. Due to the requirements of after-heat-removal a valve type with control capability had to be chosen. A special design of butterfly valves was selected for the primary and secondary circuits of SNR-300. The development and tests performed with this type of valve are described. In the field of small sodium valves, tests with a 50 mm diameter freeze-seal valve are reported, and the current status of bellows-seal-valves to be inserted into SNR-300 is discussed. (U.S.)

Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients

Directory of Open Access Journals (Sweden)

Michael Auer

2009-02-01

Full Text Available The aim of this work is to develop a simultaneous multi user access system – READ (Remote ASIC Design and Test that allows users to perform test and measurements remotely via clients running on mobile devices as well as on standard PCs. The system also facilitates the remote design of circuits with the PAC-Designer The system is controlled by LabVIEW and was implemented using a Data Acquisition Card from National instruments. Such systems are specially suited for manufacturing process monitoring and control. The performance of the simultaneous access was tested under load with a variable number of users. The server implements a queue that processes user’s commands upon request.

The online sealing performance test of the primary circuit pressure boundary check valve in nuclear power plants

International Nuclear Information System (INIS)

Yang Yunfei; Huang Huimin

2013-01-01

The primary circuit pressure boundary check valves of 320 MW pressurized water reactor is a nuclear grade I key equipment. The sealing demand is very high, which is directly related to the internal leakage rate of the primary circuit system. After the welding check valve is repaired, the sealing performance is judged by color printing checks. If there is water or humid vapor in the pipe, it will affect the accuracy of the color printing checks. For the particularity of the online check valve tightness test, online detecting device is designed by the hydraulic pressure drop method in other nuclear power plants, but the method has some shortcomings and restrictions. In this paper, we design a reliable and portable test equipment by the low-pressure gas seal test flow measurement, which make accurate and quantitative judgment of sealing property after the pressure boundary check valves are repaired. (authors)

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing

Password Based Distribution Panel and Circuit Breaker Operation for the Safety of Lineman during Maintenance Work

OpenAIRE

Hudedmani, Mallikarjun G; Ummannanavar, Nitin; Mudaliar, Mani Dheeraj; Sooji, Chandana; Bogar, Mala

2017-01-01

Security is the prime concern in our day to day life while performing any activity. In the current scenario, accidental death of lineman is often read and evidenced. In this direction, a safety measure to safe guard the operator is found very necessary looking into the present working style. The electric lineman safety system is designed to control the control panel doors and circuit breaker by using a password for the safety. Critical electrical accidents to lineman are on the rise during el...

Discharge quenching circuit for counters

International Nuclear Information System (INIS)

Karasik, A.S.

1982-01-01

A circuit for quenching discharges in gas-discharge detectors with working voltage of 3-5 kV based on transistors operating in the avalanche mode is described. The quenching circuit consists of a coordinating emitter follower, amplifier-shaper for avalanche key cascade control which changes potential on the counter electrodes and a shaper of discharge quenching duration. The emitter follower is assembled according to a widely used flowsheet with two transistors. The circuit permits to obtain a rectangular quenching pulse with front of 100 ns and an amplitude of up to 3.2 kV at duration of 500 μm-8 ms. Application of the quenching circuit described permits to obtain countering characteristics with the slope less than or equal to 0.02%/V and plateau extent greater than or equal to 300 V [ru

Synchronization circuit for shaping picosecond accelerated-electron pulses

International Nuclear Information System (INIS)

Pavlov, Y.S.; Solov'ev, N.G.; Tomnikov, A.P.

1986-01-01

The authors discuss a high-speed circuit for synchronization of trigger pulses of the deflector modulator of an accelerator with a given phase of rf voltage of 200 MHz. The measured time instability between the output trigger pulses of the circuit and the input rf voltage is ≤ + or - 0.05 nsec. The circuit is implemented by ECL integrated circuits of series K100 and K500, and operates in both the pulse (pulse duration 3 μsec and repetition frequency 400 Hz) and continuous modes

Beam dynamics requirements for HL–LHC electrical circuits

CERN Document Server

Gamba, Davide; Cerqueira Bastos, Miguel; Coello De Portugal - Martinez Vazquez, Jaime Maria; De Maria, Riccardo; Giovannozzi, Massimo; Martino, Michele; Tomas Garcia, Rogelio

2017-01-01

A certain number of LHC magnets and relative electrical circuits will be replaced for the HL-LHC upgrade. The performance of the new circuits will need to be compatible with the current installation, and to provide the necessary improvements to meet the tight requirements of the new operational scenario. This document summarises the present knowledge of the performance and use of the LHC circuits and, based on this and on the new optics requirements, provides the necessary specifications for the new HL-LHC electrical circuits.

Tester Detects Steady-Short Or Intermittent-Open Circuits

Science.gov (United States)

Anderson, Bobby L.

1990-01-01

Momentary open circuits or steady short circuits trigger buzzer. Simple, portable, lightweight testing circuit sounds long-duration alarm when it detects steady short circuit or momentary open circuit in coaxial cable or other two-conductor transmission line. Tester sensitive to discontinuities lasting 10 microseconds or longer. Used extensively for detecting intermittent open shorts in accelerometer and extensometer cables. Also used as ordinary buzzer-type continuity checker to detect steady short or open circuits.

Results of water corrosion in static cell tests representing multi-metal assemblies in the hydraulic circuits of Tore Supra

Energy Technology Data Exchange (ETDEWEB)

Lipa, M.; Blanchet, J. [Association Euratom-CEA Cadarache, 13 - Saint-Paul-lez-Durance (France). Dept. de Recherches sur la Fusion Controlee; Cellier, F. [Framatome, Centre Technique, 71 - Saint Marcel (France)

2007-07-01

Full text of publication follows: Tore supra (TS) has used from the beginning of operation in 1989 actively cooled plasma facing components. Since the operation and baking temperature of all in vessel components has been defined to be up to 230 deg. C at 40 bars, a special water chemistry of the cooling water plant was suggested in order to avoid eventual water leaks due to corrosion (general corrosion, galvanic corrosion, stress corrosion, etc.) at relative high temperatures and pressures in tubes, pipes, bellows, water boxes, coils, etc. From the beginning of TS operation, in vessel components (e.g. wall protection panels, limiters, ergodic divertor coils, neutralisers and diagnostics) represented a unique combination of metals in the hydraulic circuit mainly such as stainless steel, Inconel, CuCrZr, Nickel and Copper. These different materials were joined together by welding (St to St, Inconel to Inconel, CuCrZr to CuCrZr and CuCrZr to St-St via a Ni sleeve adapter), brazing (St-St to Cu and Cu-LSTP), friction (CuCrZr and Cu to St-St), explosion (CuCrZr to St-St) and memory metal junction (Cryo-fit to Cu - only test sample). Following experiences obtained with steam generator tubes of nuclear power plants, a cooling water quality of AVT (all volatile treatment) has been defined based on demineralized water with adjustment of the pH value to about 9.0/ 7.0 (25 deg. C/ 200 deg. C) by addiction of ammoniac, and hydrazine in order to absorb oxygen dissolved in water. At that time, a simplified water corrosion test program has been performed using static (no circulation) test cell samples made of above mentioned TS metal combinations. All test cell samples, prepared and filled with AVT water, were performed at 280 deg. C and 65 bars in an autoclave during 3000 hours. The test cell water temperature has been chosen to be sufficient above the TS component working temperature, in order to accelerate an eventual corrosion process. Generally all above mentioned metal

Results of water corrosion in static cell tests representing multi-metal assemblies in the hydraulic circuits of Tore Supra

International Nuclear Information System (INIS)

Lipa, M.; Blanchet, J.

2007-01-01

Full text of publication follows: Tore supra (TS) has used from the beginning of operation in 1989 actively cooled plasma facing components. Since the operation and baking temperature of all in vessel components has been defined to be up to 230 deg. C at 40 bars, a special water chemistry of the cooling water plant was suggested in order to avoid eventual water leaks due to corrosion (general corrosion, galvanic corrosion, stress corrosion, etc.) at relative high temperatures and pressures in tubes, pipes, bellows, water boxes, coils, etc. From the beginning of TS operation, in vessel components (e.g. wall protection panels, limiters, ergodic divertor coils, neutralisers and diagnostics) represented a unique combination of metals in the hydraulic circuit mainly such as stainless steel, Inconel, CuCrZr, Nickel and Copper. These different materials were joined together by welding (St to St, Inconel to Inconel, CuCrZr to CuCrZr and CuCrZr to St-St via a Ni sleeve adapter), brazing (St-St to Cu and Cu-LSTP), friction (CuCrZr and Cu to St-St), explosion (CuCrZr to St-St) and memory metal junction (Cryo-fit to Cu - only test sample). Following experiences obtained with steam generator tubes of nuclear power plants, a cooling water quality of AVT (all volatile treatment) has been defined based on demineralized water with adjustment of the pH value to about 9.0/ 7.0 (25 deg. C/ 200 deg. C) by addiction of ammoniac, and hydrazine in order to absorb oxygen dissolved in water. At that time, a simplified water corrosion test program has been performed using static (no circulation) test cell samples made of above mentioned TS metal combinations. All test cell samples, prepared and filled with AVT water, were performed at 280 deg. C and 65 bars in an autoclave during 3000 hours. The test cell water temperature has been chosen to be sufficient above the TS component working temperature, in order to accelerate an eventual corrosion process. Generally all above mentioned metal

Light Duty Utility Arm system pre-operational (cold test) test plan

International Nuclear Information System (INIS)

Bennett, K.L.

1995-01-01

The Light Duty Utility (LDUA) Cold Test Facility, located in the Hanford 400 Area, will be used to support cold testing (pre- operational tests) of LDUA subsystems. Pre-operational testing is composed of subsystem development testing and rework activities, and integrated system qualification testing. Qualification testing will be conducted once development work is complete and documentation is under configuration control. Operational (hot) testing of the LDUA system will follow the testing covered in this plan and will be covered in a separate test plan

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

Science.gov (United States)

Shin, SeungJun; Yu, YunSeop; Choi, JungBum

2008-10-01

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

Aqueous corrosion in static capsule tests representing multi-metal assemblies in the hydraulic circuit of Tore Supra

Energy Technology Data Exchange (ETDEWEB)

Lipa, M. [Association Euratom-CEA, CEA/DSM/DRFC, Centre de Cadarache, 13108 Saint-Paul-Lez-Durance (France)], E-mail: manfred.lipa@cea.fr; Blanchet, J.; Feron, D. [CEA/DEN/SCCME, Centre de Saclay, 91191 Gif sur Yvette (France); Cellier, F. [AREVA ANP, Centre Technique, 71380 Saint Marcel (France)

2008-12-15

Tore supra (TS) in vessel components represent a unique combination of metals in the hydraulic circuit. Different materials, e.g. stainless steel, copper alloys, nickel, etc., were joined together by fusion welding, brazing and friction. Since the operation and baking temperature of all in vessel components has been defined to be set at 230 deg. C/40 bars a special water chemistry of the cooling water loop was suggested in order to prevent eventual water leaks due to corrosion at relative high temperatures and pressures in tubes, bellows, coils and coolant plant ancillary equipments. Following experiences with water chemistry in Pressurised Water Reactors, an all volatile chemical treatment (AVT) has been defined for the cooling water quality of TS. Since then, a simplified static (no fluid circulation) corrosion test program at relatively high temperature and pressure has been performed using capsule-type samples made of above mentioned multi-metal assemblies.

A circuit design for multi-inputs stateful OR gate

Energy Technology Data Exchange (ETDEWEB)

Chen, Qiao; Wang, Xiaoping, E-mail: wangxiaoping@hust.edu.cn; Wan, Haibo; Yang, Ran; Zheng, Jian

2016-09-07

The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.

A circuit design for multi-inputs stateful OR gate

International Nuclear Information System (INIS)

Chen, Qiao; Wang, Xiaoping; Wan, Haibo; Yang, Ran; Zheng, Jian

2016-01-01

The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.

Resistor Extends Life Of Battery In Clocked CMOS Circuit

Science.gov (United States)

Wells, George H., Jr.

1991-01-01

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Wide operating window spin-torque majority gate towards large-scale integration of logic circuits

Science.gov (United States)

Vaysset, Adrien; Zografos, Odysseas; Manfrini, Mauricio; Mocuta, Dan; Radu, Iuliana P.

2018-05-01

Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven character of domain expansion. Here, we propose an improved STMG concept where the domain wall is driven with current. Thus, input switching and domain wall propagation are decoupled, leading to higher energy efficiency and allowing greater technological optimization. To ensure majority operation, pinning sites are introduced. We observe through micromagnetic simulations that the new structure works for all input combinations, regardless of the initial state. Contrary to the original concept, the working condition is only given by threshold and depinning currents. Moreover, cascading is now possible over long distances and fan-out is demonstrated. Therefore, this improved STMG concept is ready to build complete Boolean circuits in absence of external magnetic fields.

Wiring of electronic evaluation circuits

International Nuclear Information System (INIS)

Bauer, R.; Svoboda, Z.

1977-01-01

The wiring is described of electronic evaluation circuits for the automatic viewing of photographic paper strip negatives on which line tracks with an angular scatter relative to the spectrograph longitudinal axis were recorded during the oblique flight of nuclear particles during exposure in the spectrograph. In coincidence evaluation, the size of the angular scatter eventually requires that evaluation dead time be increased. The equipment consists of minimally two fixed registers and a block of logic circuits whose output is designed such as will allow connection to equipment for recording signals corresponding to the number of tracks on the film. The connection may be implemented using integrated circuits guaranteeing high operating reliability and life. (J.B.)

Hybrid Direct-Current Circuit Breaker

Science.gov (United States)

Wang, Ruxi (Inventor); Premerlani, William James (Inventor); Caiafa, Antonio (Inventor); Pan, Yan (Inventor)

2017-01-01

A circuit breaking system includes a first branch including at least one solid-state snubber; a second branch coupled in parallel to the first branch and including a superconductor and a cryogenic contactor coupled in series; and a controller operatively coupled to the at least one solid-state snubber and the cryogenic contactor and programmed to, when a fault occurs in the load circuit, activate the at least one solid-state snubber for migrating flow of the electrical current from the second branch to the first branch, and, when the fault is cleared in the load circuit, activate the cryogenic contactor for migrating the flow of the electrical current from the first branch to the second branch.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Non-noise instabilities in oscilloscope trigger circuits

International Nuclear Information System (INIS)

Burd, Aleksander

2011-01-01

The paper discusses two phenomena called tremor, which result in incorrect operation of the oscilloscope trigger circuits. Both of them change delays introduced by the trigger circuit, resulting in horizontal shifts of traces on the screen, but the origins of the two phenomena are different. Both kinds of tremors in the oscilloscope trigger circuits produce images on the screen, which often are similar to those resulting from the noise jitter. Hence, limited knowledge of tremor may be a source of improper interpretation of the oscilloscope measurements. On the other hand tremor can be considered as a different approach to the problem of flip-flop circuit's metastability

Development of a pulse shape discrimination circuit

International Nuclear Information System (INIS)

Ye Bangjiao; Fan Wei; Fan Yangmei; Yu Xiaoqi; Mei Wen; Wang Zhongmin; Han Rongdian; Xiao Zhenxi

1994-01-01

A pulse shape discrimination circuit was designed and used in an experiment measuring double-differential cross sections of (n, charged particle) reaction; to identify p, α and γ. The performance of the circuit was tested. With this circuit, excellent identification of p, α and γ was obtained. ((orig.))

Streaming Reduction Circuit

NARCIS (Netherlands)

Gerards, Marco Egbertus Theodorus; Kuper, Jan; Kokkeler, Andre B.J.; Molenkamp, Egbert

2009-01-01

Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths

Contribution to the electrothermal simulation in power electronics. Development of a simulation methodology applied to switching circuits under variable operating conditions; Contribution a la simulation electrothermique en electronique de puissance. Developpement d`une methode de simulation pour circuits de commutation soumis a des commandes variables

Energy Technology Data Exchange (ETDEWEB)

Vales, P.

1997-03-19

In modern hybrid or monolithic integrated power circuits, electrothermal effects can no longer be ignored. A methodology is proposed in order to simulate electrothermal effects in power circuits, with a significant reduction of the computation time while taking into account electrical and thermal time constants which are usually widely different. A supervising program, written in Fortran, uses system call sequences and manages an interactive dialog between a fast thermal simulator and a general electrical simulator. This explicit coupling process between two specific simulators requires a multi-task operating system. The developed software allows for the prediction of the electrothermal power dissipation drift in the active areas of components, and the prediction of thermally-induced coupling effects between adjacent components. An application to the study of hard switching circuits working under variable operating conditions is presented

Feasibility Study of the PS Injection for 2 GeV LIU Beams with an Upgraded KFA-45 Injection Kicker System Operating in Short Circuit Mode

CERN Document Server

Kramer, Thomas; Borburgh, Jan; Ducimetière, Laurent; Feliciano, Luis; Ferrero Colomo, Alvaro; Goddard, Brennan; Sermeus, Luc

2016-01-01

Under the scope of the LIU project the CERN PS Booster to PS beam transfer will be modified to match the requirements for the future 2 GeV beams. This paper describes the evaluation of the proposed upgrade of the PS injection kicker. Different schemes of an injection for LIU beams into the PS have been outlined in the past already under the aspect of individual transfer kicker rise and fall time performances. Homogeneous rise and fall time requirements in the whole PSB to PS transfer chain have been established which allowed to consider an upgrade option of the present injection kicker system operated in short circuit mode. The challenging pulse quality constraints require an improvement of the flat top and post pulse ripples. Both operation modes, terminated and short circuit mode are analysed and analogue circuit simulations for the present and upgraded system are outlined. Recent measurements on the installed kickers are presented and analysed together with the simulation data. First measurements verifying...

Development of integrated thermionic circuits for high-temperature applications

International Nuclear Information System (INIS)

McCormick, J.B.; Wilde, D.; Depp, S.; Hamilton, D.J.; Kerwin, W.; Derouin, C.; Roybal, L.; Dooley, R.

1981-01-01

A class of devices known as integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 0 C is described. The evolution of the ITC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500 0 C environments for extended periods of time

Superhigh-frequency circuit for the EPR spectrometer with rectifier screening

International Nuclear Information System (INIS)

Zhizhchenko, G.A.; Tsvirko, L.V.

1983-01-01

The hamodyne SHF circuit of a 3-cm EPR spectrometer with a reflecting resonator is described. The optimum operating mode of SHF-rectifier at a constant phase difference is automatically assured in the circuit. The circuit employs a reflecting p-i-n- attenuator and a SHF-rectifier sereen which simplify the spectrometer tuming. The circuit is used in a miniature EPR radiospectrometer Minsk EPR-6-type

An optoelectronic integrated device including a laser and its driving circuit

Energy Technology Data Exchange (ETDEWEB)

Matsueda, H.; Nakano, H.; Tanaka, T.P.

1984-10-01

A monolithic optoelectronic integrated circuit (OEIC) including a laser diode, photomonitor and driving and detecting circuits has been fabricated on a semi-insulating GaAs substrate. The OEIC has a horizontal integrating structure which is suitable for realising high-density multifunctional devices. The fabricating process and the static and dynamic characteristics of the optical and electronic elements are described. The preliminary results of the co-operative operation of the laser and its driving circuit are also presented.

Single-server blind quantum computation with quantum circuit model

Science.gov (United States)

Zhang, Xiaoqian; Weng, Jian; Li, Xiaochun; Luo, Weiqi; Tan, Xiaoqing; Song, Tingting

2018-06-01

Blind quantum computation (BQC) enables the client, who has few quantum technologies, to delegate her quantum computation to a server, who has strong quantum computabilities and learns nothing about the client's quantum inputs, outputs and algorithms. In this article, we propose a single-server BQC protocol with quantum circuit model by replacing any quantum gate with the combination of rotation operators. The trap quantum circuits are introduced, together with the combination of rotation operators, such that the server is unknown about quantum algorithms. The client only needs to perform operations X and Z, while the server honestly performs rotation operators.

Endogenous money, circuits and financialization

OpenAIRE

Malcolm Sawyer

2013-01-01

This paper locates the endogenous money approach in a circuitist framework. It argues for the significance of the credit creation process for the evolution of the economy and the absence of any notion of ‘neutrality of money’. Clearing banks are distinguished from other financial institutions as the providers of initial finance in a circuit whereas other financial institutions operate in a final finance circuit. Financialization is here viewed in terms of the growth of financial assets an...

Development of data acquisition system for test circuit for the Thermo-Hydraulic Laboratory of CDTN

International Nuclear Information System (INIS)

Corrade, Thales Jose Rodrigues; Mesquita, Amir Zacarias; Santos, Andre Augusto Campagnole dos

2013-01-01

The Circuit Water-Air (CWA), present in the Laboratorio de Termo-Hidraulica of the Centro de Desenvolvimento da Tecnologia Nuclear/Comissao Nacional de Energia Nuclear (CDTN / CNEN), has been used to evaluate devices present in nuclear fuel elements of a PWR (Pressurized Water Reactor). Currently, a segment of 5x5 beam simulators grids with spacer bars is being tested, serving one of the activities under the Project FUJB / FINEP / INB - 'Development of New Generation of Nuclear Fuel Element '. For the measurements of pressure drop along this beam, a system of data acquisition based on Basic language was created. Although this system is efficient and robust, their resources are very limited. Therefore, it was decided to use the software LabVIEW® implementing a more versatile and modern system. This article describes the new data acquisition system, and presents some results. The main parameters are monitored: temperature, density, dynamic viscosity, Reynolds number. The values of standard deviation, mean and uncertainty of an arbitrary channel are calculated. The system was installed and tested in the circuit under experimental conditions and showed satisfactory results.

The Limitations to Delay-Insensitivity in Asynchronous Circuits

National Research Council Canada - National Science Library

Martin, Alain J

1990-01-01

... produced are delay-insensitive (DI). A digital circuit is DI when its correct operation is independent of the delays in operators and in the wires connecting the operators, except that the delays are finite and positive...

The Maplin electronic circuits handbook

CERN Document Server

Tooley, Michael

1990-01-01

The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

Communication and Sensing Circuits on Cellulose

Directory of Open Access Journals (Sweden)

Federico Alimenti

2015-06-01

Full Text Available This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT era.

WRAP TRUPACT loading systems operational test report

International Nuclear Information System (INIS)

DOSRAMOS, E.V.

1999-01-01

This Operational Test Report documents the operational testing of the TRUPACT process equipment HNF-3918, Revision 0, TRUPACT Operational Test Procedure. The test accomplished the following: Procedure validation; Facility equipment interface; Facility personnel support; and Subcontractor personnel support interface. Field changes are documented as test exceptions with resolutions. All resolutions are completed or a formal method is identified to track the resolution through to completion

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

Science.gov (United States)

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Breathing circuit compliance and accuracy of displayed tidal volume during pressure-controlled ventilation of infants: A quality improvement project.

Science.gov (United States)

Glenski, Todd A; Diehl, Carrie; Clopton, Rachel G; Friesen, Robert H

2017-09-01

% greater in the infant test lung (mean±SD TV 15±5 vs 9±4 mL; mean [95% CI] difference=6.3 [5.6, 7.1] mL, Ptidal volume was 41% greater than actual tidal volume (difference of 10.4 [8.6, 12.2] mL) when the circuit was expanded after the preuse self-test (preintervention) and 7% greater (difference of 2.5 [0.7, 4.2] mL) in subjects when the circuit was expanded prior to the preuse self-test (postintervention) (Ptidal volume in infants less than 10 kg during pressure-controlled ventilation. Overestimation of reported tidal volume can be avoided by expanding the breathing circuit tubing to the length which will be used during a case prior to performing the anesthesia machine preuse self-test. After department-wide education and implementation, performing a correct preuse self-test is now the standard practice in our cardiac operating rooms. © 2017 John Wiley & Sons Ltd.

Method for Evaluating the Corrosion Resistance of Aluminum Metallization of Integrated Circuits under Multifactorial Influence

Science.gov (United States)

Kolomiets, V. I.

2018-03-01

The influence of complex influence of climatic factors (temperature, humidity) and electric mode (supply voltage) on the corrosion resistance of metallization of integrated circuits has been considered. The regression dependence of the average time of trouble-free operation t on the mentioned factors has been established in the form of a modified Arrhenius equation that is adequate in a wide range of factor values and is suitable for selecting accelerated test modes. A technique for evaluating the corrosion resistance of aluminum metallization of depressurized CMOS integrated circuits has been proposed.

Dimensioning of optimal probe circuits for the non-destructive testing of materials by eddy-current using Buschbeck-Meinke chart

International Nuclear Information System (INIS)

Ott, A.

1982-01-01

By application of a modified form of the Buschbeck-Meinke-diagram, known from conduction theory, easy-to use dimensioning rules can be given for the probe circuits of single-frequency eddy-current test instruments. Dimensioning is found for circuits that work with amplitude or phase measurements, that suppress optimal the disturbance parameters in certain regions. In a similar way one can determine dimensioning, with which the measurement quantity causes the highest possible signal charge. (orig.) [de

F-Paris: integrated electronic circuits [Tender

CERN Multimedia

2003-01-01

"Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

Operation of the nuclear fuel cycle test facilities -Operation of the hot test loop facilities

International Nuclear Information System (INIS)

Chun, S. Y.; Jeong, M. K.; Park, C. K.; Yang, S. K.; Won, S. Y.; Song, C. H.; Jeon, H. K.; Jeong, H. J.; Cho, S.; Min, K. H.; Jeong, J. H.

1997-01-01

A performance and reliability of a advanced nuclear fuel and reactor newly designed should be verified by performing the thermal hydraulics tests. In thermal hydraulics research team, the thermal hydraulics tests associated with the development of an advanced nuclear fuel and reactor haven been carried out with the test facilities, such as the Hot Test Loop operated under high temperature and pressure conditions, Cold Test Loop, RCS Loop and B and C Loop. The objective of this project is to obtain the available experimental data and to develop the advanced measuring techniques through taking full advantage of the facilities. The facilities operated by the thermal hydraulics research team have been maintained and repaired in order to carry out the thermal hydraulics tests necessary for providing the available data. The performance tests for the double grid type bottom end piece which was improved on the debris filtering effectivity were performed using the PWR-Hot Test Loop. The CANDU-Hot Test Loop was operated to carry out the pressure drop tests and strength tests of CANFLEX fuel. The Cold Test Loop was used to obtain the local velocity data in subchannel within HANARO fuel bundle and to study a thermal mixing characteristic of PWR fuel bundle. RCS thermal hydraulic loop was constructed and the experiments have been carried out to measure the critical heat flux. In B and C Loop, the performance tests for each component were carried out. (author). 19 tabs., 78 figs., 19 refs

Operation of the nuclear fuel cycle test facilities -Operation of the hot test loop facilities

Energy Technology Data Exchange (ETDEWEB)

Chun, S. Y.; Jeong, M. K.; Park, C. K.; Yang, S. K.; Won, S. Y.; Song, C. H.; Jeon, H. K.; Jeong, H. J.; Cho, S.; Min, K. H.; Jeong, J. H.

1997-01-01

A performance and reliability of a advanced nuclear fuel and reactor newly designed should be verified by performing the thermal hydraulics tests. In thermal hydraulics research team, the thermal hydraulics tests associated with the development of an advanced nuclear fuel and reactor haven been carried out with the test facilities, such as the Hot Test Loop operated under high temperature and pressure conditions, Cold Test Loop, RCS Loop and B and C Loop. The objective of this project is to obtain the available experimental data and to develop the advanced measuring techniques through taking full advantage of the facilities. The facilities operated by the thermal hydraulics research team have been maintained and repaired in order to carry out the thermal hydraulics tests necessary for providing the available data. The performance tests for the double grid type bottom end piece which was improved on the debris filtering effectivity were performed using the PWR-Hot Test Loop. The CANDU-Hot Test Loop was operated to carry out the pressure drop tests and strength tests of CANFLEX fuel. The Cold Test Loop was used to obtain the local velocity data in subchannel within HANARO fuel bundle and to study a thermal mixing characteristic of PWR fuel bundle. RCS thermal hydraulic loop was constructed and the experiments have been carried out to measure the critical heat flux. In B and C Loop, the performance tests for each component were carried out. (author). 19 tabs., 78 figs., 19 refs.

Simplified design of filter circuits

CERN Document Server

Lenk, John

1999-01-01

Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets

Testing installation for a steam generator

International Nuclear Information System (INIS)

Dubourg, M.

1985-01-01

The invention proposes a testing installation for a steam generator associated to a boiler, comprising a testing exchanger connected to a feeding circuit in secondary fluid and to a circuit to release the steam produced, and comprising a heating-tube bundle connected to a closed circuit of circulation of a primary coolant at the same temperature and at the pressure than the primary fluid. The heating-tube bundle of the testing exchanger has the same height than the primary bundle of the steam generator and the testing exchanger is at the same level and near the steam generator and is fed by the same secondary fluid such as it is subject to the same operation phases during a long period. The in - vention applies, more particularly, to the steam generators of pressurized water nuclear power plants [fr

Feeding and purge systems of coolant primary circuit and coolant secondary circuit control of the I sup(123) target

International Nuclear Information System (INIS)

Almeida, G.L. de.

1986-01-01

The Radiation Protection Service of IEN (Brazilian-CNEN) detected three faults in sup(123)I target cooling system during operation process for producing sup(123)I: a) non hermetic vessel containing contaminated water from primary coolant circuit; possibility of increasing radioactivity in the vessel due to accumulation of contaminators in cooling water and; situation in region used for personnels to arrange and adjust equipments in nuclear physics area, to carried out maintenance of cyclotron and target coupling in irradiation room. The primary circuit was changed by secondary circuit for target coolant circulating through coil of tank, which receive weater from secondary circuit. This solution solved the three problems simultaneously. (M.C.K.)

Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods

Directory of Open Access Journals (Sweden)

Hai Au Huynh

2015-01-01

Full Text Available Direct power injection (DPI and bulk current injection (BCI methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC. The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.

W-087 Operational test report. Revision 1

Energy Technology Data Exchange (ETDEWEB)

Joshi, A.W.

1997-06-10

This Acceptance Test Procedure/Operational Test Procedure (ATP/OTP) has been prepared to demonstrate that the Electrical/Instrumentation and Mechanical systems function as required by project criteria and to verify proper operation of the integrated system including the interlocks. The equipment to be tested includes the following: a. Leak detection system operation and controls. b. Electrical interlocks.- C. Transfer pump oper ation. d. Vacuum breaker system interlocks.

Measurements of the Effects of Smoke on Active Circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1999-01-01

Smoke has long been recognized as the most common source of fire damage to electrical equipment; however, most failures have been analyzed after the fire was out and the smoke vented. The effects caused while the smoke is still in the air have not been explored. Such effects have implications for new digital equipment being installed in nuclear reactors. The U.S. Nuclear Regulatory Commission is sponsoring work to determine the impact of smoke on digital instrumentation and control. As part of this program, Sandia National Laboratories has tested simple active circuits to determine how smoke affects them. These tests included the study of three possible failure modes on a functional board: (1) circuit bridging, (2) corrosion (metal loss), and (3) induction of stray capacitance. The performance of nine different circuits was measured continuously on bare and conformably coated boards during smoke exposures lasting 1 hour each and continued for 24 hours after the exposure started. The circuit that was most affected by smoke (100% change in measured values) was the one most sensitive to circuit bridging. Its high impedance (50 MOmega) was shorted during the exposure, but in some cases recovered after the smoke was vented. The other two failure modes, corrosion and induced stray capacitance, caused little change in the function of the circuits. The smoke permanently increased resistance of the circuit tested for corrosion, implying that the cent acts were corroded. However, the change was very small (< 2%). The stray-capacitance test circuit showed very little change after a smoke exposure in either the short or long term. The results of the tests suggest that conformal coatings and type of circuit are major considerations when designing digital circuitry to be used in critical control systems

Measurements of the effects of smoke on active circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1998-01-01

Smoke has long been recognized as the most common source of fire damage to electrical equipment; however, most failures have been analyzed after the fire was out and the smoke vented. The effects caused while the smoke is still in the air have not been explored. Such effects have implications for new digital equipment being installed in nuclear reactors. The US Nuclear Regulatory Commission is sponsoring work to determine the impact of smoke on digital instrumentation and control. As part of this program, Sandia National Laboratories has tested simple active circuits to determine how smoke affects them. These tests included the study of three possible failure modes on a functional board: (1) circuit bridging, (2) corrosion (metal loss), and (3) induction of stray capacitance. The performance of nine different circuits was measured continuously on bare and conformally coated boards during smoke exposures lasting 1 hour each and continued for 24 hours after the exposure started. The circuit that was most affected by smoke (100% change in measured values) was the one most sensitive to circuit bridging. Its high impedance (50 Mohm) was shorted during the exposure, but in some cases recovered after the smoke was vented. The other two failure modes, corrosion and induced stray capacitance, caused little change in the function of the circuits. The smoke permanently increased resistance of the circuit tested for corrosion, implying that the contacts were corroded. However, the change was very small (< 2%). The stray capacitance test circuit showed very little change after a smoke exposure in either the short or long term. The results of the tests suggest that conformal coatings and type of circuit are major considerations when designing digital circuitry to be used in critical control systems

Secondary Circuit Start Up Chemistry Optimisation

International Nuclear Information System (INIS)

Fontan, Guillaume; Morel, Pascal

2012-09-01

In a context of investment and renewal of equipment, Electricite De France (EDF) put enhanced efforts on operating practices during start-up of the secondary circuit, in order to improve operational performance and materials lifetime. This article focuses on the objective of optimizing the filling, the chemical conditioning and the thermal conditioning of the secondary fluid, while taking into account the following issues: - Limiting the time required to obtain a proper chemistry, - Limiting the amount of water and steam used, - Limiting the amount of effluent generated. The scope is all start-up conditions of secondary circuit, both after refuelling outage or fortuitous shutdowns of the plant. The recommendations produced are based on existing local procedures and good practices, which were collected and developed in order to propose a generic methodology understandable and useful both for operators, chemists and managers. (authors)

Design of chaotic analog noise generators with logistic map and MOS QT circuits

International Nuclear Information System (INIS)

Vazquez-Medina, R.; Diaz-Mendez, A.; Rio-Correa, J.L. del; Lopez-Hernandez, J.

2009-01-01

In this paper a method to design chaotic analog noise generators using MOS transistors is presented. Two aspects are considered, the determination of operation regime of the MOS circuit and the statistical distribution of its output signal. The operation regime is related with the transconductance linear (TL: translinear) principle. For MOS transistors this principle was originally formulated in weak inversion regime; but, strong inversion regimen is used because in 1991, Seevinck and Wiegerink made the generalization for this principle. The statistical distribution of the output signal on the circuit, which should be a uniform distribution, is related with the parameter value that rules the transfer function of the circuit, the initial condition (seed) in the circuit and its operation as chaotic generator. To show these concepts, the MOS Quadratic Translinear circuit proposed by Wiegerink in 1993 was selected and it is related with the logistic map and its properties. This circuit will operate as noise generator if it works in strong inversion regime using current-mode approach when the parameter that rules the transfer function is higher than the onset chaos value (3.5699456...) for the logistic map.

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built

Radioactivity of long-lived nuclides in the primary circuit of the reactor BOR-60 during operation with defective fuel elements

International Nuclear Information System (INIS)

Gryazev, V.M.; Kizin, V.D.; Lisitsyn, E.S.; Polyakov, V.I.; Chechetkin, Y.V.

1978-06-01

The summarized results of measurements of the enrichment and distribution of radioactive nuclides from corrosion and of fission products during the four years of operation of BOR-60, including a longer period of operation with detective fuel elements in the core, are presented. It is shown that for operation with approximately 1% leaking fuel rods radiation exposure becomes worse manily because of release and enrichment of cesium isotopes in the coolant. Of the other fission products, the largest contribution to the dose rate in pipework and components is given by 140 Ba / 140 La and 95 Nb. On operation with 0.1 to 0.2% of leaking fuel rods, this contribution is comparable to that of the corrosion products 60 Co and 54 Mn. The radioactivity of corrosion products in the circuit has not increased within the last three years and was about one order of magnitude lower than the theoretical values. The corrosion and fission products are nonuniformly distributed over the circuit. Concentration of 95 Nb and 60 Co in the pipe for 'cold' sodium is larger by a factor of 2 - 5 and of 140 Ba and 54 Mn by a factor of 10-20 than in the pipes for 'hot' sodium. Most of the cobalt was found to deposit in the heat exchanges. The effectiveness of emptying the pipes from coolant in order to reduce the dose sate is assessed. (orig.) [de

Gas chromatographic measurement in water-steam circuits

International Nuclear Information System (INIS)

Zschetke, J.; Nieder, R.

1984-01-01

A gas chromatographic technique for measurements in water-steam circuits, which has been well known for many years, has been improved by design modifications. A new type of equipment developed for special measuring tasks on nuclear engineering plant also has a general application. To date measurements have been carried out on the ''Otto Hahn'' nuclear powered ship, on the KNK and AVR experimental nuclear power plants at Karlsruhe and Juelich respectively and on experimental boiler circuits. The measurements at the power plants were carried out under different operating conditions. In addition measurements during the alkali operating mode and during combined cycle operation were carried out on the AVR reactor. It has been possible to draw new conclusion from the many measurements undertaken. (orig.) [de

Microwave integrated circuits for space applications

Science.gov (United States)

Leonard, Regis F.; Romanofsky, Robert R.

1991-01-01

Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

30 CFR 56.6402 - Deenergized circuits near detonators.

Science.gov (United States)

2010-07-01

... Electric Blasting § 56.6402 Deenergized circuits near detonators. Electrical distribution circuits within 50 feet of electric detonators at the blast site shall be deenergized. Such circuits need not be deenergized between 25 to 50 feet of the electric detonators if stray current tests, conducted as frequently...

30 CFR 57.6402 - Deenergized circuits near detonators.

Science.gov (United States)

2010-07-01

... Electric Blasting-Surface and Underground § 57.6402 Deenergized circuits near detonators. Electrical distribution circuits within 50 feet of electric detonators at the blast site shall be deenergized. Such circuits need not be deenergized between 25 to 50 feet of the electric detonators if stray current tests...

Modelling nonstationary thermohydrodynamic processes in heat-exchange circuits with a two-phase coolant

International Nuclear Information System (INIS)

Blinkov, V.N.

1993-01-01

This paper presents a mathematical model and a open-quotes fastclose quotes computer program for analyzing nonstationary thermohydrodynamic processes in distributed multi-element circuits containing a two-phase coolant. The author's approach is based on representing the distributed multi-element circuits with the two-phase coolant (such as cooling circuits of the reactor of an atomic power station) in the form of equivalent thermohydrodynamic chains composed of idealized elements with the intrinsic properties of the structure elements of real systems. The author has developed the nomenclature of such conceptual elements for objects which can be modelled; the nomenclature encompasses the control volumes (with a single-phase or two-phase coolant or a moving boundary of boiling/condensation) and the branch lines (type of tube and connections in dependence on the inertia of the coolant being taken into account) for a hydrodynamic submodel and the thermal components and lines for a thermal submodel. The mathematical models which have been developed and the program using them are designated for various forms of calculating slow thermohydrodynamic processes in multi-element coolant circuits in reactors and modeling test stands. The program facilitates calculation of the range of stable operation, detailed studies of stationary and nonstationary modes of operation, and forecasts of effective engineering measures to obtain stability with the aid of microcomputers

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array.

Science.gov (United States)

Wu, Jian-Feng; Wang, Feng; Wang, Qi; Li, Jian-Qing; Song, Ai-Guo

2016-12-06

With one operational amplifier (op-amp) in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D) resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements' bypass currents, which were injected into array's non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT) with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC) was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT's measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately.

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Directory of Open Access Journals (Sweden)

Ramesh Vaddi

2009-01-01

Full Text Available In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

Science.gov (United States)

Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

2017-05-01

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Joule-Thief Circuit Performance for Electricity Energy Saving of Emergency Lamps

Science.gov (United States)

Nuryanto Budisusila, Eka; Arifin, Bustanul

2017-04-01

The alternative energy such as battery as power source is required as energy source failures. The other need is outdoor lighting. The electrical power source is expected to be a power saving, optimum and has long life operating. The Joule-Thief circuit is one of solution method for energy saving by using raised electromagnetic force on cored coil when there is back-current. This circuit has a transistor operated as a switch to cut voltage and current flowing along the coils. The present of current causing magnetic induction and generates energy. Experimental prototype was designed by using battery 1.5V to activate Light Emitting Diode or LED as load. The LED was connected in parallel or serial circuit configuration. The result show that the joule-thief circuit able to supply LED circuits up to 40 LEDs.

Automatic ranging circuit for a digital panel meter

International Nuclear Information System (INIS)

Mueller, T.R.; Ross, H.H.

1976-01-01

This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to ensure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit. The system was designed for readout of a fluorescence analyzer for uranium analysis

Application of a path sensitizing method on automated generation of test specifications for control software

International Nuclear Information System (INIS)

Morimoto, Yuuichi; Fukuda, Mitsuko

1995-01-01

An automated generation method for test specifications has been developed for sequential control software in plant control equipment. Sequential control software can be represented as sequential circuits. The control software implemented in a control equipment is designed from these circuit diagrams. In logic tests of VLSI's, path sensitizing methods are widely used to generate test specifications. But the method generates test specifications at a single time only, and can not be directly applied to sequential control software. The basic idea of the proposed method is as follows. Specifications of each logic operator in the diagrams are defined in the software design process. Therefore, test specifications of each operator in the control software can be determined from these specifications, and validity of software can be judged by inspecting all of the operators in the logic circuit diagrams. Candidates for sensitized paths, on which test data for each operator propagates, can be generated by the path sensitizing method. To confirm feasibility of the method, it was experimentally applied to control software in digital control equipment. The program could generate test specifications exactly, and feasibility of the method was confirmed. (orig.) (3 refs., 7 figs.)

Biofouling evaluation in the seawater cooling circuit of an operating coastal power plant

Energy Technology Data Exchange (ETDEWEB)

Murthy, P.S.; Veeramani, P.; Ershath, M.I.M.; Venugopalan, V.P. [BARC Facilities, Water and Steam Chemistry Div., Kalpakkam, Tamil Nadu (India)

2010-07-01

Chlorination is the most commonly used method of biofouling control in cooling water systems of coastal power stations. In the present study, we report results of extensive sampling in different sections of the cooling water system of an operating power station undertaken during three consecutive maintenance shutdowns. The power plant employed continuous low level chlorination (0.2 ± 0.1 mg L{sup -1} TRO) with twice-a-week booster dosing (0.4 ± 0.1 mg L-1 TRO for 8 hours). In addition, the process seawater heat exchangers received supplementary dosing of bromide treatment (0.2 ± 0.1 mg L{sup -1} TRO for 1 hour in every 8 h shift). Biofouling samples were collected from the cooling water conduits, heat exchanger water boxes, pipelines, heated discharge conduits and outfall section during the annual maintenance shutdown of the plant in the years 2007, 2008 and 2009. Simultaneous monitoring of biofouling on test coupons in coastal waters enabled direct comparison of fouling situation on test panels and that in the cooling system. The data showed significant reduction in biofouling inside the cooling circuit as compared to the coastal waters. However, significant amount of fouling was still evident at several places, indicating inadequacy of the biocide treatment regime. The maximum load of 31.3 kg m{sup 2} y{sup -1} was observed in the conduits leading to the process seawater heat exchangers (PSW-HX) and the minimum of 1.3 kg m{sup 2} y{sup -1} was observed in the outfall section. Fouling loads of 12.2 - 14.7 kg m{sup 2} y{sup -1} were observed in the concrete conduits feeding the main condensers. Bromide treatment ahead of the PSW-HX could marginally reduce the fouling load in the downstream section of the dosing point; the HX inlets still showed good biofouling. Species diversity across the cooling water system showed the pre-condenser section to be dominated by green mussels (Perna viridis), pearl oysters (Pinctada sp.) and edible oysters (Crassostrea sp

Biofouling evaluation in the seawater cooling circuit of an operating coastal power plant

International Nuclear Information System (INIS)

Murthy, P.S.; Veeramani, P.; Ershath, M.I.M.; Venugopalan, V.P.

2010-01-01

Chlorination is the most commonly used method of biofouling control in cooling water systems of coastal power stations. In the present study, we report results of extensive sampling in different sections of the cooling water system of an operating power station undertaken during three consecutive maintenance shutdowns. The power plant employed continuous low level chlorination (0.2 ± 0.1 mg L -1 TRO) with twice-a-week booster dosing (0.4 ± 0.1 mg L-1 TRO for 8 hours). In addition, the process seawater heat exchangers received supplementary dosing of bromide treatment (0.2 ± 0.1 mg L -1 TRO for 1 hour in every 8 h shift). Biofouling samples were collected from the cooling water conduits, heat exchanger water boxes, pipelines, heated discharge conduits and outfall section during the annual maintenance shutdown of the plant in the years 2007, 2008 and 2009. Simultaneous monitoring of biofouling on test coupons in coastal waters enabled direct comparison of fouling situation on test panels and that in the cooling system. The data showed significant reduction in biofouling inside the cooling circuit as compared to the coastal waters. However, significant amount of fouling was still evident at several places, indicating inadequacy of the biocide treatment regime. The maximum load of 31.3 kg m 2 y -1 was observed in the conduits leading to the process seawater heat exchangers (PSW-HX) and the minimum of 1.3 kg m 2 y -1 was observed in the outfall section. Fouling loads of 12.2 - 14.7 kg m 2 y -1 were observed in the concrete conduits feeding the main condensers. Bromide treatment ahead of the PSW-HX could marginally reduce the fouling load in the downstream section of the dosing point; the HX inlets still showed good biofouling. Species diversity across the cooling water system showed the pre-condenser section to be dominated by green mussels (Perna viridis), pearl oysters (Pinctada sp.) and edible oysters (Crassostrea sp.), whereas the post-condenser section and heat

Results of experimental research of the modes of short circuit in a traction network

Directory of Open Access Journals (Sweden)

P.Ye. Mykhalichenko

2012-08-01

Full Text Available In the article the results, namely oscillograms of the transitional feeder electric values obtained by the experimental tests of the short circuit modes in case of setting off different types of substation fast-acting switches are presented. The experiments were conducted on the operating electrified track sections of the Prydniprovs’ka Railway.

Low cost design of microprocessor EDAC circuit

International Nuclear Information System (INIS)

Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

2015-01-01

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

Design and testing of a low impedance transceiver circuit for nitrogen-14 nuclear quadrupole resonance.

Science.gov (United States)

Sato-Akaba, Hideo

2014-01-01

A low impedance transceiver circuit consisting of a transmit-receive switch circuit, a class-D amplifier and a transimpedance amplifier (TIA) was newly designed and tested for a nitrogen-14 NQR. An NQR signal at 1.37MHz from imidazole was successfully observed with the dead time of ~85µs under the high Q transmission (Q~120) and reception (Q~140). The noise performance of the low impedance TIA with an NQR probe was comparable with a commercial low noise 50Ω amplifier (voltage input noise: 0.25 nV/Hz) which was also connected to the probe. The protection voltage for the pre-amplifier using the low impedance transceiver was ~10 times smaller than that for the pre-amplifier using a 50Ω conventional transceiver, which is suitable for NQR remote sensing applications. Copyright © 2014 Elsevier Inc. All rights reserved.

Commutation circuit for an HVDC circuit breaker

Science.gov (United States)

Premerlani, William J.

1981-01-01

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

Short-circuit experiments on a high Tc-superconducting cable conductor

DEFF Research Database (Denmark)

Tønnesen, Ole; Jensen, E.H.; Traholt, C.

2002-01-01

A high temperature superconductor (HTS) cable conductor (CC) with a critical current of 2.1 kA was tested over a range of short-circuit currents up to 20 kA. The duration of the short-circuit currents is 1 s. Between each short-circuit test the critical current of the HTS CC was measured in order...

Progress in radiation immune thermionic integrated circuits

International Nuclear Information System (INIS)

Lynn, D.K.; McCormick, J.B.

1985-08-01

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs

Progress in radiation immune thermionic integrated circuits

Energy Technology Data Exchange (ETDEWEB)

Lynn, D.K.; McCormick, J.B. (comps.)

1985-08-01

This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

Directory of Open Access Journals (Sweden)

Zong Yao

2016-06-01

Full Text Available This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts, the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

Electrochemical ion exchanger in the water circuit to measure cation conductivity

International Nuclear Information System (INIS)

Bengtsson, B.; Ingemarsson, R.; Settervik, G.; Velin, A.

2010-01-01

In Ringhals NPP, more than four years of successful operation with a full-scale EDI for the recycling of steam generator blow down (SGBD) gave the inspiration to modify and 'scale down' this EDI process. This with purpose to explore the possibilities to replace the cation exchanger columns used for cation conductivity analysis, with some small and integrated electrochemical ion-exchange cells. Monitoring the cation conductivity requires the use of a small cation resin column upstream of the conductivity probe and is one of the most important analyses at power plants. However, when operating with high alkaline treatment in the steam circuit, it's connected to the disadvantage of getting the resins rapidly exhausted, with needs to be frequently replaced or regenerated. This is causing interruptions in the monitoring and giving rise to high workload for the maintenance. This paper reports about some optimization and tests of two different two-compartment electrochemical cells for the possible replacements of cation resin columns when analyzing cation conductivity in the secondary steam circuit at Ringhals NPPs. Field tests during start up condition and more than four months of steady operation together with real and simulated test for impurity influences, indicates that a ELectrical Ion Echange process (ELIX) could be successfully used to replace the resin columns in Ringhals during operating with high pH-AVT (All Volatile Treatment), using hydrazine and ammonia. Installation of an ELIX-system downstream a particle filter and upstream of a small cation resin column, will introduce additional safety and further reduce the maintenance with possible interruptions. Performance of the ELIX-process together with other chemical additives (Morpholine, ETA, MPA, DMA) and dispersants, may be further evaluated to qualify the ELIX-process as well as SGBD-EDI for wider use in nuclear applications. (author)

Equivalent circuit modeling of a superconducting synchronous generator with double electromagnetic shields. Part II. Equivalent circuit model and estimation of its constants for design examples

International Nuclear Information System (INIS)

Muta, I.; Magarikaji, N.

1980-01-01

Operational impedances of synchronous machine are very important in the study of dynamic and transient stability. In recent years, it has become possible to analyze the transient behavior of operational impedance by the direct Fourier transformation of frequency response characteristics of operational impedance. It is desired very much to derive the equivalent circuit based on exact operational impedances. In this paper, we calculate the frequency characteristics of operational impedances which are derived in a companion paper. Also, we analyze the effects of various parameters on the equivalent circuit constants. Approximate expressions for sub-subtransient, subtransient and transient reactances are derived from the theoretical expressions for operational impedances. The validity of theoretical calculations is confirmed by comparison with experimental results

Increase of energy efficiency in proportional adjusting of flow rate in the boiler circuit

OpenAIRE

Artamonov Pavel A.; Kurilenko Nikolai I.; Mamontov Gennady Ya.

2017-01-01

The article presents the results of theoretical studies in the field of the boiler circuit operating modes for the boiler rooms operating by the independent heat supply scheme. The 3D model of a boiler circuit for a boiler room with 3 MW rated output was developed, based on which there was made an estimation of the boiler pump performance indicators. There is proposed a method for reducing energy costs for the operation of the pumping equipment of the boiler circuit.

Participation in testing and start up operations

International Nuclear Information System (INIS)

Prasad, Y.S.R.

1977-01-01

Testing and start up operations of a nuclear power plant require careful planning. A detailed program of tests and the responsibility of implementing them is discussed. Requirement of documentation covering the tests and operating procedures is explained. The performance of the system during normal and abnomal operating conditions is analysed and required are modifications carried out. Various phases of commissioning and their significance are explained. Preparation of maintenance documentation and training of operating and maintenance staff during this period are discussed. Necessity of close liaison between the regulatory body and the operating organization is explained. (orig.) [de

Study of transitory regimes in hydraulic cooling circuits

International Nuclear Information System (INIS)

Bonnin, Jacques; Fanelli, Michel.

1975-01-01

The problem of transient regimes operated voluntary or not in hydraulic circuits is posed and the risks they cause are shown. As for the case of coolant flow loss the various methods for studying the problem are examined: numerical simulation (explicit and implicit), physical model, on-site testing. The numerical methods that not yet fully satisfying or economic, are still very badly representative for hollow closures. Physical models, expensive in the case of a first facility, are not still fully representative (inconsistent similitudes, difficulties in pump picturing). Site test recordings are often a trouble for exploitation and always limited to nondestructive tests. Comparison between the three methods, already satisfying, will have to be improved to allow remedies to the over pressures due to the transients to be developed [fr

Neutron-induced soft errors in CMOS circuits

International Nuclear Information System (INIS)

Hazucha, P.

1999-01-01

The subject of this thesis is a systematic study of soft errors occurring in CMOS integrated circuits when being exposed to radiation. The vast majority of commercial circuits operate in the natural environment ranging from the sea level to aircraft flight altitudes (less than 20 km), where the errors are caused mainly by interaction of atmospheric neutrons with silicon. Initially, the soft error rate (SER) of a static memory was measured for supply voltages from 2V to 5V when irradiated by 14 MeV and 100 MeV neutrons. Increased error rate due to the decreased supply voltage has been identified as a potential hazard for operation of future low-voltage circuits. A novel methodology was proposed for accurate SER characterization of a manufacturing process and it was validated by measurements on a 0.6 μm process and 100 MeV neutrons. The methodology can be applied to the prediction of SER in the natural environment

Earth current monitoring circuit for inductive loads

CERN Document Server

Montabonnet, V; Thurel, Y; Cussac, P

2010-01-01

The search for higher magnetic fields in particle accelerators increasingly demands the use of superconducting magnets. This magnet technology has a large amount of magnetic energy storage during operation at relatively high currents. As such, many monitoring and protection systems are required to safely operate the magnet, including the monitoring of any leakage of current to earth in the superconducting magnet that indicates a failure of the insulation to earth. At low amplitude, the earth leakage current affects the magnetic field precision. At a higher level, the earth leakage current can additionally generate local losses which may definitively damage the magnet or its instrumentation. This paper presents an active earth fault current monitoring circuit, widely deployed in the converters for the CERN Large Hadron Collider (LHC) superconducting magnets. The circuit allows the detection of earth faults before energising the circuit as well as limiting any eventual earth fault current. The electrical stress...

Operation experience with elevated ammonia

International Nuclear Information System (INIS)

Vankova, Katerina; Kysela, Jan; Malac, Miroslav; Petrecky, Igor; Svarc, Vladimir

2011-01-01

The 10 VVER units in the Czech and Slovak Republics are all in very good water chemistry and radiation condition, yet questions have arisen regarding the optimization of cycle chemistry and improved operation in these units. To address these issues, a comprehensive experimental program for different water chemistries of the primary circuit was carried out at the Rez Nuclear Research Institute, Czech Republic, with the goal of judging the influence of various water chemistries on radiation build-up. Four types of water chemistries were compared: standard VVER water chemistry (in common use), direct hydrogen dosing without ammonia, standard VVER water chemistry with elevated ammonia levels, and zinc dosing to standard VVER water chemistry. The test results showed that the types of water chemistry other than the common one have benefits for the operation of the nuclear power plant (NPP) primary circuit. Operation experience with elevated ammonia at NPP Dukovany Units 3 and 4 is presented which validates the experimental results, demonstrating improved corrosion product volume activity. (orig.)

The Automated DC Parameter Testing of GaAs MESFETs Using the Singer Automatic Integrated Circuit Test System.

Science.gov (United States)

1980-09-01

USING THE SINGER AUTOMATIC INTEGRATED CIRCUIT TEST SYSTEM, THOMAS L. HARPER AFIT/EE/GE/80- 7 Ist LT USAF -- -- - - __ AFIT/EE/GE/80-7 THE AUTOMATED DC...THOMAS L. HARPER ist Lt USAF Graduate Electrical Engineering September 1980 it’ Codes A _ _ _ J PREFACE This report is in support of the ongoing effort in...8217.-- I *t -1 ,p - tUel-, ir. ( /.s , j Yf) L) b ..... l P i:. +’ ,T i~: ",,’+l l L V i i ,’b : O Iil r, P V 47 C’+t ( ’ I ViH 47 V ’L 4 £, ,.;l 1 , h

Circuit training enhances function in patients undergoing total knee arthroplasty: a retrospective cohort study.

Science.gov (United States)

Hsu, Wei-Hsiu; Hsu, Wei-Bin; Shen, Wun-Jer; Lin, Zin-Rong; Chang, Shr-Hsin; Hsu, Robert Wen-Wei

2017-10-19

The number of patients receiving total knee arthroplasty (TKA) has been rising every year due to the aging population and the obesity epidemic. Post-operative rehabilitation is important for the outcome of TKA. A series of 34 patients who underwent primary unilateral TKA was retrospectively collected and divided into either exercise group (n = 16) and control group (n = 18). The exercise group underwent a 24-week course of circuit training beginning 3 months after total knee arthroplasty (TKA). The effect of circuit training on TKA patients in terms of motion analysis, muscle strength testing, Knee injury and Osteoarthritis Outcomes Score (KOOS) questionnaire and patient-reported outcome measurement Short-Form Health Survey (SF-36) at the pre-operation, pre-exercise, mid-exercise, and post-exercise. Motion analysis revealed the stride length, step velocity, and excursion of active knee range of motion significantly improved in the exercise group when compared to those in the control group. KOOS questionnaire showed a greater improvement in pain, ADL, and total scores in the exercise group. The SF-36 questionnaire revealed a significant improvement in general health, bodily pain, social function, and physical components score in the exercise group. The post-operative circuit training intervention can facilitate recovery of knee function and decrease the degree of pain in the TKA and might be considered a useful adjunct rehabilitative modality. The ultimate influence of circuit training on TKA needs further a prospective randomized clinical trial study and long-term investigation. NCT02928562.

SSC Test Operations Contract Overview

Science.gov (United States)

Kleim, Kerry D.

2010-01-01

This slide presentation reviews the Test Operations Contract at the Stennis Space Center (SSC). There are views of the test stands layouts, and closer views of the test stands. There are descriptions of the test stand capabilities, some of the other test complexes, the Cryogenic propellant storage facility, the High Pressure Industrial Water (HPIW) facility, and Fluid Component Processing Facility (FCPF).

Development of electron beam deflection circuit

International Nuclear Information System (INIS)

Leo Kwee Wah; Lojius Lombigit; Abu Bakar Ghazali; Azaman

2007-01-01

This paper describes a development of a power supply circuit to deflect and move the electron beam across the window of the Baby electron beam machine. It comprises a discussion of circuit design, its assembly and the test results. A variety of input and output conditions have been tested and it was found that the design is capable to supply 1.0 A with 50Hz on X-axis coil and 0.4A with 500Hz on Y-axis coil. (Author)

Simulation Analysis of DC and Switching Impulse Superposition Circuit

Science.gov (United States)

Zhang, Chenmeng; Xie, Shijun; Zhang, Yu; Mao, Yuxiang

2018-03-01

Surge capacitors running between the natural bus and the ground are affected by DC and impulse superposition voltage during operation in the converter station. This paper analyses the simulation aging circuit of surge capacitors by PSCAD electromagnetic transient simulation software. This paper also analyses the effect of the DC voltage to the waveform of the impulse voltage generation. The effect of coupling capacitor to the test voltage waveform is also studied. Testing results prove that the DC voltage has little effect on the waveform of the output of the surge voltage generator, and the value of the coupling capacitor has little effect on the voltage waveform of the sample. Simulation results show that surge capacitor DC and impulse superimposed aging test is feasible.

New way on designing majorant coincidence circuits

International Nuclear Information System (INIS)

Gajdamaka, R.I.; Kalinnikov, V.A.; Nikityuk, N.M.; Shirikov, V.P.

1982-01-01

A new way of designing fast devices of combinatorial selection by the number of particles passing through a multichannel charged particle detector is decribed. The algorithm of their operation is based on modern algebraic coding theory. By application of analytical computational methods Boolean expressions can be obtianed for designing basic circuits for a large number of inputs. An example of computation of 15 inputs majorant coincidence circuit is considered

Pulse-power circuit diagnostics for the Nova laser

International Nuclear Information System (INIS)

Christie, D.J.; Dallum, G.E.; Gritton, D.G.; Merritt, B.T.; Whitham, K.; Berkbigler, L.W.

1982-01-01

The Nova laser will have a large pulse power system for driving laser amplifiers, incorporating approximately 1600 flashlamp circuits. An automated system has been designed for diagnosing the condition of these flashlamp circuits. It records digitized circuit current waveforms and detects current excursions above a given threshold. In addition, it is able to fire flashlamps at a low energy to ascertain the health of the system. Data from this system can be ploted for inspection by the operator, analyzed by the computer system and archived for future reference

Study of the interaction between heavy ions and integrated circuits using a pulsed laser beam

International Nuclear Information System (INIS)

Lewis, D.; Fouillat, P.; Pouget, V.; Lapuyade, H.

2002-01-01

A new pulsed laser beam equipment dedicated to the characterization of integrated circuit is presented. Using ultra-short laser pulses is a convenient way to simulate experimentally the spatial environment of integrated circuits when interactions with heavy ions occur. This experimental set-up can be considered as a complementary tool for particle accelerators to evaluate the hardness assurance of integrated circuits for space applications. These particles generate temporally electrical disturbance called Single Event Effect (SEE). The theoretical approach of an equivalence between heavy ions and a laser pulses is discussed. The experimental set-up and some relevant operational methodologies are presented. Experimental results demonstrate that the induced electrical responses due to an heavy ion or a laser pulse are quite similar. Some sensitivity mappings of integrated circuits provided by this test bench illustrate the capabilities and the limitations of this laser-based technique. Contrary to the particle accelerators, it provides useful information concerning the spatial and temporal dependences of SEE mechanisms. (authors)

Fully Integrated Solar Energy Harvester and Sensor Interface Circuits for Energy-Efficient Wireless Sensing Applications

Directory of Open Access Journals (Sweden)

Maher Kayal

2013-02-01

Full Text Available This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used to transmit the measurement results to a base station. As the harvested solar energy varies considerably in different lighting conditions, in order to guarantee autonomous operation of the sensor, the proposed area- and energy-efficient circuit scales the power consumption and performance of the sensor. The power management circuit dynamically decreases the operating frequency of digital circuits and bias currents of analog circuits in the sensor interface circuit and increases the idle time of the transceiver under reduced light intensity. The proposed microsystem has been implemented in a 0.18 µm complementary metal-oxide-semiconductor (CMOS process and occupies a core area of only 0.25 mm2. This circuit features a low power consumption of 2.1 µW when operating at its highest performance. It operates with low power supply voltage in the 0.8V to 1.6 V range.

Nanophotonic integrated circuits from nanoresonators grown on silicon.

Science.gov (United States)

Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

2014-07-07

Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

A high-precision synchronization circuit for clock distribution

International Nuclear Information System (INIS)

Lu Chong; Tan Hongzhou; Duan Zhikui; Ding Yi

2015-01-01

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm 2 , and the power consumption is 1.64 mW at 500 MHz. (paper)

Operation control device for a nuclear reactor fuel exchanger

International Nuclear Information System (INIS)

Aida, Takashi.

1984-01-01

Purpose: To provide a operation control device for a nuclear reactor fuel exchanger with reduced size and weight capable of optionally meeting the complicated and versatile mode of the operation scope. Constitution: The operation range of a fuel exchanger is finely divided so as to attain the state capable of discriminating between operation-allowable range and operation-inhibitive range, which are stored in a memory circuit. Upon operating the fuel exchanger, the position is detected and a divided range data corresponding to the present position is taken out from the memory circuit so as to determine whether the fuel exchanger is to be run or stopped. Use of reduced size and compact IC circuits (calculation circuit, memory circuit, data latch circuit) and input/output interface circuits or the likes contributes to the size reduction of the exchanger control system to enlarge the floor maintenance space. (Moriyama, K.)

The oil pressure test of the hydraulic impeller blade

Science.gov (United States)

Ye, Wen-bo; Jia, Li-tao

2017-12-01

This article introduced the structure of the Kaplan runner in hydropower station and the operating process of the oil pressure test has been described. What’s more, the whole process, including filling oil to the runner hub, the movement of the runner blade, the oil circuit, have been presented in detail.Since the manipulation of the oil circuit which controlled by three Valve groups consisting of six valves was complicated, the author is planning to replace them with 3-position 3-way electromagnetic valves, so we can simplify the operation procedure.The author hopes this article can provide technical reference for the oil pressure test.

The design of charge measurement circuit of MWPC

International Nuclear Information System (INIS)

Guan Xiaolei; Xiang Haisheng; Sheng Huayi; Zhao Yubin; Zhao Pingping; Zhang Hongyu; Jiang Xiaoshan; Zhao Jingwei; Zhao Dongxu

2010-01-01

It introduces the design of charge measurement (MQ) circuit of MWPC, including how MQ works in the whole MWPC readout electronic system, the architecture of MQ circuit, and the logic and algorithm design of FPGA. MQ circuit can also be applied to readout systems for other detectors. The test results in different working modes are provided. (authors)

Active quenching circuit for a InGaAs single-photon avalanche diode

International Nuclear Information System (INIS)

Zheng Lixia; Wu Jin; Xi Shuiqing; Shi Longxing; Liu Siyang; Sun Weifeng

2014-01-01

We present a novel gated operation active quenching circuit (AQC). In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I–V characteristic measurement results of the detector. The circuit integrated with aROIC (readout integrated circuit) is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications. (semiconductor integrated circuits)

Circuit bridging of components by smoke

International Nuclear Information System (INIS)

Tanaka, T.J.; Nowlen, S.P.; Anderson, D.J.

1996-10-01

Smoke can adversely affect digital electronics; in the short term, it can lead to circuit bridging and in the long term to corrosion of metal parts. This report is a summary of the work to date and component-level tests by Sandia National Laboratories for the Nuclear Regulatory Commission to determine the impact of smoke on digital instrumentation and control equipment. The component tests focused on short-term effects such as circuit bridging in typical components and the factors that can influence how much the smoke will affect them. These factors include the component technology and packaging, physical board protection, and environmental conditions such as the amount of smoke, temperature of burn, and humidity level. The likelihood of circuit bridging was tested by measuring leakage currents and converting those currents to resistance in ohms. Hermetically sealed ceramic packages were more resistant to smoke than plastic packages. Coating the boards with an acrylic spray provided some protection against circuit bridging. The smoke generation factors that affect the resistance the most are humidity, fuel level, and burn temperature. The use of CO 2 as a fire suppressant, the presence of galvanic metal, and the presence of PVC did not significantly affect the outcome of these results

Resonance circuits for adiabatic circuits

Directory of Open Access Journals (Sweden)

C. Schlachta

2003-01-01

Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

Novel circuits for radiation hardened memories

International Nuclear Information System (INIS)

Haraszti, T.P.; Mento, R.P.; Moyer, N.E.; Grant, W.M.

1992-01-01

This paper reports on implementation of large storage semiconductor memories which combine radiation hardness with high packing density, operational speed, and low power dissipation and require both hardened circuit and hardened process technologies. Novel circuits, including orthogonal shuffle type of write-read arrays, error correction by weighted bidirectional codes and associative iterative repair circuits, are proposed for significant improvements of SRAMs' immunity against the effects of total dose and cosmic particle impacts. The implementation of the proposed circuit resulted in fault-tolerant 40-Mbit and 10-Mbit monolithic memories featuring a data rate of 120 MHz and power dissipation of 880 mW. These experimental serial-parallel memories were fabricated with a nonhardened standard CMOS processing technology, yet provided a total dose hardness of 1 Mrad and a projected SEU rate of 1 x 10 - 12 error/bit/day. Using radiation hardened processing improvements by factors of 10 to 100 are predicted in both total dose hardness and SEU rate

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array

Directory of Open Access Journals (Sweden)

Jian-Feng Wu

2016-12-01

Full Text Available With one operational amplifier (op-amp in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements’ bypass currents, which were injected into array’s non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT’s measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately.

An Enhanced Random Vibration and Fatigue Model for Printed Circuit Boards

Directory of Open Access Journals (Sweden)

Bruno de Castro Braz

Full Text Available Abstract Aerospace vehicles are mostly exposed to random vibration loads during its operational lifetime. These harsh conditions excites vibration responses in the vehicles printed circuit boards, what can cause failure on mission functionality due to fatigue damage of electronic components. A novel analytical model to evaluate the useful life of embedded electronic components (capacitors, chips, oscillators etc. mounted on Printed Circuit Boards (PCB is presented. The fatigue damage predictions are calculated by the relative displacement between the PCB and the component, the lead stiffness, as well the natural vibration modes of the PCB and the component itself. Statistical methods are used for fatigue cycle counting. The model is applied to experimental fatigue tests of PCBs available on literature. The analytical results are of the same magnitude order of the experimental findings.

A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators

Directory of Open Access Journals (Sweden)

Leon Chua

2012-03-01

Full Text Available A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

Water chemistry and corrosion in water-steam circuits of nuclear power plants

International Nuclear Information System (INIS)

Gardent, R.; Menet, O.

1981-01-01

The water and steam circuits of steam generators in pressurized-water nuclear power plants are described together with the mechanism of denting, and the corrosion of spacer plates that leads to cracks in tubes by constriction. The different chemical specifications applicable to the water of the secondary circuit of the generators in normal operation and on first commissioning are listed. The results obtained and the measurements of chemical values taken in operation on the water in the secondary circuits of steam generators at Fessenheim and Bugey are presented [fr

Wiring Together Synthetic Bacterial Consortia to Create a Biological Integrated Circuit.

Science.gov (United States)

Perry, Nicolas; Nelson, Edward M; Timp, Gregory

2016-12-16

The promise of adapting biology to information processing will not be realized until engineered gene circuits, operating in different cell populations, can be wired together to express a predictable function. Here, elementary biological integrated circuits (BICs), consisting of two sets of transmitter and receiver gene circuit modules with embedded memory placed in separate cell populations, were meticulously assembled using live cell lithography and wired together by the mass transport of quorum-sensing (QS) signal molecules to form two isolated communication links (comlinks). The comlink dynamics were tested by broadcasting "clock" pulses of inducers into the networks and measuring the responses of functionally linked fluorescent reporters, and then modeled through simulations that realistically captured the protein production and molecular transport. These results show that the comlinks were isolated and each mimicked aspects of the synchronous, sequential networks used in digital computing. The observations about the flow conditions, derived from numerical simulations, and the biofilm architectures that foster or silence cell-to-cell communications have implications for everything from decontamination of drinking water to bacterial virulence.

Sistem Proteksi Arus Bocor Menggunakan Earth Leakage Circuit Breaker Berbasis Arduino

Directory of Open Access Journals (Sweden)

Syukriyadin Syukriyadin

2017-02-01

Full Text Available Touching a live part of electrical equipment either intentionally or unintentionally can cause an electric shock. The touch can occur directly or indirectly and results in the flow of electric current through the human body to the ground. This electric current is known as the leakage current and can have fatal effects on the human body such as burns, cramps, faint and death. This paper aims to design a prototype protection model of the earth leakage circuit breaker device based on Arduino (ELCBA to protect the human body from the electrical hazards. The performance of the ELCBA is investigated by detecting the earth leakage current to the grounding system (TN.  The prototype is designed and simulated by using Proteus software. Based on the response test carried out on the prototype, it can be concluded that the ELCBA can operate properly to disconnect the electric circuit if the leakage current is detected greater than or equal to 30 mA with a time delay of 15 ms and to reclose the circuit again after 5 minutes.

Testing of SF6- and vacuum generator circuit breakers

NARCIS (Netherlands)

Smeets, R.P.P.; Paske, te L.H.

2011-01-01

Generator circuit breakers differ in various aspects from standard distribution breakers. One of the main differences is in the electrical stresses during fault current interruption. This situation will be discussed in the present contribution, along with the standardization status and the

A High-Voltage Level Tolerant Transistor Circuit

NARCIS (Netherlands)

Annema, Anne J.; Geelen, Godefridus Johannes Gertrudis Maria

2001-01-01

A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1)

Multi-qubit circuit quantum electrodynamics

International Nuclear Information System (INIS)

Viehmann, Oliver

2013-01-01

Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

Multi-qubit circuit quantum electrodynamics

Energy Technology Data Exchange (ETDEWEB)

Viehmann, Oliver

2013-09-03

Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

On-Chip AC self-test controller

Science.gov (United States)

Flanagan, John D [Rhinebeck, NY; Herring, Jay R [Poughkeepsie, NY; Lo, Tin-Chee [Fishkill, NY

2009-09-29

A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.

Efficiently characterizing the total error in quantum circuits

Science.gov (United States)

Carignan-Dugas, Arnaud; Wallman, Joel J.; Emerson, Joseph

A promising technological advancement meant to enlarge our computational means is the quantum computer. Such a device would harvest the quantum complexity of the physical world in order to unfold concrete mathematical problems more efficiently. However, the errors emerging from the implementation of quantum operations are likewise quantum, and hence share a similar level of intricacy. Fortunately, randomized benchmarking protocols provide an efficient way to characterize the operational noise within quantum devices. The resulting figures of merit, like the fidelity and the unitarity, are typically attached to a set of circuit components. While important, this doesn't fulfill the main goal: determining if the error rate of the total circuit is small enough in order to trust its outcome. In this work, we fill the gap by providing an optimal bound on the total fidelity of a circuit in terms of component-wise figures of merit. Our bound smoothly interpolates between the classical regime, in which the error rate grows linearly in the circuit's length, and the quantum regime, which can naturally allow quadratic growth. Conversely, our analysis substantially improves the bounds on single circuit element fidelities obtained through techniques such as interleaved randomized benchmarking. This research was supported by the U.S. Army Research Office through Grant W911NF- 14-1-0103, CIFAR, the Government of Ontario, and the Government of Canada through NSERC and Industry Canada.

Clipper circuit of pulse modulator used for klystron-5045 power supply

CERN Document Server

Akimov, A V

2001-01-01

While the operation of modulator to the pulsed transformer of klystron-5045, current through the primary winding of the pulse transformer (PT) continues to flow even upon the end of the klystron voltage operating pulse. This is determined by an energy stored in magnetizing inductance. The prolongation of magnetizing current passing process simultaneously with the premature choking of thyratron can cause high voltage of inverse polarity at the klystron, which cause the destruction of the cathode. We have considered the possibility of shortening time of magnetizing current passage for the charge of reasonable choice of clipper circuit parameters. The behavior of clipper circuit was studied in modulators used for the VEPP-5 (BINP, Russia) preinjector klystron power supply. The optimum operation run of the circuit was selected and its design features are described.

A diagonal address generator for a Josephson memory circuit

International Nuclear Information System (INIS)

Suzuki, H.; Hasuo, S.

1987-01-01

The authors propose that a diagonal D address generator, which is useful for a single flux quantum (SFQ) memory cell in the triple coincidence scheme, can be performed by a full adder circuit. For the purpose of evaluating the D address generator for a 16-kbit memory circuit, a 6-bit full adder circuit, using a current-steering flip-flop circuit, has been designed and fabricated with the lead-alloy process. Operating times for the address latch, carry generator, and sum generator were 150 ps, 250 ps/stage, and 1.4 ns, respectively. From these results, they estimate that the time necessary for the diagonal signal generation is 2.8 ns

Test tube systems with cutting/recombination operations

Energy Technology Data Exchange (ETDEWEB)

Freund, R. [Technische Universitaet Wien (Austria); Csuhaj-Varju, E. [Computer and Automation Institute, Budapest (Hungary); Wachtler, F. [Universitaet Wien (Austria)

1996-12-31

We introduce test tube systems based on operations that are closely related to the splicing operations, i.e. we consider the operations of cutting a string at a specific site into two pieces with marking them at the cut ends and of recombining two strings with specifically marked endings. Whereas in the splicing of two strings these strings are cut at specific sites and the cut pieces are recombined immediately in a crosswise way, in CR(cutting/recombination)-schemes cutting can happen independently from recombining the cut pieces. Test tube systems based on these operations of cutting and recombination turn out to have maximal generative power even if only very restricted types of input filters for the test tubes are used for the redistribution of the contents of the test tubes after a period of cuttings and recombinations in the test tubes. 10 refs.

A Alternative Analog Circuit Design Methodology Employing Integrated Artificial Intelligence Techniques

Science.gov (United States)

Tuttle, Jeffery L.

In consideration of the computer processing power now available to the designer, an alternative analog circuit design methodology is proposed. Computer memory capacities no longer require the reduction of the transistor operational characteristics to an imprecise formulation. Therefore, it is proposed that transistor modelling be abandoned in favor of fully characterized transistor data libraries. Secondly, availability of the transistor libraries would facilitate an automated selection of the most appropriate device(s) for the circuit being designed. More specifically, a preprocessor computer program to a more sophisticated circuit simulator (e.g. SPICE) is developed to assist the designer in developing the basic circuit topology and the selection of the most appropriate transistor. Once this is achieved, the circuit topology and selected transistor data library would be downloaded to the simulator for full circuit operational characterization and subsequent design modifications. It is recognized that the design process is enhanced by the use of heuristics as applied to iterative design results. Accordingly, an artificial intelligence (AI) interface is developed to assist the designer in applying the preprocessor results. To demonstrate the retrofitability of the AI interface to established programs, the interface is specifically designed to be as non-intrusive to the host code as possible. Implementation of the proposed methodology offers the potential to speed the design process, since the preprocessor both minimizes the required number of simulator runs and provides a higher acceptance potential of the initial and subsequent simulator runs. Secondly, part count reductions may be realizable since the circuit topologies are not as strongly driven by transistor limitations. Thirdly, the predicted results should more closely match actual circuit operations since the inadequacies of the transistor models have been virtually eliminated. Finally, the AI interface

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

Science.gov (United States)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Silicon integrated circuit process

International Nuclear Information System (INIS)

Lee, Jong Duck

1985-12-01

This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

Silicon integrated circuit process

Energy Technology Data Exchange (ETDEWEB)

Lee, Jong Duck

1985-12-15

This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

Micromachined integrated quantum circuit containing a superconducting qubit

Science.gov (United States)