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Sample records for stacked cmos chip

  1. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  2. On-chip deposition of carbon nanotubes using CMOS microhotplates

    International Nuclear Information System (INIS)

    Haque, M S; Teo, K B K; Rupensinghe, N L; Ali, S Z; Haneef, I; Maeng, Sunglyul; Park, J; Udrea, F; Milne, W I

    2008-01-01

    The direct deposition of carbon nanotubes on CMOS microhotplates is demonstrated in this paper. Tungsten microhotplates, fabricated on thin SOI membranes aside CMOS control circuitry, are used to locally grow carbon nanotubes by chemical vapour deposition. Unlike bulk heating of the entire chip, which could cause degradation to CMOS devices and interconnects due to high growth temperatures in excess of 500 deg. C, this novel technique allows carbon nanotubes to be grown on-chip in localized regions. The microfabricated heaters are thermally isolated from the rest of the CMOS chip as they are on the membranes. This allows carbon nanotubes to be grown alongside CMOS circuitry on the same wafer without any external heating, thus enabling new applications (e.g. smart gas sensing) where the integration of CMOS and carbon nanotubes is required

  3. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  4. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  5. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  6. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  7. CMOS realization of a 2-layer CNN universal machine chip.

    Science.gov (United States)

    Carmona, R; Jiménez-Garrido, F; Domínguez-Castro, R; Espejo, S; Rodríguez-Vázquez, A

    2003-12-01

    Some features of the biological retina can be modelled by a 2-layer cellular neural network (CNN) composed of locally connected elementary nonlinear processors. In order to explore these complex spatiotemporal dynamics for image processing, a prototype chip has been designed and fabricated in a 0.5 microm CMOS technology. Design challenges, trade-offs, the building blocks and the tests results for this system with 0.5 x 10(6) transistors, most of them operating in analog mode, are presented in this paper.

  8. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  9. Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

    Science.gov (United States)

    Li, Lin; Yin, Heyu; Mason, Andrew J

    2018-04-01

    The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

  10. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  11. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  12. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  13. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    Science.gov (United States)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  14. Volumetric imaging using single chip integrated CMUT-on-CMOS IVUS array.

    Science.gov (United States)

    Tekes, Coskun; Zahorian, Jaime; Gurun, Gokce; Satir, Sarp; Xu, Toby; Hochman, Michael; Degertekin, F Levent

    2012-01-01

    An intravascular ultrasound (IVUS) catheter that can provide forward viewing volumetric ultrasound images would be an invaluable clinical tool for guiding interventions. Single chip integration of front-end electronics with capacitive micromachined ultrasonic transducers (CMUTs) is highly desirable to reduce the interconnection complexity and enable miniaturization in IVUS catheters. For this purpose we use the monolithic CMUT-on-CMOS integration where CMUTs are fabricated directly on top of pre-processed CMOS wafers. This minimizes parasitic capacitances associated with connection lines. We have recently implemented a system design including all the required electronics using 0.35-µm CMOS process integrated with a 1.4-mm diameter CMUT array. In this study, we present the experimental volumetric imaging results from an ex-vivo chicken heart phantom. The imaging results demonstrate that the single-chip forward looking IVUS (FL-IVUS) system with monolithically integrated electronics has potential to visualize the front view of coronary arteries.

  15. 3D stacked chips from emerging processes to heterogeneous systems

    CERN Document Server

    Fettweis, Gerhard

    2016-01-01

    This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

  16. Experimental verification of on-chip CMOS fractional-order capacitor emulators

    KAUST Repository

    Tsirimokou, G.

    2016-06-13

    The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

  17. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    CERN Document Server

    AUTHOR|(SzGeCERN)756402

    2017-01-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using...

  18. Electromagnetic design methods in systems-on-chip: integrated filters for wireless CMOS RFICs

    International Nuclear Information System (INIS)

    Contopanagos, Harry

    2005-01-01

    We present general methods for designing on-chip CMOS passives and utilizing these integrated elements to design on-chip CMOS filters for wireless communications. These methods rely on full-wave electromagnetic numerical calculations that capture all the physics of the underlying foundry technologies. This is especially crucial for deep sub-micron CMOS technologies as it is important to capture the physical effects of finite (and mediocre) Q-factors limited by material losses and constraints on expensive die area, low self-resonance frequencies and dual parasitics that are particularly prevalent in deep sub-micron CMOS processes (65 nm-0.18 μm. We use these integrated elements in an ideal synthesis of a Bluetooth/WLAN pass-band filter in single-ended or differential architectures, and show the significant deviations of the on-chip filter response from the ideal one. We identify which elements in the filter circuit need to maximize their Q-factors and which Q-factors do not affect the filter performance. This saves die area, and predicts the FET parameters (especially transconductances) and negative-resistance FET topologies that have to be integrated in the filter to restore its performance. (invited paper)

  19. A 24 GHz CMOS oscillator transmitter with an inkjet printed on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.

    2016-08-15

    CMOS based RF circuits have demonstrated efficient performance over the decades. However, one bottle neck with this technology is its lossy nature for passive components such as inductors, antennas etc. Due to this drawback, passives are either implemented off chip or the designers work with the inefficient passives. This problem can be alleviated by using inkjet printing as a post process on CMOS chip. In this work, we demonstrate inkjet printing of a patterned polymer (SU8) layer on a 24 GHz oscillator chip to isolate the lossy Si substrate from the passives which are inkjet printed on top of the SU8 layer. As a proof of concept, a monopole antenna is printed on top of the SU8 layer integrating it with the oscillator through the exposed RF pads to realize an oscillator transmitter. The proposed hybrid fabrication technique can be extended to multiple dielectric and conductive printed layers to demonstrate complete RF systems on CMOS chips which are efficient, cost-effective and above all small in size. © 2016 IEEE.

  20. CMOS active pixel sensor type imaging system on a chip

    Science.gov (United States)

    Fossum, Eric R. (Inventor); Nixon, Robert (Inventor)

    2011-01-01

    A single chip camera which includes an .[.intergrated.]. .Iadd.integrated .Iaddend.image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the .[.intergrated.]. .Iadd.integrated .Iaddend.structure reduces the noise that is picked up during imaging.

  1. A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2007-01-01

    Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate

  2. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2015-03-01

    Full Text Available This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  3. Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

    Science.gov (United States)

    López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  4. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    Directory of Open Access Journals (Sweden)

    Chang-Hung Lee

    2014-05-01

    Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  5. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Milin Zhang

    2010-01-01

    Full Text Available Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

  6. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  7. CMOS front end analog signal readout chip for Si-strip/PIN detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2001-01-01

    The paper presents the design of an 8-channel front-end chip for Si-strip detectors, ranging in capacitance from 1 to 30 pf. Each channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a track-hold stage. The channel outputs are connected to an analog multiplexer which is controlled by an external clock for serial readout. The peaking time is adjustable over 250ns-2us in four fixed steps by external control. There is provision for changing gain low/high. A derivative of the chip is also developed for dosimeter application that uses small area diodes as detectors. The circuit has a power dissipation of 6 MW per channel and is designed to fabricate in 1.2um CMOS technology. The Opf noise is ∼400e. The design approach is presented and the results of simulation are shown. (author)

  8. Electronic radon monitoring with the CMOS System-on-Chip AlphaRad

    Energy Technology Data Exchange (ETDEWEB)

    Higueret, S. [Institut Pluridisciplinaire Hubert Curien (IPHC) UMR 7500 CNRS/IN2P3, 23 rue du Loess, BP 28, F-67037 Strasbourg Cedex 2 (France); Husson, D. [Institut Pluridisciplinaire Hubert Curien (IPHC) UMR 7500 CNRS/IN2P3, 23 rue du Loess, BP 28, F-67037 Strasbourg Cedex 2 (France)], E-mail: Daniel.Husson@ires.in2p3.fr; Le, T.D.; Nourreddine, A. [Institut Pluridisciplinaire Hubert Curien (IPHC) UMR 7500 CNRS/IN2P3, 23 rue du Loess, BP 28, F-67037 Strasbourg Cedex 2 (France); Michielsen, N. [Institut de Radioprotection et de Surete Nucleaire (IRSN, DSU-SERAC-LPMA), BP 68, 91192 Gif-sur-Yvette Cedex (France)

    2008-01-11

    The development of the integrated circuit AlphaRad as a new System-on-Chip for detection of {alpha}-particles has already been reported. This paper deals with electronic monitoring of atmospheric radon, which is one of the promising applications of the chip. The future electronic radon monitor (ERM) is designed to be compact, inexpensive, operating at low voltage and fully stand-alone. We present here the complete electronic board of the future ERM: it is made of three independent AlphaRad chips running in parallel, mounted on a small printed-circuit board which includes a numeric block for data treatment based on a Xilinx programmable gate array. The maximal counting rate of the AlphaRad chip has been pushed to at least 3x10{sup 6} {alpha}-particles cm{sup -2}. The complete system for detection of the solid aerosols will be published separately, and this paper will focus on the electronic board alone. Already 20 times faster than our first measurement with a CMOS pixel sensor, the system was tested at low and high activities, showing an excellent linearity for {sup 222}Rn levels up to 80 kBq m{sup -3}.

  9. 3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

    Science.gov (United States)

    Le, Fuliang; Lee, Shi-Wei Ricky; Zhang, Qiming

    2017-04-01

    3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

  10. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  11. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    2018-02-02

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  12. Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

    Science.gov (United States)

    He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

    2013-09-18

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  13. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    Directory of Open Access Journals (Sweden)

    Cally Gill

    2013-09-01

    Full Text Available The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  14. Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

    Science.gov (United States)

    Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

    2017-09-01

    The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

  15. An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

    Directory of Open Access Journals (Sweden)

    Ismail Cevik

    2015-03-01

    Full Text Available An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT-based power management system (PMS is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

  16. An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

    Science.gov (United States)

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

    2015-03-06

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

  17. Modular high-performance 2-μm CCD-BiCMOS process technology for application-specific image sensors and image sensor systems on a chip

    Science.gov (United States)

    Guidash, R. Michael; Lee, P. P. K.; Andrus, J. M.; Ciccarelli, Antonio S.; Erhardt, H. J.; Fischer, J. R.; Meisenzahl, Eric J.; Philbrick, Robert H.; Kenney, Timothy J.

    1995-04-01

    A 2 micrometers BiCMOS process module has been developed for incorporation into existing high performance 2-phase CCD processes, to enable integration of digital and analog circuits on- chip with the CCD image sensor. The modular process architecture allows the integration of CMOS, NPN bipolar or BiCMOS circuits without affecting the baseline CCD characteristics. A design of experiments approach was employed using process and device simulation tools and selected physical experiments, to optimize CMOS and NPN device performance and process latitude. Both enhancement and depletion mode Poly-1 and Poly-2 CMOS devices were realized and demonstrated good long channel behavior down to 1.6 micrometers drawn. A 12 V, 2.5 GHz, low collector resistance NPN was also produced. Experimental process splits were used to demonstrate and verify that the CMOS and NPN process module incorporation did not affect the CCD device characteristics or yield. CMOS circuit performance was found to be comparable to that of a standard 2 micrometers CMOS process. Finally, a trilinear sensor with on-chip timing generation and correlated double sample was designed and fabricated. To our knowledge this is the first demonstration of high performance CCD, 2 micrometers CMOS, and an isolated vertical NPN, integrated on the same chip.

  18. AlphaRad, a new integrated CMOS System-on-Chip for high efficiency alpha particles counting

    Energy Technology Data Exchange (ETDEWEB)

    Husson, D. [Universite Louis Pasteur and IPHC (UMR7178), 23 Rue du Loess, BP 28, F-67037, Strasbourg, Cedex 2 (France)]. E-mail: husson@lepsi.in2p3.fr; Bozier, A. [InESS (UMR7163), F-67037 Strasbourg, Cedex 2 (France); Higueret, S. [IPHC - UMR7178, 23 Rue du Loess, BP 28, F-67037 Strasbourg, Cedex 2 (France); Le, T.D. [IPHC - UMR7178, 23 Rue du Loess, BP 28, F-67037 Strasbourg, Cedex 2 (France); Nourreddine, A. [Universite Louis Pasteur and IPHC (UMR7178), 23 Rue du Loess, BP 28, F-67037, Strasbourg, Cedex 2 (France)

    2006-12-21

    An integrated System-on-Chip (SoC) has been designed in 0.6{mu}m CMOS mixed analog/digital technology, and tested for high rate alpha particle counting. The sensor is the most innovative part of the chip, with a total active area of 2x2.5mmx5mm. The two-stage charge-to-voltage amplification scheme includes a numerical block for offset compensation. Designed with a gain of 700, the chip has been tested in alpha sources: a very high signal over noise ratio was obtained, leading to a detection efficiency of 5MeV alpha particles close to 100%. The chip is working at room temperature and has been tested up to 300kHz reset frequency. Future applications of this SoC will focus on detection of fast and thermal neutrons free of gamma contamination.

  19. A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

    OpenAIRE

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2007-01-01

    Abstract—Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previous designs (a few Gb/s), but at much lower power than recently published work. Both low static power and low dynamic power (low energy per bit) is aimed for. A capacitive pre-emphasis trans...

  20. A pixel readout chip for 10-30 MRad in standard 0.25 mu m CMOS

    CERN Document Server

    Campbell, M; Burns, M; Cantatore, E; Casagrande, L; Delmastro, M; Dinapoli, R; Faccio, F; Heijne, Erik H M; Jarron, Pierre; Lupták, M; Marchioro, A; Martinengo, P; Minervini, D; Morel, M; Pernigotti, E; Ropotar, I; Snoeys, W; Wyllie, Ken H

    1999-01-01

    A radiation tolerant pixel detector readout chip has been developed in a commercial 0.25 mu m CMOS process. The chip is a matrix of two columns of 65 identical cells. Each readout cell comprises a preamplifier, a shaper filter, a discriminator, a delay line and readout logic. The chip occupies 10 mm/sup 2/, and contains about 50000 transistors. Electronic noise (~220 e rms) and threshold dispersion (~160 e rms) allow operation at 1500 e average threshold. The radiation tolerance of this mixed mode analog-digital circuit has been enhanced by designing NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The chip, which was developed at CERN for the ALICE and LHCb experiments, was still operational after receiving 3.6*10/sup 13/ protons over an area of 2 mm *2 mm. Other chips were irradiated with X-rays and remained fully functional up to 30 Mrad(SiO2) with only minor changes in analog parameters. These results indicate that careful use of deep submicron CMOS technologies can lea...

  1. Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

    Science.gov (United States)

    Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

    2018-01-01

    Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

  2. System on chip thermal vacuum sensor based on standard CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Li Jinfeng; Tang Zhenan; Wang Jiaqi, E-mail: ljf970204@yahoo.com.c [Department of Electronic Engineering, Dalian University of Technology, Dalian 116024 (China)

    2009-03-15

    An on-chip microelectromechanical system was fabricated in a 0.5 mum standard CMOS process for gas pressure detection. The sensor was based on a micro-hotplate (MHP) and had been integrated with a rail to rail operational amplifier and an 8-bit successive approximation register (SAR) A/D converter. A tungsten resistor was manufactured on the MHP as the sensing element, and the sacrificial layer of the sensor was made from polysilicon and etched by surface-micromachining technology. The operational amplifier was configured to make the sensor operate in constant current mode. A digital bit stream was provided as the system output. The measurement results demonstrate that the gas pressure sensitive range of the vacuum sensor extends from 1 to 10{sup 5} Pa. In the gas pressure range from 1 to 100 Pa, the sensitivity of the sensor is 0.23 mV/ Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The operational amplifier can drive 200 omega resistors distortionlessly, and the SAR A/D converter achieves a resolution of 7.4 bit with 100 kHz sample rate. The performance of the operational amplifier and the SAR A/D converter meets the requirements of the sensor system.

  3. A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

    International Nuclear Information System (INIS)

    Wan Chuanchuan; Li Zhiqun; Hou Ningbing

    2011-01-01

    A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

  4. Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

    Directory of Open Access Journals (Sweden)

    Chang-Chun Lee

    2015-08-01

    Full Text Available three-dimensional integrated circuit (3D-IC structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF. The mechanical properties of this equivalent material, including Young’s modulus (E, Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE, are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.

  5. An integrated CMOS quantitative-polymerase-chain-reaction lab-on-chip for point-of-care diagnostics.

    Science.gov (United States)

    Norian, Haig; Field, Ryan M; Kymissis, Ioannis; Shepard, Kenneth L

    2014-10-21

    Considerable effort has recently been directed toward the miniaturization of quantitative-polymerase-chain-reaction (qPCR) instrumentation in an effort to reduce both cost and form factor for point-of-care applications. Considerable gains have been made in shrinking the required volumes of PCR reagents, but resultant prototypes retain their bench-top form factor either due to heavy heating plates or cumbersome optical sensing instrumentation. In this paper, we describe the use of complementary-metal-oxide semiconductor (CMOS) integrated circuit (IC) technology to produce a fully integrated qPCR lab-on-chip. Exploiting a 0.35 μm high-voltage CMOS process, the IC contains all of the key components for performing qPCR. Integrated resistive heaters and temperature sensors regulate the surface temperature of the chip to an accuracy of 0.45 °C. Electrowetting-on-dielectric microfluidics are actively driven from the chip surface, allowing for droplet generation and transport down to volumes less than 1.2 nanoliter. Integrated single-photon avalanche diodes (SPADs) are used for fluorescent monitoring of the reaction, allowing for the quantification of target DNA with more than four-orders-of-magnitude of dynamic range and sensitivities down to a single copy per droplet. Using this device, reliable and sensitive real-time proof-of-concept detection of Staphylococcus aureus (S. aureus) is demonstrated.

  6. On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

    Science.gov (United States)

    Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

    2014-07-10

    Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

  7. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  8. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Science.gov (United States)

    Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

    2017-09-01

    Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  9. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  10. A method enabling height-control of chips for edge-emitting laser stacking

    Science.gov (United States)

    Thanh Tung, Bui; Ma, Laina; Amano, Takeru; Kikuchi, Katsuya; Mori, Masahiko; Aoyagi, Masahiro

    2015-04-01

    In this paper we present a stacking method that enables the mounting of edge-emitting laser (EEL) devices at compulsory positions for feeding a coupling waveguide at a low temperature, i.e., 110 °C. Bonding laser chips are integrated to an interposer with embedded waveguides using an electrically conductive adhesive (ECA), i.e., silver-filled epoxy resin that relied on the surface tension phenomenon. A simple dispensing technique based on the capillary effect was used to generate adhesive droplets for bonding purposes. The ability to control the bonding height from 3 to 25 µm was demonstrated. While the post-bond in-plane offsets of the bonding EEL chip are determined by the accuracy of the bonder (i.e., within 2 µm range), the bonding height can be engineered, with a deviation within 1 µm, by balancing the external bonding forces with the surface tension of a certain adhesive volume. The reliability of the bond, i.e., bond strength of 106 gf, and heat dissipation function of the ECA, were also validated. The results obtained in this work imply that the use of this low-temperature, height-controllable approach for the stacking of EEL continues to look highly promising.

  11. Compact Shorted Stacked-Patch Antenna Integrated with Chip-Package Based on LTCC Technology

    Directory of Open Access Journals (Sweden)

    Yongjiu Li

    2014-01-01

    Full Text Available A low profile chip-package stacked-patch antenna is proposed by using low temperature cofired ceramic (LTCC technology. The proposed antenna employs a stacked-patch to achieve two operating frequency bands and enhance the bandwidth. The height of the antenna is decreased to 4.09 mm (about λ/25 at 2.45 GHz due to the shorted pin. The package is mounted on a 44 × 44 mm2 ground plane to miniaturize the volume of the system. The design parameters of the antenna and the effect of the antenna on chip-package cavity are carefully analyzed. The designed antenna operates at a center frequency of 2.45 GHz and its impedance bandwidth (S11< -10 dB is 200 MHz, resulting from two neighboring resonant frequencies at 2.41 and 2.51 GHz, respectively. The average gain across the frequency band is about 5.28 dBi.

  12. Microfluidic chip for stacking, separation and extraction of multiple DNA fragments.

    Science.gov (United States)

    Wu, Ruige; Seah, Y P; Wang, Zhiping

    2016-03-11

    A disposable integrated microfluidic device was developed for rapid sample stacking, separation and extraction of multiple DNA fragments from a relatively large amount of sample. Isotachophoresis hyphenated gel electrophoresis (ITP-GE) was used to pre-concentrate and separate DNA fragments, followed by extraction of pure DNA fragments with electroelution on-chip. DNA fragments of 200bp, 500bp and 1kbp were successfully separated and collected in the extraction chamber within 25min. The extraction efficiency obtained from the chip was 49.9%, 52.1% and 53.7% for 200bp, 500bp and 1kbp DNA fragments, respectively. The extracted DNA fragments exhibited compatibility with downstream enzymatic reactions, for example PCR. The chip was also used to extract DNA fragments with specific size range from sheared genomic DNA and demonstrated similar performance to that using traditional gel cutting method. The whole assay can finish in 32min, 6 times faster than traditional method. Copyright © 2016 Elsevier B.V. All rights reserved.

  13. On-Chip Testing Schemes of Through-Silicon-Vias (TSVs in 3D Stacked ICs

    Directory of Open Access Journals (Sweden)

    Shadi MS. Harb

    2017-07-01

    Full Text Available This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs in 3D ICs technology. 3D Gunning Transceiver Logic (GTL I/O testing is proposed to characterize the performance of 3D TSVs in high speed applications. The GTL testing circuit will fire different data patterns at different frequencies to characterize the transient performance of TSVs. In addition, Different testing schemes based on an oscillation ring testing methodology are proposed to detect TSVs faults such as stuck-at, open, slope and delay degradation, and severe crosstalk TSVs coupling. A parallel ring-based oscillator test structure is proposed and simulated based on a high performance fully tunable electrical circuit pi-model where a single and coupled TSVs with ground-signal-ground (GSG and ground-signal-signal-ground (GSSG 3D vias configurations are used as a test vehicle for 3D interconnect characterization and test. Simulation results are presented using the Keysight/Agilent Advance Design System (ADS and a standard 0.25 µm CMOS process.

  14. Easy simulation and design of on-chip inductors in standard CMOS processes

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jørgensen, Allan

    1998-01-01

    This paper presents an approach to CMOS inductor modelling, that allow easy simulation in SPICE-like simulators. A number of test results are presented concerning optimal center hole, inductor area, wire spacing and self-inductance. Finally a comprehensive design guide is provided on how to design...... close-to-optimal inductors without the use of electromagnetic simulators...

  15. An analog CMOS chip set for neural networks with arbitrary topologies

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1993-01-01

    implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b...

  16. Performance evaluation of a fully depleted monolithic pixel detector chip in 150 nm CMOS technology

    International Nuclear Information System (INIS)

    Obermann, Theresa

    2017-06-01

    The depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a (fully) depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and highly resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, developed in a 150 nm process on a highly resistive n-type wafer of 50 μm thickness, were characterized. The prototypes have 352 square pixels of 40 μm pitch and a small n-well charge collection node with very low capacitance of 5 fF (n + -implantation size: 5 μm x 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part). The characterization of the prototypes demonstrates the proof of principle of the concept. Prior to irradiation the prototypes show a signal from a minimum ionizing particle ranging from 2400 e - to 3000 e - while the noise is 30 e - due to the low capacitance. After the irradiation of the prototypes with neutrons up to a fluence of 5 x 10 14 neutrons/cm 2 the performance suffers from the radiation damage leading to a signal of 1000 e - and a higher noise of 60 e - due to the increase of the leakage current. The detection efficiency of the prototypes reduces from 94 % to 26 % after the fluence of 5 x 10 14 particles/cm 2 . Due to the small fill factor the detection efficiency shows are strong dependence on the position within the pixel after irradiation. Thus the DMAPS concept with low fill factor can be used for precise vertex reconstruction in High Energy Physics experiments without severe performance loss up to moderate fluences (< 1 x 10 14 particles/cm 2 ). The expected particle fluences inside of the volume of the upgrade of the ATLAS pixel detector exceed this limit. However, possible applications could be at future linear collider (ILC or CLIC) experiments and B-factories where the low material budget

  17. A 94 GHz CMOS based oscillator transmitter with an on-chip meandered dipole antenna

    KAUST Repository

    Cheema, Hammad M.

    2015-10-26

    A miniaturized 94 GHz oscillator transmitter in 65nm CMOS is presented. An extremely small silicon foot-print of 0.25mm2 is achieved through meandering of the top-metal dipole antenna, conjugate matching between the oscillator and the antenna without impedance matching elements and efficient placement of the oscillator circuit within the antenna. The antenna demonstrates bandwidth of 90 to 99 GHz (10%) and a gain of -6dBi. The use of parasitic aware antenna-circuit code-sign strategy results in an accurate measured oscillation frequency of 94.1 GHz. The oscillator exhibits a measured output power of -25 dBm, phase noise of -88 dBc/Hz at 1 MHz offset and consumes 8.4mW from a 1V supply. © 2015 IEEE.

  18. Radiation effects in a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors

    International Nuclear Information System (INIS)

    Brucker, G.J.; Heagerty, W.

    1976-01-01

    This paper presents the results obtained from total dose and transient radiation tests on a CMOS/SOS/Al-Gate D/A converter and on-chip diagnostic transistors. Samples were irradiated by cobalt-60 gamma rays under worst-case conditions, and by 10-MeV electron pulses of 50-ns and 4.4-μs duration. Devices were fabricated with three different insulators; the two discussed here are standard wet oxide and a pyrogenic oxide. Test transistors on the D/A chips made it possible to diagnose the failure modes of the converter and to evaluate some special designs. These consisted of standard edge p- and n-channel transistors, edgeless units, edgeless tetrode transistors, and an edgeless type transmission gate with a diode clamp from substrate to gate. The total dose results indicate that the pyrogenic oxide increased the failure dose of the operational amplifier portion of the converter from 10 3 rads (Si) to 2 x 10 6 rads (Si); however, the sample and hold failed after exposure to a low level of 10 3 rads (Si). Test devices indicated this to be due to the radiation-induced leakage current of the transmission gate which discharges the sample and hold capacitor. The diode clamp decreased the threshold voltage shifts and the leakage currents. The edgeless devices improved the device performance because of a more abrupt turn-on. Narrow-pulse test data indicated that the edgeless units produced less photocurrent than the edge units by about a factor of three to four. Converter upset levels are less than or equal to 10 9 rads/s due to precision requirements which make a few millivolt transients untenable

  19. A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

    International Nuclear Information System (INIS)

    Santos, D.M.; Dow, S.F.; Flasck, J.M.; Levi, M.E.

    1996-01-01

    Phase-locked loops have been employed in the past to obtain sub-nanosecond time resolution in high energy physics and nuclear science applications. An alternative solution based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Mueller C-element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multichannel, time-to-digital converter (TDC) targeted for one specific frequency. The two circuits, DLL and TDC, are implemented in CMOS 1.2 microm and 0.8 microm technologies, respectively. Test results show a timing jitter of less than 30 ps for the DLL circuit and less than 190 ps integral and differential nonlinearity for the TDC circuit

  20. Investigation of CMOS Multiplexer Jet Matrix Addressing and Micro-Droplets within a Printhead Chip

    Directory of Open Access Journals (Sweden)

    Jian-Chiun Liou

    2017-11-01

    Full Text Available In this study, we demonstrate and investigate a new droplet injection design. We create a thermal inkjet (TIJ printhead using an application-specific integrated circuit system and bulk micromachining technology (microelectromechanical systems. We design inkjet printhead chips with a new structure and investigate their properties. For the new structure, the integration of complementary metal-oxide-semiconductors (MOSs and enhancement-mode devices, as well as power switches and a TIJ heater transducer, enables logic functions to be executed on-chip. This capability is used in the proposed design to address individual jets with even fewer input lines than in matrix addressing. A high number of jets (at least 896 can be addressed with only 11 input lines. E1 (Enable 1 and E2 (Enable 2 are set up dependently, and they have the ability to reverse their signals in relation to each other (i.e., if E1 is disabled, E2 is enabled and vice versa. The E1 and E2 signals each service 448 jets. If one of the MOSs is turned on, then it corresponds to a power line with a similar function. If an addressing gate terminal of the other MOS has a discharge action, then we can control a different heater to generate heating bubbles in the jet inks. The operating frequency for addressing these measurements is 18 kHz in normal mode, 26 kHz in draft mode, and 16 kHz in best mode.

  1. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

    International Nuclear Information System (INIS)

    Feng Peng; Zhang Qi; Wu Nanjian

    2011-01-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma—delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm 2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is −10.7 dBm/−8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is −0.6 °C/0.5 °C (−1.0 °C/1.2 °C) in the operating range from 5 to 15 °C in high resolution mode (−30 to 50 °C in low resolution mode). The resolution of the sensor achieves 0.02 °C (0.18 °C) in high (low) resolution mode. (semiconductor integrated circuits)

  2. Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

    Energy Technology Data Exchange (ETDEWEB)

    Krzyżanowska, A. [AGH-UST, Cracow; Deptuch, G. W. [Fermilab; Maj, P. [AGH-UST, Cracow; Gryboś, P. [AGH-UST, Cracow; Szczygieł, R. [AGH-UST, Cracow

    2017-08-01

    This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operation of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.

  3. Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2013-08-01

    Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

  4. On-chip skin color detection using a triple-well CMOS process

    Science.gov (United States)

    Boussaid, Farid; Chai, Douglas; Bouzerdoum, Abdesselam

    2004-03-01

    In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

  5. Low-Noise CMOS Circuits for On-Chip Signal Processing in Focal-Plane Arrays

    Science.gov (United States)

    Pain, Bedabrata

    The performance of focal-plane arrays can be significantly enhanced through the use of on-chip signal processing. Novel, in-pixel, on-focal-plane, analog signal-processing circuits for high-performance imaging are presented in this thesis. The presence of a high background-radiation is a major impediment for infrared focal-plane array design. An in-pixel, background-suppression scheme, using dynamic analog current memory circuit, is described. The scheme also suppresses spatial noise that results from response non-uniformities of photo-detectors, leading to background limited infrared detector readout performance. Two new, low-power, compact, current memory circuits, optimized for operation at ultra-low current levels required in infrared-detection, are presented. The first one is a self-cascading current memory that increases the output impedance, and the second one is a novel, switch feed-through reducing current memory, implemented using error-current feedback. This circuit can operate with a residual absolute -error of less than 0.1%. The storage-time of the memory is long enough to also find applications in neural network circuits. In addition, a voltage-mode, accurate, low-offset, low-power, high-uniformity, random-access sample-and-hold cell, implemented using a CCD with feedback, is also presented for use in background-suppression and neural network applications. A new, low noise, ultra-low level signal readout technique, implemented by individually counting photo-electrons within the detection pixel, is presented. The output of each unit-cell is a digital word corresponding to the intensity of the photon flux, and the readout is noise free. This technique requires the use of unit-cell amplifiers that feature ultra-high-gain, low-power, self-biasing capability and noise in sub-electron levels. Both single-input and differential-input implementations of such amplifiers are investigated. A noise analysis technique is presented for analyzing sampled

  6. Design and results from the APV25, a deep sub-micron CMOS front-end chip for the CMS tracker

    CERN Document Server

    French, M J; Morrissey, Q R; Neviani, A; Turchetta, R; Fulcher, J R; Hall, G; Noah, E; Raymond, M; Cervelli, G; Moreira, P; Marseguerra, G

    2001-01-01

    The APV25 is a 128-channel analogue pipeline chip for the readout of silicon microstrip detectors in the CMS tracker at the LHC. Each channel comprises a low noise amplifier, a 192-cell analogue pipeline and a deconvolution readout circuit. Output data are transmitted on a single differential current output via an analogue multiplexer. The chip is fabricated in a standard 0.25 mu m CMOS process to take advantage of the radiation tolerance, lower noise and power, and high circuit density, Experimental characterisation of this circuit shows full functionality and good performance both in pre- and post- irradiation (20 Mrad) conditions. The measured noise is significantly reduced compared to earlier APV versions. A description of the design and results from measurements prior to irradiation are presented. (9 refs).

  7. Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50 micron pitch

    CERN Document Server

    Bellazzini, R; Minuti, M; Baldini, L; Brez, A; Cavalca, F; Latronico, L; Omodei, N; Massai, M M; Sgro, C; Costa, E; Krummenacher, P S F; De Oliveira, R

    2006-01-01

    We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50 micron pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and two poly-silicon layers of a 0.18 micron VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The ve...

  8. An On-Chip interconnect and protocol stack for multiple communication paradigms and programming models

    NARCIS (Netherlands)

    Hansson, A.; Goossens, Kees

    2009-01-01

    A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication

  9. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  10. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  11. Effect of gamma irradiation on leakage current in CMOS read-out chips for the ATLAS upgrade silicon strip tracker at the HL-LHC

    CERN Document Server

    Stucci, Stefania Antonia; Lynn, Dave; Kierstead, James; Kuczewski, Philip; van Nieuwenhuizen, Gerrit J; Rosin, Guy; Tricoli, Alessandro

    2017-01-01

    The increase of the leakage current of NMOS transistors in detector readout chips in certain 130 nm CMOS technologies during exposure to ionising radiation needs special consideration in the design of detector systems, as this can result in a large increase of the supply current and power dissipation. As part of the R&D; program for the upgrade of the ATLAS inner detector tracker for the High Luminosity upgrade of the LHC at CERN, a dedicated set of irradiations have been carried out with the $^60$Co gamma-ray source at the Brookhaven National Laboratory. Measurements will be presented that characterise the increase in the digital leakage current in the 130 nm-technology ABC130 readout chips. The variation of the current as a function of time and total ionising dose has been studied under various conditions of dose rate, temperature and power applied to the chip. The range of variation of dose rates and temperatures has been set to be close to those expected at the High Luminosity LHC, i.e. in the range 0...

  12. A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

    Directory of Open Access Journals (Sweden)

    Chia-Hua Ho

    2012-03-01

    Full Text Available This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs in the conventional Complementary Metal-Oxide Semiconductor (CMOS-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH and sensitive deoxyribonucleic acid (DNA detection ability (100 pM at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window. The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  13. A CMOS-compatible poly-Si nanowire device with hybrid sensor/memory characteristics for System-on-Chip applications.

    Science.gov (United States)

    Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

    2012-01-01

    This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically V(th)-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady V(th) adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  14. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Orit Skorka

    2011-04-01

    Full Text Available Technologies to fabricate integrated circuits (IC with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  15. Design and fabrication of vertically-integrated CMOS image sensors.

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  16. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  17. IRRADIATION MEASUREMENTS ON THE 0.25 micro m CMOS PIXEL READOUT TEST CHIP BY A 14 MEV NEUTRON FACILITY

    CERN Document Server

    Barbera, R; CERN. Geneva; Palmeri, A; Pappalardo, G S; Riggi, F; Di Liberto, S; Meddi, F; Sestito, S; Loi, D; Angelone, M; Badalà, A; Pillon, M

    2000-01-01

    ALICE-ITS-2000-24   Abstract   A test facility station with 14 MeV neutrons was arranged at the FNG-ENEA Laboratory in Frascati (Italy) for the characterization with respect to radiation tolerance of the prototype pixel readout chips in 0.25 m m IBM technology done in edgeless design. This facility could allow to test both the readout chips and the pilot chips for the pixel readout system. In fact, both ASICs will have to survive at the same radiation level foreseen for the innermost layer (r = 4 cm) of the Inner Tracker System (ITS) in the LHC-ALICE experiment. Two test chips were exposed to an overall flux of 1.3 x 1012 14 MeV neutrons/cm2, which is larger than the expected neutron flux in ALICE during 10 years data taking. No variation in the parameters defining the chip functionality (analog and digital currents, linearity, shapes of the signal, efficiency) was observed.

  18. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  19. Single-chip ring resonator-based 1 x 8 optical beam forming network in CMOS-compatible waveguide technology

    NARCIS (Netherlands)

    Zhuang, L.; Roeloffzen, C.G.H.; Heideman, Rene; Borreman, A.; Meijerink, Arjan; van Etten, Wim

    2007-01-01

    Optical ring resonators (ORRs) are good candidates to provide continuously tunable delay in optical beam forming networks (OBFNs) for phased array antenna systems. Delay and splitting/combining elements can be integrated on a single optical chip to form an OBFN. A state-of-the-art ring resonator-

  20. Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond

    NARCIS (Netherlands)

    Snoeys, W.; Burns, M.; Campbell, M.; Cantatore, E.; Cencelli, V.; Dinapoli, R.; Heijne, E.; Jarron, P.; Lamanna, P.; Minervini, D.; Morel, M.; O'shea, V.; Quiquempoix, V.; San Segundo Bello, D.; van Koningsveld, B.; Wyllie, K.

    The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these

  1. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

    CERN Document Server

    Snoeys, W; Burns, M; Campbell, M; Cantatore, E; Carrer, N; Casagrande, L; Cavagnoli, A; Dachs, C; Di Liberto, S; Formenti, F; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Letheren, M F; Marchioro, A; Martinengo, P; Meddi, F; Mikulec, B; Morando, M; Morel, M; Noah, E; Paccagnella, A; Ropotar, I; Saladino, S; Sansen, Willy; Santopietro, F; Scarlassara, F; Segato, G F; Signe, P M; Soramel, F; Vannucci, Luigi; Vleugels, K

    2000-01-01

    A new pixel readout prototype has been developed at CERN for high- energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 mu m CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad-1.7 Mrad depending on the type of radiation. 10 keV X-rays, /sup 60/Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed. (20 refs).

  2. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  3. Integrated tunable CMOS laser.

    Science.gov (United States)

    Creazzo, Timothy; Marchena, Elton; Krasulick, Stephen B; Yu, Paul K L; Van Orden, Derek; Spann, John Y; Blivin, Christopher C; He, Lina; Cai, Hong; Dallesasse, John M; Stone, Robert J; Mizrahi, Amit

    2013-11-18

    An integrated tunable CMOS laser for silicon photonics, operating at the C-band, and fabricated in a commercial CMOS foundry is presented. The III-V gain medium section is embedded in the silicon chip, and is hermetically sealed. The gain section is metal bonded to the silicon substrate creating low thermal resistance into the substrate and avoiding lattice mismatch problems. Optical characterization shows high performance in terms of side mode suppression ratio, relative intensity noise, and linewidth that is narrow enough for coherent communications.

  4. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  5. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  6. Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

    Directory of Open Access Journals (Sweden)

    Al Al

    2015-01-01

    Full Text Available Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ-comparator, the encoder and the parallel input serial output (PISO register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

  7. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  8. Characterization, integration and reliability of HfO{sub 2} and LaLuO{sub 3} high-κ/metal gate stacks for CMOS applications

    Energy Technology Data Exchange (ETDEWEB)

    Nichau, Alexander

    2013-07-15

    The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-κ/metal gate stacks. LaLuO{sub 3} and HfO{sub 2} are investigated as two different high-κ oxides on silicon in conjunction with TiN as the metal electrode. LaLuO{sub 3} and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO{sub 3} is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO{sub 3} on germanium, germanate formation is shown. LaLuO{sub 3} is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70μA/μm at 1μm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO{sub 3} in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-κ oxide. Different approaches are presented for a further EOT reduction with LaLuO{sub 3} and HfO{sub 2}. Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO{sub 2} gate stacks is scalable below 1 nm by the use of thinned interfacial SiO{sub 2}. The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the

  9. Characterization, integration and reliability of HfO2 and LaLuO3 high-κ/metal gate stacks for CMOS applications

    International Nuclear Information System (INIS)

    Nichau, Alexander

    2013-01-01

    The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-κ/metal gate stacks. LaLuO 3 and HfO 2 are investigated as two different high-κ oxides on silicon in conjunction with TiN as the metal electrode. LaLuO 3 and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO 3 is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO 3 on germanium, germanate formation is shown. LaLuO 3 is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70μA/μm at 1μm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO 3 in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-κ oxide. Different approaches are presented for a further EOT reduction with LaLuO 3 and HfO 2 . Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO 2 gate stacks is scalable below 1 nm by the use of thinned interfacial SiO 2 . The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the gate electrode to decrease the EOT of HfO 2 gate stacks

  10. George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

    Science.gov (United States)

    Chen, Tze-Chiang (T. C.)

    The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

  11. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  12. Design of an ultra-compact electro-absorption modulator comprised of a deposited TiN/HfO₂/ITO/Cu stack for CMOS backend integration.

    Science.gov (United States)

    Zhu, Shiyang; Lo, G Q; Kwong, D L

    2014-07-28

    An ultra-compact electro-absorption (EA) modulator operating around 1.55-μm telecom wavelengths is proposed and theoretically investigated. The modulator is comprised of a stack of TiN/HfO2modulator inserted in the 400-nm × 340-nm-Si stripe waveguide exhibits insertion loss of 2.9 (3.2) dB and modulation depth of 19.9 (15.2) dB for the TE (TM) mode. The modulation speed is ~11 GHz, limited by the RC delay, and the energy consumption is ~0.4 pJ/bit. The stack can also be deposited on a low-index-contrast waveguide such as Si3N4. For example, a 4-μm-long EA modulator inserted in an 800-nm × 600-nm-Si3N4 stripe waveguide exhibits insertion loss of 6.3 (3.5) dB and modulation depth of 16.5 (15.8) dB for the TE (TM) mode. The influences of the ITO, TiN, HfO2 layers and the beneath dielectric core, as well as the processing tolerance, on the performance of the proposed EA modulator are systematically investigated.

  13. A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

    Science.gov (United States)

    Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

    2016-01-01

    This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

  14. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  15. CCD and CMOS sensors

    Science.gov (United States)

    Waltham, Nick

    The charge-coupled device (CCD) has been developed primarily as a compact image sensor for consumer and industrial markets, but is now also the preeminent visible and ultraviolet wavelength image sensor in many fields of scientific research including space-science and both Earth and planetary remote sensing. Today"s scientific or science-grade CCD will strive to maximise pixel count, focal plane coverage, photon detection efficiency over the broadest spectral range and signal dynamic range whilst maintaining the lowest possible readout noise. The relatively recent emergence of complementary metal oxide semiconductor (CMOS) image sensor technology is arguably the most important development in solid-state imaging since the invention of the CCD. CMOS technology enables the integration on a single silicon chip of a large array of photodiode pixels alongside all of the ancillary electronics needed to address the array and digitise the resulting analogue video signal. Compared to the CCD, CMOS promises a more compact, lower mass, lower power and potentially more radiation tolerant camera.

  16. Qualification method for a 1 MGy-tolerant front-end chip designed in 65 nm CMOS for the read-out of remotely operated sensors and actuators during maintenance in ITER

    Energy Technology Data Exchange (ETDEWEB)

    Verbeeck, Jens, E-mail: jens.verbeeck@esat.kuleuven.be [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Cao, Ying [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Van Uffelen, Marco; Casellas, Laura Mont; Damiani, Carlo; Morales, Emilio Ruiz; Santana, Roberto Ranz [Fusion for Energy (F4E), c/Josep, no. 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Meek, Richard; Haist, Bernhard [Oxford Technologies Ltd. (OTL), 7 Nuffield Way, Abingdon OX14 1RL (United Kingdom); Hamilton, David [ITER Organisation (IO), Route de Vinon-sur-Verdon, CS 90 046, 13067 St. Paul les Durance Cedex (France); Steyaert, Michiel [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KU Leuven, ESAT, Advanced Integrated Sensing Lab (AdvISe), Kleinhoefstraat 4, 2440 Geel (Belgium)

    2015-10-15

    This paper describes the radiation qualification procedure for a 1 MGy-tolerant Application Specific Integrated Circuit (ASIC) developed in 65 nm CMOS technology. The chip is intended for the read-out of electrical signals of sensors and actuators during maintenance in ITER. First the general working principle of the ASIC is shown. The developed IC allows to read-out, condition and digitize multiple low bandwidth (<10 kHz) sensors. In addition the IC is able to multiplex the digitized sensor signals. To comply with ITER-relevant constraints an adapted radiation qualification procedure has been proposed. The radiation-qualification procedure describes the test criteria and test conditions of the developed ASICs, which are also compared with COTS alternatives, to meet the stringent qualification procedures for electronics exposed to radiation in ITER.

  17. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  18. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  19. CMOS Active Pixel Sensor Technology and Reliability Characterization Methodology

    Science.gov (United States)

    Chen, Yuan; Guertin, Steven M.; Pain, Bedabrata; Kayaii, Sammy

    2006-01-01

    This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.

  20. A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2007-01-01

    Abstract A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. A capacitive pre-emphasis transmitter lowers the power and increases the bandwidth. The receiver uses DFE with a power-efficient continuous-time feedback filter. The transceiver, fabricated in 1.2V 90nm

  1. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  2. Stacking technology for a space constrained microsystem

    DEFF Research Database (Denmark)

    Heschel, Matthias; Kuhmann, Jochen Friedrich; Bouwstra, Siebe

    1998-01-01

    In this paper we present a stacking technology for an integrated packaging of an intelligent transducer which is formed by a micromachined silicon transducer and an integrated circuit chip. Transducer and circuitry are stacked on top of each other with an intermediate chip in between. The bonding...

  3. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  4. Transmission Lines in CMOS: An Explorative Study

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Kreienkamp, R.; Ellermeyer, T.; Langmann, U.

    On-chip transmission line modelling and design become increasingly important as frequencies are continuously going up. This paper explores possibilities to implement transmission lines on CMOS ICs via coupled coplanar strips. EM-field simulations with SONNET are used to estimate important

  5. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  6. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  7. Analog floating-point BiCMOS sampling chip and architecture of the BaBar CsI calorimeter front-end electronics system at the SLAC B-Factory

    Energy Technology Data Exchange (ETDEWEB)

    Haller, G.M.; Freytag, D.R. [Stanford Univ., CA (United States). Stanford Linear Accelerator Center

    1996-06-01

    The design and implementation of an analog floating-point sampling integrated circuit for the BaBar detector at the SLAC B-Factory is described. The CARE (Custom Auto-Range Encoding) circuit is part of an 18-bit dynamic range sampling system with a 4-MHz waveform digitization rate for the CsI calorimeter. The architecture and methodology of the system are described. The CARE integrated circuit receives dual-range (gain of 1 and 32) 13-bit signals from the 18-bit range preamplifiers mounted directly on the CsI crystals and converts the input at a rate of 4 MHz to an auto-range floating-point format with a 10-bit analog mantissa and 2 digital range bits (for 4 ranges). Additional functions integrated on the chip are averaging and selection circuitry for signals originating from two independent diodes per crystal and range-selection overwrite circuitry. The circuit will be mounted within the detector structure and thus low power dissipation is essential. The circuit has been fabricated in a 1.2 {micro}m BiCMOS process with polysilicon-to-polysilicon capacitors and polysilicon resistors. Measurement results are presented. One complete CARE channel dissipates 25 mW.

  8. Statistical Analysis of the Random Telegraph Noise in a 1.1 μm Pixel, 8.3 MP CMOS Image Sensor Using On-Chip Time Constant Extraction Method.

    Science.gov (United States)

    Chao, Calvin Yi-Ping; Tu, Honyih; Wu, Thomas Meng-Hsiu; Chou, Kuo-Yu; Yeh, Shang-Fu; Yin, Chin; Lee, Chih-Lin

    2017-11-23

    A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model.

  9. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  10. Monolithic CMOS pixel detector for international linear collider ...

    Indian Academy of Sciences (India)

    the vertex detector elements and thus existing CCDs are not adequate. New CCD architectures are ... sizes of the 292 detector elements (chips) are summarized in tables 1 and 2. The baseline time structure of ... an R&D contract, we developed a conceptual design for a monolithic CMOS device. (chip) that achieves the ILC ...

  11. On-chip data communication

    NARCIS (Netherlands)

    Schinkel, Daniel

    2011-01-01

    On-chip data communication is an active research area, as interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Especially for global interconnects that have to span large parts of a chip, there is an increasing gap between transistor speed and

  12. Design of a 1-chip IBM-3270 protocol handler

    NARCIS (Netherlands)

    Spaanenburg, L.

    1989-01-01

    The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be compiled and optimized into a 35 mm**2 chip in 4

  13. A safety monitoring system for taxi based on CMOS imager

    Science.gov (United States)

    Liu, Zhi

    2005-01-01

    CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

  14. Fundamental performance differences of CMOS and CCD imagers: part V

    Science.gov (United States)

    Janesick, James R.; Elliott, Tom; Andrews, James; Tower, John; Pinter, Jeff

    2013-02-01

    Previous papers delivered over the last decade have documented developmental progress made on large pixel scientific CMOS imagers that match or surpass CCD performance. New data and discussions presented in this paper include: 1) a new buried channel CCD fabricated on a CMOS process line, 2) new data products generated by high performance custom scientific CMOS 4T/5T/6T PPD pixel imagers, 3) ultimate CTE and speed limits for large pixel CMOS imagers, 4) fabrication and test results of a flight 4k x 4k CMOS imager for NRL's SoloHi Solar Orbiter Mission, 5) a progress report on ultra large stitched Mk x Nk CMOS imager, 6) data generated by on-chip sub-electron CDS signal chain circuitry used in our imagers, 7) CMOS and CMOSCCD proton and electron radiation damage data for dose levels up to 10 Mrd, 8) discussions and data for a new class of PMOS pixel CMOS imagers and 9) future CMOS development work planned.

  15. Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

    KAUST Repository

    Chen, Min Cheng

    2014-12-01

    Stackable 3DFETs such as FinFET using hybrid Si/MoS2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) Ion,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device Vth are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics. © 2014 IEEE.

  16. A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

    Directory of Open Access Journals (Sweden)

    Chih-Ting Lin

    2012-08-01

    Full Text Available A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

  17. A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.

    Science.gov (United States)

    Chen, Zhiyuan; Law, Man-Kay; Mak, Pui-In; Martins, Rui P

    2017-02-01

    In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 × efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 V in gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- [Formula: see text] CMOS technology and occupies an active area of 1.54 [Formula: see text]. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 [Formula: see text] from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 [Formula: see text] at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.

  18. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  19. Implementing inverted master-slave 3D semiconductor stack

    Science.gov (United States)

    Coteus, Paul W.; Hall, Shawn A.; Takken, Todd E.

    2016-03-08

    A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.

  20. A CMOS high speed imaging system design based on FPGA

    Science.gov (United States)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  1. Algebraic stacks

    Indian Academy of Sciences (India)

    generally, any fiber product) is not uniquely defined: it is only defined up to unique isomorphism. ..... Fiber product. Given two morphisms f1 : F1 ! G, f2 : F2 ! G, we define a new stack. F1 آG F2 (with projections to F1 and F2) as follows. The objects are triples ًX1; X2; ق ..... In fact, any Artin stack F can be defined in this fashion.

  2. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  3. Monolithic integration of a plasmonic sensor with CMOS technology

    Science.gov (United States)

    Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

    2017-02-01

    Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

  4. Low energy CMOS for space applications

    Science.gov (United States)

    Panwar, Ramesh; Alkalaj, Leon

    1992-01-01

    The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

  5. Chip, Chip, Hooray!

    Science.gov (United States)

    Kelly, Susan

    2001-01-01

    Presents a science laboratory using different brands of potato chips in which students test their oiliness, size, thickness, saltiness, quality, and cost, then analyze the results to determine the best chip. Gives a brief history of potato chips. (YDS)

  6. Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

    KAUST Repository

    Hussain, Aftab M.

    2016-12-01

    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

  7. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  8. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  9. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    digital base-band processing on the same chip. Presently, only few examples of CMOS used for RF front-end circuits have been presented by academia, and so far no commercial products exist. The approach has been to do a CMOS block by block replacement of the blocks in traditional transceiver architectures......This paper is a survey paper presenting the Nordic CONFRONT project and reporting some results from the group at CIE/DTU, Denmark. The objective of the project is to demonstrate the feasibility of sub-micron CMOS for the realisation of RF front-end circuits operating at frequencies in the 1...... circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  10. CMOS sensors for atmospheric imaging

    Science.gov (United States)

    Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

    2017-09-01

    Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

  11. An introduction to deep submicron CMOS for vertex applications

    CERN Document Server

    Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, P; Santiard, Jean-Claude; Snoeys, W; Wyllie, K

    2001-01-01

    Microelectronics has become a key enabling technology in the development of tracking detectors for High Energy Physics. Deep submicron CMOS is likely to be extensively used in all future tracking systems. Radiation tolerance in the Mrad region has been achieved and complete readout chips comprising many millions of transistors now exist. The choice of technology is dictated by market forces but the adoption of deep submicron CMOS for tracking applications still poses some challenges. The techniques used are reviewed and some of the future challenges are discussed.

  12. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  13. Algebraic stacks

    Indian Academy of Sciences (India)

    truct the 'moduli stack', that captures all the information that we would like in a fine moduli space. ..... the fine moduli space), it has the property that for any family W of vector bundles (i.e. W is a vector bundle over B ...... the etale topology is finer: V is a 'small enough open subset' because the square root can be defined on it.

  14. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  15. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  16. RF CMOS reliability simulations

    NARCIS (Netherlands)

    Sasse, G.T.; Acar, M.; Kuper, F.G.; Schmitz, Jurriaan

    2008-01-01

    We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events.

  17. Hyperspectral CMOS imager

    Science.gov (United States)

    Jerram, P. A.; Fryer, M.; Pratlong, J.; Pike, A.; Walker, A.; Dierickx, B.; Dupont, B.; Defernez, A.

    2017-11-01

    CCDs have been used for many years for Hyperspectral imaging missions and have been extremely successful. These include the Medium Resolution Imaging Spectrometer (MERIS) [1] on Envisat, the Compact High Resolution Imaging Spectrometer (CHRIS) on Proba and the Ozone Monitoring Instrument operating in the UV spectral region. ESA are also planning a number of further missions that are likely to use CCD technology (Sentinel 3, 4 and 5). However CMOS sensors have a number of advantages which means that they will probably be used for hyperspectral applications in the longer term. There are two main advantages with CMOS sensors: First a hyperspectral image consists of spectral lines with a large difference in intensity; in a frame transfer CCD the faint spectral lines have to be transferred through the part of the imager illuminated by intense lines. This can lead to cross-talk and whilst this problem can be reduced by the use of split frame transfer and faster line rates CMOS sensors do not require a frame transfer and hence inherently will not suffer from this problem. Second, with a CMOS sensor the intense spectral lines can be read multiple times within a frame to give a significant increase in dynamic range. We will describe the design, and initial test of a CMOS sensor for use in hyperspectral applications. This device has been designed to give as high a dynamic range as possible with minimum cross-talk. The sensor has been manufactured on high resistivity epitaxial silicon wafers and is be back-thinned and left relatively thick in order to obtain the maximum quantum efficiency across the entire spectral range

  18. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  19. AN ARRAY OF MONOLITHIC FBAR-CMOS OSCILLATORS FOR MASS-SENSING APPLICATIONS.

    Science.gov (United States)

    Johnston, M L; Kymissis, I; Shepard, K L

    2009-06-21

    We present a monolithic, solidly-mounted CMOS-FBAR oscillator array for mass sensing applications. Thin-film bulk acoustic resonators (FBAR) are an effective platform for sensitive biological and chemical detection, where their high operating frequencies make them many times more sensitive than a quartz crystal microbalance. By monolithic integration with CMOS drive circuitry, we aim to overcome the spatial limitations of externally-coupled resonators to build dense sensor arrays without specialized fabrication techniques. The sensors in this work are constructed in a 6 × 4 array atop a 0.18μm CMOS active substrate, and mass sensitivity comparable to off-chip FBAR sensors is demonstrated.

  20. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    OpenAIRE

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2011-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and ...

  1. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

    Science.gov (United States)

    Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

    2012-01-11

    Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

  2. Gain Enhanced On-Chip Folded Dipole Antenna Utilizing Artificial Magnetic Conductor at 94 GHz

    KAUST Repository

    Nafe, Mahmoud

    2017-09-05

    On-chip antennas suffer from low gain values and distorted radiation patterns due to lossy and high permittivity Si substrate. An ideal solution would be to isolate the lossy Si substrate from the antenna through a Perfect Electric Conductor (PEC) ground plane, however the typical CMOS stack up which has multiple metal layers embedded in a thin oxide layer does not permit this. In this work, an Artificial Magnetic Conductor (AMC) reflecting surface has been utilized to isolate the Si substrate from the antenna. Contrary to the previous reports, the AMC structure is completely embedded in the thin oxide layer with the ground plane above the Si substrate. In this approach, the AMC surface acts for the first time as both a reflector and a silicon shield. As a result the antenna radiation pattern is not distorted and its gain is improved by 8 dB. The fabricated prototype demonstrates good impedance and radiation characteristics.

  3. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  4. Smart CMOS image sensor for lightning detection and imaging

    OpenAIRE

    Rolando, Sébastien; Goiffon, Vincent; Magnan, Pierre; Corbière, Franck; Molina, Romain; Tulet, Michel; Bréart-de-Boisanger, Michel; Saint-Pé, Olivier; Guiry, Saïprasad; Larnaudie, Franck; Leone, Bruno; Perez-Cuevas, Leticia; Zayer, Igor

    2013-01-01

    We present a CMOS image sensor dedicated to lightning detection and imaging. The detector has been designed to evaluate the potentiality of an on-chip lightning detection solution based on a smart sensor. This evaluation is performed in the frame of the predevelopment phase of the lightning detector that will be implemented in the Meteosat Third Generation Imager satellite for the European Space Agency. The lightning detection process is performed by a smart detector combining an in-pixel fra...

  5. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  6. Low-power high-accuracy micro-digital sun sensor by means of a CMOS image sensor

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.

    2013-01-01

    A micro-digital sun sensor (?DSS) is a sun detector which senses a satellite’s instant attitude angle with respect to the sun. The core of this sensor is a system-on-chip imaging chip which is referred to as APS+. The APS+ integrates a CMOS active pixel sensor (APS) array of 368×368??pixels , a

  7. First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

    International Nuclear Information System (INIS)

    Traversi, Gianluca; Bulgheroni, Antonio; Caccia, Massimo; Jastrzab, Marcin; Manghisoni, Massimo; Pozzati, Enrico; Ratti, Lodovico; Re, Valerio

    2009-01-01

    In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. In this work, the experimental characterization of the SDR0 chip, including data from radioactive source ( 55 Fe) tests, will be presented.

  8. Interconnects and On-Chip Data Communication Techniques

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria

    Global on-chip communication is rapidly becoming a speed and power bottleneck in CMOS circuits. In this paper, a ‘mixed-signal’ approach is taken to analyze on-chip interconnects and it is investigated how data-rates can be improved. It is shown that complex signaling schemes such as OFDM and CDMA

  9. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  10. A Neuron- and a Synapse Chip for Artificial Neural Networks

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1992-01-01

    A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where...... the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 ¿m CMOS process for test purposes. The propagation time through...... the synapse and neuron chips is less than 4 ¿s and the weight matrix has a 10 bit resolution....

  11. Design of a Highly Dependable Beamforming Chip

    NARCIS (Netherlands)

    Kerkhoff, Hans G.; Zhang, Xiao; Zhang, X.

    As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip is designed using 64 reconfigurable Xentium tile processors. A functional dependability analysis for this application was carried out

  12. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    International Nuclear Information System (INIS)

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  13. Development of an integrated CMOS detector for radon activity measurement and neutron dosimetry

    Energy Technology Data Exchange (ETDEWEB)

    Higueret, S.; Trocme, M.; Husson, D.; Le, T.D.; Nourreddine, A. [Universite Louis Pasteur (ULP), CNRS, IN2P3, Institut Pluridisciplinaire Hubert Curien (IPHC-DRS), 67 - Strasbourg (France)

    2008-07-01

    The development of pixel CMOS sensors for particle tracking in high energy physics has led to promising applications for dosimetry. We present the last results in electronic monitoring of atmospheric radon with the new system-on-chip AlphaRad, as well as highly efficient detection of fast neutrons with a mega-pixel Active Pixel Sensor of the MIMOSA generation.

  14. III-V/Ge channel MOS device technologies in nano CMOS era

    Science.gov (United States)

    Takagi, Shinichi; Zhang, Rui; Suh, Junkyo; Kim, Sang-Hyeon; Yokoyama, Masafumi; Nishi, Koichi; Takenaka, Mitsuru

    2015-06-01

    CMOS utilizing high-mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III-V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III-V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III-V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III-V MOS device technologies, we mainly address the gate stack technology, III-V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III-V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III-V/Ge channels.

  15. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2005-01-01

    On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard...

  16. Micromachined high-performance RF passives in CMOS substrate

    International Nuclear Information System (INIS)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-01-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

  17. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications

    Directory of Open Access Journals (Sweden)

    Elnaz Ghodsevali

    2017-04-01

    Full Text Available A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µV rms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter.

  18. Miniaturized FDDA and CMOS Based Potentiostat for Bio-Applications.

    Science.gov (United States)

    Ghodsevali, Elnaz; Morneau-Gamache, Samuel; Mathault, Jessy; Landari, Hamza; Boisselier, Élodie; Boukadoum, Mounir; Gosselin, Benoit; Miled, Amine

    2017-04-10

    A novel fully differential difference CMOS potentiostat suitable for neurotransmitter sensing is presented. The described architecture relies on a fully differential difference amplifier (FDDA) circuit to detect a wide range of reduction-oxidation currents, while exhibiting low-power consumption and low-noise operation. This is made possible thanks to the fully differential feature of the FDDA, which allows to increase the source voltage swing without the need for additional dedicated circuitry. The FDDA also reduces the number of amplifiers and passive elements in the potentiostat design, which lowers the overall power consumption and noise. The proposed potentiostat was fabricated in 0.18 µm CMOS, with 1.8 V supply voltage. The device achieved 5 µA sensitivity and 0.99 linearity. The input-referred noise was 6.9 µV rms and the flicker noise was negligible. The total power consumption was under 55 µW. The complete system was assembled on a 20 mm × 20 mm platform that includes the potentiostat chip, the electrode terminals and an instrumentation amplifier for redox current buffering, once converted to a voltage by a series resistor. the chip dimensions were 1 mm × 0.5 mm and the other PCB components were off-chip resistors, capacitors and amplifiers for data acquisition. The system was successfully tested with ferricyanide, a stable electroactive compound, and validated with dopamine, a popular neurotransmitter.

  19. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  20. Emulation of high-frequency substrate noise generation in CMOS digital circuits

    Science.gov (United States)

    Shimazaki, Shunsuke; Taga, Shota; Makita, Tetsuya; Azuma, Naoya; Miura, Noriyuki; Nagata, Makoto

    2014-01-01

    A noise emulator is based on the capacitor charging modeling and generates power and substrate noises expected in a CMOS digital integrated circuit. An off-chip near-magnetic-field sensor indirectly characterizes the distribution of clock timing and the adjustability of skews within on-chip digital circuits. An on-chip noise monitor captures power and substrate noise waveforms and evaluates noise frequency components in a wide frequency bandwidth. A 65 nm CMOS prototype demonstrated power and substrate noise generation in a variety of operating scenarios of digital integrated circuits. Power noise generation emulated at 125 MHz exhibits the enhancements of high-order harmonic components after deskewing at a timing resolution of 37.8 ps, as is specifically seen in more than 10 dB enlargement of the substrate noise component at 2.1 GHz.

  1. A 0.18 {mu}m CMOS single-inductor single-stage quadrature frontend for GNSS receiver

    Energy Technology Data Exchange (ETDEWEB)

    Li Bing; Zhuang Yiqi; Han Yeqi; Xing Xiaoling; Li Zhenrong; Long Qiang, E-mail: waxmax@126.com [Key Laboratory of the Ministry of Education for Wide Bandgap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2011-09-15

    This paper presents an improved merged architecture for a low-IF GNSS receiver frontend, where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO. Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented. The gain plan and noise figure are discussed. The phase noise, quadrature accuracy and power consumption are improved. The test chip is fabricated though a 0.18 {mu}m RF CMOS process. The measured noise figure is 5.4 dB on average, with a gain of 43 dB and a IIP3 of -39 dBm. The measured phase noise is better than -105 dBc/Hz at 1 MHz offset. The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications. (semiconductor integrated circuits)

  2. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  3. Speckle Interferometry of Close Visual Binaries with the ZW Optical ASI 224MC CMOS Camera

    Science.gov (United States)

    Genet, Russell; Rowe, David; Ashcraft, Clif; Wen, Sam; Jones, Gregory; Schillings, Benoit; Harshaw, Richard; Ray, Jimmy; Hass, Jacob

    2016-03-01

    Rapid improvements have been made in the design and manufacture of high-speed CMOS cameras with low read noise. Scientific CMOS (sCMOS) cameras appeared on the market a few years ago with performance approaching that of EMCCD cameras. Although sCMOS cameras remained expensive (typically over 10,000), there was hope that the cost of the low-noise CMOS chips would be reduced, allowing them to be incorporated into low-cost, mass-market cameras. This happened recently. A team at Sony developed a low read-noise (less than 1 electron) chip that has been incorporated in a camera made by ZWO that only costs 359 US, and just weighs 120 g (4.2 oz). Benoit Shillings obtained one of these cameras, placed it on his 0.5-meter telescope in San Jose, California, and, using a list of targets supplied by Richard Harshaw, quickly demonstrated that the new ZWO camera could observe remarkably faint and close double stars.

  4. Radiation-hard silicon gate bulk CMOS cell family

    International Nuclear Information System (INIS)

    Gibbon, C.F.; Habing, D.H.; Flores, R.S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved

  5. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  6. A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

    Science.gov (United States)

    Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

    2012-08-01

    An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

  7. Wireless Interconnects for Intra-chip & Inter-chip Transmission

    Science.gov (United States)

    Narde, Rounak Singh

    With the emergence of Internet of Things and information revolution, the demand of high performance computing systems is increasing. The copper interconnects inside the computing chips have evolved into a sophisticated network of interconnects known as Network on Chip (NoC) comprising of routers, switches, repeaters, just like computer networks. When network on chip is implemented on a large scale like in Multicore Multichip (MCMC) systems for High Performance Computing (HPC) systems, length of interconnects increases and so are the problems like power dissipation, interconnect delays, clock synchronization and electrical noise. In this thesis, wireless interconnects are chosen as the substitute for wired copper interconnects. Wireless interconnects offer easy integration with CMOS fabrication and chip packaging. Using wireless interconnects working at unlicensed mm-wave band (57-64GHz), high data rate of Gbps can be achieved. This thesis presents study of transmission between zigzag antennas as wireless interconnects for Multichip multicores (MCMC) systems and 3D IC. For MCMC systems, a four-chips 16-cores model is analyzed with only four wireless interconnects in three configurations with different antenna orientations and locations. Return loss and transmission coefficients are simulated in ANSYS HFSS. Moreover, wireless interconnects are designed, fabricated and tested on a 6'' silicon wafer with resistivity of 55O-cm using a basic standard CMOS process. Wireless interconnect are designed to work at 30GHz using ANSYS HFSS. The fabricated antennas are resonating around 20GHz with a return loss of less than -10dB. The transmission coefficients between antenna pair within a 20mm x 20mm silicon die is found to be varying between -45dB to -55dB. Furthermore, wireless interconnect approach is extended for 3D IC. Wireless interconnects are implemented as zigzag antenna. This thesis extends the work of analyzing the wireless interconnects in 3D IC with different

  8. Digital Switching CMOS Power Amplifier for Multiband and Multimode Handset Applications

    Science.gov (United States)

    Nakatani, Toshifumi

    This thesis is directed towards the development of a digitally-assisted radio frequency power amplifier (RF PA) which is one of the potential solutions to realize a multiband and multimode transmitter with high efficiency for handset applications. To improve efficiency and linearity in multiple conditions, PA circuits and digital signal processing (DSP) algorithms are co-designed. In the dissertation, a proposed architecture employs a current-mode class-D (CMCD) configuration for high efficiency, and a polar modulation scheme driven by digital inputs. Detail design, fabrication and experimental results are given for circuit implementation and DSP of this architecture. First, a multiband watt-class complementary metal-oxide-semiconductor (CMOS) PA is demonstrated using 0.15 um CMOS integrated circuits (ICs), off-chip inductor and balun. To obtain high breakdown voltage, stacked field effect transistors (FETs) are used. The CMCD PA is tuned by band-switching capacitors, operating in the 0.7-1.8 GHz frequency band. The overall efficiencies of 27.1 / 25.6 % are achieved at 30.2 / 28.9 dBm CW output powers and 0.85 / 1.75 GHz carrier frequencies, respectively. Next, to achieve wide output power dynamic range, an architecture consisting of small segmented unti-cells is introduced into the PA, where multiple three-state unit-cells are used and the state of each unit-cell is controlled to provide a specific output power. The overall dynamic ranges are expanded to approximately 90 dB and 85 dB at and 0.85 / 1.75 GHz, respectively. The dissertation then presents digital modulation algorithms. The digital compensation techniques are developed to maintain linearity of an envelope modulator of the polar transmitter. A new digital pulse width modulation algorithm is also shown to partially suppress spurious signals associated with the digital input envelope signal. When wideband code-division multiple access (WCDMA) modulation is implemented, spur suppression of 9-10 dB is

  9. CMOS capacitive biosensors for highly sensitive biosensing applications.

    Science.gov (United States)

    Chang, An-Yu; Lu, Michael S-C

    2013-01-01

    Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

  10. An RF Power Amplifier in a Digital CMOS Process

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck; Fallesen, Carsten

    2002-01-01

    A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor...... is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA...... is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3 pi /8-8PSK) modulated signal....

  11. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  12. Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Fang Tang

    2014-01-01

    Full Text Available Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

  13. 60 GHz 5-bit digital controlled phase shifter in a digital 40 nm CMOS technology without ultra-thick metals

    NARCIS (Netherlands)

    Gao, H.; Ying, K.; Matters-Kammerer, M.K.; Harpe, P.; Wang, B.; Liu, B.; Serdijn, W.A.; Baltus, P.G.M.

    2016-01-01

    A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to

  14. Deploying OpenStack

    CERN Document Server

    Pepple, Ken

    2011-01-01

    OpenStack was created with the audacious goal of being the ubiquitous software choice for building public and private cloud infrastructures. In just over a year, it's become the most talked-about project in open source. This concise book introduces OpenStack's general design and primary software components in detail, and shows you how to start using it to build cloud infrastructures. If you're a developer, technologist, or system administrator familiar with cloud offerings such as Rackspace Cloud or Amazon Web Services, Deploying OpenStack shows you how to obtain and deploy OpenStack softwar

  15. A CMOS smart temperature and humidity sensor with combined readout.

    Science.gov (United States)

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  16. HV-CMOS detectors in BCD8 technology

    Science.gov (United States)

    Andreazza, A.; Castoldi, A.; Ceriale, V.; Chiodini, G.; Citterio, M.; Darbo, G.; Gariano, G.; Gaudiello, A.; Guazzoni, C.; Joshi, A.; Liberali, V.; Passadore, S.; Ragusa, F.; Ruscino, E.; Sbarra, C.; Shrimali, H.; Sidoti, A.; Stabile, A.; Yadav, I.; Zaffaroni, E.

    2016-11-01

    This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm2. To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

  17. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  18. Reliability in CMOS IC processing

    Science.gov (United States)

    Shreeve, R.; Ferrier, S.; Hall, D.; Wang, J.

    1990-01-01

    Critical CMOS IC processing reliability monitors are defined in this paper. These monitors are divided into three categories: process qualifications, ongoing production workcell monitors, and ongoing reliability monitors. The key measures in each of these categories are identified and prioritized based on their importance.

  19. A CMOS Switched Transconductor Mixer

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Louwsma, S.M.; Wienk, Gerhardus J.M.; Nauta, Bram

    A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled

  20. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    of wafer through-holes the main challenge is to protect the CMOS wafer during etching. In the case of DRIE etching of the wafer through-holes the main challenges are proper insulation of the wafer through-holes, conformal deposition of via metal and structuring of the deposited metal. This thesis discusses...

  1. CMOS Analog IC Design: Fundamentals

    DEFF Research Database (Denmark)

    Bruun, Erik

    This book is intended for use as the main textbook for an introductory course in CMOS analog integrated circuit design. It is aimed at electronics engineering students who have followed basic courses in mathematics, physics, circuit theory, electronics and signal processing. It takes the students...

  2. OpenStack essentials

    CERN Document Server

    Radez, Dan

    2015-01-01

    If you need to get started with OpenStack or want to learn more, then this book is your perfect companion. If you're comfortable with the Linux command line, you'll gain confidence in using OpenStack.

  3. Mastering OpenStack

    CERN Document Server

    Khedher, Omar

    2015-01-01

    This book is intended for system administrators, cloud engineers, and system architects who want to deploy a cloud based on OpenStack in a mid- to large-sized IT infrastructure. If you have a fundamental understanding of cloud computing and OpenStack and want to expand your knowledge, then this book is an excellent checkpoint to move forward.

  4. Readout circuit design of the retina-like CMOS image sensor

    Science.gov (United States)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  5. Spark protection layers for CMOS pixel anode chips in MPGDs

    NARCIS (Netherlands)

    Bilevych, Y.; Bilevych, Y.; Blanco Carballo, V.M.; Chefdeville, M.A.; Colas, P.; Delagnes, E.; Fransen, M.; van der Graaff, H.; Koppert, W.J.C.; Melai, J.; Salm, Cora; Schmitz, Jurriaan; Timmermans, J.; Timmermans, J.; Wyrsch, N.

    2011-01-01

    In this work we have investigated the functioning of high resistivity amorphous silicon and silicon-rich nitride layers as a protection against discharges in Micro-Patterned Gaseous Detectors (MPGDs).When the anode is protected by a high resistivity layer, discharge signals are limited in charge. A

  6. Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits

    OpenAIRE

    K.Srilakshmi; Y.Syamala; A.Suvir Vikram

    2013-01-01

    Power dissipation in high performance systems requi res more expensive packaging. In this situation, lo w power VLSI design has assumed great importance as a n active and rapidly developing field. As the densi ty and operating speed of CMOS VLSI chip increases, st atic power dissipation becomes more significant. Th is is due to the leakage current when the transistor i s off this is threshold voltage dependent. This can be ...

  7. Performance and Irradiation Tests of the 0.3$\\mu$m CMOS TDC for the ATLAS MDT

    OpenAIRE

    Arai, Y; Fukuda, M; Emura, T

    1999-01-01

    ATLAS Muon TDC test-element group chip (AMTTEG) was developed and tested to confirm the performance of critical circuits of the TDC and measure radiation tolerance of the process. The chip was fabricated in a 0.3 mm CMOS Gate-Array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a Co60 source, and neutron irradiation, using PROSPERO reactor in France, were also ...

  8. Flip chip assembly of thinned chips for hybrid pixel detector applications

    International Nuclear Information System (INIS)

    Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

    2014-01-01

    There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

  9. Packetizing OCP Transactions in the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    The scaling of CMOS technology causes a widening gap between the performance of on-chip communication and computation. This calls for a communication-centric design flow. The MANGO network-on-chip architecture enables globally asynchronous locally synchronous (GALS) system-on-chip design, while...... facilitating IP reuse by standard socket access points. Two types of services are available: connection-less best-effort routing and connection-oriented guaranteed service (GS) routing. This paper presents the core-centric programming model for establishing and using GS connections in MANGO. We show how OCP...

  10. On-chip electrochromic micro display for a disposable bio-sensor chip

    Science.gov (United States)

    Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

    2017-12-01

    This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

  11. CMOS optimization for radiation hardness

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Fossum, J.G.

    1975-01-01

    Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

  12. Chip-size-packaged silicon microphones [for hearing instruments

    DEFF Research Database (Denmark)

    Müllenborn, Matthias; Rombach, Pirmin; Klein, Udo

    2001-01-01

    The first results of silicon microphones that are completely batch-packaged and integrated with signal conditioning circuitry in a chip stack are discussed. The chip stack is designed to be directly mounted into a system, such as a hearing instrument, without further single-chip handling or wire...... consumption of about 50 μW in the near future, thereby living up to the tight specifications of microphones for hearing instruments. Other potential applications include mobile phones, headsets, and wearable computers, in which space is constrained....

  13. CMOS Image Sensor with a Built-in Lane Detector

    Directory of Open Access Journals (Sweden)

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  14. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  15. Drop casting of stiffness gradients for chip integration into stretchable substrates

    International Nuclear Information System (INIS)

    Naserifar, Naser; LeDuc, Philip R; Fedder, Gary K

    2017-01-01

    Stretchable electronics have demonstrated promise within unobtrusive wearable systems in areas such as health monitoring and medical therapy. One significant question is whether it is more advantageous to develop holistic stretchable electronics or to integrate mature CMOS into stretchable electronic substrates where the CMOS process is separated from the mechanical processing steps. A major limitation with integrating CMOS is the dissimilar interface between the soft stretchable and hard CMOS materials. To address this, we developed an approach to pattern an elastomeric polymer layer with spatially varying mechanical properties around CMOS electronics to create a controllable material stiffness gradient. Our experimental approach reveals that modifying the interfaces can increase the strain failure threshold up to 30% and subsequently decreases delamination. The stiffness gradient in the polymer layer provides a safe region for electronic chips to function under a substrate tensile strain up to 150%. These results will have impacts in diverse applications including skin sensors and wearable health monitoring systems. (paper)

  16. A compact PE memory for vision chips

    Science.gov (United States)

    Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

    2014-09-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

  17. A compact PE memory for vision chips

    International Nuclear Information System (INIS)

    Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

    2014-01-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

  18. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  19. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    Science.gov (United States)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  20. High-speed DSP applied to a multimedia chip set

    Science.gov (United States)

    Chester, David B.

    1996-06-01

    The hardware portion of the Harris Semiconductor Personal Computer Multimedia System is a 5 chip set which implements, in conjunction with a host processor and associated software and firmware, a complete H.320 video teleconferencing capability over ISDN 2B lines. The chip is comprised of a PAL/NTSC Video Encoder, a PAL/NTSC Video Decoder, a Video Codec, a Bus Interface and Audio Processor chip, and an Audio Codec. All 5 chips in the set are implemented in a 0.5 or 0.6 micron CMOS process. Each of the chips implement digital signal processing algorithms of varying levels of complexity and flexibility. These levels range from standard interpolation and decimation filter implementations found on the Audio Codec to dual programmable digital signal processor cores found on the Bus Interface and Audio Processor chip. A top level description of the chip set architecture is presented, along with a functional description of a typical video teleconferencing system based on this chip set. This is followed by a top level description of the various digital signal processing architectures and approaches used in the individual chips in the chip set.

  1. Pulse processing CMOS ASIC for Si-strip/PIN detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2004-01-01

    The paper presents the design of an 8-channel front-end signal processing ASIC for Si-strip detectors with capacitance from 1 to 40 pf. Each channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a track-hold stage. The channel outputs are connected to an analog multiplexer which is controlled by an external clock for serial readout. The peaking time is adjustable over 500 ns-1.2us in steps by external control. There is provision for changing gain and polarity. The circuit has a power dissipation of 16 mw per channel and is designed to fabricate in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 5 by 5 mm with target package 48 pin CLCC. (author)

  2. Power pulsing of the CMOS sensor Mimosa 26

    International Nuclear Information System (INIS)

    Kuprash, Oleg

    2013-01-01

    Mimosa 26 is a monolithic active pixel sensor developed by IPHC (Strasbourg) and IRFU (Saclay) as a prototype for the ILC vertex detector studies. The resolution requirements for the ILC tracking detector are very extreme, demanding very low material in the detector, thus only air cooling can be considered. Power consumption has to be reduced as far as possible. The beam structure of the ILC allows the possibility of power pulsing: only for about the 1 ms long bunch train full power is required, and during the 199 ms long pauses between the bunch trains the power can be reduced to a minimum. Not being adapted for the power pulsing, the sensor shows in laboratory tests a good performance under power pulsing. The power pulsing allows to significantly reduce the heating of the chip and divides power consumption approximately by a factor of 6. In this report a summary of power pulsing studies using the digital readout of Mimosa 26 is given. -- Highlights: • First power pulsing studies using digital readout of Mimosa 26 CMOS sensor were done. • Fake hit rates under power pulsing conditions and under normal conditions were compared. • The measurements demonstrate that there is so far no showstopper to operate CMOS pixel sensors in power pulsing mode

  3. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  4. An integrated CMOS high data rate transceiver for video applications

    Science.gov (United States)

    Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

    2012-07-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  5. Power pulsing of the CMOS sensor Mimosa 26

    Energy Technology Data Exchange (ETDEWEB)

    Kuprash, Oleg, E-mail: oleg.kuprash@desy.de

    2013-12-21

    Mimosa 26 is a monolithic active pixel sensor developed by IPHC (Strasbourg) and IRFU (Saclay) as a prototype for the ILC vertex detector studies. The resolution requirements for the ILC tracking detector are very extreme, demanding very low material in the detector, thus only air cooling can be considered. Power consumption has to be reduced as far as possible. The beam structure of the ILC allows the possibility of power pulsing: only for about the 1 ms long bunch train full power is required, and during the 199 ms long pauses between the bunch trains the power can be reduced to a minimum. Not being adapted for the power pulsing, the sensor shows in laboratory tests a good performance under power pulsing. The power pulsing allows to significantly reduce the heating of the chip and divides power consumption approximately by a factor of 6. In this report a summary of power pulsing studies using the digital readout of Mimosa 26 is given. -- Highlights: • First power pulsing studies using digital readout of Mimosa 26 CMOS sensor were done. • Fake hit rates under power pulsing conditions and under normal conditions were compared. • The measurements demonstrate that there is so far no showstopper to operate CMOS pixel sensors in power pulsing mode.

  6. Stack filter classifiers

    Energy Technology Data Exchange (ETDEWEB)

    Porter, Reid B [Los Alamos National Laboratory; Hush, Don [Los Alamos National Laboratory

    2009-01-01

    Just as linear models generalize the sample mean and weighted average, weighted order statistic models generalize the sample median and weighted median. This analogy can be continued informally to generalized additive modeels in the case of the mean, and Stack Filters in the case of the median. Both of these model classes have been extensively studied for signal and image processing but it is surprising to find that for pattern classification, their treatment has been significantly one sided. Generalized additive models are now a major tool in pattern classification and many different learning algorithms have been developed to fit model parameters to finite data. However Stack Filters remain largely confined to signal and image processing and learning algorithms for classification are yet to be seen. This paper is a step towards Stack Filter Classifiers and it shows that the approach is interesting from both a theoretical and a practical perspective.

  7. A system-on-chip digital pH meter for use in a wireless diagnostic capsule

    OpenAIRE

    Hammond, P.A.; Ali, D.; Cumming, D.R.S.

    2005-01-01

    This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is de...

  8. Optimization of CMOS active pixels for high resolution digital radiography

    International Nuclear Information System (INIS)

    Kim, Young Soo

    2007-02-01

    characteristics. The size of these pixels is 100 μm x 100 μm. The test chip was fabricated using ETRI 0.8 μm (2P/2M) standard CMOS process. It was found that the epitaxial type pixels have similar noise level compared to nonepitaxial type, and the noise of diffusion type pixel is larger than for a well type pixel on the same substrate type at the output node. But, at the input node, the n diffusion /p epitaxial /p substrate type pixel has the maximum SNR compared to other types. Secondly, the size of the designed pixels is 20 μm for high resolution X-ray imaging. In these test structures, AMIS 0.5 μm (2P/3M) CMOS standard process are used for fabrication and different values for design parameters (including optimum design parameters extracted from the developed model) are considered. The results of the noise measurement are agreed with model calculation and the optimum values of in-pixel components can be extracted using developed noise model.

  9. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    . The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  10. On Stack Reconstruction Problem

    Directory of Open Access Journals (Sweden)

    V. D. Аkeliev

    2009-01-01

    Full Text Available The paper describes analytical investigations that study relation of fuel combustion regimes with concentration values of sulphur anhydride in flue gases and acid dew point. Coefficients of convective heat transfer at internal and external surfaces of stacks have been determined in the paper. The paper reveals the possibility to reconstruct stacks while using gas discharging channel made of composite material on the basis of glass-reinforced plastic which permits to reduce thermo-stressed actions on reinforced concrete and increase volume of released gases due to practically two-fold reduction of gas-dynamic pressure losses along the pipe length.

  11. Laser pulse stacking method

    Science.gov (United States)

    Moses, E.I.

    1992-12-01

    A laser pulse stacking method is disclosed. A problem with the prior art has been the generation of a series of laser beam pulses where the outer and inner regions of the beams are generated so as to form radially non-synchronous pulses. Such pulses thus have a non-uniform cross-sectional area with respect to the outer and inner edges of the pulses. The present invention provides a solution by combining the temporally non-uniform pulses in a stacking effect to thus provide a more uniform temporal synchronism over the beam diameter. 2 figs.

  12. CMOS integrated switching power converters

    CERN Document Server

    Villar-Pique, Gerard

    2011-01-01

    This book describes the structured design and optimization of efficient, energy processing integrated circuits. The approach is multidisciplinary, covering the monolithic integration of IC design techniques, power electronics and control theory. In particular, this book enables readers to conceive, synthesize, design and implement integrated circuits with high-density high-efficiency on-chip switching power regulators. Topics covered encompass the structured design of the on-chip power supply, efficiency optimization, IC-compatible power inductors and capacitors, power MOSFET switches and effi

  13. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  14. po_stack_movie

    DEFF Research Database (Denmark)

    2009-01-01

    po_stack® er et reolsystem, hvis enkle elementer giver stor flexibilitet, variation og skulpturel virkning. Elementerne stables og forskydes frit, så reolens rum kan vendes til begge sider, være åbne eller lukkede og farvekombineres ubegrænset. Reolen kan let ombygges, udvides eller opdeles, når ...

  15. Learning SaltStack

    CERN Document Server

    Myers, Colton

    2015-01-01

    If you are a system administrator who manages multiple servers, then you know how difficult it is to keep your infrastructure in line. If you've been searching for an easier way, this book is for you. No prior experience with SaltStack is required.

  16. Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

    Directory of Open Access Journals (Sweden)

    Min Yoon

    2016-01-01

    Full Text Available We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency CMOS (fT/fmax=120/140 GHz technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

  17. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  18. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  19. A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

    Science.gov (United States)

    Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

    2018-04-05

    Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

  20. Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

    Science.gov (United States)

    Wei, Liping; Yan, Wenrong; Ho, Derek

    2017-12-04

    Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

  1. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  2. 0.8 /spl mu/m CMOS implementation of weighted-order statistic image filter based on cellular neural network architecture.

    Science.gov (United States)

    Kowalski, J

    2003-01-01

    In this paper, a very large scale integration chip of an analog image weighted-order statistic (WOS) filter based on cellular neural network (CNN) architecture for real-time applications is described. The chip has been implemented in CMOS AMS 0.8 /spl mu/m technology. CNN-based filter consists of feedforward nonlinear template B operating within the window of 3 /spl times/ 3 pixels around the central pixel being filtered. The feedforward nonlinear CNN coefficients have been realized using programmable nonlinear coupler circuits. The WOS filter chip allows for processing of images with 300 pixels horizontal resolution. The resolution can be increased by cascading of the chips. Experimental results of basic circuit building blocks measurements are presented. Functional tests of the chip have been performed using a special test setup for PAL composite video signal processing. Using the setup real images have been filtered by WOS filter chip under test.

  3. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    Science.gov (United States)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  4. Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

    Science.gov (United States)

    Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

    2017-05-01

    The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

  5. A 0.18μm CMOS low-power radiation sensor for UWB wireless transmission

    International Nuclear Information System (INIS)

    Crepaldi, M; Demarchi, D; Gabrielli, A; Khan, A; Pikhay, E; Roizin, Y; Villani, G; Zhang, Z

    2012-01-01

    The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm 2 , the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

  6. A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

    International Nuclear Information System (INIS)

    Zhou Qianneng; Wang Yongsheng; Lai Fengchang

    2009-01-01

    A capacitor-free CMOS low-dropout (LDO) regulator for system-on-chip (SoC) applications is presented. By adopting AC-boosting and active-feedback frequency compensation (ACB-AFFC), the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 x 472 μm 2 . Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.

  7. Reliability of high mobility SiGe channel MOSFETs for future CMOS applications

    CERN Document Server

    Franco, Jacopo; Groeseneken, Guido

    2014-01-01

    Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and pr...

  8. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...... distortion is not achievable with CMOS current mirrors...

  9. Nanopore-CMOS Interfaces for DNA Sequencing.

    Science.gov (United States)

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-08-06

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

  10. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  11. Energy Expenditure of Sport Stacking

    Science.gov (United States)

    Murray, Steven R.; Udermann, Brian E.; Reineke, David M.; Battista, Rebecca A.

    2009-01-01

    Sport stacking is an activity taught in many physical education programs. The activity, although very popular, has been studied minimally, and the energy expenditure for sport stacking is unknown. Therefore, the purposes of this study were to determine the energy expenditure of sport stacking in elementary school children and to compare that value…

  12. OpenStack cloud security

    CERN Document Server

    Locati, Fabio Alessandro

    2015-01-01

    If you are an OpenStack administrator or developer, or wish to build solutions to protect your OpenStack environment, then this book is for you. Experience of Linux administration and familiarity with different OpenStack components is assumed.

  13. Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

    Directory of Open Access Journals (Sweden)

    Shojan P. Pavunny

    2014-03-01

    Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

  14. CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

    Science.gov (United States)

    Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

    2018-04-01

    Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

  15. Implementation and low speed test of ultra-fast interface circuits for Josephson-CMOS hybrid memories

    Energy Technology Data Exchange (ETDEWEB)

    Fujiwara, K.; Miyakawa, H.; Yoshikawa, N.; Feng, Y.; Whiteley, S.R.; Van Duzer, T

    2003-10-15

    We have been developing Josephson-CMOS hybrid memories where high-density CMOS devices are used as storage cells. One of the key components in the system is the interface circuit, which amplifies the signal from the SFQ circuits into voltage level processible in the CMOS circuits at high-speed. In this paper, we have implemented the ultra-fast interface circuit, which is composed of a Josephson driver and a Josephson-CMOS hybrid amplifier. The propagation delay of the ultra-fast interface circuit is estimated to be about 60 ps assuming a 2.5 kA/cm{sup 2} Nb process and a 0.6 {mu}m CMOS process. A low speed test results of the interface circuit shows that it amplifies the input voltage of 80 {mu}V to 0.9 V. We have also investigated their propagation delay and output voltage swing assuming the spread of the critical current in the Josephson stack.

  16. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  17. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  18. Latch-up in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Estreich, D.B.; Dutton, R.W.

    1978-04-01

    An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

  19. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  20. Crosstalk in modern on-chip interconnects a FDTD approach

    CERN Document Server

    Kaushik, B K; Patnaik, Amalendu

    2016-01-01

    The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the ...

  1. Low-loss CMOS copper plasmonic waveguides at the nanoscale (Conference Presentation)

    Science.gov (United States)

    Fedyanin, Dmitry Y.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.; Volkov, Valentyn S.

    2016-05-01

    Implementation of optical components in microprocessors can increase their performance by orders of magnitude. However, the size of optical elements is fundamentally limited by diffraction, while miniaturization is one of the essential concepts in the development of high-speed and energy-efficient electronic chips. Surface plasmon polaritons (SPPs) are widely considered to be promising candidates for the next generation of chip-scale technology thanks to the ability to break down the fundamental diffraction limit and manipulate optical signals at the truly nometer scale. In the past years, a variety of deep-subwavelength plasmonic structures have been proposed and investigated, including dielectric-loaded SPP waveguides, V-groove waveguides, hybrid plasmonic waveguides and metal nanowires. At the same time, for practical application, such waveguide structures must be integrated on a silicon chip and be fabricated using CMOS fabrication process. However, to date, acceptable characteristics have been demonstrated only with noble metals (gold and silver), which are not compatible with industry-standard manufacturing technologies. On the other hand, alternative materials introduce enormous propagation losses due absorption in the metal. This prevents plasmonic components from implementation in on-chip nanophotonic circuits. In this work, we experimentally demonstrate for the first time that copper plasmonic waveguides fabricated in a CMOS compatible process can outperform gold waveguides showing the same level of mode confinement and lower propagation losses. At telecommunication wavelengths, the fabricated ultralow-loss deep-subwavelength hybrid plasmonic waveguides ensure a relatively long propagation length of more than 50 um along with strong mode confinement with the mode size down to lambda^2/70, which is confirmed by direct scanning near-field optical microscopy (SNOM) measurements. These results create the backbone for design and development of high

  2. Development of a 750x750 pixels CMOS imager sensor for tracking applications

    Science.gov (United States)

    Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

    2017-11-01

    Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on-chip

  3. Stack Caching Using Split Data Caches

    DEFF Research Database (Denmark)

    Nielsen, Carsten; Schoeberl, Martin

    2015-01-01

    In most embedded and general purpose architectures, stack data and non-stack data is cached together, meaning that writing to or loading from the stack may expel non-stack data from the data cache. Manipulation of the stack has a different memory access pattern than that of non-stack data, showing...... higher temporal and spatial locality. We propose caching stack and non-stack data separately and develop four different stack caches that allow this separation without requiring compiler support. These are the simple, window, and prefilling with and without tag stack caches. The performance of the stack...

  4. E-link A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication

    CERN Document Server

    Bonacini, S; Moreira, P

    2009-01-01

    The e-link, an electrical interface suitable for transmission of data over PCBs or electrical cables, within a distance of a few meters, at data rates up to 320 Mbit/s, is presented. The elink is targeted for the connection between the GigaBit Transceiver (GBTX) chip and the Front-End (FE) integrated circuits. A commercial component complying with the Scalable Low- Voltage Signaling (SLVS) electrical standard was tested and demonstrated a performance level compatible with our application. Test results are presented. A SLVS transmitter/receiver IP block was designed in 130 nm CMOS technology. A test chip was submitted for fabrication.

  5. 5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

    KAUST Repository

    Ouda, Mahmoud H.

    2013-04-17

    A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.

  6. Self-powered integrated systems-on-chip (energy chip)

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-04-23

    In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  7. Small-Delay Fault BIST in High-Speed Chip Interfaces

    NARCIS (Netherlands)

    Petre, O.; Kerkhoff, H.G.

    2004-01-01

    During the past years, due to the decrease of the minimum feature size in CMOS technology, the on-chip clock frequencies have increased dramatically ranging into the GHz domain. This increase has also pushed the need for higher data-transfer rates between these high-speed ICs, in order to optimize

  8. A Differential 4-Path Highly Linear Widely Tunable On-Chip Band-Pass Filter

    NARCIS (Netherlands)

    Ghaffari, A.; Klumperink, Eric A.M.; Nauta, Bram

    2010-01-01

    Abstract A passive switched capacitor RF band-pass filter with clock controlled center frequency is realized in 65nm CMOS. An off-chip transformer which acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity

  9. The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

    International Nuclear Information System (INIS)

    Baturitsky, M.A.; Yurenya, Yu.P.Yu.P.

    2002-01-01

    The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

  10. Fully Integrated, Low Drop-Out Linear Voltage Regulator in 180 nm CMOS

    DEFF Research Database (Denmark)

    Yosef-Hay, Yoni; Larsen, Dennis Øland; Llimos Muntal, Pere

    2017-01-01

    This paper presents a capacitor-free low dropout (LDO) linear regulator based on a dual loop topology. The regulator utilizes two feedback loops to satisfy the challenges of hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes....... The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0-100 pF capacitive load. The design has been taped out in a 0.18 µm CMOS process. The proposed regulator has a low component count, area of 0.012 mm2 and is suitable for system-on-chip integration...

  11. A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology

    Science.gov (United States)

    Mazza, G.; Rivetti, A.; Moreira, P.; Wyllie, K.; Soos, C.; Troska, J.; Gui, P.

    2012-01-01

    The GigaBit Transceiver (GBT) project aims at the design of a radiation tolerant chip set for high speed optical data transmission. The chipset includes the GigaBit Laser Driver (GBLD), a radiation tolerant ASIC designed in a standard CMOS 130 nm technology. The GBLD is a laser driver designed to work to up to 5 Gb/s and capable to drive both Vertical Cavity Surface Emitting Lasers (VCSELs) and Edge Emitting Lasers (EELs). The GBLD can provide a modulation current up to 24 mA and a bias current up to 43 mA with the pre-emphasis function to compensate for external capacitive load.

  12. Prototype Active Silicon Sensor in 150 nm HR-CMOS Technology for ATLAS Inner Detector Upgrade

    CERN Document Server

    Rymaszewski, Piotr; Breugnon, Patrick; Godiot, Stépahnie; Gonella, Laura; Hemperek, Tomasz; Hirono, Toko; Hügging, Fabian; Krüger, Hans; Liu, Jian; Pangaud, Patrick; Peric, Ivan; Rozanov, Alexandre; Wang, Anqing; Wermes, Norbert

    2016-01-01

    The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

  13. A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS

    DEFF Research Database (Denmark)

    Deleuran, Alexander N.; Lindbjerg, Nicklas; Pedersen, Martin K.

    2015-01-01

    A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration....... A current step load from 0-50 mA with a rise time of 1 µs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load....

  14. Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC

    Directory of Open Access Journals (Sweden)

    D. Arbet

    2014-09-01

    Full Text Available In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC based on digitally compensated input offset of the operational amplifier (OPAMP is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved.

  15. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    Havranek, Miroslav

    2014-09-01

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  16. DNA Chip

    Indian Academy of Sciences (India)

    Imagine a world without identity cards; no I-cards for the college or office or bank account or anything! All you are carrying is a small (say, 2cm x 2cm) 'DNA-chip', which has the whole of your genetic profile on it. Your identity cannot get more authentic than that. Imagine a world where marriages are not decided by matching ...

  17. Passive stack ventilation

    Energy Technology Data Exchange (ETDEWEB)

    Palmer, J.; Parkins, L.; Shaw, P.; Watkins, R. [Databuild, Birmingham (United Kingdom)

    1994-12-31

    The adequate ventilation of houses is essential for both the occupants and the building fabric. As air-tightness standards increase, background infiltration levels decrease and extra ventilation has to be designed into the building. Passive stack ventilation has many advantages - particularly when employed in low cost housing schemes -but it is essential that it performs satisfactorily. This paper give the results from monitoring two passive stack ventilation schemes. One scheme was a retrofit into refurbished local authority houses in which a package of energy efficiency measures had been taken and condensation had been a problem. The other series of tests were conducted on a new installation in a Housing Association development. Nine houses were monitored each of which had at least two passive vents. The results show air flow rates by the passive ducts equivalent to approximately 1 room air change per hour. The air flow in the ducts was influenced by both, internal to external temperature difference and wind speed and direction. (author)

  18. Asymmetric Flexible Supercapacitor Stack

    Directory of Open Access Journals (Sweden)

    Leela Mohana Reddy A

    2008-01-01

    Full Text Available AbstractElectrical double layer supercapacitor is very significant in the field of electrical energy storage which can be the solution for the current revolution in the electronic devices like mobile phones, camera flashes which needs flexible and miniaturized energy storage device with all non-aqueous components. The multiwalled carbon nanotubes (MWNTs have been synthesized by catalytic chemical vapor deposition technique over hydrogen decrepitated Mischmetal (Mm based AB3alloy hydride. The polymer dispersed MWNTs have been obtained by insitu polymerization and the metal oxide/MWNTs were synthesized by sol-gel method. Morphological characterizations of polymer dispersed MWNTs have been carried out using scanning electron microscopy (SEM, transmission electron microscopy (TEM and HRTEM. An assymetric double supercapacitor stack has been fabricated using polymer/MWNTs and metal oxide/MWNTs coated over flexible carbon fabric as electrodes and nafion®membrane as a solid electrolyte. Electrochemical performance of the supercapacitor stack has been investigated using cyclic voltammetry, galvanostatic charge-discharge, and electrochemical impedance spectroscopy.

  19. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  20. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  1. CMOS Transmitter using Pulse-Width Modulation Pre-Emphasis achieving 33dB Loss Compensation at 5-Gb/s

    OpenAIRE

    Schrader, J.H.R.; Klumperink, Eric A.M.; Visschers, J.L.; Nauta, Bram

    2005-01-01

    A digital transmitter pre-emphasis technique is presented that is based on pulse-width modulation, instead of finite impulse response (FIR) filtering. The technique fits well to future high-speed low-voltage CMOS processes. A 0.13 /spl mu/m CMOS transmitter achieves more than 5 Gb/s (2-PAM) over 25 m of standard RG-58U low-end coaxial copper cable. The test chip compensates for up to 33 dB of channel loss at the fundamental signaling frequency (2.5 GHz), which is the highest figure compared t...

  2. A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

    Science.gov (United States)

    Chen, Shuo-Mao; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lee, I. C.; Chiang, Yen-Ting

    2008-08-01

    A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the fT/fmax, respectively, which are 1000%, 200%, and 60% improvements in current gain, fT and fmax, respectively as compared to the LBJT reported previously.

  3. Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors.

    Science.gov (United States)

    Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

    2017-05-02

    Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components.

  4. Design and application of a metal wet-etching post-process for the improvement of CMOS-MEMS capacitive sensors

    International Nuclear Information System (INIS)

    Tsai, Ming-Han; Sun, Chih-Ming; Liu, Yu-Chia; Fang, Weileun; Wang, Chuanwei

    2009-01-01

    This study presents a process design methodology to improve the performance of a CMOS-MEMS gap-closing capacitive sensor. In addition to the standard CMOS process, the metal wet-etching approach is employed as the post-CMOS process to realize the present design. The dielectric layers of the CMOS process are exploited to form the main micro mechanical structures of the sensor. The metal layers of the CMOS process are used as the sensing electrodes and sacrificial layers. The advantages of the sensor design are as follows: (1) the parasitic capacitance is significantly reduced by the dielectric structure, (2) in-plane and out-of-plane sensing gaps can be reduced to increase the sensitivity, and (3) plate-type instead of comb-type out-of-plane sensing electrodes are available to increase the sensing electrode area. To demonstrate the feasibility of the present design, a three-axis capacitive CMOS-MEMS accelerometers chip is implemented and characterized. Measurements show that the sensitivities of accelerometers reach 11.5 mV G −1 (in the X-, Y-axes) and 7.8 mV G −1 (in the Z-axis), respectively, which are nearly one order larger than existing designs. Moreover, the detection of 10 mG excitation using the three-axis accelerometer is demonstrated for both in-plane and out-of-plane directions

  5. CMOS circuits for electromagnetic vibration transducers interfaces for ultra-low voltage energy harvesting

    CERN Document Server

    Maurath, Dominic

    2015-01-01

    Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100µW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over...

  6. A quadruple well CMOS MAPS prototype for the Layer0 of the SuperB SVT

    Science.gov (United States)

    Zucca, S.; Ratti, L.; Traversi, G.; Morsani, F.; Gabrielli, A.; Giorgi, F.

    2013-08-01

    The chip prototype Apsel4well, including monolithic active pixel sensors (MAPS), is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180 nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks of three transistor MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to a further improvement in terms of charge collection performance and radiation resistance. This work introduces the channel readout design features of the chip Apsel4well developed with the mentioned approach and shows results of device simulations of a 3×3 pixel matrix.

  7. A 10 MHz micropower CMOS front end for direct readout of pixel detectors

    International Nuclear Information System (INIS)

    Campbell, M.; Heijne, E.H.M.; Jarron, P.; Krummenacher, F.; Enz, C.C.; Declercq, M.; Vittoz, E.; Viertel, G.

    1990-01-01

    In the framework of the CERN-LAA project for detector R and D, a micropower circuit of 200 μmx200 μm with a current amplifier, a latched comparator and a digital memory element has been tested electrically and operated in connection with linear silicon detector arrays. The experimental direct-readout (DRO) chip comprises a matrix of 9x12 circuit cells and has been manufactured in a 3 μm CMOS technology. Particles and X-ray photons below 22 keV were detected, and thresholds can be set between 2000 and 20000 e - . The noise is less than 4 keV FWHM or 500 e - rms and the power dissipation per pixel element is 30 μW. The chip can be coupled to a detector matrix using bump bonding. (orig.)

  8. Instant BlueStacks

    CERN Document Server

    Judge, Gary

    2013-01-01

    Get to grips with a new technology, understand what it is and what it can do for you, and then get to work with the most important features and tasks. A fast-paced, example-based approach guide for learning BlueStacks.This book is for anyone with a Mac or PC who wants to run Android apps on their computer. Whether you want to play games that are freely available for Android but not your computer, or you want to try apps before you install them on a physical device or use it as a development tool, this book will show you how. No previous experience is needed as this is written in plain English

  9. An on-chip programmable instrumentation microsystem for gastrointestinal telemetry applications.

    Science.gov (United States)

    Wang, Lei; Hammond, Paul; Johannesson, Erik; Tang, Tong Boon; Astaras, Alexandros; Cumming, David R S; Beaumont, Steve P; Murray, Alan F; Cooper, Jonathan M

    2004-01-01

    We have developed an integrated circuit microsystem instrument using a design methodology akin to that for system-on-chip microelectronics. The microsystem is optimised for low-power gastrointestinal telemetry applications and includes mixed-signal sensor circuits, programmable digital system, a feedback clock control loop and RF circuits that were integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3 V CMOS process. Unintended signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes has been minimised. Tests show that the wireless instrument-on-chip worked as intended.

  10. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

    Directory of Open Access Journals (Sweden)

    Preethi Padmanabhan

    2018-02-01

    Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  11. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

    Science.gov (United States)

    Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

    2018-01-01

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

  12. CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

    CERN Document Server

    Aznar, Francisco; Calvo Lopez, Belén

    2013-01-01

    This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

  13. Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

    Science.gov (United States)

    Benoit, M.; Braccini, S.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Perić, I.; Rimoldi, M.; Ristić, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

    2018-02-01

    HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the 4th generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between 1× 1014 and 5× 1015 1-MeV- neq. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of 85 V. The sample irradiated to a fluence of 1× 1015 neq—a relevant value for a large volume of the upgraded tracker—exhibited 99.7% average hit efficiency. The results give strong evidence for the radiation tolerance of HV-CMOS sensors and their suitability as sensors for the experimental HL-LHC upgrades and future large-area silicon-based tracking detectors in high-radiation environments.

  14. CMOS Monolithic Active Pixel Sensors (MAPS): New ‘eyes’ for science

    Science.gov (United States)

    Turchetta, R.; Allport, P. P.; Casse, G.; Clark, A.; Crooks, J.; Evans, A.; Fant, A.; Faruqi, A. R.; French, M. J.; Henderson, R.; Morrissey, Q.; Prior, D.; Prydderch, M.; Velthuis, J. J.; Villani, G.; Waltham, N.; Willmore, B.; Willmore, P.

    2006-05-01

    Re-invented in the early 1990s on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology have slowly invaded the world of consumer imaging and are now on the edge of becoming the first technology in this field, previously dominated by Charge-Coupled Devices (CCD). Thanks to the advantages brought by the use of standard CMOS technology, MAPS have great potential in many areas including function integration, leading to the concept of a camera-on-a-chip, pixel size, random access to selected region-of-interest, low power, higher speed and radiation resistance. In many ways, MAPS have introduced a new way of doing imaging. Despite their success in the consumer arena, MAPS are still to make a definitive impact in the world of scientific imaging. This paper first briefly reviews the way radiation is detected by a CMOS sensor, before analysing the main noise source and its relationship with the full well capacity and the dynamic range. This paper will also show first examples of scientific results, obtained in the detection of low-energy electrons.

  15. GridPix: An integrated readout system for gaseous detectors with a pixel chip as anode

    Energy Technology Data Exchange (ETDEWEB)

    Graaf, Harry van der [NIKHEF, Kruislaan 409, 1098 SJ Amsterdam (Netherlands)], E-mail: vdgraaf@nikhef.nl

    2007-10-01

    GridPix is a gas-filled detector in which a Micro Pattern Gas Detector is combined with a CMOS pixel chip. In a next step, a procedure to construct a grid onto a Si wafer, using chip production technology ('wafer post-processing'), has been developed. Protection against discharges are under study, and an ageing test of a Micromegas chamber has been carried out, after verifying the chamber's proportionality at a very high dose rate. The GridPix detector can be applied as X-ray imaging device. With a drift gap of only 1 mm, GridPix could be well applied as radiation hard, low power, (and therefore) low-mass vertex (track) detector. New developments in CMOS pixel chips, forming the core of the detector, are presented.

  16. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  17. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  18. Assessing Elementary Algebra with STACK

    Science.gov (United States)

    Sangwin, Christopher J.

    2007-01-01

    This paper concerns computer aided assessment (CAA) of mathematics in which a computer algebra system (CAS) is used to help assess students' responses to elementary algebra questions. Using a methodology of documentary analysis, we examine what is taught in elementary algebra. The STACK CAA system, http://www.stack.bham.ac.uk/, which uses the CAS…

  19. HPC Software Stack Testing Framework

    Energy Technology Data Exchange (ETDEWEB)

    2017-07-27

    The HPC Software stack testing framework (hpcswtest) is used in the INL Scientific Computing Department to test the basic sanity and integrity of the HPC Software stack (Compilers, MPI, Numerical libraries and Applications) and to quickly discover hard failures, and as a by-product it will indirectly check the HPC infrastructure (network, PBS and licensing servers).

  20. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  1. Installation of a TCT set-up for characterization of novel HV-CMOS planar silicon sensors

    CERN Document Server

    Marx, Lisa

    2013-01-01

    For future upgrades of the LHC it is necessary to develop new tracking detectors: more radiation hard and cost efficient pixel detectors with high spacial resolution are required for the planned high luminosity version of the LHC (HL-LHC). For future tracking devices HV-CMOS active pixel sensors are great candidates since they fulfill all the demands mentioned above. First prototypes of these sensors are assembled on custom test boards and together with FE-I4 readout chips they make up the first test pixel detectors. One approach for testing these chips is through using lasers to induce electron-hole-pairs into the depletion zone of the sensor chip diodes to simulate an ionizing particle crossing through the bulk. Comparison measurements of irradiated/non-irradiated sensors are used to explore the radiation hardness of the sensors.

  2. 60-GHz CMOS phase-locked loops

    CERN Document Server

    Cheema, Hammad M; van Roermund, Arthur HM

    2010-01-01

    The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. ""60-GHz CMOS Phase-Locked Loops"" focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of i

  3. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  4. Challenges & Roadmap for Beyond CMOS Computing Simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-12-01

    Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

  5. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  6. Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

    Science.gov (United States)

    Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

    2014-01-01

    This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  7. Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

    Science.gov (United States)

    Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

    2004-06-01

    Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

  8. Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

    Science.gov (United States)

    Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

    2015-07-21

    Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

  9. Circuit design of a novel FPGA chip FDP2008

    International Nuclear Information System (INIS)

    Wu Fang; Wang Yabin; Chen Liguang; Wang Jian; Lai Jinmei; Wang Yuan; Tong Jiarong

    2009-01-01

    A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18 μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 x 30 logic TILEs, 200 programmable IOBs and 10 x 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently. (semiconductor integrated circuits)

  10. Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

    CERN Document Server

    Marcotulli, Andrea

    2016-01-01

    New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

  11. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  12. A platform for European CMOS image sensors for space applications

    Science.gov (United States)

    Minoglou, K.; San Segundo Bello, D.; Sabuncuoglu Tezcan, D.; Haspeslagh, L.; Van Olmen, J.; Merry, B.; Cavaco, C.; Mazzamuto, F.; Toqué-Trésonne, I.; Moirin, R.; Brouwer, M.; Toccafondi, M.; Preti, G.; Rosmeulen, M.; De Moor, P.

    2017-11-01

    Both ESA and the EC have identified the need for a supply chain of CMOS imagers for space applications which uses solely European sources. An essential requirement on this supply chain is the platformization of the process modules, in particular when it comes to very specific processing steps, such as those required for the manufacturing of backside illuminated image sensors. This is the goal of the European (EC/FP7/SPACE) funded project EUROCIS. All EUROCIS partners have excellent know-how and track record in the expertise fields required. Imec has been leading the imager chip design and the front side and backside processing. LASSE, as a major player in the laser annealing supplier sector, has been focusing on the optimization of the process related to the backside passivation of the image sensors. TNO, known worldwide as a top developer of instruments for scientific research, including space research and sensors for satellites, has contributed in the domain of optical layers for space instruments and optimized antireflective coatings. Finally, Selex ES, as a world-wide leader for manufacturing instruments with expertise in various space missions and programs, has defined the image sensor specifications and is taking care of the final device characterization. In this paper, an overview of the process flow, the results on test structures and imagers processed using this platform will be presented.

  13. Smart CMOS sensor for wideband laser threat detection

    Science.gov (United States)

    Schwarze, Craig R.; Sonkusale, Sameer

    2015-09-01

    The proliferation of lasers has led to their widespread use in applications ranging from short range standoff chemical detection to long range Lidar sensing and target designation operating across the UV to LWIR spectrum. Recent advances in high energy lasers have renewed the development of laser weapons systems. The ability to measure and assess laser source information is important to both identify a potential threat as well as determine safety and nominal hazard zone (NHZ). Laser detection sensors are required that provide high dynamic range, wide spectral coverage, pulsed and continuous wave detection, and large field of view. OPTRA, Inc. and Tufts have developed a custom ROIC smart pixel imaging sensor architecture and wavelength encoding optics for measurement of source wavelength, pulse length, pulse repetition frequency (PRF), irradiance, and angle of arrival. The smart architecture provides dual linear and logarithmic operating modes to provide 8+ orders of signal dynamic range and nanosecond pulse measurement capability that can be hybridized with the appropriate detector array to provide UV through LWIR laser sensing. Recent advances in sputtering techniques provide the capability for post-processing CMOS dies from the foundry and patterning PbS and PbSe photoconductors directly on the chip to create a single monolithic sensor array architecture for measuring sources operating from 0.26 - 5.0 microns, 1 mW/cm2 - 2 kW/cm2.

  14. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  15. Environmental assessment of phosphogypsum stacks

    International Nuclear Information System (INIS)

    Odat, M.; Al-Attar, L.; Raja, G.; Abdul Ghany, B.

    2008-03-01

    Phosphogypsum is one of the most important by-products of phosphate fertilizer industry. It is kept in large stacks to the west of Homs city. Storing Phosphogypsum as open stacks exposed to various environmental effects, wind and rain, may cause pollution of the surrounding ecosystem (soil, plant, water and air). This study was carried out in order to assess the environmental impact of Phosphogypsum stacks on the surrounding ecosystem. The obtained results show that Phosphogypsum stacks did not increase the concentration of radionuclides, i.e. Radon-222 and Radium-226, the external exposed dose of gamma rays, as well as the concentration of heavy metals in the components of the ecosystem, soil, plant, water and air, as their concentrations did not exceed the permissible limits. However, the concentration of fluorine in the upper layer of soil, located to the east of the Phosphogypsum stacks, increased sufficiently, especially in the dry period of the year. Also, the concentration of fluoride in plants growing up near-by the Phosphogypsum stacks was too high, exceeded the permissible levels. This was reflected in poising plants and animals, feeding on the plants. Consequently, increasing the concentration of fluoride in soil and plants is the main impact of Phosphogypsum stacks on the surrounding ecosystem. Minimising this effect could be achieved by establishing a 50 meter wide protection zone surrounding the Phosphogypsum stacks, which has to be planted with non palatable trees, such as pine and cypress, forming wind barriers. Increasing the concentrations of heavy metals and fluoride in infiltrated water around the stacks was high; hence cautions must be taken to prevent its usage in any application or disposal in adjacent rivers and leaks.(author)

  16. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  17. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, H.; Klumperink, Eric A.M.; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel

  18. Different mathematical relations with CMOS VLSI circuits

    International Nuclear Information System (INIS)

    Chible, H.; Ghandour, A.

    2007-01-01

    In this paper, Analog VLSI CMOS circuits that implements different mathematical functions, equations, or relations such as ''Addition, Subtraction, Multiplier, Quadratic, Square Root, Linear, and Hyperbolic Tangent relations'' with limited and wide range variations are presented. These relations and functions are useful for analog neural network hardware and analog signal processing implementation (author)

  19. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  20. Low noise monolithic CMOS front end electronics

    International Nuclear Information System (INIS)

    Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

    1987-01-01

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  1. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  2. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation i...

  3. CMOS Compatible Ultra-Compact Modulator

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss <1dB at telecommunication wavelengths....

  4. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  5. PieceStack: Toward Better Understanding of Stacked Graphs.

    Science.gov (United States)

    Wu, Tongshuang; Wu, Yingcai; Shi, Conglei; Qu, Huamin; Cui, Weiwei

    2016-02-24

    Stacked graphs have been widely adopted in various fields, because they are capable of hierarchically visualizing a set of temporal sequences as well as their aggregation. However, because of visual illusion issues, connections between overly-detailed individual layers and overly-generalized aggregation are intercepted. Consequently, information in this area has yet to be fully excavated. Thus, we present PieceStack in this paper, to reveal the relevance of stacked graphs in understanding intrinsic details of their displayed shapes. This new visual analytic design interprets the ways through which aggregations are generated with individual layers by interactively splitting and re-constructing the stacked graphs. A clustering algorithm is designed to partition stacked graphs into sub-aggregated pieces based on trend similarities of layers. We then visualize the pieces with augmented encoding to help analysts decompose and explore the graphs with respect to their interests. Case studies and a user study are conducted to demonstrate the usefulness of our technique in understanding the formation of stacked graphs.

  6. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

    2014-01-01

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  7. Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

    Science.gov (United States)

    Kenter, Almus

    The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

  8. A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

    Science.gov (United States)

    Tateno, Takashi; Nishikawa, Jun

    2014-01-01

    In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

  9. A CMOS IC–based multisite measuring system for stimulation and recording in neural preparations in vitro

    Directory of Open Access Journals (Sweden)

    Takashi eTateno

    2014-10-01

    Full Text Available In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS integrated circuit (IC chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 mm × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA, and a PC. To test the system, microelectrode arrays (MEAs were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μV root mean square (10 Hz to 100 kHz, which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μVpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

  10. ATLAS software stack on ARM64

    CERN Document Server

    Smith, Joshua Wyatt; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment explores new hardware and software platforms that, in the future, may be more suited to its data intensive workloads. One such alternative hardware platform is the ARM architecture, which is designed to be extremely power efficient and is found in most smartphones and tablets. CERN openlab recently installed a small cluster of ARM 64-bit evaluation prototype servers. Each server is based on a single-socket ARM 64-bit system on a chip, with 32 Cortex-A57 cores. In total, each server has 128 GB RAM connected with four fast memory channels. This paper reports on the port of the ATLAS software stack onto these new prototype ARM64 servers. This included building the "external" packages that the ATLAS software relies on. Patches were needed to introduce this new architecture into the build as well as patches that correct for platform specific code that caused failures on non-x86 architectures. These patches were applied such that porting to further platforms will need no or only very little adj...

  11. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR......In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... greater than 84 dB. The equivalent input referred noise in the bandwidth of interest is 5 nV/√Hz. The amplifier power consumption is 275 μW....

  12. Resizing methodology for CMOS analog circuits

    Science.gov (United States)

    Levi, Timothée; Tomas, Jean; Lewis, Noëlle; Fouillat, Pascal

    2007-05-01

    This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. This methodology is applied to both linear and non-linear examples: an OTA and a ring oscillator. The results are compared on three CMOS processes whose minimum length is 0.8 μm, 0.35 μm, 0.25 μm.

  13. Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

    CERN Document Server

    INSPIRE-00218480

    2016-01-01

    The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

  14. HELIX128S-2 - A readout chip for the silicon vertex detector and inner tracker detector of HERA-B

    International Nuclear Information System (INIS)

    Trunk, U.; Fallot-Burghardt, W.; Sexauer, E.; Knoepfle, K-T.; Hofmann, W.; Cuje, M.; Glass, B.; Feuerstack-Raible, M.; Eisele, F.; Straumann, U.

    1998-01-01

    HERA-B is a fixed target experiment at the HERA proton storage ring dedicated to examine CP-violation in the B-Meson system. Based on the RD20-FElix concept a readout chip has been designed in AMS's 0.8 μm CMOS process for the HERA-B silicon vertex and inner tracker (MSGC) detectors. Various test chips have been submitted and successfully tested since '95, thus enabling the submission of a fully integrated 128 channel version in April '97. Design features of this chip (HELIX128S-2) and test results of its predecessor HELIX128 are presented

  15. Development and characterisation of a radiation hard readout chip for the LHCb outer tracker detector

    International Nuclear Information System (INIS)

    Stange, U.

    2005-01-01

    The reconstruction of charged particle tracks in the Outer Tracker detector of the LHCb experiment requires to measure the drift times of the straw tubes. A Time to Digital Converter (TDC) chip has been developed for this task. The chip integrates into the LHCb data acquisition schema and fulfils the requirements of the detector. The OTIS chip is manufactured in a commercial 0.25 μm CMOS process. A 32-channel TDC core drives the drift time measurement (25 ns measurement range, 390 ps nominal resolution) without introducing dead times. The resulting drift times are buffered until a trigger decision arrives after the fixed latency of 4 μs. In case of a trigger accept signal, the digital control core processes and transmits the corresponding data to the following data acquisition stage. Drift time measurement and data processing are independent from the detector occupancy. The digital control core of the OTIS chip has been developed within this doctoral thesis. It has been integrated into the TDC chip together with other constituents of the chip. Several test chips and prototype versions of the TDC chip have been characterised. The present version of the chip OTIS1.2 fulfils all requirements and is ready for mass production. (Orig.)

  16. Resizing methodology for CMOS analog circuit

    OpenAIRE

    Levi, Timothée; Tomas, J.; Lewis, N.; Fouillat, P.

    2007-01-01

    International audience; This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain...

  17. Radiation characteristics of scintillator coupled CMOS APS for radiography conditions

    International Nuclear Information System (INIS)

    Kim, Kwang Hyun; Kim, Soongpyung; Kang, Dong-Won; Kim, Dong-Kie

    2006-01-01

    Under industrial radiography conditions, we analyzed short-term radiation characteristics of scintillator coupled CMOS APS (hereinafter SC CMOS APS). By means of experimentation, the contribution of the transmitted X-ray through the scintillator to the properties of the CMOS APS and the afterimage, generated in the acquired image even at low dose condition, were investigated. To see the transmitted X-ray effects on the CMOS APS, Fein focus TM X-ray machine, two scintillators of Lanex TM Fine and Regular, and two CMOS APS array of RadEye TM were used under the conditions of 50 kV p /1 mAs and 100 kV p /1 mAs. By measuring the transmitted X-ray on signal and Noise Power Spectrum, we analytically examined the generation mechanism of the afterimage, based on dark signal or dark current increase in the sensor, and explained the afterimage in the SC CMOS APS

  18. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  19. Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Cheng-Yang Liu

    2009-12-01

    Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

  20. Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

    Science.gov (United States)

    Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

    2009-01-01

    The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

  1. Wideband pulse amplifiers for the NECTAr chip

    Energy Technology Data Exchange (ETDEWEB)

    Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

    2012-12-11

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  2. Flip-chip integrated optical wireless transceivers

    Science.gov (United States)

    O'Brien, Dominic C.; Faulkner, Grahame E.; Zyambo, Emmanuel B.; Edwards, David J.; Stavrinou, Paul N.; Parry, Gareth; Bellon, Jacques; Sibley, Martin J. N.; Lalithambika, Vinod A.; Joyner, Valencia M.; Samsudin, Rina J.; Holburn, David M.; Mears, Robert J.

    2002-12-01

    The widespread use of Optical LANs is dependent on the ability to fabricate low cost transceiver components. These are usually complex, and fabrication involves the integration of optoelectronic and electronic devices, as well as optical components. A consortium of four UK universities are currently involved in a project to demonstrate integrated optical wireless transceiver subsystems that can provide eye-safe line of sight in-building communication at 155Mbit/s and above. In this paper we discuss the flip-chip integration of two-dimensional arrays of novel microcavity LEDs with custom CMOS integrated circuits in order to produce solid state tracking emitters. Design, fabrication and integration of these structures are detailed. The scaleability and future capability available given further optimisation and development of these systems is also discussed.

  3. Development of a Three Dimensional Neural Sensing Device by a Stacking Method

    Directory of Open Access Journals (Sweden)

    Chih-Wei Chang

    2010-04-01

    Full Text Available This study reports a new stacking method for assembling a 3-D microprobe array. To date, 3-D array structures have usually been assembled with vertical spacers, snap fasteners and a supporting platform. Such methods have achieved 3-D structures but suffer from complex assembly steps, vertical interconnection for 3-D signal transmission, low structure strength and large implantable opening. By applying the proposed stacking method, the previous techniques could be replaced by 2-D wire bonding. In this way, supporting platforms with slots and vertical spacers were no longer needed. Furthermore, ASIC chips can be substituted for the spacers in the stacked arrays to achieve system integration, design flexibility and volume usage efficiency. To avoid overflow of the adhesive fluid during assembly, an anti-overflow design which made use of capillary action force was applied in the stacking method as well. Moreover, presented stacking procedure consumes only 35 minutes in average for a 4 × 4 3-D microprobe array without requiring other specially made assembly tools. To summarize, the advantages of the proposed stacking method for 3-D array assembly include simplified assembly process, high structure strength, smaller opening area and integration ability with active circuits. This stacking assembly technique allows an alternative method to create 3-D structures from planar components.

  4. Behavior of faulty double BJT BiCMOS logic gates

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1992-01-01

    Logic Behavior of a Double BJT BiCMOS device under transistor level shorts and opens is examined. In addition to delay faults, faults that cause the gate to exhibit sequential behavior were observed. Several faults can be detected only by monitoring the current. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS, to bring out the testability differences.

  5. Characterization of pixel sensor designed in 180 nm SOI CMOS technology

    Science.gov (United States)

    Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

    2018-01-01

    A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

  6. Systematic study of packaging designs on the performance of CMOS thermoresistive micro calorimetric flow sensors

    International Nuclear Information System (INIS)

    Xu, Wei; Gao, Bo; Xu, Kun; Lee, Yi-Kuen; Pan, Liang; Chiu, Yi

    2017-01-01

    We systematically study the effect of two packaging configurations for the CMOS thermoresistive micro calorimetric flow (TMCF) sensors: S-type with the sensor chip protrusion-mounted on the flow channel wall and E-type with the sensor chip flush-mounted on the flow channel wall. Although the experimental results indicated that the sensitivity of the S-type was increased by more than 30%; the corresponding flow range as compared to the E-type was dramatically reduced by 60% from 0–11 m s −1 to 0–4.5 m s −1 . Comprehensive 2D CFD simulation and in-house developed 3D numerical simulations based on the gas-kinetic scheme were applied to study the flow separation of these two packaging designs with the major parameters. Indeed, the S-type design with the large protrusion would change the local convective heat transfer of the TMCF sensor and dramatically decrease the sensors’ performance. In addition, parametric CFD simulations of the packaging designs provide inspiration to propose a novel general flow regime map (FRM), i.e. normalized protrusion d * versus reduced chip Reynolds number Re * , where the critical boundary curve for the flow separation of TMCF sensors was determined at different channel aspect ratios. The proposed FRM can be a useful guideline for the packaging design and manufacturing of different micro thermal flow sensors. (paper)

  7. Deep n-well MAPS in a 130 nm CMOS technology: Beam test results

    Energy Technology Data Exchange (ETDEWEB)

    Neri, N., E-mail: nicola.neri@pi.infn.i [Universita degli Studi di Pisa and INFN-Pisa (Italy); Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Ceccanti, M.; Cenci, R.; Cervelli, A.; Crescioli, F.; Dell' Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M.A.; Gregucci, S.; Mammini, P.; Marchiori, G.; Massa, M.; Morsani, F.; Paoloni, E.; Piendibene, M. [Universita degli Studi di Pisa and INFN-Pisa (Italy)

    2010-11-01

    We report on recent beam test results for the APSEL4D chip, a new deep n-well MAPS prototype with a full in-pixel signal processing chain obtained by exploiting the triple well option of the CMOS 0.13{mu}m process. The APSEL4D chip consists of a 4096 pixel matrix (32 rows and 128 columns) with 50x50{mu}m{sup 2} pixel cell area, with custom readout architecture capable of performing data sparsification at pixel level. APSEL4D has been characterized in terms of charge collection efficiency and intrinsic spatial resolution under different conditions of discriminator threshold settings using a 12 GeV/c proton beam in the T9 area of the CERN PS. We observe a maximum hit efficiency of 92% and we estimate an intrinsic resolution of about 14{mu}m. The data driven approach of the tracking detector readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on associative memories. The analysis of the beam test data is critically reviewed along with the characterization of the device under test.

  8. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  9. Time-predictable Stack Caching

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar

    completely. Thus, in systems with hard deadlines the worst-case execution time (WCET) of the real-time software running on them needs to be bounded. Modern architectures use features such as pipelining and caches for improving the average performance. These features, however, make the WCET analysis more...... addresses, provides an opportunity to predict and tighten the WCET of accesses to data in caches. In this thesis, we introduce the time-predictable stack cache design and implementation within a time-predictable processor. We introduce several optimizations to our design for tightening the WCET while...... keeping the timepredictability of the design intact. Moreover, we provide a solution for reducing the cost of context switching in a system using the stack cache. In design of these caches, we use custom hardware and compiler support for delivering time-predictable stack data accesses. Furthermore...

  10. Glassy carbon based supercapacitor stacks

    Energy Technology Data Exchange (ETDEWEB)

    Baertsch, M.; Braun, A.; Koetz, R.; Haas, O. [Paul Scherrer Inst. (PSI), Villigen (Switzerland)

    1997-06-01

    Considerable effort is being made to develop electrochemical double layer capacitors (EDLC) that store relatively large quantities of electrical energy and possess at the same time a high power density. Our previous work has shown that glassy carbon is suitable as a material for capacitor electrodes concerning low resistance and high capacity requirements. We present the development of bipolar electrochemical glassy carbon capacitor stacks of up to 3 V. Bipolar stacks are an efficient way to meet the high voltage and high power density requirements for traction applications. Impedance and cyclic voltammogram measurements are reported here and show the frequency response of a 1, 2, and 3 V stack. (author) 3 figs., 1 ref..

  11. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  12. Through-Silicon-Via Underfill Dispensing for 3D Die/Interposer Stacking

    Science.gov (United States)

    Le, Fuliang

    The next generation packaging keeps up with the increased demands of functionality by using the third dimension. 3D chip stacking with TSVs has been identified as one of the major technologies to achieve higher silicon density and shorter interconnection. In order to protect solder interconnections from hostile environments and redistribute thermal stress caused by CTE mismatch, underfill should be applied for the under-chip spaces. In this study, TSV underfill dispensing is introduced to address the underfill challenge for 3D chip stacks. The material properties are first measured and the general trend indicates viscosity and contact angle dropping significantly with an increase in temperature, and surface tension falling slightly as the temperature increases. Underfill should assure a complete encapsulation, avoiding excessive filling time that can result in substantial manufacturing delays. Typically, the inflows for TSV underfill can be free droplets or a constant flow rate. For a constant inflow, the underfill flow is driven by pressure difference and the filling time is governed by flow radius, gap clearance and the constant flow rate. For an inflow of free droplets, the underfill flow is driven by capillary action and the filling time is related to viscosity, flow radius, gap clearance, surface tension, contact angle and TSV size. In general, TSV underfill dispensing with a constant inflow has much shorter filling time than dispensing with an inflow of free droplets. TSV underfill dispensing on a 3D chip stack may induce the risk of an edge flood failure. In order to avoid an edge flood, fluid pressure around the sidewalls of a 3D chip stack cannot exceed limit equilibrium pressure. For TSV dispensing with free droplets, there is no risk of forming an edge flood. However, for a constant inflow, TSV dispensing should be carefully controlled to avoid excessive pressure. Besides, it is suggested that the TSVs in stacked chips be aligned in the vertical

  13. Multiple Segmentation of Image Stacks

    DEFF Research Database (Denmark)

    Smets, Jonathan; Jaeger, Manfred

    2014-01-01

    We propose a method for the simultaneous construction of multiple image segmentations by combining a recently proposed “convolution of mixtures of Gaussians” model with a multi-layer hidden Markov random field structure. The resulting method constructs for a single image several, alternative...... segmentations that capture different structural elements of the image. We also apply the method to collections of images with identical pixel dimensions, which we call image stacks. Here it turns out that the method is able to both identify groups of similar images in the stack, and to provide segmentations...

  14. Simulating Small-Scale Object Stacking Using Stack Stability

    DEFF Research Database (Denmark)

    Kronborg Thomsen, Kasper; Kraus, Martin

    2015-01-01

    This paper presents an extension system to a closed-source, real-time physics engine for improving structured stacking behavior with small-scale objects such as wooden toy bricks. The proposed system was implemented and evaluated. The tests showed that the system is able to simulate several common...

  15. Design of the 65 nm CLICpix demonstrator chip

    CERN Document Server

    Valerio, P.; Campbell, M.

    2012-01-01

    A hybrid pixel detector ASIC designed to be used in the vertex detector for the CLIC experiment is presented in this note. It has been designed using a commercial 65 nm CMOS technology. The main features include simultaneous 4-bit TOT and TOA measurements with 10 ns accuracy, a spatial resolution of 3 um (the pixel size is 25x25 um), an on-chip data compression scheme and power pulsing capability. A prototype with a fully featured array of 64 by 64 pixels has been designed and produced. Testing on the prototype is ongoing.

  16. Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

    Science.gov (United States)

    Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

    2018-04-01

    Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

  17. Pressurized electrolysis stack with thermal expansion capability

    Science.gov (United States)

    Bourgeois, Richard Scott

    2015-07-14

    The present techniques provide systems and methods for mounting an electrolyzer stack in an outer shell so as to allow for differential thermal expansion of the electrolyzer stack and shell. Generally, an electrolyzer stack may be formed from a material with a high coefficient of thermal expansion, while the shell may be formed from a material having a lower coefficient of thermal expansion. The differences between the coefficients of thermal expansion may lead to damage to the electrolyzer stack as the shell may restrain the thermal expansion of the electrolyzer stack. To allow for the differences in thermal expansion, the electrolyzer stack may be mounted within the shell leaving a space between the electrolyzer stack and shell. The space between the electrolyzer stack and the shell may be filled with a non-conductive fluid to further equalize pressure inside and outside of the electrolyzer stack.

  18. PHYSICS: Toward Atom Chips.

    Science.gov (United States)

    Fortágh, József; Zimmermann, Claus

    2005-02-11

    As a novel approach for turning the peculiar features of quantum mechanics into practical devices, researchers are investigating the use of ultracold atomic clouds above microchips. Such "atom chips" may find use as sensitive probes for gravity, acceleration, rotation, and tiny magnetic forces. In their Perspective, Fortagh and Zimmermann discuss recent advances toward creating atom chips, in which current-carrying conductors in the chips create magnetic microtraps that confine the atomic clouds. Despite some intrinsic limits to the performance of atom chips, existing technologies are capable of producing atom chips, and many possibilities for their construction remain to be explored.

  19. The Direct FuelCell™ stack engineering

    Science.gov (United States)

    Doyon, J.; Farooque, M.; Maru, H.

    FuelCell Energy (FCE) has developed power plants in the size range of 300 kW to 3 MW for distributed power generation. Field-testing of the sub-megawatt plants is underway. The FCE power plants are based on its Direct FuelCell™ (DFC) technology. This is so named because of its ability to generate electricity directly from a hydrocarbon fuel, such as natural gas, by reforming it inside the fuel cell stack itself. All FCE products use identical 8000 cm 2 cell design, approximately 350-400 cells per stack, external gas manifolds, and similar stack compression systems. The difference lies in the packaging of the stacks inside the stack module. The sub-megawatt system stack module contains a single horizontal stack whereas the MW-class stack module houses four identical vertical stacks. The commonality of the design, internal reforming features, and atmospheric operation simplify the system design, reduce cost, improve efficiency, increase reliability and maintainability. The product building-block stack design has been advanced through three full-size stack operations at company's headquarters in Danbury, CT. The initial proof-of-concept of the full-size stack design was verified in 1999, followed by a 1.5 year of endurance verification in 2000-2001, and currently a value-engineered stack version is in operation. This paper discusses the design features, important engineering solutions implemented, and test results of FCE's full-size DFC stacks.

  20. sCMOS detector for imaging VNIR spectrometry

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  1. Chip-to-chip SnO2 nanowire network sensors for room temperature H2 detection

    Science.gov (United States)

    Köck, A.; Brunet, E.; Mutinati, G. C.; Maier, T.; Steinhauer, S.

    2012-06-01

    The employment of nanowires is a very powerful strategy to improve gas sensor performance. We demonstrate a gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected SnO2 nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device is able to detect a H2 concentration of only 20 ppm in synthetic air with ~ 60% relative humidity at room temperature. At an operating temperature of 300°C a concentration of 50 ppm H2 results in a sensitivity of 5%. At this elevated temperature the sensor shows a linear response in a concentration range between 10 ppm and 100 ppm H2. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.

  2. Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

    Science.gov (United States)

    Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

    2016-10-01

    The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

  3. A 32-channels, 025 mu m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anelli, G; Anghinolfi, F; Martínez, M I; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32*256 cells analogue memory and 16 successive approximation 10 bit A /D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way; when an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial. 0.25 mu m CMOS technology. It has been extensively tested both on a bench and connected with the detector in several beam tests. In this paper both design issues and test results are presented. The commercial technology used for the design has been yield radiation tolerant with special layout techniques. Total dose irradiation tests are also presented. (13 refs).

  4. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 {mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing, E-mail: wubin@ime.ac.cn [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2011-05-15

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 {mu}m 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm{sup 2} area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  5. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

    International Nuclear Information System (INIS)

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing

    2011-01-01

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm 2 area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  6. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

    Science.gov (United States)

    Bin, Wu; Yumei, Zhou; Yongxu, Zhu; Zhengdong, Zhang; Jingjing, Cai

    2011-05-01

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 × 2.6 mm2 area and consumes 83 mW under typical work modes.

  7. Stack semantics of type theory

    DEFF Research Database (Denmark)

    Coquand, Thierry; Mannaa, Bassel; Ruch, Fabian

    2017-01-01

    We give a model of dependent type theory with one univalent universe and propositional truncation interpreting a type as a stack, generalizing the groupoid model of type theory. As an application, we show that countable choice cannot be proved in dependent type theory with one univalent universe...

  8. Multilayer Piezoelectric Stack Actuator Characterization

    Science.gov (United States)

    Sherrit, Stewart; Jones, Christopher M.; Aldrich, Jack B.; Blodget, Chad; Bao, Xioaqi; Badescu, Mircea; Bar-Cohen, Yoseph

    2008-01-01

    Future NASA missions are increasingly seeking to use actuators for precision positioning to accuracies of the order of fractions of a nanometer. For this purpose, multilayer piezoelectric stacks are being considered as actuators for driving these precision mechanisms. In this study, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and extreme temperatures and voltages. AC signal testing included impedance, capacitance and dielectric loss factor of each actuator as a function of the small-signal driving sinusoidal frequency, and the ambient temperature. DC signal testing includes leakage current and displacement as a function of the applied DC voltage. The applied DC voltage was increased to over eight times the manufacturers' specifications to investigate the correlation between leakage current and breakdown voltage. Resonance characterization as a function of temperature was done over a temperature range of -180C to +200C which generally exceeded the manufacturers' specifications. In order to study the lifetime performance of these stacks, five actuators from one manufacturer were driven by a 60volt, 2 kHz sine-wave for ten billion cycles. The tests were performed using a Lab-View controlled automated data acquisition system that monitored the waveform of the stack electrical current and voltage. The measurements included the displacement, impedance, capacitance and leakage current and the analysis of the experimental results will be presented.

  9. Open stack thermal battery tests

    Energy Technology Data Exchange (ETDEWEB)

    Long, Kevin N. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Roberts, Christine C. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Grillet, Anne M. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Headley, Alexander J. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Fenton, Kyle [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Wong, Dennis [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Ingersoll, David [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-04-17

    We present selected results from a series of Open Stack thermal battery tests performed in FY14 and FY15 and discuss our findings. These tests were meant to provide validation data for the comprehensive thermal battery simulation tools currently under development in Sierra/Aria under known conditions compared with as-manufactured batteries. We are able to satisfy this original objective in the present study for some test conditions. Measurements from each test include: nominal stack pressure (axial stress) vs. time in the cold state and during battery ignition, battery voltage vs. time against a prescribed current draw with periodic pulses, and images transverse to the battery axis from which cell displacements are computed. Six battery configurations were evaluated: 3, 5, and 10 cell stacks sandwiched between 4 layers of the materials used for axial thermal insulation, either Fiberfrax Board or MinK. In addition to the results from 3, 5, and 10 cell stacks with either in-line Fiberfrax Board or MinK insulation, a series of cell-free “control” tests were performed that show the inherent settling and stress relaxation based on the interaction between the insulation and heat pellets alone.

  10. Adding large EM stack support

    KAUST Repository

    Holst, Glendon

    2016-12-01

    Serial section electron microscopy (SSEM) image stacks generated using high throughput microscopy techniques are an integral tool for investigating brain connectivity and cell morphology. FIB or 3View scanning electron microscopes easily generate gigabytes of data. In order to produce analyzable 3D dataset from the imaged volumes, efficient and reliable image segmentation is crucial. Classical manual approaches to segmentation are time consuming and labour intensive. Semiautomatic seeded watershed segmentation algorithms, such as those implemented by ilastik image processing software, are a very powerful alternative, substantially speeding up segmentation times. We have used ilastik effectively for small EM stacks – on a laptop, no less; however, ilastik was unable to carve the large EM stacks we needed to segment because its memory requirements grew too large – even for the biggest workstations we had available. For this reason, we refactored the carving module of ilastik to scale it up to large EM stacks on large workstations, and tested its efficiency. We modified the carving module, building on existing blockwise processing functionality to process data in manageable chunks that can fit within RAM (main memory). We review this refactoring work, highlighting the software architecture, design choices, modifications, and issues encountered.

  11. CMOS compatible route for GaAs based large scale flexible and transparent electronics

    KAUST Repository

    Nour, Maha A.

    2014-08-01

    Flexible electronics using gallium arsenide (GaAs) for nano-electronics with high electron mobility and optoelectronics with direct band gap are attractive for many applications. Here we describe a state-of-the-art CMOS compatible batch fabrication process of transforming traditional electronic circuitry into large-area flexible, semitransparent platform. We show a simple release process for peeling off 200 nm of GaAs from 200 nm GaAs/300 nm AlAs stack on GaAs substrate using diluted hydrofluoric acid (HF). This process enables releasing a single top layer compared to peeling off all layers with small sizes at the same time. This is done utilizing a network of release holes which contributes to the better transparency (45 % at 724 nm wavelength) observed.

  12. Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology

    Science.gov (United States)

    Poludniowski, G.; Allinson, N. M.; Anaxagoras, T.; Esposito, M.; Green, S.; Manolopoulos, S.; Nieto-Camero, J.; Parker, D. J.; Price, T.; Evans, P. M.

    2014-06-01

    Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed.

  13. Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology

    International Nuclear Information System (INIS)

    Poludniowski, G; Esposito, M; Evans, P M; Allinson, N M; Anaxagoras, T; Green, S; Parker, D J; Price, T; Manolopoulos, S; Nieto-Camero, J

    2014-01-01

    Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed. (paper)

  14. Proton-counting radiography for proton therapy: a proof of principle using CMOS APS technology.

    Science.gov (United States)

    Poludniowski, G; Allinson, N M; Anaxagoras, T; Esposito, M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Price, T; Evans, P M

    2014-06-07

    Despite the early recognition of the potential of proton imaging to assist proton therapy (Cormack 1963 J. Appl. Phys. 34 2722), the modality is still removed from clinical practice, with various approaches in development. For proton-counting radiography applications such as computed tomography (CT), the water-equivalent-path-length that each proton has travelled through an imaged object must be inferred. Typically, scintillator-based technology has been used in various energy/range telescope designs. Here we propose a very different alternative of using radiation-hard CMOS active pixel sensor technology. The ability of such a sensor to resolve the passage of individual protons in a therapy beam has not been previously shown. Here, such capability is demonstrated using a 36 MeV cyclotron beam (University of Birmingham Cyclotron, Birmingham, UK) and a 200 MeV clinical radiotherapy beam (iThemba LABS, Cape Town, SA). The feasibility of tracking individual protons through multiple CMOS layers is also demonstrated using a two-layer stack of sensors. The chief advantages of this solution are the spatial discrimination of events intrinsic to pixelated sensors, combined with the potential provision of information on both the range and residual energy of a proton. The challenges in developing a practical system are discussed.

  15. Monolithic integration of photonic and electronic circuits in a CMOS process

    Science.gov (United States)

    Mekis, Attila; Abdalla, Sherif; Analui, Behnam; Gloeckner, Steffen; Guckenberger, Andrew; Koumans, Roger; Kucharski, Daniel; Liang, Yi; Masini, Gianlorenzo; Mirsaidi, Sina; Narasimha, Adithyaram; Pinguet, Thierry; Sadagopan, Vikram; Welch, Brian; White, Joe; Witzens, Jeremy

    2008-02-01

    We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission speed and report on its performance.

  16. An integrated low 1/f noise and high-sensitivity CMOS instrumentation amplifier for TMR sensors

    Science.gov (United States)

    Gao, Zhiqiang; Luan, Bo; Zhao, Jincai; Liu, Xiaowei

    2017-03-01

    In this paper, a very low 1/f noise integrated Wheatstone bridge magnetoresistive sensor ASIC based on magnetic tunnel junction (MTJ) technology is presented for high sensitivity measurements. The present CMOS instrumentation amplifier employs the gain-boost folded-cascode structure based on the capacitive-feedback chopper-stabilized technique. By chopping both the input and the output of the amplifier, combined with MTJ magnetoresistive sensitive elements, a noise equivalent magnetoresistance 1 nT/Hz1/2 at 2 Hz, the equivalent input noise spectral density 17 nV/Hz1/2(@2Hz) is achieved. The chip-scale package of the TMR sensor and the instrumentation amplifier is only about 5 mm × 5 mm × 1 mm, while the whole DC current dissipates only 2 mA.

  17. Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage

    Directory of Open Access Journals (Sweden)

    G. Nagy

    2016-06-01

    Full Text Available In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a latchup risk, bulk-driven charge pumps can safely be used only in low-voltage applications. For the input voltage below 200 mV and output current of 1 uA, the proposed bulk-driven topology can achieve about 10 % higher efficiency than the conventional gate-driven cross-coupled charge pump. Therefore, it can be effectively used in DC-DC converters, which are the basic building blocks of on-chip energy harvesting systems with ultra-low supply voltage.

  18. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    Energy Technology Data Exchange (ETDEWEB)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-01-15

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 mum RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm{sup 2} and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  19. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    International Nuclear Information System (INIS)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan

    2009-01-01

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm 2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  20. A low power, large dynamic range, CMOS amplifier and analog memory for capacitive sensors

    CERN Document Server

    Aspell, P; Bloch, P; Bourotte, J; Grabit, R; Jarron, Pierre; Reynaud, S; Van Hove, A; Zamiatin, N I

    1996-01-01

    This paper has been written to announce the design of a CMOS charge to voltage amplifier and it¹s integration within an analog memory. Together they provide the necessary front end electronics for the CMS electromagnetic calorimeter (ECAL) preshower detector systeAspell,Pm in the LHC experiment foreseen at the CERN particle physics laboratory. The design and measurements of the amplifier realised in a 1.5mm bulk CMOS process as a 16 channel prototype chip are presented. Results show the mean gain and peaking time of = 1.74mV/mip, = 18ns with channel to channel variations; s(peak_voltage) = 8% and s(peak_time) = 6.5%. The dynamic range is shown to be linear over 400mips with an integral non linearity (INL)=0.05mV as expressed in terms of sigma from the mean gain over the 400mip range. The measured noise of the amplifier was ENC=1800+41e/pF with a power consumption of 2.4mW/channel. The amplifier can support extreme levels of leakage current. The gain remains constant for up to 200mA of leakage current. The ...

  1. A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

    Science.gov (United States)

    Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

    2014-10-01

    This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

  2. A 10-bit 100 MSamples/s BiCMOS D/A Converter

    DEFF Research Database (Denmark)

    Jørgensen, Ivan Herald Holger; Tunheim, Svein Anders

    1997-01-01

    This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8 micron BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis......, and focus has been set on reducing dynamic nonlinearities to achieve a high spurious free dynamic range (SFDR) at high generated frequencies. The main part of the DAC consists of a matrix of current cells. Each current cell contains an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock...... to ensure accurate clocking. A bipolar differential pair, with a cascode CMOS current sink, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. The DAC operates at 5V, and has a power consumption of 650mW. The area of the chip-core is 2.2mm by 2.2mm...

  3. A low-power CMOS smart temperature sensor for RFID application

    International Nuclear Information System (INIS)

    Xie Liangbo; Liu Jiaxin; Wang Yao; Wen Guangjun

    2014-01-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is −0.69/+0.85 °C after one-point calibration over a temperature range of −40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm 2 , and it is suitable for RFID application. (semiconductor integrated circuits)

  4. Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

    Science.gov (United States)

    Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

    2008-02-01

    Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

  5. Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

    CERN Document Server

    Benoit, M.; Casse, G.; Chen, H.; Chen, K.; Bello, F.A.Di; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Peric, I.; Rimoldi, M.; Ristic, B.; Vicente Barrero Pinto, M.; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

    2018-02-08

    HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{\\mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1\\cdot 10^{14}$ and $5\\cdot 10^{15}$ 1-MeV-n$_\\textrm{eq}$/cm$^2$. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of $85\\,$V. The sample irradiated to a fluence of $1\\cdot 10^{15}$ n$_\\textrm{eq}$/cm$^2$ - a relevant value for a large volume of the upgraded tracker - exhibited 99.7% average hit ...

  6. Design and analysis of CMOS single photon counting avalanche photodiodes integrated with active quenching circuits

    International Nuclear Information System (INIS)

    Kim, Kwang Hyun; Kim, Young Soo

    2008-01-01

    The CMOS SPADs (Single Photon Avalanche Diodes) integrated with active quenching circuits were fabricated on same chip using AMIS 0.7 μm high voltage CMOS process without any process modifications. The SPADs have N+/P-substrate structure and their diameter of photo sensing area are 25 μm, 50 μm, 100 μm, 400 μm, and 800 μm. The avalanche multiplication is occurred at 10.7 V, and the photocurrent gain at 11 V reverse bias voltage is about 1000. In zero bias condition, the maximum quantum efficiency appears at 650 nm wavelength, and it corresponds to around 30%. The active quenching circuit is composed to a comparator, three monostable, and two MOS switch. As a circuit simulation results, the comparator and the monostable generate ∼22 nsec and ∼1 nsec delayed output pulse, respectively. The dead time of the active quenching circuits integrated with SPADs is about 100 nsec as a measured result. (author)

  7. A low-power CMOS smart temperature sensor for RFID application

    Science.gov (United States)

    Liangbo, Xie; Jiaxin, Liu; Yao, Wang; Guangjun, Wen

    2014-11-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/+0.85 °C after one-point calibration over a temperature range of -40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.

  8. A microfluidic microprocessor: controlling biomimetic containers and cells using hybrid integrated circuit/microfluidic chips.

    Science.gov (United States)

    Issadore, David; Franke, Thomas; Brown, Keith A; Westervelt, Robert M

    2010-11-07

    We present an integrated platform for performing biological and chemical experiments on a chip based on standard CMOS technology. We have developed a hybrid integrated circuit (IC)/microfluidic chip that can simultaneously control thousands of living cells and pL volumes of fluid, enabling a wide variety of chemical and biological tasks. Taking inspiration from cellular biology, phospholipid bilayer vesicles are used as robust picolitre containers for reagents on the chip. The hybrid chip can be programmed to trap, move, and porate individual living cells and vesicles and fuse and deform vesicles using electric fields. The IC spatially patterns electric fields in a microfluidic chamber using 128 × 256 (32,768) 11 × 11 μm(2) metal pixels, each of which can be individually driven with a radio frequency (RF) voltage. The chip's basic functions can be combined in series to perform complex biological and chemical tasks and can be performed in parallel on the chip's many pixels for high-throughput operations. The hybrid chip operates in two distinct modes, defined by the frequency of the RF voltage applied to the pixels: Voltages at MHz frequencies are used to trap, move, and deform objects using dielectrophoresis and voltages at frequencies below 1 kHz are used for electroporation and electrofusion. This work represents an important step towards miniaturizing the complex chemical and biological experiments used for diagnostics and research onto automated and inexpensive chips.

  9. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-09-21

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  10. Micro-scale characterization of a CMOS-based neutron detector for in-phantom measurements in radiation therapy

    Science.gov (United States)

    Arbor, Nicolas; Higueret, Stephane; Husson, Daniel

    2018-04-01

    The CMOS sensor AlphaRad has been designed at the IPHC Strasbourg for real-time monitoring of fast and thermal neutrons over a full energy spectrum. Completely integrated, highly transparent to photons and optimized for low power consumption, this sensor offers very interesting characteristics for the study of internal neutrons in radiation therapy with anthropomorphic phantoms. However, specific effects related to the CMOS metal substructure and to the charge collection process of low energy particles must be carefully estimated before being used for medical applications. We present a detailed characterization of the AlphaRad chip in the MeV energy range using proton and alpha micro-beam experiments performed at the AIFIRA facility (CENBG, Bordeaux). Two-dimensional maps of the charge collection were carried out on a micro-metric scale to be integrated into a Geant4 Monte Carlo simulation of the system. The gamma rejection, as well as the fast and thermal neutrons separation, were studied using both simulation and experimental data. The results highlight the potential of a future system based on CMOS sensor for in-phantom neutron detection in radiation therapies.

  11. Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

    2018-03-01

    Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

  12. Towards a new generation of pixel detector readout chips

    CERN Document Server

    Campbell, M; Ballabriga, R.; Frojdh, E.; Heijne, E.; Llopart, X.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.

    2016-01-01

    The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile- ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.

  13. A prototype pixel readout chip for asynchronous detection applications

    International Nuclear Information System (INIS)

    Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

    1991-01-01

    A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

  14. Electron Spin Resonance Measurement with Microinductor on Chip

    Directory of Open Access Journals (Sweden)

    Akio Kitagawa

    2011-01-01

    Full Text Available The detection of radicals on a chip is demonstrated. The proposed method is based on electron spin resonance (ESR spectroscopy and the measurement of high-frequency impedance of the microinductor fabricated on the chip. The measurement was by using a frequency sweep of approximately 100 MHz. The ESR spectra of di(phenyl-(2,4,6-trinitrophenyliminoazanium (DPPH dropped on the microinductor which is fabricated with CMOS 350-nm technology were observed at room temperature. The volume of the DPPH ethanol solution was 2 μL, and the number of spins on the micro-inductor was estimated at about 1014. The sensitivity is not higher than that of the standard ESR spectrometers. However, the result indicates the feasibility of a near field radical sensor in which the microinductor as a probe head and ESR signal processing circuit are integrated.

  15. CMOS Monolithic Active Pixel Sensors (MAPS): developments and future outlook

    NARCIS (Netherlands)

    Turchetta, R.; Fant, A.; Gasiorek, P.; Esbrand, C.; Griffiths, J.A.; Metaxas, M.G.; Royle, G.J.; Speller, R.; Venanzi, C.; van der Stelt, P.F.; Verheij, H.; Li, G.; Theodoridis, S.; Georgiou, H.; Cavouras, D.; Hall, G.; Noy, M.; Jones, J.; Leaver, J.; Machin, D.; Greenwood, S.; Khaleeq, M.; Schulerud, H.; Østby, J.M.; Triantis, F.; Asimidis, A.; Bolanakis, D.; Manthos, N.; Longo, R.; Bergamaschi, A.

    2007-01-01

    Re-invented in the early 1990s, on both sides of the Atlantic, Monolithic Active Pixel Sensors (MAPS) in a CMOS technology are today the most sold solid-state imaging devices, overtaking the traditional technology of Charge-Coupled Devices (CCD). The slow uptake of CMOS MAPS started with low-end

  16. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process...

  17. Charge-Transfer CMOS Image Sensors : Device and Radiation Aspects

    NARCIS (Netherlands)

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-?m CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of

  18. A linearization time-domain CMOS smart temperature sensor using a curvature compensation oscillator.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Hao-Wen

    2013-08-28

    This paper presents an area-efficient time-domain CMOS smart temperature sensor using a curvature compensation oscillator for linearity enhancement with a -40 to 120 °C temperature range operability. The inverter-based smart temperature sensors can substantially reduce the cost and circuit complexity of integrated temperature sensors. However, a large curvature exists on the temperature-to-time transfer curve of the inverter-based delay line and results in poor linearity of the sensor output. For cost reduction and error improvement, a temperature-to-pulse generator composed of a ring oscillator and a time amplifier was used to generate a thermal sensing pulse with a sufficient width proportional to the absolute temperature (PTAT). Then, a simple but effective on-chip curvature compensation oscillator is proposed to simultaneously count and compensate the PTAT pulse with curvature for linearization. With such a simple structure, the proposed sensor possesses an extremely small area of 0.07 mm2 in a TSMC 0.35-mm CMOS 2P4M digital process. By using an oscillator-based scheme design, the proposed sensor achieves a fine resolution of 0.045 °C without significantly increasing the circuit area. With the curvature compensation, the inaccuracy of -1.2 to 0.2 °C is achieved in an operation range of -40 to 120 °C after two-point calibration for 14 packaged chips. The power consumption is measured as 23 mW at a sample rate of 10 samples/s.

  19. A Linearization Time-Domain CMOS Smart Temperature Sensor Using a Curvature Compensation Oscillator

    Directory of Open Access Journals (Sweden)

    Hao-Wen Chen

    2013-08-01

    Full Text Available This paper presents an area-efficient time-domain CMOS smart temperature sensor using a curvature compensation oscillator for linearity enhancement with a −40 to 120 °C temperature range operability. The inverter-based smart temperature sensors can substantially reduce the cost and circuit complexity of integrated temperature sensors. However, a large curvature exists on the temperature-to-time transfer curve of the inverter-based delay line and results in poor linearity of the sensor output. For cost reduction and error improvement, a temperature-to-pulse generator composed of a ring oscillator and a time amplifier was used to generate a thermal sensing pulse with a sufficient width proportional to the absolute temperature (PTAT. Then, a simple but effective on-chip curvature compensation oscillator is proposed to simultaneously count and compensate the PTAT pulse with curvature for linearization. With such a simple structure, the proposed sensor possesses an extremely small area of 0.07 mm2 in a TSMC 0.35-mm CMOS 2P4M digital process. By using an oscillator-based scheme design, the proposed sensor achieves a fine resolution of 0.045 °C without significantly increasing the circuit area. With the curvature compensation, the inaccuracy of −1.2 to 0.2 °C is achieved in an operation range of −40 to 120 °C after two-point calibration for 14 packaged chips. The power consumption is measured as 23 mW at a sample rate of 10 samples/s.

  20. Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Aunet, Snorre

    2002-06-01

    This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

  1. An inductorless CMOS realization of Chua's circuit

    CERN Document Server

    Radwan, A G; El-Sedeek, A L

    2003-01-01

    In this paper, an inductorless CMOS realization of Chua's circuit [IEEE Trans. Circ. Syst.--I 1985;32:798] is presented. The circuit is derived from the dimensionless form of Chua's circuit and can generate Rossler or double-scroll attractors by changing a single capacitor's value. Variables are represented in the current domain to facilitate adding or subtracting variables. New G sub m -C representation of the Chua diode as well as the Chua circuit are presented. The circuit can operate from supply voltage as low as +-1.5 V. Transistor-level simulation results using PSpice in 0.5 mu m Mietec process are presented.

  2. CMOS current controlled fully balanced current conveyor

    Science.gov (United States)

    Chunhua, Wang; Qiujing, Zhang; Haiguang, Liu

    2009-07-01

    This paper presents a current controlled fully balanced second-generation current conveyor circuit (CF-BCCII). The proposed circuit has the traits of fully balanced architecture, and its X-Y terminals are current controllable. Based on the CFBCCII, two biquadratic universal filters are also proposed as its applications. The CFBCCII circuits and the two filters were fabricated with chartered 0.35-μm CMOS technology; with ±1.65 V power supply voltage, the total power consumption of the CFBCCII circuit is 3.6 mW. Comparisons between measured and HSpice simulation results are also given.

  3. Analysis of bipolar and CMOS amplifiers

    CERN Document Server

    Sodagar, Amir M

    2007-01-01

    The classical approach to analog circuit analysis is a daunting prospect to many students, requiring tedious enumeration of contributing factors and lengthy calculations. Most textbooks apply this cumbersome approach to small-signal amplifiers, which becomes even more difficult as the number of components increases. Analysis of Bipolar and CMOS Amplifiers offers students an alternative that enables quick and intuitive analysis and design: the analysis-by-inspection method.This practical and student-friendly text demonstrates how to achieve approximate results that fall within an acceptable ran

  4. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  5. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  6. Development of a dynamic CT system for neutron radiography and consecutive visualization of three-dimensional water behavior in a PEFC stack

    International Nuclear Information System (INIS)

    Murakawa, Hideki; Hashimoto, Michinori; Sugimoto, Katsumi; Asano, Hitoshi; Takenaka, Nobuyuki; Mochiki, Koh-ichi; Yasuda, Ryo

    2011-01-01

    A dynamic CT system was developed for visualization of consecutive three-dimensional water behavior in a PEFC stack for neutron radiography. The system is composed of a neutron image intensifier and a C-MOS high speed video camera. An operating stack with three cells based on the Japan Automobile Research Institute standard was visualized using the neutron radiography system at a research reactor JRR-3 in Japan Atomic Energy Agency. The dynamic water behavior in channels in the operating PEFC stack was clearly visualized every 15 seconds by using the system. The water amount in each cell was evaluated by the CT reconstructed images. It was shown that a cell voltage decreased gradually when the water increased and increased rapidly when the water was evacuated. It was estimated that the power generation stopped when the channel of a cell was partly filled with the water because the air supply was blocked to a cell in the stack. (author)

  7. Development and durability of SOFC stacks

    Energy Technology Data Exchange (ETDEWEB)

    Beeaff, D.; Dinesen, A.R.; Mikkelsen, Lars; Nielsen, Karsten A.; Solvang, M.; Hendriksen, Peter V.

    2004-12-01

    The present project is a part of the Danish SOFC programme, which has the overall aim of establishing a Danish production of SOFC - cells, stacks and systems for economical and environmentally friendly power production. The aim of the present project was to develop and demonstrate (on a small scale, few cells, few thousand hours) a durable, thermally cyclable stack with high performance at 750 deg. C. Good progress towards this target has been made and demonstrated at the level of stack-elements (one cell between two interconnects) or small stacks (3 5 cells). Three different stacks or stack-elements have been operated for periods exceeding 3000 hr. The work has covered development of stack-components (seals, interconnects, coatings, contact layers), establishment of procedures for stack assembly and initiation, and detailed electrical characterisation with the aims of identifying performance limiting factors as well as long term durability. Further, post test investigations have been carried out to identify possible degradation mechanisms. (BA)

  8. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  9. On the integration of memristors with CMOS using nanoimprint lithography

    Science.gov (United States)

    Xia, Qiangfei; Tong, W. M.; Wu, W.; Yang, J. J.; Li, X.; Robinett, W.; Cardinali, T.; Cumbie, M.; Ellenson, J. E.; Kuekes, P.; Williams, R. S.

    2009-03-01

    Memristors were vertically integrated with CMOS circuits using nanoimprint lithography (NIL), making a transistor/memeristor hybrid circuit. Several planarization technologies were developed for the CMOS substrates to meet the surface planarity requirement for NIL. Accordingly, different integration schemes were developed and optimized. UV-curable NIL (UV-NIL) using a double layer spin-on resists was carried out to pattern the electrodes for memristors. This is the first demonstration of NIL on active CMOS substrates that are fabricated in a CMOS fab. Our work demonstrates that NIL is compatible with commercial IC fabrication process. It was also demonstrated that the memristors are integratable with traditional CMOS to make hybrid circuits without changing the current infrastructure in IC industry.

  10. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  11. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

    Science.gov (United States)

    De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  12. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  13. A novel colour-sensitive CMOS detector

    International Nuclear Information System (INIS)

    Langfelder, G.; Longoni, A.; Zaraga, F.

    2009-01-01

    A novel colour-sensitive semiconductor detector is proposed. The device (named Transverse Field Detector (TFD)) can be used to measure the colour of the incident light without any colour filter. The device is completely compatible with standard CMOS processes and is suitable to be integrated in a pixel array for imaging purposes. The working principle is based on the capability of this device to collect at different superficial junctions the carriers, generated at different depths, by means of suitable transverse electric fields. The transverse components of the electric field are generated inside the depleted region by a suitable bias of the superficial junctions. Thanks to the differences in the light absorption coefficients at different wavelengths, the device performs colour separation. Among the advantages of this approach are the capability of an active tuning of the pixel colour response, which can be obtained just by changing the biasing values of collecting junctions, and foreseen higher colour fidelity, thanks to the easy extension to four colour pixels. First test structures of three colours TFD pixels were designed and built in a standard CMOS 90 nm technology. Operative principles of the device and first experimental results are presented.

  14. CMOS preamplifier for low-capacitance detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gramegna, G. [Politecnico di Bari (Italy); O`Connor, P. [Brookhaven National Lab., Upton, NY (United States); Rehak, P. [Brookhaven National Lab., Upton, NY (United States); Hart, S. [Wayne State Univ. (United States)

    1997-05-01

    We present a new CMOS preamplifier and shaper, optimized for charge measurements with detectors of 0.1-1 pF capacitance. A self-adaptive biasing scheme with nonlinear pole-zero cancellation allows us to use an MOS device operated in the triode region as the DC feedback element while eliminating nonlinearity and sensitivity to supply, temperature, and process variations and accepting up to several {mu}A leakage current. The circuit is continuously sensitive and requires no external adjustments to set the feedback resistance. Secondary sources of noise are minimized subject to a power dissipation constraint. Implemented in a 1.2 {mu}m CMOS process, the preamplifier achieves an ENC of 35 e{sup -} + 58 e{sup -}/pF at 23 {mu}s shaping time at a power consumption of about 3.2 mW. The integrated preamp/shaper has 50 ns shaping time and the ENC is 120 e{sup -}. It has 0.3% nonlinearity over an input dynamic range of 0-5 fC. (orig.).

  15. Challenges of nickel silicidation in CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Breil, Nicolas [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Lavoie, Christian [IBM T.J. Watson Research Center, Yorktown Heights, NY (United States); Ozcan, Ahmet [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Baumann, Frieder [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Klymko, Nancy [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Nummy, Karen [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Sun, Bing [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Jordan-Sweet, Jean [IBM T.J. Watson Research Center, Yorktown Heights, NY (United States); Yu, Jian [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Zhu, Frank [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Narasimha, Shreesh [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States); Chudzik, Michael [IBM Semiconductor Research and Development Center (SRDC), East Fishkill, NY (United States)

    2015-04-01

    In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of the nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.

  16. A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

    Science.gov (United States)

    Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

    2016-03-03

    This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

  17. TEST ON ABCD CHIPS

    CERN Document Server

    Ferrère, D; Zsenei, A; Kaplon, J; Lacasta, C; Dabrowski, W; Kudlaty, J; Wolter, M; Azman, S

    1998-01-01

    The ABCD chip is one of the two technological options for the binary readout architecture under development for the Silicon Tracker (SCT) in ATLAS. The chip is realised in the DMILL technology (a 0.8 mum BICMOS trench isolation process). This note reports on the first results obtained at CERN on the p-type ABCD chips of the first batch delivered by TEMIC in February 1998.

  18. CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

    Science.gov (United States)

    Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

    2015-12-01

    Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

  19. The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

    Energy Technology Data Exchange (ETDEWEB)

    Aglieri Rinella, Gianluca, E-mail: gianluca.aglieri.rinella@cern.ch

    2017-02-11

    The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10{sup −5} and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm{sup 2} for the application in the Inner Barrel Layers and below 20 mW/cm{sup 2} for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported. - Highlights: • The ALPIDE chip, an innovative CMOS pixel particle detector is described. • It achieves excellent detection performance figures and very low power consumption. • The characterization of prototypes confirms the achievement of the specifications.

  20. Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

    KAUST Repository

    Shamim, Atif

    2012-07-28

    The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2-3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author\\'s best knowledge, its size of 3 mm2 is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed. © 2010 IEEE.

  1. CHIP Reporting in the CPS

    Data.gov (United States)

    U.S. Department of Health & Human Services — CHIP reporting in the CPS is unreliable. Only 10 to 30 percent of those with CHIP (but not Medicaid) report this type of coverage in the CPS. Many with CHIP report...

  2. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  3. Monolithic CMUT on CMOS Integration for Intravascular Ultrasound Applications

    Science.gov (United States)

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F. Levent

    2012-01-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter based volumetric imaging arrays where the elements need to be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom designed CMOS receiver electronics from a commercial IC foundry. The CMUT on CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT to CMOS interconnection. This CMUT to CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire bonding method. Characterization experiments indicate that the CMUT on CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Experiments on a 1.6 mm diameter dual-ring CMUT array with a 15 MHz center frequency show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging CTOs located 1 cm away from the CMUT array. PMID:23443701

  4. Lightweight Stacks of Direct Methanol Fuel Cells

    Science.gov (United States)

    Narayanan, Sekharipuram; Valdez, Thomas

    2004-01-01

    An improved design concept for direct methanol fuel cells makes it possible to construct fuel-cell stacks that can weigh as little as one-third as much as do conventional bipolar fuel-cell stacks of equal power. The structural-support components of the improved cells and stacks can be made of relatively inexpensive plastics. Moreover, in comparison with conventional bipolar fuel-cell stacks, the improved fuel-cell stacks can be assembled, disassembled, and diagnosed for malfunctions more easily. These improvements are expected to bring portable direct methanol fuel cells and stacks closer to commercialization. In a conventional bipolar fuel-cell stack, the cells are interspersed with bipolar plates (also called biplates), which are structural components that serve to interconnect the cells and distribute the reactants (methanol and air). The cells and biplates are sandwiched between metal end plates. Usually, the stack is held together under pressure by tie rods that clamp the end plates. The bipolar stack configuration offers the advantage of very low internal electrical resistance. However, when the power output of a stack is only a few watts, the very low internal resistance of a bipolar stack is not absolutely necessary for keeping the internal power loss acceptably low.

  5. Fully integrated circuit chip of microelectronic neural bridge

    Science.gov (United States)

    Xiaoyan, Shen; Zhigong, Wang

    2014-09-01

    Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-μm CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.

  6. A Vision Chip for Color Segmentation and Pattern Matching

    Directory of Open Access Journals (Sweden)

    Ralph Etienne-Cummings

    2003-06-01

    Full Text Available A 128(H × 64(V × RGB CMOS imager is integrated with region-of-interest selection, RGB-to-HSI transformation, HSI-based pixel segmentation, (36bins × 12bits-HSI histogramming, and sum-of-absolute-difference (SAD template matching. Thirty-two learned color templates are stored and compared to each image. The chip captures the R, G, and B images using in-pixel storage before passing the pixel content to a multiplying digital-to-analog converter (DAC for white balancing. The DAC can also be used to pipe in images for a PC. The color processing uses a biologically inspired color opponent representation and an analog lookup table to determine the Hue (H of each pixel. Saturation (S is computed using a loser-take-all circuit. Intensity (I is given by the sum of the color components. A histogram of the segments of the image, constructed by counting the number of pixels falling into 36 Hue intervals of 10 degrees, is stored on a chip and compared against the histograms of new segments using SAD comparisons. We demonstrate color-based image segmentation and object recognition with this chip. Running at 30 fps, it uses 1 mW. To our knowledge, this is the first chip that integrates imaging, color segmentation, and color-based object recognition at the focal plane.

  7. Solid Oxide Fuel Cell Stack Diagnostics

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Barfod, Rasmus Gottrup

    . An operating stack is subject to compositional gradients in the gaseous reactant streams, and temperature gradients across each cell and across the stack, which complicates detailed analysis. Several experimental stacks from Topsoe Fuel Cell A/S were characterized using Electrochemical Impedance Spectroscopy...... (EIS). The stack measurement geometry was optimized for EIS by careful selection of the placement of current feeds and voltage probes in order to minimize measurement errors. It was demonstrated that with the improved placement of current feeds and voltage probes it is possible to separate the loss...... in the hydrogen fuel gas supplied to the stack. EIS was used to examine the long-term behavior and monitor the evolution of the impedance of each of the repeating units and the whole stack. The observed impedance was analyzed in detail for one of the repeating units and the whole stack and the losses reported...

  8. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  9. CHIP, CHIP, ARRAY! THREE CHIPS FOR POST-GENOMIC RESEARCH

    Science.gov (United States)

    Cambridge Healthtech Institute recently held the 4th installment of their popular "Lab-on-a-Chip" series in Zurich, Switzerland. As usual, it was enthusiastically received and over 225 people attended the 2-1/2 day meeting to see and hear about some of the latest developments an...

  10. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    Science.gov (United States)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  11. InP-DHBT-on-BiCMOS technology with fT/fmax of 400/350 GHz for heterogeneous integrated millimeter-wave sources

    DEFF Research Database (Denmark)

    Kraemer, Tomas; Ostermay, Ina; Jensen, Thomas

    2013-01-01

    This paper presents a novel InP-SiGe BiCMOS technology using wafer-scale heterogeneous integration. The vertical stacking of the InP double heterojunction bipolar transistor (DHBT) circuitry directly on top of the BiCMOS wafer enables ultra-broadband interconnects with ...-100 GHz. The 0.8 × 5 μm2 InP DHBTs show fT/fmax of 400/350 GHz with an output power of more than 26 mW at 96 GHz. These are record values for a heterogeneously integrated transistor on silicon. As a circuit example, a 164-GHz signal source is presented. It features a voltage-controlled oscillator in Bi...

  12. A Cytomorphic Chip for Quantitative Modeling of Fundamental Bio-Molecular Circuits.

    Science.gov (United States)

    2015-08-01

    We describe a 0.35 μm BiCMOS silicon chip that quantitatively models fundamental molecular circuits via efficient log-domain cytomorphic transistor equivalents. These circuits include those for biochemical binding with automatic representation of non-modular and loading behavior, e.g., in cascade and fan-out topologies; for representing variable Hill-coefficient operation and cooperative binding; for representing inducer, transcription-factor, and DNA binding; for probabilistic gene transcription with analogic representations of log-linear and saturating operation; for gain, degradation, and dynamics of mRNA and protein variables in transcription and translation; and, for faithfully representing biological noise via tunable stochastic transistor circuits. The use of on-chip DACs and ADCs enables multiple chips to interact via incoming and outgoing molecular digital data packets and thus create scalable biochemical reaction networks. The use of off-chip digital processors and on-chip digital memory enables programmable connectivity and parameter storage. We show that published static and dynamic MATLAB models of synthetic biological circuits including repressilators, feed-forward loops, and feedback oscillators are in excellent quantitative agreement with those from transistor circuits on the chip. Computationally intensive stochastic Gillespie simulations of molecular production are also rapidly reproduced by the chip and can be reliably tuned over the range of signal-to-noise ratios observed in biological cells.

  13. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  14. Development of a CMOS process using high energy ion implantation

    International Nuclear Information System (INIS)

    Stolmeijer, A.

    1986-01-01

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  15. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  16. A low-noise wide dynamic range CMOS image sensor with low and high temperatures resistance

    Science.gov (United States)

    Mizobuchi, Koichi; Adachi, Satoru; Tejada, Jose; Oshikubo, Hiromichi; Akahane, Nana; Sugawa, Shigetoshi

    2008-02-01

    A temperature-resistant 1/3 inch SVGA (800×600 pixels) 5.6 μm pixel pitch wide-dynamic-range (WDR) CMOS image sensor has been developed using a lateral-over-flow-integration-capacitor (LOFIC) in a pixel. The sensor chips are fabricated through 0.18 μm 2P3M process with totally optimized front-end-of-line (FEOL) & back-end-of-line (BEOL) for a lower dark current. By implementing a low electrical field potential design for photodiodes, reducing damages, recovering crystal defects and terminating interface states in the FEOL+BEOL, the dark current is improved to 12 e - /pixel-sec at 60 deg.C with 50% reduction from the previous very-low-dark-current (VLDC) FEOL and its contribution to the temporal noise is improved. Furthermore, design optimizations of the readout circuits, especially a signal-and noise-hold circuit and a programmable-gain-amplifier (PGA) are also implemented. The measured temporal noise is 2.4 e -rms at 60 fps (:36 MHz operation). The dynamic-range (DR) is extended to 100 dB with 237 ke - full well capacity. In order to secure the temperature-resistance, the sensor chip also receives both an inorganic cap onto micro lens and a metal hermetic seal package assembly. Image samples at low & high temperatures show significant improvement in image qualities.

  17. Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

    CERN Document Server

    Tsirimokou, Georgia; Elwakil, Ahmed

    2017-01-01

    This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...

  18. Low-noise CMOS preamplifier-shaper for silicon drift detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gramegna, G. [Brookhaven National Lab., Upton, NY (United States); O`Connor, P.; Rehak, P. [Politecnico di Bari (Italy); Hart, S. [Wayne State Univ., Detroit, MI (United States)

    1996-12-31

    We have designed a 16-channel preamplifier-shaper for particle tracking using silicon drift detectors (SDD). The preamplifier, which is optimized for a detector capacitance of 0.2 - 0.8 pF, uses two new circuit techniques to achieve a low noise (ENC 120 e- + 62 e-/pF), high linearity (< 0.5% to 50 fC), and good tolerance to process variations and temperature and power supply fluctuations. The circuit is continuously sensitive, has no digital signals on chip, and requires no external components or critical adjustments. The peaking time of the shaper is 50 nsec and the power dissipation, including an off-chip driver, is 6.5 mW/channel. The circuit is fabricated in 1.2 um CMOS and can accommodate detector leakage currents of up to 1.5 uA. Although the circuit was developed for use with particle tracking detectors, these techniques are also well-suited for the design of lower-noise preamplifiers for high-resolution X-ray spectroscopy systems.

  19. CMOS analog baseband circuitry for an IEEE 802.11 b/g/n WLAN transceiver

    International Nuclear Information System (INIS)

    Gong Zheng; Chu Xiaojie; Shi Yin; Lei Qianqian; Lin Min

    2012-01-01

    An analog baseband circuit for a direct conversion wireless local area network (WLAN) transceiver in a standard 0.13-μm CMOS occupying 1.26 mm 2 is presented. The circuit consists of active-RC receiver (RX) 4th order elliptic lowpass filters(LPFs), transmit (PGAs) with DC offset cancellation (DCOC) servo loops, and on-chip output buffers. The RX baseband gain can be programmed in the range of −11 to 49 dB in 2 dB steps with 50–30.2 nV/√Hz input referred noise (IRN) and a 21 to −41 dBm in-band 3rd order interception point (IIP3). The RX/TX LPF cutoff frequencies can be switched between 5 MHz, 10 MHz, and 20 MHz to fulfill the multimode 802.11b/g/n requirements. The TX baseband gain of the I/Q paths are tuned separately from −1.6 to 0.9 dB in 0.1 dB steps to calibrate TX I/Q gain mismatches. By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array, the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply. (semiconductor integrated circuits)

  20. CMOS analog baseband circuitry for an IEEE 802.11 b/g/n WLAN transceiver

    Science.gov (United States)

    Zheng, Gong; Xiaojie, Chu; Qianqian, Lei; Min, Lin; Yin, Shi

    2012-11-01

    An analog baseband circuit for a direct conversion wireless local area network (WLAN) transceiver in a standard 0.13-μm CMOS occupying 1.26 mm2 is presented. The circuit consists of active-RC receiver (RX) 4th order elliptic lowpass filters(LPFs), transmit (PGAs) with DC offset cancellation (DCOC) servo loops, and on-chip output buffers. The RX baseband gain can be programmed in the range of -11 to 49 dB in 2 dB steps with 50-30.2 nV/√Hz input referred noise (IRN) and a 21 to -41 dBm in-band 3rd order interception point (IIP3). The RX/TX LPF cutoff frequencies can be switched between 5 MHz, 10 MHz, and 20 MHz to fulfill the multimode 802.11b/g/n requirements. The TX baseband gain of the I/Q paths are tuned separately from -1.6 to 0.9 dB in 0.1 dB steps to calibrate TX I/Q gain mismatches. By using an identical integrator based elliptic filter synthesis method together with global compensation applied to the LPF capacitor array, the power consumption of the RX LPF is considerably reduced and the proposed chip draws 26.8 mA/8 mA by the RX/TX baseband paths from a 1.2 V supply.

  1. A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC

    Science.gov (United States)

    Yijun, Song; Wenyuan, Li

    2014-06-01

    A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 μm CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which canperform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within ±0.28 LSB and ±0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 mW.

  2. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  3. Design trade-off between spatial resolution and power consumption in CMOS biosensor circuit based on millimeter-wave LC oscillator array

    Science.gov (United States)

    Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

    2018-03-01

    In this paper, we describe a trade-off between spatial resolution and power consumption in an LC oscillator-based CMOS biosensor, which can detect biomolecules by observing the resonance frequency shift due to changes in the complex permittivity of the biomolecules. The optimal operating frequency and improvement in the image resolution of the sensor output require a reduction in the size of the inductor. However, it is necessary to increase the transconductance of the cross-coupling transistor to achieve the oscillation condition, although the power consumption increases. We confirmed the trade-off between the spatial resolution and the power consumption of this sensor using SPICE simulation. A test chip was fabricated using a 65 nm CMOS process, and the transition in the peak frequency and the power consumption were measured. When the outer diameter of the inductor was 46 µm, the power consumption was 31.2 mW, which matched well with the simulation results.

  4. Noise Properties of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1996-01-01

    model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model...... is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current...... sources, and with the class AB design the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current...

  5. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  6. An Associative Memory Chip for the Trigger System of the ATLAS Experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00380893; The ATLAS collaboration; Liberali, Valentino; Crescioli, Francesco; Beretta, Matteo; Frontini, Luca; Annovi, Alberto; Stabile, Alberto

    2016-01-01

    The AM06 is the 6th version of a large associative memory chip designed in 65 nm CMOS tech- nology. The AM06 operates as a highly parallel ASIC processor for pattern recognition in the ATLAS experiment at CERN. It is the core of the Fast TracKer electronic system, which is tai- lored for on-line track finding in the trigger system of the ATLAS experiment. The Fast TracKer system is able to process events up to 100 MHz in real time. The AM06 is a complex chip, and it has been designed combining full-custom memory arrays, standard logic cells and IP blocks. It contains memory banks that store data organized in 18 bit words; a group of 8 words is called a pattern. The chip silicon area is 168 mm2; it contains 421 millions of transistors and it stores 217 patterns. Moreover, the associative memory is suitable also for other interdisciplinary appli- cations (i.e., general purpose image filtering and analysis). In the near future we plan to design a more powerful and flexible chip in 28 nm CMOS technology.

  7. Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

    CERN Document Server

    Llopart Cudie, Xavier; Campbell, M

    2007-01-01

    Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

  8. Seismic (SSE) evaluation for the 291Z stack at the Hanford Site -- Addition of environmental monitoring penetrations

    International Nuclear Information System (INIS)

    Baxter, J.T.

    1994-01-01

    The purpose of this 291Z stack analysis is to determine the structural effects of chipping additional holes into the stacks concrete walls. The proposed holes are for new environmental monitoring sample probes to be installed at three different elevations. The approximate elevations proposed at this time are 50 ft, 135 ft and 175 ft. There will be four holes required at each of the elevations to support two sample probes extending across the diameter of the stack. A structural sensitivity study has been completed to assess the effect of the proposed holes on the baseline seismic qualification of the stack completed by URS/John A. Blume ampersand Associates, Engineers, San Francisco, California (URS/Blume) in August, 1988. Results of the sensitivity study indicate that the stack would still have adequate structural moment capacity if the new holes were drilled cutting the vertical strength reinforcing steel, or if existing penetrations added since original construction have inadvertently cut vertical rebars. For current and future modifications, no vertical rebar should be cut. A limited number of horizontal rebar, no more than 2, may be cut at the new hole locations without significantly influencing the stack structural shear capacity. New penetrations in the 291Z stack should not be located below elevation 47 ft., 4 in. due to rebar layout and the fact that maximum seismic structural loads occur below this elevation. No vertical rebar should be cut when chipping the new penetrations in the stack concrete wall for the environmental monitoring equipment. Wind load qualification was reviewed. Seismic loads govern over wind loads for all structural load cases; therefore no additional wind analyses are required

  9. Germanium CMOS potential from material and process perspectives: Be more positive about germanium

    Science.gov (United States)

    Toriumi, Akira; Nishimura, Tomonori

    2018-01-01

    practically viable, we need to understand why electron mobility is severely degraded in the inversion layer in Ge n-channel MOSFETs and to find out how it can be increased. In the Si CMOS technology, the SiO2/Si interface has long been investigated and cannot be ignored even after the introduction of high-k gate stack technology. In that sense, the GeO2/Ge interface should be intensively studied to make the best of Ge’s advantages. Therefore we first discuss the GeO2/Ge interface with regard to its physical and electrical characteristics. When we regard Ge as a channel material beyond Si for high performance ULSIs, we also have to seriously consider the gate stack scalability and reliability. The source/drain engineering, as well as the gate stack formation, is another challenge in Ge MOSFET design. Both the higher metal/Ge contact resistance and the larger p/n junction leakage current may be the consequences of Ge’s intrinsic properties because they are derived from the strong Fermi-level pinning and the narrow energy band gap, respectively. Even if the carrier transport in the channel may be ideally ballistic, these properties should degrade FET properties. The narrower energy band gap of Ge is often addressed, but the higher dielectric constant of Ge is rarely discussed. This is also the case for most of the other high-mobility materials. The dielectric constant is directly and negatively related to short-channel effects, and we have not been able to provide a substantial solution to overcome this hardship. We have to keep this in mind for the short-channel FET operation. Although a number of problems remain to be solved, in this paper, we view the current status of Ge FET technology positively. A number of (but not all) Ge-related challenges have been overcome in the past 10 years, which seems to be a good time to summarize the status of Ge technology, particularly materials engineering aspects rather than device integration issues. Since we cannot cover all of the

  10. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    consideration. In this work, delay and power metrics for both MCML and CMOS have been studied and a broader analysis of MCML is presented. Near minimum sized transistors are used and power consumption is measured for a wide variety of circuit blocks. The most important goal of this project is to evaluate......Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand...

  11. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  12. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

    Science.gov (United States)

    Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

    2016-12-31

    Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  13. Depleted CMOS pixels for LHC proton–proton experiments

    International Nuclear Information System (INIS)

    Wermes, N.

    2016-01-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  14. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  15. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  17. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation hardened CMOS devices and circuits - LDRD Project (FY99)

    International Nuclear Information System (INIS)

    Myers, David R.; Jessing, Jeffrey R.; Spahn, Olga B.; Shaneyfelt, Marty R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

  18. Vertically stacked nanocellulose tactile sensor.

    Science.gov (United States)

    Jung, Minhyun; Kim, Kyungkwan; Kim, Bumjin; Lee, Kwang-Jae; Kang, Jae-Wook; Jeon, Sanghun

    2017-11-16

    Paper-based electronic devices are attracting considerable attention, because the paper platform has unique attributes such as flexibility and eco-friendliness. Here we report on what is claimed to be the firstly fully integrated vertically-stacked nanocellulose-based tactile sensor, which is capable of simultaneously sensing temperature and pressure. The pressure and temperature sensors are operated using different principles and are stacked vertically, thereby minimizing the interference effect. For the pressure sensor, which utilizes the piezoresistance principle under pressure, the conducting electrode was inkjet printed on the TEMPO-oxidized-nanocellulose patterned with micro-sized pyramids, and the counter electrode was placed on the nanocellulose film. The pressure sensor has a high sensitivity over a wide range (500 Pa-3 kPa) and a high durability of 10 4 loading/unloading cycles. The temperature sensor combines various materials such as poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS), silver nanoparticles (AgNPs) and carbon nanotubes (CNTs) to form a thermocouple on the upper nanocellulose layer. The thermoelectric-based temperature sensors generate a thermoelectric voltage output of 1.7 mV for a temperature difference of 125 K. Our 5 × 5 tactile sensor arrays show a fast response, negligible interference, and durable sensing performance.

  19. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    Science.gov (United States)

    Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

    2016-01-01

    Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

  20. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    Directory of Open Access Journals (Sweden)

    Sukanta Roy

    Full Text Available Micro-electro mechanical system (MEMS based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM. A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

  1. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  2. Generalized data stacking programming model with applications

    Directory of Open Access Journals (Sweden)

    Hala Samir Elhadidy

    2016-09-01

    Full Text Available Recent researches have shown that, everywhere in various sciences the systems are following stacked-based stored change behavior when subjected to events or varying environments “on and above” their normal situations. This paper presents a generalized data stack programming (GDSP model which is developed to describe the system changes under varying environment. These changes which are captured with different ways such as sensor reading are stored in matrices. Extraction algorithm and identification technique are proposed to extract the different layers between images and identify the stack class the object follows; respectively. The general multi-stacking network is presented including the interaction between various stack-based layering of some applications. The experiments prove that the concept of stack matrix gives average accuracy of 99.45%.

  3. Charged particle detection performances of CMOS pixel sensors produced in a 0.18μm process with a high resistivity epitaxial layer

    Energy Technology Data Exchange (ETDEWEB)

    Senyukov, S., E-mail: serhiy.senyukov@cern.ch; Baudot, J.; Besson, A.; Claus, G.; Cousin, L.; Dorokhov, A.; Dulinski, W.; Goffe, M.; Hu-Guo, C.; Winter, M.

    2013-12-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50μm thin CMOS Pixel Sensors (CPS) covering either the three innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35μm CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJazz0.18μm CMOS process were studied with the help of the first prototype chip MIMOSA 32. The beam tests performed with negative pions of 120 GeV/c at the CERN-SPS allowed to measure a signal-to-noise ratio (SNR) for the non-irradiated chip in the range between 22 and 32 depending on the pixel design. The chip irradiated with the combined dose of 1 MRad and 10{sup 13}n{sub eq}/cm{sup 2} was observed to yield an SNR ranging between 11 and 23 for coolant temperatures varying from 15 °C to 30 °C. These SNR values were measured to result in particle detection efficiencies above 99.5% and 98% before and after irradiation, respectively. These satisfactory results allow to validate the TowerJazz0.18μm CMOS process for the ALICE ITS upgrade.

  4. Trigger Data Serializer ASIC chip for the ATLAS New Small Wheel sTGC Detector

    Science.gov (United States)

    Meng, Xiangting; Wang, Jinhong; Guan, Liang; Sang, Ziru; Chapman, John; Zhou, Bing; Zhu, Junjie

    2015-04-01

    The small-strip thin-gap chambers (sTGC) will be used as the trigger device for the Phase-I upgrade of the ATLAS new small wheel (nSW) muon detector. An Application-Specific Integrated Circuit (ASIC) chip is needed to collect digital signals from both pad and strip detectors and serialize the outputs to the circuitry located on the rim of the nSW. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (speed output data rate (4.8 Gbps), harsh radiation environment (about 300 kRad), and low power consumption (<1 W) impose great challenges for the design of this ASIC chip using the IBM 130 nm CMOS process. We will present our design and test results based on the prototype chip we build.

  5. A system-on-chip digital pH meter for use in a wireless diagnostic capsule.

    Science.gov (United States)

    Hammond, Paul A; Ali, Danish; Cumming, David R S

    2005-04-01

    This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units.

  6. Development of a low-cost 2.5-Gbps SFP optical transceiver using 0.18μm CMOS ICs

    Science.gov (United States)

    Chai, Yi Yoon; Zhang, Jing; Ramana, Pamidighantma V.; Yap, Guan Jie; Lau, John Hon-Shing

    2008-02-01

    The high cost of optoelectronics components typically used for long-haul communication is prohibitive in the Fiber to the Home (FTTH) and Passive Optical Networks (PONs). One method of cost reduction is through the reducing the cost of the electronics in the transceiver and reducing the packaging cost. We report the development of low-cost 2.5-Gbps optical transceiver for Gigabit Passive Optical Network (GPON) using CMOS driver ICs and chip-on-board assembly method. We developed the Laser Diode Driver (LDD), Trans-impedance Amplifier (TIA), Limiting Amplifier (LA) and the Clock and Data Recovery (CDR) using CMOS technology for short reach application and developed the burst mode version of the ICs for PON applications. The ICs are designed in house and fabricated on a standard CMOS 8" wafer with 0.18μm technology. The devices operate at 1.8V and are low power in nature, thus reducing the demand on power dissipation. The transceiver consists of an un-cooled and direct modulated laser diode driven with a LDD, a high speed PIN photo-diode with amplifier and CMOS ICs. The bare CMOS ICs are attached on a transceiver substrate that is compliant with the small form-factor pluggable (SFP) package multisource agreement (MSA) and coupled to a 1310nm FP laser TOSA and a PIN ROSA with LC connector. The integrated transceiver is characterized up to 2.5-Gbps. In this publication, we present the detail of the module development, assembly methods and performance characterization at 1310nm.

  7. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  8. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  9. Modeling and simulation of TDI CMOS image sensors

    Science.gov (United States)

    Nie, Kai-ming; Yao, Su-ying; Xu, Jiang-tao; Gao, Jing

    2013-09-01

    In this paper, a mathematical model of TDI CMOS image sensors was established in behavioral level through MATLAB based on the principle of a TDI CMOS image sensor using temporal oversampling rolling shutter in the along-track direction. The geometric perspective and light energy transmission relationships between the scene and the image on the sensor are included in the proposed model. A graphical user interface (GUI) of the model was also established. A high resolution satellitic picture was used to model the virtual scene being photographed. The effectiveness of the proposed model was verified by computer simulations based on the satellitic picture. In order to guide the design of TDI CMOS image sensors, the impacts of some parameters of TDI CMOS image sensors including pixel pitch, pixel photosensitive size, and integration time on the performance of the sensors were researched through the proposed model. The impacts of the above parameters on the sensors were quantified by sensor's modulation transfer function (MTF) of the along-track direction, which was calculated by slanted-edge method. The simulation results indicated that the TDI CMOS image sensor can get a better performance with smaller pixel photosensitive size and shorter integration time. The proposed model is useful in the process of researching and developing a TDI CMOS image sensor.

  10. Flexural characteristics of a stack leg

    International Nuclear Information System (INIS)

    Cook, J.

    1979-06-01

    A 30 MV tandem Van de Graaff accelerator is at present under construction at Daresbury Laboratory. The insulating stack of the machine is of modular construction, each module being 860 mm in length. Each live section stack module contains 8 insulating legs mounted between bulkhead rings. The design, fabrication (from glass discs bonded to stainless steel discs using an epoxy film adhesive) and testing of the stack legs is described. (U.K.)

  11. Hydrogen Embrittlement And Stacking-Fault Energies

    Science.gov (United States)

    Parr, R. A.; Johnson, M. H.; Davis, J. H.; Oh, T. K.

    1988-01-01

    Embrittlement in Ni/Cu alloys appears related to stacking-fault porbabilities. Report describes attempt to show a correlation between stacking-fault energy of different Ni/Cu alloys and susceptibility to hydrogen embrittlement. Correlation could lead to more fundamental understanding and method of predicting susceptibility of given Ni/Cu alloy form stacking-fault energies calculated from X-ray diffraction measurements.

  12. Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers

    Directory of Open Access Journals (Sweden)

    Hyoungho Ko

    2010-11-01

    Full Text Available In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g~389 mV/g, the output nonlinearity of 0.43% FSO~0.60% FSO, the input range of ±2 g and a bias instability of 122 μg~229 μg. The signal-to-noise ratio and the noise equivalent resolution are measured to be74.00 dB~75.23 dB and 180 μg/rtHz~190 μg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%~1.9% and 0.3%~0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics.

  13. Development of a compact electronic dosemeter from CMOS sensor for radon measurement; Developpement d'un dosimetre electronique compact a base de capteurs CMOS pour la mesure du radon

    Energy Technology Data Exchange (ETDEWEB)

    Higueret, St

    2007-12-15

    Radon detection is a long-standing challenge in the field of radioprotection, and the IPHC Institute of Strasbourg has pushed for the development of a fully electronic device, portable and really standalone. Our first prototype of CMOS system-on-chip is presented, together with efficiency tests and the corresponding physics simulations (TRIM, GEANT IV). We describe several electronic boards which have been developed for various kinds of tests, firstly passive detection of {alpha}-particles from gaseous {sup 222}Rn in a large spectrum of activity concentrations. In a second stage, active collection of the daughter isotopes {sup 218}Po and {sup 214}Po was performed: these elements, appearing as attached on the aerosols present in air, are an important contribution to internal {alpha}-irradiation. The final electronic system, of only 10 cm size, includes four independent chips to ensure simultaneous detection of radon gas and its aerosols. An excellent linearity has been measured up to 80 kBq.m{sup -3} on the BACCARA bench of the IRSN at Saclay. A new generation chip is also studied. (author)

  14. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

  15. Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  16. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  17. Stacks of SPS Dipole Magnets

    CERN Multimedia

    1974-01-01

    Stacks of SPS Dipole Magnets ready for installation in the tunnel. The SPS uses a separated function lattice with dipoles for bending and quadrupoles for focusing. The 6.2 m long normal conducting dipoles are of H-type with coils that are bent-up at the ends. There are two types, B1 (total of 360) and B2 (384). Both are for a maximum field of 1.8 Tesla and have the same outer dimensions (450x800 mm2 vxh) but with different gaps (B1: 39x129 mm2, B2: 52x92 mm2) tailored to the beam size. The yoke, made of 1.5 mm thick laminations, consists of an upper and a lower half joined together in the median plane once the coils have been inserted.

  18. California dreaming?[PEM stacks

    Energy Technology Data Exchange (ETDEWEB)

    Crosse, J.

    2002-06-01

    Hyundai's Santa Fe FCEV will be on sale by the end of 2002. Hyundai uses PEM stacks that are manufactured by International Fuel Cells (IFC), a division of United Technologies. Santa Fe is equipped with a 65 kW electric powertrain of Enova systems and Shell's new gasoline reformer called Hydrogen Source. Eugene Jang, Senior Engineer - Fuel Cell and Materials at Hyundai stated that the compressor related losses on IFC system are below 3%. The maximum speed offered by the vehicle is estimated as 123km/hr while the petrol equivalent fuel consumption is quoted between 5.6L/100 km and 4.8L/100 km. Santa Fe is a compact vehicle offering better steering response and a pleasant drive. (author)

  19. CARIOCA : A Fast Binary Front-End Implemented in 0.25Pm CMOS using a Novel Current-Mode Technique for the LHCb Muon Detector

    CERN Multimedia

    2000-01-01

    The CARIOCA front-end is an amplifier discriminator chip, using 0.25mm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10W. Measurements showed a peaking time of 14ns and noise of 450e- at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC remains almost unchanged up to a detector capacitance of 120pF.

  20. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-03-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  1. コモンセントロイド配置によるCMOS OTAのCMRR改善効果の評価

    OpenAIRE

    澤本, 岳秀; 桑原, 浩一; 谷本, 洋; 原口, 大; SAWAMOTO, Takehide; KUWAHARA, Koichi; TANIMOTO, Hiroshi; HARAGUCHI, Masaru

    2010-01-01

    Common-mode rejection ratio (CMRR) deviation due to mismatching among MOS transistors in feedforward type OTA has been evaluated for chips fabricated with and without common-centroid layout technique. The mesured common-mode voltage gain (CMVG) data for 10 samples are evaluated by averaged CMVG and its relative variation to input common-mode dc bias point. The results clearly indicate the effectiveness of the common-centroid layout for an OTA in OTA in an 0.15 μm CMOS process to have better C...

  2. Resistance to radiation of a 0.8 μm CMOS VLSI readout of instrumentation for accelerators used in tumor therapy

    International Nuclear Information System (INIS)

    Cirio, R.; Bonazzola, G.; Dogiorgis, G.; Marchetto, F.; Peroni, C.; Donetti, M.; Marietti, M.

    1999-01-01

    This paper shows the results of irradiations with photons and neutrons of a Very Large Scale Integration (VLSI) CMOS AMS 0.8μm chip used in medical physics applications. It has been designed as readout of dosimeters and monitor chambers used on electron/photon and proton/carbon ions for tumor therapy. The chip is located close to the detectors and it is thus used in a radioactive environment. We have performed measurements on 30 MV X-rays, fast and thermal neutrons. The chip behaves well (i.e. the gain variations are below 1%) up to X- ray doses of 75 krad and a total fast neutron number of 4*10 12 . This allows the use of the chip over several years (>5) without performance modifications. It has to be noticed that in real life the dose rates are much lower than during the tests, allowing a self-repairing of the chip with annealing. No Single Event Effect was observed up to 10 10 neutrons. (authors)

  3. Chip to System Testability

    National Research Council Canada - National Science Library

    McNamer, Michael

    1997-01-01

    The ultimate objective of the Chip-to-System Testability program was the development of a structured testability implementation methodology which will be used as a basis for a PC-based tool called TESPAD...

  4. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states and...

  5. Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

    Science.gov (United States)

    Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

    2013-08-01

    This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

  6. A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications †

    Science.gov (United States)

    Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Muroyama, Masanori

    2017-01-01

    Robot tactile sensation can enhance human–robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as “sensor platform LSI”) as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated. PMID:29061954

  7. A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications.

    Science.gov (United States)

    Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Nonomura, Yutaka; Muroyama, Masanori

    2017-08-28

    Robot tactile sensation can enhance human-robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as "sensor platform LSI") as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated.

  8. High Inductance Coil Embedded on Magnetic Sensor Chip for Biomagnetic Signal Measurements

    Science.gov (United States)

    Lyu, Hyunjune; Choi, Jun Rim

    2013-09-01

    For the purpose of biomagnetic measurements, a magnetic sensor chip is manufactured using a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. A high-inductance coil and an instrumentation amplifier (IA) are embedded on this chip. The embedded high-inductance coil sensor contains suitable sensitivity and bandwidth for biomagnetic measurements, and is designed via electromagnetic field simulation. A low-gm operational transconductance amplifier (OTA) is also implemented on the chip to reduce the transconductance value. The output signal sensitivity of the magnetic sensor chip is 3.25 fT/μV, and the output reference noise is $21.1 fT/\\sqrtHz. The instrumentation amplifier is designed to minimize the magnetic signal noise using current feedback and a band-pass filter (BPF) with a bandwidth between 0.5 kHz and 5 kHz. The common-mode rejection ratio (CMRR) is measured at 117.5 dB by the Multi-Project Chip test. The proposed magnetic sensor chip is designed such that the input reference noise is maintained below 0.87 μV.

  9. Development of a CMOS SOI pixel detector

    CERN Document Server

    Ishino, Hirokazu; Hazumi, M; Ikegami, Y; Kohriki, T; Tajima, O; Terada, S; Tsuboyama, T; Unno, Y; Ushiroda, Y; Ikeda, H; Hara, K; Ishino, H; Kawasaki, T; Miyake, H; Martin, E; Varner, G; Tajima, H; Ohno, M; Fukuda, K; Komatsubara, H; Ida, J

    2007-01-01

    We have developed a monolithic radiation pixel detector using silicon on insulator (SOI) with a commercial 0.15 m fullydepleted- SOI technology and a Czochralski high resistivity silicon substrate in place of a handle wafer. The SOI TEG (Test Element Group) chips with a size of 2.5 x 2.5mm2 consisting of 20 x 20 um2 pixels have been designed and manufactured. Performance tests with a laser light illumination and a . ray radioactive source indicate successful operation of the detector. We also brie y discuss the back gate effect as well as the simulation study.

  10. Large-area CMOS solid-state photomultipliers and recent developments

    Energy Technology Data Exchange (ETDEWEB)

    Johnson, Erik B., E-mail: ejohnson@rmdinc.com [Radiation Monitoring Devices, Inc., 44 Hunt Street, Watertown, MA 02472 (United States); Stapels, Christopher J.; Xiao Jiechen [Radiation Monitoring Devices, Inc., 44 Hunt Street, Watertown, MA 02472 (United States); Augustine, Frank L. [Augustine Engineering, 2115 Park Dale Lane, Encinitas, CA 92024 (United States); Christian, James F. [Radiation Monitoring Devices, Inc., 44 Hunt Street, Watertown, MA 02472 (United States)

    2011-10-01

    The CMOS solid-state photomultiplier (SSPM) is an array of Geiger avalanche photodiodes (GPD) read out in parallel. These devices are not susceptible to magnetic fields, less expensive to fabricate than many other photodetector technologies, compact, and allow for on-chip integration of signal processing circuits. A number of nuclear detection applications require detector sizes on the order of 1 cm. Standard silicon fabrication technology limits the size of the SSPM die, and tiling of the silicon die can result in large-area devices but results in dead space between die for bonding purposes. Radiation Monitoring Devices (RMD) has fabricated 1x1 cm SSPM arrays on a single die. The size of these devices is large enough to provide an alternative detector for scintillation detector applications compared to photomultiplier tubes. Although the size increases the dark noise, we will demonstrate that the large-area SSPM can provide a PMT-like response for {sup 22}Na gamma rays using an LYSO crystal. Each of the noise terms associated with the large-area SSPM is discussed, quantifying the cross talk and after pulse multipliers, which are scaling factors to the gain to account for the additional output charge from the SSPM. The excess noise factor associated with cross talk and after pulsing has a linear dependence on the multiplier term. The signal and noise terms have been compiled to provide the best operating voltage of roughly 6 V above breakdown for a 1x1 cm CMOS SSPM to be operated with a short integration time (<10 ns) and at 0 deg. C.

  11. Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

    Science.gov (United States)

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

    2011-12-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

  12. Vector Fields and Flows on Differentiable Stacks

    DEFF Research Database (Denmark)

    A. Hepworth, Richard

    2009-01-01

    This paper introduces the notions of vector field and flow on a general differentiable stack. Our main theorem states that the flow of a vector field on a compact proper differentiable stack exists and is unique up to a uniquely determined 2-cell. This extends the usual result on the existence...... of vector fields....

  13. 40 CFR 61.44 - Stack sampling.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 8 2010-07-01 2010-07-01 false Stack sampling. 61.44 Section 61.44 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL... Firing § 61.44 Stack sampling. (a) Sources subject to § 61.42(b) shall be continuously sampled, during...

  14. Learning OpenStack networking (Neutron)

    CERN Document Server

    Denton, James

    2014-01-01

    If you are an OpenStack-based cloud operator with experience in OpenStack Compute and nova-network but are new to Neutron networking, then this book is for you. Some networking experience is recommended, and a physical network infrastructure is required to provide connectivity to instances and other network resources configured in the book.

  15. Project W-420 stack monitoring system upgrades

    International Nuclear Information System (INIS)

    CARPENTER, K.E.

    1999-01-01

    This project will execute the design, procurement, construction, startup, and turnover activities for upgrades to the stack monitoring system on selected Tank Waste Remediation System (TWRS) ventilation systems. In this plan, the technical, schedule, and cost baselines are identified, and the roles and responsibilities of project participants are defined for managing the Stack Monitoring System Upgrades, Project W-420

  16. On the "stacking fault" in copper

    NARCIS (Netherlands)

    Fransens, J.R.; Pleiter, F

    2003-01-01

    The results of a perturbed gamma-gamma angular correlations experiment on In-111 implanted into a properly cut single crystal of copper show that the defect known in the literature as "stacking fault" is not a planar faulted loop but a stacking fault tetrahedron with a size of 10-50 Angstrom.

  17. Status of MCFC stack technology at IHI

    Energy Technology Data Exchange (ETDEWEB)

    Hosaka, M.; Morita, T.; Matsuyama, T.; Otsubo, M. [Ishikawajima-Harima Heavy Industries Co., Ltd., Tokyo (Japan)

    1996-12-31

    The molten carbonate fuel cell (MCFC) is a promising option for highly efficient power generation possible to enlarge. IHI has been studying parallel flow MCFC stacks with internal manifolds that have a large electrode area of 1m{sup 2}. IHI will make two 250 kW stacks for MW plant, and has begun to make cell components for the plant. To improve the stability of stack, soft corrugated plate used in the separator has been developed, and a way of gathering current from stacks has been studied. The DC output potential of the plant being very high, the design of electric insulation will be very important. A 20 kW short stack test was conducted in 1995 FY to certificate some of the improvements and components of the MW plant. These activities are presented below.

  18. Two- and multi-terminal CMOS/BiCMOS Si LED’s

    Science.gov (United States)

    du Plessis, Monuko; Aharoni, Herzl; Snyman, Lukas W.

    2005-02-01

    Silicon is an indirect bandgap material, but light emission is observed from reverse biased pn junctions. Even though the quantum efficiency is low, it may still be advantageous to use these devices in all-silicon optoelectronic integrated circuits (OICs). In this paper new research results with regard to low-voltage field emission BiCMOS and CMOS two- and multi-terminal Si LEDs are presented. The differences observed between avalanche and low-voltage field emission LED performance are presented. It is shown that the low-voltage devices exhibit a square-law light intensity vs. reverse current non-linearity at low-current levels, but a linear dependency at higher currents, compared to the linear behaviour of avalanche devices at all current levels. The detail spectral characteristics of the field emission devices are investigated, showing that in the non-linear region of operation, the shape of the emitted spectrum changes, with reduced short wavelength generation at lower current levels. Bipolar junction transistor (BJT) multi-terminal devices are also discussed, and the square-law behaviour of these devices is presented.

  19. A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors.

    Science.gov (United States)

    Lin, Qingyu; Miao, Wei; Zhang, Wancheng; Fu, Qiuyu; Wu, Nanjian

    2009-01-01

    A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 μm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

  20. A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

    Directory of Open Access Journals (Sweden)

    Nanjian Wu

    2009-07-01

    Full Text Available A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps. A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

  1. A Monolithic Multisensor Microchip with Complete On-Chip RF Front-End.

    Science.gov (United States)

    Merenda, Massimo; Felini, Corrado; Della Corte, Francesco G

    2018-01-02

    In this paper, a new wireless sensor, designed for a 0.35 µm CMOS technology, is presented. The microchip was designed to be placed on an object for the continuous remote monitoring of its temperature and illumination state. The temperature sensor is based on the temperature dependence of the I-V characteristics of bipolar transistors available in CMOS technology, while the illumination sensor is an integrated p-n junction photodiode. An on-chip 2.5 GHz transmitter, coupled to a mm-sized dipole radiating element fabricated on the same microchip and made in the top metal layer of the same die, sends the collected data wirelessly to a radio receiver using an On-Off Keying (OOK) modulation pattern.

  2. The impact of stack geometry and mean pressure on cold end temperature of stack in thermoacoustic refrigeration systems

    Science.gov (United States)

    Wantha, Channarong

    2018-02-01

    This paper reports on the experimental and simulation studies of the influence of stack geometries and different mean pressures on the cold end temperature of the stack in the thermoacoustic refrigeration system. The stack geometry was tested, including spiral stack, circular pore stack and pin array stack. The results of this study show that the mean pressure of the gas in the system has a significant impact on the cold end temperature of the stack. The mean pressure of the gas in the system corresponds to thermal penetration depth, which results in a better cold end temperature of the stack. The results also show that the cold end temperature of the pin array stack decreases more than that of the spiral stack and circular pore stack geometry by approximately 63% and 70%, respectively. In addition, the thermal area and viscous area of the stack are analyzed to explain the results of such temperatures of thermoacoustic stacks.

  3. 60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.

    2014-04-01

    A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.

  4. CMOS IMAGING SENSOR TECHNOLOGY FOR AERIAL MAPPING CAMERAS

    Directory of Open Access Journals (Sweden)

    K. Neumann

    2016-06-01

    Full Text Available In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  5. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  6. The design of the CMOS wireless bar code scanner applying optical system based on ZigBee

    Science.gov (United States)

    Chen, Yuelin; Peng, Jian

    2008-03-01

    The traditional bar code scanner is influenced by the length of data line, but the farthest distance of the wireless bar code scanner of wireless communication is generally between 30m and 100m on the market. By rebuilding the traditional CCD optical bar code scanner, a CMOS code scanner is designed based on the ZigBee to meet the demands of market. The scan system consists of the CMOS image sensor and embedded chip S3C2401X, when the two dimensional bar code is read, the results show the inaccurate and wrong code bar, resulted from image defile, disturber, reads image condition badness, signal interference, unstable system voltage. So we put forward the method which uses the matrix evaluation and Read-Solomon arithmetic to solve them. In order to construct the whole wireless optics of bar code system and to ensure its ability of transmitting bar code image signals digitally with long distances, ZigBee is used to transmit data to the base station, and this module is designed based on image acquisition system, and at last the wireless transmitting/receiving CC2430 module circuit linking chart is established. And by transplanting the embedded RTOS system LINUX to the MCU, an applying wireless CMOS optics bar code scanner and multi-task system is constructed. Finally, performance of communication is tested by evaluation software Smart RF. In broad space, every ZIGBEE node can realize 50m transmission with high reliability. When adding more ZigBee nodes, the transmission distance can be several thousands of meters long.

  7. Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology

    Science.gov (United States)

    Dentoni Litta, Eugenio; Hellström, Per-Erik; Henkel, Christoph; Östling, Mikael

    2014-08-01

    This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 °C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 × 1011 cm-2 eV-1. The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 °C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition ˜1 × 1011 cm-2 eV-1 and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.

  8. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  9. CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

    National Research Council Canada - National Science Library

    An, S

    2001-01-01

    .... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

  10. Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

    Science.gov (United States)

    Tomczak, Y.; Swerts, J.; Mertens, S.; Lin, T.; Couet, S.; Liu, E.; Sankaran, K.; Pourtois, G.; Kim, W.; Souriau, L.; Van Elshocht, S.; Kar, G.; Furnemont, A.

    2016-01-01

    Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm2 after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

  11. A Dynamic Range Expansion Technique for CMOS Image Sensors with Dual Charge Storage in a Pixel and Multiple Sampling

    Directory of Open Access Journals (Sweden)

    Shinya Itoh

    2008-03-01

    Full Text Available A dynamic range expansion technique for CMOS image sensors with dual charge storage in a pixel and multiple sampling technique is presented. Each pixel contains a photodiode and a storage diode which is connected to the photodiode via a separation gate. The sensitivity of the signal charge in the storage diode can be controlled either by a separation gate which limits the charge to flow into the storage diode or by controlling the accumulation time in the storage diode. The operation of the sensitivity control with separation gate techniques is simulated and it is found that a blocking layer to the storage diode plays an important role for high controllability of sensitivity of the storage diode. A prototype chip for testing multiple short time accumulations is fabricated and measured.

  12. A CMOS 0.13 mu m, 5-Gb/s laser driver for high energy physics applications

    CERN Document Server

    Mazza, G; Moreira, P; Rivetti, A; Soos, C; Troska, J; Wyllie, K

    2012-01-01

    The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC designed to drive both edge emitting lasers and VCSELs at data rates up to 5 Gb/s. It is part of the GigaBit Transceiver (GBT) and Versatile Link projects, which are designing a bi-directional optical data transmission system capable of operating in the radiation environment of a typical HEP experiment. The GBLD can provide laser diode modulation currents up to 24 mA and laser bias currents up to 43 mA. Pre- and de-emphasis functions are implemented to compensate for high external capacitive loads and asymmetric laser response. The chip, designed in a 0.13 $\\mu$m CMOS technology, is powered by a single 2.5 V power supply and can be programmed via an $I2C$ interface.

  13. A CMOS 0.13 μm, 5 Gb/s Laser Driver for High Energy Physics Applications

    Science.gov (United States)

    Mazza, Giovanni; Gui, Ping; Moreira, Paulo; Rivetti, Angelo; Soos, Csaba; Troska, Jan; Wyllie, Ken

    2012-12-01

    The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC designed to drive both edge emitting lasers and VCSELs at data rates up to 5 Gb/s. It is part of the GigaBit Transceiver (GBT) and Versatile Link projects, which are designing a bi-directional optical data transmission system capable of operating in the radiation environment of a typical HEP experiment. The GBLD can provide laser diode modulation currents up to 24 mA and laser bias currents up to 43 mA. Pre- and de-emphasis functions are implemented to compensate for high external capacitive loads and asymmetric laser response. The chip, designed in a 0.13 μm CMOS technology, is powered by a single 2.5 V power supply and can be programmed via an I2C interface.

  14. A 3-5 GHz TH-UWB transmitter in 0.18-μm RF CMOS technology

    International Nuclear Information System (INIS)

    Duan Jihai; Wang Zhigong; Li Zhiqun

    2009-01-01

    An RF transmitter is proposed for 3-5 GHz time-hopping ultra wideband (TH-UWB) wireless applications. The transmitter consists of a 4-GHz oscillator, a switch with a controllable attenuator and an output matching circuit. Through controlling the low frequency signals with time-hopping pulse position modulation (TH-PPM), the circuit supplies TH-UWB signals and can directly drive an antenna by a transmission line. The transmitter was implemented in a 0.18-μm CMOS technology; the output amplitude is about 65 mV at a 50 ? load from a 1.8-V supply, the return loss (S 11 ) at the output port is less than -10 dB, and the chip size is 0.7 x 0.8 mm 2 , with a power consumption of 12.3 mW.

  15. A 3-5 GHz TH-UWB transmitter in 0.18-{mu}m RF CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Duan Jihai; Wang Zhigong; Li Zhiqun, E-mail: djh@guet.edu.c [School of Integrated Circuits, Southeast University, Nanjing 210096 (China)

    2009-07-15

    An RF transmitter is proposed for 3-5 GHz time-hopping ultra wideband (TH-UWB) wireless applications. The transmitter consists of a 4-GHz oscillator, a switch with a controllable attenuator and an output matching circuit. Through controlling the low frequency signals with time-hopping pulse position modulation (TH-PPM), the circuit supplies TH-UWB signals and can directly drive an antenna by a transmission line. The transmitter was implemented in a 0.18-{mu}m CMOS technology; the output amplitude is about 65 mV at a 50 ? load from a 1.8-V supply, the return loss (S{sub 11}) at the output port is less than -10 dB, and the chip size is 0.7 x 0.8 mm{sup 2}, with a power consumption of 12.3 mW.

  16. A Compact P⁺ Contact Resistance Model for Characterization of Substrate Coupling in Modern Lightly Doped CMOS Processes

    DEFF Research Database (Denmark)

    Shen, Ming; Mikkelsen, Jan H.; Jensen, Ole Kiel

    2012-01-01

    Compact modeling of P+ contact resistances is important for characterization of substrate noise coupling in mixed-signal System on Chips (SoCs). Existing contact resistance models can handle uniformly doped bulk or epitaxial substrates. However, compact contact resistance models feasible for modern......, and it is scalable to layout/substrate parameters. The proposed model can also be used to predict noise coupling in terms of S-parameters. The model validation has been done by both EM simulations and measurements, and satisfactory agreement is found between the modeled and measured resistances as well as S-parameters....... lightly-doped CMOS processes with P-well layers are still unavailable. This paper presents a new compact resistance model aiming at solving this problem. A Conformal Mapping(CM) method was used to derive the closed-form expressions for the resistances in the model. The model requires no fitting factors...

  17. KPIX a pixel detector imaging chip

    CERN Document Server

    Cadeddu, S; Caria, M

    2002-01-01

    We present a VLSI custom device, named KPIX, developed in a 0.6 mu m CMOS technology. The circuit is dedicated to readout solid-state detectors covering large areas (on the order of square centimetre) and featuring very small currents. KPIX integrates 1024 channels (current amplifiers) and 8 ADCs on a 15.5x4 mm sup 2 area. Both an analogue and digital readout are allowed, with a 10 bit amplitude resolution. Amplifiers are organized in 8 columns of 128 rows. When choosing the digital or the analogue readout, the complete set of channels can be read out in about 30 ms. The specific design of the amplification cells allows to measure very small input current levels, on the order of fractions of pico-ampere. Power consumption has also been kept at the level of 80 mu W per cell and 150 mW (peak value) in total. The specific chip architecture and geometry allow use of many KPIX circuits together in order to serve a large detector sensitive area. The KPIX structure is presented along with some measurements character...

  18. The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

    CERN Document Server

    Aglieri Rinella, Gianluca

    2016-01-01

    The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10−5 and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm2 for the application in the Inner Barrel Layers and below 20 mW/cm2 for the Outer Barrel Layers, ...

  19. Development of a 55 μm pitch 8 inch CMOS image sensor for the high resolution NDT application

    Science.gov (United States)

    Kim, M. S.; Kim, G.; Cho, G.; Kim, D.

    2016-11-01

    A CMOS image sensor (CIS) with a large area for the high resolution X-ray imaging was designed. The sensor has an active area of 125 × 125 mm2 comprised with 2304 × 2304 pixels and a pixel size of 55 × 55 μm2. First batch samples were fabricated by using an 8 inch silicon CMOS image sensor process with a stitching method. In order to evaluate the performance of the first batch samples, the electro-optical test and the X-ray test after coupling with an image intensifier screen were performed. The primary results showed that the performance of the manufactured sensors was limited by a large stray capacitance from the long path length between the analog multiplexer on the chip and the bank ADC on the data acquisition board. The measured speed and dynamic range were limited up to 12 frame per sec and 55 dB respectively, but other parameters such as the MTF, NNPS and DQE showed a good result as designed. Based on this study, the new X-ray CIS with ~ 50 μm pitch and ~ 150 cm2 active area are going to be designed for the high resolution X-ray NDT equipment for semiconductor and PCB inspections etc.

  20. A high frequency active voltage doubler in standard CMOS using offset-controlled comparators for inductive power transmission.

    Science.gov (United States)

    Lee, Hyung-Min; Ghovanloo, Maysam

    2013-06-01

    In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std . CMOS process, occupying 0.144 mm(2) of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages.