Single chip camera active pixel sensor

Science.gov (United States)

Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

2003-01-01

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Anisotropy of Single-Crystal Silicon in Nanometric Cutting.

Science.gov (United States)

Wang, Zhiguo; Chen, Jiaxuan; Wang, Guilian; Bai, Qingshun; Liang, Yingchun

2017-12-01

The anisotropy exhibited by single-crystal silicon in nanometric cutting is very significant. In order to profoundly understand the effect of crystal anisotropy on cutting behaviors, a large-scale molecular dynamics model was conducted to simulate the nanometric cutting of single-crystal silicon in the (100)[0-10], (100)[0-1-1], (110)[-110], (110)[00-1], (111)[-101], and (111)[-12-1] crystal directions in this study. The simulation results show the variations of different degrees in chip, subsurface damage, cutting force, and friction coefficient with changes in crystal plane and crystal direction. Shear deformation is the formation mechanism of subsurface damage, and the direction and complexity it forms are the primary causes that result in the anisotropy of subsurface damage. Structurally, chips could be classified into completely amorphous ones and incompletely amorphous ones containing a few crystallites. The formation mechanism of the former is high-pressure phase transformation, while the latter is obtained under the combined action of high-pressure phase transformation and cleavage. Based on an analysis of the material removal mode, it can be found that compared with the other crystal direction on the same crystal plane, the (100)[0-10], (110)[-110], and (111)[-101] directions are more suitable for ductile cutting.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

Science.gov (United States)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

K-band single-chip electron spin resonance detector.

Science.gov (United States)

Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

2012-04-01

We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

Science.gov (United States)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

SVX3: A deadtimeless readout chip for silicon strip detectors

International Nuclear Information System (INIS)

Zimmerman, T.; Huffman, T.; Srage, J.; Stroehmer, R.; Yarema, R.; Garcia-Sciveras, M.; Luo, L.; Milgrome, O.

1997-12-01

A new silicon strip readout chip called the SVX3 has been designed for the 720,000 channel CDF silicon upgrade at Fermilab. SVX3 incorporates an integrator, analog delay pipeline, ADC, and data sparsification for each of 128 identical channels. Many of the operating parameters are programmable via a serial bit stream, which allows the chip to be used under a variety of conditions. Distinct features of SVX3 include use of a backside substrate contact for optimal ground referencing, and the capability of simultaneous signal acquisition and digital readout allowing deadtimeless operation in the Fermilab Tevatron

Study of silicon chip soldering in high-power transistor housing

Directory of Open Access Journals (Sweden)

Vasily S. Anosov

2017-09-01

We experimentally assessed the effect of outer housing layer materials and back side chip metallization. For lead-silver soldering of silicon chips, the best housing is that with a nickel outer layer rather than with a gold-plated one, because the resultant thermal resistance is lower and the absence of gold makes the technology cheaper. We obtained a 0.6 K/W thermal resistance for a 24 mm2 chip area.

Fiber-chip edge coupler with large mode size for silicon photonic wire waveguides.

Science.gov (United States)

Papes, Martin; Cheben, Pavel; Benedikovic, Daniel; Schmid, Jens H; Pond, James; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, Gonzalo; Ye, Winnie N; Xu, Dan-Xia; Janz, Siegfried; Dado, Milan; Vašinek, Vladimír

2016-03-07

Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO 2 upper cladding thin high-index Si 3 N 4 layers. The Si 3 N 4 layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.

Transparent Nanopore Cavity Arrays Enable Highly Parallelized Optical Studies of Single Membrane Proteins on Chip.

Science.gov (United States)

Diederichs, Tim; Nguyen, Quoc Hung; Urban, Michael; Tampé, Robert; Tornow, Marc

2018-06-13

Membrane proteins involved in transport processes are key targets for pharmaceutical research and industry. Despite continuous improvements and new developments in the field of electrical readouts for the analysis of transport kinetics, a well-suited methodology for high-throughput characterization of single transporters with nonionic substrates and slow turnover rates is still lacking. Here, we report on a novel architecture of silicon chips with embedded nanopore microcavities, based on a silicon-on-insulator technology for high-throughput optical readouts. Arrays containing more than 14 000 inverted-pyramidal cavities of 50 femtoliter volumes and 80 nm circular pore openings were constructed via high-resolution electron-beam lithography in combination with reactive ion etching and anisotropic wet etching. These cavities feature both, an optically transparent bottom and top cap. Atomic force microscopy analysis reveals an overall extremely smooth chip surface, particularly in the vicinity of the nanopores, which exhibits well-defined edges. Our unprecedented transparent chip design provides parallel and independent fluorescent readout of both cavities and buffer reservoir for unbiased single-transporter recordings. Spreading of large unilamellar vesicles with efficiencies up to 96% created nanopore-supported lipid bilayers, which are stable for more than 1 day. A high lipid mobility in the supported membrane was determined by fluorescent recovery after photobleaching. Flux kinetics of α-hemolysin were characterized at single-pore resolution with a rate constant of 0.96 ± 0.06 × 10 -3 s -1 . Here, we deliver an ideal chip platform for pharmaceutical research, which features high parallelism and throughput, synergistically combined with single-transporter resolution.

Anisotropic multi-spot DBR porous silicon chip for the detection of human immunoglobin G.

Science.gov (United States)

Cho, Bomin; Um, Sungyong; Sohn, Honglae

2014-07-01

Asymmetric porous silicon multilayer (APSM)-based optical biosensor was developed to specify human Immunoglobin G (Ig G). APSM chip was generated by an electrochemical etching of silicon wafer using an asymmetric electrode configuration in aqueous ethanolic HF solution and constituted with nine arrayed porous silicon multilayer. APSM prepared from anisotropic etching conditions displayed a sharp reflection resonance in the reflectivity spectrum. Each spot displayed single reflection resonance at different wavelengths as a function of the lateral distance from the Pt counter electrode. The sensor system was consisted of the 3 x 3 spot array of APSM modified with protein A. The system was probed with an aqueous human Ig G. Molecular binding and specificity was monitored as a shift in wavelength of reflection resonance.

Optical continuum generation on a silicon chip

Science.gov (United States)

Jalali, Bahram; Boyraz, Ozdal; Koonath, Prakash; Raghunathan, Varun; Indukuri, Tejaswi; Dimitropoulos, Dimitri

2005-08-01

Although the Raman effect is nearly two orders of magnitude stronger than the electronic Kerr nonlinearity in silicon, under pulsed operation regime where the pulse width is shorter than the phonon response time, Raman effect is suppressed and Kerr nonlinearity dominates. Continuum generation, made possible by the non-resonant Kerr nonlinearity, offers a technologically and economically appealing path to WDM communication at the inter-chip or intra-chip levels. We have studied this phenomenon experimentally and theoretically. Experimentally, a 2 fold spectral broadening is obtained by launching ~4ps optical pulses with 2.2GW/cm2 peak power into a conventional silicon waveguide. Theoretical calculations, that include the effect of two-photon-absorption, free carrier absorption and refractive index change indicate that up to >30 times spectral broadening is achievable in an optimized device. The broadening is due to self phase modulation and saturates due to two photon absorption. Additionally, we find that free carrier dynamics also contributes to the spectral broadening and cause the overall spectrum to be asymmetric with respect to the pump wavelength.

Silicon μ-strip detectors with SVX chip readout

International Nuclear Information System (INIS)

Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.; Timm, S.; Vorwalter, K.; Werding, R.

1994-01-01

A new silicon strip detector has been designed and constructed for a fixed target experiment at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into Fastbus memory. Construction and performance during the actual data taking run are discussed. ((orig.))

Miniature silicon electronic biological assay chip and applications for rapid battlefield diagnostics

Science.gov (United States)

Cunningham, Brian T.; Regan, Robert A.; Clapp, Christopher; Hildebrant, Eric; Weinberg, Marc S.; Williams, John

1999-07-01

Assessing the medical condition of battlefield personnel requires the development of rapid, portable biological diagnostic assays for a wide variety of antigens and enzymes. Ideally, such an assay would be inexpensive, small, and require no added reagents while maintaining the sensitivity and accuracy of laboratory-based assays. In this work, a microelectromechanical (MEMS) based biological assay sensor is presented which is expected to meet the above requirements. The sensor is a thin silicon membrane resonator (SMR) which registers a decrease in resonant frequency when mass is adsorbed onto its surface. By coating the sensor surface with a monolayer of antibody, for example, we have detected the corresponding antigen with a detection resolution of 0.25 ng/ml in phosphate buffer solution. Micromachining techniques are being used to integrate many (64 elements on the first test chip) identical SMR sensors into a single silicon chip which would be capable of simultaneously performing a wide variety of biomedical assays. The sensors require only a small printed circuit board and 8V power supply to operate and provide a readout. The presentation will describe the operation of the SMR sensor, the fabrication of the sensor array, and initial test results using commercially available animal immunoglobulins in laboratory-prepared test solutions.

Dye molecules as single-photon sources and large optical nonlinearities on a chip

International Nuclear Information System (INIS)

Hwang, J; Hinds, E A

2011-01-01

We point out that individual organic dye molecules, deposited close to optical waveguides on a photonic chip, can act as single-photon sources. A thin silicon nitride strip waveguide is expected to collect 28% of the photons from a single dibenzoterrylene molecule. These molecules can also provide large, localized optical nonlinearities, which are enough to discriminate between one photon or two through a differential phase shift of 2 0 per photon. This new atom-photon interface may be used as a resource for processing quantum information.

Characterization of porous silicon integrated in liquid chromatography chips

NARCIS (Netherlands)

Tiggelaar, Roald M.; Verdoold, Vincent; Eghbali, H.; Desmet, G.; Gardeniers, Johannes G.E.

2009-01-01

Properties of porous silicon which are relevant for use of the material as a stationary phase in liquid chromatography chips, like porosity, pore size and specific surface area, were determined with high-resolution SEM and N2 adsorption–desorption isotherms. For the anodization conditions

Quantitation of ultraviolet-induced single-strand breaks using oligonucleotide chip

International Nuclear Information System (INIS)

Pal, Sukdeb; Kim, Min Jung; Choo, Jaebum; Kang, Seong Ho; Lee, Kyeong-Hee; Song, Joon Myong

2008-01-01

A simple, accurate and robust methodology was established for the direct quantification of ultraviolet (UV)-induced single-strand break (SSB) using oligonucleotide chip. Oligonucleotide chips were fabricated by covalently anchoring the fluorescent-labeled ssDNAs onto silicon dioxide chip surfaces. Assuming that the possibility of more than one UV-induced SSB to be generated in a small oligonucleotide is extremely low, SSB formation was investigated quantifying the endpoint probe density by fluorescence measurement upon UV irradiation. The SSB yields obtained based on the highly sensitive laser-induced fluorometric determination of fluorophore-labeled oligonucleotides were found to coincide well with that predicted from a theoretical extrapolation of the results obtained for plasmid DNAs using conventional agarose gel electrophoresis. The developed method has the potential to serve as a high throughput, sample-thrifty, and time saving tool to realize more realistic, and direct quantification of radiation and chemical-induced strand breaks. It will be especially useful for determining the frequency of SSBs or lesions convertible to SSBs by specific cleaving reagents or enzymes

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

Science.gov (United States)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS

Alpha radiation detection using silicon memory chips - preliminary studies

International Nuclear Information System (INIS)

Pace, R.; Paix, D.; Haskard, M.

1993-01-01

Alpha radiation dosage is an important occupational health factor in the mining of uranium and mineral sands. Alpha radiation induced errors in the data of silicon based memory chips provide the foundation for a new type of sensor, with the potential for affordable and prompt measurement of personal alpha doses. With particular reference to Dynamic Random Access Memories (DRAM) this paper introduces the operating principle of a memory based radiation sensor, which is the error mechanism in silicon integrated circuits. 14 refs., 3 figs

Solid state silicon based condenser microphone for hearing aid, has transducer chip and IC chip between intermediate chip and openings on both sides of intermediate chip, to allow sound towards diaphragm

DEFF Research Database (Denmark)

2000-01-01

towards diaphragm. Surface of the chip (2) has electrical conductors (14) to connect chip with IC chip (3). USE - For use in miniature electroacoustic devices such as hearing aid. ADVANTAGE - Since sound inlet is covered by filter, dust, moisture and other impurities do not obstruct interior and sound...... inlet of microphone. External electrical connection can be made economically reliable and the thermal stress is avoided with the small size solid state silicon based condenser microphone....

On-chip real-time single-copy polymerase chain reaction in picoliter droplets

Energy Technology Data Exchange (ETDEWEB)

Beer, N R; Hindson, B; Wheeler, E; Hall, S B; Rose, K A; Kennedy, I; Colston, B

2007-04-20

The first lab-on-chip system for picoliter droplet generation and PCR amplification with real-time fluorescence detection has performed PCR in isolated droplets at volumes 10{sup 6} smaller than commercial real-time PCR systems. The system utilized a shearing T-junction in a silicon device to generate a stream of monodisperse picoliter droplets that were isolated from the microfluidic channel walls and each other by the oil phase carrier. An off-chip valving system stopped the droplets on-chip, allowing them to be thermal cycled through the PCR protocol without droplet motion. With this system a 10-pL droplet, encapsulating less than one copy of viral genomic DNA through Poisson statistics, showed real-time PCR amplification curves with a cycle threshold of {approx}18, twenty cycles earlier than commercial instruments. This combination of the established real-time PCR assay with digital microfluidics is ideal for isolating single-copy nucleic acids in a complex environment.

Opening of K+ channels by capacitive stimulation from silicon chip

Science.gov (United States)

Ulbrich, M. H.; Fromherz, P.

2005-10-01

The development of stable neuroelectronic systems requires a stimulation of nerve cells from semiconductor devices without electrochemical effects at the electrolyte/solid interface and without damage of the cell membrane. The interaction must rely on a reversible opening of voltage-gated ion channels by capacitive coupling. In a proof-of-principle experiment, we demonstrate that Kv1.3 potassium channels expressed in HEK293 cells can be opened from an electrolyte/oxide/silicon (EOS) capacitor. A sufficient strength of electrical coupling is achieved by insulating silicon with a thin film of TiO2 to achieve a high capacitance and by removing NaCl from the electrolyte to enhance the resistance of the cell-chip contact. When a decaying voltage ramp is applied to the EOS capacitor, an outward current through the attached cell membrane is observed that is specific for Kv1.3 channels. An open probability up to fifty percent is estimated by comparison with a numerical simulation of the cell-chip contact.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon

Science.gov (United States)

Tokel, Onur; Turnalı, Ahmet; Makey, Ghaith; Elahi, Parviz; ćolakoǧlu, Tahir; Ergeçen, Emre; Yavuz, Ã.-zgün; Hübner, René; Zolfaghari Borra, Mona; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F. Ã.-mer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3, with untapped potential for mid-infrared optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow the fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realized with techniques like reactive ion etching. Embedded optical elements7, electronic devices and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1-µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has an optical index different to that in unmodified parts, enabling the creation of numerous photonic devices. Optionally, these parts can be chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface—that is, `in-chip'—microstructures for microfluidic cooling of chips, vias, micro-electro-mechanical systems, photovoltaic applications and photonic devices that match or surpass corresponding state-of-the-art device performances.

In-chip microstructures and photonic devices fabricated by nonlinear laser lithography deep inside silicon.

Science.gov (United States)

Tokel, Onur; Turnali, Ahmet; Makey, Ghaith; Elahi, Parviz; Çolakoğlu, Tahir; Ergeçen, Emre; Yavuz, Özgün; Hübner, René; Borra, Mona Zolfaghari; Pavlov, Ihor; Bek, Alpan; Turan, Raşit; Kesim, Denizhan Koray; Tozburun, Serhat; Ilday, Serim; Ilday, F Ömer

2017-10-01

Silicon is an excellent material for microelectronics and integrated photonics1-3 with untapped potential for mid-IR optics4. Despite broad recognition of the importance of the third dimension5,6, current lithography methods do not allow fabrication of photonic devices and functional microelements directly inside silicon chips. Even relatively simple curved geometries cannot be realised with techniques like reactive ion etching. Embedded optical elements, like in glass7, electronic devices, and better electronic-photonic integration are lacking8. Here, we demonstrate laser-based fabrication of complex 3D structures deep inside silicon using 1 µm-sized dots and rod-like structures of adjustable length as basic building blocks. The laser-modified Si has a different optical index than unmodified parts, which enables numerous photonic devices. Optionally, these parts are chemically etched to produce desired 3D shapes. We exemplify a plethora of subsurface, i.e. , " in-chip" microstructures for microfluidic cooling of chips, vias, MEMS, photovoltaic applications and photonic devices that match or surpass the corresponding state-of-the-art device performances.

A scalable single-chip multi-processor architecture with on-chip RTOS kernel

NARCIS (Netherlands)

Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

2003-01-01

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

An automatic single channel analyzer based on single-chip microcomputer

International Nuclear Information System (INIS)

Yan Xuekun; Jia Mingchun; Zhang Yan; Liu Mingjian; Luo Ming

2008-01-01

The hardware and software of an automatic single channel analyzer based on AT89C51RC single-chip microcomputer is described in this paper. The equipment takes a method of channel-width-adjusting symmetrically, and makes use of single-chip microcomputer to control the two DAC0832 so as to adjust the discriminating threshold and channel-width automatically. As a result, the auto-measuring of the single channel analyzer is realized. Its circuit configuration is simple, and the uniformity of its channel-width is well, too. (authors)

Single-crystal silicon trench etching for fabrication of highly integrated circuits

Science.gov (United States)

Engelhardt, Manfred

1991-03-01

The development of single crystal silicon trench etching for fabrication of memory cells in 4 16 and 64Mbit DRAMs is reviewed in this paper. A variety of both etch tools and process gases used for the process development is discussed since both equipment and etch chemistry had to be improved and changed respectively to meet the increasing requirements for high fidelity pattern transfer with increasing degree of integration. In additon to DRAM cell structures etch results for deep trench isolation in advanced bipolar ICs and ASICs are presented for these applications grooves were etched into silicon through a highly doped buried layer and at the borderline of adjacent p- and n-well areas respectively. Shallow trench etching of large and small exposed areas with identical etch rates is presented as an approach to replace standard LOCOS isolation by an advanced isolation technique. The etch profiles were investigated with SEM TEM and AES to get information on contathination and damage levels and on the mechanism leading to anisotropy in the dry etch process. Thermal wave measurements were performed on processed single crystal silicon substrates for a fast evaluation of the process with respect to plasma-induced substrate degradation. This useful technique allows an optimization ofthe etch process regarding high electrical performance of the fully processed memory chip. The benefits of the use of magnetic fields for the development of innovative single crystal silicon dry

An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

International Nuclear Information System (INIS)

Fiorini, C.; Porro, M.

2006-01-01

We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

Directory of Open Access Journals (Sweden)

Diwei He

2015-07-01

Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

Science.gov (United States)

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

Crossing the Resolution Limit in Near-Infrared Imaging of Silicon Chips: Targeting 10-nm Node Technology

Directory of Open Access Journals (Sweden)

Krishna Agarwal

2015-05-01

Full Text Available The best reported resolution in optical failure analysis of silicon chips is 120-nm half pitch demonstrated by Semicaps Private Limited, whereas the current and future industry requirement for 10-nm node technology is 100-nm half pitch. We show the first experimental evidence for resolution of features with 100-nm half pitch buried in silicon (λ/10.6, thus fulfilling the industry requirement. These results are obtained using near-infrared reflection-mode imaging using a solid immersion lens. The key novel feature of our approach is the choice of an appropriately sized collection pinhole. Although it is usually understood that, in general, resolution is improved by using the smallest pinhole consistent with an adequate signal level, it is found that in practice for silicon chips there is an optimum pinhole size, determined by the generation of induced currents in the sample. In failure analysis of silicon chips, nondestructive imaging is important to avoid disturbing the functionality of integrated circuits. High-resolution imaging techniques like SEM or TEM require the transistors to be exposed destructively. Optical microscopy techniques may be used, but silicon is opaque in the visible spectrum, mandating the use of near-infrared light and thus poor resolution in conventional optical microscopy. We expect our result to change the way semiconductor failure analysis is performed.

Performance of the CAMEX64 silicon strip readout chip

International Nuclear Information System (INIS)

Yarema, R.J.

1989-06-01

The CAMEX64 is a 64 channel full custom CMOS chip designed specifically for the readout of silicon strip detectors. CAMEX which stands for CMOS Multichannel Analog MultiplEXer for Silicon Strip Detectors was designed by members of the Franhofer Institute for Microelectronic Circuits and Systems and the Max Planck Institute for Physics and Astrophysics. Each CAMEX channel has a switched capacitor charge sensitive amplifier with 4 sampling capacitors and a multiplexing scheme for reading out each of the channels on an analog bus. The device uses multiple sampling capacitors to filter and reduce input noise. Filtering is controlled through sampling techniques using external clocks. The device operates in a double correlated sampling mode and therefore cannot separate detector leakage current from a charge input. Normal operation of this device is similar to all other silicon readout chips designed and built thus far in that there is a data acquisition cycle during which charge is simultaneously accepted on all channels for a short period of time from a detector array, followed by a readout cycle where that charge or hit information is read out. This device works especially well for colliding beam experiments where the time of charge arrival is accurately known. However it can be used in fixed target or asynchronous mode where the time of charge arrival is not well known. In the asynchronous mode it appears that gain is somewhat dependent on the time interval required to decide whether or not to accept charge input information and thus the maximum signal to noise performance found with the synchronous mode may not be achieved in the asynchronous mode. 18 figs., 5 tabs

Origami chip-on-sensor design: progress and new developments

International Nuclear Information System (INIS)

Irmler, C; Bergauer, T; Frankenberger, A; Friedl, M; Gfall, I; Valentan, M; Ishikawa, A; Kato, E; Negishi, K; Kameswara, R; Mohanty, G; Onuki, Y; Shimizu, N; Tsuboyama, T

2013-01-01

The Belle II silicon vertex detector will consist of four layers of double-sided silicon strip detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO 2 cooling of the readout chips by a single, thin cooling pipe per ladder. Recently, we assembled a module consisting of two consecutive 6'' double-sided silicon strip detectors, both read out by Origami flexes. Such a compound of Origami modules is required for the ladders of the outer Belle II SVD layers. Consequently, it is intended to verify the scalability of the assembly procedure, the performance of combined Origami flexes as well as the efficiency of the CO 2 cooling system for a higher number of APV25 chips.

New generation of single-chip microcomputers focused on cost performance

Energy Technology Data Exchange (ETDEWEB)

Akao, Y.; Iwashita, H. (Hitachi, Ltd., Tokyo (Japan))

1993-06-01

A single-chip microcomputer which incorporates a CPU (central processing unit), memory, and peripheral functions in one chip has been increasingly applied to various fields as the heart of electronic equipment in terms of its economy, compactness, lightness, and suitability for mass production. In response to a wide variety of needs, a lineup must have substantial breadth with regard to performance, on-chip memory capacity, on-chip peripheral functions, operating voltage, and packaging. In particular, low-voltage high-speed operation, high integration, expanded address space, and improved software productivity, which are required for mobile communication terminals, are the common needs for single-chip microcomputers. In accordance with these needs, Hitachi has been actively developing new products. The present paper introduces Hitachi's lineup of single-chip microcomputers. 10 figs., 1 tab.

Laser Soldering and Thermal Cycling Tests of Monolithic Silicon Pixel Chips

CERN Document Server

Strand, Frode Sneve

2015-01-01

An ALPIDE-1 monolithic silicon pixel sensor prototype has been laser soldered to a flex printed circuit using a novel interconnection technique using lasers. This technique is to be optimised to ensure stable, good quality connections between the sensor chips and the FPCs. To test the long-term stability of the connections, as well as study the effects on hit thresholds and noise in the sensor, it was thermally cycled in a climate chamber 1200 times. The soldered connections showed good qualities like even melting and good adhesion on pad/flex surfaces, and the chip remained in working condition for 1080 cycles. After this, a few connections failed, having cracks in the soldering tin, rendering the chip unusable. Threshold and noise characteristics seemed stable, except for the noise levels of sector 2 in the chip, for 1000 cycles in a temperature interval of "10^{\\circ}" and "50^{\\circ}" C. Still, further testing with wider temperature ranges and more cycles is needed to test the limitations of the chi...

Ultracompact on-chip photothermal power monitor based on silicon hybrid plasmonic waveguides

Directory of Open Access Journals (Sweden)

Wu Hao

2017-01-01

Full Text Available We propose and demonstrate an ultracompact on-chip photothermal power monitor based on a silicon hybrid plasmonic waveguide (HPWG, which consists of a metal strip, a silicon core, and a silicon oxide (SiO2 insulator layer between them. When light injected to an HPWG is absorbed by the metal strip, the temperature increases and the resistance of the metal strip changes accordingly due to the photothermal and thermal resistance effects of the metal. Therefore, the optical power variation can be monitored by measuring the resistance of the metal strip on the HPWG. To obtain the electrical signal for the resistance measurement conveniently, a Wheatstone bridge circuit is monolithically integrated with the HPWG on the same chip. As the HPWG has nanoscale light confinement, the present power monitor is as short as ~3 μm, which is the smallest photothermal power monitor reported until now. The compactness helps to improve the thermal efficiency and the response speed. For the present power monitor fabricated with simple fabrication processes, the measured responsivity is as high as about 17.7 mV/mW at a bias voltage of 2 V and the power dynamic range is as large as 35 dB.

High Power Broadband Multispectral Source on a Hybrid Silicon Chip

Science.gov (United States)

2017-03-14

optical bandwidth of the erbium-doped- fiber -amplifier with densely-spaced frequency channels. To extend the spectral capacity of the Si-on-insulator...associated with non-uniform undercut at the taper tip across the chip after wet etching the active region. Figure 14. Normalized optical emission...Hutchinson, J., Shin, J.-H., Fish, G., and Fang, A., “Integrated silicon photonic laser sources for telecom and datacom,” in [National Fiber Optic

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

Science.gov (United States)

Ashenafi, Emeshaw

regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon

Qubit entanglement between ring-resonator photon-pair sources on a silicon chip

Science.gov (United States)

Silverstone, J. W.; Santagati, R.; Bonneau, D.; Strain, M. J.; Sorel, M.; O'Brien, J. L.; Thompson, M. G.

2015-01-01

Entanglement—one of the most delicate phenomena in nature—is an essential resource for quantum information applications. Scalable photonic quantum devices must generate and control qubit entanglement on-chip, where quantum information is naturally encoded in photon path. Here we report a silicon photonic chip that uses resonant-enhanced photon-pair sources, spectral demultiplexers and reconfigurable optics to generate a path-entangled two-qubit state and analyse its entanglement. We show that ring-resonator-based spontaneous four-wave mixing photon-pair sources can be made highly indistinguishable and that their spectral correlations are small. We use on-chip frequency demultiplexers and reconfigurable optics to perform both quantum state tomography and the strict Bell-CHSH test, both of which confirm a high level of on-chip entanglement. This work demonstrates the integration of high-performance components that will be essential for building quantum devices and systems to harness photonic entanglement on the large scale. PMID:26245267

Single-Chip Computers With Microelectromechanical Systems-Based Magnetic Memory

NARCIS (Netherlands)

Carley, L. Richard; Bain, James A.; Fedder, Gary K.; Greve, David W.; Guillou, David F.; Lu, Michael S.C.; Mukherjee, Tamal; Santhanam, Suresh; Abelmann, Leon; Min, Seungook

This article describes an approach for implementing a complete computer system (CPU, RAM, I/O, and nonvolatile mass memory) on a single integrated-circuit substrate (a chip)—hence, the name "single-chip computer." The approach presented combines advances in the field of microelectromechanical

Identifying EGFR-Expressed Cells and Detecting EGFR Multi-Mutations at Single-Cell Level by Microfluidic Chip

Science.gov (United States)

Li, Ren; Zhou, Mingxing; Li, Jine; Wang, Zihua; Zhang, Weikai; Yue, Chunyan; Ma, Yan; Peng, Hailin; Wei, Zewen; Hu, Zhiyuan

2018-03-01

EGFR mutations companion diagnostics have been proved to be crucial for the efficacy of tyrosine kinase inhibitor targeted cancer therapies. To uncover multiple mutations occurred in minority of EGFR-mutated cells, which may be covered by the noises from majority of un-mutated cells, is currently becoming an urgent clinical requirement. Here we present the validation of a microfluidic-chip-based method for detecting EGFR multi-mutations at single-cell level. By trapping and immunofluorescently imaging single cells in specifically designed silicon microwells, the EGFR-expressed cells were easily identified. By in situ lysing single cells, the cell lysates of EGFR-expressed cells were retrieved without cross-contamination. Benefited from excluding the noise from cells without EGFR expression, the simple and cost-effective Sanger's sequencing, but not the expensive deep sequencing of the whole cell population, was used to discover multi-mutations. We verified the new method with precisely discovering three most important EGFR drug-related mutations from a sample in which EGFR-mutated cells only account for a small percentage of whole cell population. The microfluidic chip is capable of discovering not only the existence of specific EGFR multi-mutations, but also other valuable single-cell-level information: on which specific cells the mutations occurred, or whether different mutations coexist on the same cells. This microfluidic chip constitutes a promising method to promote simple and cost-effective Sanger's sequencing to be a routine test before performing targeted cancer therapy.[Figure not available: see fulltext.

Application of single-chip microcomputer in radiation detection

International Nuclear Information System (INIS)

Zhang Songshou

1993-01-01

The single-chip microcomputer has some advantages in many aspects for example the strong function, the small volume, the low-power, firmed and reliable. It is used widely in the control of industry, instrument, communication and machine, etc.. The paper introduces that the single-chip microcomputer is used in radiation detection, mostly including the use of control, linear, compensation, calculation, prefabricated change, improving precision and training

Lab-on-chip system combining a microfluidic-ELISA with an array of amorphous silicon photosensors for the detection of celiac disease epitopes

Directory of Open Access Journals (Sweden)

Francesca Costantini

2015-12-01

Full Text Available This work presents a lab-on-chip system, which combines a glass-polydimethilsiloxane microfluidic network and an array of amorphous silicon photosensors for the diagnosis and follow-up of Celiac disease. The microfluidic chip implements an on-chip enzyme-linked immunosorbent assay (ELISA, relying on a sandwich immunoassay between antibodies against gliadin peptides (GPs and a secondary antibody marked with horseradish peroxidase (Ig-HRP. This enzyme catalyzes a chemiluminescent reaction, whose light intensity is detected by the amorphous silicon photosensors and transduced into an electrical signal that can be processed to recognize the presence of antibodies against GPs in the serum of people affected by Celiac syndrome.The correct operation of the developed lab-on-chip has been demonstrated using rabbit serum in the microfluidic ELISA. In particular, optimizing the dilution factors of both sera and Ig-HRP samples in the flowing solutions, the specific and non-specific antibodies against GPs can be successfully distinguished, showing the suitability of the presented device to effectively screen celiac disease epitopes. Keywords: Lab-on-chip, Celiac disease, Microfluidics, On-chip detection, ELISA, Amorphous silicon photosensors

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

Science.gov (United States)

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

2015-01-12

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

Single-chip microcomputer application in nuclear radiation monitoring instruments

International Nuclear Information System (INIS)

Zhang Songshou

1994-01-01

The single-chip microcomputer has advantage in many respects i.e. multiple function, small size, low-power consumption,reliability etc. It is widely used now in industry, instrumentation, communication and machinery. The author introduced usage of single-chip microcomputer in nuclear radiation monitoring instruments for control, linear compensation, calculation, changeable parameter presetting and military training

The single chip microcomputer technique in an intelligent nuclear instrument

International Nuclear Information System (INIS)

Wang Tieliu; Sun Punan; Wang Ying

1995-01-01

The authors present that how to acquire and process the output signals from the nuclear detector adopting single chip microcomputer technique, including working principles and the designing method of the computer's software and hardware in the single chip microcomputer instrument

A 240-channel thick film multi-chip module for readout of silicon drift detectors

International Nuclear Information System (INIS)

Lynn, D.; Bellwied, R.; Beuttenmueller, R.; Caines, H.; Chen, W.; DiMassimo, D.; Dyke, H.; Elliott, D.; Grau, M.; Hoffmann, G.W.; Humanic, T.; Jensen, P.; Kleinfelder, S.A.; Kotov, I.; Kraner, H.W.; Kuczewski, P.; Leonhardt, B.; Li, Z.; Liaw, C.J.; LoCurto, G.; Middelkamp, P.; Minor, R.; Mazeh, N.; Nehmeh, S.; O'Conner, P.; Ott, G.; Pandey, S.U.; Pruneau, C.; Pinelli, D.; Radeka, V.; Rescia, S.; Rykov, V.; Schambach, J.; Sedlmeir, J.; Sheen, J.; Soja, B.; Stephani, D.; Sugarbaker, E.; Takahashi, J.; Wilson, K.

2000-01-01

We have developed a thick film multi-chip module for readout of silicon drift (or low capacitance ∼200 fF) detectors. Main elements of the module include a custom 16-channel NPN-BJT preamplifier-shaper (PASA) and a custom 16-channel CMOS Switched Capacitor Array (SCA). The primary design criteria of the module were the minimizations of the power (12 mW/channel), noise (ENC=490 e - rms), size (20.5 mmx63 mm), and radiation length (1.4%). We will discuss various aspects of the PASA design, with emphasis on the preamplifier feedback network. The SCA is a modification of an integrated circuit that has been previously described [1]; its design features specific to its application in the SVT (Silicon Vertex Tracker in the STAR experiment at RHIC) will be discussed. The 240-channel multi-chip module is a circuit with five metal layers fabricated in thick film technology on a beryllia substrate and contains 35 custom and commercial integrated circuits. It has been recently integrated with silicon drift detectors in both a prototype system assembly for the SVT and a silicon drift array for the E896 experiment at the Alternating Gradient Synchrotron at the Brookhaven National Laboratory. We will discuss features of the module's design and fabrication, report the test results, and emphasize its performance both on the bench and under experimental conditions

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

Science.gov (United States)

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Precision Photothermal Annealing of Nanoporous Gold Thin Films for the Microfabrication of a Single-chip Material Libraries

Energy Technology Data Exchange (ETDEWEB)

Harris, C. D. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Shen, N. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Rubenchik, A. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Demos, S. G. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Matthews, M. J. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

2015-06-30

Single-chip material libraries of thin films of nanostructured materials are a promising approach for high throughput studies of structure-property relationship in the fields of physics and biology. Nanoporous gold (np-Au), produced by an alloy corrosion process, is a nanostructured material of specific interest in both these fields. One attractive property of np-Au is its self-similar coarsening behavior by thermally induced surface diffusion. However, traditional heat application techniques for the modification of np-Au are bulk processes that cannot be used to generate a library of different pore sizes on a single chip. Laser micromachining offers an attractive solution to this problem by providing a means to apply energy with high spatial and temporal resolution. In the present study we use finite element multiphysics simulations to predict the effects of laser mode (continuous-wave vs. pulsed) and supporting substrate thermal conductivity on the local np-Au film temperatures during photothermal annealing and subsequently investigate the mechanisms by which the np-Au network is coarsening. Our simulations predict that continuous-wave mode laser irradiation on a silicon supporting substrate supports the widest range of morphologies that can be created through the photothermal annealing of thin film np-Au. Using this result we successfully fabricate a single-chip material library consisting of 81 np-Au samples of 9 different morphologies for use in increased throughput material interaction studies.

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip

Science.gov (United States)

Shulaker, Max M.; Hills, Gage; Park, Rebecca S.; Howe, Roger T.; Saraswat, Krishna; Wong, H.-S. Philip; Mitra, Subhasish

2017-07-01

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors—promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage—fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce ‘highly processed’ information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

Silicon-Chip-Based Optical Frequency Combs

Science.gov (United States)

2015-10-26

fiber-based polarization controllers and a polarization beam splitter , and the output power is monitored with a sensitive photodiode. We use a...a single CW laser beam coupled to a microresonators can produce stabilized, octave-spanning combs through highly cascaded four-wave mixing (FWM...resonator designs , the resonator and the coupling waveguide are monolithically integrated. Thus, the entire on-chip configuration of CMOS-compatible

Distributed Processing Using Single-chip Microcomputers

National Research Council Canada - National Science Library

Pritchett, William

1996-01-01

This project investigates the use of single-chip microprocessors as nodes in a token ring control network and explores the implementation of a protocol to manage communication across such a network...

An electrochromatography chip with integrated waveguides for UV absorbance detection

International Nuclear Information System (INIS)

Gustafsson, O; Mogensen, K B; Ohlsson, P D; Kutter, J P; Liu, Y; Jacobson, S C

2008-01-01

A silicon-based microchip for electrochromatographic separations is presented. Apart from a microfluidic network, the microchip has integrated UV-transparent waveguides for detection and integrated couplers for optical fibers on the chip, yielding the most complete chromatography microchip to date in terms of the integration of optical components. The microfluidic network and the optical components are fabricated in a single etching step in silicon and subsequently thermally oxidized. The separation column consists of a regular array of microfabricated solid support structures with a monolayer of an octylsilane covalently bonded to the surfaces to provide chromatographic interaction. The chip features a 1 mm long U-shaped detection cell and planar silicon dioxide waveguides that couple light to and from the detection cell. Microfabricated on-chip fiber couplers assure perfect alignment of optical fibers to the waveguides. The entire oxidized silicon microchip structure is sealed with a glass lid. Reversed phase electrochromatographic separation of three neutral compounds is demonstrated using UV absorbance detection at 254 nm. Baseline separation of the analytes is achieved in less than two minutes

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

OpenAIRE

Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

International Nuclear Information System (INIS)

Irmler, C.; Bauer, A.; Bergauer, T.; Adamczyk, K.; Bacher, S.; Aihara, H.; Angelini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Aziz, T.; Babu, V.; Bahinipati, S.; Barberio, E.; Baroncelli, Ti.; Baroncelli, To.; Basith, A.K.; Behera, P.K.; Bhuyan, B.; Bilka, T.

2016-01-01

The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests

Single-Event Effects in Silicon and Silicon Carbide Power Devices

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2014-01-01

NASA Electronics Parts and Packaging program-funded activities over the past year on single-event effects in silicon and silicon carbide power devices are presented, with focus on SiC device failure signatures.

Development of new assembly techniques for a silicon micro-vertex detector unit using the flip-chip bonding method

International Nuclear Information System (INIS)

Saitoh, Y.; Takeuchi, H.; Mandai, M.; Kanazawa, H.; Yamanaka, J.; Miyahara, S.; Kamiya, M.; Fujita, Y.; Higashi, Y.; Ikeda, H.; Ikeda, M.; Koike, S.; Matsuda, T.; Ozaki, H.; Tanaka, M.; Tsuboyama, T.; Avrillon, S.; Okuno, S.; Haba, J.; Hanai, H.; Mori, S.; Yusa, K.; Fukunaga, C.

1994-01-01

Full-size models of a detector unit for a silicon micro-vertex detector were built for the KEK B factory. The Flip-Chip Bonding (FCB) method using a new type anisotropic conductive film was examined. The structure using the FCB method successfully provides a new architecture for the silicon micro-vertex detector unit. (orig.)

Broadband and scalable optical coupling for silicon photonics using polymer waveguides

Science.gov (United States)

La Porta, Antonio; Weiss, Jonas; Dangel, Roger; Jubin, Daniel; Meier, Norbert; Horst, Folkert; Offrein, Bert Jan

2018-04-01

We present optical coupling schemes for silicon integrated photonics circuits that account for the challenges in large-scale data processing systems such as those used for emerging big data workloads. Our waveguide based approach allows to optimally exploit the on-chip optical feature size, and chip- and package real-estate. It further scales well to high numbers of channels and is compatible with state-of-the-art flip-chip die packaging. We demonstrate silicon waveguide to polymer waveguide coupling losses below 1.5 dB for both the O- and C-bands with a polarisation dependent loss of <1 dB. Over 100 optical silicon waveguide to polymer waveguide interfaces were assembled within a single alignment step, resulting in a physical I/O channel density of up to 13 waveguides per millimetre along the chip-edge, with an average coupling loss of below 3.4 dB measured at 1310 nm.

Flip chip assembly of thinned chips for hybrid pixel detector applications

CERN Document Server

Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

Science.gov (United States)

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Application of quantum-dot multi-wavelength lasers and silicon photonic ring resonators to data-center optical interconnects

Science.gov (United States)

Beckett, Douglas J. S.; Hickey, Ryan; Logan, Dylan F.; Knights, Andrew P.; Chen, Rong; Cao, Bin; Wheeldon, Jeffery F.

2018-02-01

Quantum dot comb sources integrated with silicon photonic ring-resonator filters and modulators enable the realization of optical sub-components and modules for both inter- and intra-data-center applications. Low-noise, multi-wavelength, single-chip, laser sources, PAM4 modulation and direct detection allow a practical, scalable, architecture for applications beyond 400 Gb/s. Multi-wavelength, single-chip light sources are essential for reducing power dissipation, space and cost, while silicon photonic ring resonators offer high-performance with space and power efficiency.

Soft error modeling and analysis of the Neutron Intercepting Silicon Chip (NISC)

International Nuclear Information System (INIS)

Celik, Cihangir; Unlue, Kenan; Narayanan, Vijaykrishnan; Irwin, Mary J.

2011-01-01

Soft errors are transient errors caused due to excess charge carriers induced primarily by external radiations in the semiconductor devices. Soft error phenomena could be used to detect thermal neutrons with a neutron monitoring/detection system by enhancing soft error occurrences in the memory devices. This way, one can convert all semiconductor memory devices into neutron detection systems. Such a device is being developed at The Pennsylvania State University and named Neutron Intercepting Silicon Chip (NISC). The NISC is envisioning a miniature, power efficient, and active/passive operation neutron sensor/detector system. NISC aims to achieve this goal by introducing 10 B-enriched Borophosphosilicate Glass (BPSG) insulation layers in the semiconductor memories. In order to model and analyze the NISC, an analysis tool using Geant4 as the transport and tracking engine is developed for the simulation of the charged particle interactions in the semiconductor memory model, named NISC Soft Error Analysis Tool (NISCSAT). A simple model with 10 B-enriched layer on top of the lumped silicon region is developed in order to represent the semiconductor memory node. Soft error probability calculations were performed via the NISCSAT with both single node and array configurations to investigate device scaling by using different node dimensions in the model. Mono-energetic, mono-directional thermal and fast neutrons are used as the neutron sources. Soft error contribution due to the BPSG layer is also investigated with different 10 B contents and the results are presented in this paper.

Solar cell structure incorporating a novel single crystal silicon material

Science.gov (United States)

Pankove, Jacques I.; Wu, Chung P.

1983-01-01

A novel hydrogen rich single crystal silicon material having a band gap energy greater than 1.1 eV can be fabricated by forming an amorphous region of graded crystallinity in a body of single crystalline silicon and thereafter contacting the region with atomic hydrogen followed by pulsed laser annealing at a sufficient power and for a sufficient duration to recrystallize the region into single crystal silicon without out-gassing the hydrogen. The new material can be used to fabricate semiconductor devices such as single crystal silicon solar cells with surface window regions having a greater band gap energy than that of single crystal silicon without hydrogen.

On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

Science.gov (United States)

Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

2018-04-01

The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

Readout electronics development for the ATLAS silicon tracker

International Nuclear Information System (INIS)

Borer, K.; Beringer, J.; Anghinolfi, F.; Aspell, P.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Bonino, R.; Clark, A.G.; Kambara, H.; La Marra, D.; Leger, A.; Wu, X.; Richeux, J.P.; Taylor, G.N.; Fedotov, M.; Kuper, E.; Velikzhanin, Yu.; Campbell, D.; Murray, P.; Seller, P.

1995-01-01

We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints. (orig.)

A CMOS 130nm Evaluation digitzer chip for silicon strips readout

CERN Document Server

Da Silva, W; Dhellot, M; Fougeron, D; Genat, J F; Hermel, R; Huppert, J f; Kapusta, F; Lebbolo, H; Pham, T H; Rossel, F; Savoy-navarro, A; Sefri, R; Vilalte

2007-01-01

A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power.

A single-chip computer analysis system for liquid fluorescence

International Nuclear Information System (INIS)

Zhang Yongming; Wu Ruisheng; Li Bin

1998-01-01

The single-chip computer analysis system for liquid fluorescence is an intelligent analytic instrument, which is based on the principle that the liquid containing hydrocarbons can give out several characteristic fluorescences when irradiated by strong light. Besides a single-chip computer, the system makes use of the keyboard and the calculation and printing functions of a CASIO printing calculator. It combines optics, mechanism and electronics into one, and is small, light and practical, so it can be used for surface water sample analysis in oil field and impurity analysis of other materials

An analog silicon retina with multichip configuration.

Science.gov (United States)

Kameda, Seiji; Yagi, Tetsuya

2006-01-01

The neuromorphic silicon retina is a novel analog very large scale integrated circuit that emulates the structure and the function of the retinal neuronal circuit. We fabricated a neuromorphic silicon retina, in which sample/hold circuits were embedded to generate fluctuation-suppressed outputs in the previous study [1]. The applications of this silicon retina, however, are limited because of a low spatial resolution and computational variability. In this paper, we have fabricated a multichip silicon retina in which the functional network circuits are divided into two chips: the photoreceptor network chip (P chip) and the horizontal cell network chip (H chip). The output images of the P chip are transferred to the H chip with analog voltages through the line-parallel transfer bus. The sample/hold circuits embedded in the P and H chips compensate for the pattern noise generated on the circuits, including the analog communication pathway. Using the multichip silicon retina together with an off-chip differential amplifier, spatial filtering of the image with an odd- and an even-symmetric orientation selective receptive fields was carried out in real time. The analog data transfer method in the present multichip silicon retina is useful to design analog neuromorphic multichip systems that mimic the hierarchical structure of neuronal networks in the visual system.

Broadband enhancement of single photon emission and polarization dependent coupling in silicon nitride waveguides.

Science.gov (United States)

Bisschop, Suzanne; Guille, Antoine; Van Thourhout, Dries; Hens, Zeger; Brainis, Edouard

2015-06-01

Single-photon (SP) sources are important for a number of optical quantum information processing applications. We study the possibility to integrate triggered solid-state SP emitters directly on a photonic chip. A major challenge consists in efficiently extracting their emission into a single guided mode. Using 3D finite-difference time-domain simulations, we investigate the SP emission from dipole-like nanometer-sized inclusions embedded into different silicon nitride (SiNx) photonic nanowire waveguide designs. We elucidate the effect of the geometry on the emission lifetime and the polarization of the emitted SP. The results show that highly efficient and polarized SP sources can be realized using suspended SiNx slot-waveguides. Combining this with the well-established CMOS-compatible processing technology, fully integrated and complex optical circuits for quantum optics experiments can be developed.

Scientific performances of the XAA1.2 front-end chip for silicon microstrip detectors

International Nuclear Information System (INIS)

Del Monte, Ettore; Soffitta, Paolo; Morelli, Ennio; Pacciani, Luigi; Porrovecchio, Geiland; Rubini, Alda; Uberti, Olga; Costa, Enrico; Di Persio, Giuseppe; Donnarumma, Immacolata; Evangelista, Yuri; Feroci, Marco; Lazzarotto, Francesco; Mastropietro, Marcello; Rapisarda, Massimo

2007-01-01

The XAA1.2 is a custom ASIC chip for silicon microstrip detectors adapted by Ideas for the SuperAGILE instrument on board the AGILE space mission. The chip is equipped with 128 input channels, each one containing a charge preamplifier, shaper, peak detector and stretcher. The most important features of the ASIC are the extended linearity, low noise and low power consumption. The XAA1.2 underwent extensive laboratory testing in order to study its commandability and functionality and evaluate its scientific performances. In this paper we describe the XAA1.2 features, report the laboratory measurements and discuss the results emphasizing the scientific performances in the context of the SuperAGILE front-end electronics

Study on irradiation effects of nucleus electromagnetic pulse on single chip computer system

International Nuclear Information System (INIS)

Hou Minsheng; Liu Shanghe; Wang Shuping

2001-01-01

Intense electromagnetic pulse, namely nucleus electromagnetic pulse (NEMP), lightning electromagnetic pulse (LEMP) and high power microwave (HPM), can disturb and destroy the single chip computer system. To study this issue, the authors made irradiation experiments by NEMPs generated by gigahertz transversal electromagnetic (GTEM) Cell. The experiments show that shutdown, restarting, communication errors of the single chip microcomputer system would occur when it was irradiated by the NEMPs. Based on the experiments, the cause on the effects on the single chip microcomputer system is discussed

Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

Science.gov (United States)

Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

1997-01-01

The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

A primary battery-on-a-chip using monolayer graphene

Science.gov (United States)

Iost, Rodrigo M.; Crespilho, Frank N.; Kern, Klaus; Balasubramanian, Kannan

2016-07-01

We present here a bottom-up approach for realizing on-chip on-demand batteries starting out with chemical vapor deposition-grown graphene. Single graphene monolayers contacted by electrode lines on a silicon chip serve as electrodes. The anode and cathode are realized by electrodeposition of zinc and copper respectively onto graphene, leading to the realization of a miniature graphene-based Daniell cell on a chip. The electrolyte is housed partly in a gel and partly in liquid form in an on-chip enclosure molded using a 3d printer or made out of poly(dimethylsiloxane). The realized batteries provide a stable voltage (∼1.1 V) for many hours and exhibit capacities as high as 15 μAh, providing enough power to operate a pocket calculator. The realized batteries show promise for deployment as on-chip power sources for autonomous systems in lab-on-a-chip or biomedical applications.

Subsurface damage mechanism of high speed grinding process in single crystal silicon revealed by atomistic simulations

International Nuclear Information System (INIS)

Li, Jia; Fang, Qihong; Zhang, Liangchi; Liu, Youwen

2015-01-01

Highlights: • Molecular dynamic model of nanoscale high speed grinding of silicon workpiece has been established. • The effect of grinding speed on subsurface damage and grinding surface integrity by analyzing the chip, dislocation movement, and phase transformation during high speed grinding process are thoroughly investigated. • Subsurface damage is studied by the evolution of surface area at first time for more obvious observation on transition from ductile to brittle. • The hydrostatic stress and von Mises stress by the established analytical model are studied subsurface damage mechanism during nanoscale grinding. - Abstract: Three-dimensional molecular dynamics (MD) simulations are performed to investigate the nanoscale grinding process of single crystal silicon using diamond tool. The effect of grinding speed on subsurface damage and grinding surface integrity by analyzing the chip, dislocation movement, and phase transformation are studied. We also establish an analytical model to calculate several important stress fields including hydrostatic stress and von Mises stress for studying subsurface damage mechanism, and obtain the dislocation density on the grinding subsurface. The results show that a higher grinding velocity in machining brittle material silicon causes a larger chip and a higher temperature, and reduces subsurface damage. However, when grinding velocity is above 180 m s −1 , subsurface damage thickness slightly increases because a higher grinding speed leads to the increase in grinding force and temperature, which accelerate dislocation nucleation and motion. Subsurface damage is studied by the evolution of surface area at first time for more obvious observation on transition from ductile to brittle, that provides valuable reference for machining nanometer devices. The von Mises stress and the hydrostatic stress play an important role in the grinding process, and explain the subsurface damage though dislocation mechanism under high

Design and simulation of MEMS microvalves for silicon photonic biosensor chip

Science.gov (United States)

Amemiya, Yoshiteru; Nakashima, Yuuto; Maeda, Jun; Yokoyama, Shin

2018-04-01

For the early and easy diagnosis of diseases, we have proposed a silicon photonic biosensor chip with two kinds of MEMS microvalves for a multiple-item detection system. The driving voltage of the vertical type with the circular-plate capacitor structure and that of the lateral type with the comb-shaped electrode are investigated. From mechanical calculations, the driving voltage of the vertical type is estimated to be 30 V and that of the lateral type to be 15 V. The propagation loss at the intersecting waveguides of arrayed ring-resonator biosensors is also estimated. In the case of optimized intersecting waveguides, more than 67% transmittance of TE-mode light is simulated for the series connection of 20 intersecting waveguides. It is confirmed that it is possible to fabricate an 8 × 12 arrayed biosensor chip in an area of 1 × 1.5 mm2 taking the device size of the microvalves into consideration. We have, for the first time, designed a whole system, including sensors and a fluid channel with MEMS microvalves.

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Programmable lab-on-a-chip system for single cell analysis

Science.gov (United States)

Thalhammer, S.

2009-05-01

The collection, selection, amplification and detection of minimum genetic samples became a part of everyday life in medical and biological laboratories, to analyze DNA-fragments of pathogens, patient samples and traces on crime scenes. About a decade ago, a handful of researchers began discussing an intriguing idea. Could the equipment needed for everyday chemistry and biology procedures be shrunk to fit on a chip in the size of a fingernail? Miniature devices for, say, analysing DNA and proteins should be faster and cheaper than conventional versions. Lab-on-a-chip is an advanced technology that integrates a microfluidic system on a microscale chip device. The "laboratory" is created by means of channels, mixers, reservoirs, diffusion chambers, integrated electrodes, pumps, valves and more. With lab-ona- chip technology, complete laboratories on a square centimetre can be created. Here, a multifunctional programmable Lab-on-a-Chip driven by nanofluidics and controlled by surface acoustic waves (SAW) is presented. This system combines serial DNA-isolation-, amplification- and array-detection-process on a modified glass-platform. The fluid actuation is controlled via SAW by interdigital transducers implemented in the chemical modified chip surface. The chemical surface modification allows fluid handling in the sub-microliter range. Minute amount of sample material is extracted by laser-based microdissection out of e.g. histological sections at the single cell level. A few picogram of genetic material are isolated and transferred via a low-pressure transfer system (SPATS) onto the chip. Subsequently the genetic material inside single droplets, which behave like "virtual" beaker, is transported to the reaction and analysis centers on the chip surface via surface acoustic waves, mainly known as noise dumping filters in mobile phones. At these "biological reactors" the genetic material is processed, e.g. amplified via polymerase chain reaction methods, and genetically

Research on single-chip microcomputer controlled rotating magnetic field mineralization model

Science.gov (United States)

Li, Yang; Qi, Yulin; Yang, Junxiao; Li, Na

2017-08-01

As one of the method of selecting ore, the magnetic separation method has the advantages of stable operation, simple process flow, high beneficiation efficiency and no chemical environment pollution. But the existing magnetic separator are more mechanical, the operation is not flexible, and can not change the magnetic field parameters according to the precision of the ore needed. Based on the existing magnetic separator is mechanical, the rotating magnetic field can be used for single chip microcomputer control as the research object, design and trial a rotating magnetic field processing prototype, and through the single-chip PWM pulse output to control the rotation of the magnetic field strength and rotating magnetic field speed. This method of using pure software to generate PWM pulse to control rotary magnetic field beneficiation, with higher flexibility, accuracy and lower cost, can give full play to the performance of single-chip.

Pixel detector readout chip

CERN Multimedia

1991-01-01

Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

Mechanism of single atom switch on silicon

DEFF Research Database (Denmark)

Quaade, Ulrich; Stokbro, Kurt; Thirstrup, C.

1998-01-01

We demonstrate single atom switch on silicon which operates by displacement of a hydrogen atom on the silicon (100) surface at room temperature. We find two principal effects by which the switch is controlled: a pronounced maximum of the switching probability as function of sample bias...

Beam Test Results for Single- and Double-Sided Silicon Detector Prototypes of the CMS Central Detector

CERN Document Server

Adriani, O

1997-01-01

We report the results of two beam tests performed in July and September 1995 at CERN using silicon microstrip detectors of various types: single sided, double sided with small angle stereo strips, double sided with orthogonal strips, double sided with pads. For the read-out electronics use was made of Preshape32, Premux128 and VA1 chips. The signal to noise ratio and the resolution of the detectors was studied for different incident angles of the incoming particles and for different values of the detector bias voltage. The goal of these tests was to check and improve the performances of the prototypes for the CMS Central Detector.

Invited Article: Electrically tunable silicon-based on-chip microdisk resonator for integrated microwave photonic applications

Directory of Open Access Journals (Sweden)

Weifeng Zhang

2016-11-01

Full Text Available Silicon photonics with advantages of small footprint, compatibility with the mature CMOS fabrication technology, and its potential for seamless integration with electronics is making a significant difference in realizing on-chip integration of photonic systems. A microdisk resonator (MDR with a strong capacity in trapping and storing photons is a versatile element in photonic integrated circuits. Thanks to the large index contrast, a silicon-based MDR with an ultra-compact footprint has a great potential for large-scale and high-density integrations. However, the existence of multiple whispering gallery modes (WGMs and resonance splitting in an MDR imposes inherent limitations on its widespread applications. In addition, the waveguide structure of an MDR is incompatible with that of a lateral PN junction, which leads to the deprivation of its electrical tunability. To circumvent these limitations, in this paper we propose a novel design of a silicon-based MDR by introducing a specifically designed slab waveguide to surround the disk and the lateral sides of the bus waveguide to suppress higher-order WGMs and to support the incorporation of a lateral PN junction for electrical tunability. An MDR based on the proposed design is fabricated and its optical performance is evaluated. The fabricated MDR exhibits single-mode operation with a free spectral range of 28.85 nm. Its electrical tunability is also demonstrated and an electro-optic frequency response with a 3-dB modulation bandwidth of ∼30.5 GHz is measured. The use of the fabricated MDR for the implementation of an electrically tunable optical delay-line and a tunable fractional-order temporal photonic differentiator is demonstrated.

On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

Science.gov (United States)

Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

2017-08-30

Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

Resistivity distribution of silicon single crystals using codoping

Science.gov (United States)

Wang, Jong Hoe

2005-07-01

Numerous studies including continuous Czochralski method and double crucible technique have been reported on the control of macroscopic axial resistivity distribution in bulk crystal growth. The simple codoping method for improving the productivity of silicon single-crystal growth by controlling axial specific resistivity distribution was proposed by Wang [Jpn. J. Appl. Phys. 43 (2004) 4079]. Wang [J. Crystal Growth 275 (2005) e73] demonstrated using numerical analysis and by experimental results that the axial specific resistivity distribution can be modified in melt growth of silicon crystals and relatively uniform profile is possible by B-P codoping method. In this work, the basic characteristic of 8 in silicon single crystal grown using codoping method is studied and whether proposed method has advantage for the silicon crystal growth is discussed.

Data Transmission and Thermo-Optic Tuning Performance of Dielectric-Loaded Plasmonic Structures Hetero-Integrated on a Silicon Chip

DEFF Research Database (Denmark)

Giannoulis, G.; Kalavrouziotis, D.; Apostolopoulos, D.

2012-01-01

We demonstrate experimental evidence of the data capture and the low-energy thermo-optic tuning credentials of dielectric-loaded plasmonic structures integrated on a silicon chip. We show 7-nm thermo-optical tuning of a plasmonic racetrack-resonator with less than 3.3 mW required electrical power...

Study of a Microfluidic Chip Integrating Single Cell Trap and 3D Stable Rotation Manipulation

Directory of Open Access Journals (Sweden)

Liang Huang

2016-08-01

Full Text Available Single cell manipulation technology has been widely applied in biological fields, such as cell injection/enucleation, cell physiological measurement, and cell imaging. Recently, a biochip platform with a novel configuration of electrodes for cell 3D rotation has been successfully developed by generating rotating electric fields. However, the rotation platform still has two major shortcomings that need to be improved. The primary problem is that there is no on-chip module to facilitate the placement of a single cell into the rotation chamber, which causes very low efficiency in experiment to manually pipette single 10-micron-scale cells into rotation position. Secondly, the cell in the chamber may suffer from unstable rotation, which includes gravity-induced sinking down to the chamber bottom or electric-force-induced on-plane movement. To solve the two problems, in this paper we propose a new microfluidic chip with manipulation capabilities of single cell trap and single cell 3D stable rotation, both on one chip. The new microfluidic chip consists of two parts. The top capture part is based on the least flow resistance principle and is used to capture a single cell and to transport it to the rotation chamber. The bottom rotation part is based on dielectrophoresis (DEP and is used to 3D rotate the single cell in the rotation chamber with enhanced stability. The two parts are aligned and bonded together to form closed channels for microfluidic handling. Using COMSOL simulation and preliminary experiments, we have verified, in principle, the concept of on-chip single cell traps and 3D stable rotation, and identified key parameters for chip structures, microfluidic handling, and electrode configurations. The work has laid a solid foundation for on-going chip fabrication and experiment validation.

Strong spin-photon coupling in silicon

Science.gov (United States)

Samkharadze, N.; Zheng, G.; Kalhor, N.; Brousse, D.; Sammak, A.; Mendes, U. C.; Blais, A.; Scappucci, G.; Vandersypen, L. M. K.

2018-03-01

Long coherence times of single spins in silicon quantum dots make these systems highly attractive for quantum computation, but how to scale up spin qubit systems remains an open question. As a first step to address this issue, we demonstrate the strong coupling of a single electron spin and a single microwave photon. The electron spin is trapped in a silicon double quantum dot, and the microwave photon is stored in an on-chip high-impedance superconducting resonator. The electric field component of the cavity photon couples directly to the charge dipole of the electron in the double dot, and indirectly to the electron spin, through a strong local magnetic field gradient from a nearby micromagnet. Our results provide a route to realizing large networks of quantum dot–based spin qubit registers.

Application of single-chip microcomputer to portable radon and radon daughters monitor

International Nuclear Information System (INIS)

Meng Yecheng; Huang Zhanyun; She Chengye

1992-01-01

Application of single-chip microcomputer to portable radon and radon daughters monitor is introduced in this paper. With the single-chip microcomputer automation comes into effect in the process from sampling to measuring of radon and radon daughters. The concentrations of radon and radon daughters can be easily shown when the conversion coefficients are pre-settled before the measurement. Moreover, the principle and design are briefly discussed according to the characteristics of the monitor

Ultra-thin chip technology and applications

CERN Document Server

2010-01-01

Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

Evaluation of local radiation damage in silicon sensor via charge collection mapping with the Timepix read-out chip

International Nuclear Information System (INIS)

Platkevic, M; Jakubek, J; Jakubek, M; Pospisil, S; Zemlicka, J; Havranek, V; Semian, V

2013-01-01

Studies of radiation hardness of silicon sensors are standardly performed with single-pad detectors evaluating their global electrical properties. In this work we introduce a technique to visualize and determine the spatial distribution of radiation damage across the area of a semiconductor sensor. The sensor properties such as charge collection efficiency and charge diffusion were evaluated locally at many points of the sensor creating 2D maps. For this purpose we used a silicon sensor bump bonded to the pixelated Timepix read-out chip. This device, operated in Time-over-threshold (TOT) mode, allows for the direct energy measurement in each pixel. Selected regions of the sensor were intentionally damaged by defined doses (up to 10 12 particles/cm 2 ) of energetic protons (of 2.5 and 4 MeV). The extent of the damage was measured in terms of the detector response to the same ions. This procedure was performed either on-line during irradiation or off-line after it. The response of the detector to each single particle was analyzed determining the charge collection efficiency and lateral charge diffusion. We evaluated the changes of these parameters as a function of radiation dose. These features are related to the local properties such as the spatial homogeneity of the sensor. The effect of radiation damage was also independently investigated measuring local changes of signal response to γ, and X rays and alpha particles.

Fabrication and characterization of n-on-n silicon pixel detectors compatible with the Medipix2 readout chip

Energy Technology Data Exchange (ETDEWEB)

Zorzi, N. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy)]. E-mail: zorzi@itc.it; Bisogni, M.G. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Boscardin, M. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Dalla Betta, G.-F. [Dipartimento di Informatica e Telecomunicazioni, Universita di Trento, Via Sommarive 14, I-38050 Povo (Trento) (Italy); Gregori, P. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Novelli, M. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Piemonte, C. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Quattrocchi, M. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy); Ronchin, S. [ITC-irst, Divisione Microsistemi, Via Sommarive 18, I-38050 Povo (Trento) (Italy); Rosso, V. [Dipartimento di Fisica, Universita di Pisa and Sezione INFN, Via Buonarroti 2, I-56127 Pisa (Italy)

2005-07-01

Pixel detectors for mammographic applications have been fabricated at ITC-irst on 800 {mu}m thick silicon wafers adopting a double side n{sup +}-on-n fabrication technology. The activity aims at increasing the X-ray detection efficiency in the energy range of interest minimizing the risk of electrical discharges in hybrid systems operating at high voltages. The detectors, having a layout compatible with the Medipix2 photon counting chip, feature two different design solutions for the p-isolation between neighboring n{sup +}-pixels. We report on the characterization of the fabrication process and on preliminary results of electrical measurements on full detectors and pixel test structures. In particular, we found that the detectors can be reliably operated above the full depletion voltage regardless of the isolation design, that however, impacts the performances in terms of current-voltage characteristics, single pixel currents, inter-pixel resistances and inter-pixel capacitances.

Fabrication and characterization of n-on-n silicon pixel detectors compatible with the Medipix2 readout chip

International Nuclear Information System (INIS)

Zorzi, N.; Bisogni, M.G.; Boscardin, M.; Dalla Betta, G.-F.; Gregori, P.; Novelli, M.; Piemonte, C.; Quattrocchi, M.; Ronchin, S.; Rosso, V.

2005-01-01

Pixel detectors for mammographic applications have been fabricated at ITC-irst on 800 μm thick silicon wafers adopting a double side n + -on-n fabrication technology. The activity aims at increasing the X-ray detection efficiency in the energy range of interest minimizing the risk of electrical discharges in hybrid systems operating at high voltages. The detectors, having a layout compatible with the Medipix2 photon counting chip, feature two different design solutions for the p-isolation between neighboring n + -pixels. We report on the characterization of the fabrication process and on preliminary results of electrical measurements on full detectors and pixel test structures. In particular, we found that the detectors can be reliably operated above the full depletion voltage regardless of the isolation design, that however, impacts the performances in terms of current-voltage characteristics, single pixel currents, inter-pixel resistances and inter-pixel capacitances

Silicon nanowire transistors

CERN Document Server

Bindal, Ahmet

2016-01-01

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

Silicon microphotonic waveguides

International Nuclear Information System (INIS)

Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

2004-01-01

Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

Single-chip serial channel enhances multi-processor systems

Energy Technology Data Exchange (ETDEWEB)

Millar, J.

1982-01-01

In this paper multiprocessor systems are described and explained. The impact that VLSI advancements are having on multiprocessor design is pointed out. The TMS 7041 single-chip microcomputer is described briefly, highlighting its multiprocessor communication capability. And finally, a typical multiprocessor system is shown, implementing the TMS 7041.

Tractor performance monitor based on a single-chip microcomputer

Energy Technology Data Exchange (ETDEWEB)

Bedri, A.R.; Marley, S.J.; Buchelle, W.F.; Smay, T.A.

1981-01-01

A tractor performance monitor based on a single-chip microcomputer was developed to measure ground speed, slip, fuel consumption (rate and total), total area, theoretical time, and total time. Transducers used are presented in detail. 5 refs.

Generation, transmission, and detection of terahertz photons on an electrically driven single chip

Energy Technology Data Exchange (ETDEWEB)

Ikushima, Kenji; Ito, Atsushi; Okano, Shun [Department of Applied Physics, Tokyo University of Agriculture and Technology, 2-24-16 Nakacho, Koganei, Tokyo 184-8588 (Japan)

2014-02-03

We demonstrate single photon counting of terahertz (THz) waves transmitted from a local THz point source through a coplanar two-wire waveguide on a GaAs/AlGaAs single heterostructure crystal. In the electrically driven all-in-one chip, quantum Hall edge transport is used to achieve a noiseless injection current for a monochromatic point source of THz fields. The local THz fields are coupled to a coplanar two-wire metal waveguide and transmitted over a macroscopic scale greater than the wavelength (38 μm in GaAs). THz waves propagating on the waveguide are counted as individual photons by a quantum-dot single-electron transistor on the same chip. Photon counting on integrated high-frequency circuits will open the possibilities for on-chip quantum optical experiments.

Self-diffusion in single crystalline silicon nanowires

Science.gov (United States)

Südkamp, T.; Hamdana, G.; Descoins, M.; Mangelinck, D.; Wasisto, H. S.; Peiner, E.; Bracht, H.

2018-04-01

Self-diffusion experiments in single crystalline isotopically controlled silicon nanowires with diameters of 70 and 400 nm at 850 and 1000 °C are reported. The isotope structures were first epitaxially grown on top of silicon substrate wafers. Nanowires were subsequently fabricated using a nanosphere lithography process in combination with inductively coupled plasma dry reactive ion etching. Three-dimensional profiling of the nanosized structure before and after diffusion annealing was performed by means of atom probe tomography (APT). Self-diffusion profiles obtained from APT analyses are accurately described by Fick's law for self-diffusion. Data obtained for silicon self-diffusion in nanowires are equal to the results reported for bulk silicon crystals, i.e., finite size effects and high surface-to-volume ratios do not significantly affect silicon self-diffusion. This shows that the properties of native point defects determined from self-diffusion in bulk crystals also hold for nanosized silicon structures with diameters down to 70 nm.

Rapid manufacturing of low-noise membranes for nanopore sensors by trans-chip illumination lithography

International Nuclear Information System (INIS)

Janssen, Xander J A; Jonsson, Magnus P; Plesa, Calin; Soni, Gautam V; Dekker, Cees; Dekker, Nynke H

2012-01-01

In recent years, the concept of nanopore sensing has matured from a proof-of-principle method to a widespread, versatile technique for the study of biomolecular properties and interactions. While traditional nanopore devices based on a nanopore in a single layer membrane supported on a silicon chip can be rapidly fabricated using standard microfabrication methods, chips with additional insulating layers beyond the membrane region can provide significantly lower noise levels, but at the expense of requiring more costly and time-consuming fabrication steps. Here we present a novel fabrication protocol that overcomes this issue by enabling rapid and reproducible manufacturing of low-noise membranes for nanopore experiments. The fabrication protocol, termed trans-chip illumination lithography, is based on illuminating a membrane-containing wafer from its backside such that a photoresist (applied on the wafer’s top side) is exposed exclusively in the membrane regions. Trans-chip illumination lithography permits the local modification of membrane regions and hence the fabrication of nanopore chips containing locally patterned insulating layers. This is achieved while maintaining a well-defined area containing a single thin membrane for nanopore drilling. The trans-chip illumination lithography method achieves this without relying on separate masks, thereby eliminating time-consuming alignment steps as well as the need for a mask aligner. Using the presented approach, we demonstrate rapid and reproducible fabrication of nanopore chips that contain small (12 μm × 12 μm) free-standing silicon nitride membranes surrounded by insulating layers. The electrical noise characteristics of these nanopore chips are shown to be superior to those of simpler designs without insulating layers and comparable in quality to more complex designs that are more challenging to fabricate. (paper)

A Low Cost Single Chip VDL Compatible Transceiver ASIC

Science.gov (United States)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

Cavity-assisted quantum computing in a silicon nanostructure

International Nuclear Information System (INIS)

Tang Bao; Qin Hao; Zhang Rong; Xue Peng; Liu Jin-Ming

2014-01-01

We present a scheme of quantum computing with charge qubits corresponding to one excess electron shared between dangling-bond pairs of surface silicon atoms that couple to a microwave stripline resonator on a chip. By choosing a certain evolution time, we propose the realization of a set of universal single- and two-qubit logical gates. Due to its intrinsic stability and scalability, the silicon dangling-bond charge qubit can be regarded as one of the most promising candidates for quantum computation. Compared to the previous schemes on quantum computing with silicon bulk systems, our scheme shows such advantages as a long coherent time and direct control and readout. (general)

Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

KAUST Repository

Johansson, Johan R.

2012-03-12

We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

KAUST Repository

Johansson, Johan R.; Bosaeus, Niklas; Kann, Nina; Å kerman, Bjö rn; Nordé n, Bengt; Khalid, Waqas

2012-01-01

We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

A fully packaged micromachined single crystalline resonant force sensor

Energy Technology Data Exchange (ETDEWEB)

Cavalloni, C.; Gnielka, M.; Berg, J. von [Kistler Instrumente AG, Winterthur (Switzerland); Haueis, M.; Dual, J. [ETH Zuerich, Inst. of Mechanical Systems, Zuerich (Switzerland); Buser, R. [Interstate Univ. of Applied Science Buchs, Buchs (Switzerland)

2001-07-01

In this work a fully packaged resonant force sensor for static load measurements is presented. The working principle is based on the shift of the resonance frequency in response to the applied load. The heart of the sensor, the resonant structure, is fabricated by micromachining using single crystalline silicon. To avoid creep and hysteresis and to minimize temperature induced stress the resonant structure is encapsulated using an all-in-silicon solution. This means that the load coupling, the excitation of the microresonator and the detection of the oscillation signal are integrated in only one single crystalline silicon chip. The chip is packaged into a specially designed housing made of steel which has been designed with respect to application in harsh environments. The unloaded sensor has an initial frequency of about 22,5 kHz. The sensitivity amounts to 26 Hz/N with a linearity error significantly less than 0,5%FSO. (orig.)

Optothermal response of a single silicon nanotip

Science.gov (United States)

Vella, A.; Shinde, D.; Houard, J.; Silaeva, E.; Arnoldi, L.; Blum, I.; Rigutti, L.; Pertreux, E.; Maioli, P.; Crut, A.; Del Fatti, N.

2018-02-01

The optical properties and thermal dynamics of conical single silicon nanotips are experimentally and theoretically investigated. The spectral and spatial dependencies of their optical extinction are quantitatively measured by spatial modulation spectroscopy (SMS). A nonuniform optical extinction along the tip axis and an enhanced near-infrared absorption, as compared to bulk crystalline silicon, are evidenced. This information is a key input for computing the thermal response of single silicon nanotips under ultrafast laser illumination, which is investigated by laser assisted atom probe tomography (La-APT) used as a highly sensitive temperature probe. A combination of these two experimental techniques and comparison with modeling also permits us to elucidate the impact of thermal effects on the laser assisted field evaporation process. Extension of this coupled approach opens up future perspectives for the quantitative study of the optical and thermal properties of a wide class of individual nano-objects, in particular elongated ones such as nanotubes, nanowires, and nanocones, which constitute promising nanosources for electron and/or ion emission.

Experimental single-chip color HDTV image acquisition system with 8M-pixel CMOS image sensor

Science.gov (United States)

Shimamoto, Hiroshi; Yamashita, Takayuki; Funatsu, Ryohei; Mitani, Kohji; Nojiri, Yuji

2006-02-01

We have developed an experimental single-chip color HDTV image acquisition system using 8M-pixel CMOS image sensor. The sensor has 3840 × 2160 effective pixels and is progressively scanned at 60 frames per second. We describe the color filter array and interpolation method to improve image quality with a high-pixel-count single-chip sensor. We also describe an experimental image acquisition system we used to measured spatial frequency characteristics in the horizontal direction. The results indicate good prospects for achieving a high quality single chip HDTV camera that reduces pseudo signals and maintains high spatial frequency characteristics within the frequency band for HDTV.

Influence of transient radiation for the behaviour of the 80C31 single-chip microcontrollers

International Nuclear Information System (INIS)

Zhou Kaiming; Xie Zeyuan; Yang Youli

2006-01-01

Radiation characteristic of transient dose rate and the changed rule of latchup current with the gamma dose rate in 'flash-1' were researched in the 80C31 Single-chip Microcontrollers. The latchup current characteristic of the 80C31 Single-chip Microcontrollers was analyzed in shallow deep latchup. (authors)

On-Chip All-Optical Passive 3.55 Gbit/s NRZ-to-PRZ Format Conversion Using a High-Q Silicon-Based Microring Resonator

International Nuclear Information System (INIS)

Yao, Zhai; Shao-Wu, Chen; Guang-Hui, Ren

2010-01-01

We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108ps width and 4.98 dB ER

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

Directory of Open Access Journals (Sweden)

M. Elsobky

2017-09-01

Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Architectures for single-chip image computing

Science.gov (United States)

Gove, Robert J.

1992-04-01

This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

Initial beam test results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Adolphsen, C.; Litke, A.; Schwarz, A.

1986-01-01

Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

Energy Technology Data Exchange (ETDEWEB)

Loechner, S.

2006-07-26

The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

International Nuclear Information System (INIS)

Loechner, S.

2006-01-01

The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

Design of Water Temperature Control System Based on Single Chip Microcomputer

Science.gov (United States)

Tan, Hanhong; Yan, Qiyan

2017-12-01

In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

International Nuclear Information System (INIS)

Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

2010-01-01

We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

Piezoresistive effect in top-down fabricated silicon nanowires

DEFF Research Database (Denmark)

Reck, Kasper; Richter, Jacob; Hansen, Ole

2008-01-01

We have designed and fabricated silicon test chips to investigate the piezoresistive properties of both crystalline and polycrystalline nanowires using a top-down approach, in order to comply with conventional fabrication techniques. The test chip consists of 5 silicon nanowires and a reference...

The artificial satellite observation chronograph controlled by single chip microcomputer.

Science.gov (United States)

Pan, Guangrong; Tan, Jufan; Ding, Yuanjun

1991-06-01

The instrument specifications, hardware structure, software design, and other characteristics of the chronograph mounting on a theodolite used for artificial satellite observation are presented. The instrument is a real time control system with a single chip microcomputer.

Spectroscopy study of imaging devices based on silicon Pixel Array Detector coupled to VATAGP7 read-out chips

International Nuclear Information System (INIS)

Linhart, V; Lacasta, C; Llosa, G; Stankova, V; Burdette, D; Chessi, E; Cochran, E; Honscheid, K; Kagan, H; Weilhammer, P; Cindro, V; Grosicar, B; Mikuz, M; Studen, A; Zontar, D; Clinthorne, N H

2011-01-01

Spectroscopic and timing response studies have been conducted on a detector module consisting of a silicon Pixel Array Detector bonded on two VATAGP7 read-out chips manufactured by Gamma-Medica Ideas using laboratory gamma sources and the internal calibration facilities (the calibration system of the read-out chips). The performed tests have proven that the chips have (i) non-linear calibration curves which can be approximated by power functions, (ii) capability to measure the energy of photons with energy resolution better than 2 keV (exact range and resolution depend on experimental setup), (iii) the internal calibration facility which provides 6 out of 16 available internal calibration charges within our region of interest (spanning the Compton edge of 511 keV photons). The peaks induced by the internal calibration facility are suitable for a fit of the calibration curves. However, they are not suitable for measurements of equivalent noise charge because their full width at half maximum varies with their amplitude. These facts indicate that the VATAGP7 chips are useful and precise tools for a wide variety of spectroscopic devices. We have also explored time walk of the module and peaking time of the spectroscopy signals provided by the chips. We have observed that (iv) the time walk is caused partly by the peaking time of the signals provided by the fast shaper of the chips and partly by the timing uncertainty related to the varying position of the photon interaction, (v) the peaking time of the spectroscopy signals provided by the chips increases with increasing pulse height.

On-Chip Single-Plasmon Nanocircuit Driven by a Self-Assembled Quantum Dot.

Science.gov (United States)

Wu, Xiaofei; Jiang, Ping; Razinskas, Gary; Huo, Yongheng; Zhang, Hongyi; Kamp, Martin; Rastelli, Armando; Schmidt, Oliver G; Hecht, Bert; Lindfors, Klas; Lippitz, Markus

2017-07-12

Quantum photonics holds great promise for future technologies such as secure communication, quantum computation, quantum simulation, and quantum metrology. An outstanding challenge for quantum photonics is to develop scalable miniature circuits that integrate single-photon sources, linear optical components, and detectors on a chip. Plasmonic nanocircuits will play essential roles in such developments. However, for quantum plasmonic circuits, integration of stable, bright, and narrow-band single photon sources in the structure has so far not been reported. Here we present a plasmonic nanocircuit driven by a self-assembled GaAs quantum dot. Through a planar dielectric-plasmonic hybrid waveguide, the quantum dot efficiently excites narrow-band single plasmons that are guided in a two-wire transmission line until they are converted into single photons by an optical antenna. Our work demonstrates the feasibility of fully on-chip plasmonic nanocircuits for quantum optical applications.

Space division multiplexing chip-to-chip quantum key distribution

DEFF Research Database (Denmark)

Bacco, Davide; Ding, Yunhong; Dalgaard, Kjeld

2017-01-01

nodes of the quantum keys to their respective destinations. In this paper we present an experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM), through multicore fiber technology. Parallel and independent quantum...

Chips 2020

CERN Document Server

2016-01-01

The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

DNA analysis by single molecule stretching in nanofluidic biochips

DEFF Research Database (Denmark)

Abad, E.; Juarros, A.; Retolaza, A.

2011-01-01

Imprint Lithography (NIL) technology combined with a conventional anodic bonding of the silicon base and Pyrex cover. Using this chip, we have performed single molecule imaging on a bench-top fluorescent microscope system. Lambda phage DNA was used as a model sample to characterize the chip. Single molecules of λ-DNA......Stretching single DNA molecules by confinement in nanofluidic channels has attracted a great interest during the last few years as a DNA analysis tool. We have designed and fabricated a sealed micro/nanofluidic device for DNA stretching applications, based on the use of the high throughput Nano...... stained with the fluorescent dye YOYO-1 were stretched in the nanochannel array and the experimental results were analysed to determine the extension factor of the DNA in the chip and the geometrical average of the nanochannel inner diameter. The determination of the extension ratio of the chip provides...

A contact-lens-shaped IC chip technology

International Nuclear Information System (INIS)

Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

2014-01-01

We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

The ALICE Silicon Pixel Detector System (SPD)

CERN Document Server

Kluge, A; Antinori, Federico; Burns, M; Cali, I A; Campbell, M; Caselle, M; Ceresa, S; Dima, R; Elias, D; Fabris, D; Krivda, Marian; Librizzi, F; Manzari, Vito; Morel, M; Moretto, Sandra; Osmic, F; Pappalardo, G S; Pepato, Adriano; Pulvirenti, A; Riedler, P; Riggi, F; Santoro, R; Stefanini, G; Torcato De Matos, C; Turrisi, R; Tydesjo, H; Viesti, G; PH-EP

2007-01-01

The ALICE silicon pixel detector (SPD) comprises the two innermost layers of the ALICE inner tracker system. The SPD includes 120 detector modules (half-staves) each consisting of 10 ALICE pixel chips bump bonded to two silicon sensors and one multi-chip read-out module. Each pixel chip contains 8192 active cells, so that the total number of pixel cells in the SPD is ≈ 107. The on-detector read-out is based on a multi-chip-module containing 4 ASICs and an optical transceiver module. The constraints on material budget and detector module dimensions are very demanding.

Experimental demonstration of reservoir computing on a silicon photonics chip

Science.gov (United States)

Vandoorne, Kristof; Mechet, Pauline; van Vaerenbergh, Thomas; Fiers, Martin; Morthier, Geert; Verstraeten, David; Schrauwen, Benjamin; Dambre, Joni; Bienstman, Peter

2014-03-01

In today’s age, companies employ machine learning to extract information from large quantities of data. One of those techniques, reservoir computing (RC), is a decade old and has achieved state-of-the-art performance for processing sequential data. Dedicated hardware realizations of RC could enable speed gains and power savings. Here we propose the first integrated passive silicon photonics reservoir. We demonstrate experimentally and through simulations that, thanks to the RC paradigm, this generic chip can be used to perform arbitrary Boolean logic operations with memory as well as 5-bit header recognition up to 12.5 Gbit s-1, without power consumption in the reservoir. It can also perform isolated spoken digit recognition. Our realization exploits optical phase for computing. It is scalable to larger networks and much higher bitrates, up to speeds >100 Gbit s-1. These results pave the way for the application of integrated photonic RC for a wide range of applications.

A Novel Silicon Micromachined Integrated MCM Thermal Management System

Science.gov (United States)

Kazmierczak, M. J.; Henderson, H. T.; Gerner, F. M.

1997-01-01

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high

Single-Event Effects in Silicon Carbide Power Devices

Science.gov (United States)

Lauenstein, Jean-Marie; Casey, Megan C.; LaBel, Kenneth A.; Ikpe, Stanley; Topper, Alyson D.; Wilcox, Edward P.; Kim, Hak; Phan, Anthony M.

2015-01-01

This report summarizes the NASA Electronic Parts and Packaging Program Silicon Carbide Power Device Subtask efforts in FY15. Benefits of SiC are described and example NASA Programs and Projects desiring this technology are given. The current status of the radiation tolerance of silicon carbide power devices is given and paths forward in the effort to develop heavy-ion single-event effect hardened devices indicated.

Narrow band wavelength selective filter using grating assisted single ring resonator

Energy Technology Data Exchange (ETDEWEB)

Prabhathan, P., E-mail: PPrabhathan@ntu.edu.sg; Murukeshan, V. M. [Centre for Optical and Laser Engineering (COLE), School of Mechanical and Aerospace Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

2014-09-15

This paper illustrates a filter configuration which uses a single ring resonator of larger radius connected to a grating resonator at its drop port to achieve single wavelength selectivity and switching property with spectral features suitable for on-chip wavelength selection applications. The proposed configuration is expected to find applications in silicon photonics devices such as, on-chip external cavity lasers and multi analytic label-free biosensors. The grating resonator has been designed for a high Q-factor, high transmittivity, and minimum loss so that the wavelength selectivity of the device is improved. The proof-of-concept device has been demonstrated on a Silicon-on-Insulator (SOI) platform through electron beam lithography and Reactive Ion Etching (RIE) process. The transmission spectrum shows narrow band single wavelength selection and switching property with a high Free Spectral Range (FSR) ∼60 nm and side band rejection ratio >15 dB.

Versatile single-chip event sequencer for atomic physics experiments

Science.gov (United States)

Eyler, Edward

2010-03-01

A very inexpensive dsPIC microcontroller with internal 32-bit counters is used to produce a flexible timing signal generator with up to 16 TTL-compatible digital outputs, with a time resolution and accuracy of 50 ns. This time resolution is easily sufficient for event sequencing in typical experiments involving cold atoms or laser spectroscopy. This single-chip device is capable of triggered operation and can also function as a sweeping delay generator. With one additional chip it can also concurrently produce accurately timed analog ramps, and another one-chip addition allows real-time control from an external computer. Compared to an FPGA-based digital pattern generator, this design is slower but simpler and more flexible, and it can be reprogrammed using ordinary `C' code without special knowledge. I will also describe the use of the same microcontroller with additional hardware to implement a digital lock-in amplifier and PID controller for laser locking, including a simple graphics-based control unit. This work is supported in part by the NSF.

Radiation effect characterization and test methods of single-chip and multi-chip stacked 16Mbit DRAMs

International Nuclear Information System (INIS)

LaBel, K.A.; Gates, M.M.; Moran, A.K.; Kim, H.S.; Seidleck, C.M.; Marshall, P.; Kinnison, J.; Carkhuff, B.

1996-01-01

This paper presents radiation effects characterization performed by the NASA Goddard Space Flight Center (GSFC) on spaceflight candidate 16Mbit DRAMs. This includes heavy ion, proton, and Co60 irradiations on single-chip devices as well as proton irradiation of a stacked DRAM module. Lastly, a discussion of test methodology is undertaken

Multi-quantum spin resonances of intrinsic defects in silicon carbide

International Nuclear Information System (INIS)

Georgy Astakhov

2014-01-01

We report the observation of multi-quantum microwave absorption and emission, induced by the optical excitation of silicon vacancy related defects in silicon carbide (SiC). In particular, we observed two-quantum transitions from +3/2 to -1/2 and from -3/2 to +1/2 spin sublevels, unambiguously indicating the spin S = 3/2 ground state. Our findings may have implications for a broad range of quantum applications. On one hand, a single silicon vacancy defect is a potential source of indistinguishable microwave photon pairs due to the two-quantum emission process. On the other hand, the two-quantum absorption can be used generate a population inversion, which is a prerequisite to fabricate solid-state maser and quantum microwave amplifier. This opens a new platform cavity quantum electrodynamics experiments and quantum information processing on a single chip. (author)

The silicon chip: A versatile micro-scale platform for micro- and nano-scale systems

Science.gov (United States)

Choi, Edward

Cutting-edge advances in micro- and nano-scale technology require instrumentation to interface with the external world. While technology feature sizes are continually being reduced, the size of experimentalists and their instrumentation do not mirror this trend. Hence there is a need for effective application-specific instrumentation to bridge the gap from the micro and nano-scale phenomena being studied to the comparative macro-scale of the human interfaces. This dissertation puts forward the idea that the silicon CMOS integrated circuit, or microchip in short, serves as an excellent platform to perform this functionality. The electronic interfaces designed for the semiconductor industry are particularly attractive as development platforms, and the reduction in feature sizes that has been a hallmark of the industry suggests that chip-scale instrumentation may be more closely coupled to the phenomena of interest, allowing finer control or improved measurement capabilities. Compatibility with commercial processes will further enable economies of scale through mass production, another welcome feature of this approach. Thus chip-scale instrumentation may replace the bulky, expensive, cumbersome-to-operate macro-scale prototypes currently in use for many of these applications. The dissertation examines four specific applications in which the chip may serve as the ideal instrumentation platform. These are nanorod manipulation, polypyrrole bilayer hinge microactuator control, organic transistor hybrid circuits, and contact fluorescence imaging. The thesis is structured around chapters devoted to each of these projects, in addition to a chapter on preliminary work on an RFID system that serves as a wireless interface model. Each of these chapters contains tools and techniques developed for chip-scale instrumentation, from custom scripts for automated layout and data collection to microfabrication processes. Implementation of these tools to develop systems for the

On-chip all-optical wavelength conversion of multicarrier, multilevel modulation (OFDM m-QAM) signals using a silicon waveguide.

Science.gov (United States)

Li, Chao; Gui, Chengcheng; Xiao, Xi; Yang, Qi; Yu, Shaohua; Wang, Jian

2014-08-01

We report on-chip all-optical wavelength conversion of multicarrier multilevel modulation signals in a silicon waveguide. Using orthogonal frequency-division multiplexing (OFDM) combined with advanced multilevel quadrature amplitude modulation (QAM) signals (i.e., OFDM m-QAM), we experimentally demonstrate all-optical wavelength conversions of 3.2 Gbaud/s OFDM 16/32/64/128-QAM signals based on the degenerate four-wave mixing (FWM) nonlinear effect in a silicon waveguide. The measured optical signal-to-noise ratio (OSNR) penalties of wavelength conversion are ∼3  dB for OFDM 16-QAM and ∼4  dB for OFDM 32-QAM at 7% forward error correction (FEC) threshold and ∼3.5  dB for OFDM 64-QAM and ∼4.5  dB for OFDM 128-QAM at 20% FEC threshold. The observed clear constellations of converted idlers imply favorable performance obtained for silicon-waveguide-based OFDM 16/32/64/128-QAM wavelength conversions.

HNT neurons patterned on a parylene-C/silicon dioxide interface

International Nuclear Information System (INIS)

Unsworth, C.P.; Graham, E.S.; Dragunow, M.; Delivopoulos, E.; Murray, A.F.

2010-01-01

Full text: In this article, we describe how we have successfully patterned lines of human teratocarcinoma cell line-derived (HNT) neurons on silicon chip. The silicon chips used in this study were created by depositing lines of the biomaterial Parylene-C onto a silicon dioxide substrate using photolithographic techniques. The chips were then immersed in a range of serums and the HNT neurons cultured for different periods of time. It was found that chips immersed in Foetal Bovine Serum (FBS) and then plated with 70 cells per square mm for 3 h on a Parylene-C thickness of 100 nm provided excellent patterning on the Parylene-C material with a very sharp contrast to the silicon dioxide substrate. The human HNT neuron was chosen as it provides the closest model to adult human neural tissue. The breakthrough in patterning such cells on silicon chip has widespread implication and value as a platform technology; to enable a detailed study of adult human brain circuits for a range of adult human brain pathologies. This could eventually lead to potential new treatments and lead to the development of new drug assays. (author)

First results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

1986-01-01

A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

Silicon photonics: some remaining challenges

Science.gov (United States)

Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

2016-03-01

This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

Reliable Single Chip Genotyping with Semi-Parametric Log-Concave Mixtures

NARCIS (Netherlands)

R.C.A. Rippe (Ralph); J.J. Meulman (Jacqueline); P.H.C. Eilers (Paul)

2012-01-01

textabstractThe common approach to SNP genotyping is to use (model-based) clustering per individual SNP, on a set of arrays. Genotyping all SNPs on a single array is much more attractive, in terms of flexibility, stability and applicability, when developing new chips. A new semi-parametric method,

Integration of lateral porous silicon membranes into planar microfluidics.

Science.gov (United States)

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

High coincidence-to-accidental ratio continuous-wave photon-pair generation in a grating-coupled silicon strip waveguide

DEFF Research Database (Denmark)

Guo, Kai; Christensen, Erik Nicolai; Christensen, Jesper Bjerge

2017-01-01

We demonstrate a very high coincidence-to-accidental ratio of 673 using continuous-wave photon-pair generation in a silicon strip waveguide through spontaneous four-wave mixing. This result is obtained by employing on-chip photonic-crystal-based grating couplers for both low-loss fiber......-to-chip coupling and on-chip suppression of generated spontaneous Raman scattering noise. We measure a minimum heralded second-order correlation of g(H)((2)) (0) = 0.12, demonstrating that our source operates in the single- photon regime with low noise. (C) 2017 The Japan Society of Applied Physics...

Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

CERN Document Server

Llopart Cudie, Xavier; Campbell, M

2007-01-01

Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

International Nuclear Information System (INIS)

Alemi, M.; Campbell, M.; Gys, T.; Mikulec, B.; Piedigrossi, D.; Puertolas, D.; Rosso, E.; Schomaker, R.; Snoeys, W.; Wyllie, K.

2000-01-01

We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface

First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

Energy Technology Data Exchange (ETDEWEB)

Alemi, M.; Campbell, M.; Gys, T. E-mail: thierry.gys@cern.ch; Mikulec, B.; Piedigrossi, D.; Puertolas, D.; Rosso, E.; Schomaker, R.; Snoeys, W.; Wyllie, K

2000-07-11

We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface.

The tensile effect on crack formation in single crystal silicon irradiated by intense pulsed ion beam

Science.gov (United States)

Liang, Guoying; Shen, Jie; Zhang, Jie; Zhong, Haowen; Cui, Xiaojun; Yan, Sha; Zhang, Xiaofu; Yu, Xiao; Le, Xiaoyun

2017-10-01

Improving antifatigue performance of silicon substrate is very important for the development of semiconductor industry. The cracking behavior of silicon under intense pulsed ion beam irradiation was studied by numerical simulation in order to understand the mechanism of induced surface peeling observed by experimental means. Using molecular dynamics simulation based on Stillinger Weber potential, tensile effect on crack growth and propagation in single crystal silicon was investigated. Simulation results reveal that stress-strain curves of single crystal silicon at a constant strain rate can be divided into three stages, which are not similar to metal stress-strain curves; different tensile load velocities induce difference of single silicon crack formation speed; the layered stress results in crack formation in single crystal silicon. It is concluded that the crack growth and propagation is more sensitive to strain rate, tensile load velocity, stress distribution in single crystal silicon.

Cohort analysis of a single nucleotide polymorphism on DNA chips.

Science.gov (United States)

Schwonbeck, Susanne; Krause-Griep, Andrea; Gajovic-Eichelmann, Nenad; Ehrentreich-Förster, Eva; Meinl, Walter; Glatt, Hansrüdi; Bier, Frank F

2004-11-15

A method has been developed to determine SNPs on DNA chips by applying a flow-through bioscanner. As a practical application we demonstrated the fast and simple SNP analysis of 24 genotypes in an array of 96 spots with a single hybridisation and dissociation experiment. The main advantage of this methodical concept is the parallel and fast analysis without any need of enzymatic digestion. Additionally, the DNA chip format used is appropriate for parallel analysis up to 400 spots. The polymorphism in the gene of the human phenol sulfotransferase SULT1A1 was studied as a model SNP. Biotinylated PCR products containing the SNP (The SNP summary web site: ) (mutant) and those containing no mutation (wild-type) were brought onto the chips coated with NeutrAvidin using non-contact spotting. This was followed by an analysis which was carried out in a flow-through biochip scanner while constantly rinsing with buffer. After removing the non-biotinylated strand a fluorescent probe was hybridised, which is complementary to the wild-type sequence. If this probe binds to a mutant sequence, then one single base is not fully matching. Thereby, the mismatched hybrid (mutant) is less stable than the full-matched hybrid (wild-type). The final step after hybridisation on the chip involves rinsing with a buffer to start dissociation of the fluorescent probe from the immobilised DNA strand. The online measurement of the fluorescence intensity by the biochip scanner provides the possibility to follow the kinetics of the hybridisation and dissociation processes. According to the different stability of the full-match and the mismatch, either visual discrimination or kinetic analysis is possible to distinguish SNP-containing sequence from the wild-type sequence.

Hybrid integration of carbon nanotubes in silicon photonic structures

Science.gov (United States)

Durán-Valdeiglesias, E.; Zhang, W.; Alonso-Ramos, C.; Le Roux, X.; Serna, S.; Hoang, H. C.; Marris-Morini, D.; Cassan, E.; Intonti, F.; Sarti, F.; Caselli, N.; La China, F.; Gurioli, M.; Balestrieri, M.; Vivien, L.; Filoramo, A.

2017-02-01

Silicon photonics, due to its compatibility with the CMOS platform and unprecedented integration capability, has become the preferred solution for the implementation of next generation optical interconnects to accomplish high efficiency, low energy consumption, low cost and device miniaturization in one single chip. However, it is restricted by silicon itself. Silicon does not have efficient light emission or detection in the telecommunication wavelength range (1.3 μm-1.5 μm) or any electro-optic effect (i.e. Pockels effect). Hence, silicon photonic needs to be complemented with other materials for the realization of optically-active devices, including III-V for lasing and Ge for detection. The very different requirement of these materials results in complex fabrication processes that offset the cost-effectiveness of the Si photonics approach. For this purpose, carbon nanotubes (CNTs) have recently been proposed as an attractive one-dimensional light emitting material. Interestingly, semiconducting single walled CNTs (SWNTs) exhibit room-temperature photo- and electro-luminescence in the near-IR that could be exploited for the implementation of integrated nano-sources. They can also be considered for the realization of photo-detectors and optical modulators, since they rely on intrinsically fast non-linear effects, such as Stark and Kerr effect. All these properties make SWNTs ideal candidates in order to fabricate a large variety of optoelectronic devices, including near-IR sources, modulators and photodetectors on Si photonic platforms. In addition, solution processed SWNTs can be integrated on Si using spin-coating or drop-casting techniques, obviating the need of complex epitaxial growth or chip bonding approaches. Here, we report on our recent progress in the coupling of SWNTs light emission into optical resonators implemented on the silicon-on-insulator (SOI) platform. .

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications.

Science.gov (United States)

Chen, Zhiyuan; Law, Man-Kay; Mak, Pui-In; Martins, Rui P

2017-02-01

In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 × efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4 V in gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- [Formula: see text] CMOS technology and occupies an active area of 1.54 [Formula: see text]. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 [Formula: see text] from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 [Formula: see text] at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment.

The LHCb Silicon Tracker Project

International Nuclear Information System (INIS)

Agari, M.; Bauer, C.; Baumeister, D.; Blouw, J.; Hofmann, W.; Knoepfle, K.T.; Loechner, S.; Schmelling, M.; Pugatch, V.; Bay, A.; Carron, B.; Frei, R.; Jiminez-Otero, S.; Tran, M.-T.; Voss, H.; Adeva, B.; Esperante, D.; Lois, C.; Vasquez, P.; Bernhard, R.P.; Bernet, R.; Ermoline, Y.; Gassner, J.; Koestner, S.; Lehner, F.; Needham, M.; Siegler, M.; Steinkamp, O.; Straumann, U.; Vollhardt, A.; Volyanskyy, D.

2006-01-01

Two silicon strip detectors, the Trigger Tracker(TT) and the Inner Tracker(Italy) will be constructed for the LHCb experiment. Transverse momentum information extracted from the TT will be used in the Level 1 trigger. The IT is part of the main tracking system behind the magnet. Both silicon detectors will be read out using a custom-developed chip by the ASIC lab in Heidelberg. The signal-over-noise behavior and performance of various geometrical designs of the silicon sensors, in conjunction with the Beetle read-out chip, have been extensively studied in test beam experiments. Results from those experiments are presented, and have been used in the final choice of sensor geometry

Hybrid III-V/silicon lasers

Science.gov (United States)

Kaspar, P.; Jany, C.; Le Liepvre, A.; Accard, A.; Lamponi, M.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Shen, A.; Charbonnier, P.; Mallecot, F.; Duan, G.-H.; Gentner, J.-.; Fedeli, J.-M.; Olivier, S.; Descos, A.; Ben Bakir, B.; Messaoudene, S.; Bordel, D.; Malhouitre, S.; Kopp, C.; Menezo, S.

2014-05-01

The lack of potent integrated light emitters is one of the bottlenecks that have so far hindered the silicon photonics platform from revolutionizing the communication market. Photonic circuits with integrated light sources have the potential to address a wide range of applications from short-distance data communication to long-haul optical transmission. Notably, the integration of lasers would allow saving large assembly costs and reduce the footprint of optoelectronic products by combining photonic and microelectronic functionalities on a single chip. Since silicon and germanium-based sources are still in their infancy, hybrid approaches using III-V semiconductor materials are currently pursued by several research laboratories in academia as well as in industry. In this paper we review recent developments of hybrid III-V/silicon lasers and discuss the advantages and drawbacks of several integration schemes. The integration approach followed in our laboratory makes use of wafer-bonded III-V material on structured silicon-on-insulator substrates and is based on adiabatic mode transfers between silicon and III-V waveguides. We will highlight some of the most interesting results from devices such as wavelength-tunable lasers and AWG lasers. The good performance demonstrates that an efficient mode transfer can be achieved between III-V and silicon waveguides and encourages further research efforts in this direction.

Thin Single Crystal Silicon Solar Cells on Ceramic Substrates: November 2009 - November 2010

Energy Technology Data Exchange (ETDEWEB)

Kumar, A.; Ravi, K. V.

2011-06-01

In this program we have been developing a technology for fabricating thin (< 50 micrometres) single crystal silicon wafers on foreign substrates. We reverse the conventional approach of depositing or forming silicon on foreign substrates by depositing or forming thick (200 to 400 micrometres) ceramic materials on high quality single crystal silicon films ~ 50 micrometres thick. Our key innovation is the fabrication of thin, refractory, and self-adhering 'handling layers or substrates' on thin epitaxial silicon films in-situ, from powder precursors obtained from low cost raw materials. This 'handling layer' has sufficient strength for device and module processing and fabrication. Successful production of full sized (125 mm X 125 mm) silicon on ceramic wafers with 50 micrometre thick single crystal silicon has been achieved and device process flow developed for solar cell fabrication. Impurity transfer from the ceramic to the silicon during the elevated temperature consolidation process has resulted in very low minority carrier lifetimes and resulting low cell efficiencies. Detailed analysis of minority carrier lifetime, metals analysis and device characterization have been done. A full sized solar cell efficiency of 8% has been demonstrated.

Subwavelength silicon photonics

International Nuclear Information System (INIS)

Cheben, P.; Bock, P.J.; Schmid, J.H.; Lapointe, J.; Janz, S.; Xu, D.-X.; Densmore, A.; Delage, A.; Lamontagne, B.; Florjanczyk, M.; Ma, R.

2011-01-01

With the goal of developing photonic components that are compatible with silicon microelectronic integrated circuits, silicon photonics has been the subject of intense research activity. Silicon is an excellent material for confining and manipulating light at the submicrometer scale. Silicon optoelectronic integrated devices have the potential to be miniaturized and mass-produced at affordable cost for many applications, including telecommunications, optical interconnects, medical screening, and biological and chemical sensing. We review recent advances in silicon photonics research at the National Research Council Canada. A new type of optical waveguide is presented, exploiting subwavelength grating (SWG) effect. We demonstrate subwavelength grating waveguides made of silicon, including practical components operating at telecom wavelengths: input couplers, waveguide crossings and spectrometer chips. SWG technique avoids loss and wavelength resonances due to diffraction effects and allows for single-mode operation with direct control of the mode confinement by changing the refractive index of a waveguide core over a range as broad as 1.6 - 3.5 simply by lithographic patterning. The light can be launched to these waveguides with a coupling loss as small as 0.5 dB and with minimal wavelength dependence, using coupling structures similar to that shown in Fig. 1. The subwavelength grating waveguides can cross each other with minimal loss and negligible crosstalk which allows massive photonic circuit connectivity to overcome the limits of electrical interconnects. These results suggest that the SWG waveguides could become key elements for future integrated photonic circuits. (authors)

Modeling optical transmissivity of graphene grate in on-chip silicon photonic device

Directory of Open Access Journals (Sweden)

Iraj S. Amiri

2018-06-01

Full Text Available A three-dimensional (3-D finite-difference-time-domain (FDTD analysis was used to simulate a silicon photonic waveguide. We have calculated power and transmission of the graphene used as single or multilayers to study the light transmission behavior. A new technique has been developed to define the straight silicon waveguide integrated with grate graphene layer. The waveguide has a variable grate spacing to be filled by the graphene layer. The number of graphene atomic layers varies between 100 and 1000 (or 380 nm and 3800 nm, the transmitted power obtained varies as ∼30% and ∼80%. The ∼99%, blocking of the light was occurred in 10,000 (or 38,000 nm atomic layers of the graphene grate. Keywords: Optical waveguide, Silicon waveguide, Grate, Graphene, Optical transmissivity

Ductile-regime turning of germanium and silicon

Science.gov (United States)

Blake, Peter N.; Scattergood, Ronald O.

1989-01-01

Single-point diamond turning of silicon and germanium was investigated in order to clarify the role of cutting depth in coaxing a ductile chip formation in normally brittle substances. Experiments based on the rapid withdrawal of the tool from the workpiece have shown that microfracture damage is a function of the effective depth of cut (as opposed to the nominal cutting depth). In essence, damage created by the leading edge of the tool is removed several revolutions later by lower sections of the tool edge, where the effective cutting depth is less. It appears that a truly ductile cutting response can be achieved only when the effective cutting depth, or critical chip thickness, is less than about 20 nm. Factors such as tool rake angle are significant in that they will affect the actual value of the critical chip thickness for transition from brittle to ductile response. It is concluded that the critical chip thickness is an excellent parameter for measuring the effects of machining conditions on the ductility of the cut and for designing tool-workpiece geometry in both turning and grinding.

Testing of a single-polarity piezoresistive three-dimensional stress-sensing chip

International Nuclear Information System (INIS)

Gharib, H H; Moussa, W A

2013-01-01

A new piezoresistive stress-sensing rosette is developed to extract the components of the three-dimensional (3D) stress tensor using single-polarity (n-type) piezoresistors. This paper presents the testing of a micro-fabricated sensing chip utilizing the developed single-polarity rosette. The testing is conducted using a four-point bending of a chip-on-beam to induce five controlled stress components, which are analyzed both numerically and experimentally. Numerical analysis using finite element analysis is conducted to study the levels of the induced stress components at three rosette-sites and the levels of the stress field non-uniformities, and to simulate the extracted stress components from the sensing rosette. The experimental analysis applied tensile and compressive loads over three rosette-sites at different load increments. The experimentally extracted stress components show good linearity with the applied load and values close to the numerical model. (paper)

Multicore systems on-chip practical software/hardware design

CERN Document Server

Abdallah, Abderazek Ben

2013-01-01

System on chips designs have evolved from fairly simple unicore, single memory designs to complex heterogeneous multicore SoC architectures consisting of a large number of IP blocks on the same silicon. To meet high computational demands posed by latest consumer electronic devices, most current systems are based on such paradigm, which represents a real revolution in many aspects in computing.The attraction of multicore processing for power reduction is compelling. By splitting a set of tasks among multiple processor cores, the operating frequency necessary for each core can be reduced, allowi

Shor's quantum factoring algorithm on a photonic chip.

Science.gov (United States)

Politi, Alberto; Matthews, Jonathan C F; O'Brien, Jeremy L

2009-09-04

Shor's quantum factoring algorithm finds the prime factors of a large number exponentially faster than any other known method, a task that lies at the heart of modern information security, particularly on the Internet. This algorithm requires a quantum computer, a device that harnesses the massive parallelism afforded by quantum superposition and entanglement of quantum bits (or qubits). We report the demonstration of a compiled version of Shor's algorithm on an integrated waveguide silica-on-silicon chip that guides four single-photon qubits through the computation to factor 15.

Note: A silicon-on-insulator microelectromechanical systems probe scanner for on-chip atomic force microscopy

Energy Technology Data Exchange (ETDEWEB)

Fowler, Anthony G.; Maroufi, Mohammad; Moheimani, S. O. Reza, E-mail: Reza.Moheimani@newcastle.edu.au [School of Electrical Engineering and Computer Science, University of Newcastle, Callaghan, NSW 2308 (Australia)

2015-04-15

A new microelectromechanical systems-based 2-degree-of-freedom (DoF) scanner with an integrated cantilever for on-chip atomic force microscopy (AFM) is presented. The silicon cantilever features a layer of piezoelectric material to facilitate its use for tapping mode AFM and enable simultaneous deflection sensing. Electrostatic actuators and electrothermal sensors are used to accurately position the cantilever within the x-y plane. Experimental testing shows that the cantilever is able to be scanned over a 10 μm × 10 μm window and that the cantilever achieves a peak-to-peak deflection greater than 400 nm when excited at its resonance frequency of approximately 62 kHz.

MACSYM. Towards a system of measurement and control on a single chip

Energy Technology Data Exchange (ETDEWEB)

Zannoli, S

1984-03-01

Since it is now possible to produce A/D and D/A integrated circuits on a single chip at a remarkably low cost, the production of an entire system for the acquisition of measurements and control of data on a single chip can be foreseen. The MACSYM (measurement and control system), produced by Analog Devices Inc., contains all its components on a single circuit board. The MACSYM 150 is a multiprocessor with separate analogue and digital buses. Because it contains three CPUS with special functions, it has high operating speeds and can handle a number of programs simultaneously. Since this model is designed for on line and real time measurements of physical quantities it has a number of different stores, including a central store, a store for graphs in colour and fast output and input stores for metered data. The author describes the interface provided and the terminals to which data can be supplied and mentions the programming language used.

Low loss hollow-core waveguide on a silicon substrate

Science.gov (United States)

Yang, Weijian; Ferrara, James; Grutter, Karen; Yeh, Anthony; Chase, Chris; Yue, Yang; Willner, Alan E.; Wu, Ming C.; Chang-Hasnain, Connie J.

2012-07-01

Optical-fiber-based, hollow-core waveguides (HCWs) have opened up many new applications in laser surgery, gas sensors, and non-linear optics. Chip-scale HCWs are desirable because they are compact, light-weight and can be integrated with other devices into systems-on-a-chip. However, their progress has been hindered by the lack of a low loss waveguide architecture. Here, a completely new waveguiding concept is demonstrated using two planar, parallel, silicon-on-insulator wafers with high-contrast subwavelength gratings to reflect light in-between. We report a record low optical loss of 0.37 dB/cm for a 9-μm waveguide, mode-matched to a single mode fiber. Two-dimensional light confinement is experimentally realized without sidewalls in the HCWs, which is promising for ultrafast sensing response with nearly instantaneous flow of gases or fluids. This unique waveguide geometry establishes an entirely new scheme for low-cost chip-scale sensor arrays and lab-on-a-chip applications.

Optical biosensor based on a silicon nanowire ridge waveguide for lab on chip applications

International Nuclear Information System (INIS)

Gamal, Rania; Ismail, Yehea; Swillam, Mohamed A

2015-01-01

We propose a novel sensor using a silicon nanowire ridge waveguide (SNRW). This waveguide is comprised of an array of silicon nanowires on an insulator substrate that has the envelope of a ridge waveguide. The SNRW inherently maximizes the overlap between the material-under-test and the incident light wave by introducing voids to the otherwise bulk structure. When a sensing sample is injected, the voids within the SNRW adopt the refractive index of the material-under-test. Hence, the strong contribution of the material-under-test to the overall modal effective index will greatly augment the sensitivity. Additionally, the ridge structure provides a fabrication convenience as it covers the entire substrate, ensuring that the etching process would not damage the substrate. Finite-difference time-domain simulations are conducted and showed that the percentage change in the effective index due to a 1% change in the surrounding environment is more than 170 times the change perceived in an evanescent-detection based bulk silicon ridge waveguide. Moreover, the SNRW proves to be more sensitive than recent other, non-evanescent sensors. In addition, the detection limit for this structure was revealed to be as small as 10 −8 . A compact bimodal waveguide based on SNRW is designed and tested. It delivers high sensitivity values that offer comparable performance to similar low-index light-guiding sensing configurations; however, our proposed structure has much smaller footprints and allows high dense integration for lab-on-chip applications. (paper)

Implantable Biomedical Signal Monitoring Using RF Energy Harvestingand On-Chip Antenna

Directory of Open Access Journals (Sweden)

Jiann-Shiun Yuan

2015-08-01

Full Text Available This paper presents the design of an energy harvesting wireless and battery-less silicon-on-chip (SoC device that can be implanted in the human body to monitor certain health conditions. The proposed architecture has been designed on TSMC 0.18μm CMOS ICs and is an integrated system with a rectenna (antenna and rectifier and transmitting circuit, all on a single chip powered by an external transmitter and that is small enough to be inserted in the human eye, heart or brain. The transmitting and receiving antennas operate in the 5.8- GHz ISM band and have a -10dB gain. The distinguishing feature of this design is the rectenna that comprises of a singlestage diode connected NMOS rectifier and a 3-D on-chip antenna that occupies only 2.5 × 1 × 2.8 mm3 of chip area and has the ability to communicate within proximity of 5 cm while giving 10% efficiency. The external source is a reader that powers up the RF rectifier in the implantable chip triggering it to start sending data back to the reader enabling an efficient method of health evaluation for the patient.

Poly-silicon quantum-dot single-electron transistors

International Nuclear Information System (INIS)

Kang, Kwon-Chil; Lee, Joung-Eob; Lee, Jung-Han; Lee, Jong-Ho; Shin, Hyung-Cheol; Park, Byung-Gook

2012-01-01

For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also, to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.

Performance tests of developed silicon strip detector by using a 150 GeV electron beam

International Nuclear Information System (INIS)

Hyun, Hyojung; Jung, Sunwoo; Kah, Dongha; Kang, Heedong; Kim, Hongjoo; Park, Hwanbae

2008-01-01

We manufactured and characterized a silicon micro-strip detector to be used in a beam tracker. A silicon detector features a DC-coupled silicon strip sensor with VA1 Prime2 analog readout chips. The silicon strip sensors have been fabricated on 5-in. wafers at Electronics and Telecommunications Research Institute (Daejeon, Korea). The silicon strip sensor is single-sided and has 32 channels with a 1 mm pitch, and its active area is 3.2 by 3.2 cm 2 with 380 μm thickness. The readout electronics consists of VA hybrid, VA Interface, and FlashADC and Control boards. Analog signals from the silicon strip sensor were being processed by the analog readout chips on the VA hybrid board. Analog signals were then changed into digital signals by a 12 bit 25 MHz FlashADC. The digital signals were read out by the Linux-operating PC through the FlashADC-USB2 interface. The DAQ system and analysis programs were written in the framework of ROOT package. The beam test with the silicon detector had been performed at CERN beam facility. We used a 150 GeV electron beam out of the SPS(Super Proton Synchrotron) H2 beam line. We present beam test setup and measurement result of signal-to-noise ratio of each strip channel. (author)

Single-Chip Multiple-Frequency RF MEMS Resonant Platform for Wireless Communications, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — A novel, single-chip, multiple-frequency platform for RF/IF filtering and clock reference based on contour-mode aluminum nitride (AlN) MEMS piezoelectric resonators...

Towards a new generation of pixel detector readout chips

CERN Document Server

Campbell, M; Ballabriga, R.; Frojdh, E.; Heijne, E.; Llopart, X.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.

2016-01-01

The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile- ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.

Single Photon Sources in Silicon Carbide

International Nuclear Information System (INIS)

Brett Johnson

2014-01-01

Single photon sources in semiconductors are highly sought after as they constitute the building blocks of a diverse range of emerging technologies such as integrated quantum information processing, quantum metrology and quantum photonics. In this presentation, we show the first observation of single photon emission from deep level defects in silicon carbide (SiC). The single photon emission is photo-stable at room temperature and surprisingly bright. This represents an exciting alternative to diamond color centers since SiC possesses well-established growth and device engineering protocols. The defect is assigned to the carbon vacancy-antisite pair which gives rise to the AB photoluminescence lines. We discuss its photo-physical properties and their fabrication via electron irradiation. Preliminary measurements on 3C SiC nano-structures will also be discussed. (author)

RBS/channeling analysis of hydrogen-implanted single crystals of FZ silicon and 6H silicon

International Nuclear Information System (INIS)

Irwin, R.B.

1984-01-01

Single crystals of FZ silicon and 6H silicon carbide were implanted with hydrogen ions (50 and 80 keV, respectively) to fluences from 2 x 10 16 H + /cm 2 to 2 x 10 18 H+/cm 2 . The implantations were carried out at three temperatures: approx.95K, 300 K, and approx.800 K. Swelling of the samples was measured by surface profilometry. RBS/channeling was used to obtain the damage profiles and to determine the amount of hydrogen retained in the lattice. The damage profiles are centered around X/sub m/ for the implants into silicon and around R/sub p/ for silicon carbide. For silicon carbide implanted at 95 K and 300 K and for silicon implanted at 95 K, the peak damage region is amorphous for fluences above 8 x 10 16 H + /cm 2 , 4 x 10 17 H + /cm 2 , and 2 x 10 17 H + /cm 2 , respectively. Silicon implanted at 300 and 800 K and silicon carbide implanted at 800 K remain crystalline up to fluences of 1 x 10 18 H + /cm 2 . The channeling damage results agree with previously reported TEM and electron diffraction data. The predictions of a simple disorder-accumulation model with a linear annealing term explains qualitatively the observed damage profiles in silicon carbide. Quantitatively, however, the model predicts faster development of the damage profiles than is observed at low fluences in both silicon and silicon carbide. For samples implanted at 300 and 800 K, the model also predicts substantially less peak disorder than is observed. The effect of the surface, the retained hydrogen, the shape of S/sub D/(X), and the need for a nonlinear annealing term may be responsible for the discrepancy

High speed video recording system on a chip for detonation jet engine testing

Directory of Open Access Journals (Sweden)

Samsonov Alexander N.

2018-01-01

Full Text Available This article describes system on a chip development for high speed video recording purposes. Current research was started due to difficulties in selection of FPGAs and CPUs which include wide bandwidth, high speed and high number of multipliers for real time signal analysis implementation. Current trend of high density silicon device integration will result soon in a hybrid sensor-controller-memory circuit packed in a single chip. This research was the first step in a series of experiments in manufacturing of hybrid devices. The current task is high level syntheses of high speed logic and CPU core in an FPGA. The work resulted in FPGA-based prototype implementation and examination.

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

Science.gov (United States)

Beheim, Glenn M.

2003-01-01

installed in water-cooled jackets, as shown. This was a severe test because the pressure-sensing chips were exposed to the hot combustion gases. Prior to the installation of the SiC pressure sensors, two high-temperature silicon sensors, installed in the same locations, did not survive a single engine run. The durability of the leadless SiC pressure sensor was demonstrated when both SiC sensors operated properly throughout the two runs that were conducted.

Ring resonator-based single-chip 1x8 optical beam forming network in LPCVD waveguide technology

NARCIS (Netherlands)

Zhuang, L.; Roeloffzen, C.G.H.; Heideman, Rene; Borreman, A.; Meijerink, Arjan; van Etten, Wim; Koonen, A.M.J.; Leijtens, X.J.M.; van den Boom, H.P.A.; Verdurmen, E.J.M.; Molina Vázquez, J.

2006-01-01

Optical ring resonators (ORRs) are good candidates to provide continuously tunable delay in beam forming networks (BFNs) for phased array antenna systems. Delay and splitting/combining elements can be integrated on a single optical chip to form an OBFN. A state-of-the-art 1×8 OBFN chip has been

Silicon Drift Detectors - A Novel Technology for Vertex Detectors

Science.gov (United States)

Lynn, D.

1996-10-01

Silicon Drift Detectors (SDD) are novel position sensing silicon detectors which operate in a manner analogous to gas drift detectors. Single SDD's were shown in the CERN NA45 experiment to permit excellent spatial resolution (pseudo-rapidity. Over the last three years we undertook a concentrated R+D effort to optimize the performance of the detector by minimizing the inactive area, the operating voltage and the data volume. We will present test results from several wafer prototypes. The charge produced by the passage of ionizing particles through the bulk of the detectors is collected on segmented anodes, with a pitch of 250 μm, on the far edges of the detector. The anodes are wire-bonded to a thick film multi-chip module which contains preamplifier/shaper chips and CMOS based switched capacitor arrays used as an analog memory pipeline. The ADC is located off-detector. The complete readout chain from the wafer to the DAQ will be presented. Finally we will show physics performance simulations based on the resolution achieved by the SVT prototypes.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

Science.gov (United States)

Bartelink, Dirk J.

1998-11-01

recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Chips 2020 a guide to the future of nanoelectronics

CERN Document Server

2012-01-01

The chips in present-day cell phones already contain billions of sub-100-nanometer transistors. By 2020, however, we will see systems-on-chips with trillions of 10-nanometer transistors. But this will be the end of the miniaturization, because yet smaller transistors, containing just a few control atoms, are subject to statistical fluctuations and thus no longer useful. We also need to worry about a potential energy crisis, because in less than five years from now, with current chip technology, the internet alone would consume the total global electrical power! This book presents a new, sustainable roadmap towards ultra-low-energy (femto-Joule), high-performance electronics. The focus is on the energy-efficiency of the various chip functions: sensing, processing, and communication, in a top-down spirit involving new architectures such as silicon brains, ultra-low-voltage circuits, energy harvesting, and 3D silicon technologies. Recognized world leaders from industry and from the research community share thei...

X-ray quality increasing system controlled by single-chip microcomputer in single phase fluoroscopy unit

International Nuclear Information System (INIS)

Wang Qiaolin; Gu Hongmei

2004-01-01

Objective: To decrease the amount of radiation that doctor and patient receives by increasing X-ray quality. Methods: Using Single-chip Microcomputer technology, test and modulate AC(Alternating Current) from high voltage generator by IGBT. X-ray tube generates X-rays only at high energy area. Thus the amount of radiation decreases. Results: The tube current decreases remarkably and the amount of radiation that doctor and patient receives decreases effectively. Conclusion: the system can effectively decrease the amount of radiation and is widely applicable to the upgrade of all kinds of single phase X-ray units. (authors)

The development of the time-keeping clock with TS-1 single chip microcomputer.

Science.gov (United States)

Zhou, Jiguang; Li, Yongan

The authors have developed a time-keeping clock with Intel 8751 single chip microcomputer that has been successfully used in time-keeping station. The hard-soft ware design and performance of the clock are introduced.

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems.

Science.gov (United States)

Indiveri, Giacomo

2008-09-03

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

Directory of Open Access Journals (Sweden)

Giacomo Indiveri

2008-09-01

Full Text Available Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Efficient On-chip Optical Microresonator for Optical Comb Generation: Design and Fabrication

Science.gov (United States)

Han, Kyunghun

An optical frequency comb is a series of equally spaced frequency components. It has gained much attention since Nobel physics prize was awarded John L. Hall and Theodor W. Hansch for their contribution to the optical frequency comb technique in 2005. The optical frequency comb has been extensively studied because of its precision as a tool for spectroscopy, and is now widely used in bio- and chemical sensors, optical clocks, mode-locked dark pulse generation, soliton generation, and optical communication. Recently, thanks to the developments in nanotechnology, the optical frequency comb generation is made possible at a chip-scale level with microresonators. However, because the threshold power of the optical frequency comb generation is beyond the capability of the on-chip laser source, efficient microresonator is required. Here, we demonstrate an ultra-compact and highly efficient strip-slot direct mode coupler, aiming to achieve slotted silicon microresonator cladded with nonlinear polymer Poly-DDMEBT in SOI platform. As an application of the strip-slot direct mode coupling, a double slot fiber-to-chip edge coupler is demonstrated showing 2 dB insertion loss reduction compared to the conventional single tip edge coupler. For silicon nitride platform, we investigated evanescent wave coupling of microresonator, focusing on bus waveguide geometry optimization. The optimized waveguide width offers an efficient excitation of a fundamental mode in the resonator waveguide. This investigation can benefit low threshold comb generation by enhancing the extinction ratio. We experimentally demonstrated the high Q-factor micro-ring resonator with intrinsic Q of 12.6 million as well as the single FSR comb generation with 63 mW.

TID-dependent current measurements of IBL readout chips

Energy Technology Data Exchange (ETDEWEB)

Dette, Karola [TU Dortmund, Experimentelle Physik IV (Germany); CERN (Switzerland); Collaboration: ATLAS Pixel-Collaboration

2016-07-01

The ATLAS detector consists of several subsystems with a hybrid pixel detector as the innermost component of the tracking system. The pixel detector has been composed of three layers of silicon sensor assemblies during the first data taking run of the LHC and has been upgraded with a new 4th layer, the so-called Insertable B-Layer (IBL), in summer 2014. Each silicon sensor of the IBL is connected to a Front End readout chip (FE-I4) via bump bonds. During the first year of data taking an increase of the LV current produced by the readout chips was observed. This increase could be traced back to radiation damage inside the silicon. The dependence of the current on the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations and will be presented in this talk.

Ultrahigh-speed hybrid laser for silicon photonic integrated chips

DEFF Research Database (Denmark)

Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

2013-01-01

Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

Integration of microelectronic chips in microfluidic systems on printed circuit board

International Nuclear Information System (INIS)

Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

2012-01-01

A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

The fabrication of a double-layer atom chip with through silicon vias for an ultra-high-vacuum cell

International Nuclear Information System (INIS)

Chuang, Ho-Chiao; Lin, Yun-Siang; Lin, Yu-Hsin; Huang, Chi-Sheng

2014-01-01

This study presents a double-layer atom chip that provides users with increased diversity in the design of the wire patterns and flexibility in the design of the magnetic field. It is more convenient for use in atomic physics experiments. A negative photoresist, SU-8, was used as the insulating layer between the upper and bottom copper wires. The electrical measurement results show that the upper and bottom wires with a width of 100 µm can sustain a 6 A current without burnout. Another focus of this study is the double-layer atom chips integrated with the through silicon via (TSV) technique, and anodically bonded to a Pyrex glass cell, which makes it a desired vacuum chamber for atomic physics experiments. Thus, the bonded glass cell not only significantly reduces the overall size of the ultra-high-vacuum (UHV) chamber but also conducts the high current from the backside to the front side of the atom chip via the TSV under UHV (9.5 × 10 −10  Torr). The TSVs with a diameter of 70 µm were etched through by the inductively coupled plasma ion etching and filled by the bottom-up copper electroplating method. During the anodic bonding process, the electroplated copper wires and TSVs on atom chips also need to pass the examination of the required bonding temperature of 250 °C, under an applied voltage of 1000 V. Finally, the UHV test of the double-layer atom chips with TSVs at room temperature can be reached at 9.5 × 10 −10  Torr, thus satisfying the requirements of atomic physics experiments under an UHV environment. (paper)

Analysis of single-photon time resolution of FBK silicon photomultipliers

International Nuclear Information System (INIS)

Acerbi, Fabio; Ferri, Alessandro; Gola, Alberto; Zorzi, Nicola; Piemonte, Claudio

2015-01-01

We characterized and analyzed an important feature of silicon photomultipliers: the single-photon time resolution (SPTR). We characterized the SPTR of new RGB (Red–Green–Blue) type Silicon Photomultipliers and SPADs produced at FBK (Trento, Italy), studying its main limiting factors. We compared time resolution of 1×1 mm 2 and 3×3 mm 2 SiPMs and a single SiPM cell (i.e. a SPAD with integrated passive-quenching), employing a mode-locked pulsed laser with 2-ps wide pulses. We estimated the contribution of front-end electronic-noise, of cell-to-cell uniformity, and intrinsic cell time-resolution. At a single-cell level, we compared the results obtained with different layouts. With a circular cell with a top metallization covering part of the edge and enhancing the signal extraction, we reached ~20 ps FWHM of time resolution

Mixed-signal early vision chip with embedded image and programming memories and digital I/O

Science.gov (United States)

Linan-Cembrano, Gustavo; Rodriguez-Vazquez, Angel; Dominguez-Castro, Rafael; Espejo, Servando

2003-04-01

From a system level perspective, this paper presents a 128x128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

Monolithic nanoscale photonics-electronics integration in silicon and other group IV elements

CERN Document Server

Radamson, Henry

2014-01-01

Silicon technology is evolving rapidly, particularly in board-to-board or chip-to chip applications. Increasingly, the electronic parts of silicon technology will carry out the data processing, while the photonic parts take care of the data communication. For the first time, this book describes the merging of photonics and electronics in silicon and other group IV elements. It presents the challenges, the limitations, and the upcoming possibilities of these developments. The book describes the evolution of CMOS integrated electronics, status and development, and the fundamentals of silicon p

Control of single-electron charging of metallic nanoparticles onto amorphous silicon surface.

Science.gov (United States)

Weis, Martin; Gmucová, Katarína; Nádazdy, Vojtech; Capek, Ignác; Satka, Alexander; Kopáni, Martin; Cirák, Július; Majková, Eva

2008-11-01

Sequential single-electron charging of iron oxide nanoparticles encapsulated in oleic acid/oleyl amine envelope and deposited by the Langmuir-Blodgett technique onto Pt electrode covered with undoped hydrogenated amorphous silicon film is reported. Single-electron charging (so-called quantized double-layer charging) of nanoparticles is detected by cyclic voltammetry as current peaks and the charging effect can be switched on/off by the electric field in the surface region induced by the excess of negative/positive charged defect states in the amorphous silicon layer. The particular charge states in amorphous silicon are created by the simultaneous application of a suitable bias voltage and illumination before the measurement. The influence of charged states on the electric field in the surface region is evaluated by the finite element method. The single-electron charging is analyzed by the standard quantized double layer model as well as two weak-link junctions model. Both approaches are in accordance with experiment and confirm single-electron charging by tunnelling process at room temperature. This experiment illustrates the possibility of the creation of a voltage-controlled capacitor for nanotechnology.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

Science.gov (United States)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All

Development and characterisation of a radiation hard readout chip for the LHCb experiment

CERN Document Server

Baumeister, Daniel; Stachel, Johanna

2003-01-01

Within this doctoral thesis parts of the radiation hard readout chip Beetle have been developed and characterised, before and after irradiation. The design work included the analogue memory with the corresponding readout amplifier as well as components of the digital control circuitry. An interface compatible with the I2C-standard and the control logic for event readout have been implemented. A scheme has been developed which ensures the robustness of the Beetle chip against Single-Event Upset (SEU). This includes the consistent use of triple-redundant memory devices together with a self-triggered correction in parts of the circuit. The Beetle ASIC is a 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier and a CR-RC pulse shaper. It features an equivalent noise charge of ENC = 497 e− +48.3 e−/pF·Cin. The analogue memory is a switched capacitor array, which provides a latency of max. 4 µs. The 128 channels are transmitted off chip in 9...

Observing the morphology of single-layered embedded silicon nanocrystals by using temperature-stable TEM membranes

Directory of Open Access Journals (Sweden)

Sebastian Gutsch

2015-04-01

Full Text Available We use high-temperature-stable silicon nitride membranes to investigate single layers of silicon nanocrystal ensembles by energy filtered transmission electron microscopy. The silicon nanocrystals are prepared from the precipitation of a silicon-rich oxynitride layer sandwiched between two SiO2 diffusion barriers and subjected to a high-temperature annealing. We find that such single layers are very sensitive to the annealing parameters and may lead to a significant loss of excess silicon. In addition, these ultrathin layers suffer from significant electron beam damage that needs to be minimized in order to image the pristine sample morphology. Finally we demonstrate how the silicon nanocrystal size distribution develops from a broad to a narrow log-normal distribution, when the initial precipitation layer thickness and stoichiometry are below a critical value.

Amorphous silicon based particle detectors

OpenAIRE

Wyrsch, N.; Franco, A.; Riesen, Y.; Despeisse, M.; Dunand, S.; Powolny, F.; Jarron, P.; Ballif, C.

2012-01-01

Radiation hard monolithic particle sensors can be fabricated by a vertical integration of amorphous silicon particle sensors on top of CMOS readout chip. Two types of such particle sensors are presented here using either thick diodes or microchannel plates. The first type based on amorphous silicon diodes exhibits high spatial resolution due to the short lateral carrier collection. Combination of an amorphous silicon thick diode with microstrip detector geometries permits to achieve micromete...

Flowmeter with silicon flow tube

NARCIS (Netherlands)

Lammerink, Theodorus S.J.; Dijkstra, Marcel; Haneveld, J.; Lötters, Joost Conrad

2009-01-01

A flowmeter comprising a system chip with a silicon substrate provided on a carrier, in an opening whereof at least one silicon flow tube is provided for transporting a medium whose flow rate is to be measured, said tube having two ends that issue via a wall of the opening into channels coated with

Debugging systems-on-chip communication-centric and abstraction-based techniques

CERN Document Server

Vermeulen, Bart

2014-01-01

This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly.  Readers learn step-by-step the key requirements for debugging a modern, silicon SOC implementation, nine factors that complicate this debugging task, and a new debug approach that addresses these requirements and complicating factors.  The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach is discussed in detail, showing how it helps to meet debug requirements and address the nine, previously identified factors that complicate debugging silicon implementations of SOCs. The authors also derive the debug infrastructure requirements to support debugging of a silicon implementation of an SOC with their CSAR debug approach. This debug infrastructure consists of a generic on-chip debug architecture, a configurable automated design-for-debug ...

Modeling optical transmissivity of graphene grate in on-chip silicon photonic device

Science.gov (United States)

Amiri, Iraj S.; Ariannejad, M. M.; Jalil, M. A.; Ali, J.; Yupapin, P.

2018-06-01

A three-dimensional (3-D) finite-difference-time-domain (FDTD) analysis was used to simulate a silicon photonic waveguide. We have calculated power and transmission of the graphene used as single or multilayers to study the light transmission behavior. A new technique has been developed to define the straight silicon waveguide integrated with grate graphene layer. The waveguide has a variable grate spacing to be filled by the graphene layer. The number of graphene atomic layers varies between 100 and 1000 (or 380 nm and 3800 nm), the transmitted power obtained varies as ∼30% and ∼80%. The ∼99%, blocking of the light was occurred in 10,000 (or 38,000 nm) atomic layers of the graphene grate.

Analysis of single-photon time resolution of FBK silicon photomultipliers

Energy Technology Data Exchange (ETDEWEB)

Acerbi, Fabio, E-mail: acerbi@fbk.eu; Ferri, Alessandro; Gola, Alberto; Zorzi, Nicola; Piemonte, Claudio

2015-07-01

We characterized and analyzed an important feature of silicon photomultipliers: the single-photon time resolution (SPTR). We characterized the SPTR of new RGB (Red–Green–Blue) type Silicon Photomultipliers and SPADs produced at FBK (Trento, Italy), studying its main limiting factors. We compared time resolution of 1×1 mm{sup 2} and 3×3 mm{sup 2} SiPMs and a single SiPM cell (i.e. a SPAD with integrated passive-quenching), employing a mode-locked pulsed laser with 2-ps wide pulses. We estimated the contribution of front-end electronic-noise, of cell-to-cell uniformity, and intrinsic cell time-resolution. At a single-cell level, we compared the results obtained with different layouts. With a circular cell with a top metallization covering part of the edge and enhancing the signal extraction, we reached ~20 ps FWHM of time resolution.

A silicon central pattern generator controls locomotion in vivo.

Science.gov (United States)

Vogelstein, R J; Tenore, F; Guevremont, L; Etienne-Cummings, R; Mushahwar, V K

2008-09-01

We present a neuromorphic silicon chip that emulates the activity of the biological spinal central pattern generator (CPG) and creates locomotor patterns to support walking. The chip implements ten integrate-and-fire silicon neurons and 190 programmable digital-to-analog converters that act as synapses. This architecture allows for each neuron to make synaptic connections to any of the other neurons as well as to any of eight external input signals and one tonic bias input. The chip's functionality is confirmed by a series of experiments in which it controls the motor output of a paralyzed animal in real-time and enables it to walk along a three-meter platform. The walking is controlled under closed-loop conditions with the aide of sensory feedback that is recorded from the animal's legs and fed into the silicon CPG. Although we and others have previously described biomimetic silicon locomotor control systems for robots, this is the first demonstration of a neuromorphic device that can replace some functions of the central nervous system in vivo.

Development of γ dose rate monitor based on FPGA and single-chip microcomputer

International Nuclear Information System (INIS)

He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

2009-01-01

A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

Development of based on 89S51 single-chip microcomputer electronic dosimeter

International Nuclear Information System (INIS)

Wang Junhua; Zhou Jiachao; Sun Jianghan; Du Xiao

2009-01-01

It describes the main design features and basic properties of based on 89S51 single-chip microcomputer electronic dosimeter with wide range and multi purposes. The dosimeter can display dose rate or accumulative dose or the maximum dose rate, record accumulative dose, the maximum dose rate and classes. (authors)

Prototyping of Silicon Strip Detectors for the Inner Tracker of the ALICE Experiment

CERN Document Server

Sokolov, Oleksiy

2006-01-01

The ALICE experiment at CERN will study heavy ion collisions at a center-of-mass energy 5.5∼TeV per nucleon. Particle tracking around the interaction region at radii r<45 cm is done by the Inner Tracking System (ITS), consisting of six cylindrical layers of silicon detectors. The outer two layers of the ITS use double-sided silicon strip detectors. This thesis focuses on testing of these detectors and performance studies of the detector module prototypes at the beam test. Silicon strip detector layers will require about 20 thousand HAL25 front-end readout chips and about 3.5 thousand hybrids each containing 6 HAL25 chips. During the assembly procedure, chips are bonded on a patterned TAB aluminium microcables which connect to all the chip input and output pads, and then the chips are assembled on the hybrids. Bonding failures at the chip or hybrid level may either render the component non-functional or deteriorate its the performance such that it can not be used for the module production. After each bond...

A nuclear pulse amplitude acquisition system based on 80C31 single-chip microcomputer

International Nuclear Information System (INIS)

Zhao Xiuliang; Qu Guopu; Guo Lanying; Zhang Songbai

1999-01-01

A kind of multichannel nuclear pulse amplitude signal acquisition system is described, which is composed of pulse peak detector, integrated S/H circuit, A/D converter and 80C31 single-chip microcomputer

Gain-Enhanced On-Chip Antenna Utilizing Artificial Magnetic Conductor Reflecting Surface at 94 GHz

KAUST Repository

Nafe, Mahmoud

2015-08-04

Nowadays, there is a growing demand for high frequency-bandwidth mm-wave (30-300 GHz) electronic wireless transceiver systems to support applications such as high data-rate wireless communication and high resolution imaging. Such mm-wave systems are becoming more feasible due to the extreme transistor downscaling in silicon-based integrated circuits, which enabled densely-integrated high-speed elec- tronics operating up to more than 100 GHz with low fabrication cost. To further enhance system integrability, it is required to implement all wireless system compo- nents on the chip. Presently, the last major barrier to true System-on-Chip (SoC) realization is the antenna implementation on the silicon chip. Although at mm-wave frequencies the antenna size becomes small enough to fit on chip, the antenna performance is greatly deteriorated due the high conductivity and high relative permittivity of the silicon substrate. The negative e↵ects of the silicon substrate could be avoided by using a metallic reflecting surface on top of silicon, which e↵ectively isolates the antenna from the silicon. However, this approach has the shortcoming of having to implement the antenna on the usually very thin silicon oxide layer of a typical CMOS fabrication process (10’s of μm). This forces the antenna to be in a very close proximity (less than one hundredth of a wavelength) to the reflecting surface. In this regime, the use of conventional metallic reflecting surface for silicon shielding has severe e↵ects on the antenna performance as it tends to reduce the antenna radiation resistance resulting in most of the energy being absorbed rather than radiated. In this work, the use of specially patterned reflecting surfaces for improving on- chip antenna performance is investigated. By using a periodic metallic surface on top of a grounded substrate, the structure can mimic the behavior of a perfect mag- netic conductor, hence called Artificial Magnetic Conductor (AMC) surface

Luneburg lens in silicon photonics.

Science.gov (United States)

Di Falco, Andrea; Kehr, Susanne C; Leonhardt, Ulf

2011-03-14

The Luneburg lens is an aberration-free lens that focuses light from all directions equally well. We fabricated and tested a Luneburg lens in silicon photonics. Such fully-integrated lenses may become the building blocks of compact Fourier optics on chips. Furthermore, our fabrication technique is sufficiently versatile for making perfect imaging devices on silicon platforms.

The PASTA chip for the silicon micro strip sensor of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Riccardi, Alberto; Brinkmann, Kai-Thomas; Di Pietro, Valentino; Quagli, Tommaso; Schnell, Robert; Zaunick, Hans-Georg [II. Physikalisches Institut, Justus-Liebig-Universitaet, Giessen (Germany); Ritman, James; Stockmanns, Tobias; Zambanini, Andre [Forschungszentrum Juelich (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy); Collaboration: PANDA-Collaboration

2016-07-01

In the Micro Vertex Detector, which is the innermost detector of PANDA, there are two different types of sensors: hybrid pixel and double sided micro strips. My work is focused on the development of the ASIC readout for the strips, which in the PANDA experiment must cope with a hit rate up to 50 kHz per channel. The energy loss measurement of the particles crossing the silicon sensor is obtained by implementing the Time over Threshold technique. The first PASTA (PANDA Strip ASIC) prototype is based on a Time to Digital Converter with an analog clock interpolator which combines good time resolution with a low power consumption. A full size chip was developed in a 0.11μ m CMOS technology and delivered in Autumn 2015. It features 64 channels with both analog and digital parts, a digital global controller, LVDS drivers and integrated bias. In the presentation, an overview of PASTA and the results of the first tests is presented.

Silicon photonics for telecommunications and biomedicine

CERN Document Server

Fathpour, Sasan

2011-01-01

Given silicon's versatile material properties, use of low-cost silicon photonics continues to move beyond light-speed data transmission through fiber-optic cables and computer chips. Its application has also evolved from the device to the integrated-system level. A timely overview of this impressive growth, Silicon Photonics for Telecommunications and Biomedicine summarizes state-of-the-art developments in a wide range of areas, including optical communications, wireless technologies, and biomedical applications of silicon photonics. With contributions from world experts, this reference guides

High surface area silicon materials: fundamentals and new technology.

Science.gov (United States)

Buriak, Jillian M

2006-01-15

Crystalline silicon forms the basis of just about all computing technologies on the planet, in the form of microelectronics. An enormous amount of research infrastructure and knowledge has been developed over the past half-century to construct complex functional microelectronic structures in silicon. As a result, it is highly probable that silicon will remain central to computing and related technologies as a platform for integration of, for instance, molecular electronics, sensing elements and micro- and nanoelectromechanical systems. Porous nanocrystalline silicon is a fascinating variant of the same single crystal silicon wafers used to make computer chips. Its synthesis, a straightforward electrochemical, chemical or photochemical etch, is compatible with existing silicon-based fabrication techniques. Porous silicon literally adds an entirely new dimension to the realm of silicon-based technologies as it has a complex, three-dimensional architecture made up of silicon nanoparticles, nanowires, and channel structures. The intrinsic material is photoluminescent at room temperature in the visible region due to quantum confinement effects, and thus provides an optical element to electronic applications. Our group has been developing new organic surface reactions on porous and nanocrystalline silicon to tailor it for a myriad of applications, including molecular electronics and sensing. Integration of organic and biological molecules with porous silicon is critical to harness the properties of this material. The construction and use of complex, hierarchical molecular synthetic strategies on porous silicon will be described.

Ultrafast all-optical order-to-chaos transition in silicon photonic crystal chips

KAUST Repository

Bruck, Roman

2016-06-08

The interaction of light with nanostructured materials provides exciting new opportunities for investigating classical wave analogies of quantum phenomena. A topic of particular interest forms the interplay between wave physics and chaos in systems where a small perturbation can drive the behavior from the classical to chaotic regime. Here, we report an all-optical laser-driven transition from order to chaos in integrated chips on a silicon photonics platform. A square photonic crystal microcavity at telecom wavelengths is tuned from an ordered into a chaotic regime through a perturbation induced by ultrafast laser pulses in the ultraviolet range. The chaotic dynamics of weak probe pulses in the near infrared is characterized for different pump-probe delay times and at various positions in the cavity, with high spatial accuracy. Our experimental analysis, confirmed by numerical modelling based on random matrices, demonstrates that nonlinear optics can be used to control reversibly the chaotic behavior of light in optical resonators. (Figure presented.) . © 2016 by WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Variable-Width Datapath for On-Chip Network Static Power Reduction

Energy Technology Data Exchange (ETDEWEB)

Michelogiannakis, George; Shalf, John

2013-11-13

With the tight power budgets in modern large-scale chips and the unpredictability of application traffic, on-chip network designers are faced with the dilemma of designing for worst- case bandwidth demands and incurring high static power overheads, or designing for an average traffic pattern and risk degrading performance. This paper proposes adaptive bandwidth networks (ABNs) which divide channels and switches into lanes such that the network provides just the bandwidth necessary in each hop. ABNs also activate input virtual channels (VCs) individually and take advantage of drowsy SRAM cells to eliminate false VC activations. In addition, ABNs readily apply to silicon defect tolerance with just the extra cost for detecting faults. For application traffic, ABNs reduce total power consumption by an average of 45percent with comparable performance compared to single-lane power-gated networks, and 33percent compared to multi-network designs.

Isolating and moving single atoms using silicon nanocrystals

Science.gov (United States)

Carroll, Malcolm S.

2010-09-07

A method is disclosed for isolating single atoms of an atomic species of interest by locating the atoms within silicon nanocrystals. This can be done by implanting, on the average, a single atom of the atomic species of interest into each nanocrystal, and then measuring an electrical charge distribution on the nanocrystals with scanning capacitance microscopy (SCM) or electrostatic force microscopy (EFM) to identify and select those nanocrystals having exactly one atom of the atomic species of interest therein. The nanocrystals with the single atom of the atomic species of interest therein can be sorted and moved using an atomic force microscope (AFM) tip. The method is useful for forming nanoscale electronic and optical devices including quantum computers and single-photon light sources.

Tailoring the optical constants in single-crystal silicon with embedded silver nanostructures for advanced silicon photonics applications

International Nuclear Information System (INIS)

Akhter, Perveen; Huang, Mengbing; Spratt, William; Kadakia, Nirag; Amir, Faisal

2015-01-01

Plasmonic effects associated with metal nanostructures are expected to hold the key to tailoring light emission/propagation and harvesting solar energy in materials including single crystal silicon which remains the backbone in the microelectronics and photovoltaics industries but unfortunately, lacks many functionalities needed for construction of advanced photonic and optoelectronics devices. Currently, silicon plasmonic structures are practically possible only in the configuration with metal nanoparticles or thin film arrays on a silicon surface. This does not enable one to exploit the full potential of plasmonics for optical engineering in silicon, because the plasmonic effects are dominant over a length of ∼50 nm, and the active device region typically lies below the surface much beyond this range. Here, we report on a novel method for the formation of silver nanoparticles embedded within a silicon crystal through metal gettering from a silver thin film deposited at the surface to nanocavities within the Si created by hydrogen ion implantation. The refractive index of the Ag-nanostructured layer is found to be 3–10% lower or higher than that of silicon for wavelengths below or beyond ∼815–900 nm, respectively. Around this wavelength range, the optical extinction values increase by a factor of 10–100 as opposed to the pure silicon case. Increasing the amount of gettered silver leads to an increased extinction as well as a redshift in wavelength position for the resonance. This resonance is attributed to the surface plasmon excitation of the resultant silver nanoparticles in silicon. Additionally, we show that the profiles for optical constants in silicon can be tailored by varying the position and number of nanocavity layers. Such silicon crystals with embedded metal nanostructures would offer novel functional base structures for applications in silicon photonics, optoelectronics, photovoltaics, and plasmonics

Silicon on insulator by ion implantation: A dream or a reality

Energy Technology Data Exchange (ETDEWEB)

Pinizzotto, R F [Ultrastructure, Inc., Richardson, TX (USA)

1985-03-01

One method of producing a silicon-on-oxide structure is to implant a sufficient dose of oxygen into a conventional silicon substrate to synthesize a layer of SiO/sub 2/ just below the surface. If the proper implant conditions are maintained, the top silicon layer will be a single crystal. The required doses are large, but the use of commercially available medium current implanters can reduce the time to 25 minutes per wafer. This adds about $ 10 per chip in process related costs. A very large implanter (100 mA analyzed beam) may not be the best approach for scaling up the process. The power in the beam and the power required for operation of the machine are both enormous. A more conservative approach of using multiple medium current implanters may prove to be more economical in the long run.

A monolithic glass chip for active single-cell sorting based on mechanical phenotyping.

Science.gov (United States)

Faigle, Christoph; Lautenschläger, Franziska; Whyte, Graeme; Homewood, Philip; Martín-Badosa, Estela; Guck, Jochen

2015-03-07

The mechanical properties of biological cells have long been considered as inherent markers of biological function and disease. However, the screening and active sorting of heterogeneous populations based on serial single-cell mechanical measurements has not been demonstrated. Here we present a novel monolithic glass chip for combined fluorescence detection and mechanical phenotyping using an optical stretcher. A new design and manufacturing process, involving the bonding of two asymmetrically etched glass plates, combines exact optical fiber alignment, low laser damage threshold and high imaging quality with the possibility of several microfluidic inlet and outlet channels. We show the utility of such a custom-built optical stretcher glass chip by measuring and sorting single cells in a heterogeneous population based on their different mechanical properties and verify sorting accuracy by simultaneous fluorescence detection. This offers new possibilities of exact characterization and sorting of small populations based on rheological properties for biological and biomedical applications.

A 2.4GHz ULP OOK single-chip transceiver for healthcare applications

NARCIS (Netherlands)

Vidojkovic, M.; Huang, X.; Harpe, P.J.A.; Rampu, S.; Zhou, C.; Huang, Li; Molengraft, van de J.; Imamura, K.; Büsze, B.; Bouwens, F.; Konijnenburg, M.; Santana, J.; Breeschoten, A.; Huisken, J.; Philips, K.; Dolmans, G.; Groot, de H.W.H.

2011-01-01

This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36–2.4 GHz medical BAN and 2.4–2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct

Design of silicon-based fractal antennas

KAUST Repository

Ghaffar, Farhan A.

2012-11-20

This article presents Sierpinski carpet fractal antennas implemented in conventional low resistivity (Ï =10 Ω cm) as well as high resistivity (Ï =1500 Ω cm) silicon mediums. The fractal antenna is 36% smaller as compared with a typical patch antenna at 24 GHz and provides 13% bandwidth on high resistivity silicon, suitable for high data rate applications. For the first time, an on-chip fractal antenna array is demonstrated in this work which provides double the gain of a single fractal element as well as enhanced bandwidth. A custom test fixture is utilized to measure the radiation pattern and gain of these probe-fed antennas. In addition to gain and impedance characterization, measurements have also been made to study intrachip communication through these antennas. The comparison between the low resistivity and high resistivity antennas indicate that the former is not a suitable medium for array implementation and is only suitable for short range communication whereas the latter is appropriate for short and medium range wireless communication. The design is well-suited for compact, high data rate System-on-Chip (SoC) applications as well as for intrachip communication such as wireless global clock distribution in synchronous systems. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:180-186, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27245 Copyright © 2012 Wiley Periodicals, Inc.

Design of silicon-based fractal antennas

KAUST Repository

Ghaffar, Farhan A.; Shamim, Atif

2012-01-01

This article presents Sierpinski carpet fractal antennas implemented in conventional low resistivity (Ï =10 Ω cm) as well as high resistivity (Ï =1500 Ω cm) silicon mediums. The fractal antenna is 36% smaller as compared with a typical patch antenna at 24 GHz and provides 13% bandwidth on high resistivity silicon, suitable for high data rate applications. For the first time, an on-chip fractal antenna array is demonstrated in this work which provides double the gain of a single fractal element as well as enhanced bandwidth. A custom test fixture is utilized to measure the radiation pattern and gain of these probe-fed antennas. In addition to gain and impedance characterization, measurements have also been made to study intrachip communication through these antennas. The comparison between the low resistivity and high resistivity antennas indicate that the former is not a suitable medium for array implementation and is only suitable for short range communication whereas the latter is appropriate for short and medium range wireless communication. The design is well-suited for compact, high data rate System-on-Chip (SoC) applications as well as for intrachip communication such as wireless global clock distribution in synchronous systems. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:180-186, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27245 Copyright © 2012 Wiley Periodicals, Inc.

Spectral diffusion of quasi localized excitons in single silicon nanocrystals

Energy Technology Data Exchange (ETDEWEB)

Martin, Joerg; Cichos, Frank [Centre for nanostructured Materials and Analytics, Institute of Physics, Chemnitz University of Technology, Reichenhainer Street 70, 09107 Chemnitz (Germany); Borczyskowski, Christian von, E-mail: Borczyskowski@physik.tu-chemnitz.de [Centre for nanostructured Materials and Analytics, Institute of Physics, Chemnitz University of Technology, Reichenhainer Street 70, 09107 Chemnitz (Germany)

2012-08-15

Evolution in time of photoluminescence spectra of SiO{sub x} capped single silicon nanocrystals has been investigated by means of confocal optical spectroscopy at room temperature. Large spectral jumps between subsequent spectra of up to 40 meV have been detected leading to noticeable line broadening and variation in the electron-phonon coupling. Further, a correlation between emission energy and emission intensity has been found and discussed in terms of an intrinsic Stark effect. Anti-correlated variations of the electron-phonon coupling to Si and SiO{sub 2} phonons as a function of photoluminescence energy indicate that the nearly localized excition is to some extent coupled to phonons in the shell covering the silicon nanocrystal. However, coupling is reduced upon increasing Stark effect, while at the same time coupling to phonons of the Si core increases. - Highlights: Black-Right-Pointing-Pointer Single silicon nanocrystals are detected via confocal microscopy. Black-Right-Pointing-Pointer Photoluminescence energies fluctuate strongly in time. Black-Right-Pointing-Pointer Spectral fluctuation is described in the form of spectral diffusion. Black-Right-Pointing-Pointer Dynamic processes are strongly controlled by electron-phonon coupling.

The readout system of the new H1 silicon detectors

International Nuclear Information System (INIS)

Buerger, J.; Hansen, K.; Lange, W.; Prell, S.; Zimmermann, W.; Henschel, H.; Haynes, W.J.; Noyes, G.W.; Joensson, L.; Gabathuler, K.; Horisberger, R.; Wagener, M.; Eichler, R.; Erdmann, W.; Niggli, H.; Pitzl, D.

1995-03-01

The H1 detector at HERA at DESY undergoes presently a major upgrade. In this context silicon strip detectors have been installed at beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 Silicon Detectors and performance data of the complete readout chain. (orig.)

Silicon Dioxide Thin Film Mediated Single Cell Nucleic Acid Isolation

Science.gov (United States)

Bogdanov, Evgeny; Dominova, Irina; Shusharina, Natalia; Botman, Stepan; Kasymov, Vitaliy; Patrushev, Maksim

2013-01-01

A limited amount of DNA extracted from single cells, and the development of single cell diagnostics make it necessary to create a new highly effective method for the single cells nucleic acids isolation. In this paper, we propose the DNA isolation method from biomaterials with limited DNA quantity in sample, and from samples with degradable DNA based on the use of solid-phase adsorbent silicon dioxide nanofilm deposited on the inner surface of PCR tube. PMID:23874571

A single chip with multiple talents

CERN Multimedia

Francesco Poppi

2010-01-01

The Medipix chips developed at CERN are being used in a variety of fields: from medicine to education and back to high-tech engineering. The scene is set for a bright future for this versatile technology.   The Medipix chip. It didn’t take long for a brilliant team of physicists and engineers who were working on pixel detectors for the LHC to realize that the technology had great potential in medical imaging. This was the birth of the Medipix project. Fifteen years later, with the collaboration of 18 research institutes, the team has produced an advanced version of the initial ideas: Medipix3 is a device that can measure very accurately the position and energy of the photons (one by one) that hit the associated detector. Radiography and computed tomography (CT) use X-ray photons to study the human body. The different energies of the photons in the beam can be thought of as the colours of the X-ray spectrum. This is why the use of Medipix3 chips in such diagnostic techniques is referred...

Probing and irradiation tests of ALICE pixel chip wafers and sensors

CERN Document Server

Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

2004-01-01

In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

Fully Printed Flexible Single-Chip RFID Tag with Light Detection Capabilities

Directory of Open Access Journals (Sweden)

Aniello Falco

2017-03-01

Full Text Available A printed passive radiofrequency identification (RFID tag in the ultra-high frequency band for light and temperature monitoring is presented. The whole tag has been manufactured by printing techniques on a flexible substrate. Antenna and interconnects are realized with silver nanoparticles via inkjet printing. A sprayed photodetector performs the light monitoring, whereas temperature measurement comes from an in-built sensor in the silicon RFID chip. One of the advantages of this system is the digital read-out and transmission of the sensors information on the RFID tag that ensures reliability. Furthermore, the use of printing techniques allows large-scale manufacturing and the direct fabrication of the tag on the desired surface. This work proves for the first time the feasibility of the embedment of large-scale organic photodetectors onto inkjet printed RFID tags. Here, we solve the problem of integration of different manufacturing techniques to develop an optimal final sensor system.

Controlling growth density and patterning of single crystalline silicon nanowires

International Nuclear Information System (INIS)

Chang, Tung-Hao; Chang, Yu-Cheng; Liu, Fu-Ken; Chu, Tieh-Chi

2010-01-01

This study examines the usage of well-patterned Au nanoparticles (NPs) as a catalyst for one-dimensional growth of single crystalline Si nanowires (NWs) through the vapor-liquid-solid (VLS) mechanism. The study reports the fabrication of monolayer Au NPs through the self-assembly of Au NPs on a 3-aminopropyltrimethoxysilane (APTMS)-modified silicon substrate. Results indicate that the spin coating time of Au NPs plays a crucial role in determining the density of Au NPs on the surface of the silicon substrate and the later catalysis growth of Si NWs. The experiments in this study employed optical lithography to pattern Au NPs, treating them as a catalyst for Si NW growth. The patterned Si NW structures easily produced and controlled Si NW density. This approach may be useful for further studies on single crystalline Si NW-based nanodevices and their properties.

Ultra-high-speed Optical Signal Processing using Silicon Photonics

DEFF Research Database (Denmark)

Oxenløwe, Leif Katsuo; Ji, Hua; Jensen, Asger Sellerup

with a photonic layer on top to interconnect them. For such systems, silicon is an attractive candidate enabling both electronic and photonic control. For some network scenarios, it may be beneficial to use optical on-chip packet switching, and for high data-density environments one may take advantage...... of the ultra-fast nonlinear response of silicon photonic waveguides. These chips offer ultra-broadband wavelength operation, ultra-high timing resolution and ultra-fast response, and when used appropriately offer energy-efficient switching. In this presentation we review some all-optical functionalities based...... on silicon photonics. In particular we use nano-engineered silicon waveguides (nanowires) [1] enabling efficient phasematched four-wave mixing (FWM), cross-phase modulation (XPM) or self-phase modulation (SPM) for ultra-high-speed optical signal processing of ultra-high bit rate serial data signals. We show...

ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon

Science.gov (United States)

Tracy, Lisa; Luhman, Dwight; Carr, Stephen; Borchardt, John; Bishop, Nathaniel; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Witzel, Wayne; Blume-Kohout, Robin; Nielsen, Erik; Lilly, Michael; Carroll, Malcolm

In this talk we will discuss electron spin resonance experiments in single donor silicon qubit devices fabricated at Sandia National Labs. A self-aligned device structure consisting of a polysilicon gate SET located adjacent to the donor is used for donor electron spin readout. Using a cryogenic HEMT amplifier next to the silicon device, we demonstrate spin readout at 100 kHz bandwidth and Rabi oscillations with 0.96 visibility. Electron spin resonance measurements on these devices show a linewidth of 30 kHz and coherence times T2* = 10 us and T2 = 0.3 ms. We also discuss estimates of the fidelity of our donor electron spin qubit measurements using gate set tomography. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon.

Wafer of Intel Pentium 4 Prescott Chips

CERN Multimedia

Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

Why I am optimistic about the silicon-photonic route to quantum computing

Directory of Open Access Journals (Sweden)

Terry Rudolph

2017-03-01

Full Text Available This is a short overview explaining how building a large-scale, silicon-photonic quantum computer has been reduced to the creation of good sources of 3-photon entangled states (and may simplify further. Given such sources, each photon needs to pass through a small, constant, number of components, interfering with at most 2 other spatially nearby photons, and current photonics engineering has already demonstrated the manufacture of thousands of components on two-dimensional semiconductor chips with performance that, once scaled up, allows the creation of tens of thousands of photons entangled in a state universal for quantum computation. At present the fully integrated, silicon-photonic architecture we envisage involves creating the required entangled states by starting with single-photons produced non-deterministically by pumping silicon waveguides (or cavities combined with on-chip filters and nanowire superconducting detectors to herald that a photon has been produced. These sources are multiplexed into being near-deterministic, and the single photons then passed through an interferometer to non-deterministically produce small entangled states—necessarily multiplexed to near-determinism again. This is followed by a “ballistic” scattering of the small-scale entangled photons through an interferometer such that some photons are detected, leaving the remainder in a large-scale entangled state which is provably universal for quantum computing implemented by single-photon measurements. There are a large number of questions regarding the optimum ways to make and use the final cluster state, dealing with static imperfections, constructing the initial entangled photon sources and so on, that need to be investigated before we can aim for millions of qubits capable of billions of computational time steps. The focus in this article is on the theoretical side of such questions.

Building blocks for a polarimeter-on-a-chip

International Nuclear Information System (INIS)

Stevenson, Thomas R.; Hsieh, W.-T.; Schneider, Gideon; Travers, Douglas; Cao, Nga; Wollack, Edward; Limon, Michele; Kogut, Alan

2006-01-01

For the 'Primordial Anisotropy Polarization Pathfinder Array (PAPPA)' balloon flight project, we have designed and made thin-film niobium microstrip circuits as building blocks for a 'polarimeter-on-a-chip' in which superconducting transmission lines are used to couple millimeter wave signals from planar antennas to superconducting transition edge sensor (TES) detectors. Our goal is to demonstrate technology for precision measurements of the polarization of the cosmic microwave background. To enable characterization and verification of our microstrip components, we have incorporated waveguide probes on each chip that can bring millimeter wave signals from a room temperature vector network analyzer to the superconducting circuits on the chip and back again for S-parameter measurements. We have designed a planar antenna and RF choke on the probes to efficiently couple radiation between waveguide and thin-film microstrip. To support the probe antennas in waveguides, we sculpted thin silicon cantilevers that extend from an edge of each silicon chip into a pair of waveguides within a specially designed split-block mount. This technique will allow us to make calibrated measurements at low temperatures of the velocity, impedance, and loss properties of our niobium transmission lines, the frequency response of microstrip filters, hybrid couplers, or terminations, and the performance of integrated detectors

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto

2014-02-25

In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

A chip-scale, telecommunications-band frequency conversion interface for quantum emitters.

Science.gov (United States)

Agha, Imad; Ates, Serkan; Davanço, Marcelo; Srinivasan, Kartik

2013-09-09

We describe a chip-scale, telecommunications-band frequency conversion interface designed for low-noise operation at wavelengths desirable for common single photon emitters. Four-wave-mixing Bragg scattering in silicon nitride waveguides is used to demonstrate frequency upconversion and downconversion between the 980 nm and 1550 nm wavelength regions, with signal-to-background levels > 10 and conversion efficiency of ≈ -60 dB at low continuous wave input pump powers ( 25 % in existing geometries. Finally, we present waveguide designs that can be used to connect shorter wavelength (637 nm to 852 nm) quantum emitters with 1550 nm.

EIGER: Next generation single photon counting detector for X-ray applications

Energy Technology Data Exchange (ETDEWEB)

Dinapoli, Roberto, E-mail: roberto.dinapoli@psi.ch [Paul Scherrer Institut, 5232 Villigen PSI (Switzerland); Bergamaschi, Anna; Henrich, Beat; Horisberger, Roland; Johnson, Ian; Mozzanica, Aldo; Schmid, Elmar; Schmitt, Bernd; Schreiber, Akos; Shi, Xintian; Theidel, Gerd [Paul Scherrer Institut, 5232 Villigen PSI (Switzerland)

2011-09-11

EIGER is an advanced family of single photon counting hybrid pixel detectors, primarily aimed at diffraction experiments at synchrotrons. Optimization of maximal functionality and minimal pixel size (using a 0.25{mu}m process and conserving the radiation tolerant design) has resulted in 75x75{mu}m{sup 2} pixels. Every pixel comprises a preamplifier, shaper, discriminator (with a 6 bit DAC for threshold trimming), a configurable 4/8/12 bit counter with double buffering, as well as readout, control and test circuitry. A novel feature of this chip is its double buffered counter, meaning a next frame can be acquired while the previous one is being readout. An array of 256x256 pixels fits on a {approx}2x2cm{sup 2} chip and a sensor of {approx}8x4cm{sup 2} will be equipped with eight readout chips to form a module containing 0.5 Mpixel. Several modules can then be tiled to form larger area detectors. Detectors up to 4x8 modules (16 Mpixel) are planned. To achieve frame rates of up to 24 kHz the readout architecture is highly parallel, and the chip readout happens in parallel on 32 readout lines with a 100 MHz Double Data Rate clock. Several chips and singles (i.e. a single chip bump-bonded to a single chip silicon sensor) were tested both with a lab X-ray source and at Swiss Light Source (SLS) beamlines. These tests demonstrate the full functionality of the chip and provide a first assessment of its performance. High resolution X-ray images and 'high speed movies' were produced, even without threshold trimming, at the target system frame rates (up to {approx}24kHz in 4 bit mode). In parallel, dedicated hardware, firmware and software had to be developed to comply with the enormous data rate the chip is capable of delivering. Details of the chip design and tests will be given, as well as highlights of both test and final readout systems.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

Large-scale membrane transfer process: its application to single-crystal-silicon continuous membrane deformable mirror

International Nuclear Information System (INIS)

Wu, Tong; Sasaki, Takashi; Hane, Kazuhiro; Akiyama, Masayuki

2013-01-01

This paper describes a large-scale membrane transfer process developed for the construction of large-scale membrane devices via the transfer of continuous single-crystal-silicon membranes from one substrate to another. This technique is applied for fabricating a large stroke deformable mirror. A bimorph spring array is used to generate a large air gap between the mirror membrane and the electrode. A 1.9 mm × 1.9 mm × 2 µm single-crystal-silicon membrane is successfully transferred to the electrode substrate by Au–Si eutectic bonding and the subsequent all-dry release process. This process provides an effective approach for transferring a free-standing large continuous single-crystal-silicon to a flexible suspension spring array with a large air gap. (paper)

A 3 W High-Voltage Single-Chip Green Light-Emitting Diode with Multiple-Cells Network

Directory of Open Access Journals (Sweden)

W. Wang

2015-01-01

Full Text Available A parallel and series network structure was introduced into the design of the high-voltage single-chip (HV-SC light-emitting diode to inhibit the effect of current crowding and to improve the yield. Using such a design, a 6.6×5 mm2 large area LED chip of 24 parallel stages was demonstrated with 3 W light output power (LOP at the current of 500 mA. The forward voltage was measured to be 83 V with the same current injection, corresponding to 3.5 V for a single stage. The LED chip’s average thermal resistance was identified to be 0.28 K/W by using infrared thermography analysis.

Flexible integration of free-standing nanowires into silicon photonics.

Science.gov (United States)

Chen, Bigeng; Wu, Hao; Xin, Chenguang; Dai, Daoxin; Tong, Limin

2017-06-14

Silicon photonics has been developed successfully with a top-down fabrication technique to enable large-scale photonic integrated circuits with high reproducibility, but is limited intrinsically by the material capability for active or nonlinear applications. On the other hand, free-standing nanowires synthesized via a bottom-up growth present great material diversity and structural uniformity, but precisely assembling free-standing nanowires for on-demand photonic functionality remains a great challenge. Here we report hybrid integration of free-standing nanowires into silicon photonics with high flexibility by coupling free-standing nanowires onto target silicon waveguides that are simultaneously used for precise positioning. Coupling efficiency between a free-standing nanowire and a silicon waveguide is up to ~97% in the telecommunication band. A hybrid nonlinear-free-standing nanowires-silicon waveguides Mach-Zehnder interferometer and a racetrack resonator for significantly enhanced optical modulation are experimentally demonstrated, as well as hybrid active-free-standing nanowires-silicon waveguides circuits for light generation. These results suggest an alternative approach to flexible multifunctional on-chip nanophotonic devices.Precisely assembling free-standing nanowires for on-demand photonic functionality remains a challenge. Here, Chen et al. integrate free-standing nanowires into silicon waveguides and show all-optical modulation and light generation on silicon photonic chips.

Nonlinear silicon photonics

Science.gov (United States)

Tsia, Kevin K.; Jalali, Bahram

2010-05-01

An intriguing optical property of silicon is that it exhibits a large third-order optical nonlinearity, with orders-ofmagnitude larger than that of silica glass in the telecommunication band. This allows efficient nonlinear optical interaction at relatively low power levels in a small footprint. Indeed, we have witnessed a stunning progress in harnessing the Raman and Kerr effects in silicon as the mechanisms for enabling chip-scale optical amplification, lasing, and wavelength conversion - functions that until recently were perceived to be beyond the reach of silicon. With all the continuous efforts developing novel techniques, nonlinear silicon photonics is expected to be able to reach even beyond the prior achievements. Instead of providing a comprehensive overview of this field, this manuscript highlights a number of new branches of nonlinear silicon photonics, which have not been fully recognized in the past. In particular, they are two-photon photovoltaic effect, mid-wave infrared (MWIR) silicon photonics, broadband Raman effects, inverse Raman scattering, and periodically-poled silicon (PePSi). These novel effects and techniques could create a new paradigm for silicon photonics and extend its utility beyond the traditionally anticipated applications.

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

Science.gov (United States)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

Chip-to-chip SnO2 nanowire network sensors for room temperature H2 detection

Science.gov (United States)

Köck, A.; Brunet, E.; Mutinati, G. C.; Maier, T.; Steinhauer, S.

2012-06-01

The employment of nanowires is a very powerful strategy to improve gas sensor performance. We demonstrate a gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected SnO2 nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device is able to detect a H2 concentration of only 20 ppm in synthetic air with ~ 60% relative humidity at room temperature. At an operating temperature of 300°C a concentration of 50 ppm H2 results in a sensitivity of 5%. At this elevated temperature the sensor shows a linear response in a concentration range between 10 ppm and 100 ppm H2. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.

X-γ dose rate continuous monitor with wide range based on single-chip microcomputer

International Nuclear Information System (INIS)

Wu Debo; Ling Qiu; Guo Lanying; Yang Binhua

2007-01-01

This paper describes a concept about circuit designing of X-γ dose rate continuous monitor with wide range based on single-chip microcomputer, and also presents the design procedure of hardware and software, and gives several methods for solving the design procedure of hardware and software with emphasis. (authors)

Strong coupling of a single electron in silicon to a microwave photon

Science.gov (United States)

Mi, X.; Cady, J. V.; Zajac, D. M.; Deelman, P. W.; Petta, J. R.

2017-01-01

Silicon is vital to the computing industry because of the high quality of its native oxide and well-established doping technologies. Isotopic purification has enabled quantum coherence times on the order of seconds, thereby placing silicon at the forefront of efforts to create a solid-state quantum processor. We demonstrate strong coupling of a single electron in a silicon double quantum dot to the photonic field of a microwave cavity, as shown by the observation of vacuum Rabi splitting. Strong coupling of a quantum dot electron to a cavity photon would allow for long-range qubit coupling and the long-range entanglement of electrons in semiconductor quantum dots.

A Facile Droplet-Chip-Time-Resolved Inductively Coupled Plasma Mass Spectrometry Online System for Determination of Zinc in Single Cell.

Science.gov (United States)

Wang, Han; Chen, Beibei; He, Man; Hu, Bin

2017-05-02

Single cell analysis is a significant research field in recent years reflecting the heterogeneity of cells in a biological system. In this work, a facile droplet chip was fabricated and online combined with time-resolved inductively coupled plasma mass spectrometry (ICPMS) via a microflow nebulizer for the determination of zinc in single HepG2 cells. On the focusing geometric designed PDMS microfluidic chip, the aqueous cell suspension was ejected and divided by hexanol to generate droplets. The droplets encapsulated single cells remain intact during the transportation into ICP for subsequent detection. Under the optimized conditions, the frequency of droplet generation is 3-6 × 10 6 min -1 , and the injected cell number is 2500 min -1 , which can ensure the single cell encapsulation. ZnO nanoparticles (NPs) were used for the quantification of zinc in single cells, and the accuracy was validated by conventional acid digestion-ICPMS method. The ZnO NPs incubated HepG2 cells were analyzed as model samples, and the results exhibit the heterogeneity of HepG2 cells in the uptake/adsorption of ZnO NPs. The developed online droplet-chip-ICPMS analysis system achieves stable single cell encapsulation and has high throughput for single cell analysis. It has the potential in monitoring the content as well as distribution of trace elements/NPs at the single cell level.

Realization of a counter/timer circuit used in digital pulse height analysis in a single chip

International Nuclear Information System (INIS)

Mahmoud, I.I.

2000-01-01

This paper presents a single chip realization of a counter circuit, which is used in random signal processing and nuclear gamma ray spectrometers. The circuit contains a counter to count the repetition rate of a selected pulse train coming from a single channel analyzer circuit. Also, it contains a timer to measure the accumulation period. The timer possesses a predetermined time facility so that processing lasts for a certain adjustable predetermined period. The counter and the timer are synchronized to start and stop simultaneously at the beginning and end of the counting interval. A multiplexed BCD to 7-segment decoder/driver is also included in the circuit. The multiplexing allows the decrease of pin count of the chip.Two stages are designed, simulated for a single channel, however more stages and channels can be added by copying the designed circuits. Schematic flow of Xilinx v.1.2I is used as the design strategy with top-level schematic design containing VHDL and schematic macros

Single-chip RF communications systems in CMOS

DEFF Research Database (Denmark)

Olesen, Ole

1997-01-01

The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

Science.gov (United States)

Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

2011-01-01

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

On-Chip Sensing of Thermoelectric Thin Film’s Merit

OpenAIRE

Xiao, Zhigang; Zhu, Xiaoshan

2015-01-01

Thermoelectric thin films have been widely explored for thermal-to-electrical energy conversion or solid-state cooling, because they can remove heat from integrated circuit (IC) chips or micro-electromechanical systems (MEMS) devices without involving any moving mechanical parts. In this paper, we report using silicon diode-based temperature sensors and specific thermoelectric devices to characterize the merit of thermoelectric thin films. The silicon diode temperature sensors and thermoelect...

Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

Science.gov (United States)

Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

2013-11-15

We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

Spin Measurements of an Electron Bound to a Single Phosphorous Donor in Silicon

Science.gov (United States)

Luhman, D. R.; Nguyen, K.; Tracy, L. A.; Carr, S. M.; Borchardt, J.; Bishop, N. C.; Ten Eyck, G. A.; Pluym, T.; Wendt, J.; Carroll, M. S.; Lilly, M. P.

2014-03-01

The spin of an electron bound to a single donor implanted in silicon is potentially useful for quantum information processing. We report on our efforts to measure and manipulate the spin of an electron bound to a single P donor in silicon. A low number of P donors are implanted using a self-aligned process into a silicon substrate in close proximity to a single-electron-transistor (SET) defined by lithographically patterned polysilicon gates. The SET is used to sense the occupancy of the electron on the donor and for spin read-out. An adjacent transmission line allows the application of microwave pulses to rotate the spin of the electron. We will present data from various experiments designed to exploit these capabilities. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. The work was supported by Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

Heterogeneously integrated silicon photonics for the mid-infrared and spectroscopic sensing.

Science.gov (United States)

Chen, Yu; Lin, Hongtao; Hu, Juejun; Li, Mo

2014-07-22

Besides being the foundational material for microelectronics, crystalline silicon has long been used for the production of infrared lenses and mirrors. More recently, silicon has become the key material to achieve large-scale integration of photonic devices for on-chip optical interconnect and signal processing. For optics, silicon has significant advantages: it offers a very high refractive index and is highly transparent in the spectral range from 1.2 to 8 μm. To fully exploit silicon’s superior performance in a remarkably broad range and to enable new optoelectronic functionalities, here we describe a general method to integrate silicon photonic devices on arbitrary foreign substrates. In particular, we apply the technique to integrate silicon microring resonators on mid-infrared compatible substrates for operation in the mid-infrared. These high-performance mid-infrared optical resonators are utilized to demonstrate, for the first time, on-chip cavity-enhanced mid-infrared spectroscopic analysis of organic chemicals with a limit of detection of less than 0.1 ng.

Annealing effect of H+ -implanted single crystal silicon on strain and crystal structure

International Nuclear Information System (INIS)

Duo Xinzhong; Liu Weili; Zhang Miao; Gao Jianxia; Fu Xiaorong; Lin Chenglu

2000-01-01

The work focuses on the rocking curves of H + -implanted single silicon crystal detected by Four-Crystal X-ray diffractometer. The samples were annealed under different temperatures. Lattice defect in H + -implanted silicon crystals was detected by Rutherford Backscattering Spectrometry. It appeared that H-related complex did not crush until annealing temperature reached about 400 degree C. At that temperature H 2 was formed, deflated in silicon lattice and strained the lattice. But defects did not come into being in large quantity. The lattice was undamaged. When annealing temperature reached 500 degree C, strain induced by H 2 deflation crashed the silicon lattice. A large number of defects were formed. At the same time bubbles in the crystal and blister/flaking on the surface could be observed

The composing technique of fast and large scale nuclear data acquisition and control system with single chip microcomputers and PC computers

International Nuclear Information System (INIS)

Xu Zurun; Wu Shiying; Liu Haitao; Yao Yangsen; Wang Yingguan; Yang Chaowen

1998-01-01

The technique of employing single-chip microcomputers and PC computers to compose a fast and large scale nuclear data acquisition and control system was discussed in detail. The optimum composition mode of this kind of system, the acquisition and control circuit unit based on single-chip microcomputers, the real-time communication methods and the software composition under the Windows 3.2 were also described. One, two and three dimensional spectra measured by this system were demonstrated

The composing technique of fast and large scale nuclear data acquisition and control system with single chip microcomputers and PC computers

International Nuclear Information System (INIS)

Xu Zurun; Wu Shiying; Liu Haitao; Yao Yangsen; Wang Yingguan; Yang Chaowen

1997-01-01

The technique of employing single-chip microcomputers and PC computers to compose a fast and large scale nuclear data acquisition and control system was discussed in detail. The optimum composition mode of this kind of system, the acquisition and control circuit unit based on single-chip microcomputers, the real-time communication methods and the software composition under the Windows 3.2 were also described. One, two and three dimensional spectra measured by this system were demonstrated

Design of automatic curtain controlled by wireless based on single chip 51 microcomputer

Science.gov (United States)

Han, Dafeng; Chen, Xiaoning

2017-08-01

In order to realize the wireless control of the domestic intelligent curtains, a set of wireless intelligent curtain control system based on 51 single chip microcomputer have been designed in this paper. The intelligent curtain can work in the manual mode, automatic mode and sleep mode and can be carried out by the button and mobile phone APP mode loop switch. Through the photosensitive resistance module and human pyroelectric infrared sensor to collect the indoor light value and the data whether there is the person in the room, and then after single chip processing, the motor drive module is controlled to realize the positive inversion of the asynchronous motor, the intelligent opening and closing of the curtain have been realized. The operation of the motor can be stopped under the action of the switch and the curtain opening and closing and timing switch can be controlled through the keys and mobile phone APP. The optical fiber intensity, working mode, curtain state and system time are displayed by LCD1602. The system has a high reliability and security under practical testing and with the popularity and development of smart home, the design has broad market prospects.

On-chip hybrid photonic-plasmonic light concentrator for nanofocusing in an integrated silicon photonics platform.

Science.gov (United States)

Luo, Ye; Chamanzar, Maysamreza; Apuzzo, Aniello; Salas-Montiel, Rafael; Nguyen, Kim Ngoc; Blaize, Sylvain; Adibi, Ali

2015-02-11

The enhancement and confinement of electromagnetic radiation to nanometer scale have improved the performances and decreased the dimensions of optical sources and detectors for several applications including spectroscopy, medical applications, and quantum information. Realization of on-chip nanofocusing devices compatible with silicon photonics platform adds a key functionality and provides opportunities for sensing, trapping, on-chip signal processing, and communications. Here, we discuss the design, fabrication, and experimental demonstration of light nanofocusing in a hybrid plasmonic-photonic nanotaper structure. We discuss the physical mechanisms behind the operation of this device, the coupling mechanisms, and how to engineer the energy transfer from a propagating guided mode to a trapped plasmonic mode at the apex of the plasmonic nanotaper with minimal radiation loss. Optical near-field measurements and Fourier modal analysis carried out using a near-field scanning optical microscope (NSOM) show a tight nanofocusing of light in this structure to an extremely small spot of 0.00563(λ/(2n(rmax)))(3) confined in 3D and an exquisite power input conversion of 92%. Our experiments also verify the mode selectivity of the device (low transmission of a TM-like input mode and high transmission of a TE-like input mode). A large field concentration factor (FCF) of about 4.9 is estimated from our NSOM measurement with a radius of curvature of about 20 nm at the apex of the nanotaper. The agreement between our theory and experimental results reveals helpful insights about the operation mechanism of the device, the interplay of the modes, and the gradual power transfer to the nanotaper apex.

Single-mode glass waveguide technology for optical interchip communication on board level

Science.gov (United States)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a

On nanostructured silicon success

DEFF Research Database (Denmark)

Sigmund, Ole; Jensen, Jakob Søndergaard; Frandsen, Lars Hagedorn

2016-01-01

Recent Letters by Piggott et al. 1 and Shen et al. 2 claim the smallest ever dielectric wave length and polarization splitters. The associated News & Views article by Aydin3 states that these works “are the first experimental demonstration of on-chip, silicon photonic components based on complex...

Towards Single-Step Biofabrication of Organs on a Chip via 3D Printing.

Science.gov (United States)

Knowlton, Stephanie; Yenilmez, Bekir; Tasoglu, Savas

2016-09-01

Organ-on-a-chip engineering employs microfabrication of living tissues within microscale fluid channels to create constructs that closely mimic human organs. With the advent of 3D printing, we predict that single-step fabrication of these devices will enable rapid design and cost-effective iterations in the development stage, facilitating rapid innovation in this field. Copyright © 2016 Elsevier Ltd. All rights reserved.

Hybrid Integrated Silicon Microfluidic Platform for Fluorescence Based Biodetection

Directory of Open Access Journals (Sweden)

André Darveau

2007-09-01

Full Text Available The desideratum to develop a fully integrated Lab-on-a-chip device capable ofrapid specimen detection for high throughput in-situ biomedical diagnoses and Point-of-Care testing applications has called for the integration of some of the novel technologiessuch as the microfluidics, microphotonics, immunoproteomics and Micro ElectroMechanical Systems (MEMS. In the present work, a silicon based microfluidic device hasbeen developed for carrying out fluorescence based immunoassay. By hybrid attachment ofthe microfluidic device with a Spectrometer-on-chip, the feasibility of synthesizing anintegrated Lab-on-a-chip type device for fluorescence based biosensing has beendemonstrated. Biodetection using the microfluidic device has been carried out usingantigen sheep IgG and Alexafluor-647 tagged antibody particles and the experimentalresults prove that silicon is a compatible material for the present application given thevarious advantages it offers such as cost-effectiveness, ease of bulk microfabrication,superior surface affinity to biomolecules, ease of disposability of the device etc., and is thussuitable for fabricating Lab-on-a-chip type devices.

Latest Advances in the Generation of Single Photons in Silicon Carbide

Directory of Open Access Journals (Sweden)

Albert Boretti

2016-06-01

Full Text Available The major barrier for optical quantum information technologies is the absence of reliable single photons sources providing non-classical light states on demand which can be easily and reliably integrated with standard processing protocols for quantum device fabrication. New methods of generation at room temperature of single photons are therefore needed. Heralded single photon sources are presently being sought based on different methods built on different materials. Silicon Carbide (SiC has the potentials to serve as the preferred material for quantum applications. Here, we review the latest advances in single photon generation at room temperatures based on SiC.

GigaTracker, a Thin and Fast Silicon Pixels Tracker

CERN Document Server

Velghe, Bob; Bonacini, Sandro; Ceccucci, Augusto; Kaplon, Jan; Kluge, Alexander; Mapelli, Alessandro; Morel, Michel; Noël, Jérôme; Noy, Matthew; Perktold, Lukas; Petagna, Paolo; Poltorak, Karolina; Riedler, Petra; Romagnoli, Giulia; Chiozzi, Stefano; Cotta Ramusino, Angelo; Fiorini, Massimiliano; Gianoli, Alberto; Petrucci, Ferruccio; Wahl, Heinrich; Arcidiacono, Roberta; Jarron, Pierre; Marchetto, Flavio; Gil, Eduardo Cortina; Nuessle, Georg; Szilasi, Nicolas

2014-01-01

GigaTracker, the NA62’s upstream spectrometer, plays a key role in the kinematically constrained background suppression for the study of the K + ! p + n ̄ n decay. It is made of three independent stations, each of which is a six by three cm 2 hybrid silicon pixels detector. To meet the NA62 physics goals, GigaTracker has to address challenging requirements. The hit time resolution must be better than 200 ps while keeping the total thickness of the sensor to less than 0.5 mm silicon equivalent. The 200 μm thick sensor is divided into 18000 300 μm 300 μm pixels bump-bounded to ten independent read-out chips. The chips use an end-of-column architecture and rely on time-over- threshold discriminators. A station can handle a crossing rate of 750 MHz. Microchannel cooling technology will be used to cool the assembly. It allows us to keep the sensor close to 0 C with 130 μm of silicon in the beam area. The sensor and read-out chip performance were validated using a 45 pixel demonstrator with a laser test setu...

Remote monitor used on the 13N leak rate measurement system based on single-chip microcomputer

International Nuclear Information System (INIS)

Tang Rulong; Qiu Xiaoping; Guo Lanying

2012-01-01

It describes a design on Remote Monitor based on single-chip microcomputer, and also presents the design procedure of hardware and software for circuit design, and gives some of specific instructions about the important parts of the design. (authors)

Mechanical and electrical properties of ultra-thin chips and flexible electronics assemblies during bending

NARCIS (Netherlands)

Van Den Ende, D.A.; Van De Wiel, H.J.; Kusters, R.H.L.; Sridhar, A.; Schram, J.F.M.; Cauwe, M.; Van Den Brand, J.

2014-01-01

Ultra-thin chips of less than 20 μm become flexible, allowing integration of silicon IC technology with highly flexible electronics such as food packaging sensor systems or healthcare and sport monitoring tags as wearable patches or even directly in clothing textile. The ultra-thin chips in these

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

Energy Technology Data Exchange (ETDEWEB)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

2017-07-01

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

Micromachined On-Chip Dielectric Resonator Antenna Operating at 60 GHz

KAUST Repository

Sallam, Mai

2015-06-01

This paper presents a novel cylindrical Dielectric Resonator Antenna (DRA) suitable for millimeter-wave on-chip systems. The antenna was fabricated from a single high resistivity silicon wafer via micromachining technology. The new antenna was characterized using HFSS and experimentally with good agreement been found between the simulations and experiment. The proposed DRA has good radiation characteristics, where its gain and radiation efficiency are 7 dBi and 79.35%, respectively. These properties are reasonably constant over the working frequency bandwidth of the antenna. The return loss bandwidth was 2.23 GHz, which corresponds to 3.78% around 60 GHz. The antenna was primarily a broadside radiator with -15 dB cross polarization level.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

International Nuclear Information System (INIS)

Holland, S.E.

2000-01-01

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels

Detector and Front-end electronics for ALICE and STAR silicon strip layers

CERN Document Server

Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

1998-01-01

Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

The dark side of silicon energy efficient computing in the dark silicon era

CERN Document Server

Liljeberg, Pasi; Hemani, Ahmed; Jantsch, Axel; Tenhunen, Hannu

2017-01-01

This book presents the state-of-the art of one of the main concerns with microprocessors today, a phenomenon known as "dark silicon". Readers will learn how power constraints (both leakage and dynamic power) limit the extent to which large portions of a chip can be powered up at a given time, i.e. how much actual performance and functionality the microprocessor can provide. The authors describe their research toward the future of microprocessor development in the dark silicon era, covering a variety of important aspects of dark silicon-aware architectures including design, management, reliability, and test. Readers will benefit from specific recommendations for mitigating the dark silicon phenomenon, including energy-efficient, dedicated solutions and technologies to maximize the utilization and reliability of microprocessors. Enables readers to understand the dark silicon phenomenon and why it has emerged, including detailed analysis of its impacts; Presents state-of-the-art research, as well as tools for mi...

Electronic spectrum of a deterministic single-donor device in silicon

International Nuclear Information System (INIS)

Fuechsle, Martin; Miwa, Jill A.; Mahapatra, Suddhasatta; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.

2013-01-01

We report the fabrication of a single-electron transistor (SET) based on an individual phosphorus dopant that is deterministically positioned between the dopant-based electrodes of a transport device in silicon. Electronic characterization at mK-temperatures reveals a charging energy that is very similar to the value expected for isolated P donors in a bulk Si environment. Furthermore, we find indications for bulk-like one-electron excited states in the co-tunneling spectrum of the device, in sharp contrast to previous reports on transport through single dopants

All-solid-state supercapacitors on silicon using graphene from silicon carbide

Energy Technology Data Exchange (ETDEWEB)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca, E-mail: f.iacopi@griffith.edu.au [Environmental Futures Research Institute, Griffith University, Nathan 4111 (Australia); Wood, Barry [Centre for Microscopy and Microanalysis, The University of Queensland, St. Lucia 4072 (Australia)

2016-05-02

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm{sup −2} with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

All-solid-state supercapacitors on silicon using graphene from silicon carbide

International Nuclear Information System (INIS)

Wang, Bei; Ahmed, Mohsin; Iacopi, Francesca; Wood, Barry

2016-01-01

Carbon-based supercapacitors are lightweight devices with high energy storage performance, allowing for faster charge-discharge rates than batteries. Here, we present an example of all-solid-state supercapacitors on silicon for on-chip applications, paving the way towards energy supply systems embedded in miniaturized electronics with fast access and high safety of operation. We present a nickel-assisted graphitization method from epitaxial silicon carbide on a silicon substrate to demonstrate graphene as a binder-free electrode material for all-solid-state supercapacitors. We obtain graphene electrodes with a strongly enhanced surface area, assisted by the irregular intrusion of nickel into the carbide layer, delivering a typical double-layer capacitance behavior with a specific area capacitance of up to 174 μF cm"−"2 with about 88% capacitance retention over 10 000 cycles. The fabrication technique illustrated in this work provides a strategic approach to fabricate micro-scale energy storage devices compatible with silicon electronics and offering ultimate miniaturization capabilities.

Single-layer graphene on silicon nitride micromembrane resonators

DEFF Research Database (Denmark)

Schmid, Silvan; Bagci, Tolga; Zeuthen, Emil

2014-01-01

Due to their low mass, high quality factor, and good optical properties, silicon nitride (SiN) micromembrane resonators are widely used in force and mass sensing applications, particularly in optomechanics. The metallization of such membranes would enable an electronic integration with the prospect...... for exciting new devices, such as optoelectromechanical transducers. Here, we add a single-layer graphene on SiN micromembranes and compare electromechanical coupling and mechanical properties to bare dielectric membranes and to membranes metallized with an aluminium layer. The electrostatic coupling...

Development of a high-speed single-photon pixellated detector for visible wavelengths

CERN Document Server

Mac Raighne, Aaron; Mathot, Serge; McPhate, Jason; Vallerga, John; Jarron, Pierre; Brownlee, Colin; O’Shea, Val

2009-01-01

We present the development of a high-speed, single-photon counting, Hybrid Photo Detector (HPD). The HPD consists of a vacuum tube, containing the detector assembly, sealed with a transparent optical input window. Photons incident on the photocathode eject a photoelectron into a large electric field, which accelerates the incident electron onto a silicon detector. The silicon detector is bump bonded to a Medipix readout chip. This set-up allows for the detection and readout of low incident photon intensities at rates that are otherwise unattainable with current camera technology. Reported is the fabrication of the camera that brings together a range of sophisticated design and fabrication techniques and the expected theoretical imaging performance. Applications to cellular and molecular microscopy are also described in which single-photon-counting abilities at high frame rates are crucial

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

Science.gov (United States)

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Drug delivery via porous silicon: a focused patent review.

Science.gov (United States)

Kulyavtsev, Paulina A; Spencer, Roxanne P

2017-03-01

Although silicon is more commonly associated with computer chips than with drug delivery, with the discovery that porous silicon is a viable biocompatible material, mesoporous silicon with pores between 2 and 50 nm has been loaded with small molecule and biomolecule therapeutics and safely implanted for controlled release. As porous silicon is readily oxidized, porous silica must also be considered for drug delivery applications. Since 2010, only a limited number of US patents have been granted, primarily for ophthalmologic and immunotherapy applications, in contrast to the growing body of technical literature in this area.

Chip based single cell analysis for nanotoxicity assessment.

Science.gov (United States)

Shah, Pratikkumar; Kaushik, Ajeet; Zhu, Xuena; Zhang, Chengxiao; Li, Chen-Zhong

2014-05-07

Nanomaterials, because of their tunable properties and performances, have been utilized extensively in everyday life related consumable products and technology. On exposure, beyond the physiological range, nanomaterials cause health risks via affecting the function of organisms, genomic systems, and even the central nervous system. Thus, new analytical approaches for nanotoxicity assessment to verify the feasibility of nanomaterials for future use are in demand. The conventional analytical techniques, such as spectrophotometric assay-based techniques, usually require a lengthy and time-consuming process and often produce false positives, and often cannot be implemented at a single cell level measurement for studying cell behavior without interference from its surrounding environment. Hence, there is a demand for a precise, accurate, sensitive assessment for toxicity using single cells. Recently, due to the advantages of automation of fluids and minimization of human errors, the integration of a cell-on-a-chip (CoC) with a microfluidic system is in practice for nanotoxicity assessments. This review explains nanotoxicity and its assessment approaches with advantages/limitations and new approaches to overcome the confines of traditional techniques. Recent advances in nanotoxicity assessment using a CoC integrated with a microfluidic system are also discussed in this review, which may be of use for nanotoxicity assessment and diagnostics.

Reliable single chip genotyping with semi-parametric log-concave mixtures.

Directory of Open Access Journals (Sweden)

Ralph C A Rippe

Full Text Available The common approach to SNP genotyping is to use (model-based clustering per individual SNP, on a set of arrays. Genotyping all SNPs on a single array is much more attractive, in terms of flexibility, stability and applicability, when developing new chips. A new semi-parametric method, named SCALA, is proposed. It is based on a mixture model using semi-parametric log-concave densities. Instead of using the raw data, the mixture is fitted on a two-dimensional histogram, thereby making computation time almost independent of the number of SNPs. Furthermore, the algorithm is effective in low-MAF situations.Comparisons between SCALA and CRLMM on HapMap genotypes show very reliable calling of single arrays. Some heterozygous genotypes from HapMap are called homozygous by SCALA and to lesser extent by CRLMM too. Furthermore, HapMap's NoCalls (NN could be genotyped by SCALA, mostly with high probability. The software is available as R scripts from the website www.math.leidenuniv.nl/~rrippe.

Gain enhancement of low profile on-chip dipole antenna via Artificial Magnetic Conductor at 94 GHz

KAUST Repository

Nafe, Mahmoud; Syed, Ahad; Shamim, Atif

2015-01-01

The bottleneck for realizing high efficiency System-on-Chip is integrating the antenna on the lossy silicon substrate. To shield the antenna from the silicon, a ground plane can be used. However, the ultra-thin oxide does not provide enough

Surface morphology evolution in silicon during ion beam processing; TOPICAL

International Nuclear Information System (INIS)

Bedrossian P; Caturla, M; Diaz de la Rubia, T; Johnson, M

1999-01-01

The Semiconductor Industry Association (SIA) projects that the semiconductor chips used in personal computers and scientific workstations will reach five times the speed and ten times the memory capacity of the current pentium-class processor by the year 2007. However, 1 GHz on-chip clock speeds and 64 Gbits/Chip DRAM technology will not come easy and without a price. Such technologies will require scaling the minimum feature size of CMOS devices (the transistors in the silicon chip) down to below 100nm from the current 180 to 250 nm. This requirement has profound implications for device manufacturing. Existing processing techniques must increasingly be understood quantitatively and modeled with unprecedented precision. Indeed, revolutionary advances in the development of physics-based process simulation tools will be required to achieve the goals for cost efficient manufacturing, and to satisfy the needs of the defense industrial base. These advances will necessitate a fundamental improvement in our basic understanding of microstructure evolution during processing. In order to cut development time and costs, the semiconductor industry makes extensive use of simple models of dopant implantation, and of phenomenological models of defect annealing and diffusion. However, the production of a single device often requires more than 200 processing steps, and the cumulative effects of the various steps are far too complex to be treated with these models. The lack of accurate process modeling simulators is proving to be a serious impediment to the development of next generation devices. New atomic-level models are required to describe the point defect distributions produced by the implantation process, and the defect and dopant diffusion resulting from rapid thermal annealing steps. In this LDRD project, we investigated the migration kinetics of defects and dopants in silicon both experimentally and theoretically to provide a fundamental database for use in the development

ISPA (imaging silicon pixel array) experiment

CERN Multimedia

Patrice Loïez

2002-01-01

The bump-bonded silicon pixel detector, developed at CERN by the EP-MIC group, is shown here in its ceramic carrier. Both represent the ISPA-tube anode. The chip features between 1024 (called OMEGA-1) and 8196 (ALICE-1) active pixels.

TC9447F, single-chip DSP (digital signal processor) for audio; 1 chip audio yo DSP LSI TC9447F

Energy Technology Data Exchange (ETDEWEB)

NONE

1999-03-01

TC9447F is a single-chip DSP for audio which builds in 2-channel AD converter/4-channel DA converter. It can build various application programs such as the sound field control like hall simulation, digital filter like equalizer, and dynamic range control, in the program memory (ROM). Further, it builds in {+-}10dB trim use electronic volume for two channels. It also builds data delay use RAM (64K-bit) in, so no RAM to be separately attached is necessary. (translated by NEDO)

Tracking performance of a single-crystal and a polycrystalline diamond pixel-detector

Energy Technology Data Exchange (ETDEWEB)

Menasce, D.; et al.

2013-06-01

We present a comparative characterization of the performance of a single-crystal and a polycrystalline diamond pixel-detector employing the standard CMS pixel readout chips. Measurements were carried out at the Fermilab Test Beam Facility, FTBF, using protons of momentum 120 GeV/c tracked by a high-resolution pixel telescope. Particular attention was directed to the study of the charge-collection, the charge-sharing among adjacent pixels and the achievable position resolution. The performance of the single-crystal detector was excellent and comparable to the best available silicon pixel-detectors. The measured average detection-efficiency was near unity, ε = 0.99860±0.00006, and the position-resolution for shared hits was about 6 μm. On the other hand, the performance of the polycrystalline detector was hampered by its lower charge collection distance and the readout chip threshold. A new readout chip, capable of operating at much lower threshold (around 1 ke^$-$), would be required to fully exploit the potential performance of the polycrystalline diamond pixel-detector.

The H1 silicon vertex detector

International Nuclear Information System (INIS)

Pitzl, D.; Behnke, O.; Biddulph, M.; Boesiger, K.; Eichler, R.; Erdmann, W.; Gabathuler, K.; Gassner, J.; Haynes, W.J..; Horisberger, R.; Kausch, M.; Lindstroem, M.; Niggli, H.; Noyes, G.; Pollet, P.; Steiner, S.; Streuli, S.; Szeker, K.; Truoel, P.

2000-01-01

The design, construction and performance of the H1 silicon vertex detector is described. It consists of two cylindrical layers of double-sided, double-metal silicon sensors read out by a custom designed analog pipeline chip. The analog signals are transmitted by optical fibres to a custom-designed ADC board and are reduced on PowerPC processors. Details of the design and construction are given and performance figures from the first data-taking periods are presented

Nonlinear optical interactions in silicon waveguides

Directory of Open Access Journals (Sweden)

Kuyken B.

2017-03-01

Full Text Available The strong nonlinear response of silicon photonic nanowire waveguides allows for the integration of nonlinear optical functions on a chip. However, the detrimental nonlinear optical absorption in silicon at telecom wavelengths limits the efficiency of many such experiments. In this review, several approaches are proposed and demonstrated to overcome this fundamental issue. By using the proposed methods, we demonstrate amongst others supercontinuum generation, frequency comb generation, a parametric optical amplifier, and a parametric optical oscillator.

Micro benchtop optics by bulk silicon micromachining

Science.gov (United States)

Lee, Abraham P.; Pocha, Michael D.; McConaghy, Charles F.; Deri, Robert J.

2000-01-01

Micromachining of bulk silicon utilizing the parallel etching characteristics of bulk silicon and integrating the parallel etch planes of silicon with silicon wafer bonding and impurity doping, enables the fabrication of on-chip optics with in situ aligned etched grooves for optical fibers, micro-lenses, photodiodes, and laser diodes. Other optical components that can be microfabricated and integrated include semi-transparent beam splitters, micro-optical scanners, pinholes, optical gratings, micro-optical filters, etc. Micromachining of bulk silicon utilizing the parallel etching characteristics thereof can be utilized to develop miniaturization of bio-instrumentation such as wavelength monitoring by fluorescence spectrometers, and other miniaturized optical systems such as Fabry-Perot interferometry for filtering of wavelengths, tunable cavity lasers, micro-holography modules, and wavelength splitters for optical communication systems.

ALICE chip processor

CERN Multimedia

Maximilien Brice

2003-01-01

This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

Fabrication of a novel silicon single electron transistor for Si:P quantum computer devices

International Nuclear Information System (INIS)

Angus, S.J.; Smith, C.E.A.; Gauja, E.; Dzurak, A.S.; Clark, R.G.; Snider, G.L.

2004-01-01

Full text: Quantum computation relies on the successful measurement of quantum states. Single electron transistors (SETs) are known to be able to perform fast and sensitive charge measurements of solid state qubits. However, due to their sensitivity, SETs are also very susceptible to random charge fluctuations in a solid-state materials environment. In previous dc transport measurements, silicon-based SETs have demonstrated greater charge stability than A1/A1 2 O 3 SETs. We have designed and fabricated a novel silicon SET architecture for a comparison of the noise characteristics of silicon and aluminium based devices. The silicon SET described here is designed for controllable and reproducible low temperature operation. It is fabricated using a novel dual gate structure on a silicon-on-insulator substrate. A silicon quantum wire is formed in a 100nm thick high-resistivity superficial silicon layer using reactive ion etching. Carriers are induced in the silicon wire by a back gate in the silicon substrate. The tunnel barriers are created electrostatically, using lithographically defined metallic electrodes (∼40nm width). These tunnel barriers surround the surface of the quantum wire, thus producing excellent electrostatic confinement. This architecture provides independent control of tunnel barrier height and island occupancy, thus promising better control of Coulomb blockade oscillations than in previously investigated silicon SETs. The use of a near intrinsic silicon substrate offers compatibility with Si:P qubits in the longer term

CMOS-compatible photonic devices for single-photon generation

Directory of Open Access Journals (Sweden)

Xiong Chunle

2016-09-01

Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

Heterogeneous Silicon Photonics OFDR Sensing System, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Luna will team with Dr. John Bowers of UCSB to develop an Optical Frequency Domain Reflectometry (OFDR) system-on-chip using heterogeneous silicon photonics to...

How good is better? A comparison between the Medipix1 and the Medipix2 chip using mammographic phantoms

International Nuclear Information System (INIS)

Pfeiffer, K.F.G.

2003-01-01

Full text: The Mixed-up chip is the successor to the Medipix 1 chip and was also developed within the framework of the Medipix Colaboration. Both chips are pixel detector readout chips working in single photon counting mode and are designed for direct conversion X-ray imaging, for which they are bump-bonded to a pixelated semiconductor sensor layer. Both assemblies used in this comparison have a 300 μm thick sensor layer made of silicon. The main changes realized in the second chip generation are the smaller pixel size of 55 μm x 55 μm, the larger number of pixels (256 x 256) and a second adjustable energy threshold which facilitates energy windowing. For comparing the two detector generations, mammographic phantoms and a suitable X-ray tube have been used. By imaging selected parts of the phantoms with both detectors under the same conditions it is possible to make a direct comparison between the imaging properties of both chips. Main aspects of the experiments were the resolution of high-contrast details and low-contrast imaging. To provide a reference point for image quality the phantoms were also imaged using standard clinical equipment. Since these measurements have been made without an anti-scatter grid, additional simulations have been performed to estimate the influence of scattered photons on the image quality

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

Science.gov (United States)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

A Medipix2-based imaging system for digital mammography with silicon pixel detectors

CERN Document Server

Bisogni, M G; Fantacci, M E; Mettivier, G; Montesi, M C; Novelli, M; Quattrocchi, M; Rosso, V; Russo, P; Stefanini, A

2004-01-01

In this paper we present the first tests of a digital imaging system based on a silicon pixel detector bump-bonded to an integrated circuit operating in single photon counting mode. The X-rays sensor is a 300 mu m thick silicon, 14 by 14 mm/sup 2/, upon which a matrix of 256 * 256 pixels has been built. The read-out chip, named MEDIPIX2, has been developed at CERN within the MEDIPIX2 Collaboration and it is composed by a matrix of 256 * 256 cells, 55 * 55 mu m/sup 2/. The spatial resolution properties of the system have been assessed by measuring the square wave resolution function (SWRF) and first images of a standard mammographic phantom were acquired using a radiographic tube in the clinical irradiation condition. (5 refs).

Packaging of silicon sensors for microfluidic bio-analytical applications

International Nuclear Information System (INIS)

Wimberger-Friedl, Reinhold; Prins, Menno; Megens, Mischa; Dittmer, Wendy; Witz, Christiane de; Nellissen, Ton; Weekamp, Wim; Delft, Jan van; Ansems, Will; Iersel, Ben van

2009-01-01

A new industrial concept is presented for packaging biosensor chips in disposable microfluidic cartridges to enable medical diagnostic applications. The inorganic electronic substrates, such as silicon or glass, are integrated in a polymer package which provides the electrical and fluidic interconnections to the world and provides mechanical strength and protection for out-of-lab use. The demonstrated prototype consists of a molded interconnection device (MID), a silicon-based giant magneto-resistive (GMR) biosensor chip, a flex and a polymer fluidic part with integrated tubing. The various processes are compatible with mass manufacturing and run at a high yield. The devices show a reliable electrical interconnection between the sensor chip and readout electronics during extended wet operation. Sandwich immunoassays were carried out in the cartridges with surface functionalized sensor chips. Biological response curves were determined for different concentrations of parathyroid hormone (PTH) on the packaged biosensor, which demonstrates the functionality and biocompatibility of the devices. The new packaging concept provides a platform for easy further integration of electrical and fluidic functions, as for instance required for integrated molecular diagnostic devices in cost-effective mass manufacturing

Skiroc A Front-end Chip to Read Out the Imaging Silicon-Tungsten Calorimeter for ILC

CERN Document Server

Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard,Gisèle; Raux, Ludovic; Wicek, Francois; Bohner, Gérard; Gay, Pascal; Lecoq, Jacques; Manen, Samuel; Royer, Laurent

2007-01-01

Integration and low-power consumption of the read-out ASIC for the International Linear Collider (ILC) 82-millionchannel W-Si calorimeter must reach an unprecedented level as it will be embedded inside the detector. Uniformity and dynamic range performance has to reach the accuracy to achieve calorimetric measurement. A first step towards this goal has been a 10,000-channel physics prototype of 18*18 cm which is currently in test beam in CERN. A new version of a full integrated read out chip (SKIROC) has been designed to equip the technologic prototype to be built for 2009. Based on the running physics prototype ASIC (FLC_PHY3), it embeds most of the required features expected for the final detector. The dynamic range has been improved from 500 to 2000 MIP. An auto-trigger capability has been added allowing built-in zero suppress. The number of channel has been doubled reaching 36 to fit smaller silicon pads and the lownoise charge preamplifier now accepts both AC and DC coupled detectors. After an exhaustive...

Dopant induced single electron tunneling within the sub-bands of single silicon NW tri-gate junctionless n-MOSFET

Science.gov (United States)

Uddin, Wasi; Georgiev, Yordan M.; Maity, Sarmistha; Das, Samaresh

2017-09-01

We report 1D electron transport of silicon junctionless tri-gate n-type transistor at 4.2 K. The step like curve observed in the current voltage characteristic suggests 1D transport. Besides the current steps for 1D transport, we found multiple spikes within individual steps, which we relate to inter-band single electron tunneling, mediated by the charged dopants available in the channel region. Clear Coulomb diamonds were observed in the stability diagram of the device. It is shown that a uniformly doped silicon nanowire can provide us the window for the single electron tunnelling. Back-gate versus front-gate color plot, where current is in a color scale, shows a crossover of the increased conduction region. This is a clear indication of the dopant-dopant interaction. It has been shown that back-gate biasing can be used to tune the coupling strength between the dopants.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

Directory of Open Access Journals (Sweden)

Kenji Okabe

2015-12-01

Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

Science.gov (United States)

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

High Sensitivity and High Detection Specificity of Gold-Nanoparticle-Grafted Nanostructured Silicon Mass Spectrometry for Glucose Analysis.

Science.gov (United States)

Tsao, Chia-Wen; Yang, Zhi-Jie

2015-10-14

Desorption/ionization on silicon (DIOS) is a high-performance matrix-free mass spectrometry (MS) analysis method that involves using silicon nanostructures as a matrix for MS desorption/ionization. In this study, gold nanoparticles grafted onto a nanostructured silicon (AuNPs-nSi) surface were demonstrated as a DIOS-MS analysis approach with high sensitivity and high detection specificity for glucose detection. A glucose sample deposited on the AuNPs-nSi surface was directly catalyzed to negatively charged gluconic acid molecules on a single AuNPs-nSi chip for MS analysis. The AuNPs-nSi surface was fabricated using two electroless deposition steps and one electroless etching step. The effects of the electroless fabrication parameters on the glucose detection efficiency were evaluated. Practical application of AuNPs-nSi MS glucose analysis in urine samples was also demonstrated in this study.

Large On-Chip Amplification in Silicon via Forward Stimulated Brillouin Scattering

Energy Technology Data Exchange (ETDEWEB)

Kittlaus, Eric [Yale Univ., New Haven, CT (United States); Shin, Heedeuk [Yale Univ., New Haven, CT (United States); Rakich, Peter [Yale Univ., New Haven, CT (United States)

2015-10-15

Strong Brillouin coupling has only recently been realized in silicon using a new class of op- tomechanical waveguides that yield both optical and phononic con nement. Despite these major advances, appreciable Brillouin ampli cation has yet to be observed in silicon. Using new membrane- suspended silicon waveguide we report large Brillouin ampli cation for the rst time, reaching levels greater than 5 dB for modest pump powers, and demonstrate a record low (5 mW) threshold for net ampli cation. This work represents a crucial advance necessary to realize high-performance Brillouin lasers and ampli ers in silicon.

A comparison of gettering in single- and multicrystalline silicon for solar cells

Energy Technology Data Exchange (ETDEWEB)

Sopori, B.L. [National Renewable Energy Lab., Golden, CO (United States); Jastrzebski, L.; Tan, T.

1996-05-01

The differences in the impurity gettering between single and multicrystalline silicon are discussed. These differences arise from impurity-defect interactions that occur during thermal processing of multicrystalline material. A gettering model is proposed to explain the observed behaviour of gettering in multicrystalline cells.

InP on SOI devices for optical communication and optical network on chip

Science.gov (United States)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Temperature effect on phase states of quartz nano-crystals in silicon single crystal

International Nuclear Information System (INIS)

Kalanov, M.U.; Ibragimova, E.M.; Khamraeva, R.N.; Rustamova, V.M.; Ummatov, Kh.D.

2006-01-01

Full text: Oxygen penetrates into the silicon lattice up to the concentration of 2·10 18 cm -3 in the course of growing [1]. By the author's opinion at a low oxygen content the formation of solid solution is possible in the local defect places of the silicon single crystal lattice due to the difference in effective ion radius of oxygen and silicon (r O 0.176 and r Si = 0.065 nm). Upon reaching some critical content (∼ 10 17 cm -3 ), it becomes favorable energetically for oxygen ions to form precipitates (SiO x ) and finally a dielectric layer (stoichiometric inclusions of SiO 2 ). It was shown later that depending on the growth conditions, indeed the quartz crystal inclusions are formed in the silicon single crystals at an amount of 0.3 /0.5 wt. % [2]. However the authors did not study a phase state of the quartz inclusions. Therefore the aim of this work was to study a phase state of the quartz inclusions in silicon crystal at various temperatures. We examined the silicon single crystals grown by Czochralski technique, which were cut in (111) plane in the form of disk of 20 mm diameter and 1.5 thickness and had hole conductivity with the specific resistance ρ o ≅ 1/10 Ohm cm. The dislocation density was N D ≅ 10 1 /10 3 cm -2 , the concentrations of oxygen and boron were N 0 ≅ 2/ 4·10 17 cm -3 and N B ≅ 3*10 15 cm -3 . Structure was analyzed at the set-up DRON-UM1 with high temperature supply UVD-2000 ( CuK = 0.1542 nm) at the temperatures of 300, 1173 and 1573 K measured with platinum-platinum-rhodium thermocouple. The high temperature diffraction spectrum measured at 1573 K in the angle range (2Θ≅10/70 d egree ) there is only one main structure reflection (111) with a high intensity and d/n ≅ 0.3136 nm (2 Θ≅ 28.5 d egree ) from the matrix lattice of silicon single crystal. The weak line at 2 Θ≅ 25.5 d egree ( d/n≅0.3136 nm) is β component of the main reflection (111), and the weak structure peak at 2Θ≅59 d egree ( d/n≅ 0.1568 nm

Silicon Waveguide with Lateral p-i-n Diode for Nonlinearity Compensation by On-Chip Optical Phase Conjugation

DEFF Research Database (Denmark)

Gajda, A.; Da Ros, Francesco; Porto da Silva, Edson

2018-01-01

A 1-dB Q-factor improvement through optical phase conjugation in a silicon waveguide with a lateral p-i-n diode enables BERsingle-polarization signal...

Pattern manipulation via on-chip phase modulation between orbital angular momentum beams

International Nuclear Information System (INIS)

Li, Huanlu; Strain, Michael J.; Meriggi, Laura; Sorel, Marc; Chen, Lifeng; Zhu, Jiangbo; Cicek, Kenan; Wang, Jianwei; Thompson, Mark G.; Cai, Xinlun; Yu, Siyuan

2015-01-01

An integrated approach to thermal modulation of relative phase between two optical vortices with opposite chirality has been demonstrated on a silicon-on-insulator substrate. The device consists of a silicon-integrated optical vortex emitter and a phase controlled 3 dB coupler. The relative phase between two optical vortices can be actively modulated on chip by applying a voltage on the integrated heater. The phase shift is shown to be linearly proportional to applied electrical power, and the rotation angle of the interference pattern is observed to be inversely proportional to topological charge. This scheme can be used in lab-on-chip, communications and sensing applications. It can be intentionally implemented with other modulation elements to achieve more complicated applications

Pattern manipulation via on-chip phase modulation between orbital angular momentum beams

Energy Technology Data Exchange (ETDEWEB)

Li, Huanlu [Department of Electrical and Electronic Engineering, University of Bristol, University Walk, Bristol BS8 1TR (United Kingdom); School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP (United Kingdom); Strain, Michael J. [School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP (United Kingdom); Wolfson Centre, Institute of Photonics, University of Strathclyde, 106 Rottenrow East, Glasgow G4 0NW (United Kingdom); Meriggi, Laura; Sorel, Marc [School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP (United Kingdom); Chen, Lifeng; Zhu, Jiangbo; Cicek, Kenan [Department of Electrical and Electronic Engineering, University of Bristol, University Walk, Bristol BS8 1TR (United Kingdom); Wang, Jianwei; Thompson, Mark G. [Centre for Quantum Photonics, H. H. Wills Physics Laboratory and Department of Electrical and Electronic Engineering, University of Bristol, Bristol BS8 1UB (United Kingdom); Cai, Xinlun, E-mail: caixlun5@mail.sysu.edu.cn [Centre for Quantum Photonics, H. H. Wills Physics Laboratory and Department of Electrical and Electronic Engineering, University of Bristol, Bristol BS8 1UB (United Kingdom); State Key Laboratory of Optoelectronic Materials and Technologies and School of Physics and Engineering, Sun Yat-sen University, Guangzhou 510275 (China); Yu, Siyuan, E-mail: s.yu@bristol.ac.uk [Department of Electrical and Electronic Engineering, University of Bristol, University Walk, Bristol BS8 1TR (United Kingdom); State Key Laboratory of Optoelectronic Materials and Technologies and School of Physics and Engineering, Sun Yat-sen University, Guangzhou 510275 (China)

2015-08-03

An integrated approach to thermal modulation of relative phase between two optical vortices with opposite chirality has been demonstrated on a silicon-on-insulator substrate. The device consists of a silicon-integrated optical vortex emitter and a phase controlled 3 dB coupler. The relative phase between two optical vortices can be actively modulated on chip by applying a voltage on the integrated heater. The phase shift is shown to be linearly proportional to applied electrical power, and the rotation angle of the interference pattern is observed to be inversely proportional to topological charge. This scheme can be used in lab-on-chip, communications and sensing applications. It can be intentionally implemented with other modulation elements to achieve more complicated applications.

Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

CERN Document Server

Kluit, R; Gromov, V

2007-01-01

The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector de...

Neutron-induced Single Event Upset on the RPC front-end chips for the CMS experiment

Energy Technology Data Exchange (ETDEWEB)

Abbrescia, M.; Colaleo, A.; Iaselli, G.; Loddo, F.; Maggi, M.; Marangelli, B.; Natali, S.; Nuzzo, S.; Pugliese, G.; Ranieri, A.; Romano, F.; Altieri, S.; Belli, G.; Bruno, G.; Guida, R.; Merlo, M.; Ratti, S.P.; Riccardi, C.; Torre, P.; Vitulo, P. E-mail: paolo.vitulo@pv.infn.it; De Bari, A.; Manera, S

2002-05-21

Neutrons from a reactor and from a cyclotron have been used to characterise the CMS Resistive Plate Chambers (RPCs) front-end chip to neutron-induced damaging events. Single Event Upset (SEU) cross-sections have been measured up to 60 MeV for different chip thresholds. Tests at a reactor were done with an integrated fast (E{sub n}>3 MeV) neutron fluence of 1.7x10{sup 10} cm{sup -2} and a thermal neutron fluence of 9.5x10{sup 11} cm{sup -2}. High-energy neutrons from a cyclotron were used up to a fluence of 10{sup 12} cm{sup -2}. Data indicate the existence of a chip SEU sensitivity already at thermal energy and a saturated SEU cross-section from 3 to 60 MeV. Values of the SEU cross-sections from the thermal run well agree with those obtained by another CMS group that uses the same technology (0.8 {mu}m BiCMOS) though with different architecture. Cross-sections obtained with fast neutrons (from 3 MeV to about 10 MeV) are consistently higher by one order of magnitude compared to the thermal one. The average time between consecutive SEU events in each chip of the CMS barrel RPCs can be estimated to be 1 h.

Chip bonding of low-melting eutectic alloys by transmitted laser radiation

Science.gov (United States)

Hoff, Christian; Venkatesh, Arjun; Schneider, Friedrich; Hermsdorf, Jörg; Bengsch, Sebastian; Wurz, Marc C.; Kaierle, Stefan; Overmeyer, Ludger

2017-06-01

Present-day thermode bond systems for the assembly of radio-frequency identification (RFID) chips are mechanically inflexible, difficult to control, and will not meet future manufacturing challenges sufficiently. Chip bonding, one of the key processes in the production of integrated circuits (ICs), has a high potential for optimization with respect to process duration and process flexibility. For this purpose, the technologies used, so far, are supposed to be replaced by a transmission laser-bonding process using low-melting eutectic alloys. In this study, successful bonding investigations of mock silicon chips and of RFID chips on flexible polymer substrates are presented using the low-melting eutectic alloy, 52In48Sn, and a laser with a wavelength of 2 μm.

Neuromorphic Silicon Neuron Circuits

Science.gov (United States)

Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

2011-01-01

Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

Neuromorphic silicon neuron circuits

Directory of Open Access Journals (Sweden)

Giacomo eIndiveri

2011-05-01

Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

Nanostructured silicon for photonics from materials to devices

CERN Document Server

Gaburro, Z; Daldosso, N

2006-01-01

The use of light to channel signals around electronic chips could solve several current problems in microelectronic evolution including: power dissipation, interconnect bottlenecks, input/output from/to optical communication channels, poor signal bandwidth, etc. It is unfortunate that silicon is not a good photonic material: it has a poor light-emission efficiency and exhibits a negligible electro-optical effect. Silicon photonics is a field having the objective of improving the physical properties of silicon; thus turning it into a photonic material and permitting the full convergence of elec

Characterization of the adhesion of thin film by Cross-Sectional Nanoindentation. Analysis of the substrate edge chipping and the film delamination

Science.gov (United States)

Felder, Eric; Roy, Sébastien; Darque-Ceretti, Evelyne

2011-07-01

Cross-Sectional Nanoindentation (CSN) is a recent method for adhesion measurement of nanoscale thin films in Ultra-Large Scale Integrated circuits. In the case of ductile thin films, the motion of the substrate chip implies significant plastic deformation of the film and complex geometry of delaminated areas. This article recalls first the experimental procedure and the two main features observed in this test performed on various plane copper films deposited on silicon: the critical force producing silicon edge chipping increases linearly with the distance of the indenter to the interface; on the section the delaminated length of the film ( a-b) is proportional to the residual silicon chip displacement u and the ratio S=u/(a-b) depends on the manufacturing process of the film, and is so related to its adhesion to the substrate. One proposes a simple analysis of the silicon edge chipping. Then a model of pull-off of an elastic-strain hardening plastic film is developed, which suggests an explanation for the delamination process. Application of the model to experimental results starting from films plastic properties deduced from nanoindentation measurements provides plausible results. Some improvements for performing the CSN test are proposed in order to make easier its interpretation.

Analog integrated circuit for micro-gyro interface realized by multi-chip service in Japan; Multi chip service ni yoru micro gyro interface shuseki kairo no sekkei to shisaku

Energy Technology Data Exchange (ETDEWEB)

Maenaka, K.; Fujita, T.; Okamoto, K.; Maeda, M. [Himeji Institute of Technology, Hyogo (Japan)

1998-10-01

This paper deals with an analog integrated circuit for micro-machined gyroscopes with capacitive output. The Integrated circuit was fabricated as a part of the first project from the `Micromachining Multi-Chip Service Cooperative Re-search Committee` organized by The Institute of Electrical Engineers Japan. This multi-chip service project offers a master slice chip with an equivalent of 9 blocks of operational amplifier circuits. Our integrated circuit includes a modulator, demodulator and synchronous rectifier for detecting small changes in the capacitance of a silicon gyroscope. In the paper, the experimental results of fabricated samples will be described. 13 refs., 15 figs.

Optic nerve signals in a neuromorphic chip II: Testing and results.

Science.gov (United States)

Zaghloul, Kareem A; Boahen, Kwabena

2004-04-01

Seeking to match the brain's computational efficiency, we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 microm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip's subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip's circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

The ALICE silicon pixel detector front-end and read-out electronics

CERN Document Server

Kluge, A

2006-01-01

The ALICE silicon pixel detector (SPD) comprises the two innermost barrel layers of the ALICE inner tracker system. The SPD includes 120 half staves each of which consists of a linear array of 10 ALICE pixel chips bump bonded to two silicon sensors. Each pixel chip contains 8192 active cells, so the total number of pixel cells in the SPD is ≈107. The tight material budget and the limitation in physical dimensions required by the detector design introduce new challenges for the integration of the on-detector electronics. An essential part of the half stave is a low-mass multi-layer flex that carries power, ground, and signals to the pixel chips. Each half stave is read out using a multi-chip module (MCM). The MCM contains three radiation hard ASICs and an 800 Mbit/s custom developed optical link for the data transfer between the detector and the control room. The detector components are less than 3 mm thick. The production of the half-staves and MCMs is currently under way. Test results as well as on overvie...

Narrow-linewidth lasers on a silicon chip

NARCIS (Netherlands)

Bernhardi, Edward; Pollnau, Markus; Di Bartolo, Baldassare; Collins, John; Silvestri, Luciano

2015-01-01

Diode-pumped distributed-feedback (DFB) channel waveguide lasers were demonstrated in Er3+-doped and Yb3+-doped Al2O3 on standard thermally ox-idized silicon substrates. Uniform surface-relief Bragg gratings were patterned by laser-interference lithography and etched into the SiO2 top cladding. The

On-Chip Method to Measure Mechanical Characteristics of a Single Cell by Using Moiré Fringe

Directory of Open Access Journals (Sweden)

Hirotaka Sugiura

2015-06-01

Full Text Available We propose a method to characterize the mechanical properties of cells using a robot-integrated microfluidic chip (robochip and microscopy. The microfluidic chip is designed to apply the specified deformations to a single detached cell using an on-chip actuator probe. The reaction force is simultaneously measured using an on-chip force sensor composed of a hollow folded beam and probe structure. In order to measure the cellular characteristics in further detail, a sub-pixel level of resolution of probe position is required. Therefore, we utilize the phase detection of moiré fringe. Using this method, the experimental resolution of the probe position reaches 42 nm. This is approximately ten times smaller than the optical wavelength, which is the limit of sharp imaging with a microscope. Calibration of the force sensor is also important in accurately measuring cellular reaction forces. We calibrated the spring constant from the frequency response, by the proposed sensing method of the probe position. As a representative of mechanical characteristics, we measured the elastic modulus of Madin-Darby Cannie Kidney (MDCK cells. In spite of the rigid spring constant, the resolution and sensitivity were twice that achieved in our previous study. Unique cellular characteristics can be elucidated by the improvements in sensing resolution and accuracy.

Ultrafast all-optical arithmetic logic based on hydrogenated amorphous silicon microring resonators

Science.gov (United States)

Gostimirovic, Dusan; Ye, Winnie N.

2016-03-01

For decades, the semiconductor industry has been steadily shrinking transistor sizes to fit more performance into a single silicon-based integrated chip. This technology has become the driving force for advances in education, transportation, and health, among others. However, transistor sizes are quickly approaching their physical limits (channel lengths are now only a few silicon atoms in length), and Moore's law will likely soon be brought to a stand-still despite many unique attempts to keep it going (FinFETs, high-k dielectrics, etc.). This technology must then be pushed further by exploring (almost) entirely new methodologies. Given the explosive growth of optical-based long-haul telecommunications, we look to apply the use of high-speed optics as a substitute to the digital model; where slow, lossy, and noisy metal interconnections act as a major bottleneck to performance. We combine the (nonlinear) optical Kerr effect with a single add-drop microring resonator to perform the fundamental AND-XOR logical operations of a half adder, by all-optical means. This process is also applied to subtraction, higher-order addition, and the realization of an all-optical arithmetic logic unit (ALU). The rings use hydrogenated amorphous silicon as a material with superior nonlinear properties to crystalline silicon, while still maintaining CMOS-compatibility and the many benefits that come with it (low cost, ease of fabrication, etc.). Our method allows for multi-gigabit-per-second data rates while maintaining simplicity and spatial minimalism in design for high-capacity manufacturing potential.

A thin film approach for SiC-derived graphene as an on-chip electrode for supercapacitors

Science.gov (United States)

Ahmed, Mohsin; Khawaja, Mohamad; Notarianni, Marco; Wang, Bei; Goding, Dayle; Gupta, Bharati; Boeckl, John J.; Takshi, Arash; Motta, Nunzio; Saddow, Stephen E.; Iacopi, Francesca

2015-10-01

We designed a nickel-assisted process to obtain graphene with sheet resistance as low as 80 Ω square-1 from silicon carbide films on Si wafers with highly enhanced surface area. The silicon carbide film acts as both a template and source of graphitic carbon, while, simultaneously, the nickel induces porosity on the surface of the film by forming silicides during the annealing process which are subsequently removed. As stand-alone electrodes in supercapacitors, these transfer-free graphene-on-chip samples show a typical double-layer supercapacitive behaviour with gravimetric capacitance of up to 65 F g-1. This work is the first attempt to produce graphene with high surface area from silicon carbide thin films for energy storage at the wafer-level and may open numerous opportunities for on-chip integrated energy storage applications.

"Hook"-calibration of GeneChip-microarrays: Chip characteristics and expression measures

Directory of Open Access Journals (Sweden)

Krohn Knut

2008-08-01

Full Text Available Abstract Background Microarray experiments rely on several critical steps that may introduce biases and uncertainty in downstream analyses. These steps include mRNA sample extraction, amplification and labelling, hybridization, and scanning causing chip-specific systematic variations on the raw intensity level. Also the chosen array-type and the up-to-dateness of the genomic information probed on the chip affect the quality of the expression measures. In the accompanying publication we presented theory and algorithm of the so-called hook method which aims at correcting expression data for systematic biases using a series of new chip characteristics. Results In this publication we summarize the essential chip characteristics provided by this method, analyze special benchmark experiments to estimate transcript related expression measures and illustrate the potency of the method to detect and to quantify the quality of a particular hybridization. It is shown that our single-chip approach provides expression measures responding linearly on changes of the transcript concentration over three orders of magnitude. In addition, the method calculates a detection call judging the relation between the signal and the detection limit of the particular measurement. The performance of the method in the context of different chip generations and probe set assignments is illustrated. The hook method characterizes the RNA-quality in terms of the 3'/5'-amplification bias and the sample-specific calling rate. We show that the proper judgement of these effects requires the disentanglement of non-specific and specific hybridization which, otherwise, can lead to misinterpretations of expression changes. The consequences of modifying probe/target interactions by either changing the labelling protocol or by substituting RNA by DNA targets are demonstrated. Conclusion The single-chip based hook-method provides accurate expression estimates and chip-summary characteristics

WDM-Coherent OCDMA over one single device based on short chip Super Structured Fiber Bragg Gratings.

Science.gov (United States)

Amaya, Waldimar; Pastor, Daniel; Baños, Rocio; Garcia-Munoz, Victor

2011-11-21

We theoretically propose and demonstrate experimentally a Coherent Direct Sequence OCDMA en/decoder for multi-channel WDM operation based on a single device. It presents a broadband spectral envelope and a periodic spectral pattern that can be employed for en/decoding multiple sub-bands simultaneously. Multi-channel operation is verified experimentally by means of Multi-Band Super Structured Fiber Bragg Gratings with binary phase encoded chips fabricated with 1mm inter-chip separation that provides 4x100 GHz ITU sub-band separation at 1.25 Gbps. The WDM-OCDMA system verification was carried out employing simultaneous encoding of four adjacent sub-bands and two different OCDMA codes. © 2011 Optical Society of America

Experimental realization of an on-chip all-optical analogue to electromagnetically induced transparency.

Science.gov (United States)

Xu, Qianfan; Sandhu, Sunil; Povinelli, Michelle L; Shakya, Jagat; Fan, Shanhui; Lipson, Michal

2006-03-31

We provide the first experimental observation of structure tuning of the electromagnetically induced transparency-like spectrum in integrated on-chip optical resonator systems. The system consists of coupled silicon ring resonators with 10 microm diameter on silicon, where the coherent interference between the two coupled resonators is tuned. We measured a transparency-resonance mode with a quality factor of 11,800.

Estimate the thermomechanical fatigue life of two flip chip packages

International Nuclear Information System (INIS)

Pash, R.A.; Ullah, H.S.; Khan, M.Z.

2005-01-01

The continuing demand towards high density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology, ball grid array (BOA) and chip scale package (CSP). In such structures the most widely used flip chip interconnects are solder joints. The reliability of flip chip structures largely depends on the reliability of solder joints. In this work solder joint fatigue life prediction for two chip scale packages is carried out. Elasto-plastic deformation behavior of the solder was simulated using ANSYS. Two dimensional plain strain finite element models were developed for each package to numerically compute the stress and total strain of the solder joints under temperature cycling. These stress and strain values are then used to predict the solder joint lifetime through modified Coffin Manson equation. The effect of solder joint's distance from edge of silicon die on life of the package is explored. The solder joint fatigue response is modeled for a typical temperature cycling of -60 to 140 degree C. (author)

Strain-Induced Spin-Resonance Shifts in Silicon Devices

Science.gov (United States)

Pla, J. J.; Bienfait, A.; Pica, G.; Mansir, J.; Mohiyaddin, F. A.; Zeng, Z.; Niquet, Y. M.; Morello, A.; Schenkel, T.; Morton, J. J. L.; Bertet, P.

2018-04-01

In spin-based quantum-information-processing devices, the presence of control and detection circuitry can change the local environment of a spin by introducing strain and electric fields, altering its resonant frequencies. These resonance shifts can be large compared to intrinsic spin linewidths, and it is therefore important to study, understand, and model such effects in order to better predict device performance. We investigate a sample of bismuth donor spins implanted in a silicon chip, on top of which a superconducting aluminum microresonator is fabricated. The on-chip resonator provides two functions: it produces local strain in the silicon due to the larger thermal contraction of the aluminum, and it enables sensitive electron spin-resonance spectroscopy of donors close to the surface that experience this strain. Through finite-element strain simulations, we are able to reconstruct key features of our experiments, including the electron spin-resonance spectra. Our results are consistent with a recently observed mechanism for producing shifts of the hyperfine interaction for donors in silicon, which is linear with the hydrostatic component of an applied strain.

Enhancing the brightness of electrically driven single-photon sources using color centers in silicon carbide

Science.gov (United States)

Khramtsov, Igor A.; Vyshnevyy, Andrey A.; Fedyanin, Dmitry Yu.

2018-03-01

Practical applications of quantum information technologies exploiting the quantum nature of light require efficient and bright true single-photon sources which operate under ambient conditions. Currently, point defects in the crystal lattice of diamond known as color centers have taken the lead in the race for the most promising quantum system for practical non-classical light sources. This work is focused on a different quantum optoelectronic material, namely a color center in silicon carbide, and reveals the physics behind the process of single-photon emission from color centers in SiC under electrical pumping. We show that color centers in silicon carbide can be far superior to any other quantum light emitter under electrical control at room temperature. Using a comprehensive theoretical approach and rigorous numerical simulations, we demonstrate that at room temperature, the photon emission rate from a p-i-n silicon carbide single-photon emitting diode can exceed 5 Gcounts/s, which is higher than what can be achieved with electrically driven color centers in diamond or epitaxial quantum dots. These findings lay the foundation for the development of practical photonic quantum devices which can be produced in a well-developed CMOS compatible process flow.

On-chip highly sensitive saliva glucose sensing using multilayer films composed of single-walled carbon nanotubes, gold nanoparticles, and glucose oxidase

Directory of Open Access Journals (Sweden)

Wenjun Zhang

2015-06-01

Full Text Available It is very important for human health to rapidly and accurately detect glucose levels in biological environments, especially for diabetes mellitus. We proposed a simple, highly sensitive, accurate, convenient, low-cost, and disposable glucose biosensor on a single chip. A working (sensor electrode, a counter electrode, and a reference electrode are integrated on a single chip through micro-fabrication. The working electrode is functionalized through a layer-by-layer (LBL assembly of single-walled carbon nanotubes (SWNTs and multilayer films composed of chitosan (CS, gold nanoparticles (GNp, and glucose oxidase (GOx to obtain high sensitivity and accuracy. The glucose sensor has following features: (1 direct electron transfer between GOx and the electrode surface; (2 on-a-chip; (3 glucose detection down to 0.1 mg/dL (5.6 μM; (4 good sensing linearity over 0.017–0.81 mM; (5 high sensitivity (61.4 μA/mM-cm2 with a small reactive area (8 mm2; (6 fast response; (7 high reproducibility and repeatability; (8 reliable and accurate saliva glucose detection. Thus, this disposable biosensor will be an alternative for real time tracking of glucose levels from body fluids, e.g. saliva, in a noninvasive, pain-free, accurate, and continuous way. In addition to being used as a disposable glucose biosensor, it also provides a suitable platform for on-chip electrochemical sensing for other chemical agents and biomolecules.

Surface enhanced raman spectroscopy on chip

DEFF Research Database (Denmark)

Hübner, Jörg; Anhøj, Thomas Aarøe; Zauner, Dan

2007-01-01

In this paper we report low resolution surface enhanced Raman spectra (SERS) conducted with a chip based spectrometer. The flat field spectrometer presented here is fabricated in SU-8 on silicon, showing a resolution of around 3 nm and a free spectral range of around 100 nm. The output facet...... is projected onto a CCD element and visualized by a computer. To enhance the otherwise rather weak Raman signal, a nanosurface is prepared and a sample solutions is impregnated on this surface. The surface enhanced Raman signal is picked up using a Raman probe and coupled into the spectrometer via an optical...... fiber. The obtained spectra show that chip based spectrometer together with the SERS active surface can be used as Raman sensor....

A readout system for position sensitive measurements of X-ray using silicon strip detectors

CERN Document Server

Dabrowski, W; Grybos, P; Idzik, M; Kudlaty, J

2000-01-01

In this paper we describe the development of a readout system for X-ray measurements using silicon strip detectors. The limitation concerning the inherent spatial resolution of silicon strip detectors has been evaluated by Monte Carlo simulation and the results are discussed. The developed readout system is based on the binary readout architecture and consists of two ASICs: RX32 front-end chip comprising 32 channels of preamplifiers, shapers and discriminators, and COUNT32 counter chip comprising 32 20-bit asynchronous counters and the readout logic. This work focuses on the design and performance of the front-end chip. The RX32 chip has been optimised for a low detector capacitance, in the range of 1-3 pF, and high counting rate applications. It can be used with DC coupled detectors allowing the leakage current up to a few nA per strip. For the prototype chip manufactured in a CMOS process all basic parameters have been evaluated by electronic measurements. The noise below 140 el rms has been achieved for a ...

Interfering Heralded Single Photons from Two Separate Silicon Nanowires Pumped at Different Wavelengths

Directory of Open Access Journals (Sweden)

Xiang Zhang

2016-08-01

Full Text Available Practical quantum photonic applications require on-demand single photon sources. As one possible solution, active temporal and wavelength multiplexing has been proposed to build an on-demand single photon source. In this scheme, heralded single photons are generated from different pump wavelengths in many temporal modes. However, the indistinguishability of these heralded single photons has not yet been experimentally confirmed. In this work, we achieve 88% ± 8% Hong–Ou–Mandel quantum interference visibility from heralded single photons generated from two separate silicon nanowires pumped at different wavelengths. This demonstrates that active temporal and wavelength multiplexing could generate indistinguishable heralded single photons.

A dual-unit pressure sensor for on-chip self-compensation of zero-point temperature drift

International Nuclear Information System (INIS)

Wang, Jiachou; Li, Xinxin

2014-01-01

A novel dual-unit piezoresistive pressure sensor, consisting of a sensing unit and a dummy unit, is proposed and developed for on-chip self-compensation for zero-point temperature drift. With an MIS (microholes inter-etch and sealing) process implemented only from the front side of single (1 1 1) silicon wafers, a pressure sensitive unit and another identically structured pressure insensitive dummy unit are compactly integrated on-chip to eliminate unbalance factors induced zero-point temperature-drift by mutual compensation between the two units. Besides, both units are physically suspended from silicon substrate to further suppress packaging-stress induced temperature drift. A simultaneously processes ventilation hole-channel structure is connected with the pressure reference cavity of the dummy unit to make it insensitive to detected pressure. In spite of the additional dummy unit, the sensor chip dimensions are still as small as 1.2 mm × 1.2 mm × 0.4 mm. The proposed dual-unit sensor is fabricated and tested, with the tested sensitivity being 0.104 mV kPa −1 3.3 V −1 , nonlinearity of less than 0.08% · FSO and overall accuracy error of ± 0.18% · FSO. Without using any extra compensation method, the sensor features an ultra-low temperature coefficient of offset (TCO) of 0.002% °C −1 · FSO that is much better than the performance of conventional pressure sensors. The highly stable and small-sized sensors are promising for low cost production and applications. (paper)

Single-chip ring resonator-based 1 x 8 optical beam forming network in CMOS-compatible waveguide technology

NARCIS (Netherlands)

Zhuang, L.; Roeloffzen, C.G.H.; Heideman, Rene; Borreman, A.; Meijerink, Arjan; van Etten, Wim

2007-01-01

Optical ring resonators (ORRs) are good candidates to provide continuously tunable delay in optical beam forming networks (OBFNs) for phased array antenna systems. Delay and splitting/combining elements can be integrated on a single optical chip to form an OBFN. A state-of-the-art ring resonator-

Friction and metal transfer for single-crystal silicon carbide in contact with various metals in vacuum

International Nuclear Information System (INIS)

Miyoshi, K.; Buckley, D.H.

1978-04-01

Sliding friction experiments were conducted with single-crystal silicon carbide in contact with transition metals (tungsten, iron, rhodium, nickel, titanium, and cobalt), copper, and aluminum. Results indicate the coefficient of friction for a silicon carbide-metal system is related to the d bond character and relative chemical activity of the metal. The more active the metal, the higher the coefficient of friction. All the metals examined transferred to the surface of silicon carbide in sliding. The chemical activity of metal to silicon and carbon and shear modulus of the metal may play important roles in metal transfer and the form of the wear debris. The less active metal is, and the greater resistance to shear it has, with the exception of rhodium and tungsten, the less transfer to silicon carbide

The Design, Fabrication and Characterization of a Transparent Atom Chip

Directory of Open Access Journals (Sweden)

Ho-Chiao Chuang

2014-06-01

Full Text Available This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments.

The Design, Fabrication and Characterization of a Transparent Atom Chip

Science.gov (United States)

Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

2014-01-01

This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

Silicon on-chip bandpass filters for the multiplexing of high sensitivity photonic crystal microcavity biosensors

International Nuclear Information System (INIS)

Yan, Hai; Zou, Yi; Yang, Chun-Ju; Chakravarty, Swapnajit; Wang, Zheng; Tang, Naimei; Chen, Ray T.; Fan, Donglei

2015-01-01

A method for the dense integration of high sensitivity photonic crystal (PC) waveguide based biosensors is proposed and experimentally demonstrated on a silicon platform. By connecting an additional PC waveguide filter to a PC microcavity sensor in series, a transmission passband is created, containing the resonances of the PC microcavity for sensing purpose. With proper engineering of the passband, multiple high sensitivity PC microcavity sensors can be integrated into microarrays and be interrogated simultaneously between a single input and a single output port. The concept was demonstrated with a 2-channel L55 PC biosensor array containing PC waveguide filters. The experiment showed that the sensors on both channels can be monitored simultaneously from a single output spectrum. Less than 3 dB extra loss for the additional PC waveguide filter is observed

Silicon on-chip bandpass filters for the multiplexing of high sensitivity photonic crystal microcavity biosensors

Energy Technology Data Exchange (ETDEWEB)

Yan, Hai, E-mail: hai.yan@utexas.edu; Zou, Yi; Yang, Chun-Ju [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, 10100 Burnet Rd., Austin, Texas 78758 (United States); Chakravarty, Swapnajit, E-mail: swapnajit.chakravarty@omegaoptics.com [Omega Optics, Inc., 8500 Shoal Creek Blvd., Austin, Texas 78757 (United States); Wang, Zheng [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, 10100 Burnet Rd., Austin, Texas 78758 (United States); Materials Science and Engineering Program, Texas Materials Institute, The University of Texas at Austin, Austin, Texas 78712 (United States); Tang, Naimei; Chen, Ray T., E-mail: raychen@uts.cc.utexas.edu [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, 10100 Burnet Rd., Austin, Texas 78758 (United States); Omega Optics, Inc., 8500 Shoal Creek Blvd., Austin, Texas 78757 (United States); Fan, Donglei [Materials Science and Engineering Program, Texas Materials Institute, The University of Texas at Austin, Austin, Texas 78712 (United States); Department of Mechanical Engineering, The University of Texas at Austin, Austin, Texas 78712 (United States)

2015-03-23

A method for the dense integration of high sensitivity photonic crystal (PC) waveguide based biosensors is proposed and experimentally demonstrated on a silicon platform. By connecting an additional PC waveguide filter to a PC microcavity sensor in series, a transmission passband is created, containing the resonances of the PC microcavity for sensing purpose. With proper engineering of the passband, multiple high sensitivity PC microcavity sensors can be integrated into microarrays and be interrogated simultaneously between a single input and a single output port. The concept was demonstrated with a 2-channel L55 PC biosensor array containing PC waveguide filters. The experiment showed that the sensors on both channels can be monitored simultaneously from a single output spectrum. Less than 3 dB extra loss for the additional PC waveguide filter is observed.

Preparation and characterization of tempered tungsten layers on single crystalline silicon

International Nuclear Information System (INIS)

Nitzsche, K.; Knedlik, C.; Tippmann, H.; Spiess, L.; Harman, R.; Vanek, O.; Tvarozek, V.

1984-01-01

Tungsten layers have been deposited on single crystalline silicon by sputtering and characterized by measurements of the sheet resistance by a linear four point method and the van der Pauw method. The influence of tempering under argon on the resistance has been studied. By means of the RBS spectroscopy it was found that the increase in the specific resistance is caused by interdiffusion

Anisotropy effect of crater formation on single crystal silicon surface under intense pulsed ion beam irradiation

Science.gov (United States)

Shen, Jie; Yu, Xiao; Zhang, Jie; Zhong, Haowen; Cui, Xiaojun; Liang, Guoying; Yu, Xiang; Huang, Wanying; Shahid, Ijaz; Zhang, Xiaofu; Yan, Sha; Le, Xiaoyun

2018-04-01

Due to the induced extremely fast thermal and dynamic process, Intense Pulsed Ion Beam (IPIB) is widely applied in material processing, which can bring enhanced material performance and surface craters as well. To investigate the craters' formation mechanism, a specific model was built with Finite Element Methods (FEM) to simulate the thermal field on irradiated single crystal silicon. The direct evidence for the existence of the simulated 6-fold rotational symmetric thermal distribution was provided by electron microscope images obtained on single crystal silicon. The correlation of the experiment and simulation is of great importance to understand the interaction between IPIB and materials.

1980, a revolution in silicon detectors, from energy spectrometer to radiation imager: Some technical and historical details

International Nuclear Information System (INIS)

Heijne, Erik H.M.

2008-01-01

Silicon nuclear particle detectors were introduced just 50 years ago, after single crystal manufacturing was mastered. A major change took place around 1980 when the 'planar' Metal Oxide Semiconductor (MOS) technology developed in microelectronics was systematically applied also in detector construction. With the simultaneous introduction of matched readout chips this eventually would lead to pixelized matrix detectors that function as radiation imaging devices. The critical contributions to this revolution by Josef Kemmer and Paul Burger are described. Performance of the segmented planar technology detectors improved significantly in comparison with the earlier spectrometric diodes. With efficient industrial support the use of silicon detectors in many new applications has become possible and detector systems with a sensitive area of several tens to >100m 2 have been constructed recently

Hydrogen interactions with silicon-on-insulator materials

OpenAIRE

Rivera de Mena, A.J.

2003-01-01

The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

Creating and Controlling Single Spins in Silicon Carbide

Science.gov (United States)

Christle, David

Silicon carbide (SiC) is a well-established commercial semiconductor used in high-power electronics, optoelectronics, and nanomechanical devices, and has recently shown promise for semiconductor-based implementations of quantum information technologies. In particular, a set of divacancy-related point defects have improved coherence properties relative to the prominent nitrogen-vacancy center in diamond, are addressable at near-telecom wavelengths, and reside in a material for which there already exist advanced growth, doping, and microfabrication capabilities. These properties suggest divacancies in SiC have compelling advantages for photonics and micromechanical applications, yet their relatively recent discovery means crucial aspects of their fundamental physics for these applications are not well understood. I will review our progress on manipulating spin defects in SiC, and discuss efforts towards isolating and controlling them at the single defect limit. In particular, our most recent experimental results demonstrate isolation and control of long-lived (T2 = 0 . 9 ms) divacancies in a form of SiC that can be grown epitaxially on silicon. By studying the time-resolved photoluminescence of a single divacancy, we reveal its fundamental orbital structure and characterize in detail the dynamics of its special optical cycle. Finally, we probe individual divacancies using resonant laser techniques and reveal an efficient spin-photon interface with figures of merit comparable to those reported for NV centers in diamond. These results suggest a pathway towards photon-mediated entanglement of SiC defect spins over long distances. This work was supported by NSF, AFOSR, the Argonne CNM, the Knut & Alice Wallenberg Foundation, the Linköping Linnaeus Initiative, the Swedish Government Strategic Research Area, and the Ministry of Education, Science, Sports and Culture of Japan.

Functionalization of silicon-doped single walled carbon nanotubes at the doping site: An ab initio study

International Nuclear Information System (INIS)

Song Chen; Xia Yueyuan; Zhao Mingwen; Liu Xiangdong; Li Feng; Huang Boda; Zhang Hongyu; Zhang Bingyun

2006-01-01

We performed ab initio calculations on the cytosine-functionalized silicon-doped single walled carbon nanotubes (SWNT). The results show that silicon substitutional doping to SWNT can dramatically change the atomic and electronic structures of the SWNT. And more importantly, it may provide an efficient pathway for further sidewall functionalization to synthesize more complicated SWNT based complex materials, for example, our previously proposed base-functionalized SWNTs, because the doping silicon atom can improve the reaction activity of the tube at the doping site due to its preference to form sp3 hybridization bonding

Lab-on-a-chip systems with integrated optics for biochemical applications

DEFF Research Database (Denmark)

Mogensen, Klaus Bo; Gustafsson, O; Nunes, Pedro

2008-01-01

Two different applications that take advantage of integrated planar waveguides will be shown. The first example is a silicon chips for capillary electrochromatography (CEC), where the fluidic part contains electrically insulated channels with an injection cross and a chromatography column...

Palladium modified porous silicon as multi-functional MALDI chip for serum peptide detection.

Science.gov (United States)

Li, Xiao; Chen, Xiaoming; Tan, Jie; Liang, Xiao; Wu, Jianmin

2017-02-14

Interest in using mesoporous materials for peptidomic research has increased recently. The present study reports a new type of matrix assisted laser desorption/ionization (MALDI) plate derived from electrochemically etched porous silicon (PSi) whose surface was modified with palladium nanoparticles (PdNPs). Owing to the well-tailored pore size and the molecular filtration effect of the PSi, peptides in serum samples can be selectively captured and enriched in the pore channel, thereby eliminating the interference from large proteins in subsequent MALDI-MS detection. On the other hand, the PdNPs with localized surface plasmon resonance (LSPR) effect can help to enhance the efficiency of energy absorption in the UV region. Meanwhile, the charge separation effect between the PSi semiconductor and PdNPs also can be applied to promote the accumulation of positive charges on PdNPs, resulting in an improvement in laser desorption/ionization (LDI) efficiency under positive linear detection mode. The interplay among these unique properties of PSi and PdNPs can synergistically increase the overall sensitivity in serum peptide detection. Using this technology, serum sample can be directly detected on the PSi-PdNPs chip without complicated pretreatment process. Therefore, a high fidelity serum peptide fingerprint can be acquired in a high throughput way. With the assistance of statistical analysis, colorectal cancer patients and healthy people can be accurately distinguished based on the serum peptide fingerprints.

A thin film approach for SiC-derived graphene as an on-chip electrode for supercapacitors

International Nuclear Information System (INIS)

Ahmed, Mohsin; Wang, Bei; Goding, Dayle; Iacopi, Francesca; Khawaja, Mohamad; Notarianni, Marco; Takshi, Arash; Saddow, Stephen E; Gupta, Bharati; Motta, Nunzio; Boeckl, John J

2015-01-01

We designed a nickel-assisted process to obtain graphene with sheet resistance as low as 80 Ω square −1 from silicon carbide films on Si wafers with highly enhanced surface area. The silicon carbide film acts as both a template and source of graphitic carbon, while, simultaneously, the nickel induces porosity on the surface of the film by forming silicides during the annealing process which are subsequently removed. As stand-alone electrodes in supercapacitors, these transfer-free graphene-on-chip samples show a typical double-layer supercapacitive behaviour with gravimetric capacitance of up to 65 F g −1 . This work is the first attempt to produce graphene with high surface area from silicon carbide thin films for energy storage at the wafer-level and may open numerous opportunities for on-chip integrated energy storage applications. (paper)

All-in-polymer injection molded device for single cell capture using multilevel silicon master fabrication

DEFF Research Database (Denmark)

Tanzi, S.; Larsen, S.T.; Matteucci, M.

2012-01-01

This work demonstrates a novel all-in-polymer device for single cell capture applicable for biological recordings. The chip is injection molded and comprises a "cornered" (non planar) aperture. It has been demonstrated how cornered apertures are straightforward to mold in PDMS [1,2]. In this stud...

Vertically integrated pixel readout chip for high energy physics

International Nuclear Information System (INIS)

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Khalid, Farah; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

2011-01-01

We report on the development of the vertex detector pixel readout chips based on multi-tier vertically integrated electronics for the International Linear Collider. Some testing results of the VIP2a prototype are presented. The chip is the second iteration of the silicon implementation of the prototype, data-pushed concept of the readout developed at Fermilab. The device was fabricated in the 3D MIT-LL 0.15 (micro)m fully depleted SOI process. The prototype is a three-tier design, featuring 30 x 30 (micro)m 2 pixels, laid out in an array of 48 x 48 pixels.

Radiation effects on the Viking-2 preamplifier-readout chip

International Nuclear Information System (INIS)

Fallot-Burghardt, W.; Hawblitzel, C.; Hofmann, W.; Knoepfle, K.T.; Seeger, M.; Brenner, R.; Nygaard, E.; Rudge, A.; Toker, O.; Weilhammer, P.; Yoshioka, K.

1994-01-01

We have studied the radiation sensitivity of the Viking-2 VLSI circuit which has been designed for the readout of silicon strip detectors and manufactured at Mietec in 1.5 μm CMOS technology. Both biased and unbiased chips have been irradiated with a 137 Cs γ source up to a total dose of 2 kGy (200 krad) after which all tested chips were still fully functional. We report the characteristic changes of device parameters with dose, including equivalent noise charge for different capacitive loads, and determine transistor threshold shifts and change of mobilities. ((orig.))

High-directionality fiber-chip grating coupler with interleaved trenches and subwavelength index-matching structure.

Science.gov (United States)

Benedikovic, Daniel; Alonso-Ramos, Carlos; Cheben, Pavel; Schmid, Jens H; Wang, Shurui; Xu, Dan-Xia; Lapointe, Jean; Janz, Siegfried; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, J Gonzalo; Molina-Fernández, Iñigo; Fédéli, Jean-Marc; Vivien, Laurent; Dado, Milan

2015-09-15

We present the first experimental demonstration of a new fiber-chip grating coupler concept that exploits the blazing effect by interleaving the standard full (220 nm) and shallow etch (70 nm) trenches in a 220 nm thick silicon layer. The high directionality is obtained by controlling the separation between the deep and shallow trenches to achieve constructive interference in the upward direction and destructive interference toward the silicon substrate. Utilizing this concept, the grating directionality can be maximized independent of the bottom oxide thickness. The coupler also includes a subwavelength-engineered index-matching region, designed to reduce the reflectivity at the interface between the injection waveguide and the grating. We report a measured fiber-chip coupling efficiency of -1.3  dB, the highest coupling efficiency achieved to date for a surface grating coupler in a 220 nm silicon-on-insulator platform fabricated in a conventional dual-etch process without high-index overlays or bottom mirrors.

Stretchable and foldable silicon-based electronics

KAUST Repository

Cavazos Sepulveda, Adrian Cesar

2017-03-30

Flexible and stretchable semiconducting substrates provide the foundation for novel electronic applications. Usually, ultra-thin, flexible but often fragile substrates are used in such applications. Here, we describe flexible, stretchable, and foldable 500-μm-thick bulk mono-crystalline silicon (100) “islands” that are interconnected via extremely compliant 30-μm-thick connectors made of silicon. The thick mono-crystalline segments create a stand-alone silicon array that is capable of bending to a radius of 130 μm. The bending radius of the array does not depend on the overall substrate thickness because the ultra-flexible silicon connectors are patterned. We use fracture propagation to release the islands. Because they allow for three-dimensional monolithic stacking of integrated circuits or other electronics without any through-silicon vias, our mono-crystalline islands can be used as a “more-than-Moore” strategy and to develop wearable electronics that are sufficiently robust to be compatible with flip-chip bonding.

Stretchable and foldable silicon-based electronics

KAUST Repository

Cavazos Sepulveda, Adrian Cesar; Diaz Cordero, M. S.; Carreno, Armando Arpys Arevalo; Nassar, Joanna M.; Hussain, Muhammad Mustafa

2017-01-01

Flexible and stretchable semiconducting substrates provide the foundation for novel electronic applications. Usually, ultra-thin, flexible but often fragile substrates are used in such applications. Here, we describe flexible, stretchable, and foldable 500-μm-thick bulk mono-crystalline silicon (100) “islands” that are interconnected via extremely compliant 30-μm-thick connectors made of silicon. The thick mono-crystalline segments create a stand-alone silicon array that is capable of bending to a radius of 130 μm. The bending radius of the array does not depend on the overall substrate thickness because the ultra-flexible silicon connectors are patterned. We use fracture propagation to release the islands. Because they allow for three-dimensional monolithic stacking of integrated circuits or other electronics without any through-silicon vias, our mono-crystalline islands can be used as a “more-than-Moore” strategy and to develop wearable electronics that are sufficiently robust to be compatible with flip-chip bonding.

A single-walled carbon nanotube thin film-based pH-sensing microfluidic chip.

Science.gov (United States)

Li, Cheng Ai; Han, Kwi Nam; Pham, Xuan-Hung; Seong, Gi Hun

2014-04-21

A novel microfluidic pH-sensing chip was developed based on pH-sensitive single-walled carbon nanotubes (SWCNTs). In this study, the SWCNT thin film acted both as an electrode and a pH-sensitive membrane. The potentiometric pH response was observed by electronic structure changes in the semiconducting SWCNTs in response to the pH level. In a microfluidic chip consisting of a SWCNT pH-sensing working electrode and an Ag/AgCl reference electrode, the calibration plot exhibited promising pH-sensing performance with an ideal Nernstian response of 59.71 mV pH(-1) between pH 3 and 11 (standard deviation of the sensitivity is 1.5 mV pH(-1), R(2) = 0.985). Moreover, the SWCNT electrode in the microfluidic device showed no significant variation at any pH value in the range of the flow rate between 0.1 and 15 μl min(-1). The selectivity coefficients of the SWCNT electrode revealed good selectivity against common interfering ions.

An Electrochromatography Chip with Integrated Waveguides for UV Absorbance Detection

DEFF Research Database (Denmark)

Gustafsson, Omar; Mogensen, Klaus Bo; Ohlsson, Pelle Daniel

2008-01-01

A silicon-based microchip for electrochromatographic separations is presented. Apart from a microfluidic network, the microchip has integrated UV-transparent waveguides for detection and integrated couplers for optical fibers on the chip, yielding the most complete chromatography microchip to date...... to the waveguides. The entire oxidized silicon microchip structure is sealed with a glass lid. Reversed phase electrochromatographic separation of three neutral compounds is demonstrated using UV absorbance detection at 254 nm. Baseline separation of the analytes is achieved in less than two minutes....

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Directory of Open Access Journals (Sweden)

Amlan Ganguly

2018-02-01

Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

Study of the ALICE Investigator chip in view of the requirements at CLIC

CERN Document Server

AUTHOR|(SzGeCERN)754303; Dannheim, Dominik; Fiergolski, Adrian; Van Hoorne, Jacobus Willem; Hynds, Daniel; Klempt, Wolfgang; Nurnberg, Andreas Matthias; Sielewicz, Krzysztof Marek; Snoeys, Walter

2017-01-01

CLIC is an option for a future high energy linear $e^{+}e^{−}$ collider at CERN in the post-LHC era. The CLIC machine is designed to reach centre-of-mass energies ranging from a few hundred GeV up to 3 TeV. To achieve high precision measurements, e.g. of the Higgs- width, challenging requirements are imposed on the CLIC detector. A single point tracking resolution of 7 μm and a material budget of 1-2%$X_{0}$ per layer are required for the tracker. Moreover, to suppress background hits from beam-beam interactions, a precise time slicing of hits of 10 ns is needed. To address these requirements, a large area silicon tracker is foreseen for the detector at CLIC. In this context, integrated technologies are promising candidates to achieve large scale production and low material budget. The Investigator chip is a test chip developed for the ALICE Inner Tracking System upgrade, implemented in a 180 nm CMOS process on a high resistivity substrate. It contains various test-matrices with analogue functionality, whi...

Transverse wave propagation in [ab0] direction of silicon single crystal

Energy Technology Data Exchange (ETDEWEB)

Yun, Sang Jin; Kim, Hye Jeong; Kwon, Se Ho; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan(Korea, Republic of)

2015-12-15

The speed and oscillation directions of elastic waves propagating in the [ab0] direction of a silicon single crystal were obtained by solving Christoffel's equation. It was found that the quasi waves propagate in the off-principal axis, and hence, the directions of the phase and group velocities are not the same. The maximum deviation of the two directions was 7.2 degree angle. Two modes of the pure transverse waves propagate in the [110] direction with different speeds, and hence, two peaks were observed in the pulse echo signal. The amplitude ratio of the two peaks was dependent on the initial oscillating direction of the incident wave. The pure and quasi-transverse waves propagate in the [210] direction, and the oscillation directions of these waves are perpendicular to each other. The skewing angle of the quasi wave was calculated as 7.14 degree angle, and it was measured as 9.76 degree angle. The amplitude decomposition in the [210] direction was similar to that in the [110] direction, since the oscillation directions of these waves are perpendicular to each other. These results offer useful information in measuring the crystal orientation of the silicon single crystal.

Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

KAUST Repository

Hussain, Aftab M.

2016-01-01

, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We report a process for fabricating through

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

Science.gov (United States)

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Diamond and silicon pixel detectors in high radiation environments

Energy Technology Data Exchange (ETDEWEB)

Tsung, Jieh-Wen

2012-10-15

Diamond pixel detector is a promising candidate for tracking of collider experiments because of the good radiation tolerance of diamond. The diamond pixel detector must withstand the radiation damage from 10{sup 16} particles per cm{sup 2}, which is the expected total fluence in High Luminosity Large Hadron Collider. The performance of diamond and silicon pixel detectors are evaluated in this research in terms of the signal-to-noise ratio (SNR). Single-crystal diamond pixel detectors with the most recent readout chip ATLAS FE-I4 are produced and characterized. Based on the results of the measurement, the SNR of diamond pixel detector is evaluated as a function of radiation fluence, and compared to that of planar-silicon ones. The deterioration of signal due to radiation damage is formulated using the mean free path of charge carriers in the sensor. The noise from the pixel readout circuit is simulated and calculated with leakage current and input capacitance to the amplifier as important parameters. The measured SNR shows good agreement with the calculated and simulated results, proving that the performance of diamond pixel detectors can exceed the silicon ones if the particle fluence is more than 10{sup 15} particles per cm{sup 2}.

Diamond and silicon pixel detectors in high radiation environments

International Nuclear Information System (INIS)

Tsung, Jieh-Wen

2012-10-01

Diamond pixel detector is a promising candidate for tracking of collider experiments because of the good radiation tolerance of diamond. The diamond pixel detector must withstand the radiation damage from 10 16 particles per cm 2 , which is the expected total fluence in High Luminosity Large Hadron Collider. The performance of diamond and silicon pixel detectors are evaluated in this research in terms of the signal-to-noise ratio (SNR). Single-crystal diamond pixel detectors with the most recent readout chip ATLAS FE-I4 are produced and characterized. Based on the results of the measurement, the SNR of diamond pixel detector is evaluated as a function of radiation fluence, and compared to that of planar-silicon ones. The deterioration of signal due to radiation damage is formulated using the mean free path of charge carriers in the sensor. The noise from the pixel readout circuit is simulated and calculated with leakage current and input capacitance to the amplifier as important parameters. The measured SNR shows good agreement with the calculated and simulated results, proving that the performance of diamond pixel detectors can exceed the silicon ones if the particle fluence is more than 10 15 particles per cm 2 .

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

Science.gov (United States)

Kim, Jong Cheol; Kim, Jongsik; Xin, Yan; Lee, Jinhyung; Kim, Young-Gyun; Subhash, Ghatu; Singh, Rajiv K.; Arjunan, Arul C.; Lee, Haigun

2018-05-01

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (˜3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

On-chip particle trapping and manipulation

Science.gov (United States)

Leake, Kaelyn Danielle

The ability to control and manipulate the world around us is human nature. Humans and our ancestors have used tools for millions of years. Only in recent years have we been able to control objects at such small levels. In order to understand the world around us it is frequently necessary to interact with the biological world. Optical trapping and manipulation offer a non-invasive way to move, sort and interact with particles and cells to see how they react to the world around them. Optical tweezers are ideal in their abilities but they require large, non-portable, and expensive setups limiting how and where we can use them. A cheap portable platform is required in order to have optical manipulation reach its full potential. On-chip technology offers a great solution to this challenge. We focused on the Liquid-Core Anti-Resonant Reflecting Optical Waveguide (liquid-core ARROW) for our work. The ARROW is an ideal platform, which has anti-resonant layers which allow light to be guided in liquids, allowing for particles to easily be manipulated. It is manufactured using standard silicon manufacturing techniques making it easy to produce. The planner design makes it easy to integrate with other technologies. Initially I worked to improve the ARROW chip by reducing the intersection losses and by reducing the fluorescence and background on the ARROW chip. The ARROW chip has already been used to trap and push particles along its channel but here I introduce several new methods of particle trapping and manipulation on the ARROW chip. Traditional two beam traps use two counter propagating beams. A trapping scheme that uses two orthogonal beams which counter to first instinct allow for trapping at their intersection is introduced. This scheme is thoroughly predicted and analyzed using realistic conditions. Simulations of this method were done using a program which looks at both the fluidics and optical sources to model complex situations. These simulations were also used to

Analyses of test beam data for the ATLAS upgrade readout chip (ABC130)

Energy Technology Data Exchange (ETDEWEB)

Peschke, Richard [DESY, Hamburg (Germany); Collaboration: ATLAS-Collaboration

2015-07-01

As part of the ATLAS phase II upgrade it is planned to replace the current tracker with an all silicon tracker. The outer part of the new tracker will consist of silicon strip detectors. For the readout of the strip detector a new Analog to Binary Converter chip (ABC130) was designed. The chip is processed in the 130 nm technology. In laboratory measurements the preamplifier of the new ABC130 showed a significant lower gain than expected. From the measurements in the laboratory it was not possible to distinguish if the malfunction is in the preamplifier or in the test circuit. Therefore an unbiased test was mandatory. Among other measurements, one was a test beam campaign at the Stanford Linear Accelerator Collider (SLAC). The result of measurement is shown in the presentation.

Annihilation of unthermalized positrons in a silicon single crystal at 770K

International Nuclear Information System (INIS)

Zaitsev, Yu.E.; Mungir, L.; Ue'pe, L.R.

1984-01-01

A model is considered for the annihilation of nonrelativistic positrons from quantized states in lattice channels. Annihilation gamma rays of energy over 511 keV have been observed when the positrons from an Na 22 source strike a silicon single crystal at 77 0 K. The experimental results agree well with the proposed model

Preliminary characterization of a single photon counting detection system for CT application

International Nuclear Information System (INIS)

Belcari, N.; Bisogni, M.G.; Carpentieri, C.; Del Guerra, A.; Delogu, P.; Panetta, D.; Quattrocchi, M.; Rosso, V.; Stefanini, A.

2007-01-01

The aim of this work is to evaluate the capability of a single photon counting acquisition system based on the Medipix2 read-out chip for Computed Tomography (CT) applications in Small Animal Imaging. We used a micro-focus X-ray source with a W anode. The detection system is based on the Medipix2 read-out chip, bump-bonded to a 1 mm thick silicon pixel detector. The read-out chip geometry is a matrix of 256x256 cells, 55 μmx55 μm each. This system in planar radiography shows a good detection efficiency (about 70%) at the anode voltage of 30 kV and a good spatial resolution (MTF=10% at 16.8 lp/mm). Starting from these planar performances we have characterized the system for the tomography applications with phantoms. We will present the results obtained as a function of magnification with two different background medium compositions. The effect of the reconstruction algorithm on image quality will be also discussed

Surface texture of single-crystal silicon oxidized under a thin V{sub 2}O{sub 5} layer

Energy Technology Data Exchange (ETDEWEB)

Nikitin, S. E., E-mail: nikitin@mail.ioffe.ru; Verbitskiy, V. N.; Nashchekin, A. V.; Trapeznikova, I. N.; Bobyl, A. V.; Terukova, E. E. [Russian Academy of Sciences, Ioffe Physical–Technical Institute (Russian Federation)

2017-01-15

The process of surface texturing of single-crystal silicon oxidized under a V{sub 2}O{sub 5} layer is studied. Intense silicon oxidation at the Si–V{sub 2}O{sub 5} interface begins at a temperature of 903 K which is 200 K below than upon silicon thermal oxidation in an oxygen atmosphere. A silicon dioxide layer 30–50 nm thick with SiO{sub 2} inclusions in silicon depth up to 400 nm is formed at the V{sub 2}O{sub 5}–Si interface. The diffusion coefficient of atomic oxygen through the silicon-dioxide layer at 903 K is determined (D ≥ 2 × 10{sup –15} cm{sup 2} s{sup –1}). A model of low-temperature silicon oxidation, based on atomic oxygen diffusion from V{sub 2}O{sub 5} through the SiO{sub 2} layer to silicon, and SiO{sub x} precipitate formation in silicon is proposed. After removing the V{sub 2}O{sub 5} and silicon-dioxide layers, texture is formed on the silicon surface, which intensely scatters light in the wavelength range of 300–550 nm and is important in the texturing of the front and rear surfaces of solar cells.

On-chip manipulation of single microparticles, cells, and organisms using surface acoustic waves.

Science.gov (United States)

Ding, Xiaoyun; Lin, Sz-Chin Steven; Kiraly, Brian; Yue, Hongjun; Li, Sixing; Chiang, I-Kao; Shi, Jinjie; Benkovic, Stephen J; Huang, Tony Jun

2012-07-10

Techniques that can dexterously manipulate single particles, cells, and organisms are invaluable for many applications in biology, chemistry, engineering, and physics. Here, we demonstrate standing surface acoustic wave based "acoustic tweezers" that can trap and manipulate single microparticles, cells, and entire organisms (i.e., Caenorhabditis elegans) in a single-layer microfluidic chip. Our acoustic tweezers utilize the wide resonance band of chirped interdigital transducers to achieve real-time control of a standing surface acoustic wave field, which enables flexible manipulation of most known microparticles. The power density required by our acoustic device is significantly lower than its optical counterparts (10,000,000 times less than optical tweezers and 100 times less than optoelectronic tweezers), which renders the technique more biocompatible and amenable to miniaturization. Cell-viability tests were conducted to verify the tweezers' compatibility with biological objects. With its advantages in biocompatibility, miniaturization, and versatility, the acoustic tweezers presented here will become a powerful tool for many disciplines of science and engineering.

Piezoresistance of Silicon and Strained Si0.9Ge0.1

DEFF Research Database (Denmark)

Richter, Jacob; Hansen, Ole; Larsen, A. Nylandsted

2005-01-01

We present experimentally obtained results of the piezoresistive effect in p-type silicon and strained Si0.9Ge0.1. Today, strained Si1-xGex is used for high speed electronic devices. This paper investigates if this area of use can be expanded to also cover piezoresistive micro electro mechanical...... systems (MEMS) devices. The measurements are performed on microfabricated test chips where resistors are defined in layers grown by molecular beam epitaxy on (0 0 1) silicon substrates. A uniaxial stress along the [1 1 0] direction is applied to the chip, with the use of a four point bending fixture....... The investigation covers materials with doping levels of N-A = 10(18) cm(-3) and NA = 1019 cm(-3), respectively. The results show that the pi(66) piezoresistive coefficient in strained Si0.9Ge0.1 is approximately 30% larger than the comparable pi(44) piezoresistive coefficient in silicon at a doping level of N...

CO2 laser-induced directional recrystallization to produce single crystal silicon-core optical fibers with low loss

OpenAIRE

Healy, Noel; Fokine, Michael; Franz, Yohann; Hawkins, Thomas; Jones, Maxwell; Ballato, John; Peacock, Anna C.; Gibson, Ursula J.

2016-01-01

Reduced losses in silicon-core fibers are obtained using CO2 laser directional recrystallization of the core. Single crystals with aspect ratios up to 1500:1 are reported, limited by the scan range of the equipment. This processing technique holds promise for bringing crystalline silicon-core fibers to a central role in nonlinear optics and signal processing applications.

Detecting a single molecule using a micropore-nanopore hybrid chip.

Science.gov (United States)

Liu, Lei; Zhu, Lizhong; Ni, Zhonghua; Chen, Yunfei

2013-11-21

Nanopore-based DNA sequencing and biomolecule sensing have attracted more and more attention. In this work, novel sensing devices were built on the basis of the chips containing nanopore arrays in polycarbonate (PC) membranes and micropores in Si3N4 films. Using the integrated chips, the transmembrane ionic current induced by biomolecule's translocation was recorded and analyzed, which suggested that the detected current did not change linearly as commonly expected with increasing biomolecule concentration. On the other hand, detailed translocation information (such as translocation gesture) was also extracted from the discrete current blockages in basic current curves. These results indicated that the nanofluidic device based on the chips integrated by micropores and nanopores possessed comparative potentials in biomolecule sensing.

Progress on TSV technology for Medipix3RX chip

Science.gov (United States)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Fritzsch, T.; Zoschke, K.; Graafsma, H.

2017-12-01

The progress of Through Silicon Via (TSV) technology for Medipix3RX chip done at DESY is presented here. The goal of this development is to replace the wire bonds in X-ray detectors with TSVs, in order to reduce the dead area between detectors. We obtained the first working chips assembled together with Si based sensors for X-ray detection. The 3D integration technology, including TSV, Re-distribution layer deposition, bump bonding to the Si sensor and bump bonding to the carrier PCB, was done by Fraunhofer Institute IZM in Berlin. After assembly, the module was successfully tested by recording background radiation and making X-ray images of small objects. The active area of the Medipix3RX chip is 14.1 mm×14.1 mm or 256×256 pixels. During TSV processing, the Medipix3RX chip was thinned from 775 μm original thickness, to 130 μm. The diameter of the vias is 40 μm, and the pitch between the vias is 120 μm. A liner filling approach was used to contact the TSV with the RDL on the backside of the Medipix3RX readout chip.

Excited-state lifetime measurement of silicon vacancy centers in diamond by single-photon frequency upconversion

Science.gov (United States)

Rong, Youying; Ma, Jianhui; Chen, Lingxiao; Liu, Yan; Siyushev, Petr; Wu, Botao; Pan, Haifeng; Jelezko, Fedor; Wu, E.; Zeng, Heping

2018-05-01

We report a method with high time resolution to measure the excited-state lifetime of silicon vacancy centers in bulk diamond avoiding timing jitter from the single-photon detectors. Frequency upconversion of the fluorescence emitted from silicon vacancy centers was achieved from 738 nm to 436 nm via sum frequency generation with a short pump pulse. The excited-state lifetime can be obtained by measuring the intensity of upconverted light while the pump delay changes. As a probe, a pump laser with pulse duration of 11 ps provided a high temporal resolution of the measurement. The lifetime extracted from the pump–probe curve was 0.755 ns, which was comparable to the timing jitter of the single-photon detectors.

Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias

Science.gov (United States)

Araga, Yuuki; Kikuchi, Katsuya; Aoyagi, Masahiro

2018-04-01

Substrate noise from a single through-silicon via (TSV) and the noise attenuation by a substrate tap and a guard ring are clarified. A CMOS test vehicle is designed, and 6-µm-diameter TSVs are manufactured on a 20-µm-thick silicon substrate by the via-last method. An on-chip waveform-capturing circuitry is embedded in the test vehicle to capture transient waveforms of substrate noise. The embedded waveform-capturing circuitry demonstrates small and local noise propagation. Experimental results show increased substrate noise level induced by TSVs and the effectiveness of the substrate tap and guard ring for mitigating the crosstalk among TSVs. An analytical model to explain substrate noise propagation is developed to validate experimental results. Results obtained using the substrate model with a multilayer mesh shows good consistency with experimental results, indicating that the model can be used for examination of noise suppression methods.

Non-fossil reduction materials in the silicon process - properties and behaviour

Energy Technology Data Exchange (ETDEWEB)

Myrhaug, Edin Henrik

2003-07-01

thermogravimetric experiments on single spheres have been successfully applied in packed bed models to describe the reaction between carbon and SiO-gas in both the SINTEF SiO-reactivity test and the outer zone of a hypothetical silicon furnace. The following main observations were done from the simulations: (1) Smaller particles are converted faster than larger ones of same material. (2) Charcoal particles are converted faster than coke particles of same radius. The simulations with the packed bed model gave results that indicated some differences between the reduction materials that appear logical. A silicon smelting experiment with two charge mixtures with different compositions of charcoal, wood chips and coke (50% and 100% biocarbon, respectively) were carried out in the 150 kW single-phase submerged-arc furnace at SINTEF/NTNU in Trondheim. This experiment did not reveal any significant difference between these charge mixtures. However, there were some technical problems during smelting experiments that make the conclusions about this somewhat uncertain. After the silicon smelting experiment a new method of fixating the inner structure of the furnace with epoxy compound with subsequent making a cross section plate wire saw instead of traditional excavation was applied out without any particular problems. and gave very interesting results. Samples made by core drill from different areas of the cross section plate were analysed in the microprobe. Together with evaluation of the plate itself this gave a good view of the inner structure of the furnace and was a valuable aid to evaluate different reaction mechanism in different zones of the furnace. Compared with previous excavations, an overview of the inner structure of the process was easier and faster established. The results from this work indicates that it is possible to increase the use of biocarbon (charcoal and wood chips) for silicon metal production in submerged arc furnaces without losing performance or making the

A new intelligent curtain control system based on 51 single chip microcomputer

Science.gov (United States)

Sun, Tuan; Wang, Yanhua; Wu, Mengmeng

2017-04-01

This paper uses 51 (single chip microcomputer) SCM as the operation and data processing center. According to the change of sunshine intensity and ambient temperature, a new type of intelligent curtain control system is designed by adopting photosensitive element and temperature sensor. In addition, the design also has a manual control mode. In the rain, when the light intensity is weak, the open position of the curtain can be set by the user. The system can maximize the user to provide user-friendly operation and comfortable living environment. The system can be applied to home or office environment, with a wide range of applications and simple operation and so on.

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

Science.gov (United States)

Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

2018-02-01

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

VCSELs and silicon light sources exploiting SOI grating mirrors

DEFF Research Database (Denmark)

Chung, Il-Sug; Mørk, Jesper

2012-01-01

In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI...... the Bragg reflector. Numerical simulations show that both the silicon light source and the VCSEL exploiting SOI grating mirrors have superior performances, compared to existing silicon light sources and long wavelength VCSELs. These devices are highly adequate for chip-level optical interconnects as well...

PLA and single component silicone rubber blends for sub-zero temperature blown film packaging applications

Science.gov (United States)

Meekum, Utai; Khiansanoi, Apichart

2018-06-01

The poly(lactic acid) (PLA) blend with single component silicone rubber in the presence of reactive amino silane coupling agent and polyester polyols plasticizer were studied. The manufacturing of film packaging for sub-zero temperature applications from the PLA blend was the main objective. The mechanical properties, especially the impact strengths, of PLA/silicone blends were significantly depended on the silicone loading. The outstanding impact strengths, tested at sub-zero temperature, of the blend having silicone content of 8.0 phr was achieved. It was chosen as the best candidate for the processability improvement. Adding the talc filler into the PLA/silicone blend to enhance the rheological properties was investigated. The ductility of the talc filled blends were decreased with increasing the filler contents. However, the shear viscosity of the blend was raised with talc loading. The blend loaded with 40 phr of talc filler was justified as the optimal formula for the blown film process testing and it was successfully performed with a few difficulties. The obtained blown film showed relative good flexibility in comparison with LDPE but it has low transparency.

Memory effect in silicon time-gated single-photon avalanche diodes

International Nuclear Information System (INIS)

Dalla Mora, A.; Contini, D.; Di Sieno, L.; Tosi, A.; Boso, G.; Villa, F.; Pifferi, A.

2015-01-01

We present a comprehensive characterization of the memory effect arising in thin-junction silicon Single-Photon Avalanche Diodes (SPADs) when exposed to strong illumination. This partially unknown afterpulsing-like noise represents the main limiting factor when time-gated acquisitions are exploited to increase the measurement dynamic range of very fast (picosecond scale) and faint (single-photon) optical signals following a strong stray one. We report the dependences of this unwelcome signal-related noise on photon wavelength, detector temperature, and biasing conditions. Our results suggest that this so-called “memory effect” is generated in the deep regions of the detector, well below the depleted region, and its contribution on detector response is visible only when time-gated SPADs are exploited to reject a strong burst of photons

Memory effect in silicon time-gated single-photon avalanche diodes

Energy Technology Data Exchange (ETDEWEB)

Dalla Mora, A.; Contini, D., E-mail: davide.contini@polimi.it; Di Sieno, L. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Tosi, A.; Boso, G.; Villa, F. [Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Pifferi, A. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); CNR, Istituto di Fotonica e Nanotecnologie, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

2015-03-21

We present a comprehensive characterization of the memory effect arising in thin-junction silicon Single-Photon Avalanche Diodes (SPADs) when exposed to strong illumination. This partially unknown afterpulsing-like noise represents the main limiting factor when time-gated acquisitions are exploited to increase the measurement dynamic range of very fast (picosecond scale) and faint (single-photon) optical signals following a strong stray one. We report the dependences of this unwelcome signal-related noise on photon wavelength, detector temperature, and biasing conditions. Our results suggest that this so-called “memory effect” is generated in the deep regions of the detector, well below the depleted region, and its contribution on detector response is visible only when time-gated SPADs are exploited to reject a strong burst of photons.

An all-silicon passive optical diode.

Science.gov (United States)

Fan, Li; Wang, Jian; Varghese, Leo T; Shen, Hao; Niu, Ben; Xuan, Yi; Weiner, Andrew M; Qi, Minghao

2012-01-27

A passive optical diode effect would be useful for on-chip optical information processing but has been difficult to achieve. Using a method based on optical nonlinearity, we demonstrate a forward-backward transmission ratio of up to 28 decibels within telecommunication wavelengths. Our device, which uses two silicon rings 5 micrometers in radius, is passive yet maintains optical nonreciprocity for a broad range of input power levels, and it performs equally well even if the backward input power is higher than the forward input. The silicon optical diode is ultracompact and is compatible with current complementary metal-oxide semiconductor processing.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.; Rojas, Jhonathan Prieto; Ahmed, Sally; Hussain, Aftab M.; Inayat, Salman Bin; Hussain, Muhammad Mustafa

2013-01-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

Silicon fabric for multi-functional applications

KAUST Repository

Sevilla, Galo T.

2013-06-01

This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

Silicon based mechanic-photonic wavelength converter for infrared photo-detection

Science.gov (United States)

Rudnitsky, Arkady; Agdarov, Sergey; Gulitsky, Konstantin; Zalevsky, Zeev

2017-06-01

In this paper we present a new concept to realize a mechanic-photonic wavelength converter in silicon chip by construction of nanorods and by modulating the input illumination at temporal frequency matched to the mechanic resonance of the nanorods. The use case is to realize an infrared photo detector in silicon which is not based on absorption but rather on the mechanical interaction of the nanorods with the incoming illumination.

Microfluidic Platform for the Long-Term On-Chip Cultivation of Mammalian Cells for Lab-On-A-Chip Applications.

Science.gov (United States)

Bunge, Frank; Driesche, Sander van den; Vellekoop, Michael J

2017-07-10

Lab-on-a-Chip (LoC) applications for the long-term analysis of mammalian cells are still very rare due to the lack of convenient cell cultivation devices. The difficulties are the integration of suitable supply structures, the need of expensive equipment like an incubator and sophisticated pumps as well as the choice of material. The presented device is made out of hard, but non-cytotoxic materials (silicon and glass) and contains two vertical arranged membranes out of hydrogel. The porous membranes are used to separate the culture chamber from two supply channels for gases and nutrients. The cells are fed continuously by diffusion through the membranes without the need of an incubator and low requirements on the supply of medium to the assembly. The diffusion of oxygen is modelled in order to find the optimal dimensions of the chamber. The chip is connected via 3D-printed holders to the macroscopic world. The holders are coated with Parlyene C to ensure that only biocompatible materials are in contact with the culture medium. The experiments with MDCK-cells show the successful seeding inside the chip, culturing and passaging. Consequently, the presented platform is a step towards Lab-on-a-Chip applications that require long-term cultivation of mammalian cells.

Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

Science.gov (United States)

Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

2017-02-15

An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

International Nuclear Information System (INIS)

Annovi, A.; Beretta, M. M.; Calderini, G.; Crescioli, F.; Frontini, L.; Liberali, V.; Shojaii, S.R.; Stabile, A.

2017-01-01

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called 'pattern'. Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm 2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

On-chip skin color detection using a triple-well CMOS process

Science.gov (United States)

Boussaid, Farid; Chai, Douglas; Bouzerdoum, Abdesselam

2004-03-01

In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

Single molecule localization imaging of exosomes using blinking silicon quantum dots

Science.gov (United States)

Zong, Shenfei; Zong, Junzhu; Chen, Chen; Jiang, Xiaoyue; Zhang, Yizhi; Wang, Zhuyuan; Cui, Yiping

2018-02-01

Discovering new fluorophores, which are suitable for single molecule localization microscopy (SMLM) is important for promoting the applications of SMLM in biological or material sciences. Here, we found that silicon quantum dots (Si QDs) possess a fluorescence blinking behavior, making them an excellent candidate for SMLM. The Si QDs are fabricated using a facile microwave-assisted method. Blinking of Si QDs is confirmed by single particle fluorescence measurement and the spatial resolution achieved is about 30 nm. To explore the potential application of Si QDs as the nanoprobes for SMLM imaging, cell derived exosomes are chosen as the object owing to their small size (50-100 nm in diameter). Since CD63 is commonly presented on the membrane of exosomes, CD63 aptamers are attached to the surface of Si QDs to form nanoprobes which can specifically recognize exosomes. SMLM imaging shows that Si QDs based nanoprobes can indeed realize super resolved optical imaging of exosomes. More importantly, blinking of Si QDs is observed in water or PBS buffer with no need for special imaging buffers. Besides, considering that silicon is highly biocompatible, Si QDs should have minimal cytotoxicity. These features make Si QDs quite suitable for SMLM applications especially for live cell imaging.

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

Science.gov (United States)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

Science.gov (United States)

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

Directory of Open Access Journals (Sweden)

Shantonu Biswas

2016-03-01

Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

Atomic layer deposited TiO2 for implantable brain-chip interfacing devices

International Nuclear Information System (INIS)

Cianci, E.; Lattanzio, S.; Seguini, G.; Vassanelli, S.; Fanciulli, M.

2012-01-01

In this paper we investigated atomic layer deposition (ALD) TiO 2 thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 °C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al 2 O 3 buffer layer between TiO 2 and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

New dynamic silicon photonic components enabled by MEMS technology

Science.gov (United States)

Errando-Herranz, Carlos; Edinger, Pierre; Colangelo, Marco; Björk, Joel; Ahmed, Samy; Stemme, Göran; Niklaus, Frank; Gylfason, Kristinn B.

2018-02-01

Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

The CDF Silicon Vertex Detector

International Nuclear Information System (INIS)

Tkaczyk, S.; Carter, H.; Flaugher, B.

1993-01-01

A silicon strip vertex detector was designed, constructed and commissioned at the CDF experiment at the Tevatron collider at Fermilab. The mechanical design of the detector, its cooling and monitoring are presented. The front end electronics employing a custom VLSI chip, the readout electronics and various components of the SVX system are described. The system performance and the experience with the operation of the

Simple and reusable fibre-to-chip interconnect with adjustable coupling eficiency

NARCIS (Netherlands)

Heideman, Rene; Lambeck, Paul; Parriaux, Olivier M.; Kley, Ernst-Bernhard

1997-01-01

A simple, efficient and reusable fiber-to-chip interconnect is presented. The interconnect is based on a V-groove (wet- chemically etched) in silicon, combined with a loose-mode Si3N4-channel waveguide. The loose-mode waveguide is adiabatically tapered to the integrated optical (sensor) circuitry.

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

Science.gov (United States)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Single- and double- lumen silicone breast implant integrity: prospective evaluation of MR and US criteria.

Science.gov (United States)

Berg, W A; Caskey, C I; Hamper, U M; Kuhlman, J E; Anderson, N D; Chang, B W; Sheth, S; Zerhouni, E A

1995-10-01

To evaluate the accuracy of magnetic resonance (MR) and ultrasound (US) criteria for breast implant integrity. One hundred twenty-two single-lumen silicone breast implants and 22 bilumen implants were evaluated with surface coil MR imaging and US and surgically removed. MR criteria for implant failure were a collapsed implant shell ("linguine sign"), foci of silicone outside the shell ("noose sign"), and extracapsular gel, US criteria were collapsed shell, low-level echoes within the gel, and "snowstorm" echoes of extracapsular silicone. Among single-lumen implants, MR imaging depicted 39 of 40 ruptures, 14 of 28 with minimal leakage; 49 of 54 intact implants were correctly interpreted. US depicted 26 of 40 ruptured implants, four of 28 with minimal leakage, and 30 of 54 intact implants. Among bilumen implants, MR imaging depicted four of five implants with rupture of both lumina and nine of 10 as intact; US depicted one rupture and helped identify two of 10 as intact. Mammography accurately depicted the status of 29 of 30 bilumen implants with MR imaging correlation. MR imaging depicts implant integrity more accurately than US; neither method reliably depicts minimal leakage with shell collapse. Mammography is useful in screening bilumen implant integrity.

Silicon photon-counting avalanche diodes for single-molecule fluorescence spectroscopy

Science.gov (United States)

Michalet, Xavier; Ingargiola, Antonino; Colyer, Ryan A.; Scalia, Giuseppe; Weiss, Shimon; Maccagnani, Piera; Gulinatti, Angelo; Rech, Ivan; Ghioni, Massimo

2014-01-01

Solution-based single-molecule fluorescence spectroscopy is a powerful experimental tool with applications in cell biology, biochemistry and biophysics. The basic feature of this technique is to excite and collect light from a very small volume and work in a low concentration regime resulting in rare burst-like events corresponding to the transit of a single molecule. Detecting photon bursts is a challenging task: the small number of emitted photons in each burst calls for high detector sensitivity. Bursts are very brief, requiring detectors with fast response time and capable of sustaining high count rates. Finally, many bursts need to be accumulated to achieve proper statistical accuracy, resulting in long measurement time unless parallelization strategies are implemented to speed up data acquisition. In this paper we will show that silicon single-photon avalanche diodes (SPADs) best meet the needs of single-molecule detection. We will review the key SPAD parameters and highlight the issues to be addressed in their design, fabrication and operation. After surveying the state-of-the-art SPAD technologies, we will describe our recent progress towards increasing the throughput of single-molecule fluorescence spectroscopy in solution using parallel arrays of SPADs. The potential of this approach is illustrated with single-molecule Förster resonance energy transfer measurements. PMID:25309114

The CMS silicon strip tracker and its electronic readout

International Nuclear Information System (INIS)

Friedl, M.

2001-05-01

The Large Hadron Collider (LHC) at CERN (Geneva, CH) will be the world's biggest accelerator machine when operation starts in 2006. One of its four detector experiments is the Compact Muon Solenoid (CMS), consisting of a large-scale silicon tracker and electromagnetic and hadron calorimeters, all embedded in a solenoidal magnetic field of 4 T, and a muon system surrounding the magnet coil. The Silicon Strip Tracker has a sensitive area of 206m 2 with 10 million analog channels which are read out at the collider frequency of 40 MHz. The building blocks of the CMS Tracker are the silicon sensors, APV amplifier ASICs, supporting front-end ASICs, analog and digital optical links as well as data processors and control units in the back-end. Radiation tolerance, readout speed and the huge data volume are challenging requirements. The charge collection in silicon detectors was modeled, which is discussed as well as the concepts of readout amplifiers with respect to the LHC requirements, including the deconvolution method of fast pulse shaping, electronic noise constraints and radiation effects. Moreover, extensive measurements on prototype components of the CMS Tracker and different versions of the APV chip in particular were performed. There was a significant contribution to the construction of several detector modules, characterized them in particle beam tests and quantified radiation induced effects on the APV chip and on silicon detectors. In addition, a prototype of the analog optical link and the analog performance of the back-end digitization unit were evaluated. The results are very encouraging, demonstrating the feasibility of the CMS Silicon Strip Tracker system and motivating progress towards the construction phase. (author)

Study of double porous silicon surfaces for enhancement of silicon solar cell performance

Science.gov (United States)

Razali, N. S. M.; Rahim, A. F. A.; Radzali, R.; Mahmood, A.

2017-09-01

In this work, design and simulation of double porous silicon surfaces for enhancement of silicon solar cell is carried out. Both single and double porous structures are constructed by using TCAD ATHENA and TCAD DEVEDIT tools of the SILVACO software respectively. After the structures were created, I-V characteristics and spectral response of the solar cell were extracted using ATLAS device simulator. Finally, the performance of the simulated double porous solar cell is compared with the performance of both single porous and bulk-Si solar cell. The results showed that double porous silicon solar cell exhibited 1.8% efficiency compared to 1.3% and 1.2% for single porous silicon and bulk-Si solar cell.

Inverse Raman scattering in silicon: A free-carrier enhanced effect

International Nuclear Information System (INIS)

Solli, D. R.; Koonath, P.; Jalali, B.

2009-01-01

Stimulated Raman scattering has been harnessed to produce the first silicon lasers and amplifiers. The Raman effect can also produce intensity-dependent nonlinear loss through a corollary process, inverse Raman scattering (IRS). This process has never been observed in a semiconductor. We demonstrate IRS in silicon--a process that is substantially modified by optically generated free carriers--achieving attenuation levels >15 dB with a pump intensity of 4 GW/cm 2 . Surprisingly, free-carrier absorption, the detrimental effect that generally suppresses nonlinear effects in silicon, actually facilitates IRS by delaying the onset of contamination from coherent anti-Stokes Raman scattering. Silicon-based IRS could be a valuable tool for chip-scale signal processing.

Package-friendly piezoresistive pressure sensors with on-chip integrated packaging-stress-suppressed suspension (PS3) technology

International Nuclear Information System (INIS)

Wang, Jiachou; Li, Xinxin

2013-01-01

An on-chip integrated packaging-stress-suppressed suspension (PS 3 ) technology for a packaging-stress-free pressure sensor is proposed and developed. With a MIS (microholes interetch and sealing) micromachining process implemented only from the front-side of a single-side polished (1 1 1) silicon wafer, a compact cantilever-shaped PS 3 is on-chip integrated surrounding a piezoresistive pressure-sensing structure to provide a packaging-process/substrate-friendly method for low-cost but high-performance sensor applications. With the MIS process, the chip size of the PS 3 -enclosed pressure sensor is as small as 0.8 mm × 0.8 mm. Compared with a normal pressure sensor without PS 3 (but with an identical pressure-sensing structure), the proposed pressure sensor has the same sensitivity of 0.046 mV kPa −1 (3.3 V) −1 . However, without using the thermal compensation technique, a temperature coefficient of offset of only 0.016% °C −1 FS is noted for the sensor with PS 3 , which is about 15 times better than that for the sensor without PS 3 . Featuring effective isolation and elimination of the influence from packaging stress, the PS 3 technique is promising to be widely used for packaging-friendly mechanical sensors. (paper)

The silicon vertex detector of the Belle II experiment

Energy Technology Data Exchange (ETDEWEB)

Adamczyk, K. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Aihara, H. [Department of Physics, University of Tokyo, Tokyo 113-0033 (Japan); Angelini, C. [Dipartimento di Fisica, Universitá di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Aziz, T.; Babu, V. [Tata Institute of Fundamental Research, Mumbai 400005 (India); Bacher, S. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Bahinipati, S. [Indian Institute of Technology Bhubaneswar, Satya Nagar (India); Barberio, E.; Baroncelli, T. [School of Physics, University of Melbourne, Melbourne, Victoria 3010 (Australia); Basith, A.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Batignani, G. [Dipartimento di Fisica, Universitá di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bauer, A. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Behera, P.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Bergauer, T. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Bettarini, S. [Dipartimento di Fisica, Universitá di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bhuyan, B. [Indian Institute of Technology Guwahati, Assam 781039 (India); Bilka, T. [Faculty of Mathematics and Physics, Charles University, 121 16 Prague (Czech Republic); Bosi, F. [INFN Sezione di Pisa, I-56127 Pisa (Italy); Bosisio, L. [Dipartimento di Fisica, Universitá di Trieste, I-34127 Trieste (Italy); INFN Sezione di Trieste, I-34127 Trieste (Italy); Bozek, A. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); and others

2016-07-11

The silicon vertex detector of the Belle II experiment, structured in a lantern shape, consists of four layers of ladders, fabricated from two to five silicon sensors. The APV25 readout ASIC chips are mounted on one side of the ladder to minimize the signal path for reducing the capacitive noise; signals from the sensor backside are transmitted to the chip by bent flexible fan-out circuits. The ladder is assembled using several dedicated jigs. Sensor motion on the jig is minimized by vacuum chucking. The gluing procedure provides such a rigid foundation that later leads to the desired wire bonding performance. The full ladder with electrically functional sensors is consistently completed with a fully developed assembly procedure, and its sensor offsets from the design values are found to be less than 200 μm. The potential functionality of the ladder is also demonstrated by the radioactive source test.

Thermal neutron scattering kernels for sapphire and silicon single crystals

International Nuclear Information System (INIS)

Cantargi, F.; Granada, J.R.; Mayer, R.E.

2015-01-01

Highlights: • Thermal cross section libraries for sapphire and silicon single crystals were generated. • Debye model was used to represent the vibrational frequency spectra to feed the NJOY code. • Sapphire total cross section was measured at Centro Atómico Bariloche. • Cross section libraries were validated with experimental data available. - Abstract: Sapphire and silicon are materials usually employed as filters in facilities with thermal neutron beams. Due to the lack of the corresponding thermal cross section libraries for those materials, necessary in calculations performed in order to optimize beams for specific applications, here we present the generation of new thermal neutron scattering kernels for those materials. The Debye model was used in both cases to represent the vibrational frequency spectra required to feed the NJOY nuclear data processing system in order to produce the corresponding libraries in ENDF and ACE format. These libraries were validated with available experimental data, some from the literature and others obtained at the pulsed neutron source at Centro Atómico Bariloche

Bright trions in direct-bandgap silicon nanocrystals revealed bylow-temperature single-nanocrystal spectroscopy

Czech Academy of Sciences Publication Activity Database

Kůsová, Kateřina; Pelant, Ivan; Valenta, J.

2015-01-01

Roč. 4, Oct (2015), e336 ISSN 2047-7538 R&D Projects: GA ČR(CZ) GBP108/12/G108; GA ČR GPP204/12/P235 Institutional support: RVO:68378271 Keywords : silicon nanocrystals * single-nanocrystal spectroscopy * luminescing trions Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 13.600, year: 2015

Performance Test Results of a Single-sided Silicon Strip Detector with a Radioactive Source and a Proton Beam

International Nuclear Information System (INIS)

Ki, Y. I.; Kah, D. H.; Son, D. H.; Kang, H. D.; Kim, H. J.; Kim, H. O.; Bae, J. B.; Ryu, S.; Park, H.; Kim, K. R.

2007-01-01

Due to high intrinsic precision and high speed properties of a silicon material, the silicon detector has been used in various applications such as medical imaging detector, radiation detector, positioning detectors in space science and experimental particle physics. High technology, modern equipment, and deep expertise are required to design and fabricate good quality of silicon sensors. Only few facilities in the world can develop silicon sensors which meet requirements of sensor performances. That is one of main reasons that the silicon sensor is so expensive and it takes time to purchase the silicon sensor once it is ordered. We designed and fabricated AC-coupled single-sided silicon strip sensors and developed front-end electronics and DAQ system to read out sensor signals. The silicon strip sensors were fabricated on a 5-in. n-type silicon wafer which has an orientation, high resistivity (>5 kΩ · cm) and a thickness of 380 μm. We measured the signal-to-noise ratio (SNR) of each channel by using a radioactive source and a 45 MeV proton beam from the MC-50 cyclotron at the Korea Institute of Radiological and Medical Science (KIRAMS) in Seoul. We present the measurement results of the SNRs of the silicon strip sensor with a proton beam and radioactive sources

A bipolar analog front-end integrated circuit for the SDC silicon tracker

International Nuclear Information System (INIS)

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using AT ampersand T's CBIC-U2, 4 GHz f T complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 μm pitch double-sided silicon strip detector. The chip measures 6.8 mm x 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Φ=10 14 protons/cm 2 have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process

Al transmon qubits on silicon-on-insulator for quantum device integration

Science.gov (United States)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Multiple-Event, Single-Photon Counting Imaging Sensor

Science.gov (United States)

Zheng, Xinyu; Cunningham, Thomas J.; Sun, Chao; Wang, Kang L.

2011-01-01

The single-photon counting imaging sensor is typically an array of silicon Geiger-mode avalanche photodiodes that are monolithically integrated with CMOS (complementary metal oxide semiconductor) readout, signal processing, and addressing circuits located in each pixel and the peripheral area of the chip. The major problem is its single-event method for photon count number registration. A single-event single-photon counting imaging array only allows registration of up to one photon count in each of its pixels during a frame time, i.e., the interval between two successive pixel reset operations. Since the frame time can t be too short, this will lead to very low dynamic range and make the sensor merely useful for very low flux environments. The second problem of the prior technique is a limited fill factor resulting from consumption of chip area by the monolithically integrated CMOS readout in pixels. The resulting low photon collection efficiency will substantially ruin any benefit gained from the very sensitive single-photon counting detection. The single-photon counting imaging sensor developed in this work has a novel multiple-event architecture, which allows each of its pixels to register as more than one million (or more) photon-counting events during a frame time. Because of a consequently boosted dynamic range, the imaging array of the invention is capable of performing single-photon counting under ultra-low light through high-flux environments. On the other hand, since the multiple-event architecture is implemented in a hybrid structure, back-illumination and close-to-unity fill factor can be realized, and maximized quantum efficiency can also be achieved in the detector array.

Impedance spectra of patch clamp scenarios for single cells immobilized on a lab-on-a-chip

DEFF Research Database (Denmark)

Alberti, Massimo; Snakenborg, Detlef; Lopacinska, Joanna M.

2014-01-01

and simulated impedance spectra proved that the presented method could distinguish between a cell-attached mode and a whole-cell mode even with low-quality seals. In physiological conditions, the capacitance of HeLa cells was measured to *38 pF. The first gigaseal was recorded and maintained for 40 min. Once...... membrane. After incubating the chip for 24 h, HeLa cells adhered and grew on the chip surface but did not survive when trapped on the microapertures. The microfluidic system proved to work as a micro electrophysiological analysis system, and the IS-based method can be used for further studies on the post......A simple method based on impedance spectroscopy (IS) was developed to distinguish between different patch clamp modes for single cells trapped on microapertures in a patch clamp microchannel array designed for patch clamping on cultured cells. The method allows detecting via impedance analysis...

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

Science.gov (United States)

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

Atomic layer deposited TiO{sub 2} for implantable brain-chip interfacing devices

Energy Technology Data Exchange (ETDEWEB)

Cianci, E., E-mail: elena.cianci@mdm.imm.cnr.it [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (MB) (Italy); Lattanzio, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Dipartimento di Ingegneria dell' Informazione, Universita di Padova, 35131 Padova (Italy); Seguini, G. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Vassanelli, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Fanciulli, M. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano-Bicocca, 20126 Milano (Italy)

2012-05-01

In this paper we investigated atomic layer deposition (ALD) TiO{sub 2} thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 Degree-Sign C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al{sub 2}O{sub 3} buffer layer between TiO{sub 2} and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

A low-cost multichannel pulse-height analyzer PHA 256 using single-chip microcomputer

International Nuclear Information System (INIS)

Koehler, M.; Meiling, W.

1985-01-01

The PHA 256 multichannel analyzer on the base of the U8820 single-chip microcomputer applied for radiation measurements, for example in monitoring systems with scintillation detectors, is described. The analyzer contains a power supply unit and 7 boards, namely, the processor board; data and program memory; 8-bit analog-to-digital converter; driver to display device; keyboard with 23 function keys; pulse amplifier and high-voltage supply (up to 2 kV). Software used provides preprocessing of spectra supported by following functions: addition and subtraction of different spectra, spectrum monitoring by use of a 5-point-algorithm, calculation of peak areas with linearly interpolated background

Ultra-compact silicon nitride grating coupler for microscopy systems

OpenAIRE

Zhu, Yunpeng; Wang, Jie; Xie, Weiqiang; Tian, Bin; Li, Yanlu; Brainis, Edouard; Jiao, Yuqing; Van Thourhout, Dries

2017-01-01

Grating couplers have been widely used for coupling light between photonic chips and optical fibers. For various quantum-optics and bio-optics experiments, on the other hand, there is a need to achieve good light coupling between photonic chips and microscopy systems. Here, we propose an ultra-compact silicon nitride (SiN) grating coupler optimized for coupling light from a waveguide to a microscopy system. The grating coupler is about 4 by 2 mu m(2) in size and a 116 nm 1 dB bandwidth can be...

Large-scale quantum photonic circuits in silicon

Directory of Open Access Journals (Sweden)

Harris Nicholas C.

2016-08-01

Full Text Available Quantum information science offers inherently more powerful methods for communication, computation, and precision measurement that take advantage of quantum superposition and entanglement. In recent years, theoretical and experimental advances in quantum computing and simulation with photons have spurred great interest in developing large photonic entangled states that challenge today’s classical computers. As experiments have increased in complexity, there has been an increasing need to transition bulk optics experiments to integrated photonics platforms to control more spatial modes with higher fidelity and phase stability. The silicon-on-insulator (SOI nanophotonics platform offers new possibilities for quantum optics, including the integration of bright, nonclassical light sources, based on the large third-order nonlinearity (χ(3 of silicon, alongside quantum state manipulation circuits with thousands of optical elements, all on a single phase-stable chip. How large do these photonic systems need to be? Recent theoretical work on Boson Sampling suggests that even the problem of sampling from e30 identical photons, having passed through an interferometer of hundreds of modes, becomes challenging for classical computers. While experiments of this size are still challenging, the SOI platform has the required component density to enable low-loss and programmable interferometers for manipulating hundreds of spatial modes.

Charge collection measurements with p-type Magnetic Czochralski silicon single pad detectors

International Nuclear Information System (INIS)

Tosi, C.; Bruzzi, M.; Macchiolo, A.; Scaringella, M.; Petterson, M.K.; Sadrozinski, H.F.-W.; Betancourt, C.; Manna, N.; Creanza, D.; Boscardin, M.; Piemonte, C.; Zorzi, N.; Borrello, L.; Messineo, A.

2007-01-01

The charge collected from beta source particles in single pad detectors produced on p-type Magnetic Czochralski (MCz) silicon wafers has been measured before and after irradiation with 26 MeV protons. After a 1 MeV neutron equivalent fluence of 1x10 15 cm -2 the collected charge is reduced to 77% at bias voltages below 900 V. This result is compared with previous results from charge collection measurements

Exploration within the Network-on-Chip Paradigm

NARCIS (Netherlands)

Wolkotte, P.T.

2009-01-01

A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Its functionality and maximum clock frequency grew steadily over the years. Due to the continuous increase of the number of transistors available on-chip and the operational

Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

CERN Document Server

Posch, C

2002-01-01

Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

A Cytomorphic Chip for Quantitative Modeling of Fundamental Bio-Molecular Circuits.

Science.gov (United States)

2015-08-01

We describe a 0.35 μm BiCMOS silicon chip that quantitatively models fundamental molecular circuits via efficient log-domain cytomorphic transistor equivalents. These circuits include those for biochemical binding with automatic representation of non-modular and loading behavior, e.g., in cascade and fan-out topologies; for representing variable Hill-coefficient operation and cooperative binding; for representing inducer, transcription-factor, and DNA binding; for probabilistic gene transcription with analogic representations of log-linear and saturating operation; for gain, degradation, and dynamics of mRNA and protein variables in transcription and translation; and, for faithfully representing biological noise via tunable stochastic transistor circuits. The use of on-chip DACs and ADCs enables multiple chips to interact via incoming and outgoing molecular digital data packets and thus create scalable biochemical reaction networks. The use of off-chip digital processors and on-chip digital memory enables programmable connectivity and parameter storage. We show that published static and dynamic MATLAB models of synthetic biological circuits including repressilators, feed-forward loops, and feedback oscillators are in excellent quantitative agreement with those from transistor circuits on the chip. Computationally intensive stochastic Gillespie simulations of molecular production are also rapidly reproduced by the chip and can be reliably tuned over the range of signal-to-noise ratios observed in biological cells.

Tunable complex-valued multi-tap microwave photonic filter based on single silicon-oninsulator microring resonator

DEFF Research Database (Denmark)

Lloret, Juan; Sancho, Juan; Pu, Minhao

2011-01-01

A complex-valued multi-tap tunable microwave photonic filter based on single silicon-on-insulator microring resonator is presented. The degree of tunability of the approach involving two, three and four taps is theoretical and experimentally characterized, respectively. The constraints of exploit...

Production and performance of the silicon sensor and readout electronics for the PHENIX FVTX tracker

International Nuclear Information System (INIS)

Kapustinsky, Jon Steven

2009-01-01

The Forward Silicon Vertex Tracker (FVTX) upgrade for the PHENIX detector at RHIC will extend the vertex capability of the central PHENIX Silicon Vertex Tracker (VTX). The FVTX is designed with adequate spatial resolution to separate decay muons coming from the relatively long-lived heavy quark mesons (Charm and Beauty), from prompt particles and the longer-lived pion and kaon decays that originate at the primary collision vertex. These heavy quarks can be used to probe the high density medium that is formed in Au+Au collisions at RHIC. The FVTX is designed as two endcaps. Each endcap is comprised of four silicon disks covering opening angles from 10 to 35 degrees to match the existing muon arm acceptance. Each disk consists of p-on-n, silicon wedges, with ac-coupled mini-strips on 75 (micro)m radial pitch and proj ective length in the phi direction that increases with radius. A custom front-end chip, the FPHX, has been designed for the FVTX. The chip combines fast trigger capability with data push architecture in a low power design.

Fabrication of double-dot single-electron transistor in silicon nanowire

International Nuclear Information System (INIS)

Jo, Mingyu; Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Ono, Yukinori; Inokawa, Hiroshi; Choi, Jung-Bum; Takahashi, Yasuo

2010-01-01

We propose a simple method for fabricating Si single-electron transistors (SET) with coupled dots by means of a pattern-dependent-oxidation (PADOX) method. The PADOX method is known to convert a small one-dimensional Si wire formed on a silicon-on-insulator (SOI) substrate into a SET automatically. We fabricated a double-dot Si SET when we oxidized specially designed Si nanowires formed on SOI substrates. We analyzed the measured electrical characteristics by fitting the measurement and simulation results and confirmed the double-dot formation and the position of the two dots in the Si wire.

Oxygen recoil implant from SiO2 layers into single-crystalline silicon

International Nuclear Information System (INIS)

Wang, G.; Chen, Y.; Li, D.; Oak, S.; Srivastav, G.; Banerjee, S.; Tasch, A.; Merrill, P.; Bleiler, R.

2001-01-01

It is important to understand the distribution of recoil-implanted atoms and the impact on device performance when ion implantation is performed at a high dose through surface materials into single crystalline silicon. For example, in ultralarge scale integration impurity ions are often implanted through a thin layer of screen oxide and some of the oxygen atoms are inevitably recoil implanted into single-crystalline silicon. Theoretical and experimental studies have been performed to investigate this phenomenon. We have modified the Monte Carlo ion implant simulator, UT-Marlowe (B. Obradovic, G. Wang, Y. Chen, D. Li, C. Snell, and A. F. Tasch, UT-MARLOWE Manual, 1999), which is based on the binary collision approximation, to follow the full cascade and to dynamically modify the stoichiometry of the Si layer as oxygen atoms are knocked into it. CPU reduction techniques are used to relieve the demand on computational power when such a full cascade simulation is involved. Secondary ion mass spectrometry (SIMS) profiles of oxygen have been carefully obtained for high dose As and BF 2 implants at different energies through oxide layers of various thicknesses, and the simulated oxygen profiles are found to agree very well with the SIMS data. [copyright] 2001 American Institute of Physics

The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

Energy Technology Data Exchange (ETDEWEB)

Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2015-07-01

The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

Modelling of heating and photoexcitation of single-crystal silicon under multipulse irradiation by a nanosecond laser at 1.06 μm

Science.gov (United States)

Polyakov, D. S.; Yakovlev, E. B.

2018-03-01

We report a theoretical study of heating and photoexcitation of single-crystal silicon by nanosecond laser radiation at a wavelength of 1.06 μm. The proposed physicomathematical model of heating takes into account the complex nonlinear dynamics of the interband absorption coefficient of silicon and the contribution of the radial heat removal to the cooling of silicon between pulses under multipulse irradiation, which allows one to obtain a satisfactory agreement between theoretical predictions of silicon melting thresholds at different nanosecond pulse durations and experimental data (both under single-pulse and multipulse irradiation). It is found that under irradiation by nanosecond pulses at a wavelength of 1.06 μm, the dynamic Burshtein–Moss effect can play an important role in processes of photoexcitation and heating. It is shown that with the regimes typical for laser multipulse microprocessing of silicon (the laser spot diameter is less than 100 μm, and the repetition rate of pulses is about 100 kHz), the radial heat removal cannot be neglected in the analysis of heat accumulation processes.

On-chip Magnetic Separation and Cell Encapsulation in Droplets

Science.gov (United States)

Chen, A.; Byvank, T.; Bharde, A.; Miller, B. L.; Chalmers, J. J.; Sooryakumar, R.; Chang, W.-J.; Bashir, R.

2012-02-01

The demand for high-throughput single cell assays is gaining importance because of the heterogeneity of many cell suspensions, even after significant initial sorting. These suspensions may display cell-to-cell variability at the gene expression level that could impact single cell functional genomics, cancer, stem-cell research and drug screening. The on-chip monitoring of individual cells in an isolated environment could prevent cross-contamination, provide high recovery yield and ability to study biological traits at a single cell level These advantages of on-chip biological experiments contrast to conventional methods, which require bulk samples that provide only averaged information on cell metabolism. We report on a device that integrates microfluidic technology with a magnetic tweezers array to combine the functionality of separation and encapsulation of objects such as immunomagnetically labeled cells or magnetic beads into pico-liter droplets on the same chip. The ability to control the separation throughput that is independent of the hydrodynamic droplet generation rate allows the encapsulation efficiency to be optimized. The device can potentially be integrated with on-chip labeling and/or bio-detection to become a powerful single-cell analysis device.

Studies for an upgrade of ALICE Inner Tracking System: Pixel chip characterization

Directory of Open Access Journals (Sweden)

Park Jonghan

2017-01-01

Full Text Available Inner Tracking System (ITS of ALICE is used for vertex determination and tracking. Future heavy-ion program at the LHC aims to run with high luminosity. To address this challenge, upgrade program of ITS is underway, which aims at better position resolution (factor of 3, high detection efficiency (>99%, high-rate readout capabilities (100 kHz for Pb-Pb and moderate radiation hardness (> 700 krad. The new ITS will be composed with 7 layers of silicon pixel chip based on Monolithic Active Pixel Sensor (MAPS technology. The characterization test of various version of prototype chips at different phases of development has been performed. This contribution will provide the main characterization results obtained from the measurements performed at laboratories and using test beam for finalizing the pixel chip specification.

112 Gbit/s single-polarization silicon coherent receiver with hybrid-integrated BiCMOS linear TIA

NARCIS (Netherlands)

Verbist, J.; Zhang, J.; Moeneclaey, B.; van Weerdenburg, J.; van Uden, R.; Okonkwo, C.; Yin, X.; Bauwelinck, J.; Roelkens, G.

2015-01-01

We report the design, fabrication and verification of a single-polarization silicon coherent receiver with a low-power linear TIA array. Error-free operation assuming FEC is shown at bitrates of 112 Gbit/s (28 Gbaud 16-QAM) and 56 Gbit/s (28 Gbaud QPSK).

Characterization of the Photon Counting CHASE Jr., Chip Built in a 40-nm CMOS Process With a Charge Sharing Correction Algorithm Using a Collimated X-Ray Beam

Energy Technology Data Exchange (ETDEWEB)

Krzyżanowska, A. [AGH-UST, Cracow; Deptuch, G. W. [Fermilab; Maj, P. [AGH-UST, Cracow; Gryboś, P. [AGH-UST, Cracow; Szczygieł, R. [AGH-UST, Cracow

2017-08-01

This paper presents the detailed characterization of a single photon counting chip, named CHASE Jr., built in a CMOS 40-nm process, operating with synchrotron radiation. The chip utilizes an on-chip implementation of the C8P1 algorithm. The algorithm eliminates the charge sharing related uncertainties, namely, the dependence of the number of registered photons on the discriminator’s threshold, set for monochromatic irradiation, and errors in the assignment of an event to a certain pixel. The article presents a short description of the algorithm as well as the architecture of the CHASE Jr., chip. The analog and digital functionalities, allowing for proper operation of the C8P1 algorithm are described, namely, an offset correction for two discriminators independently, two-stage gain correction, and different operation modes of the digital blocks. The results of tests of the C8P1 operation are presented for the chip bump bonded to a silicon sensor and exposed to the 3.5- μm -wide pencil beam of 8-keV photons of synchrotron radiation. It was studied how sensitive the algorithm performance is to the chip settings, as well as the uniformity of parameters of the analog front-end blocks. Presented results prove that the C8P1 algorithm enables counting all photons hitting the detector in between readout channels and retrieving the actual photon energy.

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

Science.gov (United States)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

Science.gov (United States)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Investigation of a new low cost and low consumption single poly-silicon memory

Directory of Open Access Journals (Sweden)

Patrick Calenzo

2010-10-01

Full Text Available In this paper is presented an investigation on a new low cost and voltage consumption single poly-silicon memory cell for passive RFID (Radio Frequency IDentificationapplications. This structure is low cost due to its single poly-silicon design. This memory cell has two particularities : the first one is that no deported capacitor is necessary to program this cell which allows to reduce the structure size to 1.1μm². The second one is the way the cell is erased. A Zener diode is used to generate carriers in order to be injected into the floating gate. This Zener diode is one of the key points for the functionality that has to be validated with some electrical trials. These trials permit to integrate and use the Zener diodes measured in simulations of the complete memory cell. This is done to validate the best candidate between the Zener diodes used for the cell and highlight the efficiency in consumption and rapidity to erase the cell. Besides, the writing and the reading cases are simulated in order to show the low consumption required by the cell during these phases.

A prototype pixel readout chip for asynchronous detection applications

International Nuclear Information System (INIS)

Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

1991-01-01

A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

Mid-infrared integrated photonics on silicon: a perspective

Directory of Open Access Journals (Sweden)

Lin Hongtao

2017-12-01

Full Text Available The emergence of silicon photonics over the past two decades has established silicon as a preferred substrate platform for photonic integration. While most silicon-based photonic components have so far been realized in the near-infrared (near-IR telecommunication bands, the mid-infrared (mid-IR, 2–20-μm wavelength band presents a significant growth opportunity for integrated photonics. In this review, we offer our perspective on the burgeoning field of mid-IR integrated photonics on silicon. A comprehensive survey on the state-of-the-art of key photonic devices such as waveguides, light sources, modulators, and detectors is presented. Furthermore, on-chip spectroscopic chemical sensing is quantitatively analyzed as an example of mid-IR photonic system integration based on these basic building blocks, and the constituent component choices are discussed and contrasted in the context of system performance and integration technologies.

Nonclassical light sources for silicon photonics

Science.gov (United States)

Bajoni, Daniele; Galli, Matteo

2017-09-01

Quantum photonics has recently attracted a lot of attention for its disruptive potential in emerging technologies like quantum cryptography, quantum communication and quantum computing. Driven by the impressive development in nanofabrication technologies and nanoscale engineering, silicon photonics has rapidly become the platform of choice for on-chip integration of high performing photonic devices, now extending their functionalities towards quantum-based applications. Focusing on quantum Information Technology (qIT) as a key application area, we review recent progress in integrated silicon-based sources of nonclassical states of light. We assess the state of the art in this growing field and highlight the challenges that need to be overcome to make quantum photonics a reliable and widespread technology.

Design and Implementation of 8051 Single-Chip Microcontroller for Stationary 1.0 kW PEM Fuel Cell System

Directory of Open Access Journals (Sweden)

Pei-Hsing Huang

2014-01-01

Full Text Available Proton exchange membrane fuel cells (PEMFCs have attracted significant interest as a potential green energy source. However, if the performance of such systems is to be enhanced, appropriate control strategies must be applied. Accordingly, the present study proposes a sophisticated control system for a 1.0 kW PEMFC system comprising a fuel cell stack, an auxiliary power supply, a DC-DC buck converter, and a DC-AC inverter. The control system is implemented using an 8051 single-chip microcontroller and is designed to optimize the system performance and safety in both the startup phase and the long-term operation phase. The major features of the proposed control system are described and the circuit diagrams required for its implementation introduced. In addition, the touch-sensitive, intuitive human-machine interface is introduced and typical screens are presented. Finally, the electrical characteristics of the PEMFC system are briefly examined. Overall, the results confirm that the single-chip microcontroller presented in this study has significant potential for commercialization in the near future.

A flip chip process based on electroplated solder bumps

Science.gov (United States)

Salonen, J.; Salmi, J.

1994-01-01

Compared to wire bonding and TAB, flip chip technology using solder joints offers the highest pin count and packaging density and superior electrical performance. The chips are mounted upside down on the substrate, which can be made of silicon, ceramic, glass or - in some cases - even PCB. The extra processing steps required for chips are the deposition of a suitable thin film metal layer(s) on the standard Al pad and the formation of bumps. Also, the development of new fine line substrate technologies is required to utilize the full potential of the technology. In our bumping process, bump deposition is done by electroplating, which was chosen for its simplicity and economy. Sputter deposited molybdenum and copper are used as thin film layers between the aluminum pads and the solder bumps. A reason for this choice is that the metals can be selectively etched after bumping using the bumps as a mask, thus circumventing the need for a separate mask for etching the thin film metals. The bumps are electroplated from a binary Pb-Sn bath using a thick liquid photoresist. An extensively modified commercial flip chip bonder is used for alignment and bonding. Heat assisted tack bonding is used to attach the chips to the substrate, and final reflow joining is done without flux in a vacuum furnace.

SNP typing on the NanoChip electronic microarray

DEFF Research Database (Denmark)

Børsting, Claus; Sanchez Sanchez, Juan Jose; Morling, Niels

2005-01-01

We describe a single nucleotide polymorphism (SNP) typing protocol developed for the NanoChip electronic microarray. The NanoChip array consists of 100 electrodes covered by a thin hydrogel layer containing streptavidin. An electric currency can be applied to one, several, or all electrodes...

Low-cost and versatile thermal test chip for power assemblies assessment and thermometric calibration purposes

International Nuclear Information System (INIS)

Jorda, X.; Perpina, X.; Vellvehi, M.; Madrid, F.; Flores, D.; Hidalgo, S.; Millan, J.

2011-01-01

Chips specifically designed for thermal tests such as the assessment of packages, are of main interest in Microelectronics. Nevertheless, these test dies are required in relatively low quantities and their price is a limiting factor. This work describes a low-cost thermal test chip, specifically developed for the needs of power electronics. It is based on a poly-silicon heating resistor and a decoupled Pt temperature sensing resistor on the top, allowing to dissipate more than 60 W (170 W/cm 2 ) and reaching temperatures up to 200 o C. Its simple structure allows an easy simulation and modeling. These features have been taken in profit for packaging materials assessment, calibration of temperature measurement apparatus and methods, and validation of thermal models and simulations. - Highlights: → We describe a low-cost thermal test chip developed for power electronics applications. → It integrates a poly-silicon heating resistor and a Pt temperature sensing resistor on the top. → It can dissipate up to 200 W/cm 2 and work up to 200 o C. → It has been used for thermal resistance and conductivity measurement of substrates. → It allowed also the calibration of advanced thermometric equipments.

Silicon Nanophotonics for Many-Core On-Chip Networks