Hydrogen interactions with silicon-on-insulator materials

OpenAIRE

Rivera de Mena, A.J.

2003-01-01

The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

Science.gov (United States)

Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

2008-01-01

A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

Science.gov (United States)

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

The effect of gate length on SOI-MOSFETS operation | Baedi ...

African Journals Online (AJOL)

The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

Electron mobility in the inversion layers of fully depleted SOI films

Energy Technology Data Exchange (ETDEWEB)

Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

2017-04-15

The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.

Method to improve commercial bonded SOI material

Science.gov (United States)

Maris, Humphrey John; Sadana, Devendra Kumar

2000-07-11

A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

Numerical study of self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride substrate

International Nuclear Information System (INIS)

Ding Yanfang; Zhu Ziqiang; Zhu Ming; Lin Chenglu

2006-01-01

Compared with bulk-silicon technology, silicon-on-insulator (SOI) technology possesses many advantages but it is inevitable that the buried silicon dioxide layer also thermally insulates the metal-oxide-silicon field-effect transistors (MOSFETs) from the bulk due to the low thermal conductivity. One of the alternative insulator to replace the buried oxide layer is aluminum nitride (MN), which has a thermal conductivity that is about 200 times higher than that of SiO 2 (320 W·m -1 ·K -1 versus 1.4 W·m -1 ·K -l ). To investigate the self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride (SOAN) substrate, a two-dimensional numerical analysis is performed by using a device simulator called MEDICI run on a Solaris workstation to simulate the electrical characteristics and temperature distribution by comparing with those of bulk and standard SOI MOSFETs. Our study suggests that AIN is a suitable alternative to silicon dioxide as a buried dielectric in SOI and expands the applications of SOI to high temperature conditions. (authors)

A Numerical Study on Phonon Spectral Contributions to Thermal Conduction in Silicon-on-Insulator Transistor Using Electron-Phonon Interaction Model

Energy Technology Data Exchange (ETDEWEB)

Kang, Hyung-sun; Koh, Young Ha; Jin, Jae Sik [Chosun College of Science and Technology, Gwangju (Korea, Republic of)

2017-06-15

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

Energy Technology Data Exchange (ETDEWEB)

Hemperek, Tomasz, E-mail: hemperek@uni-bonn.de; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

2015-10-01

An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

International Nuclear Information System (INIS)

Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

2013-01-01

Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

2007-07-25

A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

International Nuclear Information System (INIS)

Zhang, Z.L.; Asano, T.; Uno, H.; Tero, R.; Suzui, M.; Nakao, S.; Kaito, T.; Shibasaki, K.; Tominaga, M.; Utsumi, Y.; Gao, Y.L.; Urisu, T.

2008-01-01

The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 μm diameter is formed through the top Si layer and the SiO 2 box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully

Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

Energy Technology Data Exchange (ETDEWEB)

Zhang, Z.L.; Asano, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Uno, H. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Tero, R. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Suzui, M.; Nakao, S. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Kaito, T. [SII NanoTechnology Inc., 36-1, Takenoshita, Oyama-cho, Sunto-gun, Shizuoka, 410-1393 (Japan); Shibasaki, K.; Tominaga, M. [Okazaki Institute for Integrative Bioscience, 5-1, Higashiyama, Myodaiji, Okazaki, 444-8787 (Japan); Utsumi, Y. [Laboratory of Advanced Science and Technology for Industry, University of Hyogo, 3-1-2, Koto, Kamigori, Ako-gun, Hyogo, 678-1205 (Japan); Gao, Y.L. [Department of Physics and Astronomy, Rochester University, Rochester, New York 14627 (United States); Urisu, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan)], E-mail: urisu@ims.ac.jp

2008-03-03

The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 {mu}m diameter is formed through the top Si layer and the SiO{sub 2} box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully.

A monolithic active pixel sensor for ionizing radiation using a 180 nm HV-SOI process

Energy Technology Data Exchange (ETDEWEB)

Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany)

2016-07-01

An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-180 nm High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. Standard FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to trapped charge in the buried oxide layer and charged interface states created at the silicon oxide boundaries (back gate effect). The X-FAB 180 nm HV-SOI technology offers an additional isolation using a deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection. The design and measurement results from first prototypes are presented including radiation tolerance to total ionizing dose and charge collection properties of neutron irradiated samples.

Electrical activation of solid-phase epitaxially regrown ultra-low energy boron implants in Ge preamorphised silicon and SOI

International Nuclear Information System (INIS)

Hamilton, J.J.; Collart, E.J.H.; Colombeau, B.; Jeynes, C.; Bersani, M.; Giubertoni, D.; Sharp, J.A.; Cowern, N.E.B.; Kirkby, K.J.

2005-01-01

The formation of highly activated ultra-shallow junctions (USJ) is one of the key requirements for the next generation of CMOS devices. One promising method for achieving this is the use of Ge preamorphising implants (PAI) prior to ultra-low energy B implantation. In future technology nodes, bulk silicon wafers may be supplanted by Silicon-on-Insulator (SOI), and an understanding of the Solid Phase Epitaxial (SPE) regrowth process and its correlation to dopant electrical activation in both bulk silicon and SOI is essential in order to understand the impact of this potential technology change. This kind of understanding will also enable tests of fundamental models for defect evolution and point-defect reactions at silicon/oxide interfaces. In the present work, B is implanted into Ge PAI silicon and SOI wafers with different PAI conditions and B doses, and resulting samples are annealed at various temperatures and times. Glancing-exit Rutherford Backscattering Spectrometry (RBS) is used to monitor the regrowth of the amorphous silicon, and the resulting redistribution and electrical activity of B are monitored by SIMS and Hall measurements. The results confirm the expected enhancement of regrowth velocity by B doping, and show that this velocity is otherwise independent of the substrate type and the Ge implant distribution within the amorphised layer. Hall measurements on isochronally annealed samples show that B deactivates less in SOI material than in bulk silicon, in cases where the Ge PAI end-of-range defects are close to the SOI back interface

Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

Science.gov (United States)

2016-08-01

APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...high sound velocity — makes guiding acoustic waves difficult, motivating the use of soft chalcogenide glasses and partial or complete releases (removal

Space and military radiation effects in silicon-on-insulator devices

International Nuclear Information System (INIS)

Schwank, J.R.

1996-09-01

Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

Science.gov (United States)

Kapoor, V. J.; Shokrani, M.

1991-01-01

A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

Science.gov (United States)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Performance study of double SOI image sensors

Science.gov (United States)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Crosstalk analysis of silicon-on-insulator nanowire-arrayed waveguide grating

International Nuclear Information System (INIS)

Li Kai-Li; An Jun-Ming; Zhang Jia-Shun; Wang Yue; Wang Liang-Liang; Li Jian-Guang; Wu Yuan-Da; Yin Xiao-Jie; Hu Xiong-Wei

2016-01-01

The factors influencing the crosstalk of silicon-on-insulator (SOI) nanowire arrayed waveguide grating (AWG) are analyzed using the transfer function method. The analysis shows that wider and thicker arrayed waveguides, outsider fracture of arrayed waveguide, and larger channel space, could mitigate the deterioration of crosstalk. The SOI nanowire AWGs with different arrayed waveguide widths are fabricated by using deep ultraviolet lithography (DUV) and inductively coupled plasma etching (ICP) technology. The measurement results show that the crosstalk performance is improved by about 7 dB through adopting 800 nm arrayed waveguide width. (paper)

High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

International Nuclear Information System (INIS)

Caër, Charles; Le Roux, Xavier; Cassan, Eric

2013-01-01

We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

International Nuclear Information System (INIS)

Park, Jea-Gun; Kim, Seong-Je; Shin, Mi-Hee; Song, Seung-Hyun; Shim, Tae-Hun; Chung, Sung-Woong; Enomoto, Hirofumi

2011-01-01

A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 μA memory margin. This is a step toward achieving a terabit volatile memory cell.

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

International Nuclear Information System (INIS)

Yuan, Yang; Yong, Gao; Peng-Liang, Gong

2008-01-01

A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Technology development for SOI monolithic pixel detectors

International Nuclear Information System (INIS)

Marczewski, J.; Domanski, K.; Grabiec, P.; Grodner, M.; Jaroszewicz, B.; Kociubinski, A.; Kucharski, K.; Tomaszewski, D.; Caccia, M.; Kucewicz, W.; Niemiec, H.

2006-01-01

A monolithic detector of ionizing radiation has been manufactured using silicon on insulator (SOI) wafers with a high-resistivity substrate. In our paper the integration of a standard 3 μm CMOS technology, originally designed for bulk devices, with fabrication of pixels in the bottom wafer of a SOI substrate is described. Both technological sequences have been merged minimizing thermal budget and providing suitable properties of all the technological layers. The achieved performance proves that fully depleted monolithic active pixel matrix might be a viable option for a wide spectrum of future applications

The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator

Science.gov (United States)

Jafar, N.; Soin, N.

2009-06-01

This work presents the noise behaviour due to the applied Dual Material Gate (DMG) on the 75 nm n-channel Silicon On Insulator (SOI) device operating in the fully depletion mode, particularly for microwave circuit design. Influences of DMG properties namely the gate length ratio (L1:L2) and gate material workfunction difference (ΔΦM) as well as structural and operational parameters which are silicon thickness (TSi) and threshold voltage (VTH) setting variation on the noise performance were carried out on simulation basis using ATLAS 2D. Results show better noise performance in DMG as compare to the standard gate structure of FD-SOI devices. Higher VTH for DMG design is recommended for minimized noise figure in line with the advantage of inverse VTH roll-off characteristics for short channel effects suppression.

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Directory of Open Access Journals (Sweden)

Gammon P.M.

2017-01-01

Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

Science.gov (United States)

Ghaffari, Majid; Orouji, Ali A.

2018-06-01

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

Fully etched apodized grating coupler on the SOI platform with −058 dB coupling efficiency

DEFF Research Database (Denmark)

Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

2014-01-01

We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally investiga......We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally...

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

Science.gov (United States)

Patterson, Richard; Hammoud, Ahmad

2010-01-01

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Characterizing SOI Wafers By Use Of AOTF-PHI

Science.gov (United States)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

International Nuclear Information System (INIS)

Fu Qiang; Zhang Wan-Rong; Jin Dong-Yue; Zhao Yan-Xiao; Wang Xiao

2016-01-01

The product of the cutoff frequency and breakdown voltage ( f T ×BV CEO ) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of f T ×BV CEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness ( T BOX ) on f T , BV CEO , and the FOM of f T ×BV CEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces f T , slightly increases BV CEO to some extent, but ultimately degrades the FOM of f T ×BV CEO . Although the f T , BV CEO , and the FOM of f T ×BV CEO can be improved by increasing SOI insulator SiO 2 layer thickness T BOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO 2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick T BOX , a thin N + -buried layer is introduced into collector region to not only improve the FOM of f T ×BV CEO , but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. The result show that the FOM of f T ×BV CEO is improved and the device temperature decreases as the N + -buried layer shifts toward SOI substrate insulation layer

Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

Science.gov (United States)

Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2011-06-01

For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

Integrated programmable photonic filter on the silicon -on- insulator platform

DEFF Research Database (Denmark)

Liao, Shasha; Ding, Yunhong; Peucheret, Christophe

2014-01-01

We propose and demonstrate a silicon - on - insulator (SOI) on - chip programmable filter based on a four - tap finite impulse response structure. The photonic filter is programmable thanks to amplitude and phase modulation of each tap controlled by thermal heater s. We further demonstrate...... the tunability of the filter central wavelength, bandwidth and variable passband shape. The tuning range of the central wavelength is at least 42% of the free spectral range. The bandwidth tuning range is at least half of the free spectral range. Our scheme has distinct advantages of compactness, capability...

A technique for simultaneously improving the product of cutoff frequency-breakdown voltage and thermal stability of SOI SiGe HBT

Science.gov (United States)

Fu, Qiang; Zhang, Wan-Rong; Jin, Dong-Yue; Zhao, Yan-Xiao; Wang, Xiao

2016-12-01

The product of the cutoff frequency and breakdown voltage (fT×BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (TBOX) on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEO to some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT, BVCEO, and the FOM of fT×BVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEO is improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer

SOI Digital Accelerometer Based on Pull-in Time Configuration

NARCIS (Netherlands)

Pakula, L.S.; Rajaraman, V.; French, P.J.

2009-01-01

The operation principle, design, fabrication and measurement results of a quasi digital accelerometer fabricated on a thin silicon-on-insulator (SOI) substrate is presented. The accelerometer features quasi-digital output, therefore eliminating the need for analogue signal conditioning. The

X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates.

Science.gov (United States)

Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

2013-08-01

On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

Towards Polarization Diversity on the SOI Platform With Simple Fabrication Process

DEFF Research Database (Denmark)

Ding, Yunhong; Liu, Liu; Peucheret, Christophe

2011-01-01

We present a polarization diversity circuit built on the silicon-on-insulator (SOI) platform, which can be fabricated by a simple process. The polarization diversity is based on two identical air-clad asymmetrical directional couplers, which simultaneously play the roles of polarization splitter...... and rotator. A silicon polarization diversity circuit with a single microring resonator is fabricated on the SOI platform. Only ${1-dB polarization-dependent loss is demonstrated. A significant improvement of the polarization dependence is obtained for 20-Gb/s nonreturn-to-zero differential phase-shift keying...

SOI MESFETs on high-resistivity, trap-rich substrates

Science.gov (United States)

Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

2018-04-01

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

Increased carrier lifetimes in epitaxial silicon layers on buried silicon nitride produced by ion implantation

International Nuclear Information System (INIS)

Skorupa, W.; Kreissig, U.; Hensel, E.; Bartsch, H.

1984-01-01

Carrier lifetimes were measured in epitaxial silicon layers deposited on buried silicon nitride produced by high-dose nitrogen implantation at 330 keV. The values were in the range 20-200 μs. The results are remarkable taking into account the high density of crystal defects in the epitaxial layers. Comparing with other SOI technologies the measured lifetimes are higher by 1-2 orders of magnitude. (author)

Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

Directory of Open Access Journals (Sweden)

Xiaojun Cheng

2014-05-01

Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

International Nuclear Information System (INIS)

Kim, Tae-Hyun; Park, Jea-Gun

2013-01-01

We investigated the combined effect of the strained Si channel and hole confinement on the memory margin enhancement for a capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator (ε-Si SGOI). The memory margin for the ε-Si SGOI capacitor-less memory cell was higher than that of the memory cell fabricated on an unstrained Si-on-insulator (SOI) and increased with increasing Ge concentration of the relaxed SiGe layer; i.e. the memory margin for the ε-Si SGOI capacitor-less memory cell (138.6 µA) at a 32 at% Ge concentration was 3.3 times higher than the SOI capacitor-less memory cell (43 µA). (paper)

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

Science.gov (United States)

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Implantation of oxygen ions for the realization of SOS (silicon on insulator) structures: SIMOX

International Nuclear Information System (INIS)

Margail, J.

1987-03-01

Highdose oxygen implantation is becoming a serious candidate for SOI (silicon on insulator) structure realization. The fabrication condition study of these substrates allowed to show up the implantation and annealing parameter importance for microstructure, and particularly for crystal quality of silicon films. It has been shown that the use of high temperature annealings leads to high quality substrates: monocrystal silicon film without any precipitate, at the card scale; Si/Si O 2 interface formation. After annealing at 1340 O C, Hall mobilities have been measured in silicon film, and its residual doping is very low. First characteristics and performance of submicron CMOS circuits prooves the electric quality of these substrates [fr

Waveguide-integrated vertical pin photodiodes of Ge fabricated on p+ and n+ Si-on-insulator layers

Science.gov (United States)

Ito, Kazuki; Hiraki, Tatsurou; Tsuchizawa, Tai; Ishikawa, Yasuhiko

2017-04-01

Vertical pin structures of Ge photodiodes (PDs) integrated with Si optical waveguides are fabricated by depositing Ge epitaxial layers on Si-on-insulator (SOI) layers, and the performances of n+-Ge/i-Ge/p+-SOI PDs are compared with those of p+-Ge/i-Ge/n+-SOI PDs. Both types of PDs show responsivities as high as 1.0 A/W at 1.55 µm, while the dark leakage current is different, which is consistent with previous reports on free-space PDs formed on bulk Si wafers. The dark current of the p+-Ge/i-Ge/n+-SOI PDs is higher by more than one order of magnitude. Taking into account the activation energies for dark current as well as the dependence on PD area, the dark current of the n+-Ge/i-Ge/p+-SOI PDs is dominated by the thermal generation of carriers via mid-gap defect levels in Ge, while for the p+-Ge/i-Ge/n+-SOI PDs, the dark current is ascribed to not only thermal generation but also other mechanisms such as locally formed conduction paths.

Research on SOI-based micro-resonator devices

Science.gov (United States)

Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

2010-10-01

SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of 10 Gbit/s high speed microring modulators.

A high efficiency lateral light emitting device on SOI

NARCIS (Netherlands)

Hoang, T.; Le Minh, P.; Holleman, J.; Zieren, V.; Goossens, M.J.; Schmitz, Jurriaan

2005-01-01

The infrared light emission of lateral p/sup +/-p-n/sup +/ diodes realized on SIMOX-SOI (separation by implantation of oxygen - silicon on insulator) substrates has been studied. The confinement of the free carriers in one dimension due to the buried oxide was suggested to be a key point to increase

Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

Science.gov (United States)

Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-12-13

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

Formation of SIMOX–SOI structure by high-temperature oxygen implantation

International Nuclear Information System (INIS)

Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

2015-01-01

We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 10"1"7–10"1"8 ions/cm"2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO_2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO_2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

SOI MESFETs for Extreme Environment Electronics, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — We are proposing a new extreme environment electronics (EEE) technology based on silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs)....

Silicon-on-insulator-based polarization-independent 1×3 broadband beam splitter with adiabatic coupling

Science.gov (United States)

Gong, Yuanhao; Liu, Lei; Chang, Limin; Li, Zhiyong; Tan, Manqing; Yu, Yude

2017-10-01

We propose and numerically simulate a polarization-independent 1×3 broadband beam splitter based on silicon-on-insulator (SOI) technology with adiabatic coupling. The designed structure is simulated by beam-propagation-method (BPM) and gets simulated transmission uniformity of three outputs better than 0.3dB for TE-polarization and 0.8dB for TM-polarization in a broadband of 180nm.

Guided acoustic and optical waves in silicon-on-insulator for Brillouin scattering and optomechanics

Directory of Open Access Journals (Sweden)

Christopher J. Sarabalis

2016-10-01

Full Text Available We numerically study silicon waveguides on silica showing that it is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI material system. Thin waveguides, or fins, exhibit geometrically softened mechanical modes at gigahertz frequencies with phase velocities below the Rayleigh velocity in glass, eliminating acoustic radiation losses. We propose slot waveguides on glass with telecom optical frequencies and strong radiation pressure forces resulting in Brillouin gains on the order of 500 and 50 000 W−1m−1 for backward and forward Brillouin scattering, respectively.

Strong Electro-Absorption in GeSi Epitaxy on Silicon-on-Insulator (SOI

Directory of Open Access Journals (Sweden)

John E. Cunningham

2012-04-01

Full Text Available We have investigated the selective epitaxial growth of GeSi bulk material on silicon-on-insulator substrates by reduced pressure chemical vapor deposition. We employed AFM, SIMS, and Hall measurements, to characterize the GeSi heteroepitaxy quality. Optimal growth conditions have been identified to achieve low defect density, low RMS roughness with high selectivity and precise control of silicon content. Fabricated vertical p-i-n diodes exhibit very low dark current density of 5 mA/cm² at −1 V bias. Under a 7.5 V/µm E-field, GeSi alloys with 0.6% Si content demonstrate very strong electro-absorption with an estimated effective ∆α/α around 3.5 at 1,590 nm. We compared measured ∆α/α performance to that of bulk Ge. Optical modulation up to 40 GHz is observed in waveguide devices while small signal analysis indicates bandwidth is limited by device parasitics.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

Science.gov (United States)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Emerging heterogeneous integrated photonic platforms on silicon

Directory of Open Access Journals (Sweden)

Fathpour Sasan

2015-05-01

Full Text Available Silicon photonics has been established as a mature and promising technology for optoelectronic integrated circuits, mostly based on the silicon-on-insulator (SOI waveguide platform. However, not all optical functionalities can be satisfactorily achieved merely based on silicon, in general, and on the SOI platform, in particular. Long-known shortcomings of silicon-based integrated photonics are optical absorption (in the telecommunication wavelengths and feasibility of electrically-injected lasers (at least at room temperature. More recently, high two-photon and free-carrier absorptions required at high optical intensities for third-order optical nonlinear effects, inherent lack of second-order optical nonlinearity, low extinction ratio of modulators based on the free-carrier plasma effect, and the loss of the buried oxide layer of the SOI waveguides at mid-infrared wavelengths have been recognized as other shortcomings. Accordingly, several novel waveguide platforms have been developing to address these shortcomings of the SOI platform. Most of these emerging platforms are based on heterogeneous integration of other material systems on silicon substrates, and in some cases silicon is integrated on other substrates. Germanium and its binary alloys with silicon, III–V compound semiconductors, silicon nitride, tantalum pentoxide and other high-index dielectric or glass materials, as well as lithium niobate are some of the materials heterogeneously integrated on silicon substrates. The materials are typically integrated by a variety of epitaxial growth, bonding, ion implantation and slicing, etch back, spin-on-glass or other techniques. These wide range of efforts are reviewed here holistically to stress that there is no pure silicon or even group IV photonics per se. Rather, the future of the field of integrated photonics appears to be one of heterogenization, where a variety of different materials and waveguide platforms will be used for

ARROW-based silicon-on-insulator photonic crystal waveguides with reduced losses

DEFF Research Database (Denmark)

Lavrinenko, Andrei; Novitsky, A.; Zhilko, V.V.

2006-01-01

We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits.......We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits....

Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector

Energy Technology Data Exchange (ETDEWEB)

Ono, Shun, E-mail: s-ono@champ.hep.sci.osaka-u.ac.jp [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Togawa, Manabu; Tsuji, Ryoji; Mori, Teppei [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Yamada, Miho; Arai, Yasuo; Tsuboyama, Toru; Hanagaki, Kazunori [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org. (KEK), 1-1 Oho, Tsukuba (Japan)

2017-02-11

We have been developing a new monolithic pixel sensor with silicon-on-insulator (SOI) technology for the International Linear Collider (ILC) vertex detector system. The SOI monolithic pixel detector is realized using standard CMOS circuits fabricated on a fully depleted sensor layer. The new SOI sensor SOFIST can store both the position and timing information of charged particles in each 20×20 μm{sup 2} pixel. The position resolution is further improved by the position weighted with the charges spread to multiple pixels. The pixel also records the hit timing with an embedded time-stamp circuit. The sensor chip has column-parallel analog-to-digital conversion (ADC) circuits and zero-suppression logic for high-speed data readout. We are designing and evaluating some prototype sensor chips for optimizing and minimizing the pixel circuit.

110 GHz hybrid mode-locked fiber laser with enhanced extinction ratio based on nonlinear silicon-on-insulator micro-ring-resonator (SOI MRR)

International Nuclear Information System (INIS)

Liu, Yang; Hsu, Yung; Chow, Chi-Wai; Yang, Ling-Gang; Lai, Yin-Chieh; Yeh, Chien-Hung; Tsang, Hon-Ki

2016-01-01

We propose and experimentally demonstrate a new 110 GHz high-repetition-rate hybrid mode-locked fiber laser using a silicon-on-insulator microring-resonator (SOI MRR) acting as the optical nonlinear element and optical comb filter simultaneously. By incorporating a phase modulator (PM) that is electrically driven at a fraction of the harmonic frequency, an enhanced extinction ratio (ER) of the optical pulses can be produced. The ER of the optical pulse train increases from 3 dB to 10 dB. As the PM is only electrically driven by the signal at a fraction of the harmonic frequency, in this case 22 GHz (110 GHz/5 GHz), a low bandwidth PM and driving circuit can be used. The mode-locked pulse width and the 3 dB spectral bandwidth of the proposed mode-locked fiber laser are measured, showing that the optical pulses are nearly transform limited. Moreover, stability evaluation for an hour is performed, showing that the proposed laser can achieve stable mode-locking without the need for optical feedback or any other stabilization mechanism. (letter)

Compact polarization beam splitter for silicon photonic integrated circuits with a 340-nm-thick silicon core layer.

Science.gov (United States)

Li, Chenlei; Dai, Daoxin

2017-11-01

A polarization beam splitter (PBS) is proposed and realized for silicon photonic integrated circuits with a 340-nm-thick silicon core layer by introducing an asymmetric directional coupler (ADC), which consists of a silicon-on-insulator (SOI) nanowire and a subwavelength grating (SWG) waveguide. The SWG is introduced to provide an optical waveguide which has much higher birefringence than a regular 340-nm-thick SOI nanowire, so that it is possible to make the phase-matching condition satisfied for TE polarization only in the present design when the waveguide dimensions are optimized. Meanwhile, there is a significant phase mismatching for TM polarization automatically. In this way, the present ADC enables strong polarization selectivity to realize a PBS that separates TE and TM polarizations to the cross and through ports, respectively. The realized PBS has a length of ∼2  μm for the coupling region. For the fabricated PBS, the extinction ratio (ER) is 15-30 dB and the excess loss is 0.2-2.6 dB for TE polarization while the ER is 20-27 dB and the excess loss is 0.3-2.8 dB for TM polarization when operating in the wavelength range of 1520-1580 nm.

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

Science.gov (United States)

Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

2009-10-01

We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

Science.gov (United States)

Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

2001-12-01

We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

International Nuclear Information System (INIS)

Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Moro, F. de; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

2008-01-01

Several successful development programs have been conducted on infra-red bolometer arrays at the 'Commissariat a l'Energie Atomique' (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8x8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32x32 pixels in size

Light extraction from GaN-based LED structures on silicon-on-insulator substrates

Energy Technology Data Exchange (ETDEWEB)

Tripathy, S.; Teo, S.L.; Lin, V.K.X.; Chen, M.F. [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology, and Research), 117602 (Singapore); Dadgar, A.; Krost, A. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany); AZZURRO Semiconductors AG, Universitaetsplatz 1, 39016 Magdeburg (Germany); Christen, J. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany)

2010-01-15

Nano-patterning of GaN-based devices is a promising technology in the development of high output power devices. Recent researches have been focused on the realization of two-dimensional (2D) photonic crystal (PhC) structure to improve light extraction efficiency and to control the direction of emission. In this study, we have demonstrated improved light extraction from green light emitting diode (LED) structures on thin silicon-on-insulator (SOI) substrates using surface nanopatterning. Scanning electron microscopy (SEM) is used to probe the size, shape, and etch depth of nano-patterns on the LED surfaces. Different types of nanopatterns were created by e-beam lithography and inductively coupled plasma etching. The LED structures after post processing are studied by photoluminescence (PL) measurements. The GaN nanophotonic structures formed by ICP etching led to more than five-fold increase in the intensity of the green emission. The improved light extraction is due to the combination of SOI substrate reflectivity and photonic structures on top GaN LED surfaces. (copyright 2010 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

Science.gov (United States)

Wu, Jiayang; Moein, Tania; Xu, Xingyuan; Moss, David J.

2018-04-01

We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI) nanowires implemented by cascaded Sagnac loop reflector (CSLR) resonators. We investigate mode splitting in these standing-wave (SW) resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs) and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

Buried oxide layer in silicon

Science.gov (United States)

Sadana, Devendra Kumar; Holland, Orin Wayne

2001-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

Science.gov (United States)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

Science.gov (United States)

Feng, Tom; Ghosh, Amal K.

1980-01-01

Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300.degree. C. to about 400.degree. C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250.degree. C. Preferably the insulating layer is naturally grown silicon oxide layer.

Adiabatic Nanofocusing in Hybrid Gap Plasmon Waveguides on the Silicon-on-Insulator Platform.

Science.gov (United States)

Nielsen, Michael P; Lafone, Lucas; Rakovich, Aliaksandra; Sidiropoulos, Themistoklis P H; Rahmani, Mohsen; Maier, Stefan A; Oulton, Rupert F

2016-02-10

We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.

Characterization of dielectric materials in thin layers for the development of S.O.I. (Silicon on Insulator) substrates

International Nuclear Information System (INIS)

Gruber, Olivier

1999-01-01

This thesis deals with the characterization of oxide layer placed inside S.O.I. substrates and submitted to irradiation. This type of material is used for the development of hardened electronic components, that is to say components able to be used in a radiative environment. The irradiation induces charges (electrons or holes) in the recovered oxide. A part of these charges is trapped which leads to changes of the characteristics of the electronic components made on these substrates. The main topic of this study is the characterization of trapping properties of recovered oxides and more particularly of 'Unibond' material carried out with a new fabrication process: the 'smart-cut' process. This work is divided into three parts: - study with one carrier: this case is limited to low radiation doses where is only observed holes trapping. The evolution of the physical and chemical properties of the 'Unibond' material recovered oxide has been revealed, this evolution being due to the fabrication process. - Study with two carriers: in this case, there is trapping of holes and electrons. This type of trapping is observed in the case of strong radiation doses. A new type of electrons traps has been identified with the 'Unibond' material oxide. The transport and the trapping of holes and electrons have been studied in the case of transient phenomena created by short radiative pulses. This study has been carried out using a new measurement method. - Study with three carriers: here are added to holes and electrons the protons introduced in the recovered oxide by the annealing under hydrogen. These protons are movable when they are submitted to the effect of an electric field and they induce a memory effect according to their position in the oxide. These different works show that the 'Unibond' material is a very good solution for the future development of S.O.I. (author) [fr

Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

Energy Technology Data Exchange (ETDEWEB)

Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

2009-06-10

We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

Science.gov (United States)

Skalare, Anders; Stern, Jeffrey; Bumble, Bruce; Maiwald, Frank

2005-01-01

A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

Directory of Open Access Journals (Sweden)

Jiayang Wu

2018-04-01

Full Text Available We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI nanowires implemented by cascaded Sagnac loop reflector (CSLR resonators. We investigate mode splitting in these standing-wave (SW resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

Performance analysis of SOI MOSFET with rectangular recessed channel

Science.gov (United States)

Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

2016-03-01

In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

Energy Technology Data Exchange (ETDEWEB)

Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-06-20

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Gadolinium oxide coated fully depleted silicon-on-insulator transistors for thermal neutron dosimetry

Energy Technology Data Exchange (ETDEWEB)

Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu; Gouker, Pascale M.

2013-09-01

Fully depleted silicon-on-insulator transistors coated with gadolinium oxide are shown to be effective thermal neutron dosimeters. The theoretical neutron detection efficiency is calculated to be higher for Gd{sub 2}O{sub 3} than for other practical converter materials. Proof-of-concept dosimeter devices were fabricated and tested during thermal neutron irradiation. The transistor current changes linearly with neutron dose, consistent with increasing positive charge in the SOI buried oxide layer generated by ionization from high energy {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. The measured neutron sensitivity is approximately 1/6 the maximum theoretical value, possibly due to electron–hole recombination or conversion electron loss in interconnect wiring above the transistors. -- Highlights: • A novel Gd{sub 2}O{sub 3} coated FDSOI MOSFET thermal neutron dosimeter is presented. • Dosimeter can detect charges generated from {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. • Measured neutron sensitivity is comparable to that calculated theoretically. • Dosimeter requires zero power during operation, enabling new application areas.

Performance analysis of SOI MOSFET with rectangular recessed channel

International Nuclear Information System (INIS)

Singh, M; Mishra, G P; Mishra, S; Mohanty, S S

2016-01-01

In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed. (paper)

Broadband Silicon-On-Insulator directional couplers using a combination of straight and curved waveguide sections.

Science.gov (United States)

Chen, George F R; Ong, Jun Rong; Ang, Thomas Y L; Lim, Soon Thor; Png, Ching Eng; Tan, Dawn T H

2017-08-03

Broadband Silicon-On-Insulator (SOI) directional couplers are designed based on a combination of curved and straight coupled waveguide sections. A design methodology based on the transfer matrix method (TMM) is used to determine the required coupler section lengths, radii, and waveguide cross-sections. A 50/50 power splitter with a measured bandwidth of 88 nm is designed and fabricated, with a device footprint of 20 μm × 3 μm. In addition, a balanced Mach-Zehnder interferometer is fabricated showing an extinction ratio of >16 dB over 100 nm of bandwidth.

Ultrathin silicon oxynitride layer on GaN for dangling-bond-free GaN/insulator interface.

Science.gov (United States)

Nishio, Kengo; Yayama, Tomoe; Miyazaki, Takehide; Taoka, Noriyuki; Shimizu, Mitsuaki

2018-01-23

Despite the scientific and technological importance of removing interface dangling bonds, even an ideal model of a dangling-bond-free interface between GaN and an insulator has not been known. The formation of an atomically thin ordered buffer layer between crystalline GaN and amorphous SiO 2 would be a key to synthesize a dangling-bond-free GaN/SiO 2 interface. Here, we predict that a silicon oxynitride (Si 4 O 5 N 3 ) layer can epitaxially grow on a GaN(0001) surface without creating dangling bonds at the interface. Our ab initio calculations show that the GaN/Si 4 O 5 N 3 structure is more stable than silicon-oxide-terminated GaN(0001) surfaces. The electronic properties of the GaN/Si 4 O 5 N 3 structure can be tuned by modifying the chemical components near the interface. We also propose a possible approach to experimentally synthesize the GaN/Si 4 O 5 N 3 structure.

Formation and properties of the buried isolating silicon-dioxide layer in double-layer “porous silicon-on-insulator” structures

Energy Technology Data Exchange (ETDEWEB)

Bolotov, V. V.; Knyazev, E. V.; Ponomareva, I. V.; Kan, V. E., E-mail: kan@obisp.oscsbras.ru; Davletkildeev, N. A.; Ivlev, K. E.; Roslikov, V. E. [Russian Academy of Sciences, Omsk Scientific Center, Siberian Branch (Russian Federation)

2017-01-15

The oxidation of mesoporous silicon in a double-layer “macroporous silicon–mesoporous silicon” structure is studied. The morphology and dielectric properties of the buried insulating layer are investigated using electron microscopy, ellipsometry, and electrical measurements. Specific defects (so-called spikes) are revealed between the oxidized macropore walls in macroporous silicon and the oxidation crossing fronts in mesoporous silicon. It is found that, at an initial porosity of mesoporous silicon of 60%, three-stage thermal oxidation leads to the formation of buried silicon-dioxide layers with an electric-field breakdown strength of E{sub br} ~ 10{sup 4}–10{sup 5} V/cm. Multilayered “porous silicon-on-insulator” structures are shown to be promising for integrated chemical micro- and nanosensors.

Ultra compact triplexing filters based on SOI nanowire AWGs

Science.gov (United States)

Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

2011-04-01

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

International Nuclear Information System (INIS)

Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi

2012-01-01

The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)

Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted Silicon-on-Insulator Technology

International Nuclear Information System (INIS)

Servanton, G; Clement, L; Lepinay, K; Lorut, F; Pantel, R; Pofelski, A; Bicais, N

2013-01-01

The growing demand for wireless multimedia applications (smartphones, tablets, digital cameras) requires the development of devices combining both high speed performances and low power consumption. A recent technological breakthrough making a good compromise between these two antagonist conditions has been proposed: the 28-14nm CMOS transistor generations based on a fully-depleted Silicon-on-Insulator (FD-SOI) performed on a thin Si film of 5-6nm. In this paper, we propose to review the TEM characterization challenges that are essential for the development of extremely power-efficient System on Chip (SoC)

Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

Science.gov (United States)

Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

2014-11-25

Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

Science.gov (United States)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

International Nuclear Information System (INIS)

Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

2017-01-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

Science.gov (United States)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Optical signal processing by silicon photonics

CERN Document Server

Ahmed, Jameel; Adeel, Freeha; Hussain, Ashiq

2014-01-01

The main objective of this book is to make respective graduate students understand the nonlinear effects inside SOI waveguide and possible applications of SOI waveguides in this emerging research area of optical fibre communication. This book focuses on achieving successful optical frequency shifting by Four Wave Mixing (FWM) in silicon-on-insulator (SOI) waveguide by exploiting a nonlinear phenomenon.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

Science.gov (United States)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

Science.gov (United States)

Liu, Yongxun; Tanaka, Hiroyuki; Umeyama, Norio; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2018-06-01

P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular silicon-on-insulator (SOI) diaphragms using a cost-effective minimal-fab process, and their electrical characteristics have been systematically investigated before and after the SOI diaphragm formation. It was found that almost the same subthreshold slope (S-slope) and threshold voltage (V t) are observed in the fabricated PMOSFETs before and after the SOI diaphragm formation, and they are independent of the channel direction. On the other hand, significant variations in drain current were observed in the fabricated PMOSFETs with the 〈110〉 channel direction after the SOI diaphragm formation owing to the residual mechanical stress-induced piezoresistive effect. It was also confirmed that electrical characteristics of the fabricated PMOSFETs with the 〈100〉 channel direction are almost the same before and after the SOI diaphragm formation, i.e., not sensitive to the mechanical stress. Moreover, the drain current variations at different directions of mechanical stress and current flow were systematically investigated and discussed.

Ultra compact triplexing filters based on SOI nanowire AWGs

Energy Technology Data Exchange (ETDEWEB)

Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei, E-mail: junming@red.semi.ac.cn [State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2011-04-15

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

Ultra compact triplexing filters based on SOI nanowire AWGs

International Nuclear Information System (INIS)

Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei

2011-01-01

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

Al transmon qubits on silicon-on-insulator for quantum device integration

Science.gov (United States)

Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

2017-07-01

We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

Amorphous silicon as high index photonic material

Science.gov (United States)

Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

2009-05-01

Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

Characterization of SOI monolithic detector system

Science.gov (United States)

Álvarez-Rengifo, P. L.; Soung Yee, L.; Martin, E.; Cortina, E.; Ferrer, C.

2013-12-01

A monolithic active pixel sensor for charged particle tracking was developed. This research is performed within the framework of an R&D project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology) whose aim is to evaluate the feasibility of developing a Monolithic Active Pixel Sensor (MAPS) with Silicon-on-Insulator (SOI) technology. Two chips were fabricated: TRAPPISTe-1 and TRAPPISTe-2. TRAPPISTe-1 was produced at the WINFAB facility at the Université catholique de Louvain (UCL), Belgium, in a 2 μm fully depleted (FD-SOI) CMOS process. TRAPPISTe-2 was fabricated with the LAPIS 0.2 μm FD-SOI CMOS process. The electrical characterization on single transistor test structures and of the electronic readout for the TRAPPISTe series of monolithic pixel detectors was carried out. The behavior of the prototypes’ electronics as a function of the back voltage was studied. Results showed that both readout circuits exhibited sensitivity to the back voltage. Despite this unwanted secondary effect, the responses of TRAPPISTe-2 amplifiers can be improved by a variation in the circuit parameters.

Investigation of the stability of polysilicon layers in SOI-structures under irradiation by electrons and hard magnetic field influence

Directory of Open Access Journals (Sweden)

Khoverko Yu. N.

2010-10-01

Full Text Available The properties of recrystallized polysilicon on insulator layers of p-type conductive SOI-structures with different carrier concentration irradiated with high-energy electrons flow about 1017 сm–2 in temperature range 4,2—300 К and high magnetic fields were investigated. It was found that heavily doped laser recrystallized polysilicon on insulator layers show its radiation resistance under irradiation with high-energy electrons and magnetoresistance of such material remains quite low in magnetic field about 14 T does not exceed 1—2%. Such qulity can be applied in designing of microelectronic sensors of mechanical values operable in hard conditions of exploitation.

Method of forming buried oxide layers in silicon

Science.gov (United States)

Sadana, Devendra Kumar; Holland, Orin Wayne

2000-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Thin NbN film structures on SOI for SNSPD

Energy Technology Data Exchange (ETDEWEB)

Il' in, Konstantin; Kurz, Stephan; Henrich, Dagmar; Hofherr, Matthias; Siegel, Michael [IMS, KIT, Karlsruhe (Germany); Semenov, Alexei; Huebers, Heinz-Wilhelm [DLR, Berlin (Germany)

2012-07-01

Superconducting Nanowire Single-Photon Detectors (SNSPD) made from ultra-thin NbN films on sapphire demonstrate almost 100% intrinsic detection efficiency (DE). However the system DE values is less than 10% mostly limited by a very low absorptance of NbN films thinner than 5 nm. Integration of SNSPD in Si photonic circuit is a promising way to overcome this problem. We present results on optimization of technology of thin NbN film nanostructures on SOI (Silicon on Insulator) substrate used in Si photonics technology. Superconducting and normal state properties of these structures important for SNSPD development are presented and discussed.

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

International Nuclear Information System (INIS)

Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

2011-01-01

An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

International Nuclear Information System (INIS)

Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

2013-01-01

A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

Science.gov (United States)

Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

2000-08-01

Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

Defect formation and recrystallization in the silicon on sapphire films under Si{sup +} irradiation

Energy Technology Data Exchange (ETDEWEB)

Shemukhin, A.A., E-mail: shemuhin@gmail.com [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Nazarov, A.V.; Balakshin, Yu. V. [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Chernysh, V.S. [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Faculty of Physics, Lomonosov Moscow State University, Moscow (Russian Federation)

2015-07-01

Silicon-on-sapphire (SOS) is one of the most promising silicon-on-insulator (SOI) technologies. SOS structures are widely used in microelectronics, but to meet modern requirements the silicon layer should be 100 nm thick or less. The problem is in amount of damage in the interface layer, which decreases the quality of the produced devices. In order to improve the crystalline structure quality SOS samples with 300 nm silicon layers were implanted with Si{sup +} ions with energies in the range from 180 up to 230 keV with fluences in the range from 10{sup 14} up to 5 × 10{sup 15} cm{sup −2} at 0 °C. The crystalline structure of the samples was studied with RBS and the interface layer was studied with SIMS after subsequent annealing. It has been found out that to obtain silicon films with high lattice quality it is necessary to damage the sapphire lattice near the silicon–sapphire interface. Complete destruction of the strongly defected area and subsequent recrystallization depends on the energy of implanted ions and the substrate temperature. No significant mixing in the interface layer was observed with the SIMS.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

International Nuclear Information System (INIS)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

1998-01-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

Influence of edge effects on single event upset susceptibility of SOI SRAMs

International Nuclear Information System (INIS)

Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

2015-01-01

An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

Electronics and Sensor Study with the OKI SOI process

CERN Document Server

Arai, Yasuo

2007-01-01

While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI proces...

Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

DEFF Research Database (Denmark)

Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

2016-01-01

: off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize...

An analysis of radiation effects on electronics and soi-mos devices as an alternative

International Nuclear Information System (INIS)

Ikraiam, F. A.

2013-01-01

The effects of radiation on semiconductors and electronic components are analyzed. The performance of such circuitry depends upon the reliability of electronic devices where electronic components will be unavoidably exposed to radiation. This exposure can be detrimental or even fatal to the expected function of the devices. Single event effects (SEE), in particular, which lead to sudden device or system failure and total dose effects can reduce the lifetime of electronic devices in such systems are discussed. Silicon-on-insulator (SOI) technology is introduced as an alternative for radiation-hardened devices. I-V Characteristics Curves for SOI-MOS devices subjected to a different total radiation doses are illustrated. In addition, properties of some semiconductor materials such as diamond, diamond-like carbon films, SiC, GaP, and AlGaN/GaN are compared with those of SOI devices. The recognition of the potential usefulness of SOI-MOS semiconductor materials for harsh environments is discussed. A summary of radiation effects, impacts and mitigation techniques is also presented. (authors)

Superconducting nanowire single-photon detectors (SNSPDs) on SOI for near-infrared range

Energy Technology Data Exchange (ETDEWEB)

Trojan, Philipp; Il' in, Konstantin; Henrich, Dagmar; Hofherr, Matthias; Doerner, Steffen; Siegel, Michael [Institut fuer Mikro- und Nanoelektronische Systeme (IMS), Karlsruher Institut fuer Technologie (KIT) (Germany); Semenov, Alexey [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Huebers, Heinz-Wilhelm [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Institut fuer Optik und Atomare Physik, Technische Universitaet Berlin (Germany)

2013-07-01

Superconducting nanowire single-photon detectors are promising devices for photon detectors with high count rates, low dark count rates and low dead times. At wavelengths beyond the visible range, the detection efficiency of today's SNSPDs drops significantly. Moreover, the low absorption in ultra-thin detector films is a limiting factor over the entire spectral range. Solving this problem requires approaches for an enhancement of the absorption range in feeding the light to the detector element. A possibility to obtain a better absorption is the use of multilayer substrate materials for photonic waveguide structures. We present results on development of superconducting nanowire single-photon detectors made from niobium nitride on silicon-on-insulator (SOI) multilayer substrates. Optical and superconducting properties of SNSPDs on SOI will be discussed and compared with the characteristics of detectors on common substrates.

A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

Science.gov (United States)

Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

2015-09-01

In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

International Nuclear Information System (INIS)

Li Lei; Zhou Wanting; Liu Huihua

2012-01-01

In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 μm technology. (author)

Total dose radiation effects of pressure sensors fabricated on uni-bond-SOI materials

International Nuclear Information System (INIS)

Zhu Shiyang; Huang Yiping; Wang Jin; Li Anzhen; Shen Shaoqun; Bao Minhang

2001-01-01

Piezoresistive pressure sensors with a twin-island structure were successfully fabricated using high quality Uni-bond-SOI (On Insulator) materials. Since the piezoresistors were structured by the single crystalline silicon overlayer of the SOI wafer and were totally isolated by the buried SiO 2 , the sensors are radiation-hard. The sensitivity and the linearity of the pressure sensors keep their original values after being irradiated by 60 Co γ-rays up to 2.3 x 10 4 Gy(H 2 O). However, the offset voltage of the sensor has a slight drift, increasing with the radiation dose. The absolute value of the offset voltage deviation depends on the pressure sensor itself. For comparison, corresponding polysilicon pressure sensors were fabricated using the similar process and irradiated at the same condition

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

Science.gov (United States)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

CERN Multimedia

2002-01-01

% RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

Science.gov (United States)

Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

2009-03-01

The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

Science.gov (United States)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Vertical integration of high-Q silicon nitride microresonators into silicon-on-insulator platform.

Science.gov (United States)

Li, Qing; Eftekhar, Ali A; Sodagar, Majid; Xia, Zhixuan; Atabaki, Amir H; Adibi, Ali

2013-07-29

We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

Science.gov (United States)

Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

2016-07-01

We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

arXiv Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

CERN Document Server

INSPIRE-00541780; Cindro, V.; Gorišek, A.; Hemperek, T.; Kishishita, T.; Kramberger, G.; Krüger, H.; Mandić, I.; Mikuž, M.; Wermes, N.; Zavrtanik, M.

2017-10-25

Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1x10e16 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5x10e14 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The r...

A novel SOI pressure sensor for high temperature application

International Nuclear Information System (INIS)

Li Sainan; Liang Ting; Wang Wei; Hong Yingping; Zheng Tingli; Xiong Jijun

2015-01-01

The silicon on insulator (SOI) high temperature pressure sensor is a novel pressure sensor with high-performance and high-quality. A structure of a SOI high-temperature pressure sensor is presented in this paper. The key factors including doping concentration and power are analyzed. The process of the sensor is designed with the critical process parameters set appropriately. The test result at room temperature and high temperature shows that nonlinear error below is 0.1%, and hysteresis is less than 0.5%. High temperature measuring results show that the sensor can be used for from room temperature to 350 °C in harsh environments. It offers a reference for the development of high temperature piezoresistive pressure sensors. (semiconductor devices)

Silicon based nanogap device for investigating electronic transport through 12 nm long oligomers

DEFF Research Database (Denmark)

Strobel, S.; Albert, E.; Csaba, G.

2009-01-01

We have fabricated vertical nanogap electrode devices based on Silicon-on-Insulator (SOI) substrates for investigating the electronic transport properties of long, conjugated molecular wires. Our nanogap electrode devices comprise smooth metallic contact pairs situated at the sidewall of an SOI s...

FinFET and UTBB for RF SOI communication systems

Science.gov (United States)

Raskin, Jean-Pierre

2016-11-01

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

Process Optimization for Monolithic Integration of Piezoresistive Pressure Sensor and MOSFET Amplifier with SOI Approach

International Nuclear Information System (INIS)

Kumar, V Vinoth; Dasgupta, A; Bhat, K N; KNatarajan

2006-01-01

In this paper we present the design and process optimization for fabricating piezoresitive pressure sensor and MOSFET Differential Amplifier simultaneously on the same chip. Silicon On Insulator approach has been used for realizing the membrane as well as the electronics on the same chip. The amplifier circuit has been configured in the common source connection and it has been designed with PSPICE simulation to achieve a voltage gain of about 5. In the initial set of experiments the Pressure sensor and the amplifier were fabricated on separate chips to optimize the process steps and tested in the hybrid mode. In the next set of experiments, SOI wafer having the SOI layer thickness of about 11 microns was used for realizing the membrane by anisotropic etching from the backside. The piezo-resistive pressure sensor was realized on this membrane by connecting the polysilicon resistors in the form of a Wheatstone bridge. The MOSFET source follower amplifier was also fabricated on the same SOI wafer by tailoring the process steps to suit the requirement of simultaneous fabrication of piezoresistors and the amplifier for achieving MOSFET Integrated Pressure Sensor. Reproducible results have been achieved on the SOI wafers, with the process steps developed in the laboratory. Sensitivity of 270 mV /Bar/10V, with the on chip amplifier gain of 4.5, has been achieved with this process

Determination of the quasi-TE mode (in-plane) graphene linear absorption coefficient via integration with silicon-on-insulator racetrack cavity resonators.

Science.gov (United States)

Crowe, Iain F; Clark, Nicholas; Hussein, Siham; Towlson, Brian; Whittaker, Eric; Milosevic, Milan M; Gardes, Frederic Y; Mashanovich, Goran Z; Halsall, Matthew P; Vijayaraghaven, Aravind

2014-07-28

We examine the near-IR light-matter interaction for graphene integrated cavity ring resonators based on silicon-on-insulator (SOI) race-track waveguides. Fitting of the cavity resonances from quasi-TE mode transmission spectra reveal the real part of the effective refractive index for graphene, n(eff) = 2.23 ± 0.02 and linear absorption coefficient, α(gTE) = 0.11 ± 0.01dBμm(-1). The evanescent nature of the guided mode coupling to graphene at resonance depends strongly on the height of the graphene above the cavity, which places limits on the cavity length for optical sensing applications.

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

International Nuclear Information System (INIS)

Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji

2012-01-01

An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

International Nuclear Information System (INIS)

Huang Pengcheng; Chen Shuming; Chen Jianjun

2016-01-01

In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout. (paper)

Test-beam results of a SOI pixel detector prototype

CERN Document Server

Bugiel, Roma; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Idzik, Marek; Kapusta, P; Kucewicz, Wojciech; Munker, Ruth Magdalena; Nurnberg, Andreas Matthias

2018-01-01

This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 μm thick high-resistivity float- zone n-type (FZ-n) wafer. The pixel size is 30 μm × 30 μm and its readout uses a source- follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and η-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 μm.

Optical interconnects based on VCSELs and low-loss silicon photonics

Science.gov (United States)

Aalto, Timo; Harjanne, Mikko; Karppinen, Mikko; Cherchi, Matteo; Sitomaniemi, Aila; Ollila, Jyrki; Malacarne, Antonio; Neumeyr, Christian

2018-02-01

Silicon photonics with micron-scale Si waveguides offers most of the benefits of submicron SOI technology while avoiding most of its limitations. In particular, thick silicon-on-insulator (SOI) waveguides offer 0.1 dB/cm propagation loss, polarization independency, broadband single-mode (SM) operation from 1.2 to >4 µm wavelength and ability to transmit high optical powers (>1 W). Here we describe the feasibility of Thick-SOI technology for advanced optical interconnects. With 12 μm SOI waveguides we demonstrate efficient coupling between standard single-mode fibers, vertical-cavity surface-emitting lasers (VCSELs) and photodetectors (PDs), as well as wavelength multiplexing in small footprint. Discrete VCSELs and PDs already support 28 Gb/s on-off keying (OOK), which shows a path towards 50-100 Gb/s bandwidth per wavelength by using more advanced modulation formats like PAM4. Directly modulated VCSELs enable very power-efficient optical interconnects for up to 40 km distance. Furthermore, with 3 μm SOI waveguides we demonstrate extremely dense and low-loss integration of numerous optical functions, such as multiplexers, filters, switches and delay lines. Also polarization independent and athermal operation is demonstrated. The latter is achieved by using short polymer waveguides to compensate for the thermo-optic effect in silicon. New concepts for isolator integration and polarization rotation are also explained.

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

Science.gov (United States)

Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

2018-02-01

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

Silicon-on-insulator based nanopore cavity arrays for lipid membrane investigation.

Science.gov (United States)

Buchholz, K; Tinazli, A; Kleefen, A; Dorfner, D; Pedone, D; Rant, U; Tampé, R; Abstreiter, G; Tornow, M

2008-11-05

We present the fabrication and characterization of nanopore microcavities for the investigation of transport processes in suspended lipid membranes. The cavities are situated below the surface of silicon-on-insulator (SOI) substrates. Single cavities and large area arrays were prepared using high resolution electron-beam lithography in combination with reactive ion etching (RIE) and wet chemical sacrificial underetching. The locally separated compartments have a circular shape and allow the enclosure of picoliter volume aqueous solutions. They are sealed at their top by a 250 nm thin Si membrane featuring pores with diameters from 2 µm down to 220 nm. The Si surface exhibits excellent smoothness and homogeneity as verified by AFM analysis. As biophysical test system we deposited lipid membranes by vesicle fusion, and demonstrated their fluid-like properties by fluorescence recovery after photobleaching. As clearly indicated by AFM measurements in aqueous buffer solution, intact lipid membranes successfully spanned the pores. The nanopore cavity arrays have potential applications in diagnostics and pharmaceutical research on transmembrane proteins.

Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

Science.gov (United States)

Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2014-11-17

A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a silicon photonics technology.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca

2015-09-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

2015-01-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

Energy Technology Data Exchange (ETDEWEB)

DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

1999-11-01

Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

A MEMS SOI-based piezoresistive fluid flow sensor

Science.gov (United States)

Tian, B.; Li, H. F.; Yang, H.; Song, D. L.; Bai, X. W.; Zhao, Y. L.

2018-02-01

In this paper, a SOI (silicon-on-insulator)-based piezoresistive fluid flow sensor is presented; the presented flow sensor mainly consists of a nylon sensing head, stainless steel cantilever beam, SOI sensor chip, printed circuit board, half-cylinder gasket, and stainless steel shell. The working principle of the sensor and some detailed contrastive analysis about the sensor structure were introduced since the nylon sensing head and stainless steel cantilever beam have distinct influence on the sensor performance; the structure of nylon sensing head and stainless steel cantilever beam is also discussed. The SOI sensor chip was fabricated using micro-electromechanical systems technologies, such as reactive ion etching and low pressure chemical vapor deposition. The designed fluid sensor was packaged and tested; a calibration installation system was purposely designed for the sensor experiment. The testing results indicated that the output voltage of the sensor is proportional to the square of the fluid flow velocity, which is coincident with the theoretical derivation. The tested sensitivity of the sensor is 3.91 × 10-4 V ms2/kg.

LORINE: Neutron emission Locator by SOI detectors

Energy Technology Data Exchange (ETDEWEB)

Hamrita, H.; Kondrasovs, V.; Borbotte, J. M.; Normand, S. [CEA, LIST, Laboratoire Capteurs et Architectures Electronique, F-91191 Gif-sur-Yvette Cedex (France); Saurel, N. [CEA, DAM, VALDUC, F-21120 Is sur Tille (France)

2009-07-01

The aim of this work is to develop a fast Neutron Emission Locator based on silicon on Insulator detector (LORINE). This locator can be used in the presence of significant flux of gamma radiation. LORINE was developed to locate areas containing a significant amount of actinide during the dismantling operations of equipment. From the results obtained in laboratory, we have proposed the prototype of neutron emission locator as follows: the developed design consists of 5 SOI (Silicon-on-insulator) detectors (1*1 cm{sup 2}) with their charge preamplifiers and their respective converters. All are installed on 5 faces of a boron polyethylene cube (5*5*5 cm{sup 3}). This cube plays the role of neutron shielding between the several detectors. The design must be so compact for use in glove boxes. An electronic card based on micro-controller has been made to control sensors and to send the necessary information to the computer. Location of fast neutron sources does not yet exist in a so compact design and it can be operated in the presence of very important gamma radiation flux

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

Science.gov (United States)

Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

2018-04-01

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

An SEU resistant 256K SOI SRAM

Science.gov (United States)

Hite, L. R.; Lu, H.; Houston, T. W.; Hurta, D. S.; Bailey, W. E.

1992-12-01

A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition.

Design, fabrication and characterization of a two-step released silicon dioxide piezoresistive microcantilever immunosensor

International Nuclear Information System (INIS)

Zhou, Youzheng; Wang, Zheyao; Wang, Chaonan; Ruan, Wenzhou; Liu, Litian

2009-01-01

This paper presents the design, fabrication and characterization of a silicon dioxide piezoresistive microcantilever immunosensor fabricated on silicon-on-insulator (SOI) wafers. The microcantilever consists of two strips of single crystalline silicon piezoresistors sandwiched in between two silicon dioxide layers. A theoretical model for the laminated microcantilever with a discontinuous layer is deduced using classic laminated beam theory. A two-step release method combining anisotropic and isotropic etching is developed to suspend the microcantilever, and the fabrication results show an excellent yield. The residual stress-induced free bending of the microcantilever and the stress caused by self-heating of the piezoresistors are discussed. The microcantilever sensor is characterized as an immunosensor using specific binding of antigen and antibody. These methods and some conclusions are also applicable to the development of other piezoresistive sensors that use laminated structures

Characteristics of MOSFETs fabricated in silicon-on-insulator material formed by high-dose oxygen ion implantation

International Nuclear Information System (INIS)

Lam, H.W.; Pinizzotto, R.F.; Yuan, H.T.; Bellavance, D.W.

1981-01-01

By implanting a dose of 6 x 10 17 cm -2 of 32 O 2 + at 300 keV into a silicon wafer, a buried oxide layer is formed. Crystallinity of the silicon layer above the buried oxide layer is maintained by applying a high (>200 0 C) substrate temperature during the ion implantation process. A two-step anneal cycle is found to be adequate to form the insulating buried oxide layer and to repair the implantation damage in the silicon layer on top of the buried oxide. A surface electron mobility as high as 710 cm 2 /Vs has been measured in n-channel MOSFETs fabricated in a 0.5 μm-thick epitaxial layer grown on the buried oxide wafer. A minimum subthreshold current of about 10 pA per micron of channel width at Vsub(DS)=2 V has been measured. (author)

Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2016-10-01

For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

Nanoscale contacts to organic molecules based on layered semiconductor substrates

Energy Technology Data Exchange (ETDEWEB)

Strobel, Sebastian

2009-06-15

This work reports on the integration of organic molecules as nanoelectronic device units on semiconductor substrates. Two novel preparation methods for sub-10-nm separated metal electrodes are presented using current microelectronics process technology. The first method utilises AlGaAs/GaAs heterostructures grown by molecular beam epitaxy (MBE) as mold to create planar metal electrodes employing a newly developed, high resolution nanotransfer printing (nTP) process. The second method uses commercially available Silicon-on-Insulator (SOI) substrates as base material for the fabrication of nanogap electrode devices. This sandwich-like material stack consists of a silicon substrate, a thin silicon oxide layer, and a capping silicon layer on top. Electronic transport measurements verified their excellent electrical properties at liquid helium temperatures. Specifically tailored nanogap devices featured an electrode insulation in the GW range even up to room temperature as well as within aqueous electrolyte solution. Finally, the well defined layer architecture facilitated the fabrication of electrodes with gap separations below-10-nm to be directly bridged by molecules. Approximately 12-nm-long conjugated molecules with extended -electron system were assembled onto the devices from solution. A large conductance gap was observed with a steep increase in current at a bias voltage of V{sub T}{approx}{+-}1.5 V. Theoretical calculations based on density functional theory and non-equilibrium Green's function formalism confirmed the measured non-linear IV-characteristics qualitatively and lead to the conclusion that the conductance gap mainly originates from the oxygen containing linker. Temperature dependent investigations of the conductance indicated a hopping charge transport mechanism through the central part of the molecule for bias voltages near but below V{sub T}. (orig.)

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

International Nuclear Information System (INIS)

Wang Zhigang; Zhang Bo; Li Zhaoji

2013-01-01

A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

Science.gov (United States)

Pavanello, Marcelo Antonio; de Souza, Michelly; Ribeiro, Thales Augusto; Martino, João Antonio; Flandre, Denis

2016-11-01

This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

A pile-up phenomenon during arsenic diffusion in silicon-on-insulator structures formed by oxygen implantation

Science.gov (United States)

Normand, P.; Tsoukalas, D.; Guillemot, N.; Chenevier, P.

1989-10-01

Arsenic diffusion in silicon-on-insulator formed by deep oxygen implantation is studied by secondary ion mass spectroscopy and speading resistance measurements. An enhanced diffusivity as well as a pile-up phenomenon are observed in the thin silicon layer. The McNabb and Foster equations [Trans. TMS-AIME 22, 618 (1963)] for diffusion with trapping are solved in order to simulate this last effect.

Design, fabrication and characterisation of advanced substrate crosstalk suppression structures in silicon on insulator substrates with buried ground planes (GPSOI)

International Nuclear Information System (INIS)

Stefanou, Stefanos

2002-07-01

Substrate crosstalk or coupling has been acknowledged to be a limiting factor in mixed signal RF integration. Although high levels of integration and high frequencies of operation are desirable for mixed mode RF and microwave circuits, they make substrate crosstalk more pronounced and may lead to circuit performance degradation. High signal isolation is dictated by requirements for low power dissipation, reduced number of components and lower integration costs for feasible system-on-chip (SoC) solutions. Substrate crosstalk suppression in ground plane silicon-on-insulator (GPSOI) substrates is investigated in this thesis. Test structures are designed and fabricated on SOI substrates with a buried WSi 2 plane that is connected to ground; hence it is called a ground plane. A Faraday cage structure that exhibits very high degrees of signal isolation is presented and compared to other SOI isolation schemes. The Faraday cage structure is shown to achieve 20 dB increased isolation in the frequency range of 0.5-50 GHz compared to published data for high resistivity (200 Ωcm) thin film SOI substrates with no ground planes, but where capacitive guard rings were used. The measurement results are analysed with the aid of planar electromagnetic simulators and compact lumped element models of all the fabricated test structures are developed. The accuracy of the lumped models is validated against experimental measurements. (author)

Silicon Nanowires for All-Optical Signal Processing in Optical Communication

DEFF Research Database (Denmark)

Pu, Minhao; Hu, Hao; Ji, Hua

2012-01-01

Silicon (Si), the second most abundant element on earth, has dominated in microelectronics for many decades. It can also be used for photonic devices due to its transparency in the range of optical telecom wavelengths which will enable a platform for a monolithic integration of optics...... and microelectronics. Silicon photonic nanowire waveguides fabricated on silicon-on-insulator (SOI) substrates are crucial elements in nano-photonic integrated circuits. The strong light confinement in nanowires induced by high index contrast SOI material enhances the nonlinear effects in the silicon nanowire core...... such as four-wave mixing (FWM) which is an imperative process for optical signal processing. Since the current mature silicon fabrication technology enables a precise dimension control on nanowires, dispersion engineering can be performed by tailoring nanowire dimensions to realize an efficient nonlinear...

Effect of TMAH Etching Duration on the Formation of Silicon Nano wire Transistor Patterned by AFM Nano lithography

International Nuclear Information System (INIS)

Hutagalung, S.D.; Lew, K.C.

2012-01-01

Atomic force microscopy (AFM) lithography was applied to produce nano scale pattern for silicon nano wire transistor fabrication. This technique takes advantage of imaging facility of AFM and the ability of probe movement controlling over the sample surface to create nano patterns. A conductive AFM tip was used to grow the silicon oxide nano patterns on silicon on insulator (SOI) wafer. The applied tip-sample voltage and writing speed were well controlled in order to form pre-designed silicon oxide nano wire transistor structures. The effect of tetra methyl ammonium hydroxide (TMAH) etching duration on the oxide covered silicon nano wire transistor structure has been investigated. A completed silicon nano wire transistor was obtained by removing the oxide layer via hydrofluoric acid etching process. The fabricated silicon nano wire transistor consists of a silicon nano wire that acts as a channel with source and drain pads. A lateral gate pad with a nano wire head was fabricated very close to the channel in the formation of transistor structures. (author)

Analyses of the radiation-caused characteristics change in SOI MOSFETs using field shield isolation

International Nuclear Information System (INIS)

Hirano, Yuuichi; Maeda, Shigeru; Fernandez, Warren; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Maegawa, Shigeto; Nishimura, Tadashi

1999-01-01

Reliability against radiation ia an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long regime channel. In transistors with a channel length of 0.18μm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0μm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment. (author)

BUSFET -- A radiation-hardened SOI transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

Performance of the INTPIX6 SOI pixel detector

International Nuclear Information System (INIS)

Arai, Y.; Miyoshi, T.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Turala, M.; Kucewicz, W.

2017-01-01

Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ  m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241 Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e − . The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e − . The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

Performance of the INTPIX6 SOI pixel detector

Science.gov (United States)

Arai, Y.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Kucewicz, W.; Miyoshi, T.; Turala, M.

2017-01-01

Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e-. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e-. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

International Nuclear Information System (INIS)

Patil, Ganesh C; Qureshi, S

2011-01-01

In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB

An Ultra-Efficient Nonlinear Platform: AlGaAs-On-Insulator

DEFF Research Database (Denmark)

Pu, Minhao; Ottaviano, Luisa; Semenova, Elizaveta

The combination of nonlinear and integrated photonics enables applications including optical signal processing, multi-wavelength lasers, metrology, spectroscopy, and quantum information science. Silicon-on-insulator (SOI) has emerged as a promising platform [1, 2] due to its high material...... nonlinearity and its compatibility with the CMOS industry. However, silicon suffers two-photon absorption (TPA) in the telecommunication wavelength band around 1.55 µm, which hampers its applications. Different platforms have been proposed to avoid TPA in the telecom wavelength range such as Si3N4 and Hydex [3...... a nonlinear index (n2) on the order of 10−17 W/m2 and a high refractive index (n ≈3.3), a large transparency window (from near- to mid-infrared), and the ability to engineer the material bandgap to mitigate TPA [5]. In this presentation, we introduce AlGaAson-insulator (AlGaAsOI) platform which combines both...

Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

International Nuclear Information System (INIS)

Destefanis, V; Huguenin, J L; Samson, M P; Morand, Y; Arvet, C; Monfray, S; Skotnicki, T; Hartmann, J M; Delaye, V; Boulitreau, P; Brianceau, P; Gautier, P

2010-01-01

The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 °C in windows of patterned wafers are rough, we have first of all studied the 600 °C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 °C down to 600 °C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 °C and 725 °C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 °C on (1 0 0) or at 600 °C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5–3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were

Effects of size and defects on the elasticity of silicon nanocantilevers

International Nuclear Information System (INIS)

Sadeghian, Hamed; Goosen, Johannes F L; Van Keulen, Fred; Yang, Chung-Kai; Bossche, Andre; French, Paddy J; Staufer, Urs

2010-01-01

The size-dependent elastic behavior of silicon nanocantilevers and nanowires, specifically the effective Young's modulus, has been determined by experimental measurements and theoretical investigations. The size dependence becomes more significant as the devices scale down from micro- to nano-dimensions, which has mainly been attributed to surface effects. However, discrepancies between experimental measurements and computational investigations show that there could be other influences besides surface effects. In this paper, we try to determine to what extent the surface effects, such as surface stress, surface elasticity, surface contamination and native oxide layers, influence the effective Young's modulus of silicon nanocantilevers. For this purpose, silicon cantilevers were fabricated in the top device layer of silicon on insulator (SOI) wafers, which were thinned down to 14 nm. The effective Young's modulus was extracted with the electrostatic pull-in instability method, recently developed by the authors (H Sadeghian et al 2009 Appl. Phys. Lett. 94 221903). In this work, the drop in the effective Young's modulus was measured to be significant at around 150 nm thick cantilevers. The comparison between theoretical models and experimental measurements demonstrates that, although the surface effects influence the effective Young's modulus of silicon to some extent, they alone are insufficient to explain why the effective Young's modulus decreases prematurely. It was observed that the fabrication-induced defects abruptly increased when the device layer was thinned to below 100 nm. These defects became visible as pinholes during HF-etching. It is speculated that they could be the origin of the reduced effective Young's modulus experimentally observed in ultra-thin silicon cantilevers.

Comparative study of SOI/Si hybrid substrates fabricated using high-dose and low-dose oxygen implantation

International Nuclear Information System (INIS)

Dong Yemin; Chen Meng; Chen Jing; Wang Xiang; Wang Xi

2004-01-01

Hybrid substrates comprising both silicon-on-insulator (SOI) and bulk Si regions have been fabricated using the technique of patterned separation by implantation of oxygen (SIMOX) with high-dose (1.5 x 10 18 cm -2 ) and low-dose ((1.5-3.5) x 10 17 cm -2 ) oxygen ions, respectively. Cross-sectional transmission electron microscopy (XTEM) was employed to examine the microstructures of the resulting materials. Experimental results indicate that the SOI/Si hybrid substrate fabricated using high-dose SIMOX is of inferior quality with very large surface height step and heavily damaged transitions between the SOI and bulk regions. However, the quality of the SOI/Si hybrid substrate is enhanced dramatically by reducing the implant dose. The defect density in transitions is reduced considerably. Moreover, the expected surface height difference does not exist and the surface is exceptionally flat. The possible mechanisms responsible for the improvements in quality are discussed

Ultra-low-loss inverted taper coupler for silicon-on-insulator ridge waveguide

DEFF Research Database (Denmark)

Pu, Minhao; Liu, Liu; Ou, Haiyan

2010-01-01

An ultra-low-loss coupler for interfacing a silicon-on-insulator ridge waveguide and a single-mode fiber in both polarizations is presented. The inverted taper coupler, embedded in a polymer waveguide, is optimized for both the transverse-magnetic and transverse-electric modes through tapering...... the width of the silicon-on-insulator waveguide from 450 nm down to less than 15 nm applying a thermal oxidation process. Two inverted taper couplers are integrated with a 3-mm long silicon-on-insulator ridge waveguide in the fabricated sample. The measured coupling losses of the inverted taper coupler...... for transverse-magnetic and transverse-electric modes are ~0.36 dB and ~0.66 dB per connection, respectively....

Improving breakdown voltage performance of SOI power device with folded drift region

Science.gov (United States)

Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

2016-07-01

A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

Science.gov (United States)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure.

Science.gov (United States)

Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

2017-12-23

This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e - rms , low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

BUSFET - A Novel Radiation-Hardened SOI Transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

International Nuclear Information System (INIS)

Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

2005-01-01

This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

Silicon nanowire hot carrier electroluminescence

Energy Technology Data Exchange (ETDEWEB)

Plessis, M. du, E-mail: monuko@up.ac.za; Joubert, T.-H.

2016-08-31

Avalanche electroluminescence from silicon pn junctions has been known for many years. However, the internal quantum efficiencies of these devices are quite low due to the indirect band gap nature of the semiconductor material. In this study we have used reach-through biasing and SOI (silicon-on-insulator) thin film structures to improve the internal power efficiency and the external light extraction efficiency. Both continuous silicon thin film pn junctions and parallel nanowire pn junctions were manufactured using a custom SOI technology. The pn junctions are operated in the reach-through mode of operation, thus increasing the average electric field within the fully depleted region. Experimental results of the emission spectrum indicate that the most dominant photon generating mechanism is due to intraband hot carrier relaxation processes. It was found that the SOI nanowire light source external power efficiency is at least an order of magnitude better than the comparable bulk CMOS (Complementary Metal Oxide Semiconductor) light source. - Highlights: • We investigate effect of electric field on silicon avalanche electroluminescence. • With reach-through pn junctions the current and carrier densities are kept constant. • Higher electric fields increase short wavelength radiation. • Higher electric fields decrease long wavelength radiation. • The effect of the electric field indicates intraband transitions as main mechanism.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

Science.gov (United States)

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Hydrogen interactions with silicon-on-insulator materials

NARCIS (Netherlands)

Rivera de Mena, A.J.

2003-01-01

The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously

Realization of a Hole-Doped Mott Insulator on a Triangular Silicon Lattice

Science.gov (United States)

Ming, Fangfei; Johnston, Steve; Mulugeta, Daniel; Smith, Tyler S.; Vilmercati, Paolo; Lee, Geunseop; Maier, Thomas A.; Snijders, Paul C.; Weitering, Hanno H.

2017-12-01

The physics of doped Mott insulators is at the heart of some of the most exotic physical phenomena in materials research including insulator-metal transitions, colossal magnetoresistance, and high-temperature superconductivity in layered perovskite compounds. Advances in this field would greatly benefit from the availability of new material systems with a similar richness of physical phenomena but with fewer chemical and structural complications in comparison to oxides. Using scanning tunneling microscopy and spectroscopy, we show that such a system can be realized on a silicon platform. The adsorption of one-third monolayer of Sn atoms on a Si(111) surface produces a triangular surface lattice with half filled dangling bond orbitals. Modulation hole doping of these dangling bonds unveils clear hallmarks of Mott physics, such as spectral weight transfer and the formation of quasiparticle states at the Fermi level, well-defined Fermi contour segments, and a sharp singularity in the density of states. These observations are remarkably similar to those made in complex oxide materials, including high-temperature superconductors, but highly extraordinary within the realm of conventional s p -bonded semiconductor materials. It suggests that exotic quantum matter phases can be realized and engineered on silicon-based materials platforms.

Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

Science.gov (United States)

Wu, Bin

Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

Label-free electrical determination of trypsin activity by a silicon-on-insulator based thin film resistor.

Science.gov (United States)

Neff, Petra A; Serr, Andreas; Wunderlich, Bernhard K; Bausch, Andreas R

2007-10-08

A silicon-on-insulator (SOI) based thin film resistor is employed for the label-free determination of enzymatic activity. We demonstrate that enzymes, which cleave biological polyelectrolyte substrates, can be detected by the sensor. As an application, we consider the serine endopeptidase trypsin, which cleaves poly-L-lysine (PLL). We show that PLL adsorbs quasi-irreversibly to the sensor and is digested by trypsin directly at the sensor surface. The created PLL fragments are released into the bulk solution due to kinetic reasons. This results in a measurable change of the surface potential allowing for the determination of trypsin concentrations down to 50 ng mL(-1). Chymotrypsin is a similar endopeptidase with a different specificity, which cleaves PLL with a lower efficiency as compared to trypsin. The activity of trypsin is analyzed quantitatively employing a kinetic model for enzyme-catalyzed surface reactions. Moreover, we have demonstrated the specific inactivation of trypsin by a serine protease inhibitor, which covalently binds to the active site of the enzyme.

Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

Science.gov (United States)

Chiu, Yi; Pan, Jiun-Hung

2007-05-14

The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

An integrated optic ethanol vapor sensor based on a silicon-on-insulator microring resonator coated with a porous ZnO film.

Science.gov (United States)

Yebo, Nebiyu A; Lommens, Petra; Hens, Zeger; Baets, Roel

2010-05-24

Optical structures fabricated on silicon-on-insulator technology provide a convenient platform for the implementation of highly compact, versatile and low cost devices. In this work, we demonstrate the promise of this technology for integrated low power and low cost optical gas sensing. A room temperature ethanol vapor sensor is demonstrated using a ZnO nanoparticle film as a coating on an SOI micro-ring resonator of 5 microm in radius. The local coating on the ring resonators is prepared from colloidal suspensions of ZnO nanoparticles of around 3 nm diameter. The porous nature of the coating provides a large surface area for gas adsorption. The ZnO refractive index change upon vapor adsorption shifts the microring resonance through evanescent field interaction. Ethanol vapor concentrations down to 100 ppm are detected with this sensing configuration and a detection limit below 25 ppm is estimated.

Six-beam homodyne laser Doppler vibrometry based on silicon photonics technology.

Science.gov (United States)

Li, Yanlu; Zhu, Jinghao; Duperron, Matthieu; O'Brien, Peter; Schüler, Ralf; Aasmul, Soren; de Melis, Mirko; Kersemans, Mathias; Baets, Roel

2018-02-05

This paper describes an integrated six-beam homodyne laser Doppler vibrometry (LDV) system based on a silicon-on-insulator (SOI) full platform technology, with on-chip photo-diodes and phase modulators. Electronics and optics are also implemented around the integrated photonic circuit (PIC) to enable a simultaneous six-beam measurement. Measurement of a propagating guided elastic wave in an aluminum plate (speed ≈ 909 m/s @ 61.5 kHz) is demonstrated.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

A grating coupler with a trapezoidal hole array for perfectly vertical light coupling between optical fibers and waveguides

Science.gov (United States)

Mizutani, Akio; Eto, Yohei; Kikuta, Hisao

2017-12-01

A grating coupler with a trapezoidal hole array was designed and fabricated for perfectly vertical light coupling between a single-mode optical fiber and a silicon waveguide on a silicon-on-insulator (SOI) substrate. The grating coupler with an efficiency of 53% was computationally designed at a 1.1-µm-thick buried oxide (BOX) layer. The grating coupler and silicon waveguide were fabricated on the SOI substrate with a 3.0-µm-thick BOX layer by a single full-etch process. The measured coupling efficiency was 24% for TE-polarized light at 1528 nm wavelength, which was 0.69 times of the calculated coupling efficiency for the 3.0-µm-thick BOX layer.

Barrier layer arrangement for conductive layers on silicon substrates

International Nuclear Information System (INIS)

Hung, L.S.; Agostinelli, J.A.

1990-01-01

This patent describes a circuit element comprised of a silicon substrate and a conductive layer located on the substrate. It is characterized in that the conductive layer consists essentially of a rare earth alkaline earth copper oxide and a barrier layer triad is interposed between the silicon substrate and the conductive layer comprised of a first triad layer located adjacent the silicon substrate consisting essentially of silica, a third triad layer remote from the silicon substrate consisting essentially of a least one Group 4 heavy metal oxide, and a second triad layer interposed between the first and third triad layers consisting essentially of a mixture of silica and at lease one Group 4 heavy metal oxide

Output-Conductance Transition-Free Method for Improving Radio-Frequency Linearity of SOI MOSFET Circuits

Directory of Open Access Journals (Sweden)

A. Daghighi

2013-09-01

Full Text Available In this article, a novel concept is introduced to improve the radio frequency (RF linearity of partially-depleted (PD silicon-on-insulator (SOI MOSFET circuits. The transition due to the non-zero body resistance (RBody in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown. 3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz low noise amplifier (LNA is analyzed. Mixed mode device-circuit analysis is carried out to simultaneously solve device transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third harmonic distortion (HD3 and total harmonic distortion (THD are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.

Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric

International Nuclear Information System (INIS)

Barchuk, I.P.; Kilchitskaya, V.I.; Lysenko, V.S.

1997-01-01

In this work SOI structures with buried SiO 2 -Si 3 N 4 -SiO 2 layers have been fabricated by the ZMR-technique with the aim of improving the total dose radiation hardness of the buried dielectric layer. To optimize the fabrication process, buried layers were investigated by secondary ion mass spectrometry before and after the ZMR process, and the obtained results were compared with electrical measurements. It is shown that optimization of the preparation processes of the initial buried dielectric layers provides ZMR SOI structures with multilayer buried isolation, which are of high quality for both Si film interfaces. Particular attention is paid to the investigation of radiation-induced charge trapping in buried insulators. Buried isolation structures with a nitride layer exhibit significant reduction of radiation-induced positive charge as compared to classical buried SiO 2 layers produced by either the ZMR or the SIMOX technique

The effect of baking conditions on the effective contact areas of screen-printed silver layer on silicon substrate

Energy Technology Data Exchange (ETDEWEB)

Tietun Sun; Jianmin Miao; Rongming Lin; Yongqing Fu [Nanyang Technological Univ., Micromachines Lab., Singapore (Singapore)

2005-01-01

In this paper, Ag-based paste was screen-printed on polished as well as on textured p-type (100) single crystalline silicon wafers. Three types of baking processes were studied: the tube furnace, the belt furnace and the hot plate baking. The effective contact areas of Ag/Si system were measured with a novel method, namely metal insulator semiconductor structure measurement. The results show that after baking on the hot plate at 400 deg C for 5 min, the size and number of pores in the Ag film layer as well as at the interface between silver layer and silicon decreases significantly, the effective contact area also increases about 20%, particularly on the textured silicon substrate. (Author)

The effect of baking conditions on the effective contact areas of screen-printed silver layer on silicon substrate

Energy Technology Data Exchange (ETDEWEB)

Sun, Tietun; Miao, Jianmin; Lin, Rongming; Fu, Yongqing [Micromachines Laboratory, School of Mechanical and Production Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

2005-01-01

In this paper, Ag-based paste was screen-printed on the polished as well as on the textured p-type (100) single crystalline silicon wafers. Three types of baking processes were studied: the tube furnace, the belt furnace and the hot plate baking. The effective contact areas of Ag/Si system were measured with a novel method, namely metal insulator semiconductor structure measurement. The results show that after baking on the hot plate at 400{sup o}C for 5min, the size and number of pores in the Ag film layer as well as at the interface between silver layer and silicon decreases significantly, the effective contact area also increases about 20%, particularly on the textured silicon substrate.

A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

International Nuclear Information System (INIS)

Wang Zhongjian; Cheng Xinhong; Xia Chao; Xu Dawei; Cao Duo; Song Zhaorui; Yu Yuehui; Shen Dashen

2012-01-01

A 680 V LDMOS on a thin SOI with an improved field oxide (FOX) and dual field plate was studied experimentally. The FOX structure was formed by an 'oxidation-etch-oxidation' process, which took much less time to form, and had a low protrusion profile. A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance. An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field. Using a SimBond SOI wafer with a 1.5 μm top silicon and a 3 μm buried oxide layer, CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V, and the specific on-resistance was 8.2 Ω·mm 2 . (semiconductor devices)

Nonlinear Optical Functions in Crystalline and Amorphous Silicon-on-Insulator Nanowires

DEFF Research Database (Denmark)

Baets, R.; Kuyken, B.; Liu, X.

2012-01-01

Silicon-on-Insulator nanowires provide an excellent platform for nonlinear optical functions in spite of the two-photon absorption at telecom wavelengths. Work on both crystalline and amorphous silicon nanowires is reviewed, in the wavelength range of 1.5 to 2.5 µm....

Mapping the broadband polarization properties of linear 2D SOI photonic crystal waveguides

DEFF Research Database (Denmark)

Canning, John; Skivesen, Nina; Kristensen, Martin

2007-01-01

Both quasi-TE and TM polarisation spectra for a silicon- on-insulator (SOI) waveguide are recorded over (1100-1700) nm using a broadband supercontinuum source. By studying both the input and output polarisation eigenstates we observe narrowband resonant cross coupling near the lowest quasi-TE mode...... cut-off. We also observe relatively broadband mixing between the two eigenstates to generate a complete photonic bandgap. By careful analysis of the output polarisation state we report on an inherent non-reciprocity between quasi TE and TM fundamental mode cross coupling. The nature of polarisation...

A Difference in Using Atomic Layer Deposition or Physical Vapour Deposition TiN as Electrode Material in Metal-Insulator-Metal and Metal-Insulator-Silicon Capacitors

NARCIS (Netherlands)

Groenland, A.W.; Wolters, Robertus A.M.; Kovalgin, Alexeij Y.; Schmitz, Jurriaan

2011-01-01

In this work, metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) capacitors are studied using titanium nitride (TiN) as the electrode material. The effect of structural defects on the electrical properties on MIS and MIM capacitors is studied for various electrode configurations. In the

New insights into fully-depleted SOI transistor response during total-dose irradiation

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Dodd, P.E.; Burns, J.A.; Keast, C.L.; Wyatt, P.W.

1999-01-01

In this paper, we present irradiation results on 2-fully depleted processes (HYSOI6, RKSOI) that show SOI (silicon on insulator) device response can be more complicated than originally suggested by others. The major difference between the 2 process versions is that the RKSOI process incorporates special techniques to minimize pre-irradiation parasitic leakage current from trench sidewalls. Transistors were irradiated at room temperature using 10 keV X-ray source. Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. It appears that the worst-case bias for HYPOI6 process is the bias that causes the largest increase in sidewall leakage. The RKSOI process shows a different response during irradiation, the transition response appears to be dominated by charge trapping in the buried oxide. These results have implications for hardness assurance testing. (A.C.)

Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

Science.gov (United States)

Katz, Oded; Malka, Dror

2017-07-01

In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530-1565 nm) with excess loss better than 0.23 dB.

Oxide-Free Bonding of III-V-Based Material on Silicon and Nano-Structuration of the Hybrid Waveguide for Advanced Optical Functions

Directory of Open Access Journals (Sweden)

Konstantinos Pantzas

2015-10-01

Full Text Available Oxide-free bonding of III-V-based materials for integrated optics is demonstrated on both planar Silicon (Si surfaces and nanostructured ones, using Silicon on Isolator (SOI or Si substrates. The hybrid interface is characterized electrically and mechanically. A hybrid InP-on-SOI waveguide, including a bi-periodic nano structuration of the silicon guiding layer is demonstrated to provide wavelength selective transmission. Such an oxide-free interface associated with the nanostructured design of the guiding geometry has great potential for both electrical and optical operation of improved hybrid devices.

Novel detectors for silicon based microdosimetry, their concepts and applications

Science.gov (United States)

Rosenfeld, Anatoly B.

2016-02-01

This paper presents an overview of the development of semiconductor microdosimetry and the most current (state-of-the-art) Silicon on Insulator (SOI) detectors for microdosimetry based mainly on research and development carried out at the Centre for Medical Radiation Physics (CMRP) at the University of Wollongong with collaborators over the last 18 years. In this paper every generation of CMRP SOI microdosimeters, including their fabrication, design, and electrical and charge collection characterisation are presented. A study of SOI microdosimeters in various radiation fields has demonstrated that under appropriate geometrical scaling, the response of SOI detectors with the well-known geometry of microscopically sensitive volumes will record the energy deposition spectra representative of tissue cells of an equivalent shape. This development of SOI detectors for microdosimetry with increased complexity has improved the definition of microscopic sensitive volume (SV), which is modelling the deposition of ionising energy in a biological cell, that are led from planar to 3D SOI detectors with an array of segmented microscopic 3D SVs. The monolithic ΔE-E silicon telescope, which is an alternative to the SOI silicon microdosimeter, is presented, and as an example, applications of SOI detectors and ΔE-E monolithic telescope for microdosimetery in proton therapy field and equivalent neutron dose measurements out of field are also presented. An SOI microdosimeter "bridge" with 3D SVs can derive the relative biological effectiveness (RBE) in 12C ion radiation therapy that matches the tissue equivalent proportional counter (TEPC) quite well, but with outstanding spatial resolution. The use of SOI technology in experimental microdosimetry offers simplicity (no gas system or HV supply), high spatial resolution, low cost, high count rates, and the possibility of integrating the system onto a single device with other types of detectors.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

Science.gov (United States)

Priya, Anjali; Mishra, Ram Awadh

2016-04-01

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

360° tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

DEFF Research Database (Denmark)

Pu, Minhao; Xue, Weiqi; Liu, Liu

2010-01-01

We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained......We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained...

Electrical characterization of high-pressure reactive sputtered ScOx films on silicon

International Nuclear Information System (INIS)

Castan, H.; Duenas, S.; Gomez, A.; Garcia, H.; Bailon, L.; Feijoo, P.C.; Toledano-Luque, M.; Prado, A. del; San Andres, E.; Lucia, M.L.

2011-01-01

Al/ScO x /SiN x /n-Si and Al/ScO x /SiO x /n-Si metal-insulator-semiconductor capacitors have been electrically characterized. Scandium oxide was grown by high-pressure sputtering on different substrates to study the dielectric/insulator interface quality. The substrates were silicon nitride and native silicon oxide. The use of a silicon nitride interfacial layer between the silicon substrate and the scandium oxide layer improves interface quality, as interfacial state density and defect density inside the insulator are decreased.

A 2D simulation study and characterization of a novel vertical SOI MOSFET with a smart source/body tie

International Nuclear Information System (INIS)

Lin, Jyi-Tsong; Lee, Tai-Yi; Lin, Kao-Cheng

2008-01-01

A novel vertical silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with a smart source/body contact, SSBVMOS, is presented here for the first time. 2D simulations reveal that the SSBVMOS reduces self-heating effects, with the lattice temperature reduced by 14% and the hole temperature reduced by 25%. The SSBVMOS also eliminates the floating body effect, something that other SOI vertical MOSFETs are unable to accomplish, regardless of the thickness of the thin film. The SSBVMOS is further found to have a better drain-induced barrier lowering and subthreshold swing than either a conventional vertical MOSFET or an SOI vertical MOSFET. Moreover, these results are achieved using typical pillar heights and buried oxide thicknesses. Should future technological advances allow for lower pillars or thinner buried oxides, the SSBVMOS performance would further increase

Interfacial phonon scattering and transmission loss in >1 μm thick silicon-on-insulator thin films

Science.gov (United States)

Jiang, Puqing; Lindsay, Lucas; Huang, Xi; Koh, Yee Kan

2018-05-01

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1-10 μm and a temperature range of 100-300 K. The Si /SiO2 interface roughness was determined to be 0.11 ±0.04 nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

Room to high temperature measurements of flexible SOI FinFETs with sub-20-nm fins

KAUST Repository

Diab, Amer El Hajj

2014-12-01

We report the temperature dependence of the core electrical parameters and transport characteristics of a flexible version of fin field-effect transistor (FinFET) on silicon-on-insulator (SOI) with sub-20-nm wide fins and high-k/metal gate-stacks. For the first time, we characterize them from room to high temperature (150 °C) to show the impact of temperature variation on drain current, gate leakage current, and transconductance. Variation of extracted parameters, such as low-field mobility, subthreshold swing, threshold voltage, and ON-OFF current characteristics, is reported too. Direct comparison is made to a rigid version of the SOI FinFETs. The mobility degradation with temperature is mainly caused by phonon scattering mechanism. The overall excellent devices performance at high temperature after release is outlined proving the suitability of truly high-performance flexible inorganic electronics with such advanced architecture.

A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

Science.gov (United States)

Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

2018-04-01

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

International Nuclear Information System (INIS)

Zhang Jun; Guo Yu-Feng; Xu Yue; Lin Hong; Yang Hui; Hong Yang; Yao Jia-Fei

2015-01-01

A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device. (paper)

Computer simulation for the formation of the insulator layer of silicon-on-insulator devices by N sup + and O sup + Co-implantation

CERN Document Server

Lin Qing; Xie Xin Yun; Lin Chenglu; Liu Xiang Hua

2002-01-01

A buried sandwiched layer consisting of silicon dioxide (upper part), silicon oxynitride (medium part) and silicon nitride (lower part) is formed by N sup + and O sup + co-implantation in silicon wafers at a constant temperature of 550 degree C. The microstructure is performed by cross-sectional transmission electron microscopy. To predict the quality of the buried sandwiched layer, the authors study the computer simulation for the formation of the SIMON (separated by implantation of oxygen and nitrogen) structure. The simulation program for SIMOX (separated by implantation of oxygen) is improved in order to be applied in O sup + and N sup + co-implantation on the basis of different formation mechanism between SIMOX and SIMNI (separated by implantation of nitrogen) structures. There is a good agreement between experiment and simulation results verifying the theoretical model and presumption in the program

Fabrication of open-top microchannel plate using deep X-ray exposure mask made with silicon on insulator substrate

CERN Document Server

Fujimura, T; Etoh, S I; Hattori, R; Kuroki, Y; Chang, S S

2003-01-01

We propose a high-aspect-ratio open-top microchannel plate structure. This type of microchannel plate has many advantages in electrophoresis. The plate was fabricated by deep X-ray lithography using synchrotron radiation (SR) light and the chemical wet etching process. A deep X-ray exposure mask was fabricated with a silicon on insulator (SOI) substrate. The patterned Si microstructure was micromachined into a thin Si membrane and a thick Au X-ray absorber was embedded in it by electroplating. A plastic material, polymethylmethacrylate (PMMA) was used for the plate substrate. For reduction of the exposure time and high-aspect-ratio fast wet development, the fabrication condition was optimized with respect to not the exposure dose but to the PMMA mean molecular weight (M.W.) changing after deep X-ray exposure as measured by gel permeation chromatography (GPC). Decrement of the PMMA M.W. and increment of the wet developer temperature accelerated the etching rate. Under optimized fabrication conditions, a microc...

Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs

International Nuclear Information System (INIS)

Chen Jing; Luo Jiexin; Wu Qingqing; Chai Zhan; Huang Xiaolu; Wei Xing; Wang Xi

2012-01-01

Silicon-on-insulate (SOI) MOSFETs offer benefits over bulk competitors for fully isolation and smaller junction capacitance. The performance of partially depleted (PD) SOI MOSFETs, though, is not good enough. Since the body is floating, the extra holes (for nMOSFETs) in this region accumulate, causing body potential arise, which of course degrades the performance of the device. How to suppress the floating-body effect becomes critical. There are mainly two ways for the goal. One is to employ body-contact structures, and the other SiGe source/drain structures. However, the former consumes extra area, not welcomed in the state-of-the-art chips design. The latter is not compatible with the traditional CMOS technology. Finding a structure both saving area and compatible technology is the most urgent for PD SOI MOSFETs. Recently, we have developed a new structure with extra heavy boron implantation in the source region for PD SOI nMOSFETs. It consumes no extra area and is also compatible with CMOS technology. The device is found to be free of kink effect in simulation, which implies the floating-body effect is greatly suppressed. In addition, the mechanisms of the kink-free, as well as the impact of different implanting conditions are interpreted.

Estimation of thermal insulation performance in multi-layer insulator for liquid helium pipe

International Nuclear Information System (INIS)

Shibanuma, Kiyoshi; Kuriyama, Masaaki; Shibata, Takemasa

1991-01-01

For a multi-layer insulator around the liquid helium pipes for cryopumps of JT-60 NBI, a multi-layer insulator composed of 10 layers, which can be wound around the pipe at the same time and in which the respective layers are in concentric circles by shifting them in arrangement, has been developed and tested. As the result, it was shown that the newly developed multi-layer insulator has better thermal insulation performance than the existing one, i.e. the heat load of the newly developed insulator composed of 10 layers was reduced to 1/3 the heat load of the existing insulator, and the heat leak at the joint of the insulator in longitudinal direction of the pipe was negligible. In order to clarify thermal characteristics of the multi-layer insulator, the heat transfer through the insulator has been analyzed considering the radiation heat transfer by the netting spacer between the reflectors, and the temperature dependence on the emissivities and the heat transmission coefficients of these two components of the insulator. The analytical results were in good agreements with the experimental ones, so that the analytical method was shown to be valid. Concerning the influence of the number of layers and the layer density on the insulation performance of the insulator, analytical results showed that the multi-layer insulator with the number of layer about N = 20 and the layer density below 2.0 layer/mm was the most effective for the liquid helium pipe of a JT-60 cryopump. (author)

Ultra-low loss nano-taper coupler for Silicon-on-Insulator ridge waveguide

DEFF Research Database (Denmark)

Pu, Minhao; Liu, Liu; Ou, Haiyan

2010-01-01

A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler.......A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler....

Si-nanowire-based multistage delayed Mach-Zehnder interferometer optical MUX/DeMUX fabricated by an ArF-immersion lithography process on a 300 mm SOI wafer.

Science.gov (United States)

Jeong, Seok-Hwan; Shimura, Daisuke; Simoyama, Takasi; Horikawa, Tsuyoshi; Tanaka, Yu; Morito, Ken

2014-07-01

We report good phase controllability and high production yield in Si-nanowire-based multistage delayed Mach-Zehnder interferometer-type optical multiplexers/demultiplexers (MUX/DeMUX) fabricated by an ArF-immersion lithography process on a 300 mm silicon-on-insulator (SOI) wafer. Three kinds of devices fabricated in this work exhibit clear 1×4 Ch wavelength filtering operations for various optical frequency spacing. These results are promising for their applications in high-density wavelength division multiplexing-based optical interconnects.

Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

Science.gov (United States)

Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

2017-07-01

Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

Improved the Surface Roughness of Silicon Nanophotonic Devices by Thermal Oxidation Method

Energy Technology Data Exchange (ETDEWEB)

Shi Zujun; Shao Shiqian; Wang Yi, E-mail: ywangwnlo@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, No. 1037, Luoyu Street, Wuhan 430074 (China)

2011-02-01

The transmission loss of the silicon-on-insulator (SOI) waveguide and the coupling loss of the SOI grating are determined to a large extent by the surface roughness. In order to obtain smaller loss, thermal oxidation is a good choice to reduce the surface roughness of the SOI waveguide and grating. Before the thermal oxidation, the root mean square of the surface roughness is over 11 nm. After the thermal oxidation, the SEM figure shows that the bottom of the grating is as smooth as quartz surface, while the AFM shows that the root mean square of the surface is less than 5 nm.

Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

International Nuclear Information System (INIS)

Yu Xiaomei; Tang Yaquan; Zhang Haitao

2008-01-01

This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

Fabrication of double-dot single-electron transistor in silicon nanowire

International Nuclear Information System (INIS)

Jo, Mingyu; Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Ono, Yukinori; Inokawa, Hiroshi; Choi, Jung-Bum; Takahashi, Yasuo

2010-01-01

We propose a simple method for fabricating Si single-electron transistors (SET) with coupled dots by means of a pattern-dependent-oxidation (PADOX) method. The PADOX method is known to convert a small one-dimensional Si wire formed on a silicon-on-insulator (SOI) substrate into a SET automatically. We fabricated a double-dot Si SET when we oxidized specially designed Si nanowires formed on SOI substrates. We analyzed the measured electrical characteristics by fitting the measurement and simulation results and confirmed the double-dot formation and the position of the two dots in the Si wire.

Growth of light-emitting SiGe heterostructures on strained silicon-on-insulator substrates with a thin oxide layer

Energy Technology Data Exchange (ETDEWEB)

Baidakova, N. A., E-mail: banatale@ipmras.ru [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation); Bobrov, A. I. [University of Nizhny Novgorod (Russian Federation); Drozdov, M. N.; Novikov, A. V. [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation); Pavlov, D. A. [University of Nizhny Novgorod (Russian Federation); Shaleev, M. V.; Yunin, P. A.; Yurasov, D. V.; Krasilnik, Z. F. [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation)

2015-08-15

The possibility of using substrates based on “strained silicon on insulator” structures with a thin (25 nm) buried oxide layer for the growth of light-emitting SiGe structures is studied. It is shown that, in contrast to “strained silicon on insulator” substrates with a thick (hundreds of nanometers) oxide layer, the temperature stability of substrates with a thin oxide is much lower. Methods for the chemical and thermal cleaning of the surface of such substrates, which make it possible to both retain the elastic stresses in the thin Si layer on the oxide and provide cleaning of the surface from contaminating impurities, are perfecte. It is demonstrated that it is possible to use the method of molecular-beam epitaxy to grow light-emitting SiGe structures of high crystalline quality on such substrates.

A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

Directory of Open Access Journals (Sweden)

Saeid Marjani

2016-09-01

Full Text Available In this paper, a silicon–on–insulator (SOI p–n–p–n tunneling field–effect transistor (TFET with a silicon doped hafnium oxide (Si:HfO2 ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3 and strontium bismuth tantalate (SrBi2Ta2O9 provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

Energy Technology Data Exchange (ETDEWEB)

Naumova, O. V., E-mail: naumova@isp.nsc.ru; Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

2015-10-15

The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

International Nuclear Information System (INIS)

Qiao Fengying; Pan Liyang; Wu Dong; Liu Lifang; Xu Jun

2014-01-01

In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode. (semiconductor devices)

Electrostatically Tunable Nanomechanical Shallow Arches

KAUST Repository

Kazmi, Syed N. R.; Hajjaj, Amal Z.; Da Costa, Pedro M. F. J.; Younis, Mohammad I.

2017-01-01

-beam lithography and surface nanomachining of a highly conductive device layer on a silicon-on-insulator (SOI) wafer. The experimental results show good agreement with the analytical results with a maximum tunability of 108.14% for 180 nm thick arch with a

Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

DEFF Research Database (Denmark)

Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial...... Silicon-on-Insulator (SOI) process with a die area 2.31 mm2.  A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize...

Study on structural properties of epitaxial silicon films on annealed double layer porous silicon

International Nuclear Information System (INIS)

Yue Zhihao; Shen Honglie; Cai Hong; Lv Hongjie; Liu Bin

2012-01-01

In this paper, epitaxial silicon films were grown on annealed double layer porous silicon by LPCVD. The evolvement of the double layer porous silicon before and after thermal annealing was investigated by scanning electron microscope. X-ray diffraction and Raman spectroscopy were used to investigate the structural properties of the epitaxial silicon thin films grown at different temperature and different pressure. The results show that the surface of the low-porosity layer becomes smooth and there are just few silicon-bridges connecting the porous layer and the substrate wafer. The qualities of the epitaxial silicon thin films become better along with increasing deposition temperature. All of the Raman peaks of silicon films with different deposition pressure are situated at 521 cm -1 under the deposition temperature of 1100 °C, and the Raman intensity of the silicon film deposited at 100 Pa is much closer to that of the monocrystalline silicon wafer. The epitaxial silicon films are all (4 0 0)-oriented and (4 0 0) peak of silicon film deposited at 100 Pa is more symmetric.

Fabrication of SGOI material by oxidation of an epitaxial SiGe layer on an SOI wafer with H ions implantation

International Nuclear Information System (INIS)

Cheng Xinli; Chen Zhijun; Wang Yongjin; Jin Bo; Zhang Feng; Zou Shichang

2005-01-01

SGOI materials were fabricated by thermal dry oxidation of epitaxial H-ion implanted SiGe layers on SOI wafers. The hydrogen implantation was found to delay the oxidation rate of SiGe layer and to decrease the loss of Ge atoms during oxidation. Further, the H implantation did not degrade the crystallinity of SiGe layer during fabrication of the SGOI

Thin-film piezoelectric-on-silicon resonators for high-frequency reference oscillator applications.

Science.gov (United States)

Abdolvand, Reza; Lavasani, Hossein M; Ho, Gavin K; Ayazi, Farrokh

2008-12-01

This paper studies the application of lateral bulk acoustic thin-film piezoelectric-on-substrate (TPoS) resonators in high-frequency reference oscillators. Low-motional-impedance TPoS resonators are designed and fabricated in 2 classes--high-order and coupled-array. Devices of each class are used to assemble reference oscillators and the performance characteristics of the oscillators are measured and discussed. Since the motional impedance of these devices is small, the transimpedance amplifier (TIA) in the oscillator loop can be reduced to a single transistor and 3 resistors, a format that is very power-efficient. The lowest reported power consumption is approximately 350 microW for an oscillator operating at approximately 106 MHz. A passive temperature compensation method is also utilized by including the buried oxide layer of the silicon-on-insulator (SOI) substrate in the structural resonant body of the device, and a very small (-2.4 ppm/ degrees C) temperature coefficient of frequency is obtained for an 82-MHz oscillator.

Channel-Selectable Optical Link Based on a Silicon Microring for on-Chip Interconnection

International Nuclear Information System (INIS)

Qiu Chen; Hu Ting; Wang Wan-Jun; Yu Ping; Jiang Xiao-Qing; Yang Jian-Yi

2012-01-01

A channel-selectable optical link based on a silicon microring resonator is proposed and demonstrated. This optical link consists of the wavelength-tunable microring modulators and the filters, defined on a silicon-on-insulator (SOI) platform. With a p—i—n junction embedded in the microring modulator, light at the resonant wavelength of the ring resonator is modulated. The 2 nd -order microring add-drop filter routes the modulated light. The channel selectivity is demonstrated by heating the microrings. With a thermal tuning efficiency of 5.9 mW/nm, the filter drop port response was successfully tuned with 0.8 nm channel spacing. We also show that modulation can be achieved in these channels. This device aims to offer flexibility and increase the bandwidth usage efficiency in optical interconnection

Electrical characteristics of SiGe-base bipolar transistors on thin-film SOI substrates

International Nuclear Information System (INIS)

Liao, Shu-Hui; Chang, Shu-Tong

2010-01-01

This paper, based on two-dimensional simulations, provides a comprehensive analysis of the electrical characteristics of the Silicon germanium (SiGe)-base bipolar transistors on thin-film siliconon-insulator (SOI) substrates. The impact of the buried oxide thickness (T OX ), the emitter width (W E ), and the lateral distance between the edge of the intrinsic base and the reach-through region (L col ) on both the AC and DC device characteristics was analyzed in detail. Regarding the DC characteristics, the simulation results suggest that a thicker T OX gives a larger base-collector breakdown voltage (BV CEO ), whereas reducing the T OX leads to an enhanced maximum electric field at the B-C junction. As for the AC characteristics, cut-off frequency (f T ) increases slightly with increasing buried oxide thickness and finally saturates to a constant value when the buried oxide thickness is about 0.15 μm. The collector-substrate capacitance (C CS ) decreases with increasing buried oxide thickness while the maximum oscillation frequency (f max ) increases with increasing buried oxide thickness. Furthermore, the impact of self-heating effects in the device was analyzed in various areas. The thermal resistance as a function of the buried oxide thickness indicates that the thermal resistance of the SiGe-base bipolar transistor on a SOI substrate is slightly higher than that of a bulk SiGe-base bipolar transistor. The thermal resistance is reduced by ∼37.89% when the emitter width is increased by a factor of 5 for a fixed buried oxide thickness of 0.1 μm. All the results can be used to design and optimize SiGe-base bipolar transistors on SOI substrates with minimum thermal resistance to enhance device performance.

Methods To Determine the Silicone Oil Layer Thickness in Sprayed-On Siliconized Syringes.

Science.gov (United States)

Loosli, Viviane; Germershaus, Oliver; Steinberg, Henrik; Dreher, Sascha; Grauschopf, Ulla; Funke, Stefanie

2018-01-01

The silicone lubricant layer in prefilled syringes has been investigated with regards to siliconization process performance, prefilled syringe functionality, and drug product attributes, such as subvisible particle levels, in several studies in the past. However, adequate methods to characterize the silicone oil layer thickness and distribution are limited, and systematic evaluation is missing. In this study, white light interferometry was evaluated to close this gap in method understanding. White light interferometry demonstrated a good accuracy of 93-99% for MgF 2 coated, curved standards covering a thickness range of 115-473 nm. Thickness measurements for sprayed-on siliconized prefilled syringes with different representative silicone oil distribution patterns (homogeneous, pronounced siliconization at flange or needle side, respectively) showed high instrument (0.5%) and analyst precision (4.1%). Different white light interferometry instrument parameters (autofocus, protective shield, syringe barrel dimensions input, type of non-siliconized syringe used as base reference) had no significant impact on the measured average layer thickness. The obtained values from white light interferometry applying a fully developed method (12 radial lines, 50 mm measurement distance, 50 measurements points) were in agreement with orthogonal results from combined white and laser interferometry and 3D-laser scanning microscopy. The investigated syringe batches (lot A and B) exhibited comparable longitudinal silicone oil layer thicknesses ranging from 170-190 nm to 90-100 nm from flange to tip and homogeneously distributed silicone layers over the syringe barrel circumference (110- 135 nm). Empty break-loose (4-4.5 N) and gliding forces (2-2.5 N) were comparably low for both analyzed syringe lots. A silicone oil layer thickness of 100-200 nm was thus sufficient for adequate functionality in this particular study. Filling the syringe with a surrogate solution including short

Nonlinear optical properties of silicon waveguides

International Nuclear Information System (INIS)

Tsang, H K; Liu, Y

2008-01-01

Recent work on two-photon absorption (TPA), stimulated Raman scattering (SRS) and optical Kerr effect in silicon-on-insulator (SOI) waveguides is reviewed and some potential applications of these optical nonlinearities, including silicon-based autocorrelation detectors, optical amplifiers, high speed optical switches, optical wavelength converters and self-phase modulation (SPM), are highlighted. The importance of free carriers generated by TPA in nonlinear devices is discussed, and a generalized definition of the nonlinear effective length to cater for nonlinear losses is proposed. How carrier lifetime engineering, and in particular the use of helium ion implantation, can enhance the nonlinear effective length for nonlinear devices is also discussed

Development of an X-ray imaging system with SOI pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Nishimura, Ryutaro, E-mail: ryunishi@post.kek.jp [School of High Energy Accelerator Science, SOKENDAI (The Graduate University for Advanced Studies), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Arai, Yasuo; Miyoshi, Toshinobu [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK-IPNS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Hirano, Keiichi; Kishimoto, Shunji; Hashimoto, Ryo [Institute of Materials Structure Science, High Energy Accelerator Research Organization (KEK-IMSS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan)

2016-09-21

An X-ray imaging system employing pixel sensors in silicon-on-insulator technology is currently under development. The system consists of an SOI pixel detector (INTPIX4) and a DAQ system based on a multi-purpose readout board (SEABAS2). To correct a bottleneck in the total throughput of the DAQ of the first prototype, parallel processing of the data taking and storing processes and a FIFO buffer were implemented for the new DAQ release. Due to these upgrades, the DAQ throughput was improved from 6 Hz (41 Mbps) to 90 Hz (613 Mbps). The first X-ray imaging system with the new DAQ software release was tested using 33.3 keV and 9.5 keV mono X-rays for three-dimensional computerized tomography. The results of these tests are presented. - Highlights: • The X-ray imaging system employing the SOI pixel sensor is currently under development. • The DAQ of the first prototype has the bottleneck in the total throughput. • The new DAQ release solve the bottleneck by parallel processing and FIFO buffer. • The new DAQ release was tested using 33.3 keV and 9.5 keV mono X-rays.

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

Science.gov (United States)

Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

2014-06-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

Low-loss slot waveguides with silicon (111 surfaces realized using anisotropic wet etching

Directory of Open Access Journals (Sweden)

Kapil Debnath

2016-11-01

Full Text Available We demonstrate low-loss slot waveguides on silicon-on-insulator (SOI platform. Waveguides oriented along the (11-2 direction on the Si (110 plane were first fabricated by a standard e-beam lithography and dry etching process. A TMAH based anisotropic wet etching technique was then used to remove any residual side wall roughness. Using this fabrication technique propagation loss as low as 3.7dB/cm was realized in silicon slot waveguide for wavelengths near 1550nm. We also realized low propagation loss of 1dB/cm for silicon strip waveguides.

Extreme group index measured and calculated in 2D SOI-based photonic crystal waveguides

DEFF Research Database (Denmark)

Lavrinenko, Andrei; Jacobsen, Rune Shim; Fage-Pedersen, Jacob

2005-01-01

lattice of air-holes in the 216-nm thick silicon layer in an SOI material. Experimental transmission spectra show a mode cut-off around 1562.5 nm for the fundamental photonic bandgap mode. In order to measure and model the group index of modes in the PCW, a time-of-flight (ToF) method is applied....

Widely tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

DEFF Research Database (Denmark)

Pu, Minhao; Liu, Liu; Xue, Weiqi

2010-01-01

We propose and demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator microring resonators. The phase-shifting range and the RF-power variation are analyzed. A maximum phase-shifting range of 0~600° is achieved by utilizing a dual-microring resonator...

SOI technology for power management in automotive and industrial applications

Science.gov (United States)

Stork, Johannes M. C.; Hosey, George P.

2017-02-01

Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding "Internet of Things" (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies.

Selective SiO2 etching in three dimensional structures using parylene-C as mask

NARCIS (Netherlands)

Veltkamp, Henk-Willem; Zhao, Yiyuan; de Boer, Meint J.; Wiegerink, Remco J.; Lötters, Joost Conrad

2017-01-01

This abstract describes an application of an easy and straightforward method for selective SiO2 etching in three dimensional structures, which is developed by our group. The application in this abstract is the protection of the buried-oxide (BOX) layer of a silicon-on-insulator (SOI) wafer against

Subwavelength engineered fiber-to-chip silicon-on-sapphire interconnects for mid-infrared applications (Conference Presentation)

Science.gov (United States)

Alonso-Ramos, Carlos; Han, Zhaohong; Le Roux, Xavier; Lin, Hongtao; Singh, Vivek; Lin, Pao Tai; Tan, Dawn; Cassan, Eric; Marris-Morini, Delphine; Vivien, Laurent; Wada, Kazumi; Hu, Juejun; Agarwal, Anuradha; Kimerling, Lionel C.

2016-05-01

The mid-Infrared wavelength range (2-20 µm), so-called fingerprint region, contains the very sharp vibrational and rotational resonances of many chemical and biological substances. Thereby, on-chip absorption-spectrometry-based sensors operating in the mid-Infrared (mid-IR) have the potential to perform high-precision, label-free, real-time detection of multiple target molecules within a single sensor, which makes them an ideal technology for the implementation of lab-on-a-chip devices. Benefiting from the great development realized in the telecom field, silicon photonics is poised to deliver ultra-compact efficient and cost-effective devices fabricated at mass scale. In addition, Si is transparent up to 8 µm wavelength, making it an ideal material for the implementation of high-performance mid-IR photonic circuits. The silicon-on-insulator (SOI) technology, typically used in telecom applications, relies on silicon dioxide as bottom insulator. Unfortunately, silicon dioxide absorbs light beyond 3.6 µm, limiting the usability range of the SOI platform for the mid-IR. Silicon-on-sapphire (SOS) has been proposed as an alternative solution that extends the operability region up to 6 µm (sapphire absorption), while providing a high-index contrast. In this context, surface grating couplers have been proved as an efficient means of injecting and extracting light from mid-IR SOS circuits that obviate the need of cleaving sapphire. However, grating couplers typically have a reduced bandwidth, compared with facet coupling solutions such as inverse or sub-wavelength tapers. This feature limits their feasibility for absorption spectroscopy applications that may require monitoring wide wavelength ranges. Interestingly, sub-wavelength engineering can be used to substantially improve grating coupler bandwidth, as demonstrated in devices operating at telecom wavelengths. Here, we report on the development of fiber-to-chip interconnects to ZrF4 optical fibers and integrated SOS

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

Science.gov (United States)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Silicon on insulator technology. Characteristics. Applications; Technologies silicium sur isolant. Caracteristiques. Exemples d'application

Energy Technology Data Exchange (ETDEWEB)

Suat, J. P.; Peccoud, L.; Le Goascoz, V.; Garcia, M.; Mackowiak, E.

1975-01-31

The advantages resulting from a SOS (Silicon-on-Sapphire) MOS technology are demonstrated. Experimental results giving the performance of C.MOS and depletion-enrichment P-channel technologies are presented, with an application of Silicon on insulator on development, that is to say a 1024 bits MNOS memory, peripheral circuits being developed according to the depletion-enrichment technology.

High-contrast gratings for long-wavelength laser integration on silicon

Science.gov (United States)

Sciancalepore, Corrado; Descos, Antoine; Bordel, Damien; Duprez, Hélène; Letartre, Xavier; Menezo, Sylvie; Ben Bakir, Badhise

2014-02-01

Silicon photonics is increasingly considered as the most promising way-out to the relentless growth of data traffic in today's telecommunications infrastructures, driving an increase in transmission rates and computing capabilities. This is in fact challenging the intrinsic limit of copper-based, short-reach interconnects and microelectronic circuits in data centers and server architectures to offer enough modulation bandwidth at reasonable power dissipation. In the context of the heterogeneous integration of III-V direct-bandgap materials on silicon, optics with high-contrast metastructures enables the efficient implementation of optical functions such as laser feedback, input/output (I/O) to active/passive components, and optical filtering, while heterogeneous integration of III-V layers provides sufficient optical gain, resulting in silicon-integrated laser sources. The latest ensure reduced packaging costs and reduced footprint for the optical transceivers, a key point for the short reach communications. The invited talk will introduce the audience to the latest breakthroughs concerning the use of high-contrast gratings (HCGs) for the integration of III-V-on-Si verticalcavity surface-emitting lasers (VCSELs) as well as Fabry-Perot edge-emitters (EELs) in the main telecom band around 1.55 μm. The strong near-field mode overlap within HCG mirrors can be exploited to implement unique optical functions such as dense wavelength division multiplexing (DWDM): a 16-λ100-GHz-spaced channels VCSEL array is demonstrated. On the other hand, high fabrication yields obtained via molecular wafer bonding of III-V alloys on silicon-on-insulator (SOI) conjugate excellent device performances with cost-effective high-throughput production, supporting industrial needs for a rapid research-to-market transfer.

Silicon epitaxy on textured double layer porous silicon by LPCVD

International Nuclear Information System (INIS)

Cai Hong; Shen Honglie; Zhang Lei; Huang Haibin; Lu Linfeng; Tang Zhengxia; Shen Jiancang

2010-01-01

Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521 cm -1 have a width of 7.8 cm -1 , which reveals the high crystalline quality of the silicon epitaxy.

Silicon microphotonic waveguides

International Nuclear Information System (INIS)

Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

2004-01-01

Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

Flexible FETs using ultrathin Si microwires embedded in solution processed dielectric and metal layers

Science.gov (United States)

Khan, S.; Yogeswaran, N.; Taube, W.; Lorenzelli, L.; Dahiya, R.

2015-12-01

This work presents a novel manufacturing route for obtaining high performance bendable field effect transistors (FET) by embedding silicon (Si) microwires (2.5 μm thick) in layers of solution-processed dielectric and metallic layers. The objective of this study is to explore heterogeneous integration of Si with polymers and to exploit the benefits of both microelectronics and printing technologies. Arrays of Si microwires are developed on silicon on insulator (SOI) wafers and transfer printed to polyimide (PI) substrate through a polydimethylsiloxane (PDMS) carrier stamp. Following the transfer printing of Si microwires, two different processing steps were developed to obtain top gate top contact and back gate top contact FETs. Electrical characterizations indicate devices having mobility as high as 117.5 cm2 V-1 s-1. The fabricated devices were also modeled using SILVACO Atlas. Simulation results show a trend in the electrical response similar to that of experimental results. In addition, a cyclic test was performed to demonstrate the reliability and mechanical robustness of the Si μ-wires on flexible substrates.

Flexible FETs using ultrathin Si microwires embedded in solution processed dielectric and metal layers

International Nuclear Information System (INIS)

Khan, S; Yogeswaran, N; Lorenzelli, L; Taube, W; Dahiya, R

2015-01-01

This work presents a novel manufacturing route for obtaining high performance bendable field effect transistors (FET) by embedding silicon (Si) microwires (2.5 μm thick) in layers of solution-processed dielectric and metallic layers. The objective of this study is to explore heterogeneous integration of Si with polymers and to exploit the benefits of both microelectronics and printing technologies. Arrays of Si microwires are developed on silicon on insulator (SOI) wafers and transfer printed to polyimide (PI) substrate through a polydimethylsiloxane (PDMS) carrier stamp. Following the transfer printing of Si microwires, two different processing steps were developed to obtain top gate top contact and back gate top contact FETs. Electrical characterizations indicate devices having mobility as high as 117.5 cm 2 V −1 s −1 . The fabricated devices were also modeled using SILVACO Atlas. Simulation results show a trend in the electrical response similar to that of experimental results. In addition, a cyclic test was performed to demonstrate the reliability and mechanical robustness of the Si μ-wires on flexible substrates. (paper)

Processing of n{sup +}/p{sup −}/p{sup +} strip detectors with atomic layer deposition (ALD) grown Al{sub 2}O{sub 3} field insulator on magnetic Czochralski silicon (MCz-si) substrates

Energy Technology Data Exchange (ETDEWEB)

Härkönen, J., E-mail: jaakko.harkonen@helsinki.fi [Helsinki Institute of Physics (Finland); Tuovinen, E. [Helsinki Institute of Physics (Finland); VTT Technical Research Centre of Finland, Microsystems and Nanoelectronics (Finland); Luukka, P.; Gädda, A.; Mäenpää, T.; Tuominen, E.; Arsenovich, T. [Helsinki Institute of Physics (Finland); Junkes, A. [Institute for Experimental Physics, University of Hamburg (Germany); Wu, X. [VTT Technical Research Centre of Finland, Microsystems and Nanoelectronics (Finland); Picosun Oy, Tietotie 3, FI-02150 Espoo Finland (Finland); Li, Z. [School of Materials Science and Engineering, Xiangtan University, Xiangtan, Hunan 411105 (China)

2016-08-21

Detectors manufactured on p-type silicon material are known to have significant advantages in very harsh radiation environment over n-type detectors, traditionally used in High Energy Physics experiments for particle tracking. In p-type (n{sup +} segmentation on p substrate) position-sensitive strip detectors, however, the fixed oxide charge in the silicon dioxide is positive and, thus, causes electron accumulation at the Si/SiO{sub 2} interface. As a result, unless appropriate interstrip isolation is applied, the n-type strips are short-circuited. Widely adopted methods to terminate surface electron accumulation are segmented p-stop or p-spray field implantations. A different approach to overcome the near-surface electron accumulation at the interface of silicon dioxide and p-type silicon is to deposit a thin film field insulator with negative oxide charge. We have processed silicon strip detectors on p-type Magnetic Czochralski silicon (MCz-Si) substrates with aluminum oxide (Al{sub 2}O{sub 3}) thin film insulator, grown with Atomic Layer Deposition (ALD) method. The electrical characterization by current–voltage and capacitance−voltage measurement shows reliable performance of the aluminum oxide. The final proof of concept was obtained at the test beam with 200 GeV/c muons. For the non-irradiated detector the charge collection efficiency (CCE) was nearly 100% with a signal-to-noise ratio (S/N) of about 40, whereas for the 2×10{sup 15} n{sub eq}/cm{sup 2} proton irradiated detector the CCE was 35%, when the sensor was biased at 500 V. These results are comparable with the results from p-type detectors with the p-spray and p-stop interstrip isolation techniques. In addition, interestingly, when the aluminum oxide was irradiated with Co-60 gamma-rays, an accumulation of negative fixed oxide charge in the oxide was observed.

The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

International Nuclear Information System (INIS)

Mohapatra, S K; Pradhan, K P; Sahu, P K; Pati, G S; Kumar, M R

2014-01-01

In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™. (paper)

The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

Science.gov (United States)

Mohapatra, S. K.; Pradhan, K. P.; Sahu, P. K.; Pati, G. S.; Kumar, M. R.

2014-12-01

In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.

Optimization of process parameter variations on leakage current in in silicon-oninsulator vertical double gate mosfet device

Directory of Open Access Journals (Sweden)

K.E. Kaharudin

2015-12-01

Full Text Available This paper presents a study of optimizing input process parameters on leakage current (IOFF in silicon-on-insulator (SOI Vertical Double-Gate,Metal Oxide Field-Effect-Transistor (MOSFET by using L36 Taguchi method. The performance of SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF value. An orthogonal array, main effects, signal-to-noise ratio (SNR and analysis of variance (ANOVA are utilized in order to analyze the effect of input process parameter variation on leakage current (IOFF. Based on the results, the minimum leakage current ((IOFF of SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION value at 434 µA/µm. Both the drive current (ION and leakage current (IOFF values yield a higher ION/IOFF ratio (48.22 x 106 for low power consumption application. Meanwhile, polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors with each of the contributing factor effects percentage of 59% and 25%.

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

International Nuclear Information System (INIS)

Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

2014-01-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

New dynamic silicon photonic components enabled by MEMS technology

Science.gov (United States)

Errando-Herranz, Carlos; Edinger, Pierre; Colangelo, Marco; Björk, Joel; Ahmed, Samy; Stemme, Göran; Niklaus, Frank; Gylfason, Kristinn B.

2018-02-01

Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

Porous silicon formation by hole injection from a back side p+/n junction for electrical insulation applications

International Nuclear Information System (INIS)

Fèvre, A; Menard, S; Defforge, T; Gautier, G

2016-01-01

In this paper, we propose to study the formation of porous silicon (PS) in low doped (1 × 10 14 cm −3 ) n-type silicon through hole injection from a back side p + /n junction in the dark. This technique is investigated within the framework of electrical insulation. Three different types of junctions are investigated. The first one is an epitaxial n-type layer grown on p + doped silicon wafer. The two other junctions are carried out by boron diffusion leading to p + regions with junction depths of 20 and 115 μm. The resulting PS morphology is a double layer with a nucleation layer (NL) and macropores fully filled with mesoporous material. This result is unusual for low doped n-type silicon. Morphology variations are described depending on the junction formation process, the electrolyte composition, the anodization current density and duration. In order to validate the more interesting industrial potentialities of the p + /n injection technique, a comparison is achieved with back side illumination in terms of resulting morphology and experiments confirm comparable results. Electrical characterizations of the double layer, including NL and fully filled macropores, are then performed. To our knowledge, this is the first electrical investigation in low doped n type silicon with this morphology. Compared to the bulk silicon, the measured electrical resistivities are 6–7 orders of magnitude higher at 373 K. (paper)

Automotive SOI-BCD Technology Using Bonded Wafers

International Nuclear Information System (INIS)

Himi, H.; Fujino, S.

2008-01-01

The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Optical microcavities based on surface modes in two-dimensional photonic crystals and silicon-on-insulator photonic crystals

DEFF Research Database (Denmark)

Xiao, Sanshui; Qiu, M.

2007-01-01

Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor is gr...... is gradually enhanced and the resonant frequency converges to that of the corresponding surface mode in the photonic crystals. These structures have potential applications such as sensing.......Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor...

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

Science.gov (United States)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Insulator layer formation in MgB2 SIS junctions

International Nuclear Information System (INIS)

Shimakage, H.; Tsujimoto, K.; Wang, Z.; Tonouchi, M.

2005-01-01

The dependence of current-voltage characteristics on thin film deposition conditions was investigated using MgB 2 /AlN/NbN SIS junctions. By increasing the substrate temperature in AlN insulator deposition, the current density decreased and the normal resistance increased. The results indicated that an additional insulator layer between the MgB 2 and AlN formed, either before or during the AlN deposition. The thickness of the additional insulator layer was increased with an increase in the AlN deposition temperature. From the dependence of current density on the thickness of AlN in low temperature depositions, the thickness of the additional insulator layer was estimated to be 1-1.5 nm when the AlN insulator was deposited from 0.14 to 0.7 nm. Moreover, with the current density of MgB 2 /AlN/MgB 2 SIS junctions, further insulator layer formation was confirmed

The silicon-silicon oxide multilayers utilization as intrinsic layer on pin solar cells

International Nuclear Information System (INIS)

Colder, H.; Marie, P.; Gourbilleau, F.

2008-01-01

Silicon nanostructures are promising candidate for the intrinsic layer on pin solar cells. In this work we report on new material: silicon-rich silicon oxide (SRSO) deposited by reactive magnetron sputtering of a pure silica target and an interesting structure: multilayers consisting of a stack of SRSO and pure silicon oxide layers. Two thicknesses of the SRSO sublayer, t SRSO , are studied 3 nm and 5 nm whereas the thickness of silica sublayer is maintaining at 3 nm. The presence of nanocrystallites of silicon, evidenced by X-Ray diffraction (XRD), leads to photoluminescence (PL) emission at room temperature due to the quantum confinement of the carriers. The PL peak shifts from 1.3 eV to 1.5 eV is correlated to the decreasing of t SRSO from 5 nm down to 3 nm. In the purpose of their potential utilization for i-layer, the optical properties are studied by absorption spectroscopy. The achievement a such structures at promising absorption properties. Moreover by favouring the carriers injection by the tunnel effect between silicon nanograins and silica sublayers, the multilayers seem to be interesting for solar cells

Ion beam studied of silicon oxynitride and silicon nitroxide thin layers

International Nuclear Information System (INIS)

Oude Elferink, J.B.

1989-01-01

In this the processes occurring during high temperature treatments of silicon oxynitride and silicon oxide layers are described. Oxynitride layers with various atomic oxygen to nitrogen concentration ration (O/N) are considered. The high energy ion beam techniques Rutherford backscattering spectroscopy, elastic recoil detection and nuclear reaction analysis have been used to study the layer structures. A detailed discussion of these ion beam techniques is given. Numerical methods used to obtain quantitative data on elemental compositions and depth profiles are described. The electrical compositions and depth profiles are described. The electrical properties of silicon nitride films are known to be influenced by the behaviour of hydrogen in the film during high temperature anneling. Investigations of the behaviour of hydrogen are presented. Oxidation of silicon (oxy)nitride films in O 2 /H 2 0/HCl and nitridation of silicon dioxide films in NH 3 are considered since oxynitrides are applied as an oxidation mask in the LOCOS (Local oxidation of silicon) process. The nitridation of silicon oxide layers in an ammonia ambient is considered. The initial stage and the dependence on the oxide thickness of nitrogen and hydrogen incorporation are discussed. Finally, oxidation of silicon oxynitride layers and of silicon oxide layers are compared. (author). 76 refs.; 48 figs.; 1 tab

Material synthesis for silicon integrated-circuit applications using ion implantation

Science.gov (United States)

Lu, Xiang

As devices scale down into deep sub-microns, the investment cost and complexity to develop more sophisticated device technologies have increased substantially. There are some alternative potential technologies, such as silicon-on-insulator (SOI) and SiGe alloys, that can help sustain this staggering IC technology growth at a lower cost. Surface SiGe and SiGeC alloys with germanium peak composition up to 16 atomic percent are formed using high-dose ion implantation and subsequent solid phase epitaxial growth. RBS channeling spectra and cross-sectional TEM studies show that high quality SiGe and SiGeC crystals with 8 atomic percent germanium concentration are formed at the silicon surface. Extended defects are formed in SiGe and SiGeC with 16 atomic percent germanium concentration. X-ray diffraction experiments confirm that carbon reduces the lattice strain in SiGe alloys but without significant crystal quality improvement as detected by RBS channeling spectra and XTEM observations. Separation by plasma implantation of oxygen (SPIMOX) is an economical method for SOI wafer fabrication. This process employs plasma immersion ion implantation (PIII) for the implantation of oxygen ions. The implantation rate for Pm is considerably higher than that of conventional implantation. The feasibility of SPIMOX has been demonstrated with successful fabrication of SOI structures implementing this process. Secondary ion mass spectrometry (SIMS) analysis and cross-sectional transmission electron microscopy (XTEM) micrographs of the SPIMOX sample show continuous buried oxide under single crystal overlayer with sharp silicon/oxide interfaces. The operational phase space of implantation condition, oxygen dose and annealing requirement has been identified. Physical mechanisms of hydrogen induced silicon surface layer cleavage have been investigated using a combination of microscopy and hydrogen profiling techniques. The evolution of the silicon cleavage phenomenon is recorded by a series

Compact wavelength-insensitive fabrication-tolerant silicon-on-insulator beam splitter.

Science.gov (United States)

Rasigade, Gilles; Le Roux, Xavier; Marris-Morini, Delphine; Cassan, Eric; Vivien, Laurent

2010-11-01

A star coupler-based beam splitter for rib waveguides is reported. A design method is presented and applied in the case of silicon-on-insulator rib waveguides. Experimental results are in good agreement with simulations. Excess loss lower than 1 dB is experimentally obtained for star coupler lengths from 0.5 to 1 μm. Output balance is better than 1 dB, which is the measurement accuracy, and broadband transmission is obtained over 90 nm.

X-ray and scanning electron microscopic investigation of porous silicon and silicon epitaxial layers grown on porous silicon

International Nuclear Information System (INIS)

Wierzchowski, W.; Pawlowska, M.; Nossarzewska-Orlowska, E.; Brzozowski, A.; Wieteska, K.; Graeff, W.

1998-01-01

The 1 to 5 μm thick layers of porous silicon and epitaxial layers grown on porous silicon were studied by means of X-ray diffraction methods, realised with a wide use of synchrotron source and scanning microscopy. The results of x-ray investigation pointed the difference of lateral periodicity between the porous layer and the substrate. It was also found that the deposition of epitaxial layer considerably reduced the coherence of porous fragments. A number of interface phenomena was also observed in section and plane wave topographs. The scanning electron microscopic investigation of cleavage faces enabled direct evaluation of porous layer thickness and revealed some details of their morphology. The scanning observation of etched surfaces of epitaxial layers deposited on porous silicon revealed dislocations and other defects not reasonable in the X-ray topographs. (author)

Epitaxial growth of silicon for layer transfer

Science.gov (United States)

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Nanogap biosensors for electrical and label-free detection of biomolecular interactions

International Nuclear Information System (INIS)

Kyu Kim, Sang; Cho, Hyunmin; Park, Hye-Jung; Kwon, Dohyoung; Min Lee, Jeong; Hyun Chung, Bong

2009-01-01

We demonstrate nanogap biosensors for electrical and label-free detection of biomolecular interactions. Parallel fabrication of nanometer distance gaps has been achieved using a silicon anisotropic wet etching technique on a silicon-on-insulator (SOI) wafer with a finely controllable silicon device layer. Since silicon anisotropic wet etching resulted in a trapezoid-shaped structure whose end became narrower during the etching, the nanogap structure was simply fabricated on the device layer of a SOI wafer. The nanogap devices were individually addressable and a gap size of less than 60 nm was obtained. We demonstrate that the nanogap biosensors can electrically detect biomolecular interactions such as biotin/streptavidin and antigen/antibody pairs. The nanogap devices show a current increase when the proteins are bound to the surface. The current increases proportionally depending upon the concentrations of the molecules in the range of 100 fg ml -1 -100 ng ml -1 at 1 V bias. It is expected that the nanogap developed here could be a highly sensitive biosensor platform for label-free detection of biomolecular interactions.

Substrate and p-layer effects on polymorphous silicon solar cells

Directory of Open Access Journals (Sweden)

Abolmasov S.N.

2014-07-01

Full Text Available The influence of textured transparent conducting oxide (TCO substrate and p-layer on the performance of single-junction hydrogenated polymorphous silicon (pm-Si:H solar cells has been addressed. Comparative studies were performed using p-i-n devices with identical i/n-layers and back reflectors fabricated on textured Asahi U-type fluorine-doped SnO2, low-pressure chemical vapor deposited (LPCVD boron-doped ZnO and sputtered/etched aluminum-doped ZnO substrates. The p-layers were hydrogenated amorphous silicon carbon and microcrystalline silicon oxide. As expected, the type of TCO and p-layer both have a great influence on the initial conversion efficiency of the solar cells. However they have no effect on the defect density of the pm-Si:H absorber layer.

Silver nanoparticle formation in thin oxide layer on silicon by silver-negative-ion implantation for Coulomb blockade at room temperature

International Nuclear Information System (INIS)

Tsuji, Hiroshi; Arai, Nobutoshi; Matsumoto, Takuya; Ueno, Kazuya; Gotoh, Yasuhito; Adachi, Kouichiro; Kotaki, Hiroshi; Ishikawa, Junzo

2004-01-01

Formation of silver nanoparticles formed by silver negative-ion implantation in a thin SiO 2 layer and its I-V characteristics were investigated for development single electron devices. In order to obtain effective Coulomb blockade phenomenon at room temperature, the isolated metal nanoparticles should be in very small size and be formed in a thin insulator layer such as gate oxide on the silicon substrate. Therefore, conditions of a fine particles size, high particle density and narrow distribution should be controlled at their formation without any electrical breakdown of the thin insulator layer. We have used a negative-ion implantation technique with an advantage of 'charge-up free' for insulators, with which no breakdown of thin oxide layer on Si was obtained. In the I-V characteristics with Au electrode, the current steps were observed with a voltage interval of about 0.12 V. From the step voltage the corresponded capacitance was calculated to be 0.7 aF. In one nanoparticle system, this value of capacitance could be given by a nanoparticle of about 3 nm in diameter. This consideration is consistent to the measured particle size in the cross-sectional TEM observation. Therefore, the observed I-V characteristics with steps are considered to be Coulomb staircase by the Ag nanoparticles

Broadband non-polarizing beam splitter based on guided mode resonance effect

Science.gov (United States)

Ma, Jian-Yong; Xu, Cheng; Qiang, Ying-Huai; Zhu, Ya-Bo

2011-10-01

A broadband non-polarizing beam splitter (NPBS) operating in the telecommunication C+L band is designed by using the guided mode resonance effect of periodic silicon-on-insulator (SOI) elements. It is shown that this double layer SOI structure can provide ~50/50 beam ratio with the maximum divergences between reflection and transmission being less than 8% over the spectrum of 1.4 μm~1.7 μm and 1% in the telecommunication band for both TE and TM polarizations. The physical basis of this broadband non-polarizing property is on the simultaneous excitation of the TE and TM strong modulation waveguide modes near the designed spectrum band. Meanwhile, the electric field distributions for both TE and TM polarizations verify the resonant origin of spectrum in the periodic SOI structure. Furthermore, it is demonstrated with our calculations that the beam splitter proposed here is tolerant to the deviations of incident angle and structure parameters, which make it very easy to be fabricated with current IC technology.

Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

International Nuclear Information System (INIS)

Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

2006-01-01

A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

Realization of an ultra-compact polarization beam splitter using asymmetric MMI based on silicon nitride / silicon-on-insulator platform.

Science.gov (United States)

Sun, Xiao; Aitchison, J Stewart; Mojahedi, Mo

2017-04-03

We have experimentally demonstrated a compact polarization beam splitter (PBS) based on the silicon nitride/silicon-on-insulator platform using the recently proposed augmented-low-index-guiding (ALIG) waveguide structure. The two orthogonal polarizations are split in an asymmetric multimode interference (MMI) section, which was 1.6 μm wide and 4.8 μm long. The device works well over the entire C-band wavelength range and has a measured low insertion loss of less than 1 dB. The polarization extinction ratio at the Bar Port is approximately 17 dB and at the Cross Port is approximately 25 dB. The design of the device is robust and has a good fabrication tolerance.

High-density oxidized porous silicon

International Nuclear Information System (INIS)

Gharbi, Ahmed; Souifi, Abdelkader; Remaki, Boudjemaa; Halimaoui, Aomar; Bensahel, Daniel

2012-01-01

We have studied oxidized porous silicon (OPS) properties using Fourier transform infraRed (FTIR) spectroscopy and capacitance–voltage C–V measurements. We report the first experimental determination of the optimum porosity allowing the elaboration of high-density OPS insulators. This is an important contribution to the research of thick integrated electrical insulators on porous silicon based on an optimized process ensuring dielectric quality (complete oxidation) and mechanical and chemical reliability (no residual pores or silicon crystallites). Through the measurement of the refractive indexes of the porous silicon (PS) layer before and after oxidation, one can determine the structural composition of the OPS material in silicon, air and silica. We have experimentally demonstrated that a porosity approaching 56% of the as-prepared PS layer is required to ensure a complete oxidation of PS without residual silicon crystallites and with minimum porosity. The effective dielectric constant values of OPS materials determined from capacitance–voltage C–V measurements are discussed and compared to FTIR results predictions. (paper)

Large-scale quantum photonic circuits in silicon

Directory of Open Access Journals (Sweden)

Harris Nicholas C.

2016-08-01

Full Text Available Quantum information science offers inherently more powerful methods for communication, computation, and precision measurement that take advantage of quantum superposition and entanglement. In recent years, theoretical and experimental advances in quantum computing and simulation with photons have spurred great interest in developing large photonic entangled states that challenge today’s classical computers. As experiments have increased in complexity, there has been an increasing need to transition bulk optics experiments to integrated photonics platforms to control more spatial modes with higher fidelity and phase stability. The silicon-on-insulator (SOI nanophotonics platform offers new possibilities for quantum optics, including the integration of bright, nonclassical light sources, based on the large third-order nonlinearity (χ(3 of silicon, alongside quantum state manipulation circuits with thousands of optical elements, all on a single phase-stable chip. How large do these photonic systems need to be? Recent theoretical work on Boson Sampling suggests that even the problem of sampling from e30 identical photons, having passed through an interferometer of hundreds of modes, becomes challenging for classical computers. While experiments of this size are still challenging, the SOI platform has the required component density to enable low-loss and programmable interferometers for manipulating hundreds of spatial modes.

Mode converter based on an inverse taper for multimode silicon nanophotonic integrated circuits.

Science.gov (United States)

Dai, Daoxin; Mao, Mao

2015-11-02

An inverse taper on silicon is proposed and designed to realize an efficient mode converter available for the connection between multimode silicon nanophotonic integrated circuits and few-mode fibers. The present mode converter has a silicon-on-insulator inverse taper buried in a 3 × 3μm(2) SiN strip waveguide to deal with not only for the fundamental mode but also for the higher-order modes. The designed inverse taper enables the conversion between the six modes (i.e., TE(11), TE(21), TE(31), TE(41), TM(11), TM(12)) in a 1.4 × 0.22μm(2) multimode SOI waveguide and the six modes (like the LP(01), LP(11a), LP(11b) modes in a few-mode fiber) in a 3 × 3μm(2) SiN strip waveguide. The conversion efficiency for any desired mode is higher than 95.6% while any undesired mode excitation ratio is lower than 0.5%. This is helpful to make multimode silicon nanophotonic integrated circuits (e.g., the on-chip mode (de)multiplexers developed well) available to work together with few-mode fibers in the future.

Effect of non-ideal clamping shape on the resonance frequencies of silicon nanocantilevers

Energy Technology Data Exchange (ETDEWEB)

Guillon, Samuel; Saya, Daisuke; Mazenq, Laurent; Nicu, Liviu [CNRS, LAAS, 7 Avenue du Colonel Roche, F-31077 Toulouse Cedex 4 (France); Perisanu, Sorin; Vincent, Pascal [LPMCN, Universite Claude Bernard Lyon 1 et CNRS, 43 boulevard du 11 novembre 1918, 69622 Villeurbanne Cedex (France); Lazarus, Arnaud; Thomas, Olivier, E-mail: sguillon@laas.fr [Structural Mechanics and Coupled Systems Laboratory, Conservatoire National des Arts et Metiers, 2 rue Conte, 75003 Paris (France)

2011-06-17

In this paper, we investigate the effects of non-ideal clamping shapes on the dynamic behavior of silicon nanocantilevers. We fabricated silicon nanocantilevers using silicon on insulator (SOI) wafers by employing stepper ultraviolet (UV) lithography, which permits a resolution of under 100 nm. The nanocantilevers were driven by electrostatic force inside a scanning electron microscope (SEM). Both lateral and out-of-plane resonance frequencies were visually detected with the SEM. Next, we discuss overhanging of the cantilever support and curvature at the clamping point in the silicon nanocantilevers, which generally arises in the fabrication process. We found that the fundamental out-of-plane frequency of a realistically clamped cantilever is always lower than that for a perfectly clamped cantilever, and depends on the cantilever width and the geometry of the clamping point structure. Using simulation with the finite-elements method, we demonstrate that this discrepancy is attributed to the particular geometry of the clamping point (non-zero joining curvatures and a flexible overhanging) that is obtained in the fabrication process. The influence of the material orthotropy is also investigated and is shown to be negligible.

Extreme temperature stability of thermally insulating graphene-mesoporous-silicon nanocomposite

Science.gov (United States)

Kolhatkar, Gitanjali; Boucherif, Abderraouf; Rahim Boucherif, Abderrahim; Dupuy, Arthur; Fréchette, Luc G.; Arès, Richard; Ruediger, Andreas

2018-04-01

We demonstrate the thermal stability and thermal insulation of graphene-mesoporous-silicon nanocomposites (GPSNC). By comparing the morphology of GPSNC carbonized at 650 °C as-formed to that after annealing, we show that this nanocomposite remains stable at temperatures as high as 1050 °C due to the presence of a few monolayers of graphene coating on the pore walls. This does not only make this material compatible with most thermal processes but also suggests applications in harsh high temperature environments. The thermal conductivity of GPSNCs carbonized at temperatures in the 500 °C-800 °C range is determined through Raman spectroscopy measurements. They indicate that the thermal conductivity of the composite is lower than that of silicon, with a value of 13 ± 1 W mK-1 at room temperature, and not affected by the thin graphene layer, suggesting a role of the high concentration of carbon related-defects as indicated by the high intensity of the D-band compared to G-band of the Raman spectra. This morphological stability at high temperature combined with a high thermal insulation make GPSNC a promising candidate for a broad range of applications including microelectromechanical systems and thermal effect microsystems such as flow sensors or IR detectors. Finally, at 120 °C, the thermal conductivity remains equal to that at room temperature, attesting to the potential of using our nanocomposite in devices that operate at high temperatures such as microreactors for distributed chemical conversion, solid oxide fuel cells, thermoelectric devices or thermal micromotors.

Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

Science.gov (United States)

Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

2009-01-01

This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

Optimal Design of an Ultrasmall SOI-Based 1 × 8 Flat-Top AWG by Using an MMI

Directory of Open Access Journals (Sweden)

Hongqiang Li

2013-01-01

Full Text Available Four methods based on a multimode interference (MMI structure are optimally designed to flatten the spectral response of silicon-on-insulator- (SOI- based arrayed-waveguide grating (AWG applied in a demodulation integration microsystem. In the design for each method, SOI is selected as the material, the beam propagation method is used, and the performances (including the 3 dB passband width, the crosstalk, and the insertion loss of the flat-top AWG are studied. Moreover, the output spectrum responses of AWGs with or without a flattened structure are compared. The results show that low insertion loss, crosstalk, and a flat and efficient spectral response are simultaneously achieved for each kind of structure. By comparing the four designs, the design that combines a tapered MMI with tapered input/output waveguides, which has not been previously reported, was shown to yield better results than others. The optimized design reduced crosstalk to approximately −21.9 dB and had an insertion loss of −4.36 dB and a 3 dB passband width, that is, approximately 65% of the channel spacing.

Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

International Nuclear Information System (INIS)

Dehzangi, Arash; Larki, Farhad; Naseri, Mahmud G.; Navasery, Manizheh; Majlis, Burhanuddin Y.; Razip Wee, Mohd F.; Halimah, M.K.; Islam, Md. Shabiul; Md Ali, Sawal H.; Saion, Elias

2015-01-01

Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated

Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

Energy Technology Data Exchange (ETDEWEB)

Dehzangi, Arash, E-mail: arashd53@hotmail.com [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Larki, Farhad [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Naseri, Mahmud G. [Department of Physics, Faculty of Science, Malayer University, Malayer, Hamedan (Iran, Islamic Republic of); Navasery, Manizheh [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Majlis, Burhanuddin Y.; Razip Wee, Mohd F. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Halimah, M.K. [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Islam, Md. Shabiul; Md Ali, Sawal H. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Saion, Elias [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia)

2015-04-15

Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated.

Ultrathin Oxide Passivation Layer by Rapid Thermal Oxidation for the Silicon Heterojunction Solar Cell Applications

Directory of Open Access Journals (Sweden)

Youngseok Lee

2012-01-01

Full Text Available It is difficult to deposit extremely thin a-Si:H layer in heterojunction with intrinsic thin layer (HIT solar cell due to thermal damage and tough process control. This study aims to understand oxide passivation mechanism of silicon surface using rapid thermal oxidation (RTO process by examining surface effective lifetime and surface recombination velocity. The presence of thin insulating a-Si:H layer is the key to get high Voc by lowering the leakage current (I0 which improves the efficiency of HIT solar cell. The ultrathin thermal passivation silicon oxide (SiO2 layer was deposited by RTO system in the temperature range 500–950°C for 2 to 6 minutes. The thickness of the silicon oxide layer was affected by RTO annealing temperature and treatment time. The best value of surface recombination velocity was recorded for the sample treated at a temperature of 850°C for 6 minutes at O2 flow rate of 3 Lpm. A surface recombination velocity below 25 cm/s was obtained for the silicon oxide layer of 4 nm thickness. This ultrathin SiO2 layer was employed for the fabrication of HIT solar cell structure instead of a-Si:H, (i layer and the passivation and tunneling effects of the silicon oxide layer were exploited. The photocurrent was decreased with the increase of illumination intensity and SiO2 thickness.

Theoretical model for the detection of charged proteins with a silicon-on-insulator sensor

International Nuclear Information System (INIS)

Birner, S; Uhl, C; Bayer, M; Vogl, P

2008-01-01

For a bio-sensor device based on a silicon-on-insulator structure, we calculate the sensitivity to specific charge distributions in the electrolyte solution that arise from protein binding to the semiconductor surface. This surface is bio-functionalized with a lipid layer so that proteins can specifically bind to the headgroups of the lipids on the surface. We consider charged proteins such as the green fluorescent protein (GFP) and artificial proteins that consist of a variable number of aspartic acids. Specifically, we calculate self-consistently the spatial charge and electrostatic potential distributions for different ion concentrations in the electrolyte. We fully take into account the quantum mechanical charge density in the semiconductor. We determine the potential change at the binding sites as a function of protein charge and ionic strength. Comparison with experiment is generally very good. Furthermore, we demonstrate the superiority of the full Poisson-Boltzmann equation by comparing its results to the simplified Debye-Hueckel approximation

Evaluation of a silicon 5 MHz p–n diode actuator with a laterally vibrating extensional mode

Science.gov (United States)

Miyazaki, Fumito; Baba, Kazuki; Tanigawa, Hiroshi; Furutsuka, Takashi; Suzuki, Kenichiro

2018-05-01

In this paper, we describe p–n diode actuators that are laterally driven by the force induced in a depletion layer. The previously reported p–n diode actuators have been vertically driven. Because the resonant frequency depends on the thickness of the vibrating plate, the integration of resonators with different frequencies on a chip has been difficult. The resonators in this work are driven laterally by using length-extensional vibration. We have developed a compact model based on an analytical expression, in which p–n diode actuators are driven by the forces induced by the spread of the depletion layer. The deflection generated by the p–n diode actuators was proportional to the ratio of the depletion layer width to the resonator thickness as well as the position of the p–n junction. Good agreement of experimental results with the theory was confirmed by comparing the measured values for silicon p–n diode rectangular-plate actuators fabricated using a silicon-on-insulator (SOI) substrate. The displacement amplitude of the actuators was proportional to the DC bias, while the resonant frequency was independent of the DC bias. The latter characteristic is very different from that of widely used electrostatic actuators. Although the amplitude of the actuator measured in this work was very small, it is expected that the amplitude will increase greatly by increasing the doping of the p–n diode actuators.

Development of radiation hard CMOS active pixel sensors for HL-LHC

International Nuclear Information System (INIS)

Pernegger, Heinz

2016-01-01

New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

Measure Guideline: Incorporating Thick Layers of Exterior Rigid Insulation on Walls

Energy Technology Data Exchange (ETDEWEB)

Lstiburek, Joseph [Building Science Corporation, Westford, MA (United States); Baker, Peter [Building Science Corporation, Westford, MA (United States)

2015-04-01

This measure guideline provides information about the design and construction of wall assemblies that use layers of rigid exterior insulation thicker than 1-½ inches and that require a secondary cladding attachment location exterior to the insulation. The guideline is separated into several distinct sections that cover: fundamental building science principles relating to the use of exterior insulation on wall assemblies; design principles for tailoring this use to the specific project goals and requirements; and construction detailing to increase understanding about implementing the various design elements.

Thermally-insulating layer for nuclear reactors

International Nuclear Information System (INIS)

1975-01-01

The thermally-insulating layer has been designed both for insulating surfaces within the core of a nuclear reactor and transmitting loads such as the core-weight. Said layer comprises a layer of bricks and a layer of tiles with smaller clearance between the tiles than between the bricks, the latter having a reduced cross-section against the tiles so as to be surrounded by relatively large interconnected ducts forming a continuous chamber behind the tile-layer in order to induce a substantial decreases in the transverse flow of the reactor-core coolant. The core preferably comprises hexagonal columns supported by rhomb-shaped plates, with channels distributed so as to mix the coolant of twelve columns. The plates are separated from support-tiles by means of pillars [fr

Development of advanced material composites for use as internal insulation for LH2 tanks (gas layer concept)

Science.gov (United States)

Gille, J. P.

1972-01-01

A program is described that was conducted to develop an internal insulation system for potential application to the liquid hydrogen tanks of a reusable booster, where the tanks would be subjected to repeated high temperatures. The design of the internal insulation is based on a unique gas layer concept, in which capillary or surface tension effects are used to maintain a stable gas layer, within a cellular core structure, between the tank wall and the contained liquid hydrogen. Specific objectives were to select materials for insulation systems that would be compatible with wall temperatures of 350 F and 650 F during reentry into the earth's atmosphere, and to fabricate and test insulation systems under conditions simulating the operating environment. A materials test program was conducted to evaluate the properties of candidate materials at elevated temperatures and at the temperature of liquid hydrogen, and to determine the compatibility of the materials with a hydrogen atmosphere at the appropriate elevated temperature. The materials that were finally selected included Kapton polyimide films, silicone adhesives, fiber glass batting, and in the case of the 350 F system, Teflon film.

In situ nanoscale refinement by highly controllable etching of the (111) silicon crystal plane and its influence on the enhanced electrical property of a silicon nanowire

International Nuclear Information System (INIS)

Gong Yibin; Dai Pengfei; Gao Anran; Li Tie; Zhou Ping; Wang Yuelin

2011-01-01

Nanoscale refinement on a (100) oriented silicon-on-insulator (SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide (TMAH, 25 wt%) anisotropic silicon etchant, with temperature kept at 50 °C to achieve precise etching of the (111) crystal plane. Specifically for a silicon nanowire (SiNW) with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral (2.3 nm/min) and vertical (1.7 nm/min) dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor (FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the (111) plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields. (semiconductor materials)

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

Ultrathin Oxide Passivation Layer by Rapid Thermal Oxidation for the Silicon Heterojunction Solar Cell Applications

OpenAIRE

Lee, Youngseok; Oh, Woongkyo; Dao, Vinh Ai; Hussain, Shahzada Qamar; Yi, Junsin

2012-01-01

It is difficult to deposit extremely thin a-Si:H layer in heterojunction with intrinsic thin layer (HIT) solar cell due to thermal damage and tough process control. This study aims to understand oxide passivation mechanism of silicon surface using rapid thermal oxidation (RTO) process by examining surface effective lifetime and surface recombination velocity. The presence of thin insulating a-Si:H layer is the key to get high Voc by lowering the leakage current (I0) which improves the efficie...

Process optimization of a deep trench isolation structure for high voltage SOI devices

International Nuclear Information System (INIS)

Zhu Kuiying; Qian Qinsong; Zhu Jing; Sun Weifeng

2010-01-01

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology. (semiconductor devices)

Rapid growth of single-layer graphene on the insulating substrates by thermal CVD

Energy Technology Data Exchange (ETDEWEB)

Chen, C.Y. [Faculty of Materials Science and Engineering, Kunming University of Science and Technology, Kunming 650093 (China); Key Laboratory of Marine Materials and Related Technologies, Zhejiang Key Laboratory of Marine Materials and Protective Technologies, Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Dai, D.; Chen, G.X.; Yu, J.H. [Key Laboratory of Marine Materials and Related Technologies, Zhejiang Key Laboratory of Marine Materials and Protective Technologies, Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Nishimura, K. [Key Laboratory of Marine Materials and Related Technologies, Zhejiang Key Laboratory of Marine Materials and Protective Technologies, Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Advanced Nano-processing Engineering Lab, Mechanical Systems Engineering, Kogakuin University (Japan); Lin, C.-T. [Key Laboratory of Marine Materials and Related Technologies, Zhejiang Key Laboratory of Marine Materials and Protective Technologies, Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Jiang, N., E-mail: jiangnan@nimte.ac.cn [Key Laboratory of Marine Materials and Related Technologies, Zhejiang Key Laboratory of Marine Materials and Protective Technologies, Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhan, Z.L., E-mail: zl_zhan@sohu.com [Faculty of Materials Science and Engineering, Kunming University of Science and Technology, Kunming 650093 (China)

2015-08-15

Highlights: • A rapid thermal CVD process has been developed to directly grow graphene on the insulating substrates. • The treating time consumed is ≈25% compared to conventional CVD procedure. • Single-layer and few-layer graphene can be formed on quartz and SiO{sub 2}/Si substrates, respectively. • The formation of thinner graphene at the interface is due to the fast precipitation rate of carbon atoms during cooling. - Abstract: The advance of CVD technique to directly grow graphene on the insulating substrates is particularly significant for further device fabrication. As graphene is catalytically grown on metal foils, the degradation of the sample properties is unavoidable during transfer of graphene on the dielectric layer. Moreover, shortening the treatment time as possible, while achieving single-layer growth of graphene, is worthy to be investigated for promoting the efficiency of mass production. Here we performed a rapid heating/cooling process to grow graphene films directly on the insulating substrates by thermal CVD. The treating time consumed is ≈25% compared to conventional CVD procedure. In addition, we found that high-quality, single-layer graphene can be formed on quartz, but on SiO{sub 2}/Si substrate only few-layer graphene can be obtained. The pronounced substrate effect is attributed to the different dewetting behavior of Ni films on the both substrates at 950 °C.

Thermoelectric characteristics of Pt-silicide/silicon multi-layer structured p-type silicon

International Nuclear Information System (INIS)

Choi, Wonchul; Jun, Dongseok; Kim, Soojung; Shin, Mincheol; Jang, Moongyu

2015-01-01

Electric and thermoelectric properties of silicide/silicon multi-layer structured devices were investigated with the variation of silicide/silicon heterojunction numbers from 3 to 12 layers. For the fabrication of silicide/silicon multi-layered structure, platinum and silicon layers are repeatedly sputtered on the (100) silicon bulk substrate and rapid thermal annealing is carried out for the silicidation. The manufactured devices show ohmic current–voltage (I–V) characteristics. The Seebeck coefficient of bulk Si is evaluated as 195.8 ± 15.3 μV/K at 300 K, whereas the 12 layered silicide/silicon multi-layer structured device is evaluated as 201.8 ± 9.1 μV/K. As the temperature increases to 400 K, the Seebeck coefficient increases to 237.2 ± 4.7 μV/K and 277.0 ± 1.1 μV/K for bulk and 12 layered devices, respectively. The increase of Seebeck coefficient in multi-layered structure is mainly attributed to the electron filtering effect due to the Schottky barrier at Pt-silicide/silicon interface. At 400 K, the thermal conductivity is reduced by about half of magnitude compared to bulk in multi-layered device which shows the efficient suppression of phonon propagation by using Pt-silicide/silicon hetero-junctions. - Highlights: • Silicide/silicon multi-layer structured is proposed for thermoelectric devices. • Electric and thermoelectric properties with the number of layer are investigated. • An increase of Seebeck coefficient is mainly attributed the Schottky barrier. • Phonon propagation is suppressed with the existence of Schottky barrier. • Thermal conductivity is reduced due to the suppression of phonon propagation

DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

Directory of Open Access Journals (Sweden)

V. A. Solodukha

2016-01-01

Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

Interfacing Dielectric-Loaded Plasmonic and Silicon Photonic Waveguides: Theoretical Analysis and Experimental Demonstration

DEFF Research Database (Denmark)

Tsilipakos, O.; Pitilakis, A.; Yioultsis, T. V.

2012-01-01

A comprehensive theoretical analysis of end-fire coupling between dielectric-loaded surface plasmon polariton and rib/wire silicon-on-insulator (SOI) waveguides is presented. Simulations are based on the 3-D vector finite element method. The geometrical parameters of the interface are varied...... in order to identify the ones leading to optimum performance, i.e., maximum coupling efficiency. Fabrication tolerances about the optimum parameter values are also assessed. In addition, the effect of a longitudinal metallic stripe gap on coupling efficiency is quantified, since such gaps have been...

Silicon on insulator by ion implantation: A dream or a reality

Energy Technology Data Exchange (ETDEWEB)

Pinizzotto, R F [Ultrastructure, Inc., Richardson, TX (USA)

1985-03-01

One method of producing a silicon-on-oxide structure is to implant a sufficient dose of oxygen into a conventional silicon substrate to synthesize a layer of SiO/sub 2/ just below the surface. If the proper implant conditions are maintained, the top silicon layer will be a single crystal. The required doses are large, but the use of commercially available medium current implanters can reduce the time to 25 minutes per wafer. This adds about $ 10 per chip in process related costs. A very large implanter (100 mA analyzed beam) may not be the best approach for scaling up the process. The power in the beam and the power required for operation of the machine are both enormous. A more conservative approach of using multiple medium current implanters may prove to be more economical in the long run.

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

International Nuclear Information System (INIS)

Li Jin; Liu Hongxia; Li Bin; Cao Lei; Yuan Bo

2010-01-01

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a 'rollup' in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. (semiconductor devices)

Helium ion beam induced electron emission from insulating silicon nitride films under charging conditions

Science.gov (United States)

Petrov, Yu. V.; Anikeva, A. E.; Vyvenko, O. F.

2018-06-01

Secondary electron emission from thin silicon nitride films of different thicknesses on silicon excited by helium ions with energies from 15 to 35 keV was investigated in the helium ion microscope. Secondary electron yield measured with Everhart-Thornley detector decreased with the irradiation time because of the charging of insulating films tending to zero or reaching a non-zero value for relatively thick or thin films, respectively. The finiteness of secondary electron yield value, which was found to be proportional to electronic energy losses of the helium ion in silicon substrate, can be explained by the electron emission excited from the substrate by the helium ions. The method of measurement of secondary electron energy distribution from insulators was suggested, and secondary electron energy distribution from silicon nitride was obtained.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

Science.gov (United States)

Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.

2009-12-01

The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.

Broadband non-polarizing beam splitter based on guided mode resonance effect

International Nuclear Information System (INIS)

Ma Jian-Yong; Xu Cheng; Qiang Ying-Huai; Zhu Ya-Bo

2011-01-01

A broadband non-polarizing beam splitter (NPBS) operating in the telecommunication C+L band is designed by using the guided mode resonance effect of periodic silicon-on-insulator (SOI) elements. It is shown that this double layer SOI structure can provide ∼50/50 beam ratio with the maximum divergences between reflection and transmission being less than 8% over the spectrum of 1.4 μm∼1.7 μm and 1% in the telecommunication band for both TE and TM polarizations. The physical basis of this broadband non-polarizing property is on the simultaneous excitation of the TE and TM strong modulation waveguide modes near the designed spectrum band. Meanwhile, the electric field distributions for both TE and TM polarizations verify the resonant origin of spectrum in the periodic SOI structure. Furthermore, it is demonstrated with our calculations that the beam splitter proposed here is tolerant to the deviations of incident angle and structure parameters, which make it very easy to be fabricated with current IC technology. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

International Nuclear Information System (INIS)

Cortés, I; Toulon, G; Morancho, F; Hugonnard-Bruyere, E; Villard, B; Toren, W J

2011-01-01

This paper focuses on the design and optimization of different power P-channel LDMOS transistors (V BR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (R on-sp /V BR trade-off) and dynamic (R on × Q g ) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor R on-sp /V BR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance

Thermal insulation layer for the vacuum containers of a thermonuclear device

International Nuclear Information System (INIS)

Nishikawa, Masana; Yamada, Masao; Kameari, Akihisa; Niikura, Setsuo.

1980-01-01

Purpose: To prevent temperature rise of a thermal insulation layer for a vacuum container of a thermonuclear device higher than allowable value when irradiated by neutron by constructing the layer of a cooling unit in thermal insulation material. Constitution: A metal plate attached with cooling pipes is buried in a thermal insulation material forming a thermal insulation layer to form the layer provided between a vacuum container of a thermonuclear device and a shield. (Yoshihara, H.)

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

Science.gov (United States)

Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

2018-02-01

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

Experimental verification of layout physical verification of silicon photonics

Science.gov (United States)

El Shamy, Raghi S.; Swillam, Mohamed A.

2018-02-01

Silicon photonics have been approved as one of the best platforms for dense integration of photonic integrated circuits (PICs) due to the high refractive index contrast among its materials. Silicon on insulator (SOI) is a widespread photonics technology, which support a variety of devices for lots of applications. As the photonics market is growing, the number of components in the PICs increases which increase the need for an automated physical verification (PV) process. This PV process will assure reliable fabrication of the PICs as it will check both the manufacturability and the reliability of the circuit. However, PV process is challenging in the case of PICs as it requires running an exhaustive electromagnetic (EM) simulations. Our group have recently proposed an empirical closed form models for the directional coupler and the waveguide bends based on the SOI technology. The models have shown a very good agreement with both finite element method (FEM) and finite difference time domain (FDTD) solvers. These models save the huge time of the 3D EM simulations and can be easily included in any electronic design automation (EDA) flow as the equations parameters can be easily extracted from the layout. In this paper we present experimental verification for our previously proposed models. SOI directional couplers with different dimensions have been fabricated using electron beam lithography and measured. The results from the measurements of the fabricate devices have been compared to the derived models and show a very good agreement. Also the matching can reach 100% by calibrating certain parameter in the model.

Investigation of AWG demultiplexer based SOI for CWDM application

Directory of Open Access Journals (Sweden)

Juhari Nurjuliana

2017-01-01

Full Text Available 9-channel Arrayed Waveguide Grating (AWG demultiplexer for conventional and tapered structure were simulated using beam propagation method (BPM with channel spacing of 20 nm. The AWG demultiplexer was design using high refractive index (n~3.47 material namely silicon-on-insulator (SOI with rib waveguide structure. The characteristics of insertion loss, adjacent crosstalk and output spectrum response at central wavelength of 1.55 μm for both designs were compared and analyzed. The conventional AWG produced a minimum insertion loss of 6.64 dB whereas the tapered AWG design reduced the insertion loss by 2.66 dB. The lowest adjacent crosstalk value of -16.96 dB was obtained in the conventional AWG design and this was much smaller compared to the tapered AWG design where the lowest crosstalk value is -17.23 dB. Hence, a tapered AWG design significantly reduces the insertion loss but has a slightly higher adjacent crosstalk compared to the conventional AWG design. On the other hand, the output spectrum responses that are obtained from both designs were close to the Coarse Wavelength Division Multiplexing (CWDM wavelength grid.

Thermal Performance of Cryogenic Multilayer Insulation at Various Layer Spacings

Science.gov (United States)

Johnson, Wesley Louis

2010-01-01

Multilayer insulation (MLI) has been shown to be the best performing cryogenic insulation system at high vacuum (less that 10 (exp 3) torr), and is widely used on spaceflight vehicles. Over the past 50 years, many investigations into MLI have yielded a general understanding of the many variables that are associated with MLI. MLI has been shown to be a function of variables such as warm boundary temperature, the number of reflector layers, and the spacer material in between reflectors, the interstitial gas pressure and the interstitial gas. Since the conduction between reflectors increases with the thickness of the spacer material, yet the radiation heat transfer is inversely proportional to the number of layers, it stands to reason that the thermal performance of MLI is a function of the number of layers per thickness, or layer density. Empirical equations that were derived based on some of the early tests showed that the conduction term was proportional to the layer density to a power. This power depended on the material combination and was determined by empirical test data. Many authors have graphically shown such optimal layer density, but none have provided any data at such low densities, or any method of determining this density. Keller, Cunnington, and Glassford showed MLI thermal performance as a function of layer density of high layer densities, but they didn't show a minimal layer density or any data below the supposed optimal layer density. However, it was recently discovered that by manipulating the derived empirical equations and taking a derivative with respect to layer density yields a solution for on optimal layer density. Various manufacturers have begun manufacturing MLI at densities below the optimal density. They began this based on the theory that increasing the distance between layers lowered the conductive heat transfer and they had no limitations on volume. By modifying the circumference of these blankets, the layer density can easily be

Measure Guideline. Incorporating Thick Layers of Exterior Rigid Insulation on Walls

Energy Technology Data Exchange (ETDEWEB)

Lstiburek, Joseph [Building Science Corporation, Westford, MA (United States); Baker, Peter [Building Science Corporation, Westford, MA (United States)

2015-04-09

This measure guideline, written by the U.S. Department of Energy’s Building America team Building Science Corporation, provides information about the design and construction of wall assemblies that use layers of rigid exterior insulation thicker than 1-½ in. and that require a secondary cladding attachment location exterior to the insulation. The guideline is separated into several distinct sections that cover: (1) fundamental building science principles relating to the use of exterior insulation on wall assemblies; (2) design principles for tailoring this use to the specific project goals and requirements; and (3) construction detailing to increase understanding about implementing the various design elements.

Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

Science.gov (United States)

Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

2016-09-01

In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

Urea biosensor based on Zn3Al-Urease layered double hydroxides nanohybrid coated on insulated silicon structures

International Nuclear Information System (INIS)

Barhoumi, H.; Maaref, A.; Rammah, M.; Martelet, C.; Jaffrezic, N.; Mousty, C.; Vial, S.; Forano, C.

2006-01-01

Urea biosensors for medical diagnostic monitoring were developed based on the immobilization of urease within layered double hydroxides (LDH). The urease-LDH material was obtained by a stepwise exchange reaction by urease of a Zn 3 Al-dodecyl sulphate (ZnAl-DS) colloidal suspension. XR diffraction and FTIR analysis show that this method gives rise to a Zn 3 Al-Urease LDH nanohybrid material with urease dispersion and textural properties. An aqueous suspension of this urease-LDH nanohybrid material was deposited on an insulated semiconductor (IS) structure. Biosensor responses to urea additions were obtained using capacitance (C vs. V) and impedance (Z vs. ω) measurements. An enhanced maximum limit of the dynamic range was observed in the case of the impedance measurements (110 mM) compared to (5.6 mM) the capacitive urea biosensor. The Michaelis-Menten constant was also calculated according to the Lineweaver-Burk plot. It was found that the K m value with immobilized enzymes was lower (K m = 0.67 mM) in comparison with free enzymes. This K m value obtained from the capacitance measurements indicates that the urea degradation is performed within any inhibition action on the IS/Zn 3 Al-Urease LDH electrode. A comparative study was carried out between these results and those obtained previously, using urease/ZnAl-Cl layered double hydroxides mixture coated on the pH-ISFET transducer

Nanoelectromechanical resonator for logic operations

KAUST Repository

Kazmi, Syed N. R.

2017-08-29

We report an electro-thermally tunable in-plane doubly-clamped nanoelectromechanical resonator capable of dynamically performing NOR, NOT, XNOR, XOR, and AND logic operations. Toward this, a silicon based resonator is fabricated using standard e-beam lithography and surface nanomachining of a highly conductive device layer of a silicon-on-insulator (SOI) wafer. The performance of this logic device is examined at elevated temperatures, ranging from 25 °C to 85 °C, demonstrating its resilience for most of the logic operations; thereby paving the way towards nano-elements-based mechanical computing.

Structure and field emission of graphene layers on top of silicon nanowire arrays

International Nuclear Information System (INIS)

Huang, Bohr-Ran; Chan, Hui-Wen; Jou, Shyankay; Chen, Guan-Yu; Kuo, Hsiu-An; Song, Wan-Jhen

2016-01-01

Graphical abstract: - Highlights: • We prepared graphene on top of silicon nanowires by transfer-print technique. • Graphene changed from discrete flakes to a continuous by repeated transfer-print. • The triple-layer graphene had high electron field emission due to large edge ratio. - Abstract: Monolayer graphene was grown on copper foils and then transferred on planar silicon substrates and on top of silicon nanowire (SiNW) arrays to form single- to quadruple-layer graphene films. The morphology, structure, and electron field emission (FE) of these graphene films were investigated. The graphene films on the planar silicon substrates were continuous. The single- to triple-layer graphene films on the SiNW arrays were discontinuous and while the quadruple-layer graphene film featured a mostly continuous area. The Raman spectra of the graphene films on the SiNW arrays showed G and G′ bands with a singular-Lorentzian shape together with a weak D band. The D band intensity decreased as the number of graphene layers increased. The FE efficiency of the graphene films on the planar silicon substrates and the SiNW arrays varied with the number of graphene layers. The turn-on field for the single- to quadruple-layer graphene films on planar silicon substrates were 4.3, 3.7, 3.5 and 3.4 V/μm, respectively. The turn-on field for the single- to quadruple-layer graphene films on SiNW arrays decreased to 3.9, 3.3, 3.0 and 3.3 V/μm, respectively. Correlation of the FE with structure and morphology of the graphene films is discussed.

Structure and field emission of graphene layers on top of silicon nanowire arrays

Energy Technology Data Exchange (ETDEWEB)

Huang, Bohr-Ran; Chan, Hui-Wen [Graduate Institute of Electro-Optical Engineering and Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China); Jou, Shyankay, E-mail: sjou@mail.ntust.edu.tw [Department of Materials Science and Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China); Chen, Guan-Yu [Graduate Institute of Electro-Optical Engineering and Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China); Kuo, Hsiu-An; Song, Wan-Jhen [Department of Materials Science and Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China)

2016-01-30

Graphical abstract: - Highlights: • We prepared graphene on top of silicon nanowires by transfer-print technique. • Graphene changed from discrete flakes to a continuous by repeated transfer-print. • The triple-layer graphene had high electron field emission due to large edge ratio. - Abstract: Monolayer graphene was grown on copper foils and then transferred on planar silicon substrates and on top of silicon nanowire (SiNW) arrays to form single- to quadruple-layer graphene films. The morphology, structure, and electron field emission (FE) of these graphene films were investigated. The graphene films on the planar silicon substrates were continuous. The single- to triple-layer graphene films on the SiNW arrays were discontinuous and while the quadruple-layer graphene film featured a mostly continuous area. The Raman spectra of the graphene films on the SiNW arrays showed G and G′ bands with a singular-Lorentzian shape together with a weak D band. The D band intensity decreased as the number of graphene layers increased. The FE efficiency of the graphene films on the planar silicon substrates and the SiNW arrays varied with the number of graphene layers. The turn-on field for the single- to quadruple-layer graphene films on planar silicon substrates were 4.3, 3.7, 3.5 and 3.4 V/μm, respectively. The turn-on field for the single- to quadruple-layer graphene films on SiNW arrays decreased to 3.9, 3.3, 3.0 and 3.3 V/μm, respectively. Correlation of the FE with structure and morphology of the graphene films is discussed.

Formation and properties of porous silicon layers

International Nuclear Information System (INIS)

Vitanov, P.; Kamenova, M.; Dimova-Malinovska, D.

1993-01-01

Preparation, properties and application of porous silicon films are investigated. Porous silicon structures were formed by an electrochemical etching process resulting in selective dissolution of the silicon substrate. The silicon wafers used with a resistivity of 5-10Ω.cm were doped with B to concentrations 6x10 18 -1x10 19 Ω.cm -3 in the temperature region 950 o C-1050 o C. The density of each porous films was determined from the weight loss during the anodization and it depends on the surface resistivity of the Si wafer. The density decreases with decreasing of the surface resistivity. The surface of the porous silicon layers was studied by X-ray photoelectron spectroscopy which indicates the presence of SiF 4 . The kinetic dependence of the anode potential and the porous layer thickness on the time of anodization in a galvanostatic regime for the electrolytes with various HF concentration were studied. In order to compare the properties of the resulting porous layers and to establish the dependence of the porosity on the electrolyte, three types of electrolytes were used: concentrated HF, diluted HF:H 2 O=1:1 and ethanol-hydrofluoric solutions HF:C 2 H 5 OH:H 2 O=2:1:1. High quality uniform and reproducible layers were formed using aqueous-ethanol-hydrofluoric electrolyte. Both Kikuchi's line and ring patterns were observed by TEM. The porous silicon layer was single crystal with the same orientation as the substrate. The surface shows a polycrystalline structure only. The porous silicon layers exhibit visible photoluminescence (PL) at room temperature under 480 nm Ar + laser line excitation. The peak of PL was observed at about 730 nm with FWHM about 90 nm. Photodiodes was made with a W-porous silicon junction. The current voltage and capacity voltage characteristics were similar to those of an isotype heterojunction diode. (orig.)

Metal insulator semiconductor solar cell devices based on a Cu2O substrate utilizing h-BN as an insulating and passivating layer

International Nuclear Information System (INIS)

Ergen, Onur; Gibb, Ashley; Vazquez-Mena, Oscar; Zettl, Alex; Regan, William Raymond

2015-01-01

We demonstrate cuprous oxide (Cu 2 O) based metal insulator semiconductor Schottky (MIS-Schottky) solar cells with efficiency exceeding 3%. A unique direct growth technique is employed in the fabrication, and hexagonal boron nitride (h-BN) serves simultaneously as a passivation and insulation layer on the active Cu 2 O layer. The devices are the most efficient of any Cu 2 O based MIS-Schottky solar cells reported to date

A graphene spin diode based on Rashba SOI

International Nuclear Information System (INIS)

Mohammadpour, Hakimeh

2015-01-01

In this paper a graphene-based two-terminal electronic device is modeled for application in spintronics. It is based on a gapped armchair graphene nanoribbon (GNR). The electron transport is considered through a scattering or channel region which is sandwiched between two lateral semi-infinite ferromagnetic leads. The two ferromagnetic leads, being half-metallic, are supposed to be in either parallel or anti-parallel magnetization. Meanwhile, the central channel region is a normal layer under the influence of the Rashba SOI, induced e.g., by the substrate. The device operation is based on modulating the (spin-) current by tuning the strength of the RSOI. The resultant current, being spin-polarized, is controlled by the RSOI in mutual interplay with the channel length. Inverting alternating bias voltage to a fully rectified spin-current is the main achievement of this paper. - Highlights: • Graphene-based electronic device is modeled with ferromagnetic leads. • The device operation is based on modulating the (spin-) current by Rashba SOI. • Inverting alternating bias voltage to rectified spin-current is the main achievement

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

Science.gov (United States)

Kim, Jong Cheol; Kim, Jongsik; Xin, Yan; Lee, Jinhyung; Kim, Young-Gyun; Subhash, Ghatu; Singh, Rajiv K.; Arjunan, Arul C.; Lee, Haigun

2018-05-01

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (˜3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

Science.gov (United States)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Integrated reconfigurable microring based silicon WDM receiver for on-chip optical interconnect

International Nuclear Information System (INIS)

Shen, Ao; Yang, Long-Zhi; Dai, Ting-Ge; Hao, Yin-Lei; Jiang, Xiao-Qing; Yang, Jian-Yi; Qiu, Chen

2015-01-01

We demonstrate an integrated reconfigurable wavelength division multiplexing receiver on the silicon-on-insulator (SOI) platform. The receiver is composed of a 1 × 8 thermally tunable microring resonator filter and Ge–Si photodetectors. With low thermal tuning powers the channel allocation of the receiver can be reconfigured with high accuracy and flexibility. The thermal tuning efficiency is approximately 8 mW nm −1 . We show eight-channel configurations with channel spacing of 100 GHz and 50 GHz and a configuration in which all eight channels cover an entire free spectral range of the ring with uniform channel spacing of 1.2 nm. Each channel can receive high-quality signals with a data rate of up to 13.5 Gb s −1 ; thus an aggregate data rate higher than 100 Gb s −1 can be achieved. (paper)

Atomic-Layer-Deposited Transparent Electrodes for Silicon Heterojunction Solar Cells

International Nuclear Information System (INIS)

Demaurex, Benedicte; Seif, Johannes P.; Smit, Sjoerd; Macco, Bart; Kessels, W. M.; Geissbuhler, Jonas; De Wolf, Stefaan; Ballif, Christophe

2014-01-01

We examine damage-free transparent-electrode deposition to fabricate high-efficiency amorphous silicon/crystalline silicon heterojunction solar cells. Such solar cells usually feature sputtered transparent electrodes, the deposition of which may damage the layers underneath. Using atomic layer deposition, we insert thin protective films between the amorphous silicon layers and sputtered contacts and investigate their effect on device operation. We find that a 20-nm-thick protective layer suffices to preserve, unchanged, the amorphous silicon layers beneath. Insertion of such protective atomic-layer-deposited layers yields slightly higher internal voltages at low carrier injection levels. However, we identify the presence of a silicon oxide layer, formed during processing, between the amorphous silicon and the atomic-layer-deposited transparent electrode that acts as a barrier, impeding hole and electron collection

Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

Science.gov (United States)

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

Electrohydrodynamic direct—writing of conductor—insulator-conductor multi-layer interconnection

International Nuclear Information System (INIS)

Zheng Gao-Feng; Pei Yan-Bo; Wang Xiang; Zheng Jian-Yi; Sun Dao-Heng

2014-01-01

A multi-layer interconnection structure is a basic component of electronic devices, and printing of the multi-layer interconnection structure is the key process in printed electronics. In this work, electrohydrodynamic direct-writing (EDW) is utilized to print the conductor—insulator—conductor multi-layer interconnection structure. Silver ink is chosen to print the conductor pattern, and a polyvinylpyrrolidone (PVP) solution is utilized to fabricate the insulator layer between the bottom and top conductor patterns. The influences of EDW process parameters on the line width of the printed conductor and insulator patterns are studied systematically. The obtained results show that the line width of the printed structure increases with the increase of the flow rate, but decreases with the increase of applied voltage and PVP content in the solution. The average resistivity values of the bottom and top silver conductor tracks are determined to be 1.34 × 10 −7 Ω·m and 1.39 × 10 −7 Ω·m, respectively. The printed PVP layer between the two conductor tracks is well insulated, which can meet the insulation requirement of the electronic devices. This study offers an alternative, fast, and cost-effective method of fabricating conductor—insulator—conductor multi-layer interconnections in the electronic industry

Heterojunction fully depleted SOI-TFET with oxide/source overlap

Science.gov (United States)

Chander, Sweta; Bhowmick, B.; Baishya, S.

2015-10-01

In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

Fabrication of high quality GaAs-on-insulator via ion-cut of epitaxial GaAs/Ge heterostructure

Energy Technology Data Exchange (ETDEWEB)

Chang, Yongwei; Zhang, Miao [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Deng, Chuang; Men, Chuanling [School of Energy and Power Engineering, University of Shanghai for Science and Technology, Shanghai 200093 (China); Chen, Da [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); School of Physical Science and Technology, Lanzhou University, Lanzhou 730000 (China); Zhu, Lei; Yu, Wenjie; Wei, Xing [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Di, Zengfeng, E-mail: zfdi@mail.sim.ac.cn [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China); Wang, Xi [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 (China)

2015-08-15

Highlights: • GaAs-on-insulator has been achieved by integrating of epitaxy, ion-cut and selective chemical etching. • Superior to the direct ion-cut of bulk GaAs layer with the H implantation fluence 2.0 × 10{sup 17} cm{sup −2}, the fabrication of GaAs-on-insulator by the transfer of GaAs/Ge heterostructure only needs H implantation fluence as low as 0.8 × 10{sup 17} cm{sup −2}. • The crystalline quality of the top GaAs layer of the final GaAs-on-insulator wafer is not affected by the implantation process and comparable to the as-grown status. - Abstract: Due to the extraordinary electron mobility, III–V compounds are considered as the ideal candidate channel materials for future electronic devices. In this study, a novel approach for the fabrication of high-crystalline quality GaAs-on-insulator has been proposed by integrating of ion-cut and selective chemical etching. GaAs layer with good crystalline quality has been epitaxially grown on Ge by molecular beam epitaxy (MBE). With H implantation and wafer bonding process, the GaAs/Ge heterostructure is transferred onto silicon dioxide wafer after the proper thermal treatment. Superior to the direct ion-cut of GaAs layer, which requires the H implantation fluence as high as 2.0 × 10{sup 17} cm{sup −2}, the transfer of GaAs/Ge heterostructure in the present study only needs the implantation of 0.8 × 10{sup 17} cm{sup −2} H ions. GaAs-on-insulator structure was successfully achieved by the selective chemical etching of defective Ge layer using SF{sub 6} plasma. As the GaAs/Ge heterostructure can be easily epitaxy grown on silicon platform, the proposed approach for GaAs-on-insulator manufacturing is rather compatible with mature Si integrated circuits (ICs) technology and thus can be integrated to push the microelectronic technology to post-Si era.

Fabrication of high quality GaAs-on-insulator via ion-cut of epitaxial GaAs/Ge heterostructure

International Nuclear Information System (INIS)

Chang, Yongwei; Zhang, Miao; Deng, Chuang; Men, Chuanling; Chen, Da; Zhu, Lei; Yu, Wenjie; Wei, Xing; Di, Zengfeng; Wang, Xi

2015-01-01

Highlights: • GaAs-on-insulator has been achieved by integrating of epitaxy, ion-cut and selective chemical etching. • Superior to the direct ion-cut of bulk GaAs layer with the H implantation fluence 2.0 × 10 17 cm −2 , the fabrication of GaAs-on-insulator by the transfer of GaAs/Ge heterostructure only needs H implantation fluence as low as 0.8 × 10 17 cm −2 . • The crystalline quality of the top GaAs layer of the final GaAs-on-insulator wafer is not affected by the implantation process and comparable to the as-grown status. - Abstract: Due to the extraordinary electron mobility, III–V compounds are considered as the ideal candidate channel materials for future electronic devices. In this study, a novel approach for the fabrication of high-crystalline quality GaAs-on-insulator has been proposed by integrating of ion-cut and selective chemical etching. GaAs layer with good crystalline quality has been epitaxially grown on Ge by molecular beam epitaxy (MBE). With H implantation and wafer bonding process, the GaAs/Ge heterostructure is transferred onto silicon dioxide wafer after the proper thermal treatment. Superior to the direct ion-cut of GaAs layer, which requires the H implantation fluence as high as 2.0 × 10 17 cm −2 , the transfer of GaAs/Ge heterostructure in the present study only needs the implantation of 0.8 × 10 17 cm −2 H ions. GaAs-on-insulator structure was successfully achieved by the selective chemical etching of defective Ge layer using SF 6 plasma. As the GaAs/Ge heterostructure can be easily epitaxy grown on silicon platform, the proposed approach for GaAs-on-insulator manufacturing is rather compatible with mature Si integrated circuits (ICs) technology and thus can be integrated to push the microelectronic technology to post-Si era

Fabrication of nanopores in multi-layered silicon-based membranes using focused electron beam induced etching with XeF_2 gas

International Nuclear Information System (INIS)

Liebes-Peer, Yael; Bandalo, Vedran; Sökmen, Ünsal; Tornow, Marc; Ashkenasy, Nurit

2016-01-01

The emergent technology of using nanopores for stochastic sensing of biomolecules introduces a demand for the development of simple fabrication methodologies of nanopores in solid state membranes. This process becomes particularly challenging when membranes of composite layer architecture are involved. To overcome this challenge we have employed a focused electron beam induced chemical etching process. We present here the fabrication of nanopores in silicon-on-insulator based membranes in a single step process. In this process, chemical etching of the membrane materials by XeF_2 gas is locally accelerated by an electron beam, resulting in local etching, with a top membrane oxide layer preventing delocalized etching of the silicon underneath. Nanopores with a funnel or conical, 3-dimensional (3D) shape can be fabricated, depending on the duration of exposure to XeF_2, and their diameter is dominated by the time of exposure to the electron beam. The demonstrated ability to form high-aspect ratio nanopores in comparably thick, multi-layered silicon based membranes allows for an easy integration into current silicon process technology and hence is attractive for implementation in biosensing lab-on-chip fabrication technologies. (author)

Buried Porous Silicon-Germanium Layers in Monocrystalline Silicon Lattices

Science.gov (United States)

Fathauer, Robert W. (Inventor); George, Thomas (Inventor); Jones, Eric W. (Inventor)

1998-01-01

Monocrystalline semiconductor lattices with a buried porous semiconductor layer having different chemical composition is discussed and monocrystalline semiconductor superlattices with a buried porous semiconductor layers having different chemical composition than that of its monocrystalline semiconductor superlattice are discussed. Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si-Ge layers followed by patterning into mesa structures. The mesa structures are strain etched resulting in porosification of the Si-Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si-Ge layers produced in a similar manner emitted visible light at room temperature.

Influence of oxygen on the ion-beam synthesis of silicon carbide buried layers in silicon

International Nuclear Information System (INIS)

Artamanov, V.V.; Valakh, M.Ya.; Klyui, N.I.; Mel'nik, V.P.; Romanyuk, A.B.; Romanyuk, B.N.; Yukhimchuk, V.A.

1998-01-01

The properties of silicon structures with silicon carbide (SiC) buried layers produced by high-dose carbon implantation followed by a high-temperature anneal are investigated by Raman and infrared spectroscopy. The influence of the coimplantation of oxygen on the features of SiC buried layer formation is also studied. It is shown that in identical implantation and post-implantation annealing regimes a SiC buried layer forms more efficiently in CZ Si wafers or in Si (CZ or FZ) subjected to the coimplantation of oxygen. Thus, oxygen promotes SiC layer formation as a result of the formation of SiO x precipitates and accommodation of the volume change in the region where the SiC phase forms. Carbon segregation and the formation of an amorphous carbon film on the SiC grain boundaries are also discovered

Characterization of electrical and optical properties of silicon based materials

Energy Technology Data Exchange (ETDEWEB)

Jia, Guobin

2009-12-04

characteristic DRL lines D1 to D4 has been detected, indicating the dislocations in the Alile sample are relatively clean. Test p-n junction diodes with dislocation networks (DNs) produced by silicon wafer direct bonding have been investigated by EBIC technique. Charge carriers collection and electrical conduction phenomena by the DNs were observed. Inhomogeneities in the charge collection were detected in n- and p-type samples under appropriate beam energy. The diffusion lengths in the thin top layer of silicon-on-insulator (SOI) have been measured by EBIC with full suppression of the surface recombination at the buried oxide (BOX) layer and at surface of the top layer by biasing method. The measured diffusion length is several times larger than the layer thickness. Silicon nanostructures are another important subject of this work. Electrical and optical properties of various silicon based materials like silicon nanowires, silicon nano rods, porous silicon, and Si/SiO{sub 2} multi quantum wells (MQWs) samples were investigated in this work. Silicon sub-bandgap infrared (IR) luminescence around 1570 nm was found in silicon nanowires, nano rods and porous silicon. PL measurements with samples immersed in different liquid media, for example, in aqueous HF (50%), concentrated H{sub 2}SO{sub 4} (98%) and H{sub 2}O{sub 2} established that the subbandgap IR luminescence originated from the Si/SiO{sub x} interface. EL in the sub-bandgap IR range has been observed in simple devices prepared on porous silicon and MQWs at room temperature. (orig.)

Silicon heterojunction transistor

International Nuclear Information System (INIS)

Matsushita, T.; Oh-uchi, N.; Hayashi, H.; Yamoto, H.

1979-01-01

SIPOS (Semi-insulating polycrystalline silicon) which is used as a surface passivation layer for highly reliable silicon devices constitutes a good heterojunction for silicon. P- or B-doped SIPOS has been used as the emitter material of a heterojunction transistor with the base and collector of silicon. An npn SIPOS-Si heterojunction transistor showing 50 times the current gain of an npn silicon homojunction transistor has been realized by high-temperature treatments in nitrogen and low-temperature annealing in hydrogen or forming gas

Graphene Quantum Dot Layers with Energy-Down-Shift Effect on Crystalline-Silicon Solar Cells.

Science.gov (United States)

Lee, Kyung D; Park, Myung J; Kim, Do-Yeon; Kim, Soo M; Kang, Byungjun; Kim, Seongtak; Kim, Hyunho; Lee, Hae-Seok; Kang, Yoonmook; Yoon, Sam S; Hong, Byung H; Kim, Donghwan

2015-09-02

Graphene quantum dot (GQD) layers were deposited as an energy-down-shift layer on crystalline-silicon solar cell surfaces by kinetic spraying of GQD suspensions. A supersonic air jet was used to accelerate the GQDs onto the surfaces. Here, we report the coating results on a silicon substrate and the GQDs' application as an energy-down-shift layer in crystalline-silicon solar cells, which enhanced the power conversion efficiency (PCE). GQD layers deposited at nozzle scan speeds of 40, 30, 20, and 10 mm/s were evaluated after they were used to fabricate crystalline-silicon solar cells; the results indicate that GQDs play an important role in increasing the optical absorptivity of the cells. The short-circuit current density was enhanced by about 2.94% (0.9 mA/cm(2)) at 30 mm/s. Compared to a reference device without a GQD energy-down-shift layer, the PCE of p-type silicon solar cells was improved by 2.7% (0.4 percentage points).

High temperature study of flexible silicon-on-insulator fin field-effect transistors

KAUST Repository

Diab, Amer El Hajj

2014-09-29

We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

Modelling of a DBR laser based on Raman effect in a silicon-on-insulator rib waveguide

International Nuclear Information System (INIS)

De Leonardis, Francesco; Dimastrodonato, Valeria; Passaro, Vittorio M N

2008-01-01

In this paper, third-order nonlinearities in silicon-on-insulator rib waveguides are investigated to obtain complete modelling, describing the behaviour of a stimulated Raman scattering based laser. The simulations of a distributed Bragg reflector laser operation in a time domain allow for the first time to study in detail the dependence of threshold and output powers on different device parameters. Both continuous wave and pulsed laser operations are theoretically demonstrated, as well as their dependence on device parameters

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

On the photon annealing of silicon-implanted gallium-nitride layers

International Nuclear Information System (INIS)

Seleznev, B. I.; Moskalev, G. Ya.; Fedorov, D. G.

2016-01-01

The conditions for the formation of ion-doped layers in gallium nitride upon the incorporation of silicon ions followed by photon annealing in the presence of silicon dioxide and nitride coatings are analyzed. The conditions of the formation of ion-doped layers with a high degree of impurity activation are established. The temperature dependences of the surface concentration and mobility of charge carriers in ion-doped GaN layers annealed at different temperatures are studied.

Effects of silicon:carbon P+ layer interfaces on solar cells

International Nuclear Information System (INIS)

Jeffrey, F.R.; Vernstrom, G.D.; Weber, M.F.; Gilbert, J.R.

1987-01-01

Results are presented showing the effects on amorphous silicon (a-Si) photovoltaic performance of the interfaces associated with a silicon carbide (a-Si:C) p+ layer. Carbon grading into the intrinsic layer from the p+ layer increases open circuit voltage (Voc) from 0.7V to 0.88V. This effect is very similar to the boron profile effect reported earlier and supports the contention that Voc is being limited by an electron current at the p-i interface. The interface between the p+ a-Si:C layer and the transparent conductive oxide (TCO) is shown to be a potential source of high series resistance, with an abrupt interface showing the most serious problem. The effect is explained by electron injection from the TCO into the p+ layer being inhibited as a result of band mismatch

Maximum magnitude in bias-dependent spin accumulation signals of CoFe/MgO/Si on insulator devices

International Nuclear Information System (INIS)

Ishikawa, M.; Sugiyama, H.; Inokuchi, T.; Tanamoto, T.; Saito, Y.; Hamaya, K.; Tezuka, N.

2013-01-01

We study in detail how the bias voltage (V bias ) and interface resistance (RA) depend on the magnitude of spin accumulation signals (|ΔV| or |ΔV|/I, where I is current) as detected by three-terminal Hanle measurements in CoFe/MgO/Si on insulator (SOI) devices with various MgO layer thicknesses and SOI carrier densities. We find the apparent maximum magnitude of spin polarization as a function of V bias and the correlation between the magnitude of spin accumulation signals and the shape of differential conductance (dI/dV) curves within the framework of the standard spin diffusion model. All of the experimental results can be explained by taking into account the density of states (DOS) in CoFe under the influence of the applied V bias and the quality of MgO tunnel barrier. These results indicate that it is important to consider the DOS of the ferromagnetic materials under the influence of an applied V bias and the quality of tunnel barrier when observing large spin accumulation signals in Si

Dark current of organic heterostructure devices with insulating spacer layers

Science.gov (United States)

Yin, Sun; Nie, Wanyi; Mohite, Aditya D.; Saxena, Avadh; Smith, Darryl L.; Ruden, P. Paul

2015-03-01

The dark current density at fixed voltage bias in donor/acceptor organic planar heterostructure devices can either increase or decrease when an insulating spacer layer is added between the donor and acceptor layers. The dominant current flow process in these systems involves the formation and subsequent recombination of an interfacial exciplex state. If the exciplex formation rate limits current flow, the insulating interface layer can increase dark current whereas, if the exciplex recombination rate limits current flow, the insulating interface layer decreases dark current. We present a device model to describe this behavior and illustrate it experimentally for various donor/acceptor systems, e.g. P3HT/LiF/C60.

Metal insulator semiconductor solar cell devices based on a Cu{sub 2}O substrate utilizing h-BN as an insulating and passivating layer

Energy Technology Data Exchange (ETDEWEB)

Ergen, Onur; Gibb, Ashley; Vazquez-Mena, Oscar; Zettl, Alex, E-mail: azettl@berkeley.edu [Department of Physics, University of California at Berkeley, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States); Kavli Energy Nanosciences Institute at the University of California, Berkeley, and the Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States); Regan, William Raymond [Department of Physics, University of California at Berkeley, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States)

2015-03-09

We demonstrate cuprous oxide (Cu{sub 2}O) based metal insulator semiconductor Schottky (MIS-Schottky) solar cells with efficiency exceeding 3%. A unique direct growth technique is employed in the fabrication, and hexagonal boron nitride (h-BN) serves simultaneously as a passivation and insulation layer on the active Cu{sub 2}O layer. The devices are the most efficient of any Cu{sub 2}O based MIS-Schottky solar cells reported to date.

SEMICONDUCTOR DEVICES: Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

Science.gov (United States)

Jin, Li; Hongxia, Liu; Bin, Li; Lei, Cao; Bo, Yuan

2010-08-01

For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a “rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.

A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques

International Nuclear Information System (INIS)

Yu-Feng, Guo; Zhi-Gong, Wang; Gene, Sheu; Jian-Bing, Cheng

2010-01-01

We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, two-dimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Annealing effects on magnetic properties of silicone-coated iron-based soft magnetic composites

Science.gov (United States)

Wu, Shen; Sun, Aizhi; Zhai, Fuqiang; Wang, Jin; Zhang, Qian; Xu, Wenhuan; Logan, Philip; Volinsky, Alex A.

2012-03-01

This paper focuses on novel iron-based soft magnetic composites synthesis utilizing high thermal stability silicone resin to coat iron powder. The effect of an annealing treatment on the magnetic properties of synthesized magnets was investigated. The coated silicone insulating layer was characterized by scanning electron microscopy and energy dispersive X-ray spectroscopy. Silicone uniformly coated the powder surface, resulting in a reduction of the imaginary part of the permeability, thereby increasing the electrical resistivity and the operating frequency of the synthesized magnets. The annealing treatment increased the initial permeability, the maximum permeability, and the magnetic induction, and decreased the coercivity. Annealing at 580 °C increased the maximum permeability by 72.5%. The result of annealing at 580 °C shows that the ferromagnetic resonance frequency increased from 2 kHz for conventional epoxy resin coated samples to 80 kHz for the silicone resin insulated composites.

Wide-range and fast thermally-tunable silicon photonic microring resonators using the junction field effect.

Science.gov (United States)

Wang, Xiaoxi; Lentine, Anthony; DeRose, Christopher; Starbuck, Andrew L; Trotter, Douglas; Pomerene, Andrew; Mookherjea, Shayan

2016-10-03

Tunable silicon microring resonators with small, integrated micro-heaters which exhibit a junction field effect were made using a conventional silicon-on-insulator (SOI) photonic foundry fabrication process. The design of the resistive tuning section in the microrings included a "pinched" p-n junction, which limited the current at higher voltages and inhibited damage even when driven by a pre-emphasized voltage waveform. Dual-ring filters were studied for both large (>4.9 THz) and small (850 GHz) free-spectral ranges. Thermal red-shifting was demonstrated with microsecond-scale time constants, e.g., a dual-ring filter was tuned over 25 nm in 0.6 μs 10%-90% transition time, and with efficiency of 3.2 μW/GHz.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Effect of layer thickness on device response of silicon heavily supersaturated with sulfur

Energy Technology Data Exchange (ETDEWEB)

Hutchinson, David [Department of Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy NY 12180 (United States); Department of Physics and Nuclear Engineering, United States Military Academy, West Point NY 10996 (United States); Mathews, Jay [US Army ARDEC – Benét Laboratories, Watervliet NY 12189 (United States); Department of Physics, University of Dayton, Dayton, OH 45469 (United States); Sullivan, Joseph T.; Buonassisi, Tonio [School of Engineering, Massachusetts Institute of Technology, Cambridge MA 02139 (United States); Akey, Austin [School of Engineering, Massachusetts Institute of Technology, Cambridge MA 02139 (United States); Harvard John A. Paulson School of Engineering and Applied Sciences, Cambridge MA 02138 (United States); Aziz, Michael J. [Harvard John A. Paulson School of Engineering and Applied Sciences, Cambridge MA 02138 (United States); Persans, Peter [Department of Physics, Applied Physics, and Astronomy, Rensselaer Polytechnic Institute, Troy NY 12180 (United States); Warrender, Jeffrey M., E-mail: jwarrend@post.harvard.edu [US Army ARDEC – Benét Laboratories, Watervliet NY 12189 (United States)

2016-05-15

We report on a simple experiment in which the thickness of a hyperdoped silicon layer, supersaturated with sulfur by ion implantation followed by pulsed laser melting and rapid solidification, is systematically varied at constant average sulfur concentration, by varying the implantation energy, dose, and laser fluence. Contacts are deposited and the external quantum efficiency (EQE) is measured for visible wavelengths. We posit that the sulfur layer primarily absorbs light but contributes negligible photocurrent, and we seek to support this by analyzing the EQE data for the different layer thicknesses in two interlocking ways. In the first, we use the measured concentration depth profiles to obtain the approximate layer thicknesses, and, for each wavelength, fit the EQE vs. layer thickness curve to obtain the absorption coefficient of hyperdoped silicon for that wavelength. Comparison to literature values for the hyperdoped silicon absorption coefficients [S.H. Pan et al. Applied Physics Letters 98, 121913 (2011)] shows good agreement. Next, we essentially run this process in reverse; we fit with Beer’s law the curves of EQE vs. hyperdoped silicon absorption coefficient for those wavelengths that are primarily absorbed in the hyperdoped silicon layer, and find that the layer thicknesses obtained from the fit are in good agreement with the original values obtained from the depth profiles. We conclude that the data support our interpretation of the hyperdoped silicon layer as providing negligible photocurrent at high S concentrations. This work validates the absorption data of Pan et al. [Applied Physics Letters 98, 121913 (2011)], and is consistent with reports of short mobility-lifetime products in hyperdoped layers. It suggests that for optoelectronic devices containing hyperdoped layers, the most important contribution to the above band gap photoresponse may be due to photons absorbed below the hyperdoped layer.

Effect of layer thickness on device response of silicon heavily supersaturated with sulfur

Directory of Open Access Journals (Sweden)

David Hutchinson

2016-05-01

Full Text Available We report on a simple experiment in which the thickness of a hyperdoped silicon layer, supersaturated with sulfur by ion implantation followed by pulsed laser melting and rapid solidification, is systematically varied at constant average sulfur concentration, by varying the implantation energy, dose, and laser fluence. Contacts are deposited and the external quantum efficiency (EQE is measured for visible wavelengths. We posit that the sulfur layer primarily absorbs light but contributes negligible photocurrent, and we seek to support this by analyzing the EQE data for the different layer thicknesses in two interlocking ways. In the first, we use the measured concentration depth profiles to obtain the approximate layer thicknesses, and, for each wavelength, fit the EQE vs. layer thickness curve to obtain the absorption coefficient of hyperdoped silicon for that wavelength. Comparison to literature values for the hyperdoped silicon absorption coefficients [S.H. Pan et al. Applied Physics Letters 98, 121913 (2011] shows good agreement. Next, we essentially run this process in reverse; we fit with Beer’s law the curves of EQE vs. hyperdoped silicon absorption coefficient for those wavelengths that are primarily absorbed in the hyperdoped silicon layer, and find that the layer thicknesses obtained from the fit are in good agreement with the original values obtained from the depth profiles. We conclude that the data support our interpretation of the hyperdoped silicon layer as providing negligible photocurrent at high S concentrations. This work validates the absorption data of Pan et al. [Applied Physics Letters 98, 121913 (2011], and is consistent with reports of short mobility-lifetime products in hyperdoped layers. It suggests that for optoelectronic devices containing hyperdoped layers, the most important contribution to the above band gap photoresponse may be due to photons absorbed below the hyperdoped layer.

Formation and dielectric properties of polyelectrolyte multilayers studied by a silicon-on-insulator based thin film resistor.

Science.gov (United States)

Neff, Petra A; Wunderlich, Bernhard K; Klitzing, Regine V; Bausch, Andreas R

2007-03-27

The formation of polyelectrolyte multilayers (PEMs) is investigated using a silicon-on-insulator based thin film resistor which is sensitive to variations of the surface potential. The buildup of the PEMs at the silicon oxide surface of the device can be observed in real time as defined potential shifts. The influence of polymer charge density is studied using the strong polyanion poly(styrene sulfonate), PSS, combined with the statistical copolymer poly(diallyl-dimethyl-ammoniumchloride-stat-N-methyl-N-vinylacetamide), P(DADMAC-stat-NMVA), at various degrees of charge (DC). The multilayer formation stops after a few deposition steps for a DC below 75%. We show that the threshold of surface charge compensation corresponds to the threshold of multilayer formation. However, no reversion of the preceding surface charge was observed. Screening of polyelectrolyte charges by mobile ions within the polymer film leads to a decrease of the potential shifts with the number of layers deposited. This decrease is much slower for PEMs consisting of P(DADMAC-stat-NMVA) and PSS as compared to PEMs consisting of poly(allylamine-hydrochloride), PAH, and PSS. From this, significant differences in the dielectric constants of the polyelectrolyte films and in the concentration of mobile ions within the films can be derived.

Effect of additive gases and injection methods on chemical dry etching of silicon nitride, silicon oxynitride, and silicon oxide layers in F2 remote plasmas

International Nuclear Information System (INIS)

Yun, Y. B.; Park, S. M.; Kim, D. J.; Lee, N.-E.; Kim, K. S.; Bae, G. H.

2007-01-01

The authors investigated the effects of various additive gases and different injection methods on the chemical dry etching of silicon nitride, silicon oxynitride, and silicon oxide layers in F 2 remote plasmas. N 2 and N 2 +O 2 gases in the F 2 /Ar/N 2 and F 2 /Ar/N 2 /O 2 remote plasmas effectively increased the etch rate of the layers. The addition of direct-injected NO gas increased the etch rates most significantly. NO radicals generated by the addition of N 2 and N 2 +O 2 or direct-injected NO molecules contributed to the effective removal of nitrogen and oxygen in the silicon nitride and oxide layers, by forming N 2 O and NO 2 by-products, respectively, and thereby enhancing SiF 4 formation. As a result of the effective removal of the oxygen, nitrogen, and silicon atoms in the layers, the chemical dry etch rates were enhanced significantly. The process regime for the etch rate enhancement of the layers was extended at elevated temperature

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

Directory of Open Access Journals (Sweden)

Bo Xie

2015-09-01

Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

Flexible high-κ/Metal gate metal/insulator/metal capacitors on silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-10-01

Implementation of memory on bendable substrates is an important step toward a complete and fully developed notion of mechanically flexible computational systems. In this paper, we have demonstrated a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric. We rely on standard microfabrication processes to release a thin sheet of bendable silicon (area: 18 {\\ m cm}2 and thickness: 25 \\\\mu{\\ m m}) in an inexpensive and reliable way. On such platform, we fabricated and characterized the devices showing mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and nominal strain of 0.125%) and consistent electrical behavior regardless of the applied mechanical stress. Furthermore, and for the first time, we performed a reliability study suggesting no significant difference in performance and showing an improvement in lifetime projections. © 1963-2012 IEEE.

Thermal Analysis of Low Layer Density Multilayer Insulation Test Results

Science.gov (United States)

Johnson, Wesley L.

2011-01-01

Investigation of the thermal performance of low layer density multilayer insulations is important for designing long-duration space exploration missions involving the storage of cryogenic propellants. Theoretical calculations show an analytical optimal layer density, as widely reported in the literature. However, the appropriate test data by which to evaluate these calculations have been only recently obtained. As part of a recent research project, NASA procured several multilayer insulation test coupons for calorimeter testing. These coupons were configured to allow for the layer density to be varied from 0.5 to 2.6 layer/mm. The coupon testing was completed using the cylindrical Cryostat-l00 apparatus by the Cryogenics Test Laboratory at Kennedy Space Center. The results show the properties of the insulation as a function of layer density for multiple points. Overlaying these new results with data from the literature reveals a minimum layer density; however, the value is higher than predicted. Additionally, the data show that the transition region between high vacuum and no vacuum is dependent on the spacing of the reflective layers. Historically this spacing has not been taken into account as thermal performance was calculated as a function of pressure and temperature only; however the recent testing shows that the data is dependent on the Knudsen number which takes into account pressure, temperature, and layer spacing. These results aid in the understanding of the performance parameters of MLI and help to complete the body of literature on the topic.

A new SOI high-voltage device with a step-thickness drift region and its analytical model for the electric field and breakdown voltage

International Nuclear Information System (INIS)

Luo Xiaorong; Zhang Wei; Zhang Bo; Li Zhaoji; Yang Shouguo; Zhan Zhan; Fu Daping

2008-01-01

A new SOI high-voltage device with a step-thickness drift region (ST SOI) and its analytical model for the two-dimension electric field distribution and the breakdown voltage are proposed. The electric field in the drift region is modulated and that of the buried layer is enhanced by the variable thickness SOI layer, thereby resulting in the enhancement of the breakdown voltage. Based on the Poisson equation, the expression for the two-dimension electric field distribution is presented taking the modulation effect into account, from which the RESURF (REduced SURface Field) condition and the approximate but explicit expression for the maximal breakdown voltage are derived. The analytical model can explain the effects of the device parameters, such as the step height and the step length of the SOI layer, the doping concentration and the buried oxide thickness, on the electric field distribution and the breakdown voltage. The validity of this model is demonstrated by a comparison with numerical simulations. Improvement on both the breakdown voltage and the on-resistance (R on ) for the ST SOI is obtained due to the variable thickness SOI layer

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

Energy Technology Data Exchange (ETDEWEB)

Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.; Petrovich, V. A.; Kotov, D. A.; Bondarenko, V. P. [Belarusian State University of Information and RadioElectronics (Belarus)

2016-03-15

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materials on the basis of porous silicon and nanostructures with a high aspect ratio.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

International Nuclear Information System (INIS)

Chubenko, E. B.; Redko, S. V.; Sherstnyov, A. I.; Petrovich, V. A.; Kotov, D. A.; Bondarenko, V. P.

2016-01-01

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materials on the basis of porous silicon and nanostructures with a high aspect ratio.

Forming of nanocrystal silicon films by implantation of high dose of H+ in layers of silicon on isolator and following fast thermal annealing

International Nuclear Information System (INIS)

Tyschenko, I.E.; Popov, V.P.; Talochkin, A.B.; Gutakovskij, A.K.; Zhuravlev, K.S.

2004-01-01

Formation of nanocrystalline silicon films during rapid thermal annealing of the high-dose H + ion implanted silicon-on-insulator structures was studied. It was found, that Si nanocrystals had formed alter annealings at 300-400 deg C, their formation being strongly limited by the hydrogen content in silicon and also by the annealing time. It was supposed that the nucleation of crystalline phase occurred inside the silicon islands between micropores. It is conditioned by ordering Si-Si bonds as hydrogen atoms are leaving their sites in silicon network. No coalescence of micropores takes place during the rapid thermal annealing at the temperatures up to ∼ 900 deg C. Green-orange photoluminescence was observed on synthesized films at room temperature [ru

Activity and lifetime of urease immobilized using layer-by-layer nano self-assembly on silicon microchannels.

Science.gov (United States)

Forrest, Scott R; Elmore, Bill B; Palmer, James D

2005-01-01

Urease has been immobilized and layered onto the walls of manufactured silicon microchannels. Enzyme immobilization was performed using layer-by-layer nano self-assembly. Alternating layers of oppositely charged polyelectrolytes, with enzyme layers "encased" between them, were deposited onto the walls of the silicon microchannels. The polycations used were polyethylenimine (PEI), polydiallyldimethylammonium (PDDA), and polyallylamine (PAH). The polyanions used were polystyrenesulfonate (PSS) and polyvinylsulfate (PVS). The activity of the immobilized enzyme was tested by pumping a 1 g/L urea solution through the microchannels at various flow rates. Effluent concentration was measured using an ultraviolet/visible spectrometer by monitoring the absorbance of a pH sensitive dye. The architecture of PEI/PSS/PEI/urease/PEI with single and multiple layers of enzyme demonstrated superior performance over the PDDA and PAH architectures. The precursor layer of PEI/PSS demonstrably improved the performance of the reactor. Conversion rates of 70% were achieved at a residence time of 26 s, on d 1 of operation, and >50% at 51 s, on d 15 with a six-layer PEI/urease architecture.

Silicon Integrated Dual-Mode Interferometer with Differential Outputs

Directory of Open Access Journals (Sweden)

Niklas Hoppe

2017-09-01

Full Text Available The dual-mode interferometer (DMI is an attractive alternative to Mach-Zehnder interferometers for sensor purposes, achieving sensitivities to refractive index changes close to state-of-the-art. Modern designs on silicon-on-insulator (SOI platforms offer thermally stable and compact devices with insertion losses of less than 1 dB and high extinction ratios. Compact arrays of multiple DMIs in parallel are easy to fabricate due to the simple structure of the DMI. In this work, the principle of operation of an integrated DMI with differential outputs is presented which allows the unambiguous phase shift detection with a single wavelength measurement, rather than using a wavelength sweep and evaluating the optical output power spectrum. Fluctuating optical input power or varying attenuation due to different analyte concentrations can be compensated by observing the sum of the optical powers at the differential outputs. DMIs with two differential single-mode outputs are fabricated in a 250 nm SOI platform, and corresponding measurements are shown to explain the principle of operation in detail. A comparison of DMIs with the conventional Mach-Zehnder interferometer using the same technology concludes this work.

Spontaneous layering of porous silicon layers formed at high current densities

Energy Technology Data Exchange (ETDEWEB)

Parkhutik, Vitali; Curiel-Esparza, Jorge; Millan, Mari-Carmen [R and D Center MTM, Technical University of Valencia, Valencia (Spain); Albella, Jose [Institute of Materials Science (ICMM CSIC) Madrid (Spain)

2005-06-01

We report here a curious effect of spontaneous fracturing of the silicon layers formed in galvanostatic conditions at medium and high current densities. Instead of formation of homogeneous p-Si layer as at low currents, a stack of thin layers is formed. Each layer is nearly separated from others and possesses rather flat interfaces. The effects is observed using p{sup +}-Si wafers for the p-Si formation and starts being noticeable at above 100 mA/cm{sup 2}. We interpret these results in terms of the porous silicon growth model where generation of dynamic mechanical stress during the p-Si growth causes sharp changes in Si dissolution mechanism from anisotropic etching of individual needle-like pores in silicon to their branching and isotropic etching. At this moment p-Si layer loses its adhesion to the surface of Si wafer and another p-Si layer starts growing. One of the mechanisms triggering on the separation of p-Si layers from one another is a fluctuation of local anodic current in the pore bottoms associated with gas bubble evolution during the p-Si formation. (copyright 2005 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Observation of an optical event horizon in a silicon-on-insulator photonic wire waveguide.

Science.gov (United States)

Ciret, Charles; Leo, François; Kuyken, Bart; Roelkens, Gunther; Gorza, Simon-Pierre

2016-01-11

We report on the first experimental observation of an optical analogue of an event horizon in integrated nanophotonic waveguides, through the reflection of a continuous wave on an intense pulse. The experiment is performed in a dispersion-engineered silicon-on-insulator waveguide. In this medium, solitons do not suffer from Raman induced self-frequency shift as in silica fibers, a feature that is interesting for potential applications of optical event horizons. As shown by simulations, this also allows the observation of multiple reflections at the same time on fundamental solitons ejected by soliton fission.

Improved vertical MOSFET performance using an epitaxial channel and a stacked silicon-insulator structure

International Nuclear Information System (INIS)

Uchino, T; Gili, E; Ashburn, P; Tan, L; Buiu, O; Hall, S

2012-01-01

A vertical MOSFET (VMOST) incorporating an epitaxial channel and a drain junction in a stacked silicon-insulator structure is presented. In this device structure, an oxide layer near the drain junction edge (referred to as a junction stop) acts as a dopant diffusion barrier and consequently a shallow drain junction is formed to suppress short channel effects. To investigate the scalability of this device, a simulation study in the sub-100 nm regime calibrated to measured results on the fabricated devices is carried out. The use of an epitaxial channel delivers 50% higher drive current due to the higher mobility of the retrograde channel and the junction stop structure delivers improvements of threshold voltage roll-off and drain-induced barrier lowering compared with a conventional VMOST. (fast track communication)

Resonant Varifocal Micromirror with Piezoresistive Focus Sensor

Directory of Open Access Journals (Sweden)

Kenta Nakazawa

2016-03-01

Full Text Available This paper reports a microelectromechanical systems (MEMS resonant varifocal mirror integrated with piezoresistive focus sensor. The varifocal mirror is driven electrostatically at a resonant frequency of a mirror plate to obtain the wide scanning range of a focal length. A piezoresistor is used to monitor the focal length of the varifocal mirror. The device is made of a silicon-on-insulator (SOI wafer and a glass wafer. A mirror plate and a counter electrode are fabricated by a top silicon layer of the SOI wafer and on the glass wafer, respectively. The piezoresistor is fabricated by ion implantation on a supporting beam of the mirror plate. The stress variation of the beam, which is detected by the piezoresistor, correspond the focal length of the varifocal mirror. The focus length varies from −41 to 35 mm at the resonant frequency of 9.5 kHz. The focal length of the varifocal mirror is monitored by the piezoresistor in real time.

SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

Science.gov (United States)

Patterson, Richard L.; Hammoud, Almad

2009-01-01

Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80

Oxide layers for silicon detector protection against enviroment effects

International Nuclear Information System (INIS)

Bel'tsazh, E.; Brylovska, I.; Valerian, M.

1986-01-01

It is shown that for protection of silicon detectors of nuclear radiations oxide layers could be used. The layers are produced by electrochemical oxidation of silicon surface with the following low-temperature annealing. These layers have characteristics similar to those for oxide layers produced by treatment of silicon samples at elevated temperature in oxygen flow. To determine properties of oxide layers produced by electrochemical oxidation the α-particle back-scattering method and the method of volt-farad characteristics were used. Protection properties of such layers were checked on the surface-barrier detectors. It was shown that protection properties of such detectors were conserved during long storage at room temperature and during their storage under wet-bulb temperature. Detectors without protection layer have worsened their characteristics

Waveguide silicon nitride grating coupler

Science.gov (United States)

Litvik, Jan; Dolnak, Ivan; Dado, Milan

2016-12-01

Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

Enhancement of giant magnetoimpedance in composite wire with insulator layer

International Nuclear Information System (INIS)

Wang, X.Z.; Yuan, W.Z.; Li, X.D.; Ruan, J.Z.; Zhao, Z.J.; Yang, J.X.; Yang, X.L.; Sun, Z.

2007-01-01

CuBe/NiFeB and CuBe/Insulator/NiFeB composite wires have been prepared by electroless-deposition. The giant magnetoimpedance (GMI) effect for NiFeB layer with thickness of 3 μm on CuBe core with diameter of 100 μm has been studied. After adding an insulator layer, the maximal GMI ratio of CuBe/Insulator/NiFeB composite wire is much higher than that of CuBe/NiFeB composite wire, and can reach to about 250% at the frequency range of 500 kHz-1 MHz. The results are explained in terms of difference of magnetic structure and different frequency dependence of resistance and reactance of the two kinds of composite wires

Voltage-Controlled Spray Deposition of Multiwalled Carbon Nanotubes on Semiconducting and Insulating Substrates

Science.gov (United States)

Maulik, Subhodip; Sarkar, Anirban; Basu, Srismrita; Daniels-Race, Theda

2018-05-01

A facile, cost-effective, voltage-controlled, "single-step" method for spray deposition of surfactant-assisted dispersed carbon nanotube (CNT) thin films on semiconducting and insulating substrates has been developed. The fabrication strategy enables direct deposition and adhesion of CNT films on target samples, eliminating the need for substrate surface functionalization with organosilane binder agents or metal layer coatings. Spray coating experiments on four types of sample [bare silicon (Si), microscopy-grade glass samples, silicon dioxide (SiO2), and polymethyl methacrylate (PMMA)] under optimized control parameters produced films with thickness ranging from 40 nm to 6 μm with substantial surface coverage and packing density. These unique deposition results on both semiconducting and insulator target samples suggest potential applications of this technique in CNT thin-film transistors with different gate dielectrics, bendable electronics, and novel CNT-based sensing devices, and bodes well for further investigation into thin-film coatings of various inorganic, organic, and hybrid nanomaterials on different types of substrate.

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.

2015-06-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

Single-layer graphene on silicon nitride micromembrane resonators

DEFF Research Database (Denmark)

Schmid, Silvan; Bagci, Tolga; Zeuthen, Emil

2014-01-01

Due to their low mass, high quality factor, and good optical properties, silicon nitride (SiN) micromembrane resonators are widely used in force and mass sensing applications, particularly in optomechanics. The metallization of such membranes would enable an electronic integration with the prospect...... for exciting new devices, such as optoelectromechanical transducers. Here, we add a single-layer graphene on SiN micromembranes and compare electromechanical coupling and mechanical properties to bare dielectric membranes and to membranes metallized with an aluminium layer. The electrostatic coupling...

Single-crystal-like GdNdOx thin films on silicon substrates by magnetron sputtering and high-temperature annealing for crystal seed layer application

Directory of Open Access Journals (Sweden)

Ziwei Wang

2016-06-01

Full Text Available Single-crystal-like rare earth oxide thin films on silicon (Si substrates were fabricated by magnetron sputtering and high-temperature annealing processes. A 30-nm-thick high-quality GdNdOx (GNO film was deposited using a high-temperature sputtering process at 500°C. A Gd2O3 and Nd2O3 mixture was used as the sputtering target, in which the proportions of Gd2O3 and Nd2O3 were controlled to make the GNO’s lattice parameter match that of the Si substrate. To further improve the quality of the GNO film, a post-deposition annealing process was performed at a temperature of 1000°C. The GNO films exhibited a strong preferred orientation on the Si substrate. In addition, an Al/GNO/Si capacitor was fabricated to evaluate the dielectric constant and leakage current of the GNO films. It was determined that the single-crystal-like GNO films on the Si substrates have potential for use as an insulator layer for semiconductor-on-insulator and semiconductor/insulator multilayer applications.

Method of producing buried porous silicon-geramanium layers in monocrystalline silicon lattices

Science.gov (United States)

Fathauer, Robert W. (Inventor); George, Thomas (Inventor); Jones, Eric W. (Inventor)

1997-01-01

Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si--Ge layers followed by patterning into mesa structures. The mesa structures are stain etched resulting in porosification of the Si--Ge layers with a minor amount of porosification of the monocrystalline Si layers. Thicker Si--Ge layers produced in a similar manner emitted visible light at room temperature.

Silicon based light emitter utilizing tunnel injection of excess carriers via MIS structure

Energy Technology Data Exchange (ETDEWEB)

Arguirov, Tzanimir; Kittler, Martin [IHP - Innovations for High Performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder) (Germany); IHP/BTU Joint Lab BTU Cottbus, Konrad-Wachsmann-Allee 1, 03013 Cottbus (Germany); Wenger, Christian; Lukosius, Mindaugas [IHP - Innovations for High Performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder) (Germany); Mchedlidze, Teimuraz [IHP/BTU Joint Lab BTU Cottbus, Konrad-Wachsmann-Allee 1, 03013 Cottbus (Germany); Reiche, Manfred [Max-Planck-Institut fuer Mikrostrukturphysik, Weinberg 2, 06120 Halle (Germany)

2011-04-15

We report on electro-luminescence from metal-insulator-semiconductor diodes (MISLED). MISLEDs prepared on silicon with HfO2 layers of different thicknesses were investigated and their properties compared with such prepared by using SiO2 insulator layer. The role of the insulator layer was studied in view of the efficiency of the band-to-band radiation from silicon. We show that the luminescence efficiency depends on the dielectric constant of the insulator as well as on its ability to conduct carriers by tunnelling. Efficiency enhancement of 3.3 times was detected when the SiO{sub 2} insulator was substituted by HfO{sub 2} in the MIS emitter. Optimal injection current exists, which leads to a maximal efficiency of the luminescence. The optimal current depends strongly on the thickness of the oxide. We relate the existence of an optimal current with the depth at which the injected minority carriers recombine radiatively. Thus the electric field in the semiconductor and the surface recombination are the factors determining the optimal injection (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Growth and characterization of semi-insulating carbon-doped/undoped GaN multiple-layer buffer

International Nuclear Information System (INIS)

Kim, Dong-Seok; Won, Chul-Ho; Kang, Hee-Sung; Kim, Young-Jo; Kang, In Man; Lee, Jung-Hee; Kim, Yong Tae

2015-01-01

We have proposed a new semi-insulating GaN buffer layer, which consists of multiple carbon-doped and undoped GaN layer. The buffer layer showed sufficiently good semi-insulating characteristics, attributed to the depletion effect between the carbon-doped GaN and the undoped GaN layers, even though the thickness of the carbon-doped GaN layer in the periodic structure was designed to be very thin to minimize the total carbon incorporation into the buffer layer. The AlGaN/AlN/GaN heterostructure grown on the proposed buffer exhibited much better electrical and structural properties than that grown on the conventional thick carbon-doped semi-insulating GaN buffer layer, confirmed by Hall measurement, x-ray diffraction, and secondary ion mass spectrometry. The fabricated device also showed excellent buffer breakdown characteristics. (paper)

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Science.gov (United States)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

Science.gov (United States)

Patterson, Richard L.; Hammoud, Ahmad

2010-01-01

The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

Ultrabroadband Hybrid III-V/SOI Grating Reflector for On-chip Lasers

DEFF Research Database (Denmark)

Park, Gyeong Cheol; Taghizadeh, Alireza; Chung, Il-Sug

2016-01-01

We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability.......We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability....

InP on SOI devices for optical communication and optical network on chip

Science.gov (United States)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Preparation of YBCO on YSZ layers deposited on silicon and sapphire by MOCVD: influence of the intermediate layer on the quality of the superconducting film

International Nuclear Information System (INIS)

Garcia, G.; Casado, J.; Llibre, J.; Doudkowski, M.; Santiso, J.; Figueras, A.; Schamm, S.; Dorignac, D.; Grigis, C.; Aguilo, M.

1995-01-01

YSZ buffer layers were deposited on silicon and sapphire by MOCVD. The layers deposited on silicon were highly oriented along [100] direction without in-plane orientation, probably because the existence of the SiO 2 amorphous interlayer. In contrast, epitaxial YSZ was obtained on (1-102) sapphire showing an in-plane texture defined by the following relationships: (100) YSZ // (1-102) sapphire and (110) YSZ // (01-12) sapphire. Subsequently, YBCO films were deposited on YSZ by MOCVD. Structural, morphological and electrical characterization of the superconducting layers were correlated with the in-plane texture of the buffer layers. (orig.)

Growth and characterization of InP/GaAs on SOI by MOCVD

International Nuclear Information System (INIS)

Karam, N.H.; Haven, V.; Vernon, S.M.; Namavar, F.; El-Masry, N.; Haegel, N.; Al-Jassin, M.M.

1990-01-01

This paper reports that epitaxial InP films have been successfully deposited on GaAs coated silicon wafers with a buried oxide for the first time by MOCVD. The SOI wafers were prepared using the Separation by Implantation of Oxygen (SIMOX) process. The quality of InP on SIMOX is comparable to the best of InP on Si deposited in the same reactor. Preliminary results on defect reduction techniques such as Thermal Cycle Growth (TCG) show an order of magnitude increase in the photoluminescence intensity and a factor of five reduction in the defect density. TCG has been found more effective than Thermal Cycle Annealing (TCA) in improving the crystalline perfection and optical properties of the deposited films