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Sample records for silicon-on-insulator soi layer

  1. Characterization of dielectric materials in thin layers for the development of S.O.I. (Silicon on Insulator) substrates

    International Nuclear Information System (INIS)

    Gruber, Olivier

    1999-01-01

    This thesis deals with the characterization of oxide layer placed inside S.O.I. substrates and submitted to irradiation. This type of material is used for the development of hardened electronic components, that is to say components able to be used in a radiative environment. The irradiation induces charges (electrons or holes) in the recovered oxide. A part of these charges is trapped which leads to changes of the characteristics of the electronic components made on these substrates. The main topic of this study is the characterization of trapping properties of recovered oxides and more particularly of 'Unibond' material carried out with a new fabrication process: the 'smart-cut' process. This work is divided into three parts: - study with one carrier: this case is limited to low radiation doses where is only observed holes trapping. The evolution of the physical and chemical properties of the 'Unibond' material recovered oxide has been revealed, this evolution being due to the fabrication process. - Study with two carriers: in this case, there is trapping of holes and electrons. This type of trapping is observed in the case of strong radiation doses. A new type of electrons traps has been identified with the 'Unibond' material oxide. The transport and the trapping of holes and electrons have been studied in the case of transient phenomena created by short radiative pulses. This study has been carried out using a new measurement method. - Study with three carriers: here are added to holes and electrons the protons introduced in the recovered oxide by the annealing under hydrogen. These protons are movable when they are submitted to the effect of an electric field and they induce a memory effect according to their position in the oxide. These different works show that the 'Unibond' material is a very good solution for the future development of S.O.I. (author) [fr

  2. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    Science.gov (United States)

    Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  3. DOUBLE BOSS SCULPTURED DIAPHRAGM EMPLOYED PIEZORESISTIVE MEMS PRESSURE SENSOR WITH SILICON-ON-INSULATOR (SOI

    Directory of Open Access Journals (Sweden)

    D. SINDHANAISELVI

    2017-07-01

    Full Text Available This paper presents the detailed study on the measurement of low pressure sensor using double boss sculptured diaphragm of piezoresistive type with MEMS technology in flash flood level measurement. The MEMS based very thin diaphragms to sense the low pressure is analyzed by introducing supports to achieve linearity. The simulation results obtained from Intellisuite MEMS CAD design tool show that very thin diaphragms with rigid centre or boss give acceptable linearity. Further investigations on very thin diaphragms embedded with piezoresistor for low pressure measurement show that it is essential to analyse the piezoresistor placement and size of piezoresistor to achieve good sensitivity. A modified analytical modelling developed in this study for double boss sculptured diaphragm results were compared with simulated results. Further the enhancement of sensitivity is analyzed using non uniform thickness diaphragm and Silicon-On-Insulator (SOI technique. The simulation results indicate that the double boss square sculptured diaphragm with SOI layer using 0.85μm thickness yields the higher voltage sensitivity, acceptable linearity with Small Scale Deflection.

  4. Analysis of silicon on insulator (SOI) optical microring add-drop filter based on waveguide intersections

    Science.gov (United States)

    Kaźmierczak, Andrzej; Bogaerts, Wim; Van Thourhout, Dries; Drouard, Emmanuel; Rojo-Romeo, Pedro; Giannone, Domenico; Gaffiot, Frederic

    2008-04-01

    We present a compact passive optical add-drop filter which incorporates two microring resonators and a waveguide intersection in silicon-on-insulator (SOI) technology. Such a filter is a key element for designing simple layouts of highly integrated complex optical networks-on-chip. The filter occupies an area smaller than 10μm×10μm and exhibits relatively high quality factors (up to 4000) and efficient signal dropping capabilities. In the present work, the influence of filter parameters such as the microring-resonators radii and the coupling section shape are analyzed theoretically and experimentally

  5. A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

    2008-01-01

    A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

  6. Influence of germanium on thermal dewetting and agglomeration of the silicon template layer in thin silicon-on-insulator

    International Nuclear Information System (INIS)

    Zhang, P P; Yang, B; Rugheimer, P P; Roberts, M M; Savage, D E; Lagally, M G; Liu Feng

    2009-01-01

    We investigate the influence of heteroepitaxially grown Ge on the thermal dewetting and agglomeration of the Si(0 0 1) template layer in ultrathin silicon-on-insulator (SOI). We show that increasing Ge coverage gradually destroys the long-range ordering of 3D nanocrystals along the (1 3 0) directions and the 3D nanocrystal shape anisotropy that are observed in the dewetting and agglomeration of pure SOI(0 0 1). The results are qualitatively explained by Ge-induced bond weakening and decreased surface energy anisotropy. Ge lowers the dewetting and agglomeration temperature to as low as 700 0 C.

  7. Integrated circuits of silicon on insulator S.O.I. technologies: State of the art and perspectives

    International Nuclear Information System (INIS)

    Leray, J.L.; Dupont-Nivet, E.; Raffaelli, M.; Coic, Y.M.; Musseau, O.; Pere, J.F.; Lalande, P.; Bredy, J.; Auberton-Herve, A.J.; Bruel, M.; Giffard, B.

    1989-01-01

    Silicon On Insulator technologies have been proposed to increase the integrated circuits performances in radiation operation. Active researches are conducted, in France and abroad. This paper reviews briefly radiation effects phenomenology in that particular type of structure S.O.I. New results are presented that show very good radiation behaviour in term of speed, dose (10 to 100 megarad (Si)), dose rate and S.E.U. performances [fr

  8. Strong Electro-Absorption in GeSi Epitaxy on Silicon-on-Insulator (SOI

    Directory of Open Access Journals (Sweden)

    John E. Cunningham

    2012-04-01

    Full Text Available We have investigated the selective epitaxial growth of GeSi bulk material on silicon-on-insulator substrates by reduced pressure chemical vapor deposition. We employed AFM, SIMS, and Hall measurements, to characterize the GeSi heteroepitaxy quality. Optimal growth conditions have been identified to achieve low defect density, low RMS roughness with high selectivity and precise control of silicon content. Fabricated vertical p-i-n diodes exhibit very low dark current density of 5 mA/cm2 at −1 V bias. Under a 7.5 V/µm E-field, GeSi alloys with 0.6% Si content demonstrate very strong electro-absorption with an estimated effective ∆α/α around 3.5 at 1,590 nm. We compared measured ∆α/α performance to that of bulk Ge. Optical modulation up to 40 GHz is observed in waveguide devices while small signal analysis indicates bandwidth is limited by device parasitics.

  9. Characterization of light element impurities in ultrathin silicon-on-insulator layers by luminescence activation using electron irradiation

    International Nuclear Information System (INIS)

    Nakagawa-Toyota, Satoko; Tajima, Michio; Hirose, Kazuyuki; Ohshima, Takeshi; Itoh, Hisayoshi

    2009-01-01

    We analyzed light element impurities in ultrathin top Si layers of silicon-on-insulator (SOI) wafers by luminescence activation using electron irradiation. Photoluminescence (PL) analysis under ultraviolet (UV) light excitation was performed on various commercial SOI wafers after the irradiation. We detected the C-line related to a complex of interstitial carbon and oxygen impurities and the G-line related to a complex of interstitial and substitutional carbon impurities in the top Si layer with a thickness down to 62 nm after electron irradiation. We showed that there were differences in the impurity concentration depending on the wafer fabrication methods and also that there were variations in these concentrations in the respective wafers. Xenon ion implantation was used to activate top Si layers selectively so that we could confirm that the PL signal under the UV light excitation comes not from substrates but from top Si layers. The present method is a very promising tool to evaluate the light element impurities in top Si layers. (author)

  10. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  11. 110 GHz hybrid mode-locked fiber laser with enhanced extinction ratio based on nonlinear silicon-on-insulator micro-ring-resonator (SOI MRR)

    International Nuclear Information System (INIS)

    Liu, Yang; Hsu, Yung; Chow, Chi-Wai; Yang, Ling-Gang; Lai, Yin-Chieh; Yeh, Chien-Hung; Tsang, Hon-Ki

    2016-01-01

    We propose and experimentally demonstrate a new 110 GHz high-repetition-rate hybrid mode-locked fiber laser using a silicon-on-insulator microring-resonator (SOI MRR) acting as the optical nonlinear element and optical comb filter simultaneously. By incorporating a phase modulator (PM) that is electrically driven at a fraction of the harmonic frequency, an enhanced extinction ratio (ER) of the optical pulses can be produced. The ER of the optical pulse train increases from 3 dB to 10 dB. As the PM is only electrically driven by the signal at a fraction of the harmonic frequency, in this case 22 GHz (110 GHz/5 GHz), a low bandwidth PM and driving circuit can be used. The mode-locked pulse width and the 3 dB spectral bandwidth of the proposed mode-locked fiber laser are measured, showing that the optical pulses are nearly transform limited. Moreover, stability evaluation for an hour is performed, showing that the proposed laser can achieve stable mode-locking without the need for optical feedback or any other stabilization mechanism. (letter)

  12. Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

    Science.gov (United States)

    Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-12-13

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

  13. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

    Science.gov (United States)

    Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

    2018-05-01

    In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

  14. A high-temperature silicon-on-insulator stress sensor

    International Nuclear Information System (INIS)

    Wang Zheyao; Tian Kuo; Zhou Youzheng; Pan Liyang; Liu Litian; Hu Chaohong

    2008-01-01

    A piezoresistive stress sensor is developed using silicon-on-insulator (SOI) wafers and calibrated for stress measurement for high-temperature applications. The stress sensor consists of 'silicon-island-like' piezoresistor rosettes that are etched on the SOI layer. This eliminates leakage current and enables excellent electrical insulation at high temperature. To compensate for the measurement errors caused by the misalignment of the piezoresistor rosettes with respect to the crystallographic axes, an anisotropic micromachining technique, tetramethylammonium hydroxide etching, is employed to alleviate the misalignment issue. To realize temperature-compensated stress measurement, a planar diode is fabricated as a temperature sensor to decouple the temperature information from the piezoresistors, which are sensitive to both stress and temperature. Design, fabrication and calibration of the piezoresistors are given. SOI-related characteristics such as piezoresistive coefficients and temperature coefficients as well as the influence of the buried oxide layer are discussed in detail

  15. Silicon-on-Insulator Nanowire Based Optical Waveguide Biosensors

    International Nuclear Information System (INIS)

    Li, Mingyu; Liu, Yong; Chen, Yangqing; He, Jian-Jun

    2016-01-01

    Optical waveguide biosensors based on silicon-on-insulator (SOI) nanowire have been developed for label free molecular detection. This paper reviews our work on the design, fabrication and measurement of SOI nanowire based high-sensitivity biosensors employing Vernier effect. Biosensing experiments using cascaded double-ring sensor and Mach-Zehnder- ring sensor integrated with microfluidic channels are demonstrated (paper)

  16. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    Science.gov (United States)

    Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  17. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  18. Implant damage and redistribution of indium in indium-implanted thin silicon-on-insulator

    International Nuclear Information System (INIS)

    Chen Peng; An Zhenghua; Zhu Ming; Fu, Ricky K.Y.; Chu, Paul K.; Montgomery, Neil; Biswas, Sukanta

    2004-01-01

    The indium implant damage and diffusion behavior in thin silicon-on-insulator (SOI) with a 200 nm top silicon layer were studied for different implantation energies and doses. Rutherford backscattering spectrometry in the channeling mode (RBS/C) was used to characterize the implant damage before and after annealing. Secondary ion mass spectrometry (SIMS) was used to study the indium transient enhanced diffusion (TED) behavior in the top Si layer of the SOI structure. An anomalous redistribution of indium after relatively high energy (200 keV) and dose (1 x 10 14 cm -2 ) implantation was observed in both bulk Si and SOI substrates. However, there exist differences in these two substrates that are attributable to the more predominant out-diffusion of indium as well as the influence of the buried oxide layer in the SOI structure

  19. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  20. A high voltage SOI pLDMOS with a partial interface equipotential floating buried layer

    International Nuclear Information System (INIS)

    Wu Lijuan; Zhang Wentong; Zhang Bo; Li Zhaoji

    2013-01-01

    A novel silicon-on-insulator (SOI) high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer (FBL) and its analytical model is analyzed in this paper. The surface heavily doped p-top layers, interface floating buried N + /P + layers, and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance. On the condition of ESIMOX (epoxy separated by implanted oxygen), it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from −232 V of the conventional SOI to −425 V and the specific resistance R on,sp is reduced from 0.88 to 0.2424 Ω·cm 2 . (semiconductor devices)

  1. Total dose hardening of buried insulator in implanted silicon-on-insulator structures

    International Nuclear Information System (INIS)

    Mao, B.Y.; Chen, C.E.; Pollack, G.; Hughes, H.L.; Davis, G.E.

    1987-01-01

    Total dose characteristics of the buried insulator in implanted silicon-on-insulator (SOI) substrates have been studied using MOS transistors. The threshold voltage shift of the parasitic back channel transistor, which is controlled by charge trapping in the buried insulator, is reduced by lowering the oxygen dose as well as by an additional nitrogen implant, without degrading the front channel transistor characteristics. The improvements in the radiation characteristics of the buried insulator are attributed to the decrease in the buried oxide thickness or to the presence of the interfacial oxynitride layer formed by the oxygen and nitrogen implants

  2. Peculiarities of electronic structure of silicon-on-insulator structures and their interaction with synchrotron radiation

    Directory of Open Access Journals (Sweden)

    Vladimir A. Terekhov

    2015-09-01

    Full Text Available SOI (silicon-on-insulator structures with strained and unstrained silicon layers were studied by ultrasoft X-ray emission spectroscopy and X-ray absorption near edge structure spectroscopy with the use of synchrotron radiation techniques. Analysis of X-ray data has shown a noticeable transformation of the electron energy spectrum and local partial density of states distribution in valence and conduction bands in the strained silicon layer of the SOI structure. USXES Si L2,3 spectra analysis revealed a decrease of the distance between the L2v′ и L1v points in the valence band of the strained silicon layer as well as a shift of the first two maxima of the XANES first derivation spectra to the higher energies with respect to conduction band bottom Ec. At the same time the X-ray standing waves of synchrotron radiation (λ~12–20 nm are formed in the silicon-on-insulator structure with and without strains of the silicon layer. Moreover changing the synchrotron radiation grazing angle θ by 2° leads to a change of the electromagnetic field phase to the opposite.

  3. Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

    International Nuclear Information System (INIS)

    Zhang, Z.L.; Asano, T.; Uno, H.; Tero, R.; Suzui, M.; Nakao, S.; Kaito, T.; Shibasaki, K.; Tominaga, M.; Utsumi, Y.; Gao, Y.L.; Urisu, T.

    2008-01-01

    The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 μm diameter is formed through the top Si layer and the SiO 2 box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully

  4. Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Z.L.; Asano, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Uno, H. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Tero, R. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Suzui, M.; Nakao, S. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Kaito, T. [SII NanoTechnology Inc., 36-1, Takenoshita, Oyama-cho, Sunto-gun, Shizuoka, 410-1393 (Japan); Shibasaki, K.; Tominaga, M. [Okazaki Institute for Integrative Bioscience, 5-1, Higashiyama, Myodaiji, Okazaki, 444-8787 (Japan); Utsumi, Y. [Laboratory of Advanced Science and Technology for Industry, University of Hyogo, 3-1-2, Koto, Kamigori, Ako-gun, Hyogo, 678-1205 (Japan); Gao, Y.L. [Department of Physics and Astronomy, Rochester University, Rochester, New York 14627 (United States); Urisu, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan)], E-mail: urisu@ims.ac.jp

    2008-03-03

    The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 {mu}m diameter is formed through the top Si layer and the SiO{sub 2} box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully.

  5. Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

    Science.gov (United States)

    2016-08-01

    APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...high sound velocity — makes guiding acoustic waves difficult, motivating the use of soft chalcogenide glasses and partial or complete releases (removal

  6. A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

    International Nuclear Information System (INIS)

    Jamali Mahabadi, S E; Orouji, Ali A; Keshavarzi, P; Moghadam, Hamid Amini

    2011-01-01

    In this paper, for the first time, we propose a partial silicon-on-insulator (P-SOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) with a modified buried layer in order to improve breakdown voltage (BV) and self-heating effects (SHEs). The main idea of this work is to control the electric field by shaping the buried layer. With two steps introduced in the buried layer, the electric field distribution is modified. Also a P-type window introduced makes the substrate share the vertical voltage drop, leading to a high vertical BV. Moreover, four interface electric field peaks are introduced by the buried P-layer, the Si window and two steps, which modulate the electric field in the SOI layer and the substrate. Hence, a more uniform electric field is obtained; consequently, a high BV is achieved. Furthermore, the Si window creates a conduction path between the active layer and substrate and alleviates the SHE. Two-dimensional simulations show that the BV of double step partial silicon on insulator is nearly 69% higher and alleviates SHEs 17% in comparison with its single step partial SOI counterpart and nearly 265% higher and alleviate SHEs 18% in comparison with its conventional SOI counterpart

  7. A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

    International Nuclear Information System (INIS)

    Yuan, Yang; Yong, Gao; Peng-Liang, Gong

    2008-01-01

    A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  8. Hydrogen interactions with silicon-on-insulator materials

    OpenAIRE

    Rivera de Mena, A.J.

    2003-01-01

    The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

  9. Integrated programmable photonic filter on the silicon -on- insulator platform

    DEFF Research Database (Denmark)

    Liao, Shasha; Ding, Yunhong; Peucheret, Christophe

    2014-01-01

    We propose and demonstrate a silicon - on - insulator (SOI) on - chip programmable filter based on a four - tap finite impulse response structure. The photonic filter is programmable thanks to amplitude and phase modulation of each tap controlled by thermal heater s. We further demonstrate...... the tunability of the filter central wavelength, bandwidth and variable passband shape. The tuning range of the central wavelength is at least 42% of the free spectral range. The bandwidth tuning range is at least half of the free spectral range. Our scheme has distinct advantages of compactness, capability...

  10. Method to improve commercial bonded SOI material

    Science.gov (United States)

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  11. ARROW-based silicon-on-insulator photonic crystal waveguides with reduced losses

    DEFF Research Database (Denmark)

    Lavrinenko, Andrei; Novitsky, A.; Zhilko, V.V.

    2006-01-01

    We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits.......We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits....

  12. A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

    Energy Technology Data Exchange (ETDEWEB)

    Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

    2007-07-25

    A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

  13. Electron mobility in the inversion layers of fully depleted SOI films

    Energy Technology Data Exchange (ETDEWEB)

    Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

    2017-04-15

    The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.

  14. The effect of gate length on SOI-MOSFETS operation | Baedi ...

    African Journals Online (AJOL)

    The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

  15. Crosstalk analysis of silicon-on-insulator nanowire-arrayed waveguide grating

    International Nuclear Information System (INIS)

    Li Kai-Li; An Jun-Ming; Zhang Jia-Shun; Wang Yue; Wang Liang-Liang; Li Jian-Guang; Wu Yuan-Da; Yin Xiao-Jie; Hu Xiong-Wei

    2016-01-01

    The factors influencing the crosstalk of silicon-on-insulator (SOI) nanowire arrayed waveguide grating (AWG) are analyzed using the transfer function method. The analysis shows that wider and thicker arrayed waveguides, outsider fracture of arrayed waveguide, and larger channel space, could mitigate the deterioration of crosstalk. The SOI nanowire AWGs with different arrayed waveguide widths are fabricated by using deep ultraviolet lithography (DUV) and inductively coupled plasma etching (ICP) technology. The measurement results show that the crosstalk performance is improved by about 7 dB through adopting 800 nm arrayed waveguide width. (paper)

  16. High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

    International Nuclear Information System (INIS)

    Caër, Charles; Le Roux, Xavier; Cassan, Eric

    2013-01-01

    We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics

  17. A Numerical Study on Phonon Spectral Contributions to Thermal Conduction in Silicon-on-Insulator Transistor Using Electron-Phonon Interaction Model

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Hyung-sun; Koh, Young Ha; Jin, Jae Sik [Chosun College of Science and Technology, Gwangju (Korea, Republic of)

    2017-06-15

    The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

  18. Growth of light-emitting SiGe heterostructures on strained silicon-on-insulator substrates with a thin oxide layer

    Energy Technology Data Exchange (ETDEWEB)

    Baidakova, N. A., E-mail: banatale@ipmras.ru [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation); Bobrov, A. I. [University of Nizhny Novgorod (Russian Federation); Drozdov, M. N.; Novikov, A. V. [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation); Pavlov, D. A. [University of Nizhny Novgorod (Russian Federation); Shaleev, M. V.; Yunin, P. A.; Yurasov, D. V.; Krasilnik, Z. F. [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation)

    2015-08-15

    The possibility of using substrates based on “strained silicon on insulator” structures with a thin (25 nm) buried oxide layer for the growth of light-emitting SiGe structures is studied. It is shown that, in contrast to “strained silicon on insulator” substrates with a thick (hundreds of nanometers) oxide layer, the temperature stability of substrates with a thin oxide is much lower. Methods for the chemical and thermal cleaning of the surface of such substrates, which make it possible to both retain the elastic stresses in the thin Si layer on the oxide and provide cleaning of the surface from contaminating impurities, are perfecte. It is demonstrated that it is possible to use the method of molecular-beam epitaxy to grow light-emitting SiGe structures of high crystalline quality on such substrates.

  19. Computer simulation for the formation of the insulator layer of silicon-on-insulator devices by N sup + and O sup + Co-implantation

    CERN Document Server

    Lin Qing; Xie Xin Yun; Lin Chenglu; Liu Xiang Hua

    2002-01-01

    A buried sandwiched layer consisting of silicon dioxide (upper part), silicon oxynitride (medium part) and silicon nitride (lower part) is formed by N sup + and O sup + co-implantation in silicon wafers at a constant temperature of 550 degree C. The microstructure is performed by cross-sectional transmission electron microscopy. To predict the quality of the buried sandwiched layer, the authors study the computer simulation for the formation of the SIMON (separated by implantation of oxygen and nitrogen) structure. The simulation program for SIMOX (separated by implantation of oxygen) is improved in order to be applied in O sup + and N sup + co-implantation on the basis of different formation mechanism between SIMOX and SIMNI (separated by implantation of nitrogen) structures. There is a good agreement between experiment and simulation results verifying the theoretical model and presumption in the program

  20. Space and military radiation effects in silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Schwank, J.R.

    1996-09-01

    Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

  1. An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

    Science.gov (United States)

    Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2017-06-01

    Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

  2. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Science.gov (United States)

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  3. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  4. Gadolinium oxide coated fully depleted silicon-on-insulator transistors for thermal neutron dosimetry

    Energy Technology Data Exchange (ETDEWEB)

    Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu; Gouker, Pascale M.

    2013-09-01

    Fully depleted silicon-on-insulator transistors coated with gadolinium oxide are shown to be effective thermal neutron dosimeters. The theoretical neutron detection efficiency is calculated to be higher for Gd{sub 2}O{sub 3} than for other practical converter materials. Proof-of-concept dosimeter devices were fabricated and tested during thermal neutron irradiation. The transistor current changes linearly with neutron dose, consistent with increasing positive charge in the SOI buried oxide layer generated by ionization from high energy {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. The measured neutron sensitivity is approximately 1/6 the maximum theoretical value, possibly due to electron–hole recombination or conversion electron loss in interconnect wiring above the transistors. -- Highlights: • A novel Gd{sub 2}O{sub 3} coated FDSOI MOSFET thermal neutron dosimeter is presented. • Dosimeter can detect charges generated from {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. • Measured neutron sensitivity is comparable to that calculated theoretically. • Dosimeter requires zero power during operation, enabling new application areas.

  5. VCSELs and silicon light sources exploiting SOI grating mirrors

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2012-01-01

    In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI...... the Bragg reflector. Numerical simulations show that both the silicon light source and the VCSEL exploiting SOI grating mirrors have superior performances, compared to existing silicon light sources and long wavelength VCSELs. These devices are highly adequate for chip-level optical interconnects as well...

  6. Technology development for SOI monolithic pixel detectors

    International Nuclear Information System (INIS)

    Marczewski, J.; Domanski, K.; Grabiec, P.; Grodner, M.; Jaroszewicz, B.; Kociubinski, A.; Kucharski, K.; Tomaszewski, D.; Caccia, M.; Kucewicz, W.; Niemiec, H.

    2006-01-01

    A monolithic detector of ionizing radiation has been manufactured using silicon on insulator (SOI) wafers with a high-resistivity substrate. In our paper the integration of a standard 3 μm CMOS technology, originally designed for bulk devices, with fabrication of pixels in the bottom wafer of a SOI substrate is described. Both technological sequences have been merged minimizing thermal budget and providing suitable properties of all the technological layers. The achieved performance proves that fully depleted monolithic active pixel matrix might be a viable option for a wide spectrum of future applications

  7. X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates.

    Science.gov (United States)

    Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

    2013-08-01

    On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

  8. Broadband Silicon-On-Insulator directional couplers using a combination of straight and curved waveguide sections.

    Science.gov (United States)

    Chen, George F R; Ong, Jun Rong; Ang, Thomas Y L; Lim, Soon Thor; Png, Ching Eng; Tan, Dawn T H

    2017-08-03

    Broadband Silicon-On-Insulator (SOI) directional couplers are designed based on a combination of curved and straight coupled waveguide sections. A design methodology based on the transfer matrix method (TMM) is used to determine the required coupler section lengths, radii, and waveguide cross-sections. A 50/50 power splitter with a measured bandwidth of 88 nm is designed and fabricated, with a device footprint of 20 μm × 3 μm. In addition, a balanced Mach-Zehnder interferometer is fabricated showing an extinction ratio of >16 dB over 100 nm of bandwidth.

  9. Implantation of oxygen ions for the realization of SOS (silicon on insulator) structures: SIMOX

    International Nuclear Information System (INIS)

    Margail, J.

    1987-03-01

    Highdose oxygen implantation is becoming a serious candidate for SOI (silicon on insulator) structure realization. The fabrication condition study of these substrates allowed to show up the implantation and annealing parameter importance for microstructure, and particularly for crystal quality of silicon films. It has been shown that the use of high temperature annealings leads to high quality substrates: monocrystal silicon film without any precipitate, at the card scale; Si/Si O 2 interface formation. After annealing at 1340 O C, Hall mobilities have been measured in silicon film, and its residual doping is very low. First characteristics and performance of submicron CMOS circuits prooves the electric quality of these substrates [fr

  10. Guided acoustic and optical waves in silicon-on-insulator for Brillouin scattering and optomechanics

    Directory of Open Access Journals (Sweden)

    Christopher J. Sarabalis

    2016-10-01

    Full Text Available We numerically study silicon waveguides on silica showing that it is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI material system. Thin waveguides, or fins, exhibit geometrically softened mechanical modes at gigahertz frequencies with phase velocities below the Rayleigh velocity in glass, eliminating acoustic radiation losses. We propose slot waveguides on glass with telecom optical frequencies and strong radiation pressure forces resulting in Brillouin gains on the order of 500 and 50 000 W−1m−1 for backward and forward Brillouin scattering, respectively.

  11. Silicon-on-insulator-based polarization-independent 1×3 broadband beam splitter with adiabatic coupling

    Science.gov (United States)

    Gong, Yuanhao; Liu, Lei; Chang, Limin; Li, Zhiyong; Tan, Manqing; Yu, Yude

    2017-10-01

    We propose and numerically simulate a polarization-independent 1×3 broadband beam splitter based on silicon-on-insulator (SOI) technology with adiabatic coupling. The designed structure is simulated by beam-propagation-method (BPM) and gets simulated transmission uniformity of three outputs better than 0.3dB for TE-polarization and 0.8dB for TM-polarization in a broadband of 180nm.

  12. Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

    Science.gov (United States)

    Wu, Jiayang; Moein, Tania; Xu, Xingyuan; Moss, David J.

    2018-04-01

    We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI) nanowires implemented by cascaded Sagnac loop reflector (CSLR) resonators. We investigate mode splitting in these standing-wave (SW) resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs) and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

  13. Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

    Directory of Open Access Journals (Sweden)

    Jiayang Wu

    2018-04-01

    Full Text Available We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI nanowires implemented by cascaded Sagnac loop reflector (CSLR resonators. We investigate mode splitting in these standing-wave (SW resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

  14. The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator

    Science.gov (United States)

    Jafar, N.; Soin, N.

    2009-06-01

    This work presents the noise behaviour due to the applied Dual Material Gate (DMG) on the 75 nm n-channel Silicon On Insulator (SOI) device operating in the fully depletion mode, particularly for microwave circuit design. Influences of DMG properties namely the gate length ratio (L1:L2) and gate material workfunction difference (ΔΦM) as well as structural and operational parameters which are silicon thickness (TSi) and threshold voltage (VTH) setting variation on the noise performance were carried out on simulation basis using ATLAS 2D. Results show better noise performance in DMG as compare to the standard gate structure of FD-SOI devices. Higher VTH for DMG design is recommended for minimized noise figure in line with the advantage of inverse VTH roll-off characteristics for short channel effects suppression.

  15. Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

    International Nuclear Information System (INIS)

    Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

    2013-01-01

    Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

  16. Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

    Science.gov (United States)

    Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

    2013-06-01

    The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

  17. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Science.gov (United States)

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  18. Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

    Science.gov (United States)

    Skalare, Anders; Stern, Jeffrey; Bumble, Bruce; Maiwald, Frank

    2005-01-01

    A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

  19. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

    Science.gov (United States)

    Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

    2009-03-01

    The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

  20. SOI MESFETs for Extreme Environment Electronics, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — We are proposing a new extreme environment electronics (EEE) technology based on silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs)....

  1. Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

    Science.gov (United States)

    Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

    2009-10-01

    We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

  2. Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

    Science.gov (United States)

    Chiu, Yi; Pan, Jiun-Hung

    2007-05-14

    The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

  3. Interfacial phonon scattering and transmission loss in >1 μm thick silicon-on-insulator thin films

    Science.gov (United States)

    Jiang, Puqing; Lindsay, Lucas; Huang, Xi; Koh, Yee Kan

    2018-05-01

    Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1-10 μm and a temperature range of 100-300 K. The Si /SiO2 interface roughness was determined to be 0.11 ±0.04 nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

  4. Adiabatic Nanofocusing in Hybrid Gap Plasmon Waveguides on the Silicon-on-Insulator Platform.

    Science.gov (United States)

    Nielsen, Michael P; Lafone, Lucas; Rakovich, Aliaksandra; Sidiropoulos, Themistoklis P H; Rahmani, Mohsen; Maier, Stefan A; Oulton, Rupert F

    2016-02-10

    We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.

  5. Light extraction from GaN-based LED structures on silicon-on-insulator substrates

    Energy Technology Data Exchange (ETDEWEB)

    Tripathy, S.; Teo, S.L.; Lin, V.K.X.; Chen, M.F. [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology, and Research), 117602 (Singapore); Dadgar, A.; Krost, A. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany); AZZURRO Semiconductors AG, Universitaetsplatz 1, 39016 Magdeburg (Germany); Christen, J. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany)

    2010-01-15

    Nano-patterning of GaN-based devices is a promising technology in the development of high output power devices. Recent researches have been focused on the realization of two-dimensional (2D) photonic crystal (PhC) structure to improve light extraction efficiency and to control the direction of emission. In this study, we have demonstrated improved light extraction from green light emitting diode (LED) structures on thin silicon-on-insulator (SOI) substrates using surface nanopatterning. Scanning electron microscopy (SEM) is used to probe the size, shape, and etch depth of nano-patterns on the LED surfaces. Different types of nanopatterns were created by e-beam lithography and inductively coupled plasma etching. The LED structures after post processing are studied by photoluminescence (PL) measurements. The GaN nanophotonic structures formed by ICP etching led to more than five-fold increase in the intensity of the green emission. The improved light extraction is due to the combination of SOI substrate reflectivity and photonic structures on top GaN LED surfaces. (copyright 2010 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  6. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  7. A pile-up phenomenon during arsenic diffusion in silicon-on-insulator structures formed by oxygen implantation

    Science.gov (United States)

    Normand, P.; Tsoukalas, D.; Guillemot, N.; Chenevier, P.

    1989-10-01

    Arsenic diffusion in silicon-on-insulator formed by deep oxygen implantation is studied by secondary ion mass spectroscopy and speading resistance measurements. An enhanced diffusivity as well as a pile-up phenomenon are observed in the thin silicon layer. The McNabb and Foster equations [Trans. TMS-AIME 22, 618 (1963)] for diffusion with trapping are solved in order to simulate this last effect.

  8. Silicon-on-insulator based nanopore cavity arrays for lipid membrane investigation.

    Science.gov (United States)

    Buchholz, K; Tinazli, A; Kleefen, A; Dorfner, D; Pedone, D; Rant, U; Tampé, R; Abstreiter, G; Tornow, M

    2008-11-05

    We present the fabrication and characterization of nanopore microcavities for the investigation of transport processes in suspended lipid membranes. The cavities are situated below the surface of silicon-on-insulator (SOI) substrates. Single cavities and large area arrays were prepared using high resolution electron-beam lithography in combination with reactive ion etching (RIE) and wet chemical sacrificial underetching. The locally separated compartments have a circular shape and allow the enclosure of picoliter volume aqueous solutions. They are sealed at their top by a 250 nm thin Si membrane featuring pores with diameters from 2 µm down to 220 nm. The Si surface exhibits excellent smoothness and homogeneity as verified by AFM analysis. As biophysical test system we deposited lipid membranes by vesicle fusion, and demonstrated their fluid-like properties by fluorescence recovery after photobleaching. As clearly indicated by AFM measurements in aqueous buffer solution, intact lipid membranes successfully spanned the pores. The nanopore cavity arrays have potential applications in diagnostics and pharmaceutical research on transmembrane proteins.

  9. Al transmon qubits on silicon-on-insulator for quantum device integration

    Science.gov (United States)

    Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

    2017-07-01

    We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

  10. A monolithic active pixel sensor for ionizing radiation using a 180 nm HV-SOI process

    Energy Technology Data Exchange (ETDEWEB)

    Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany)

    2016-07-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-180 nm High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. Standard FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to trapped charge in the buried oxide layer and charged interface states created at the silicon oxide boundaries (back gate effect). The X-FAB 180 nm HV-SOI technology offers an additional isolation using a deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection. The design and measurement results from first prototypes are presented including radiation tolerance to total ionizing dose and charge collection properties of neutron irradiated samples.

  11. A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

    Energy Technology Data Exchange (ETDEWEB)

    Hemperek, Tomasz, E-mail: hemperek@uni-bonn.de; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

    2015-10-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

  12. Design, fabrication and characterisation of advanced substrate crosstalk suppression structures in silicon on insulator substrates with buried ground planes (GPSOI)

    International Nuclear Information System (INIS)

    Stefanou, Stefanos

    2002-07-01

    Substrate crosstalk or coupling has been acknowledged to be a limiting factor in mixed signal RF integration. Although high levels of integration and high frequencies of operation are desirable for mixed mode RF and microwave circuits, they make substrate crosstalk more pronounced and may lead to circuit performance degradation. High signal isolation is dictated by requirements for low power dissipation, reduced number of components and lower integration costs for feasible system-on-chip (SoC) solutions. Substrate crosstalk suppression in ground plane silicon-on-insulator (GPSOI) substrates is investigated in this thesis. Test structures are designed and fabricated on SOI substrates with a buried WSi 2 plane that is connected to ground; hence it is called a ground plane. A Faraday cage structure that exhibits very high degrees of signal isolation is presented and compared to other SOI isolation schemes. The Faraday cage structure is shown to achieve 20 dB increased isolation in the frequency range of 0.5-50 GHz compared to published data for high resistivity (200 Ωcm) thin film SOI substrates with no ground planes, but where capacitive guard rings were used. The measurement results are analysed with the aid of planar electromagnetic simulators and compact lumped element models of all the fabricated test structures are developed. The accuracy of the lumped models is validated against experimental measurements. (author)

  13. Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

    Directory of Open Access Journals (Sweden)

    Xiaojun Cheng

    2014-05-01

    Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

  14. Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted Silicon-on-Insulator Technology

    International Nuclear Information System (INIS)

    Servanton, G; Clement, L; Lepinay, K; Lorut, F; Pantel, R; Pofelski, A; Bicais, N

    2013-01-01

    The growing demand for wireless multimedia applications (smartphones, tablets, digital cameras) requires the development of devices combining both high speed performances and low power consumption. A recent technological breakthrough making a good compromise between these two antagonist conditions has been proposed: the 28-14nm CMOS transistor generations based on a fully-depleted Silicon-on-Insulator (FD-SOI) performed on a thin Si film of 5-6nm. In this paper, we propose to review the TEM characterization challenges that are essential for the development of extremely power-efficient System on Chip (SoC)

  15. A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

    Science.gov (United States)

    Ghaffari, Majid; Orouji, Ali A.

    2018-06-01

    Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

  16. Fully etched apodized grating coupler on the SOI platform with −058 dB coupling efficiency

    DEFF Research Database (Denmark)

    Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

    2014-01-01

    We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally investiga......We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally...

  17. A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure.

    Science.gov (United States)

    Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

    2017-12-23

    This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e - rms , low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

  18. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Science.gov (United States)

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  19. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

    2017-01-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

  20. Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Destefanis, V; Huguenin, J L; Samson, M P; Morand, Y; Arvet, C; Monfray, S; Skotnicki, T; Hartmann, J M; Delaye, V; Boulitreau, P; Brianceau, P; Gautier, P

    2010-01-01

    The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 °C in windows of patterned wafers are rough, we have first of all studied the 600 °C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 °C down to 600 °C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 °C and 725 °C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 °C on (1 0 0) or at 600 °C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5–3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were

  1. Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Ono, Shun, E-mail: s-ono@champ.hep.sci.osaka-u.ac.jp [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Togawa, Manabu; Tsuji, Ryoji; Mori, Teppei [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Yamada, Miho; Arai, Yasuo; Tsuboyama, Toru; Hanagaki, Kazunori [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org. (KEK), 1-1 Oho, Tsukuba (Japan)

    2017-02-11

    We have been developing a new monolithic pixel sensor with silicon-on-insulator (SOI) technology for the International Linear Collider (ILC) vertex detector system. The SOI monolithic pixel detector is realized using standard CMOS circuits fabricated on a fully depleted sensor layer. The new SOI sensor SOFIST can store both the position and timing information of charged particles in each 20×20 μm{sup 2} pixel. The position resolution is further improved by the position weighted with the charges spread to multiple pixels. The pixel also records the hit timing with an embedded time-stamp circuit. The sensor chip has column-parallel analog-to-digital conversion (ADC) circuits and zero-suppression logic for high-speed data readout. We are designing and evaluating some prototype sensor chips for optimizing and minimizing the pixel circuit.

  2. Novel Applications of a Thermally Tunable Bistable Buckling Silicon-on-Insulator (SOI) Microfabricated Membrane

    Science.gov (United States)

    2015-09-17

    sensor and disposable medical blood pressure sensor, which both hit the market in 1982 [2]. Since then, MEMS technology has undergone rapid growth and...Available: http: //digitalpicture.com.au/climate-change-slowing-trains/ 49. O. Tabata , K. Kawahata, S. Sugiyama, and I. Igarashi, “Mechanical property

  3. Performance study of double SOI image sensors

    Science.gov (United States)

    Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

    2018-02-01

    Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

  4. A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

    Energy Technology Data Exchange (ETDEWEB)

    DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

    1999-11-01

    Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

  5. Theoretical model for the detection of charged proteins with a silicon-on-insulator sensor

    International Nuclear Information System (INIS)

    Birner, S; Uhl, C; Bayer, M; Vogl, P

    2008-01-01

    For a bio-sensor device based on a silicon-on-insulator structure, we calculate the sensitivity to specific charge distributions in the electrolyte solution that arise from protein binding to the semiconductor surface. This surface is bio-functionalized with a lipid layer so that proteins can specifically bind to the headgroups of the lipids on the surface. We consider charged proteins such as the green fluorescent protein (GFP) and artificial proteins that consist of a variable number of aspartic acids. Specifically, we calculate self-consistently the spatial charge and electrostatic potential distributions for different ion concentrations in the electrolyte. We fully take into account the quantum mechanical charge density in the semiconductor. We determine the potential change at the binding sites as a function of protein charge and ionic strength. Comparison with experiment is generally very good. Furthermore, we demonstrate the superiority of the full Poisson-Boltzmann equation by comparing its results to the simplified Debye-Hueckel approximation

  6. Ultra-low-loss inverted taper coupler for silicon-on-insulator ridge waveguide

    DEFF Research Database (Denmark)

    Pu, Minhao; Liu, Liu; Ou, Haiyan

    2010-01-01

    An ultra-low-loss coupler for interfacing a silicon-on-insulator ridge waveguide and a single-mode fiber in both polarizations is presented. The inverted taper coupler, embedded in a polymer waveguide, is optimized for both the transverse-magnetic and transverse-electric modes through tapering...... the width of the silicon-on-insulator waveguide from 450 nm down to less than 15 nm applying a thermal oxidation process. Two inverted taper couplers are integrated with a 3-mm long silicon-on-insulator ridge waveguide in the fabricated sample. The measured coupling losses of the inverted taper coupler...... for transverse-magnetic and transverse-electric modes are ~0.36 dB and ~0.66 dB per connection, respectively....

  7. 360° tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

    DEFF Research Database (Denmark)

    Pu, Minhao; Xue, Weiqi; Liu, Liu

    2010-01-01

    We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained......We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained...

  8. Ultra-low loss nano-taper coupler for Silicon-on-Insulator ridge waveguide

    DEFF Research Database (Denmark)

    Pu, Minhao; Liu, Liu; Ou, Haiyan

    2010-01-01

    A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler.......A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler....

  9. Fabrication of open-top microchannel plate using deep X-ray exposure mask made with silicon on insulator substrate

    CERN Document Server

    Fujimura, T; Etoh, S I; Hattori, R; Kuroki, Y; Chang, S S

    2003-01-01

    We propose a high-aspect-ratio open-top microchannel plate structure. This type of microchannel plate has many advantages in electrophoresis. The plate was fabricated by deep X-ray lithography using synchrotron radiation (SR) light and the chemical wet etching process. A deep X-ray exposure mask was fabricated with a silicon on insulator (SOI) substrate. The patterned Si microstructure was micromachined into a thin Si membrane and a thick Au X-ray absorber was embedded in it by electroplating. A plastic material, polymethylmethacrylate (PMMA) was used for the plate substrate. For reduction of the exposure time and high-aspect-ratio fast wet development, the fabrication condition was optimized with respect to not the exposure dose but to the PMMA mean molecular weight (M.W.) changing after deep X-ray exposure as measured by gel permeation chromatography (GPC). Decrement of the PMMA M.W. and increment of the wet developer temperature accelerated the etching rate. Under optimized fabrication conditions, a microc...

  10. Label-free electrical determination of trypsin activity by a silicon-on-insulator based thin film resistor.

    Science.gov (United States)

    Neff, Petra A; Serr, Andreas; Wunderlich, Bernhard K; Bausch, Andreas R

    2007-10-08

    A silicon-on-insulator (SOI) based thin film resistor is employed for the label-free determination of enzymatic activity. We demonstrate that enzymes, which cleave biological polyelectrolyte substrates, can be detected by the sensor. As an application, we consider the serine endopeptidase trypsin, which cleaves poly-L-lysine (PLL). We show that PLL adsorbs quasi-irreversibly to the sensor and is digested by trypsin directly at the sensor surface. The created PLL fragments are released into the bulk solution due to kinetic reasons. This results in a measurable change of the surface potential allowing for the determination of trypsin concentrations down to 50 ng mL(-1). Chymotrypsin is a similar endopeptidase with a different specificity, which cleaves PLL with a lower efficiency as compared to trypsin. The activity of trypsin is analyzed quantitatively employing a kinetic model for enzyme-catalyzed surface reactions. Moreover, we have demonstrated the specific inactivation of trypsin by a serine protease inhibitor, which covalently binds to the active site of the enzyme.

  11. Widely tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

    DEFF Research Database (Denmark)

    Pu, Minhao; Liu, Liu; Xue, Weiqi

    2010-01-01

    We propose and demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator microring resonators. The phase-shifting range and the RF-power variation are analyzed. A maximum phase-shifting range of 0~600° is achieved by utilizing a dual-microring resonator...

  12. Nonlinear Optical Functions in Crystalline and Amorphous Silicon-on-Insulator Nanowires

    DEFF Research Database (Denmark)

    Baets, R.; Kuyken, B.; Liu, X.

    2012-01-01

    Silicon-on-Insulator nanowires provide an excellent platform for nonlinear optical functions in spite of the two-photon absorption at telecom wavelengths. Work on both crystalline and amorphous silicon nanowires is reviewed, in the wavelength range of 1.5 to 2.5 µm....

  13. Silicon on insulator technology. Characteristics. Applications; Technologies silicium sur isolant. Caracteristiques. Exemples d'application

    Energy Technology Data Exchange (ETDEWEB)

    Suat, J. P.; Peccoud, L.; Le Goascoz, V.; Garcia, M.; Mackowiak, E.

    1975-01-31

    The advantages resulting from a SOS (Silicon-on-Sapphire) MOS technology are demonstrated. Experimental results giving the performance of C.MOS and depletion-enrichment P-channel technologies are presented, with an application of Silicon on insulator on development, that is to say a 1024 bits MNOS memory, peripheral circuits being developed according to the depletion-enrichment technology.

  14. SOI Digital Accelerometer Based on Pull-in Time Configuration

    NARCIS (Netherlands)

    Pakula, L.S.; Rajaraman, V.; French, P.J.

    2009-01-01

    The operation principle, design, fabrication and measurement results of a quasi digital accelerometer fabricated on a thin silicon-on-insulator (SOI) substrate is presented. The accelerometer features quasi-digital output, therefore eliminating the need for analogue signal conditioning. The

  15. A high efficiency lateral light emitting device on SOI

    NARCIS (Netherlands)

    Hoang, T.; Le Minh, P.; Holleman, J.; Zieren, V.; Goossens, M.J.; Schmitz, Jurriaan

    2005-01-01

    The infrared light emission of lateral p/sup +/-p-n/sup +/ diodes realized on SIMOX-SOI (separation by implantation of oxygen - silicon on insulator) substrates has been studied. The confinement of the free carriers in one dimension due to the buried oxide was suggested to be a key point to increase

  16. Determination of the quasi-TE mode (in-plane) graphene linear absorption coefficient via integration with silicon-on-insulator racetrack cavity resonators.

    Science.gov (United States)

    Crowe, Iain F; Clark, Nicholas; Hussein, Siham; Towlson, Brian; Whittaker, Eric; Milosevic, Milan M; Gardes, Frederic Y; Mashanovich, Goran Z; Halsall, Matthew P; Vijayaraghaven, Aravind

    2014-07-28

    We examine the near-IR light-matter interaction for graphene integrated cavity ring resonators based on silicon-on-insulator (SOI) race-track waveguides. Fitting of the cavity resonances from quasi-TE mode transmission spectra reveal the real part of the effective refractive index for graphene, n(eff) = 2.23 ± 0.02 and linear absorption coefficient, α(gTE) = 0.11 ± 0.01dBμm(-1). The evanescent nature of the guided mode coupling to graphene at resonance depends strongly on the height of the graphene above the cavity, which places limits on the cavity length for optical sensing applications.

  17. An integrated optic ethanol vapor sensor based on a silicon-on-insulator microring resonator coated with a porous ZnO film.

    Science.gov (United States)

    Yebo, Nebiyu A; Lommens, Petra; Hens, Zeger; Baets, Roel

    2010-05-24

    Optical structures fabricated on silicon-on-insulator technology provide a convenient platform for the implementation of highly compact, versatile and low cost devices. In this work, we demonstrate the promise of this technology for integrated low power and low cost optical gas sensing. A room temperature ethanol vapor sensor is demonstrated using a ZnO nanoparticle film as a coating on an SOI micro-ring resonator of 5 microm in radius. The local coating on the ring resonators is prepared from colloidal suspensions of ZnO nanoparticles of around 3 nm diameter. The porous nature of the coating provides a large surface area for gas adsorption. The ZnO refractive index change upon vapor adsorption shifts the microring resonance through evanescent field interaction. Ethanol vapor concentrations down to 100 ppm are detected with this sensing configuration and a detection limit below 25 ppm is estimated.

  18. Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

    International Nuclear Information System (INIS)

    Huang Pengcheng; Chen Shuming; Chen Jianjun

    2016-01-01

    In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout. (paper)

  19. Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

    International Nuclear Information System (INIS)

    Wang Zhigang; Zhang Bo; Li Zhaoji

    2013-01-01

    A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

  20. Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

    International Nuclear Information System (INIS)

    Li Lei; Zhou Wanting; Liu Huihua

    2012-01-01

    In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 μm technology. (author)

  1. Vertical integration of high-Q silicon nitride microresonators into silicon-on-insulator platform.

    Science.gov (United States)

    Li, Qing; Eftekhar, Ali A; Sodagar, Majid; Xia, Zhixuan; Atabaki, Amir H; Adibi, Ali

    2013-07-29

    We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

  2. Compact wavelength-insensitive fabrication-tolerant silicon-on-insulator beam splitter.

    Science.gov (United States)

    Rasigade, Gilles; Le Roux, Xavier; Marris-Morini, Delphine; Cassan, Eric; Vivien, Laurent

    2010-11-01

    A star coupler-based beam splitter for rib waveguides is reported. A design method is presented and applied in the case of silicon-on-insulator rib waveguides. Experimental results are in good agreement with simulations. Excess loss lower than 1 dB is experimentally obtained for star coupler lengths from 0.5 to 1 μm. Output balance is better than 1 dB, which is the measurement accuracy, and broadband transmission is obtained over 90 nm.

  3. Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

    Science.gov (United States)

    Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

    2011-06-01

    For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

  4. Luminescence properties of ZnO layers grown on Si-on-insulator substrates

    International Nuclear Information System (INIS)

    Kumar, Bhupendra; Gong, Hao; Vicknesh, S.; Chua, S. J.; Tripathy, S.

    2006-01-01

    The authors report on the photoluminescence properties of polycrystalline ZnO thin films grown on compliant silicon-on-insulator (SOI) substrates by radio frequency magnetron sputtering. The ZnO thin films on SOI were characterized by micro-Raman and photoluminescence (PL) spectroscopy. The observation of E 2 high optical phonon mode near 438 cm -1 in the Raman spectra of the ZnO samples represents the wurtzite crystal structure. Apart from the near-band-edge free exciton (FX) transition around 3.35 eV at 77 K, the PL spectra of such ZnO films also showed a strong defect-induced violet emission peak in the range of 3.05-3.09 eV. Realization of such ZnO layers on SOI would be useful for heterointegration with SOI-based microelectronics and microelectromechanical systems

  5. Electrical activation of solid-phase epitaxially regrown ultra-low energy boron implants in Ge preamorphised silicon and SOI

    International Nuclear Information System (INIS)

    Hamilton, J.J.; Collart, E.J.H.; Colombeau, B.; Jeynes, C.; Bersani, M.; Giubertoni, D.; Sharp, J.A.; Cowern, N.E.B.; Kirkby, K.J.

    2005-01-01

    The formation of highly activated ultra-shallow junctions (USJ) is one of the key requirements for the next generation of CMOS devices. One promising method for achieving this is the use of Ge preamorphising implants (PAI) prior to ultra-low energy B implantation. In future technology nodes, bulk silicon wafers may be supplanted by Silicon-on-Insulator (SOI), and an understanding of the Solid Phase Epitaxial (SPE) regrowth process and its correlation to dopant electrical activation in both bulk silicon and SOI is essential in order to understand the impact of this potential technology change. This kind of understanding will also enable tests of fundamental models for defect evolution and point-defect reactions at silicon/oxide interfaces. In the present work, B is implanted into Ge PAI silicon and SOI wafers with different PAI conditions and B doses, and resulting samples are annealed at various temperatures and times. Glancing-exit Rutherford Backscattering Spectrometry (RBS) is used to monitor the regrowth of the amorphous silicon, and the resulting redistribution and electrical activity of B are monitored by SIMS and Hall measurements. The results confirm the expected enhancement of regrowth velocity by B doping, and show that this velocity is otherwise independent of the substrate type and the Ge implant distribution within the amorphised layer. Hall measurements on isochronally annealed samples show that B deactivates less in SOI material than in bulk silicon, in cases where the Ge PAI end-of-range defects are close to the SOI back interface

  6. Process Optimization for Monolithic Integration of Piezoresistive Pressure Sensor and MOSFET Amplifier with SOI Approach

    International Nuclear Information System (INIS)

    Kumar, V Vinoth; Dasgupta, A; Bhat, K N; KNatarajan

    2006-01-01

    In this paper we present the design and process optimization for fabricating piezoresitive pressure sensor and MOSFET Differential Amplifier simultaneously on the same chip. Silicon On Insulator approach has been used for realizing the membrane as well as the electronics on the same chip. The amplifier circuit has been configured in the common source connection and it has been designed with PSPICE simulation to achieve a voltage gain of about 5. In the initial set of experiments the Pressure sensor and the amplifier were fabricated on separate chips to optimize the process steps and tested in the hybrid mode. In the next set of experiments, SOI wafer having the SOI layer thickness of about 11 microns was used for realizing the membrane by anisotropic etching from the backside. The piezo-resistive pressure sensor was realized on this membrane by connecting the polysilicon resistors in the form of a Wheatstone bridge. The MOSFET source follower amplifier was also fabricated on the same SOI wafer by tailoring the process steps to suit the requirement of simultaneous fabrication of piezoresistors and the amplifier for achieving MOSFET Integrated Pressure Sensor. Reproducible results have been achieved on the SOI wafers, with the process steps developed in the laboratory. Sensitivity of 270 mV /Bar/10V, with the on chip amplifier gain of 4.5, has been achieved with this process

  7. Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2010-01-01

    Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  8. A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

    Science.gov (United States)

    Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

    2015-09-01

    In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

  9. A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques

    International Nuclear Information System (INIS)

    Yu-Feng, Guo; Zhi-Gong, Wang; Gene, Sheu; Jian-Bing, Cheng

    2010-01-01

    We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, two-dimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  10. Observation of an optical event horizon in a silicon-on-insulator photonic wire waveguide.

    Science.gov (United States)

    Ciret, Charles; Leo, François; Kuyken, Bart; Roelkens, Gunther; Gorza, Simon-Pierre

    2016-01-11

    We report on the first experimental observation of an optical analogue of an event horizon in integrated nanophotonic waveguides, through the reflection of a continuous wave on an intense pulse. The experiment is performed in a dispersion-engineered silicon-on-insulator waveguide. In this medium, solitons do not suffer from Raman induced self-frequency shift as in silica fibers, a feature that is interesting for potential applications of optical event horizons. As shown by simulations, this also allows the observation of multiple reflections at the same time on fundamental solitons ejected by soliton fission.

  11. High temperature study of flexible silicon-on-insulator fin field-effect transistors

    KAUST Repository

    Diab, Amer El Hajj

    2014-09-29

    We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

  12. Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

    Science.gov (United States)

    Liu, Yongxun; Tanaka, Hiroyuki; Umeyama, Norio; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2018-06-01

    P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular silicon-on-insulator (SOI) diaphragms using a cost-effective minimal-fab process, and their electrical characteristics have been systematically investigated before and after the SOI diaphragm formation. It was found that almost the same subthreshold slope (S-slope) and threshold voltage (V t) are observed in the fabricated PMOSFETs before and after the SOI diaphragm formation, and they are independent of the channel direction. On the other hand, significant variations in drain current were observed in the fabricated PMOSFETs with the 〈110〉 channel direction after the SOI diaphragm formation owing to the residual mechanical stress-induced piezoresistive effect. It was also confirmed that electrical characteristics of the fabricated PMOSFETs with the 〈100〉 channel direction are almost the same before and after the SOI diaphragm formation, i.e., not sensitive to the mechanical stress. Moreover, the drain current variations at different directions of mechanical stress and current flow were systematically investigated and discussed.

  13. Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    2016-01-01

    : off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize...

  14. Formation and dielectric properties of polyelectrolyte multilayers studied by a silicon-on-insulator based thin film resistor.

    Science.gov (United States)

    Neff, Petra A; Wunderlich, Bernhard K; Klitzing, Regine V; Bausch, Andreas R

    2007-03-27

    The formation of polyelectrolyte multilayers (PEMs) is investigated using a silicon-on-insulator based thin film resistor which is sensitive to variations of the surface potential. The buildup of the PEMs at the silicon oxide surface of the device can be observed in real time as defined potential shifts. The influence of polymer charge density is studied using the strong polyanion poly(styrene sulfonate), PSS, combined with the statistical copolymer poly(diallyl-dimethyl-ammoniumchloride-stat-N-methyl-N-vinylacetamide), P(DADMAC-stat-NMVA), at various degrees of charge (DC). The multilayer formation stops after a few deposition steps for a DC below 75%. We show that the threshold of surface charge compensation corresponds to the threshold of multilayer formation. However, no reversion of the preceding surface charge was observed. Screening of polyelectrolyte charges by mobile ions within the polymer film leads to a decrease of the potential shifts with the number of layers deposited. This decrease is much slower for PEMs consisting of P(DADMAC-stat-NMVA) and PSS as compared to PEMs consisting of poly(allylamine-hydrochloride), PAH, and PSS. From this, significant differences in the dielectric constants of the polyelectrolyte films and in the concentration of mobile ions within the films can be derived.

  15. Performance analysis of SOI MOSFET with rectangular recessed channel

    Science.gov (United States)

    Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

    2016-03-01

    In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

  16. Performance analysis of SOI MOSFET with rectangular recessed channel

    International Nuclear Information System (INIS)

    Singh, M; Mishra, G P; Mishra, S; Mohanty, S S

    2016-01-01

    In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed. (paper)

  17. Evanescently Coupled Rectangular Microresonators in Silicon-on-Insulator with High Q-Values: Experimental Characterization

    Directory of Open Access Journals (Sweden)

    Manuel Mendez-Astudillo

    2017-04-01

    Full Text Available We report on evanescently coupled rectangular microresonators with dimensions up to 20 × 10 μm2 in silicon-on-insulator in an add-drop filter configuration. The influence of the geometrical parameters of the device was experimentally characterized and a high Q value of 13,000 was demonstrated as well as the multimode optical resonance characteristics in the drop port. We also show a 95% energy transfer between ports when the device is operated in TM-polarization and determine the full symmetry of the device by using an eight-port configuration, allowing the drop waveguide to be placed on any of its sides, providing a way to filter and route optical signals. We used the FDTD method to analyze the device and e-beam lithography and dry etching techniques for fabrication.

  18. Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

    Science.gov (United States)

    Doris, B.; DeSalvo, B.; Cheng, K.; Morin, P.; Vinet, M.

    2016-03-01

    This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint development program between IBM, ST Microelectronics and CEA-LETI. In particular, we review the technological developments ranging from substrate engineering to process modules that enable functionality and improve FDSOI performance over several generations. Various multi Vt integration schemes to maximize the benefits of the thin BOX FDSOI platform are discussed. Manufacturability as well as scalability concerns are highlighted and addressed. In addition, this work provides understanding of the performance/power trade-offs for FDSOI circuits and device variability. Finally, clear directions for future application-specific products are given, demonstrating that FDSOI is an attractive CMOS option for next generation high performance and low-power applications.

  19. A technique for simultaneously improving the product of cutoff frequency-breakdown voltage and thermal stability of SOI SiGe HBT

    Science.gov (United States)

    Fu, Qiang; Zhang, Wan-Rong; Jin, Dong-Yue; Zhao, Yan-Xiao; Wang, Xiao

    2016-12-01

    The product of the cutoff frequency and breakdown voltage (fT×BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (TBOX) on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEO to some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT, BVCEO, and the FOM of fT×BVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEO is improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer

  20. A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

    International Nuclear Information System (INIS)

    Fu Qiang; Zhang Wan-Rong; Jin Dong-Yue; Zhao Yan-Xiao; Wang Xiao

    2016-01-01

    The product of the cutoff frequency and breakdown voltage ( f T ×BV CEO ) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of f T ×BV CEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness ( T BOX ) on f T , BV CEO , and the FOM of f T ×BV CEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces f T , slightly increases BV CEO to some extent, but ultimately degrades the FOM of f T ×BV CEO . Although the f T , BV CEO , and the FOM of f T ×BV CEO can be improved by increasing SOI insulator SiO 2 layer thickness T BOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO 2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick T BOX , a thin N + -buried layer is introduced into collector region to not only improve the FOM of f T ×BV CEO , but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. The result show that the FOM of f T ×BV CEO is improved and the device temperature decreases as the N + -buried layer shifts toward SOI substrate insulation layer

  1. Formation of SIMOX–SOI structure by high-temperature oxygen implantation

    International Nuclear Information System (INIS)

    Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

    2015-01-01

    We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 10"1"7–10"1"8 ions/cm"2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO_2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO_2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

  2. SOI MESFETs on high-resistivity, trap-rich substrates

    Science.gov (United States)

    Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

    2018-04-01

    The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

  3. Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

    Science.gov (United States)

    Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

    2018-02-01

    We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

  4. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    Science.gov (United States)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

  5. Optical microcavities based on surface modes in two-dimensional photonic crystals and silicon-on-insulator photonic crystals

    DEFF Research Database (Denmark)

    Xiao, Sanshui; Qiu, M.

    2007-01-01

    Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor is gr...... is gradually enhanced and the resonant frequency converges to that of the corresponding surface mode in the photonic crystals. These structures have potential applications such as sensing.......Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor...

  6. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

    International Nuclear Information System (INIS)

    Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

    2013-01-01

    A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  7. Modelling of a DBR laser based on Raman effect in a silicon-on-insulator rib waveguide

    International Nuclear Information System (INIS)

    De Leonardis, Francesco; Dimastrodonato, Valeria; Passaro, Vittorio M N

    2008-01-01

    In this paper, third-order nonlinearities in silicon-on-insulator rib waveguides are investigated to obtain complete modelling, describing the behaviour of a stimulated Raman scattering based laser. The simulations of a distributed Bragg reflector laser operation in a time domain allow for the first time to study in detail the dependence of threshold and output powers on different device parameters. Both continuous wave and pulsed laser operations are theoretically demonstrated, as well as their dependence on device parameters

  8. Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

    Science.gov (United States)

    Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

    2018-02-01

    In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

  9. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  10. Solar thermoelectric generators fabricated on a silicon-on-insulator substrate

    International Nuclear Information System (INIS)

    De Leon, Maria Theresa; Chong, Harold; Kraft, Michael

    2014-01-01

    Solar thermal power generation is an attractive electricity generation technology as it is environment-friendly, has the potential for increased efficiency, and has high reliability. The design, modelling, and evaluation of solar thermoelectric generators (STEGs) fabricated on a silicon-on-insulator substrate are presented in this paper. Solar concentration is achieved by using a focusing lens to concentrate solar input onto the membrane of the STEG. A thermal model is developed based on energy balance and heat transfer equations using lumped thermal conductances. This thermal model is shown to be in good agreement with actual measurement results. For a 1 W laser input with a spot size of 1 mm, a maximum open-circuit voltage of 3.06 V is obtained, which translates to a temperature difference of 226 °C across the thermoelements and delivers 25 µW of output power under matched load conditions. Based on solar simulator measurements, a maximum TEG voltage of 803 mV was achieved by using a 50.8 mm diameter plano-convex lens to focus solar input to a TEG with a length of 1000 µm, width of 15 µm, membrane diameter of 3 mm, and 114 thermocouples. This translates to a temperature difference of 18 °C across the thermoelements and an output power under matched load conditions of 431 nW. This paper demonstrates that by utilizing a solar concentrator to focus solar radiation onto the hot junction of a TEG, the temperature difference across the device is increased; subsequently improving the TEG’s efficiency. By using materials that are compatible with standard CMOS and MEMS processes, integration of solar-driven TEGs with on-chip electronics is seen to be a viable way of solar energy harvesting where the resulting microscale system is envisioned to have promising applications in on-board power sources, sensor networks, and autonomous microsystems. (paper)

  11. Tunable complex-valued multi-tap microwave photonic filter based on single silicon-on-insulator microring resonator.

    Science.gov (United States)

    Lloret, Juan; Sancho, Juan; Pu, Minhao; Gasulla, Ivana; Yvind, Kresten; Sales, Salvador; Capmany, José

    2011-06-20

    A complex-valued multi-tap tunable microwave photonic filter based on single silicon-on-insulator microring resonator is presented. The degree of tunability of the approach involving two, three and four taps is theoretical and experimentally characterized, respectively. The constraints of exploiting the optical phase transfer function of a microring resonator aiming at implementing complex-valued multi-tap filtering schemes are also reported. The trade-off between the degree of tunability without changing the free spectral range and the number of taps is studied in-depth. Different window based scenarios are evaluated for improving the filter performance in terms of the side-lobe level.

  12. Investigation of the stability of polysilicon layers in SOI-structures under irradiation by electrons and hard magnetic field influence

    Directory of Open Access Journals (Sweden)

    Khoverko Yu. N.

    2010-10-01

    Full Text Available The properties of recrystallized polysilicon on insulator layers of p-type conductive SOI-structures with different carrier concentration irradiated with high-energy electrons flow about 1017 сm–2 in temperature range 4,2—300 К and high magnetic fields were investigated. It was found that heavily doped laser recrystallized polysilicon on insulator layers show its radiation resistance under irradiation with high-energy electrons and magnetoresistance of such material remains quite low in magnetic field about 14 T does not exceed 1—2%. Such qulity can be applied in designing of microelectronic sensors of mechanical values operable in hard conditions of exploitation.

  13. Research on SOI-based micro-resonator devices

    Science.gov (United States)

    Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

    2010-10-01

    SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of 10 Gbit/s high speed microring modulators.

  14. Thin NbN film structures on SOI for SNSPD

    Energy Technology Data Exchange (ETDEWEB)

    Il' in, Konstantin; Kurz, Stephan; Henrich, Dagmar; Hofherr, Matthias; Siegel, Michael [IMS, KIT, Karlsruhe (Germany); Semenov, Alexei; Huebers, Heinz-Wilhelm [DLR, Berlin (Germany)

    2012-07-01

    Superconducting Nanowire Single-Photon Detectors (SNSPD) made from ultra-thin NbN films on sapphire demonstrate almost 100% intrinsic detection efficiency (DE). However the system DE values is less than 10% mostly limited by a very low absorptance of NbN films thinner than 5 nm. Integration of SNSPD in Si photonic circuit is a promising way to overcome this problem. We present results on optimization of technology of thin NbN film nanostructures on SOI (Silicon on Insulator) substrate used in Si photonics technology. Superconducting and normal state properties of these structures important for SNSPD development are presented and discussed.

  15. Characterization of SOI monolithic detector system

    Science.gov (United States)

    Álvarez-Rengifo, P. L.; Soung Yee, L.; Martin, E.; Cortina, E.; Ferrer, C.

    2013-12-01

    A monolithic active pixel sensor for charged particle tracking was developed. This research is performed within the framework of an R&D project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology) whose aim is to evaluate the feasibility of developing a Monolithic Active Pixel Sensor (MAPS) with Silicon-on-Insulator (SOI) technology. Two chips were fabricated: TRAPPISTe-1 and TRAPPISTe-2. TRAPPISTe-1 was produced at the WINFAB facility at the Université catholique de Louvain (UCL), Belgium, in a 2 μm fully depleted (FD-SOI) CMOS process. TRAPPISTe-2 was fabricated with the LAPIS 0.2 μm FD-SOI CMOS process. The electrical characterization on single transistor test structures and of the electronic readout for the TRAPPISTe series of monolithic pixel detectors was carried out. The behavior of the prototypes’ electronics as a function of the back voltage was studied. Results showed that both readout circuits exhibited sensitivity to the back voltage. Despite this unwanted secondary effect, the responses of TRAPPISTe-2 amplifiers can be improved by a variation in the circuit parameters.

  16. LORINE: Neutron emission Locator by SOI detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hamrita, H.; Kondrasovs, V.; Borbotte, J. M.; Normand, S. [CEA, LIST, Laboratoire Capteurs et Architectures Electronique, F-91191 Gif-sur-Yvette Cedex (France); Saurel, N. [CEA, DAM, VALDUC, F-21120 Is sur Tille (France)

    2009-07-01

    The aim of this work is to develop a fast Neutron Emission Locator based on silicon on Insulator detector (LORINE). This locator can be used in the presence of significant flux of gamma radiation. LORINE was developed to locate areas containing a significant amount of actinide during the dismantling operations of equipment. From the results obtained in laboratory, we have proposed the prototype of neutron emission locator as follows: the developed design consists of 5 SOI (Silicon-on-insulator) detectors (1*1 cm{sup 2}) with their charge preamplifiers and their respective converters. All are installed on 5 faces of a boron polyethylene cube (5*5*5 cm{sup 3}). This cube plays the role of neutron shielding between the several detectors. The design must be so compact for use in glove boxes. An electronic card based on micro-controller has been made to control sensors and to send the necessary information to the computer. Location of fast neutron sources does not yet exist in a so compact design and it can be operated in the presence of very important gamma radiation flux

  17. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  18. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  19. HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

    Science.gov (United States)

    Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

    2000-08-01

    Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

  20. Towards Polarization Diversity on the SOI Platform With Simple Fabrication Process

    DEFF Research Database (Denmark)

    Ding, Yunhong; Liu, Liu; Peucheret, Christophe

    2011-01-01

    We present a polarization diversity circuit built on the silicon-on-insulator (SOI) platform, which can be fabricated by a simple process. The polarization diversity is based on two identical air-clad asymmetrical directional couplers, which simultaneously play the roles of polarization splitter...... and rotator. A silicon polarization diversity circuit with a single microring resonator is fabricated on the SOI platform. Only ${1-dB polarization-dependent loss is demonstrated. A significant improvement of the polarization dependence is obtained for 20-Gb/s nonreturn-to-zero differential phase-shift keying...

  1. Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

    Science.gov (United States)

    Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

    2003-05-01

    Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

  2. Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

    International Nuclear Information System (INIS)

    Li Jin; Liu Hongxia; Li Bin; Cao Lei; Yuan Bo

    2010-01-01

    For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a 'rollup' in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. (semiconductor devices)

  3. Improving breakdown voltage performance of SOI power device with folded drift region

    Science.gov (United States)

    Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

    2016-07-01

    A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  4. An SEU resistant 256K SOI SRAM

    Science.gov (United States)

    Hite, L. R.; Lu, H.; Houston, T. W.; Hurta, D. S.; Bailey, W. E.

    1992-12-01

    A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition.

  5. A novel SOI pressure sensor for high temperature application

    International Nuclear Information System (INIS)

    Li Sainan; Liang Ting; Wang Wei; Hong Yingping; Zheng Tingli; Xiong Jijun

    2015-01-01

    The silicon on insulator (SOI) high temperature pressure sensor is a novel pressure sensor with high-performance and high-quality. A structure of a SOI high-temperature pressure sensor is presented in this paper. The key factors including doping concentration and power are analyzed. The process of the sensor is designed with the critical process parameters set appropriately. The test result at room temperature and high temperature shows that nonlinear error below is 0.1%, and hysteresis is less than 0.5%. High temperature measuring results show that the sensor can be used for from room temperature to 350 °C in harsh environments. It offers a reference for the development of high temperature piezoresistive pressure sensors. (semiconductor devices)

  6. Performance of the INTPIX6 SOI pixel detector

    Science.gov (United States)

    Arai, Y.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Kucewicz, W.; Miyoshi, T.; Turala, M.

    2017-01-01

    Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e-. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e-. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

  7. Ultra compact triplexing filters based on SOI nanowire AWGs

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei, E-mail: junming@red.semi.ac.cn [State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2011-04-15

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

  8. Ultra compact triplexing filters based on SOI nanowire AWGs

    International Nuclear Information System (INIS)

    Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei

    2011-01-01

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

  9. Ultra compact triplexing filters based on SOI nanowire AWGs

    Science.gov (United States)

    Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

    2011-04-01

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

  10. Test-beam results of a SOI pixel detector prototype

    CERN Document Server

    Bugiel, Roma; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Idzik, Marek; Kapusta, P; Kucewicz, Wojciech; Munker, Ruth Magdalena; Nurnberg, Andreas Matthias

    2018-01-01

    This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 μm thick high-resistivity float- zone n-type (FZ-n) wafer. The pixel size is 30 μm × 30 μm and its readout uses a source- follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and η-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 μm.

  11. arXiv Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

    CERN Document Server

    INSPIRE-00541780; Cindro, V.; Gorišek, A.; Hemperek, T.; Kishishita, T.; Kramberger, G.; Krüger, H.; Mandić, I.; Mikuž, M.; Wermes, N.; Zavrtanik, M.

    2017-10-25

    Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1x10e16 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5x10e14 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The r...

  12. Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2016-10-01

    For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

  13. Silicon on insulator by ion implantation: A dream or a reality

    Energy Technology Data Exchange (ETDEWEB)

    Pinizzotto, R F [Ultrastructure, Inc., Richardson, TX (USA)

    1985-03-01

    One method of producing a silicon-on-oxide structure is to implant a sufficient dose of oxygen into a conventional silicon substrate to synthesize a layer of SiO/sub 2/ just below the surface. If the proper implant conditions are maintained, the top silicon layer will be a single crystal. The required doses are large, but the use of commercially available medium current implanters can reduce the time to 25 minutes per wafer. This adds about $ 10 per chip in process related costs. A very large implanter (100 mA analyzed beam) may not be the best approach for scaling up the process. The power in the beam and the power required for operation of the machine are both enormous. A more conservative approach of using multiple medium current implanters may prove to be more economical in the long run.

  14. Fabrication of SGOI material by oxidation of an epitaxial SiGe layer on an SOI wafer with H ions implantation

    International Nuclear Information System (INIS)

    Cheng Xinli; Chen Zhijun; Wang Yongjin; Jin Bo; Zhang Feng; Zou Shichang

    2005-01-01

    SGOI materials were fabricated by thermal dry oxidation of epitaxial H-ion implanted SiGe layers on SOI wafers. The hydrogen implantation was found to delay the oxidation rate of SiGe layer and to decrease the loss of Ge atoms during oxidation. Further, the H implantation did not degrade the crystallinity of SiGe layer during fabrication of the SGOI

  15. Electronics and Sensor Study with the OKI SOI process

    CERN Document Server

    Arai, Yasuo

    2007-01-01

    While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI proces...

  16. Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

    Science.gov (United States)

    Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

    2013-03-25

    n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

  17. A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

    Science.gov (United States)

    2014-01-01

    ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

  18. Comparative study of SOI/Si hybrid substrates fabricated using high-dose and low-dose oxygen implantation

    International Nuclear Information System (INIS)

    Dong Yemin; Chen Meng; Chen Jing; Wang Xiang; Wang Xi

    2004-01-01

    Hybrid substrates comprising both silicon-on-insulator (SOI) and bulk Si regions have been fabricated using the technique of patterned separation by implantation of oxygen (SIMOX) with high-dose (1.5 x 10 18 cm -2 ) and low-dose ((1.5-3.5) x 10 17 cm -2 ) oxygen ions, respectively. Cross-sectional transmission electron microscopy (XTEM) was employed to examine the microstructures of the resulting materials. Experimental results indicate that the SOI/Si hybrid substrate fabricated using high-dose SIMOX is of inferior quality with very large surface height step and heavily damaged transitions between the SOI and bulk regions. However, the quality of the SOI/Si hybrid substrate is enhanced dramatically by reducing the implant dose. The defect density in transitions is reduced considerably. Moreover, the expected surface height difference does not exist and the surface is exceptionally flat. The possible mechanisms responsible for the improvements in quality are discussed

  19. Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi

    2012-01-01

    The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)

  20. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Science.gov (United States)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  1. Mapping the broadband polarization properties of linear 2D SOI photonic crystal waveguides

    DEFF Research Database (Denmark)

    Canning, John; Skivesen, Nina; Kristensen, Martin

    2007-01-01

    Both quasi-TE and TM polarisation spectra for a silicon- on-insulator (SOI) waveguide are recorded over (1100-1700) nm using a broadband supercontinuum source. By studying both the input and output polarisation eigenstates we observe narrowband resonant cross coupling near the lowest quasi-TE mode...... cut-off. We also observe relatively broadband mixing between the two eigenstates to generate a complete photonic bandgap. By careful analysis of the output polarisation state we report on an inherent non-reciprocity between quasi TE and TM fundamental mode cross coupling. The nature of polarisation...

  2. Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial...... Silicon-on-Insulator (SOI) process with a die area 2.31 mm2.  A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize...

  3. FinFET and UTBB for RF SOI communication systems

    Science.gov (United States)

    Raskin, Jean-Pierre

    2016-11-01

    Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

  4. A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

    International Nuclear Information System (INIS)

    Park, Jea-Gun; Kim, Seong-Je; Shin, Mi-Hee; Song, Seung-Hyun; Shim, Tae-Hun; Chung, Sung-Woong; Enomoto, Hirofumi

    2011-01-01

    A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 μA memory margin. This is a step toward achieving a terabit volatile memory cell.

  5. Ultrafast all-optical switching and error-free 10 Gbit/s wavelength conversion in hybrid InP-silicon on insulator nanocavities using surface quantum wells

    Energy Technology Data Exchange (ETDEWEB)

    Bazin, Alexandre; Monnier, Paul; Beaudoin, Grégoire; Sagnes, Isabelle; Raj, Rama [Laboratoire de Photonique et de Nanostructures (CNRS UPR20), Route de Nozay, Marcoussis 91460 (France); Lenglé, Kevin; Gay, Mathilde; Bramerie, Laurent [Université Européenne de Bretagne (UEB), 5 Boulevard Laënnec, 35000 Rennes (France); CNRS-Foton Laboratory (UMR 6082), Enssat, BP 80518, 22305 Lannion Cedex (France); Braive, Rémy; Raineri, Fabrice, E-mail: fabrice.raineri@lpn.cnrs.fr [Laboratoire de Photonique et de Nanostructures (CNRS UPR20), Route de Nozay, Marcoussis 91460 (France); Université Paris Diderot, Sorbonne Paris Cité, 75207 Paris Cedex 13 (France)

    2014-01-06

    Ultrafast switching with low energies is demonstrated using InP photonic crystal nanocavities embedding InGaAs surface quantum wells heterogeneously integrated to a silicon on insulator waveguide circuitry. Thanks to the engineered enhancement of surface non radiative recombination of carriers, switching time is obtained to be as fast as 10 ps. These hybrid nanostructures are shown to be capable of achieving systems level performance by demonstrating error free wavelength conversion at 10 Gbit/s with 6 mW switching powers.

  6. A 2D simulation study and characterization of a novel vertical SOI MOSFET with a smart source/body tie

    International Nuclear Information System (INIS)

    Lin, Jyi-Tsong; Lee, Tai-Yi; Lin, Kao-Cheng

    2008-01-01

    A novel vertical silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with a smart source/body contact, SSBVMOS, is presented here for the first time. 2D simulations reveal that the SSBVMOS reduces self-heating effects, with the lattice temperature reduced by 14% and the hole temperature reduced by 25%. The SSBVMOS also eliminates the floating body effect, something that other SOI vertical MOSFETs are unable to accomplish, regardless of the thickness of the thin film. The SSBVMOS is further found to have a better drain-induced barrier lowering and subthreshold swing than either a conventional vertical MOSFET or an SOI vertical MOSFET. Moreover, these results are achieved using typical pillar heights and buried oxide thicknesses. Should future technological advances allow for lower pillars or thinner buried oxides, the SSBVMOS performance would further increase

  7. A MEMS SOI-based piezoresistive fluid flow sensor

    Science.gov (United States)

    Tian, B.; Li, H. F.; Yang, H.; Song, D. L.; Bai, X. W.; Zhao, Y. L.

    2018-02-01

    In this paper, a SOI (silicon-on-insulator)-based piezoresistive fluid flow sensor is presented; the presented flow sensor mainly consists of a nylon sensing head, stainless steel cantilever beam, SOI sensor chip, printed circuit board, half-cylinder gasket, and stainless steel shell. The working principle of the sensor and some detailed contrastive analysis about the sensor structure were introduced since the nylon sensing head and stainless steel cantilever beam have distinct influence on the sensor performance; the structure of nylon sensing head and stainless steel cantilever beam is also discussed. The SOI sensor chip was fabricated using micro-electromechanical systems technologies, such as reactive ion etching and low pressure chemical vapor deposition. The designed fluid sensor was packaged and tested; a calibration installation system was purposely designed for the sensor experiment. The testing results indicated that the output voltage of the sensor is proportional to the square of the fluid flow velocity, which is coincident with the theoretical derivation. The tested sensitivity of the sensor is 3.91 × 10-4 V ms2/kg.

  8. Influence of edge effects on single event upset susceptibility of SOI SRAMs

    International Nuclear Information System (INIS)

    Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

    2015-01-01

    An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down

  9. Superconducting nanowire single-photon detectors (SNSPDs) on SOI for near-infrared range

    Energy Technology Data Exchange (ETDEWEB)

    Trojan, Philipp; Il' in, Konstantin; Henrich, Dagmar; Hofherr, Matthias; Doerner, Steffen; Siegel, Michael [Institut fuer Mikro- und Nanoelektronische Systeme (IMS), Karlsruher Institut fuer Technologie (KIT) (Germany); Semenov, Alexey [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Huebers, Heinz-Wilhelm [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Institut fuer Optik und Atomare Physik, Technische Universitaet Berlin (Germany)

    2013-07-01

    Superconducting nanowire single-photon detectors are promising devices for photon detectors with high count rates, low dark count rates and low dead times. At wavelengths beyond the visible range, the detection efficiency of today's SNSPDs drops significantly. Moreover, the low absorption in ultra-thin detector films is a limiting factor over the entire spectral range. Solving this problem requires approaches for an enhancement of the absorption range in feeding the light to the detector element. A possibility to obtain a better absorption is the use of multilayer substrate materials for photonic waveguide structures. We present results on development of superconducting nanowire single-photon detectors made from niobium nitride on silicon-on-insulator (SOI) multilayer substrates. Optical and superconducting properties of SNSPDs on SOI will be discussed and compared with the characteristics of detectors on common substrates.

  10. Room to high temperature measurements of flexible SOI FinFETs with sub-20-nm fins

    KAUST Repository

    Diab, Amer El Hajj

    2014-12-01

    We report the temperature dependence of the core electrical parameters and transport characteristics of a flexible version of fin field-effect transistor (FinFET) on silicon-on-insulator (SOI) with sub-20-nm wide fins and high-k/metal gate-stacks. For the first time, we characterize them from room to high temperature (150 °C) to show the impact of temperature variation on drain current, gate leakage current, and transconductance. Variation of extracted parameters, such as low-field mobility, subthreshold swing, threshold voltage, and ON-OFF current characteristics, is reported too. Direct comparison is made to a rigid version of the SOI FinFETs. The mobility degradation with temperature is mainly caused by phonon scattering mechanism. The overall excellent devices performance at high temperature after release is outlined proving the suitability of truly high-performance flexible inorganic electronics with such advanced architecture.

  11. New insights into fully-depleted SOI transistor response during total-dose irradiation

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Dodd, P.E.; Burns, J.A.; Keast, C.L.; Wyatt, P.W.

    1999-01-01

    In this paper, we present irradiation results on 2-fully depleted processes (HYSOI6, RKSOI) that show SOI (silicon on insulator) device response can be more complicated than originally suggested by others. The major difference between the 2 process versions is that the RKSOI process incorporates special techniques to minimize pre-irradiation parasitic leakage current from trench sidewalls. Transistors were irradiated at room temperature using 10 keV X-ray source. Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. It appears that the worst-case bias for HYPOI6 process is the bias that causes the largest increase in sidewall leakage. The RKSOI process shows a different response during irradiation, the transition response appears to be dominated by charge trapping in the buried oxide. These results have implications for hardness assurance testing. (A.C.)

  12. Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

    Science.gov (United States)

    Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

    2001-12-01

    We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

  13. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    Science.gov (United States)

    Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

    2014-06-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

  14. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  15. Realization of an ultra-compact polarization beam splitter using asymmetric MMI based on silicon nitride / silicon-on-insulator platform.

    Science.gov (United States)

    Sun, Xiao; Aitchison, J Stewart; Mojahedi, Mo

    2017-04-03

    We have experimentally demonstrated a compact polarization beam splitter (PBS) based on the silicon nitride/silicon-on-insulator platform using the recently proposed augmented-low-index-guiding (ALIG) waveguide structure. The two orthogonal polarizations are split in an asymmetric multimode interference (MMI) section, which was 1.6 μm wide and 4.8 μm long. The device works well over the entire C-band wavelength range and has a measured low insertion loss of less than 1 dB. The polarization extinction ratio at the Bar Port is approximately 17 dB and at the Cross Port is approximately 25 dB. The design of the device is robust and has a good fabrication tolerance.

  16. Analysis and design of tunable wideband microwave photonics phase shifter based on Fabry-Perot cavity and Bragg mirrors in silicon-on-insulator waveguide.

    Science.gov (United States)

    Qu, Pengfei; Zhou, Jingran; Chen, Weiyou; Li, Fumin; Li, Haibin; Liu, Caixia; Ruan, Shengping; Dong, Wei

    2010-04-20

    We designed a microwave (MW) photonics phase shifter, consisting of a Fabry-Perot filter, a phase modulation region (PMR), and distributed Bragg reflectors, in a silicon-on-insulator rib waveguide. The thermo-optics effect was employed to tune the PMR. It was theoretically demonstrated that the linear MW phase shift of 0-2pi could be achieved by a refractive index variation of 0-9.68x10(-3) in an ultrawideband (about 38?GHz-1.9?THz), and the corresponding tuning resolution was about 6.92 degrees / degrees C. The device had a very compact size. It could be easily integrated in silicon optoelectronic chips and expected to be widely used in the high-frequency MW photonics field.

  17. SEMICONDUCTOR DEVICES: Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

    Science.gov (United States)

    Jin, Li; Hongxia, Liu; Bin, Li; Lei, Cao; Bo, Yuan

    2010-08-01

    For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a “rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.

  18. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

    Science.gov (United States)

    Pavanello, Marcelo Antonio; de Souza, Michelly; Ribeiro, Thales Augusto; Martino, João Antonio; Flandre, Denis

    2016-11-01

    This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

  19. Characteristics of MOSFETs fabricated in silicon-on-insulator material formed by high-dose oxygen ion implantation

    International Nuclear Information System (INIS)

    Lam, H.W.; Pinizzotto, R.F.; Yuan, H.T.; Bellavance, D.W.

    1981-01-01

    By implanting a dose of 6 x 10 17 cm -2 of 32 O 2 + at 300 keV into a silicon wafer, a buried oxide layer is formed. Crystallinity of the silicon layer above the buried oxide layer is maintained by applying a high (>200 0 C) substrate temperature during the ion implantation process. A two-step anneal cycle is found to be adequate to form the insulating buried oxide layer and to repair the implantation damage in the silicon layer on top of the buried oxide. A surface electron mobility as high as 710 cm 2 /Vs has been measured in n-channel MOSFETs fabricated in a 0.5 μm-thick epitaxial layer grown on the buried oxide wafer. A minimum subthreshold current of about 10 pA per micron of channel width at Vsub(DS)=2 V has been measured. (author)

  20. Output-Conductance Transition-Free Method for Improving Radio-Frequency Linearity of SOI MOSFET Circuits

    Directory of Open Access Journals (Sweden)

    A. Daghighi

    2013-09-01

    Full Text Available In this article, a novel concept is introduced to improve the radio frequency (RF linearity of partially-depleted (PD silicon-on-insulator (SOI MOSFET circuits. The transition due to the non-zero body resistance (RBody in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown. 3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz low noise amplifier (LNA is analyzed. Mixed mode device-circuit analysis is carried out to simultaneously solve device transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third harmonic distortion (HD3 and total harmonic distortion (THD are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.

  1. Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

    Science.gov (United States)

    Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

    2015-04-01

    A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

  2. A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

    Science.gov (United States)

    Priya, Anjali; Mishra, Ram Awadh

    2016-04-01

    In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

  3. Performance of the INTPIX6 SOI pixel detector

    International Nuclear Information System (INIS)

    Arai, Y.; Miyoshi, T.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Turala, M.; Kucewicz, W.

    2017-01-01

    Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ  m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241 Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e − . The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e − . The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

  4. Correlation between Co-60 and X-ray exposures on radiation-induced charge buildup in silicon-on-insulator buried oxides

    International Nuclear Information System (INIS)

    Schwank, James R.; Shaneyfelt, Marty R.; Loemker, Rhonda Ann; Draper, Bruce L.; Dodd, Paul E.; Witczak, StevenN C.; Riewe, Leonard Charles; Ferlet-Cavrois, V.; Paillet, P.; Leray, J.-L.; Fleetwood, D.M.

    2000-01-01

    Large differences in charge buildup in SOI buried oxides can result between x-ray and Co-60 irradiations. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored

  5. A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

    Science.gov (United States)

    Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

    2018-04-01

    We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

  6. Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

    Science.gov (United States)

    Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

    2014-11-17

    A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a silicon photonics technology.

  7. Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Chen Jing; Luo Jiexin; Wu Qingqing; Chai Zhan; Huang Xiaolu; Wei Xing; Wang Xi

    2012-01-01

    Silicon-on-insulate (SOI) MOSFETs offer benefits over bulk competitors for fully isolation and smaller junction capacitance. The performance of partially depleted (PD) SOI MOSFETs, though, is not good enough. Since the body is floating, the extra holes (for nMOSFETs) in this region accumulate, causing body potential arise, which of course degrades the performance of the device. How to suppress the floating-body effect becomes critical. There are mainly two ways for the goal. One is to employ body-contact structures, and the other SiGe source/drain structures. However, the former consumes extra area, not welcomed in the state-of-the-art chips design. The latter is not compatible with the traditional CMOS technology. Finding a structure both saving area and compatible technology is the most urgent for PD SOI MOSFETs. Recently, we have developed a new structure with extra heavy boron implantation in the source region for PD SOI nMOSFETs. It consumes no extra area and is also compatible with CMOS technology. The device is found to be free of kink effect in simulation, which implies the floating-body effect is greatly suppressed. In addition, the mechanisms of the kink-free, as well as the impact of different implanting conditions are interpreted.

  8. An analysis of radiation effects on electronics and soi-mos devices as an alternative

    International Nuclear Information System (INIS)

    Ikraiam, F. A.

    2013-01-01

    The effects of radiation on semiconductors and electronic components are analyzed. The performance of such circuitry depends upon the reliability of electronic devices where electronic components will be unavoidably exposed to radiation. This exposure can be detrimental or even fatal to the expected function of the devices. Single event effects (SEE), in particular, which lead to sudden device or system failure and total dose effects can reduce the lifetime of electronic devices in such systems are discussed. Silicon-on-insulator (SOI) technology is introduced as an alternative for radiation-hardened devices. I-V Characteristics Curves for SOI-MOS devices subjected to a different total radiation doses are illustrated. In addition, properties of some semiconductor materials such as diamond, diamond-like carbon films, SiC, GaP, and AlGaN/GaN are compared with those of SOI devices. The recognition of the potential usefulness of SOI-MOS semiconductor materials for harsh environments is discussed. A summary of radiation effects, impacts and mitigation techniques is also presented. (authors)

  9. Photonic crystal ring resonator-based four-channel dense wavelength division multiplexing demultiplexer on silicon on insulator platform: design and analysis

    Science.gov (United States)

    Sreenivasulu, Tupakula; Bhowmick, Kaustav; Samad, Shafeek A.; Yadunath, Thamerassery Illam R.; Badrinarayana, Tarimala; Hegde, Gopalkrishna; Srinivas, Talabattula

    2018-04-01

    A micro/nanofabrication feasible compact photonic crystal (PC) ring-resonator-based channel drop filter has been designed and analyzed for operation in C and L bands of communication window. The four-channel demultiplexer consists of ring resonators of holes in two-dimensional PC slab. The proposed assembly design of dense wavelength division multiplexing setup is shown to achieve optimal quality factor, without altering the lattice parameters or resonator size or inclusion of scattering holes. Transmission characteristics are analyzed using the three-dimensional finite-difference time-domain simulation approach. The radiation loss of the ring resonator was minimized by forced cancelation of radiation fields by fine-tuning the air holes inside the ring resonator. An average cross talk of -34 dB has been achieved between the adjacent channels maintaining an average quality factor of 5000. Demultiplexing is achieved by engineering only the air holes inside the ring, which makes it a simple and tolerant design from the fabrication perspective. Also, the device footprint of 500 μm2 on silicon on insulator platform makes it easy to fabricate the device using e-beam lithography technique.

  10. Note: A silicon-on-insulator microelectromechanical systems probe scanner for on-chip atomic force microscopy

    Energy Technology Data Exchange (ETDEWEB)

    Fowler, Anthony G.; Maroufi, Mohammad; Moheimani, S. O. Reza, E-mail: Reza.Moheimani@newcastle.edu.au [School of Electrical Engineering and Computer Science, University of Newcastle, Callaghan, NSW 2308 (Australia)

    2015-04-15

    A new microelectromechanical systems-based 2-degree-of-freedom (DoF) scanner with an integrated cantilever for on-chip atomic force microscopy (AFM) is presented. The silicon cantilever features a layer of piezoelectric material to facilitate its use for tapping mode AFM and enable simultaneous deflection sensing. Electrostatic actuators and electrothermal sensors are used to accurately position the cantilever within the x-y plane. Experimental testing shows that the cantilever is able to be scanned over a 10 μm × 10 μm window and that the cantilever achieves a peak-to-peak deflection greater than 400 nm when excited at its resonance frequency of approximately 62 kHz.

  11. Compact polarization beam splitter for silicon photonic integrated circuits with a 340-nm-thick silicon core layer.

    Science.gov (United States)

    Li, Chenlei; Dai, Daoxin

    2017-11-01

    A polarization beam splitter (PBS) is proposed and realized for silicon photonic integrated circuits with a 340-nm-thick silicon core layer by introducing an asymmetric directional coupler (ADC), which consists of a silicon-on-insulator (SOI) nanowire and a subwavelength grating (SWG) waveguide. The SWG is introduced to provide an optical waveguide which has much higher birefringence than a regular 340-nm-thick SOI nanowire, so that it is possible to make the phase-matching condition satisfied for TE polarization only in the present design when the waveguide dimensions are optimized. Meanwhile, there is a significant phase mismatching for TM polarization automatically. In this way, the present ADC enables strong polarization selectivity to realize a PBS that separates TE and TM polarizations to the cross and through ports, respectively. The realized PBS has a length of ∼2  μm for the coupling region. For the fabricated PBS, the extinction ratio (ER) is 15-30 dB and the excess loss is 0.2-2.6 dB for TE polarization while the ER is 20-27 dB and the excess loss is 0.3-2.8 dB for TM polarization when operating in the wavelength range of 1520-1580 nm.

  12. Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

    Science.gov (United States)

    Katz, Oded; Malka, Dror

    2017-07-01

    In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530-1565 nm) with excess loss better than 0.23 dB.

  13. Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

    International Nuclear Information System (INIS)

    Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

    2005-01-01

    This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

  14. The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

    International Nuclear Information System (INIS)

    Mohapatra, S K; Pradhan, K P; Sahu, P K; Pati, G S; Kumar, M R

    2014-01-01

    In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™. (paper)

  15. The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

    Science.gov (United States)

    Mohapatra, S. K.; Pradhan, K. P.; Sahu, P. K.; Pati, G. S.; Kumar, M. R.

    2014-12-01

    In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.

  16. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    CERN Multimedia

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  17. Analyses of the radiation-caused characteristics change in SOI MOSFETs using field shield isolation

    International Nuclear Information System (INIS)

    Hirano, Yuuichi; Maeda, Shigeru; Fernandez, Warren; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Maegawa, Shigeto; Nishimura, Tadashi

    1999-01-01

    Reliability against radiation ia an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long regime channel. In transistors with a channel length of 0.18μm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0μm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment. (author)

  18. Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

    Energy Technology Data Exchange (ETDEWEB)

    Naumova, O. V., E-mail: naumova@isp.nsc.ru; Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

    2015-10-15

    The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

  19. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

    International Nuclear Information System (INIS)

    Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

    2011-01-01

    An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

  20. A low on-resistance SOI LDMOS using a trench gate and a recessed drain

    International Nuclear Information System (INIS)

    Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji

    2012-01-01

    An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)

  1. Si-nanowire-based multistage delayed Mach-Zehnder interferometer optical MUX/DeMUX fabricated by an ArF-immersion lithography process on a 300 mm SOI wafer.

    Science.gov (United States)

    Jeong, Seok-Hwan; Shimura, Daisuke; Simoyama, Takasi; Horikawa, Tsuyoshi; Tanaka, Yu; Morito, Ken

    2014-07-01

    We report good phase controllability and high production yield in Si-nanowire-based multistage delayed Mach-Zehnder interferometer-type optical multiplexers/demultiplexers (MUX/DeMUX) fabricated by an ArF-immersion lithography process on a 300 mm silicon-on-insulator (SOI) wafer. Three kinds of devices fabricated in this work exhibit clear 1×4 Ch wavelength filtering operations for various optical frequency spacing. These results are promising for their applications in high-density wavelength division multiplexing-based optical interconnects.

  2. Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  3. Investigation of AWG demultiplexer based SOI for CWDM application

    Directory of Open Access Journals (Sweden)

    Juhari Nurjuliana

    2017-01-01

    Full Text Available 9-channel Arrayed Waveguide Grating (AWG demultiplexer for conventional and tapered structure were simulated using beam propagation method (BPM with channel spacing of 20 nm. The AWG demultiplexer was design using high refractive index (n~3.47 material namely silicon-on-insulator (SOI with rib waveguide structure. The characteristics of insertion loss, adjacent crosstalk and output spectrum response at central wavelength of 1.55 μm for both designs were compared and analyzed. The conventional AWG produced a minimum insertion loss of 6.64 dB whereas the tapered AWG design reduced the insertion loss by 2.66 dB. The lowest adjacent crosstalk value of -16.96 dB was obtained in the conventional AWG design and this was much smaller compared to the tapered AWG design where the lowest crosstalk value is -17.23 dB. Hence, a tapered AWG design significantly reduces the insertion loss but has a slightly higher adjacent crosstalk compared to the conventional AWG design. On the other hand, the output spectrum responses that are obtained from both designs were close to the Coarse Wavelength Division Multiplexing (CWDM wavelength grid.

  4. Biosensor properties of SOI nanowire transistors with a PEALD Al{sub 2}O{sub 3} dielectric protective layer

    Energy Technology Data Exchange (ETDEWEB)

    Popov, V. P., E-mail: popov@isp.nsc.ru; Ilnitskii, M. A.; Zhanaev, E. D. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation); Myakon’kich, A. V.; Rudenko, K. V. [Russian Academy of Sciences, Physical Technological Institute (Russian Federation); Glukhov, A. V. [Novosibirsk Semiconductor Device Plant and Design Bureau (Russian Federation)

    2016-05-15

    The properties of protective dielectric layers of aluminum oxide Al{sub 2}O{sub 3} applied to prefabricated silicon-nanowire transistor biochips by the plasma enhanced atomic layer deposition (PEALD) method before being housed are studied depending on the deposition and annealing modes. Coating the natural silicon oxide with a nanometer Al{sub 2}O{sub 3} layer insignificantly decreases the femtomole sensitivity of biosensors, but provides their stability in bioliquids. In deionized water, transistors with annealed aluminum oxide are closed due to the trapping of negative charges of <(1–10) × 10{sup 11} cm{sup −2} at surface states. The application of a positive potential to the substrate (V{sub sub} > 25 V) makes it possible to eliminate the negative charge and to perform multiple measurements in liquid at least for half a year.

  5. Flexible FETs using ultrathin Si microwires embedded in solution processed dielectric and metal layers

    Science.gov (United States)

    Khan, S.; Yogeswaran, N.; Taube, W.; Lorenzelli, L.; Dahiya, R.

    2015-12-01

    This work presents a novel manufacturing route for obtaining high performance bendable field effect transistors (FET) by embedding silicon (Si) microwires (2.5 μm thick) in layers of solution-processed dielectric and metallic layers. The objective of this study is to explore heterogeneous integration of Si with polymers and to exploit the benefits of both microelectronics and printing technologies. Arrays of Si microwires are developed on silicon on insulator (SOI) wafers and transfer printed to polyimide (PI) substrate through a polydimethylsiloxane (PDMS) carrier stamp. Following the transfer printing of Si microwires, two different processing steps were developed to obtain top gate top contact and back gate top contact FETs. Electrical characterizations indicate devices having mobility as high as 117.5 cm2 V-1 s-1. The fabricated devices were also modeled using SILVACO Atlas. Simulation results show a trend in the electrical response similar to that of experimental results. In addition, a cyclic test was performed to demonstrate the reliability and mechanical robustness of the Si μ-wires on flexible substrates.

  6. Flexible FETs using ultrathin Si microwires embedded in solution processed dielectric and metal layers

    International Nuclear Information System (INIS)

    Khan, S; Yogeswaran, N; Lorenzelli, L; Taube, W; Dahiya, R

    2015-01-01

    This work presents a novel manufacturing route for obtaining high performance bendable field effect transistors (FET) by embedding silicon (Si) microwires (2.5 μm thick) in layers of solution-processed dielectric and metallic layers. The objective of this study is to explore heterogeneous integration of Si with polymers and to exploit the benefits of both microelectronics and printing technologies. Arrays of Si microwires are developed on silicon on insulator (SOI) wafers and transfer printed to polyimide (PI) substrate through a polydimethylsiloxane (PDMS) carrier stamp. Following the transfer printing of Si microwires, two different processing steps were developed to obtain top gate top contact and back gate top contact FETs. Electrical characterizations indicate devices having mobility as high as 117.5 cm 2 V −1 s −1 . The fabricated devices were also modeled using SILVACO Atlas. Simulation results show a trend in the electrical response similar to that of experimental results. In addition, a cyclic test was performed to demonstrate the reliability and mechanical robustness of the Si μ-wires on flexible substrates. (paper)

  7. Development of an X-ray imaging system with SOI pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Nishimura, Ryutaro, E-mail: ryunishi@post.kek.jp [School of High Energy Accelerator Science, SOKENDAI (The Graduate University for Advanced Studies), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Arai, Yasuo; Miyoshi, Toshinobu [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK-IPNS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Hirano, Keiichi; Kishimoto, Shunji; Hashimoto, Ryo [Institute of Materials Structure Science, High Energy Accelerator Research Organization (KEK-IMSS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan)

    2016-09-21

    An X-ray imaging system employing pixel sensors in silicon-on-insulator technology is currently under development. The system consists of an SOI pixel detector (INTPIX4) and a DAQ system based on a multi-purpose readout board (SEABAS2). To correct a bottleneck in the total throughput of the DAQ of the first prototype, parallel processing of the data taking and storing processes and a FIFO buffer were implemented for the new DAQ release. Due to these upgrades, the DAQ throughput was improved from 6 Hz (41 Mbps) to 90 Hz (613 Mbps). The first X-ray imaging system with the new DAQ software release was tested using 33.3 keV and 9.5 keV mono X-rays for three-dimensional computerized tomography. The results of these tests are presented. - Highlights: • The X-ray imaging system employing the SOI pixel sensor is currently under development. • The DAQ of the first prototype has the bottleneck in the total throughput. • The new DAQ release solve the bottleneck by parallel processing and FIFO buffer. • The new DAQ release was tested using 33.3 keV and 9.5 keV mono X-rays.

  8. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    Science.gov (United States)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  9. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Science.gov (United States)

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  10. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  11. Reduced nonlinearities in 100-nm high SOI waveguides

    Science.gov (United States)

    Lacava, C.; Marchetti, R.; Vitali, V.; Cristiani, I.; Giuliani, G.; Fournier, M.; Bernabe, S.; Minzioni, P.

    2016-03-01

    Here we show the results of an experimental analysis dedicated to investigate the impact of optical non linear effects, such as two-photon absorption (TPA), free-carrier absorption (FCA) and free-carrier dispersion (FCD), on the performance of integrated micro-resonator based filters for application in WDM telecommunication systems. The filters were fabricated using SOI (Silicon-on-Insulator) technology by CEA-Leti, in the frame of the FP7 Fabulous Project, which aims to develop low-cost and high-performance integrated optical devices to be used in new generation passive optical- networks (NG-PON2). Different designs were tested, including both ring-based structures and racetrack-based structures, with single-, double- or triple- resonator configuration, and using different waveguide cross-sections (from 500 x 200 nm to 825 x 100 nm). Measurements were carried out using an external cavity tunable laser source operating in the extended telecom bandwidth, using both continuous wave signals and 10 Gbit/s modulated signals. Results show that the use 100-nm high waveguide allows reducing the impact of non-linear losses, with respect to the standard waveguides, thus increasing by more than 3 dB the maximum amount of optical power that can be injected into the devices before causing significant non-linear effects. Measurements with OOK-modulated signals at 10 Gbit/s showed that TPA and FCA don't affect the back-to-back BER of the signal, even when long pseudo-random-bit-sequences (PRBS) are used, as the FCD-induced filter-detuning increases filter losses but "prevents" excessive signal degradation.

  12. Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

    Science.gov (United States)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2017-08-01

    Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

  13. Nanoscale contacts to organic molecules based on layered semiconductor substrates

    Energy Technology Data Exchange (ETDEWEB)

    Strobel, Sebastian

    2009-06-15

    This work reports on the integration of organic molecules as nanoelectronic device units on semiconductor substrates. Two novel preparation methods for sub-10-nm separated metal electrodes are presented using current microelectronics process technology. The first method utilises AlGaAs/GaAs heterostructures grown by molecular beam epitaxy (MBE) as mold to create planar metal electrodes employing a newly developed, high resolution nanotransfer printing (nTP) process. The second method uses commercially available Silicon-on-Insulator (SOI) substrates as base material for the fabrication of nanogap electrode devices. This sandwich-like material stack consists of a silicon substrate, a thin silicon oxide layer, and a capping silicon layer on top. Electronic transport measurements verified their excellent electrical properties at liquid helium temperatures. Specifically tailored nanogap devices featured an electrode insulation in the GW range even up to room temperature as well as within aqueous electrolyte solution. Finally, the well defined layer architecture facilitated the fabrication of electrodes with gap separations below-10-nm to be directly bridged by molecules. Approximately 12-nm-long conjugated molecules with extended -electron system were assembled onto the devices from solution. A large conductance gap was observed with a steep increase in current at a bias voltage of V{sub T}{approx}{+-}1.5 V. Theoretical calculations based on density functional theory and non-equilibrium Green's function formalism confirmed the measured non-linear IV-characteristics qualitatively and lead to the conclusion that the conductance gap mainly originates from the oxygen containing linker. Temperature dependent investigations of the conductance indicated a hopping charge transport mechanism through the central part of the molecule for bias voltages near but below V{sub T}. (orig.)

  14. Optimal Design of an Ultrasmall SOI-Based 1 × 8 Flat-Top AWG by Using an MMI

    Directory of Open Access Journals (Sweden)

    Hongqiang Li

    2013-01-01

    Full Text Available Four methods based on a multimode interference (MMI structure are optimally designed to flatten the spectral response of silicon-on-insulator- (SOI- based arrayed-waveguide grating (AWG applied in a demodulation integration microsystem. In the design for each method, SOI is selected as the material, the beam propagation method is used, and the performances (including the 3 dB passband width, the crosstalk, and the insertion loss of the flat-top AWG are studied. Moreover, the output spectrum responses of AWGs with or without a flattened structure are compared. The results show that low insertion loss, crosstalk, and a flat and efficient spectral response are simultaneously achieved for each kind of structure. By comparing the four designs, the design that combines a tapered MMI with tapered input/output waveguides, which has not been previously reported, was shown to yield better results than others. The optimized design reduced crosstalk to approximately −21.9 dB and had an insertion loss of −4.36 dB and a 3 dB passband width, that is, approximately 65% of the channel spacing.

  15. Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

    Science.gov (United States)

    Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

    2018-02-01

    A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

  16. Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

    Energy Technology Data Exchange (ETDEWEB)

    Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-06-20

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  17. Buried oxide layer in silicon

    Science.gov (United States)

    Sadana, Devendra Kumar; Holland, Orin Wayne

    2001-01-01

    A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

  18. Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

    Science.gov (United States)

    Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

    2017-07-01

    Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

  19. Heterojunction fully depleted SOI-TFET with oxide/source overlap

    Science.gov (United States)

    Chander, Sweta; Bhowmick, B.; Baishya, S.

    2015-10-01

    In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

  20. Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

    Science.gov (United States)

    Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

    2018-05-01

    Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

  1. Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

    Science.gov (United States)

    Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

    2016-09-01

    In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

  2. Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

    Science.gov (United States)

    Takulapalli, Bharath R

    2010-02-23

    Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

  3. Characterization of pixel sensor designed in 180 nm SOI CMOS technology

    Science.gov (United States)

    Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

    2018-01-01

    A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

  4. SOI Fully complementary BI-JFET-MOS technology for analog-digital applications with vertical BJT's

    International Nuclear Information System (INIS)

    Delevoye, E.; Blanc, J.P.; Bonaime, J.; Pontcharra, J. de; Gautier, J.; Martin, F.; Truche, R.

    1993-01-01

    A silicon-on-insulator, fully complementary, Bi-JFET-MOS technology has been developed for realizing multi-megarad hardened mixed analog-digital circuits. The six different active components plus resistors and capacitors have been successfully integrated in a 25-mask process using SIMOX substrate and 1 μm thick epitaxial layer. Different constraints such as device compatibility, complexity not higher than BiCMOS technology and breakdown voltages suitable for analog applications have been considered. Several process splits have been realized and all the characteristics presented here have been measured on the same split. P + gate is used for PMOS transistor to get N and PMOST symmetrical characteristics. Both NPN and PNP vertical bipolar transistors with poly-emitters show f T > 5 GHz. 2-separated gate JFET's need no additional mask. (authors). 9 figs., 1 tab

  5. Fabrication of core-shell nanostructures via silicon on insulator dewetting and germanium condensation: towards a strain tuning method for SiGe-based heterostructures in a three-dimensional geometry.

    Science.gov (United States)

    Naffouti, Meher; David, Thomas; Benkouider, Abdelmalek; Favre, Luc; Cabie, Martiane; Ronda, Antoine; Berbezier, Isabelle; Abbarchi, Marco

    2016-07-29

    We report on a novel method for the implementation of core-shell SiGe-based nanocrystals combining silicon on insulator dewetting in a molecular beam epitaxy reactor with an ex situ Ge condensation process. With an in situ two-step process (annealing and Ge deposition) we produce two families of islands on the same sample: Si-rich, formed during the first step and, all around them, Ge-rich formed after Ge deposition. By increasing the amount of Ge deposited on the annealed samples from 0 to 18 monolayers, the islands' shape in the Si-rich zones can be tuned from elongated and flat to more symmetric and with a larger vertical aspect ratio. At the same time, the spatial extension of the Ge-rich zones is progressively increased as well as the Ge content in the islands. Further processing by ex situ rapid thermal oxidation results in the formation of a core-shell composition profile in both Si and Ge-rich zones with atomically sharp heterointerfaces. The Ge condensation induces a Ge enrichment of the islands' shell of up to 50% while keeping a pure Si core in the Si-rich zones and a ∼25% SiGe alloy in the Ge-rich ones. The large lattice mismatch between core and shell, the absence of dislocations and the islands' monocrystalline nature render this novel class of nanostructures a promising device platform for strain-based band-gap engineering. Finally, this method can be used for the implementation of ultralarge scale meta-surfaces with dielectric Mie resonators for light manipulation at the nanoscale.

  6. Improvement of SOI microdosimeter performance using pulse shape discrimination techniques

    International Nuclear Information System (INIS)

    Cornelius, I.

    2002-01-01

    Full text: Microdosimetry is used to study the radiobiological properties of densely ionising radiations encountered in hadron therapy and space environments by measuring energy deposition in microscopic volumes. The creation of a solid state microdosimeter to replace the traditional tissue equivalent proportional counter is a topic of ongoing research. The Centre for Medical Radiation Physics has been investigating a technique using microscopic arrays of reverse biased pn junctions to measure the linear energy transfer of ions. A prototype silicon-on-insulator (SOI) microdosimeter was developed and measurements were conducted at boron neutron capture therapy, proton therapy, and fast neutron therapy facilities. Previous studies have shown the current microdosimeter possesses a poorly defined sensitive volume, a consequence of charge collection events being measured for ion strikes outside the pn junction via the diffusion of charge carriers. As a result, the amount of charge collected by the microdosimeter following an ion strike has a strong dependence on the location of the strike on the device and the angle of incidence of the ion. The aim of this work was to investigate the use of pulse shape discrimination (PSD) techniques to preclude the acquisition of events resulting from ion strikes outside the depletion region of the pn junction. Experiments were carried out using the Heavy Ion Microprobe (HIMP) at the Australian Nuclear Science and Technology Organisation, Lucas Heights, Australia. The HIMP was used to measure the charge collection time as a function of ion strike location on the microdosimeter array. As expected, the charge collection time was seen to increase monotonically as the distance of the ion strike from the junction increased. The charge collection time corresponding to ion strikes within the junction was determined. Through use of suitable electronics it was possible to gate the charge collection signal based on simultaneous measurements of

  7. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

    International Nuclear Information System (INIS)

    Qiao Fengying; Pan Liyang; Wu Dong; Liu Lifang; Xu Jun

    2014-01-01

    In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode. (semiconductor devices)

  8. SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Almad

    2009-01-01

    Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80

  9. Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

  10. Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

    International Nuclear Information System (INIS)

    Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Moro, F. de; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

    2008-01-01

    Several successful development programs have been conducted on infra-red bolometer arrays at the 'Commissariat a l'Energie Atomique' (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8x8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32x32 pixels in size

  11. Method of forming buried oxide layers in silicon

    Science.gov (United States)

    Sadana, Devendra Kumar; Holland, Orin Wayne

    2000-01-01

    A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

  12. The optimal design of 15 nm gate-length junctionless SOI FinFETs for reducing leakage current

    International Nuclear Information System (INIS)

    Liu, Xi; Wu, Meile; Jin, Xiaoshi; Chuai, Rongyan; Lee, Jung-Hee; Lee, Jong-Ho

    2013-01-01

    Junctionless (JL) transistors need to be heavily doped to have large drain current in the ON-state, which engenders the effect of band-to-band tunneling (BTBT) in the OFF-state simultaneously. It causes an obvious increase of the leakage current in the OFF-state. This paper presents an effective method of reducing the leakage current by changing the geometrical shape and dimension of the oxide layer under the edge of the gate. The optimal design of 15 nm gate-length JL silicon-on-insulator FinFETs with the triple-gate structure is performed for reducing the effect of BTBT through simulation and analysis by this means. (paper)

  13. Selective SiO2 etching in three dimensional structures using parylene-C as mask

    NARCIS (Netherlands)

    Veltkamp, Henk-Willem; Zhao, Yiyuan; de Boer, Meint J.; Wiegerink, Remco J.; Lötters, Joost Conrad

    2017-01-01

    This abstract describes an application of an easy and straightforward method for selective SiO2 etching in three dimensional structures, which is developed by our group. The application in this abstract is the protection of the buried-oxide (BOX) layer of a silicon-on-insulator (SOI) wafer against

  14. Electrostatically Tunable Nanomechanical Shallow Arches

    KAUST Repository

    Kazmi, Syed N. R.; Hajjaj, Amal Z.; Da Costa, Pedro M. F. J.; Younis, Mohammad I.

    2017-01-01

    -beam lithography and surface nanomachining of a highly conductive device layer on a silicon-on-insulator (SOI) wafer. The experimental results show good agreement with the analytical results with a maximum tunability of 108.14% for 180 nm thick arch with a

  15. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    Science.gov (United States)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  16. Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

    Science.gov (United States)

    Wu, Bin

    Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

  17. High figure-of-merit SOI power LDMOS for power integrated circuits

    Directory of Open Access Journals (Sweden)

    Yashvir Singh

    2015-06-01

    Full Text Available The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device.

  18. High performance multi-finger MOSFET on SOI for RF amplifiers

    Science.gov (United States)

    Adhikari, M. Singh; Singh, Y.

    2017-10-01

    In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

  19. Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

    Science.gov (United States)

    Nasr Esfahani, Mohammad; Kilinc, Yasin; Çagatay Karakan, M.; Orhan, Ezgi; Hanay, M. Selim; Leblebici, Yusuf; Erdem Alaca, B.

    2018-04-01

    The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 μ m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3-8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

  20. Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric

    International Nuclear Information System (INIS)

    Barchuk, I.P.; Kilchitskaya, V.I.; Lysenko, V.S.

    1997-01-01

    In this work SOI structures with buried SiO 2 -Si 3 N 4 -SiO 2 layers have been fabricated by the ZMR-technique with the aim of improving the total dose radiation hardness of the buried dielectric layer. To optimize the fabrication process, buried layers were investigated by secondary ion mass spectrometry before and after the ZMR process, and the obtained results were compared with electrical measurements. It is shown that optimization of the preparation processes of the initial buried dielectric layers provides ZMR SOI structures with multilayer buried isolation, which are of high quality for both Si film interfaces. Particular attention is paid to the investigation of radiation-induced charge trapping in buried insulators. Buried isolation structures with a nitride layer exhibit significant reduction of radiation-induced positive charge as compared to classical buried SiO 2 layers produced by either the ZMR or the SIMOX technique

  1. Extreme group index measured and calculated in 2D SOI-based photonic crystal waveguides

    DEFF Research Database (Denmark)

    Lavrinenko, Andrei; Jacobsen, Rune Shim; Fage-Pedersen, Jacob

    2005-01-01

    lattice of air-holes in the 216-nm thick silicon layer in an SOI material. Experimental transmission spectra show a mode cut-off around 1562.5 nm for the fundamental photonic bandgap mode. In order to measure and model the group index of modes in the PCW, a time-of-flight (ToF) method is applied....

  2. BUSFET -- A radiation-hardened SOI transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

  3. Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology

    NARCIS (Netherlands)

    Agarwal, V.; Dutta, S; Annema, AJ; Hueting, RJE; Steeneken, P.G.; Nauta, B

    2017-01-01

    This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant

  4. A graphene spin diode based on Rashba SOI

    International Nuclear Information System (INIS)

    Mohammadpour, Hakimeh

    2015-01-01

    In this paper a graphene-based two-terminal electronic device is modeled for application in spintronics. It is based on a gapped armchair graphene nanoribbon (GNR). The electron transport is considered through a scattering or channel region which is sandwiched between two lateral semi-infinite ferromagnetic leads. The two ferromagnetic leads, being half-metallic, are supposed to be in either parallel or anti-parallel magnetization. Meanwhile, the central channel region is a normal layer under the influence of the Rashba SOI, induced e.g., by the substrate. The device operation is based on modulating the (spin-) current by tuning the strength of the RSOI. The resultant current, being spin-polarized, is controlled by the RSOI in mutual interplay with the channel length. Inverting alternating bias voltage to a fully rectified spin-current is the main achievement of this paper. - Highlights: • Graphene-based electronic device is modeled with ferromagnetic leads. • The device operation is based on modulating the (spin-) current by Rashba SOI. • Inverting alternating bias voltage to rectified spin-current is the main achievement

  5. Investigation of charge-collection efficiency of Kyoto's X-ray astronomical SOI pixel sensors, XRPIX

    Energy Technology Data Exchange (ETDEWEB)

    Matsumura, Hideaki, E-mail: matumura@cr.scphys.kyoto-u.ac.jp [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa Oiwake-cho, Sakyo-ku, Kyoto 606-8502 (Japan); Tsuru, Takeshi Go; Tanaka, Takaaki; Nakashima, Shinya; Ryu, Syukyo G. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa Oiwake-cho, Sakyo-ku, Kyoto 606-8502 (Japan); Takeda, Ayaki [Department of Particle and Nuclear Physics, Graduate School of High Energy Accelerator Science, The Graduate University for Advanced Studies (SOKENDAI), High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Arai, Yasuo; Miyoshi, Toshinobu [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK), Tsukuba 305-0801 (Japan)

    2014-11-21

    We are developing a monolithic active pixel sensor referred to as XRPIX for X-ray astronomy on the basis of silicon-on-insulator CMOS technology. A crucial issue in our recent development is the impact of incomplete charge collection on the spectroscopic performance. In this paper, we report the spectral responses of several devices having different intra-pixel structures or produced from different wafers. We found that an emission line spectrum exhibits large low-energy tails when the size of the buried p-well, which acts as the charge-collection node, is small. Moreover, in charge sharing events, the peak channels of the emission lines shift toward channels lower than those without charge sharing. This peak shift is more pronounced as the distance between the pixel center and the position of incident photon increases. This suggests that the charge-collection efficiency is degraded at the pixel boundary. We also found that the charge-collection efficiency depends on the strength of the electric field at the interface of the depletion and insulator layers.

  6. A new SOI high-voltage device with a step-thickness drift region and its analytical model for the electric field and breakdown voltage

    International Nuclear Information System (INIS)

    Luo Xiaorong; Zhang Wei; Zhang Bo; Li Zhaoji; Yang Shouguo; Zhan Zhan; Fu Daping

    2008-01-01

    A new SOI high-voltage device with a step-thickness drift region (ST SOI) and its analytical model for the two-dimension electric field distribution and the breakdown voltage are proposed. The electric field in the drift region is modulated and that of the buried layer is enhanced by the variable thickness SOI layer, thereby resulting in the enhancement of the breakdown voltage. Based on the Poisson equation, the expression for the two-dimension electric field distribution is presented taking the modulation effect into account, from which the RESURF (REduced SURface Field) condition and the approximate but explicit expression for the maximal breakdown voltage are derived. The analytical model can explain the effects of the device parameters, such as the step height and the step length of the SOI layer, the doping concentration and the buried oxide thickness, on the electric field distribution and the breakdown voltage. The validity of this model is demonstrated by a comparison with numerical simulations. Improvement on both the breakdown voltage and the on-resistance (R on ) for the ST SOI is obtained due to the variable thickness SOI layer

  7. Hydrogen interactions with silicon-on-insulator materials

    NARCIS (Netherlands)

    Rivera de Mena, A.J.

    2003-01-01

    The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously

  8. Oxygen-induced inhibition of silicon-on-insulator dewetting

    Energy Technology Data Exchange (ETDEWEB)

    Curiotto, S.; Leroy, F.; Cheynis, F.; Müller, P. [Aix Marseille Université, CNRS, CINaM UMR 7325, 13288 Marseille (France)

    2014-02-10

    We report that solid state dewetting of Si thin film on SiO{sub 2} can be reversibly inhibited by exposing the Si surface to a partial pressure of dioxygen (∼10{sup −7}Torr) at high temperature (∼1100K). Coupling in situ Low-Energy Electron Microscopy and ex situ atomic force microscopy we propose that the pinning of the contact line induced by the presence of small amounts of silicon oxide is the main physical process that inhibits the dewetting.

  9. Topology optimized design for silicon-on-insulator mode converter

    DEFF Research Database (Denmark)

    Frellsen, Louise Floor; Frandsen, Lars Hagedorn; Ding, Yunhong

    2015-01-01

    The field of photonic integrated circuits (PICs) has attracted interest in recent years as they allow high device density while requiring only low operating power. The possibility of exploiting mode division multiplexing (MDM) in future optical communication networks is being investigated...... as a potential method for supporting the constantly increasing internet traffic demand [1]. Mode converters are important components necessary to support on-chip processing of MDM signals and multiple approaches has been followed in realizing such devices [2], [3]. Topology optimization (TO) [4] is a powerful...

  10. A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

    International Nuclear Information System (INIS)

    Wang Zhongjian; Cheng Xinhong; Xia Chao; Xu Dawei; Cao Duo; Song Zhaorui; Yu Yuehui; Shen Dashen

    2012-01-01

    A 680 V LDMOS on a thin SOI with an improved field oxide (FOX) and dual field plate was studied experimentally. The FOX structure was formed by an 'oxidation-etch-oxidation' process, which took much less time to form, and had a low protrusion profile. A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance. An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field. Using a SimBond SOI wafer with a 1.5 μm top silicon and a 3 μm buried oxide layer, CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V, and the specific on-resistance was 8.2 Ω·mm 2 . (semiconductor devices)

  11. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

    1999-01-01

    A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology

  12. Photonic Hilbert transformers based on laterally apodized integrated waveguide Bragg gratings on a SOI wafer.

    Science.gov (United States)

    Bazargani, Hamed Pishvai; Burla, Maurizio; Chrostowski, Lukas; Azaña, José

    2016-11-01

    We experimentally demonstrate high-performance integer and fractional-order photonic Hilbert transformers based on laterally apodized Bragg gratings in a silicon-on-insulator technology platform. The sub-millimeter-long gratings have been fabricated using single-etch electron beam lithography, and the resulting HT devices offer operation bandwidths approaching the THz range, with time-bandwidth products between 10 and 20.

  13. Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

    Science.gov (United States)

    Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

    Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

  14. SOI optical microring resonator with poly(ethylene glycol) polymer brush for label-free biosensor applications

    Czech Academy of Sciences Publication Activity Database

    De Vos, D.; Girones, J.; Popelka, Štěpán; Schacht, E. H.; Baets, R.; Bienstman, P.

    2009-01-01

    Roč. 24, č. 8 (2009), s. 2528-2533 ISSN 0956-5663 Institutional research plan: CEZ:AV0Z40500505 Keywords : silicon-on-insulator * microring resonator * optical biosensor Subject RIV: CD - Macromolecular Chemistry Impact factor: 5.429, year: 2009

  15. Charge accumulation in the buried oxide of SOI structures with the bonded Si/SiO2 interface under γ-irradiation: effect of preliminary ion implantation

    International Nuclear Information System (INIS)

    Naumova, O V; Fomin, B I; Ilnitsky, M A; Popov, V P

    2012-01-01

    In this study, we examined the effect of preliminary boron or phosphorous implantation on charge accumulation in the buried oxide of SOI-MOSFETs irradiated with γ-rays in the total dose range (D) of 10 5 –5 × 10 7 rad. The buried oxide was obtained by high-temperature thermal oxidation of Si, and it was not subjected to any implantation during the fabrication process of SOI structures. It was found that implantation with boron or phosphorous ions, used in fabrication technologies of SOI-MOSFETs, increases the concentration of precursor traps in the buried oxide of SOI structures. Unlike in the case of boron implantation, phosphorous implantation leads to an increased density of states at the Si/buried SiO 2 interface during subsequent γ-irradiation. In the γ-irradiated SOI-MOSFETs, the accumulated charge density and the density of surface states in the Si/buried oxide layer systems both vary in proportion to k i ln D. The coefficients k i for as-fabricated and ion-implanted Si/buried SiO 2 systems were evaluated. From the data obtained, it was concluded that a low density of precursor hole traps was a factor limiting the positive charge accumulation in the buried oxide of as-fabricated (non-implanted) SOI structures with the bonded Si/buried SiO 2 interface. (paper)

  16. Hybrid III-V/SOI Resonant Cavity Photodetector

    DEFF Research Database (Denmark)

    Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

    2016-01-01

    A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization.......A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization....

  17. Scaling limits and reliability of SOI CMOS technology

    International Nuclear Information System (INIS)

    Ioannou, D E

    2005-01-01

    As bulk and PD-SOI CMOS approach their scaling limit (at gate length of around 50 nm), there is a renewed interest on FD-SOI because of its potential for continued scalability beyond this limit. In this review the performance and reliability of extremely scaled FD transistors are discussed and an attempt is made to identify critical areas for further research. (invited paper)

  18. A radiation-hardened SOI-based FPGA

    International Nuclear Information System (INIS)

    Han Xiaowei; Wu Lihua; Zhao Yan; Li Yan; Zhang Qianli; Chen Liang; Zhang Guoquan; Li Jianzhong; Yang Bo; Gao Jiantou; Wang Jian; Li Ming; Liu Guizhai; Zhang Feng; Guo Xufeng; Chen, Stanley L.; Liu Zhongli; Yu Fang; Zhao Kai

    2011-01-01

    A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 x 10 11 rad(Si)/s and a neutron fluence immunity of 1 x 10 14 n/cm 2 . (semiconductor integrated circuits)

  19. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  20. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-01-01

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

  1. Investigation of Wide-FSR SOI Optical Filters Operating in C and L Bands

    Directory of Open Access Journals (Sweden)

    V. M. N. Passaro

    2012-06-01

    Full Text Available In this paper we present the investigation of optical filters based on triple ring resonator architectures in silicon-on-insulator technology. The generalized approach based on Mason’s rule and delay line signal processing has been implemented for modeling optical filters in Z-domain. A numerical investigation based on the coefficient map has been adopted for designing optical add-drop multiplexers with wide free spectral ranges, as large as 12 THz (~ 96 nm. Low crosstalk, of the order of -20 dB, has been numerically demonstrated in overall transmittances of optimized filters.

  2. Investigation of SOI Raman Lasers for Mid-Infrared Gas Sensing

    Science.gov (United States)

    Passaro, Vittorio M.N.; De Leonardis, Francesco

    2009-01-01

    In this paper, the investigation and detailed modeling of a cascaded Raman laser, operating in the midwave infrared region, is described. The device is based on silicon-on-insulator optical waveguides and a coupled resonant microcavity. Theoretical results are compared with recent experiments, demonstrating a very good agreement. Design criteria are derived for cascaded Raman lasers working as continuous wave light sources to simultaneously sense two types of gases, namely C2H6 and CO2, at a moderate power level of 130 mW. PMID:22408481

  3. Fast and low power Michelson interferometer thermo-optical switch on SOI.

    Science.gov (United States)

    Song, Junfeng; Fang, Q; Tao, S H; Liow, T Y; Yu, M B; Lo, G Q; Kwong, D L

    2008-09-29

    We designed and fabricated silicon-on-insulator based Michelson interferometer (MI) thermo-optical switches with deep etched trenches for heat-isolation. Switch power was reduced approximately 20% for the switch with deep etched trenches, and the MI saved approximately 50% power than that of the Mach-Zehnder interferometer. 10.6 mW switch power, approximately 42 micros switch time for the MI with deep trenches, 13.14 mW switch power and approximately 34 micros switch time for the MI without deep trenches were achieved.

  4. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    Directory of Open Access Journals (Sweden)

    Bo Xie

    2015-09-01

    Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  5. Croire en soi, croire en l'autre

    Directory of Open Access Journals (Sweden)

    Eugène Enriquez

    2014-04-01

    Full Text Available La croyance aux Dieux ou en un Dieu unique c'est-à-dire à l'incroyable est fort répandue et semble normale comme avoir confiance en soi et en l'autre. Mais croire en soi et en l'autre apparaît étonnant car ce serait se mettre sur le même rang que Dieu. Effectivement l'homme essaie de ressembler à Dieu. Mais à Dieu blessé, faillible, s'interrogeant constamment. Ce Dieu nouveau est un "sujet amoureux" amoureux de soi, de l'autre et de la vie. Il se conduit comme un "Dichter" assumant une responsabilité morale. Il est difficile, voire souvent impossible de se situer comme un "Dichter". C'est pourtant la tâche à laquelle l'homme contemporain est confronté.

  6. SOI technology for power management in automotive and industrial applications

    Science.gov (United States)

    Stork, Johannes M. C.; Hosey, George P.

    2017-02-01

    Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding "Internet of Things" (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies.

  7. Design and optimization of different P-channel LUDMOS architectures on a 0.18 µm SOI-CMOS technology

    International Nuclear Information System (INIS)

    Cortés, I; Toulon, G; Morancho, F; Hugonnard-Bruyere, E; Villard, B; Toren, W J

    2011-01-01

    This paper focuses on the design and optimization of different power P-channel LDMOS transistors (V BR > 120 V) to be integrated in a new generation of smart-power technology based upon a 0.18 µm SOI-CMOS technology. Different drift architectures have been envisaged in this work with the purpose of optimizing the transistor static (R on-sp /V BR trade-off) and dynamic (R on × Q g ) characteristics to improve their switching performance. Conventional single-RESURF P-channel LUDMOS architectures on thin-SOI substrates show very poor R on-sp /V BR trade-off due to their low RESURF effectiveness. Alternative drift configurations such as the addition of an N-type buried layer deep inside the SOI layer or the application of the superjunction concept by alternatively placing stacked P- and N-type pillars could highly improve the RESURF effectiveness and the P-channel device switching performance

  8. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

  9. The Bridges SOI Model School Program at Palo Verde School, Palo Verde, Arizona.

    Science.gov (United States)

    Stock, William A.; DiSalvo, Pamela M.

    The Bridges SOI Model School Program is an educational service based upon the SOI (Structure of Intellect) Model School curriculum. For the middle seven months of the academic year, all students in the program complete brief daily exercises that develop specific cognitive skills delineated in the SOI model. Additionally, intensive individual…

  10. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

  11. SOI Transistor measurement techniques using body contacted transistors

    International Nuclear Information System (INIS)

    Worley, E.R.; Williams, R.

    1989-01-01

    Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

  12. Photonic bandpass filter characteristics of multimode SOI waveguides integrated with submicron gratings.

    Science.gov (United States)

    Sah, Parimal; Das, Bijoy Krishna

    2018-03-20

    It has been shown that a fundamental mode adiabatically launched into a multimode SOI waveguide with submicron grating offers well-defined flat-top bandpass filter characteristics in transmission. The transmitted spectral bandwidth is controlled by adjusting both waveguide and grating design parameters. The bandwidth is further narrowed down by cascading two gratings with detuned parameters. A semi-analytical model is used to analyze the filter characteristics (1500  nm≤λ≤1650  nm) of the device operating in transverse-electric polarization. The proposed devices were fabricated with an optimized set of design parameters in a SOI substrate with a device layer thickness of 250 nm. The pass bandwidth of waveguide devices integrated with single-stage gratings are measured to be ∼24  nm, whereas the device with two cascaded gratings with slightly detuned periods (ΔΛ=2  nm) exhibits a pass bandwidth down to ∼10  nm.

  13. Propriété de soi et indifférence morale du rapport à soi

    Directory of Open Access Journals (Sweden)

    Nathalie Maillard Romagnoli

    2011-05-01

    Full Text Available Je m’interroge dans cet article sur les implications du principe libertarien de la pleine propriété de soi sur la question du rapport moral à soi-même. À travers le principe de la pleine propriété de soi, les libertariens défendent la liberté entière de chacun de vivre comme il l���entend, pourvu que les droits des autres soient respectés. Apparemment, ce principe n’a pas grand-chose à nous dire sur ce que nous sommes moralement autorisés à nous faire à nous-mêmes ou non. Certains libertariens, comme Vallentyne, soutiennent toutefois que le principe de la pleine propriété de soi est incompatible avec l’existence de devoirs envers soi. La pleine propriété de soi impliquerait l’indifférence morale du rapport à soi. Je soutiens dans cet article que le principe de la pleine propriété de soi n’implique pas que ce que nous nous faisons à nous-mêmes soit moralement indifférent. Je veux aussi montrer que même si les libertariens, et en particulier Vallentyne, soutiennent la thèse de l’indifférence morale du rapport à soi, celle-ci n’est pas liée à la thèse de la pleine propriété de soi, mais bien plutôt à leur subjectivisme moral.ABSTRACTI ask in this article what the libertarian principle of full self-ownership has to say about volontary actions directed towards oneself. Through the principle of full self-ownership, libertarians defend the persons’ individual liberty to live as they choose to do, as long as they don’t infringe on the rights of others. Apparently, this principle doesn’t have much to say about what we are morally allowed to do to ourselves or not. Some libertarians, however, like Vallentyne, maintain that, if we have duties or obligations to ourselves, then we cannot be full self-owner. In this perspective, full self-ownership would imply that what we do to ourselves is morally indifferent. I want to show in this article that full self-ownership is compatible with the

  14. Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

    Science.gov (United States)

    Duclaux, Benjamin; De Caunes, Jean; Perrier, Robin; Gatefait, Maxime; Le Gratiet, Bertrand; Chapon, Jean-Damien; Monget, Cédric

    2018-03-01

    Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the "more than Moore" path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or "virtual overlay" could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.

  15. Ultrabroadband Hybrid III-V/SOI Grating Reflector for On-chip Lasers

    DEFF Research Database (Denmark)

    Park, Gyeong Cheol; Taghizadeh, Alireza; Chung, Il-Sug

    2016-01-01

    We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability.......We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability....

  16. Multilayered photonic integration on SOI platform using waveguide-based bridge structure

    Science.gov (United States)

    Majumder, Saikat; Chakraborty, Rajib

    2018-06-01

    A waveguide based structure on silicon on insulator platform is proposed for vertical integration in photonic integrated circuits. The structure consists of two multimode interference couplers connected by a single mode (SM) section which can act as a bridge over any other underlying device. Two more SM sections acts as input and output of the first and second multimode couplers respectively. Potential application of this structure is in multilayered photonic links. It is shown that the efficiency of the structure can be improved by making some design modifications. The entire simulation is done using effective-index based matrix method. The feature size chosen are comparable to waveguides fabricated previously so as to fabricate the proposed structure easily.

  17. Comparison of the ion induced charge collection in Si epilayer and SOI devices

    International Nuclear Information System (INIS)

    Hirao, Toshio; Mori, Hidenobu; Laird, Jamie Stuart; Onoda, Shinobu; Itoh, Hisayoshi

    2003-01-01

    It is known that the single-event phenomena (SEP) are the malfunction of micro electronics devices caused by the impact of an energetic heavy ion. Improving the tolerance of devices to the SEP requires a better understanding of basic charge collection mechanisms on the timescales of the order of picoseconds. In order to better elucidate these mechanisms, we measure the fast transient current resulting from heavy ion strikes with a fast sampling data collection system and a heavy ion microbeam line at JAERI. In this paper we report on differences in both the transient current and charge collection from 15 MeV carbon ions on silicon-on-insulator, Si epilayer and bulk p + n junction diodes and charge transportation under MeV ion injection is discussed

  18. A 3-DOF SOI MEMS ultrasonic energy harvester for implanted devices

    International Nuclear Information System (INIS)

    Fowler, A G; Moheimani, S O R; Behrens, S

    2013-01-01

    This paper reports the design and testing of a microelectromechanical systems (MEMS) energy harvester that is designed to harvest electrical energy from an external source of ultrasonic waves. This mechanism is potentially suited to applications including the powering of implanted devices for biomedical applications. The harvester employs a novel 3-degree of freedom design, with electrical energy being generated from displacements of a proof mass via electrostatic transducers. A silicon-on-insulator MEMS process was used to fabricate the device, with experimental characterization showing that the harvester can generate 24.7 nW, 19.8 nW, and 14.5 nW of electrical power respectively through its x-, y-, and z-axis vibrational modes

  19. Optical signal processing by silicon photonics

    CERN Document Server

    Ahmed, Jameel; Adeel, Freeha; Hussain, Ashiq

    2014-01-01

    The main objective of this book is to make respective graduate students understand the nonlinear effects inside SOI waveguide and possible applications of SOI waveguides in this emerging research area of optical fibre communication. This book focuses on achieving successful optical frequency shifting by Four Wave Mixing (FWM) in silicon-on-insulator (SOI) waveguide by exploiting a nonlinear phenomenon.

  20. Development of radiation hard CMOS active pixel sensors for HL-LHC

    International Nuclear Information System (INIS)

    Pernegger, Heinz

    2016-01-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  1. Hybrid III-V/SOI resonant cavity enhanced photodetector

    DEFF Research Database (Denmark)

    Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

    2016-01-01

    A hybrid III–V/SOI resonant-cavity-enhanced photodetector (RCE-PD) structure comprising a high-contrast grating (HCG) reflector, a hybrid grating (HG) reflector, and an air cavity between them, has been proposed and investigated. In the proposed structure, a light absorbing material is integrated...... as part of the HG reflector, enabling a very compact vertical cavity. Numerical investigations show that a quantum efficiency close to 100 % and a detection linewidth of about 1 nm can be achieved, which are desirable for wavelength division multiplexing applications. Based on these results, a hybrid RCE...

  2. Inverse Design of a SOI T-junction Polarization Beamsplitter

    Science.gov (United States)

    Ye, Zi; Qiu, Jifang; Meng, Chong; Zheng, Li; Dong, Zhenli; Wu, Jian

    2017-06-01

    A SOI T-junction polarization beamsplitter with an ultra-compact footprint of 2.8×2.8μm2 is designed based on the method of inverse design. Simulated results show that the conversion efficiencies for TE and TM lights are 73.34% (simulated insertion loss of 2dB) and 80.4% (simulated insertion loss of 1.7dB) at 1550nm, respectively; the simulated extinction ratios for TE and TM lights are 19.3dB and 13.99dB at 1558nm, respectively.

  3. The founder of the Friends Foundation--Tessie Soi.

    Science.gov (United States)

    Topurua, Ore

    2013-01-01

    Tessie Soi is well known in Papua New Guinea and beyond for her work with HIV/AIDS (human immunodeficiency virus/acquired immune deficiency syndrome) patients, including through the Friends Foundation, an organization that focuses on helping families affected by HIV and AIDS. This article explores Tessie's early life and childhood, providing insight into some of the values she learned from her parents. Providing details about the Friends Foundation and the Orphan Buddy Systems program, a program Tessie established to support AIDS orphans, the article offers insight into Tessie's beliefs and compassion, simultaneously highlighting the value she places on her family.

  4. Worst-Case Bias During Total Dose Irradiation of SOI Transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Colladant, T.; Paillet, P.; Leray, J.-L; Musseau, O.; Schwank, James R.; Shaneyfelt, Marty R.; Pelloie, J.L.; Du Port de Poncharra, J.

    2000-01-01

    The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide

  5. Nanoelectromechanical resonator for logic operations

    KAUST Repository

    Kazmi, Syed N. R.

    2017-08-29

    We report an electro-thermally tunable in-plane doubly-clamped nanoelectromechanical resonator capable of dynamically performing NOR, NOT, XNOR, XOR, and AND logic operations. Toward this, a silicon based resonator is fabricated using standard e-beam lithography and surface nanomachining of a highly conductive device layer of a silicon-on-insulator (SOI) wafer. The performance of this logic device is examined at elevated temperatures, ranging from 25 °C to 85 °C, demonstrating its resilience for most of the logic operations; thereby paving the way towards nano-elements-based mechanical computing.

  6. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  7. Gate Engineering in SOI LDMOS for Device Reliability

    Directory of Open Access Journals (Sweden)

    Aanand

    2016-01-01

    Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

  8. Méditation et pratique de soi chez Malebranche.

    Directory of Open Access Journals (Sweden)

    Éric Dubreucq

    2004-04-01

    Full Text Available Une étude des Méditations pour se disposer à l’Humilité et à la pénitence qui les replace dans le cadre des pratiques de son époque, par exemple, chez François de Sales, celles de l’oraison, de la méditation et de la contemplation, permet d’apercevoir que l’une des thèses majeures du malebranchisme, la vision en Dieu, est un effet instauré dans le destinataire par un dispositif textuel. Celui-ci tire sa puissance prescriptive de l’a priori pratique où il s’inscrit. C’est à une opération de production de soi que l’exercice spirituel donne lieu : l’analyse des quatre premières Méditations chrétiennes et métaphysiques, en particulier, montre que c’est une organisation de la substance personnelle que provoque le travail spirituel sur soi. Celui-ci consiste à déterminer le rapport à soi comme relation d’une vision attentive à une activité illuminante, par un décentrement textuel du « je » vers le « tu ».One of the major Malebranche’s assertion, that we see truth in God, is not a mere theoretical thesis. I study first the Méditations pour se disposer à l’Humilité et à la pénitence and compare them with François de Sales’ spiritual exercitations, and show that prayer, meditation and contemplation constitute the practical frameworks of this period. The text of the Méditations is an apparatus which is fit to cause an effect in its target – the self of the reader : the vision in God. The practical a priori of the meditation provides the text with prescriptive power to transform the self. Then I study the Méditations chrétiennes et métaphysiques i-iv : we see that Malebranche set his textual apparatus so that it prescribes its receiver a form of « work-on-one’s-self ». The self is here produced by the organisation of relationship between attentive vision and lighting action, and this structure is built in the self by a movement, induced by the text, which leads the self from

  9. L’estime de soi : un cas particulier d’estime sociale ?

    OpenAIRE

    Santarelli, Matteo

    2016-01-01

    Un des traits plus originaux de la théorie intersubjective de la reconnaissance d’Axel Honneth, consiste dans la façon dont elle discute la relation entre estime sociale et estime de soi. En particulier, Honneth présente l’estime de soi comme un reflet de l’estime sociale au niveau individuel. Dans cet article, je discute cette conception, en posant la question suivante : l’estime de soi est-elle un cas particulier de l’estime sociale ? Pour ce faire, je me concentre sur deux problèmes crucia...

  10. Special Issue: Planar Fully-Depleted SOI technology

    Science.gov (United States)

    Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

    2016-03-01

    We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

  11. A grating coupler with a trapezoidal hole array for perfectly vertical light coupling between optical fibers and waveguides

    Science.gov (United States)

    Mizutani, Akio; Eto, Yohei; Kikuta, Hisao

    2017-12-01

    A grating coupler with a trapezoidal hole array was designed and fabricated for perfectly vertical light coupling between a single-mode optical fiber and a silicon waveguide on a silicon-on-insulator (SOI) substrate. The grating coupler with an efficiency of 53% was computationally designed at a 1.1-µm-thick buried oxide (BOX) layer. The grating coupler and silicon waveguide were fabricated on the SOI substrate with a 3.0-µm-thick BOX layer by a single full-etch process. The measured coupling efficiency was 24% for TE-polarized light at 1528 nm wavelength, which was 0.69 times of the calculated coupling efficiency for the 3.0-µm-thick BOX layer.

  12. First results of a Double-SOI pixel chip for X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Lu, Yunpeng, E-mail: yplu@ihep.ac.cn [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Ouyang, Qun [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Arai, Yasuo [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org., KEK, Tsukuba 305-0801 (Japan); Liu, Yi; Wu, Zhigang; Zhou, Yang [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China)

    2016-09-21

    Aiming at low energy X-ray imaging, a prototype chip based on Double-SOI process was designed and tested. The sensor and pixel circuit were characterized. The long lasting crosstalk issue in SOI technology was understood. The operation of pixel was verified with a pulsed infrared laser beam. The depletion of sensor revealed by signal amplitudes is consistent with the one revealed by I–V curve. An s-curve fitting resulted in a sigma of 153 e{sup −} among which equivalent noise charge (ENC) contributed 113 e{sup −}. It's the first time that the crosstalk issue in SOI technology was solved and a counting type SOI pixel demonstrated the detection of low energy radiation quantitatively.

  13. New Insights into Fully-Depleted SOI Transistor Response During Total Dose Irradiation

    International Nuclear Information System (INIS)

    Burns, J.A.; Dodd, P.E.; Keast, C.L.; Schwank, J.R.; Shaneyfelt, M.R.; Wyatt, P.W.

    1999-01-01

    Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. No evidence was found for total-dose induced snap back. These results have implications for hardness assurance testing

  14. A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

    Science.gov (United States)

    Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

    The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

  15. Experimental verification of temperature coefficients of resistance for uniformly doped P-type resistors in SOI

    Science.gov (United States)

    Olszacki, M.; Maj, C.; Bahri, M. Al; Marrot, J.-C.; Boukabache, A.; Pons, P.; Napieralski, A.

    2010-06-01

    Many today's microsystems like strain-gauge-based piezoresistive pressure sensors contain doped resistors. If one wants to predict correctly the temperature impact on the performance of such devices, the accurate data about the temperature coefficients of resistance (TCR) are essential. Although such data may be calculated using one of the existing mobility models, our experiments showed that we can observe the huge mismatch between the calculated and measured values. Thus, in order to investigate the TCR values, a set of the test structures that contained doped P-type resistors was fabricated. As the TCR value also depends on the doping profile shape, we decided to use the very thin, 340 nm thick SOI wafers in order to fabricate the quasi-uniformly doped silicon layers ranging from 2 × 1017 at cm-3 to 1.6 × 1019 at cm-3. The results showed that the experimental data for the first-order TCR are quite far from the calculated ones especially over the doping range of 1018-1019 at cm-3 and quite close to the experimental ones obtained by Bullis about 50 years ago for bulk silicon. Moreover, for the first time, second-order coefficients that were not very consistent with the calculations were obtained.

  16. Experimental verification of temperature coefficients of resistance for uniformly doped P-type resistors in SOI

    International Nuclear Information System (INIS)

    Olszacki, M; Maj, C; Al Bahri, M; Marrot, J-C; Boukabache, A; Pons, P; Napieralski, A

    2010-01-01

    Many today's microsystems like strain-gauge-based piezoresistive pressure sensors contain doped resistors. If one wants to predict correctly the temperature impact on the performance of such devices, the accurate data about the temperature coefficients of resistance (TCR) are essential. Although such data may be calculated using one of the existing mobility models, our experiments showed that we can observe the huge mismatch between the calculated and measured values. Thus, in order to investigate the TCR values, a set of the test structures that contained doped P-type resistors was fabricated. As the TCR value also depends on the doping profile shape, we decided to use the very thin, 340 nm thick SOI wafers in order to fabricate the quasi-uniformly doped silicon layers ranging from 2 × 10 17 at cm −3 to 1.6 × 10 19 at cm −3 . The results showed that the experimental data for the first-order TCR are quite far from the calculated ones especially over the doping range of 10 18 –10 19 at cm −3 and quite close to the experimental ones obtained by Bullis about 50 years ago for bulk silicon. Moreover, for the first time, second-order coefficients that were not very consistent with the calculations were obtained.

  17. Le soi et l’estime de soi chez l’enfant: Une revue systématique de la littérature

    OpenAIRE

    Pinto, Alexandra Maria Pereira Inácio Sequeira; Gatinho, Ana Rita dos Santos; Tereno, Susana; Veríssimo, Manuela

    2016-01-01

    Cette étude vise : a) à analyser les différentes méthodes utilisées pour l’étude du Soi et chez les enfants, en ce que concerne sa qualité et son potentiel et b) à synthétiser les résultats déjà obtenus en termes de Soi/d’estime de soi/d’autoconcept, pour les enfants en âge préscolaire. Après avoir établi des critères rigoureux d’inclusion et d’exclusion, 33 articles ont été sélectionnés, dans plusieurs bases de données, nationales et international...

  18. Deep sub-micron FD-SOI for front-end application

    International Nuclear Information System (INIS)

    Ikeda, H.; Arai, Y.; Hara, K.; Hayakawa, H.; Hirose, K.; Ikegami, Y.; Ishino, H.; Kasaba, Y.; Kawasaki, T.; Kohriki, T.; Martin, E.; Miyake, H.; Mochizuki, A.; Tajima, H.; Tajima, O.; Takahashi, T.; Takashima, T.; Terada, S.; Tomita, H.; Tsuboyama, T.

    2007-01-01

    In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented

  19. Micromachined thin-film sensors for SOI-CMOS co-integration

    CERN Document Server

    Laconte, Jean; Raskin, Jean-Pierre

    2006-01-01

    Co-integration of MEMS and MOS in SOI technology is promising and well demonstrated hereThe impact of Micromachining on SOI devices is deeply analyzed for the first timeInclude extensive TMAH etching, residual stress, microheaters, gas-flow sensors reviewResidual stresses in thin films need to be more and more monitored in MEMS designsTMAH micromachining is an attractive alternative to KOH.

  20. Engineered SOI slot waveguide ring resonator V-shape resonance combs for refraction index sensing up to 1300nm/RIU (Conference Presentation)

    Science.gov (United States)

    Zhang, Weiwei; Serna, Samuel; Le Roux, Xavier; Vivien, Laurent; Cassan, Eric

    2016-05-01

    Bio-detection based on CMOS technology boosts the miniaturization of detection systems and the success on highly efficient, robust, accurate, and low coast Lab-on-Chip detection schemes. Such on chip detection technologies have covered healthy related harmful gases, bio-chemical analytes, genetic micro RNA, etc. Their monitoring accuracy is mainly qualified in terms of sensitivity and limit of the detection (LOD) of the detection system. In this context, recently developed silicon on insulator (SOI) optical devices have displayed highly performant detection abilities that LOD could go beyond 10-8RIU and sensitivity could exceeds 103nm/RIU. The SOI integrated optical sensing devices include strip/slotted waveguide consisting in structures like Mach-Zehnder interferometers (MZI), ring resonators (RR), nano cavities, etc. Typically, hollow core RR and nano-cavities could exhibit higher sensitivity due to their optical mode confinement properties with a partial localization of the electric field in low index sensing regions than devices based on evanescent field tails outside of the optical cores. Furthermore, they also provide larger sensing areas for surface functionalization to reach higher sensitivities and lower LODs. The state of art of hollow core devices, either based on Bragg gratings formed from a slot waveguide cavity or photonic crystal slot cavities, show sensitivities (S) up to 400nm/RIU and Figure of Merit (FOM) around 3,000 in water environment, FOM being defined as the inverse of LOD and precisely as FOM=SQ/λ, with λ the resonance wavelength and Q the quality factor of the considered resonator. Such high achieved FOMs in nano cavities are mainly due to their large Q factors around 15,000. While for mostly used RR, which do not require particular design strategies, relatively low Q factors around 1800 in water are met and moderate sensitivities about 300nm/RIU are found. In this work, we present here a novel slot ring resonator design to make

  1. Single halo SDODEL n-MOSFET: an alternative low-cost pseudo-SOI with better analog performance

    Science.gov (United States)

    Sarkar, Partha; Mallik, Abhijit; Sarkar, Chandan Kumar

    2009-03-01

    In this paper, with the help of extensive TCAD simulations, we investigate the analog performance of source/drain on depletion layer (SDODEL) MOSFETs with a single-halo (SH) implant near the source side of the channel. We use the SH implant in such a structure for the first time. The analog performance parameters in SH SDODEL MOSFETs are compared to those in SH MOSFETs as well as in SH SOI MOSFETs. In addition to reduced junction capacitance for the SH SDODEL structure as compared to that in bulk SH devices, it has been shown that such devices lead to improved performance and lower power dissipation for sub-100 nm CMOS technologies. Our results show that, in SH SDODEL MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/ID, etc) for the sub-100 nm technologies.

  2. Single halo SDODEL n-MOSFET: an alternative low-cost pseudo-SOI with better analog performance

    International Nuclear Information System (INIS)

    Sarkar, Partha; Mallik, Abhijit; Sarkar, Chandan Kumar

    2009-01-01

    In this paper, with the help of extensive TCAD simulations, we investigate the analog performance of source/drain on depletion layer (SDODEL) MOSFETs with a single-halo (SH) implant near the source side of the channel. We use the SH implant in such a structure for the first time. The analog performance parameters in SH SDODEL MOSFETs are compared to those in SH MOSFETs as well as in SH SOI MOSFETs. In addition to reduced junction capacitance for the SH SDODEL structure as compared to that in bulk SH devices, it has been shown that such devices lead to improved performance and lower power dissipation for sub-100 nm CMOS technologies. Our results show that, in SH SDODEL MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g m /I D , etc) for the sub-100 nm technologies

  3. Generation and confinement of mobile charges in buried oxide of SOI substrates; Generation et confinement de charges mobiles dans les oxydes enterres de substrats SOI

    Energy Technology Data Exchange (ETDEWEB)

    Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A. [CEA Bruyeres-le-Chatel, DIF, 91 (France)

    1999-07-01

    We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO{sub 2} interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

  4. Applications of Silicon-on-Insulator Photonic Crystal Structures in Miniature Spectrometer Designs

    Science.gov (United States)

    Gao, Boshen

    Optical spectroscopy is one of the most important fundamental scientific techniques. It has been widely adopted in physics, chemistry, biology, medicine and many other research fields. However, the size and weight of a spectrometer as well as the difficulty to align and maintain it have long limited spectroscopy to be a laboratory-only procedure. With the recent advancement in semiconductor electronics and photonics, miniaturized spectrometers have been introduced to complete many tasks in daily life where mobility and portability are necessary. This thesis focuses on the study of several photonic crystal (PC) nano-structures potentially suitable for miniaturized on-chip spectrometer designs. Chapter 1 briefly introduces the concept of PCs and their band structures. By analyzing the band structure, the origin of the superprism effect is explained. Defect-based PC nano-cavities are also discussed, as well as a type of coupled cavity waveguides (CCW) composed of PC nano-cavities. Chapter 2 is devoted to the optimization of a flat-band superprism structure for spectroscopy application using numerical simulations. Chapter 3 reports a fabricated broad-band superprism and the experimental characterization of its wavelength resolving performance. In chapter 4, the idea of composing a miniature spectrometer based on a single tunable PC nano-cavity is proposed. The rest of this chapter discusses the experimental study of this design. Chapter 5 examines the slow-light performance of a CCW and discusses its potential application in slow-light interferometry. Chapter 6 serves as a conclusion of this thesis and proposes directions for possible future work to follow up.

  5. Dynamics of solid thin-film dewetting in the silicon-on-insulator system

    Energy Technology Data Exchange (ETDEWEB)

    Bussmann, E; Cheynis, F; Leroy, F; Mueller, P [Centre Interdisciplinaire de Nanoscience de Marseille (CINaM) CNRS UPR 3118, Aix-Marseille Universite, 13288 Marseille (France); Pierre-Louis, O, E-mail: muller@cinam.univ-mrs.fr [LPMCN, Universite Lyon 1, 43 Bd du 11 novembre, 69622 Villeurbane (France)

    2011-04-15

    Using low-energy electron microscopy movies, we have measured the dewetting dynamics of single-crystal Si(001) thin films on SiO{sub 2} substrates. During annealing (T>700 deg. C), voids open in the Si, exposing the oxide. The voids grow, evolving Si fingers that subsequently break apart into self-organized three-dimensional (3D) Si nanocrystals. A kinetic Monte Carlo model incorporating surface and interfacial free energies reproduces all the salient features of the morphological evolution. The dewetting dynamics is described using an analytic surface-diffusion-based model. We demonstrate quantitatively that Si dewetting from SiO{sub 2} is mediated by surface-diffusion driven by surface free-energy minimization.

  6. Dynamics of solid thin-film dewetting in the silicon-on-insulator system

    Science.gov (United States)

    Bussmann, E.; Cheynis, F.; Leroy, F.; Müller, P.; Pierre-Louis, O.

    2011-04-01

    Using low-energy electron microscopy movies, we have measured the dewetting dynamics of single-crystal Si(001) thin films on SiO2 substrates. During annealing (T>700 °C), voids open in the Si, exposing the oxide. The voids grow, evolving Si fingers that subsequently break apart into self-organized three-dimensional (3D) Si nanocrystals. A kinetic Monte Carlo model incorporating surface and interfacial free energies reproduces all the salient features of the morphological evolution. The dewetting dynamics is described using an analytic surface-diffusion-based model. We demonstrate quantitatively that Si dewetting from SiO2 is mediated by surface-diffusion driven by surface free-energy minimization.

  7. Epitaxial Reactor Development for Growth of Silicon-on-Insulator Devices.

    Science.gov (United States)

    1987-04-01

    emision from substrate reflected from interface 40 Constructive interference condition 2tc= n X / 1 * Destrictive interference condition 2tD= (2n+1) X...combinations of growth conditions resulted in no oxide growth on the original silicon wafer. Growths occurred for Si:O molecular ratios higher than 1:1...growth rates occurred at 1050 0 C with water vapor at 1250 cc/min and silane at 50 cc/min. These results are shown in Table 6. The molecular ratio was 2:1

  8. Raman mediated all-optical cascadable inverter using silicon-on-insulator waveguides.

    Science.gov (United States)

    Sen, Mrinal; Das, Mukul K

    2013-12-01

    In this Letter, we propose an all-optical circuit for a cascadable and integrable logic inverter based on stimulated Raman scattering. A maximum product criteria for noise margin is taken to analyze the cascadability of the inverter. Variation of noise margin for different model parameters is also studied. Finally, the time domain response of the inverter is analyzed for different widths of input pulses.

  9. Topology-optimized mode converter in a silicon-on-insulator photonic wire waveguide

    DEFF Research Database (Denmark)

    Frellsen, Louise Floor; Ding, Yunhong; Sigmund, Ole

    2016-01-01

    A 1.4 μm × 3.4 μm fundamental to first order mode converter for the transverse electric polarization was designed using topology optimization. Insertion loss <2 dB (100 nm bandwidth) and extinction ratio >9.5 dB....

  10. Topology optimized mode multiplexing in silicon-on-insulator photonic wire waveguides

    DEFF Research Database (Denmark)

    Frellsen, Louise Floor; Ding, Yunhong; Sigmund, Ole

    2016-01-01

    We design and experimentally verify a topology optimized low-loss and broadband two-mode (de-)multiplexer, which is (de-)multiplexing the fundamental and the first-order transverse-electric modes in a silicon photonic wire. The device has a footprint of 2.6 μm x 4.22 μm and exhibits a loss 14 d...

  11. Analytic description of four-wave mixing in silicon-on-insulator waveguides

    DEFF Research Database (Denmark)

    Friis, Søren Michael Mørk; Koefoed, Jacob Gade; Guo, Kai

    2018-01-01

    and becomes a nonlinear differential equation that we solve analytically without further approximations. The signal and idler equations have no known solutions for arbitrary pump power evolution, but we calculate approximate field expressions based on a Magnus expansion, which has been used to study time...

  12. Two-dimensional optical phased array antenna on silicon-on-insulator.

    Science.gov (United States)

    Van Acoleyen, Karel; Rogier, Hendrik; Baets, Roel

    2010-06-21

    Optical wireless links can offer a very large bandwidth and can act as a complementary technology to radiofrequency links. Optical components nowadays are however rather bulky. Therefore, we have investigated the potential of silicon photonics to fabricated integrated components for wireless optical communication. This paper presents a two-dimensional phased array antenna consisting of grating couplers that couple light off-chip. Wavelength steering of $0.24 degrees /nm is presented reducing the need of active phase modulators. The needed steering range is $1.5 degrees . The 3dB angular coverage range of these antennas is about $0.007pi sr with a directivity of more than 38dBi and antenna losses smaller than 3dB.

  13. Polarization diversity DPSK demodulator on the silicon-on-insulator platform with simple fabrication

    DEFF Research Database (Denmark)

    Ding, Yunhong; Huang, Bo; Ou, Haiyan

    2013-01-01

    of a tapered waveguide followed by a 2 × 2 multimode interferometer. A lowest insertion loss of 0.5 dB with low polarization dependent loss of 1.6 dB and low polarization dependent extinction ratio smaller than 3 dB are measured for the polarization diversity circuit. Clear eye-diagrams and a finite power...

  14. Dynamics of solid thin-film dewetting in the silicon-on-insulator system

    International Nuclear Information System (INIS)

    Bussmann, E; Cheynis, F; Leroy, F; Mueller, P; Pierre-Louis, O

    2011-01-01

    Using low-energy electron microscopy movies, we have measured the dewetting dynamics of single-crystal Si(001) thin films on SiO 2 substrates. During annealing (T>700 deg. C), voids open in the Si, exposing the oxide. The voids grow, evolving Si fingers that subsequently break apart into self-organized three-dimensional (3D) Si nanocrystals. A kinetic Monte Carlo model incorporating surface and interfacial free energies reproduces all the salient features of the morphological evolution. The dewetting dynamics is described using an analytic surface-diffusion-based model. We demonstrate quantitatively that Si dewetting from SiO 2 is mediated by surface-diffusion driven by surface free-energy minimization.

  15. High temperature study of flexible silicon-on-insulator fin field-effect transistors

    KAUST Repository

    Diab, Amer El Hajj; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    . Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature

  16. Preliminary Investigation of an SOI-based Arrayed Waveguide Grating Demodulation Integration Microsystem

    Science.gov (United States)

    Li, Hongqiang; Zhou, Wenqian; Liu, Yu; Dong, Xiaye; Zhang, Cheng; Miao, Changyun; Zhang, Meiling; Li, Enbang; Tang, Chunxiao

    2014-05-01

    An arrayed waveguide grating (AWG) demodulation integration microsystem is investigated in this study. The system consists of a C-band on-chip LED, a 2 × 2 silicon nanowire-based coupler, a fiber Bragg grating (FBG) array, a 1 × 8 AWG, and a photoelectric detector array. The coupler and AWG are made from silicon-on-insulator wafers using electron beam exposure and response-coupled plasma technology. Experimental results show that the excess loss in the MMI coupler with a footprint of 6 × 100 μm2 is 0.5423 dB. The 1 × 8 AWG with a footprint of 267 × 381 μm2 and a waveguide width of 0.4 μm exhibits a central channel loss of -3.18 dB, insertion loss non-uniformity of -1.34 dB, and crosstalk level of -23.1 dB. The entire system is preliminarily tested. Wavelength measurement precision is observed to reach 0.001 nm. The wavelength sensitivity of each FBG is between 0.04 and 0.06 nm/dB.

  17. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  18. Broadband microwave photonic fully tunable filter using a single heterogeneously integrated III-V/SOI-microdisk-based phase shifter.

    Science.gov (United States)

    Lloret, Juan; Morthier, Geert; Ramos, Francisco; Sales, Salvador; Van Thourhout, Dries; Spuesens, Thijs; Olivier, Nicolas; Fédéli, Jean-Marc; Capmany, José

    2012-05-07

    A broadband microwave photonic phase shifter based on a single III-V microdisk resonator heterogeneously integrated on and coupled to a nanophotonic silicon-on-insulator waveguide is reported. The phase shift tunability is accomplished by modifying the effective index through carrier injection. A comprehensive semi-analytical model aiming at predicting its behavior is formulated and confirmed by measurements. Quasi-linear and continuously tunable 2π phase shifts at radiofrequencies greater than 18 GHz are experimentally demonstrated. The phase shifter performance is also evaluated when used as a key element in tunable filtering schemes. Distortion-free and wideband filtering responses with a tuning range of ~100% over the free spectral range are obtained.

  19. Silicon based nanogap device for investigating electronic transport through 12 nm long oligomers

    DEFF Research Database (Denmark)

    Strobel, S.; Albert, E.; Csaba, G.

    2009-01-01

    We have fabricated vertical nanogap electrode devices based on Silicon-on-Insulator (SOI) substrates for investigating the electronic transport properties of long, conjugated molecular wires. Our nanogap electrode devices comprise smooth metallic contact pairs situated at the sidewall of an SOI s...

  20. Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

    International Nuclear Information System (INIS)

    Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

    2006-01-01

    A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

  1. Sub-50 nm gate length SOI transistor development for high performance microprocessors

    International Nuclear Information System (INIS)

    Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

    2004-01-01

    Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

  2. Charge collection mechanisms in MOS/SOI transistors irradiated by energetic heavy ions

    International Nuclear Information System (INIS)

    Musseau, O.; Leray, J.L.; Ferlet, V.; Umbert, A.; Coic, Y.M.; Hesto, P.

    1991-01-01

    We have investigated with both experimental and numerical methods (Monte Carlo and drift-diffusion models) various charge collection mechanisms in NMOS/SOI transistors irradiated by single energetic heavy ions. Our physical interpretations of data emphasize the influence of various parasitic structures of the device. Two charge collection mechanisms are detailed: substrate funneling in buried MOS capacitor and latching of the parasitic bipolar transistor. Based on carrier transport and charge collection, the sensitivity of future scaled down CMOS/SOI technologies is finally discussed

  3. Generation and confinement of mobile charges in buried oxide of SOI substrates

    International Nuclear Information System (INIS)

    Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A.

    1999-01-01

    We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO 2 interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

  4. Analysis and optimization of acoustic wave micro-resonators integrating piezoelectric zinc oxide layers

    Science.gov (United States)

    Mortada, O.; Zahr, A. H.; Orlianges, J.-C.; Crunteanu, A.; Chatras, M.; Blondy, P.

    2017-02-01

    This paper reports on the design, simulation, fabrication, and test results of ZnO-based contour-mode micro-resonators integrating piezoelectric zinc oxide (ZnO) layers. The inter-digitated (IDT) type micro-resonators are fabricated on ZnO films and suspended top of 2 μm thick silicon membranes using silicon-on insulator technology. We analyze several possibilities of increasing the quality factor (Q) and the electromechanical coupling coefficient (kt2) of the devices by varying the numbers and lengths of the IDT electrodes and using different thicknesses of the ZnO layer. We designed and fabricated IDTs of different finger numbers (n = 25, 40, 50, and 80) and lengths (L = 100/130/170/200 μm) for three different thicknesses of ZnO films (200, 600, and 800 nm). The measured Q factor confirms that reducing the length and the number of IDT fingers enables us to reach better electrical performances at resonant frequencies around 700 MHz. The extracted results for an optimized micro-resonator device having an IDT length of 100 μm and 40 finger electrodes show a Q of 1180 and a kt2 of 7.4%. We demonstrate also that the reduction of the ZnO thickness from 800 nm to 200 nm increases the quality factor from 430 to 1600, respectively, around 700 MHz. Experimental data are in very good agreement with theoretical simulations of the fabricated devices

  5. Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

    Science.gov (United States)

    Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

    2007-01-01

    We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

  6. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    Science.gov (United States)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  7. Juan Goytisolo: Le soi, le monde et la création littéraire

    Directory of Open Access Journals (Sweden)

    Pablo Romero Alegría

    2010-01-01

    Full Text Available Reseña de la obra: Yannick Llored. Le soi, le monde et la création littéraire. Presses Universitaires du Septentrion. Villeneuve d’Ascq (Francia. 2009. 421 págs. ISBN: 978-2-75740-0089-0

  8. Waveguide-integrated vertical pin photodiodes of Ge fabricated on p+ and n+ Si-on-insulator layers

    Science.gov (United States)

    Ito, Kazuki; Hiraki, Tatsurou; Tsuchizawa, Tai; Ishikawa, Yasuhiko

    2017-04-01

    Vertical pin structures of Ge photodiodes (PDs) integrated with Si optical waveguides are fabricated by depositing Ge epitaxial layers on Si-on-insulator (SOI) layers, and the performances of n+-Ge/i-Ge/p+-SOI PDs are compared with those of p+-Ge/i-Ge/n+-SOI PDs. Both types of PDs show responsivities as high as 1.0 A/W at 1.55 µm, while the dark leakage current is different, which is consistent with previous reports on free-space PDs formed on bulk Si wafers. The dark current of the p+-Ge/i-Ge/n+-SOI PDs is higher by more than one order of magnitude. Taking into account the activation energies for dark current as well as the dependence on PD area, the dark current of the n+-Ge/i-Ge/p+-SOI PDs is dominated by the thermal generation of carriers via mid-gap defect levels in Ge, while for the p+-Ge/i-Ge/n+-SOI PDs, the dark current is ascribed to not only thermal generation but also other mechanisms such as locally formed conduction paths.

  9. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

    Science.gov (United States)

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-08-18

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  10. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

    Directory of Open Access Journals (Sweden)

    Ha-Duong Ngo

    2015-08-01

    Full Text Available In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load with an accuracy of 0.25% Full Scale Output (FSO. A push rod (mounted onto the steel membrane transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process. A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  11. Total dose radiation effects of pressure sensors fabricated on uni-bond-SOI materials

    International Nuclear Information System (INIS)

    Zhu Shiyang; Huang Yiping; Wang Jin; Li Anzhen; Shen Shaoqun; Bao Minhang

    2001-01-01

    Piezoresistive pressure sensors with a twin-island structure were successfully fabricated using high quality Uni-bond-SOI (On Insulator) materials. Since the piezoresistors were structured by the single crystalline silicon overlayer of the SOI wafer and were totally isolated by the buried SiO 2 , the sensors are radiation-hard. The sensitivity and the linearity of the pressure sensors keep their original values after being irradiated by 60 Co γ-rays up to 2.3 x 10 4 Gy(H 2 O). However, the offset voltage of the sensor has a slight drift, increasing with the radiation dose. The absolute value of the offset voltage deviation depends on the pressure sensor itself. For comparison, corresponding polysilicon pressure sensors were fabricated using the similar process and irradiated at the same condition

  12. Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

    Directory of Open Access Journals (Sweden)

    Avi Karsenty

    2015-01-01

    Full Text Available Nanoscale Gate-Recessed Channel (GRC Fully Depleted- (FD- SOI MOSFET device with a silicon channel thickness (tSi as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

  13. Process optimization of a deep trench isolation structure for high voltage SOI devices

    International Nuclear Information System (INIS)

    Zhu Kuiying; Qian Qinsong; Zhu Jing; Sun Weifeng

    2010-01-01

    The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology. (semiconductor devices)

  14. Numerical study of self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride substrate

    International Nuclear Information System (INIS)

    Ding Yanfang; Zhu Ziqiang; Zhu Ming; Lin Chenglu

    2006-01-01

    Compared with bulk-silicon technology, silicon-on-insulator (SOI) technology possesses many advantages but it is inevitable that the buried silicon dioxide layer also thermally insulates the metal-oxide-silicon field-effect transistors (MOSFETs) from the bulk due to the low thermal conductivity. One of the alternative insulator to replace the buried oxide layer is aluminum nitride (MN), which has a thermal conductivity that is about 200 times higher than that of SiO 2 (320 W·m -1 ·K -1 versus 1.4 W·m -1 ·K -l ). To investigate the self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride (SOAN) substrate, a two-dimensional numerical analysis is performed by using a device simulator called MEDICI run on a Solaris workstation to simulate the electrical characteristics and temperature distribution by comparing with those of bulk and standard SOI MOSFETs. Our study suggests that AIN is a suitable alternative to silicon dioxide as a buried dielectric in SOI and expands the applications of SOI to high temperature conditions. (authors)

  15. 300 nm bandwidth adiabatic SOI polarization splitter-rotators exploiting continuous symmetry breaking.

    Science.gov (United States)

    Socci, Luciano; Sorianello, Vito; Romagnoli, Marco

    2015-07-27

    Adiabatic polarization splitter-rotators are investigated exploiting continuous symmetry breaking thereby achieving significant device size and losses reduction in a single mask fabrication process for both SOI channel and ridge waveguides. A crosstalk lower than -25 dB is expected over 300nm bandwidth, making the device suitable for full grid CWDM and diplexer/triplexer FTTH applications at 1310, 1490 and 1550nm.

  16. Fabrication of nanopores in multi-layered silicon-based membranes using focused electron beam induced etching with XeF_2 gas

    International Nuclear Information System (INIS)

    Liebes-Peer, Yael; Bandalo, Vedran; Sökmen, Ünsal; Tornow, Marc; Ashkenasy, Nurit

    2016-01-01

    The emergent technology of using nanopores for stochastic sensing of biomolecules introduces a demand for the development of simple fabrication methodologies of nanopores in solid state membranes. This process becomes particularly challenging when membranes of composite layer architecture are involved. To overcome this challenge we have employed a focused electron beam induced chemical etching process. We present here the fabrication of nanopores in silicon-on-insulator based membranes in a single step process. In this process, chemical etching of the membrane materials by XeF_2 gas is locally accelerated by an electron beam, resulting in local etching, with a top membrane oxide layer preventing delocalized etching of the silicon underneath. Nanopores with a funnel or conical, 3-dimensional (3D) shape can be fabricated, depending on the duration of exposure to XeF_2, and their diameter is dominated by the time of exposure to the electron beam. The demonstrated ability to form high-aspect ratio nanopores in comparably thick, multi-layered silicon based membranes allows for an easy integration into current silicon process technology and hence is attractive for implementation in biosensing lab-on-chip fabrication technologies. (author)

  17. Design, fabrication and characterization of a two-step released silicon dioxide piezoresistive microcantilever immunosensor

    International Nuclear Information System (INIS)

    Zhou, Youzheng; Wang, Zheyao; Wang, Chaonan; Ruan, Wenzhou; Liu, Litian

    2009-01-01

    This paper presents the design, fabrication and characterization of a silicon dioxide piezoresistive microcantilever immunosensor fabricated on silicon-on-insulator (SOI) wafers. The microcantilever consists of two strips of single crystalline silicon piezoresistors sandwiched in between two silicon dioxide layers. A theoretical model for the laminated microcantilever with a discontinuous layer is deduced using classic laminated beam theory. A two-step release method combining anisotropic and isotropic etching is developed to suspend the microcantilever, and the fabrication results show an excellent yield. The residual stress-induced free bending of the microcantilever and the stress caused by self-heating of the piezoresistors are discussed. The microcantilever sensor is characterized as an immunosensor using specific binding of antigen and antibody. These methods and some conclusions are also applicable to the development of other piezoresistive sensors that use laminated structures

  18. Test of the TRAPPISTe monolithic detector system

    Science.gov (United States)

    Soung Yee, L.; Álvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

    2013-12-01

    A monolithic pixel detector named TRAPPISTe-2 has been developed in Silicon-on-Insulator (SOI) technology. A p-n junction is implanted in the bottom handle wafer and connected to readout electronics integrated in the top active layer. The two parts are insulated from each other by a buried oxide layer resulting in a monolithic detector. Two small pixel matrices have been fabricated: one containing a 3-transistor readout and a second containing a charge sensitive amplifier readout. These two readout structures have been characterized and the pixel matrices were tested with an infrared laser source. The readout circuits are adversely affected by the backgate effect, which limits the voltage that can be applied to the metal back plane to deplete the sensor, thus narrowing the depletion width of the sensor. Despite the low depletion voltages, the integrated pixel matrices were able to respond to and track a laser source.

  19. A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

    International Nuclear Information System (INIS)

    Patil, Ganesh C; Qureshi, S

    2011-01-01

    In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB

  20. Sensitivity Enhancement in Si Nanophotonic Waveguides Used for Refractive Index Sensing

    Directory of Open Access Journals (Sweden)

    Yaocheng Shi

    2016-03-01

    Full Text Available A comparative study is given for the sensitivity of several typical Si nanophotonic waveguides, including SOI (silicon-on-insulator nanowires, nanoslot waveguides, suspended Si nanowires, and nanofibers. The cases for gas sensing (ncl ~ 1.0 and liquid sensing (ncl ~ 1.33 are considered. When using SOI nanowires (with a SiO2 buffer layer, the sensitivity for liquid sensing (S ~ 0.55 is higher than that for gas sensing (S ~ 0.35 due to lower asymmetry in the vertical direction. By using SOI nanoslot waveguides, suspended Si nanowires, and Si nanofibers, one could achieve a higher sensitivity compared to sensing with a free-space beam (S = 1.0. The sensitivity for gas sensing is higher than that for liquid sensing due to the higher index-contrast. The waveguide sensitivity of an optimized suspended Si nanowire for gas sensing is as high as 1.5, which is much higher than that of a SOI nanoslot waveguide. Furthermore, the optimal design has very large tolerance to the core width variation due to the fabrication error (∆w ~ ±50 nm. In contrast, a Si nanofiber could also give a very high sensitivity (e.g., ~1.43 while the fabrication tolerance is very small (i.e., ∆w < ±5 nm. The comparative study shows that suspended Si nanowire is a good choice to achieve ultra-high waveguide sensitivity.

  1. Electrical characteristics of SiGe-base bipolar transistors on thin-film SOI substrates

    International Nuclear Information System (INIS)

    Liao, Shu-Hui; Chang, Shu-Tong

    2010-01-01

    This paper, based on two-dimensional simulations, provides a comprehensive analysis of the electrical characteristics of the Silicon germanium (SiGe)-base bipolar transistors on thin-film siliconon-insulator (SOI) substrates. The impact of the buried oxide thickness (T OX ), the emitter width (W E ), and the lateral distance between the edge of the intrinsic base and the reach-through region (L col ) on both the AC and DC device characteristics was analyzed in detail. Regarding the DC characteristics, the simulation results suggest that a thicker T OX gives a larger base-collector breakdown voltage (BV CEO ), whereas reducing the T OX leads to an enhanced maximum electric field at the B-C junction. As for the AC characteristics, cut-off frequency (f T ) increases slightly with increasing buried oxide thickness and finally saturates to a constant value when the buried oxide thickness is about 0.15 μm. The collector-substrate capacitance (C CS ) decreases with increasing buried oxide thickness while the maximum oscillation frequency (f max ) increases with increasing buried oxide thickness. Furthermore, the impact of self-heating effects in the device was analyzed in various areas. The thermal resistance as a function of the buried oxide thickness indicates that the thermal resistance of the SiGe-base bipolar transistor on a SOI substrate is slightly higher than that of a bulk SiGe-base bipolar transistor. The thermal resistance is reduced by ∼37.89% when the emitter width is increased by a factor of 5 for a fixed buried oxide thickness of 0.1 μm. All the results can be used to design and optimize SiGe-base bipolar transistors on SOI substrates with minimum thermal resistance to enhance device performance.

  2. A New Nonlinear Model of Body Resistance in Nanometer PD SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    Arash Daghighi

    2011-01-01

    Full Text Available In this paper, a nonlinear model for the body resistance of a 45nm PD SOI MOSFET is developed. This model verified on the base of the small signal three-dimensional simulation results. In this paper by using the three-dimensional simulation of ISE-TCAD software, the indicating factors of body resistance in nanometer transistors and then are shown, using the surface potential model. A mathematical relation to calculat the body resistance incorporating device width and body potential was derived. Excellent agreement was obtained by comparing the model outputs and three-dimensional simulation results.

  3. A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

    International Nuclear Information System (INIS)

    Guo Yufeng; Wang Zhigong; Sheu Gene

    2009-01-01

    This paper presents an analytical three-dimensional breakdown model of SOI lateral power devices with a circular layout. The Poisson equation is solved in cylindrical coordinates to obtain the radial surface potential and electric field distributions for both fully- and partially-depleted drift regions. The breakdown voltages for N + N and P + N junctions are derived and employed to investigate the impact of cathode region curvature. A modified RESURF criterion is proposed to provide a design guideline for optimizing the breakdown voltage and doping concentration in the drift region in three dimensional space. The analytical results agree well with MEDICI simulation results and experimental data from earlier publications. (semiconductor devices)

  4. Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

    International Nuclear Information System (INIS)

    Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

    1998-01-01

    Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

  5. A monolithic pixel sensor (TRAPPISTe-2) for particle physics instrumentation in OKI 0.2μm SOI technology

    Science.gov (United States)

    Soung Yee, L.; Alvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

    2012-12-01

    A monolithic active pixel sensor for charged particle tracking has been developed within the frame of a research and development project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology). TRAPPISTe aims to study the feasibility of developing a monolithic pixel sensor with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with an OKI 0.20μm fully depleted (FD-SOI) CMOS process. This device contains test transistors and amplifiers, as well as two pixel matrices with integrated 3-transistor and amplifier readout electronics. The results presented are based on the first electrical measurements performed on the test structures and laser measurements on the pixel matrices.

  6. Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

    Science.gov (United States)

    Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.

    2009-12-01

    The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.

  7. Evaluation of custom-designed lateral power transistors in a silicon-on-insulator process in a synchronous buck converter

    DEFF Research Database (Denmark)

    Okumus, Sinan; Fan, Lin; Nour, Yasser

    2018-01-01

    Most of todays power converters are based on power semiconductors, which are built in vertical power semiconductor processes. These devices result in limited packaging possibilities, which lead to physically long galvanic connections and therefore high external electromagnetic fields. These fields...

  8. Design of photonic phased array switches using nano electromechanical systems on silicon-on-insulator integration platform

    Science.gov (United States)

    Hussein, Ali Abdulsattar

    This thesis presents an introduction to the design and simulation of a novel class of integrated photonic phased array switch elements. The main objective is to use nano-electromechanical (NEMS) based phase shifters of cascaded under-etched slot nanowires that are compact in size and require a small amount of power to operate them. The structure of the switch elements is organized such that it brings the phase shifting elements to the exterior sides of the photonic circuits. The transition slot couplers, used to interconnect the phase shifters, are designed to enable biasing one of the silicon beams of each phase shifter from an electrode located at the side of the phase shifter. The other silicon beam of each phase shifter is biased through the rest of the silicon structure of the switch element, which is taken as a ground. Phased array switch elements ranging from 2x2 up to 8x8 multiple-inputs/multiple-outputs (MIMO) are conveniently designed within reasonable footprints native to the current fabrication technologies. Chapter one presents the general layout of the various designs of the switch elements and demonstrates their novel features. This demonstration will show how waveguide disturbances in the interconnecting network from conventional switch elements can be avoided by adopting an innovative design. Some possible applications for the designed switch elements of different sizes and topologies are indicated throughout the chapter. Chapter two presents the design of the multimode interference (MMI) couplers used in the switch elements as splitters, combiners and waveguide crossovers. Simulation data and design methodologies for the multimode couplers of interest are detailed in this chapter. Chapter three presents the design and analysis of the NEMS-operated phase shifters. Both simulations and numerical analysis are utilized in the design of a 0°-180° capable NEMS-operated phase shifter. Additionally, the response of some of the designed photonic phased array switch elements is demonstrated in this chapter. An executive summary and conclusions sections are also included in the thesis.

  9. Electrostatically Tunable Nanomechanical Shallow Arches

    KAUST Repository

    Kazmi, Syed N. R.

    2017-11-03

    We report an analytical and experimental study on the tunability of in-plane doubly-clamped nanomechanical arches under varied DC bias conditions at room temperature. For this purpose, silicon based shallow arches are fabricated using standard e-beam lithography and surface nanomachining of a highly conductive device layer on a silicon-on-insulator (SOI) wafer. The experimental results show good agreement with the analytical results with a maximum tunability of 108.14% for 180 nm thick arch with a transduction gap of 1 μm between the beam and the driving/sensing electrodes. The high tunability of shallow arches paves the ways for highly tunable band pass filtering applications in high frequency range.

  10. Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

    Science.gov (United States)

    Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

    2018-04-01

    The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

  11. Towards in-situ tem analysis of PLD Pb(Zr,Ti)O3 thin film membranes

    NARCIS (Netherlands)

    Sardan Sukas, Ö.; Berenschot, Johan W.; de Boer, Meint J.; Nguyen, Duc Minh; van Zalk, M.; Abelmann, Leon

    2011-01-01

    In this paper, a novel technique for fabricating Transmission Electron Microscopy (TEM) chips for investigating structural and piezoelectric properties of Pulse Laser Deposited (PLD) Lead Zirconium Titanate (PZT) thin films is presented. The method involves silicon-on-insulator (SOI) wafer

  12. Arbitrary waveform generator and differentiator employing an integrated optical pulse shaper

    DEFF Research Database (Denmark)

    Liao, Shasha; Ding, Yunhong; Dong, Jianji

    2015-01-01

    We propose and demonstrate an optical arbitrary waveformgenerator and high-order photonic differentiator based on a four-tap finiteimpulse response (FIR) silicon-on-insulator (SOI) on-chip circuit. Based onamplitude and phase modulation of each tap controlled by thermal heaters,we obtain several...

  13. Modal analysis and modeling of a frictionless electrostatic rotary stepper micromotor

    NARCIS (Netherlands)

    Stranczl, M.; Sarajlic, Edin; Krijnen, Gijsbertus J.M.; Fujita, H.; Gijs, M.A.M.; Yamahata, C.

    2011-01-01

    We present the design, modeling and characterization of a 3-phase electrostatic rotary stepper micromotor. The proposed motor is a monolithic device fabricated using silicon-on-insulator (SOI) technology. The rotor is suspended with a frictionless flexural pivot bearing and reaches an unprecedented

  14. Lead-free (K0.5Na0.5)NbO3 thin films by pulsed laser deposition driving MEMS-based piezoelectric cantilevers

    NARCIS (Netherlands)

    Nguyen, Duc Minh; Dekkers, Jan M.; Houwman, Evert Pieter; Vu, H.T.; Vu, Hung N.; Rijnders, Augustinus J.H.M.

    2016-01-01

    Thin film capacitors of the lead-free (K0.5Na0.5)NbO3 (KNN) with (100) orientation were grown on Pt/Ti/SiO2/SOI (silicon-on-insulator) substrates by pulsed laser deposition. The films are pure phases and do not show other crystal orientations. The remnant polarization Pr, saturation polarization

  15. Deep Reactive Ion Etching for High Aspect Ratio Microelectromechanical Components

    DEFF Research Database (Denmark)

    Jensen, Søren; Yalcinkaya, Arda Deniz; Jacobsen, S.

    2004-01-01

    A deep reactive ion etch (DRIE) process for fabrication of high aspect ratio trenches has been developed. Trenches with aspect ratios exceeding 20 and vertical sidewalls with low roughness have been demonstrated. The process has successfully been used in the fabrication of silicon-on-insulator (SOI...

  16. Near-field characterization of photonic crystal Y-splitters

    DEFF Research Database (Denmark)

    Volkov, V. S.; Bozhevolnyi, S. I.; Borel, Peter Ingo

    2005-01-01

    A scanning near-field optical microscope (SNOM) is used to directly map the propagation of light in a specially designed 50/50 photonic crystal (PC) Y-splitter fabricated on silicon-on-insulator (SOI) wafers. SNOM images are obtained for TE- and TM-polarized light in the wavelength range 1425...

  17. Characterization of ultrathin SOI film and application to short channel MOSFETs.

    Science.gov (United States)

    Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

    2008-04-23

    In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

  18. Total dose induced latch in short channel NMOS/SOI transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

    1998-01-01

    A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

  19. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    Energy Technology Data Exchange (ETDEWEB)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  20. Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits; Quantification, modelisation et conception prenant en compte les etats anterieurs des signaux dans les circuits mixtes SOI/SOS

    Energy Technology Data Exchange (ETDEWEB)

    Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S. [Southampton Univ., Dept. of Electronics and Computer Sciences (United Kingdom); Uren, M.J.; Brunson, K.M. [DERA Farnborough, GU, Hants (United Kingdom)

    1999-07-01

    This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

  1. Increased carrier lifetimes in epitaxial silicon layers on buried silicon nitride produced by ion implantation

    International Nuclear Information System (INIS)

    Skorupa, W.; Kreissig, U.; Hensel, E.; Bartsch, H.

    1984-01-01

    Carrier lifetimes were measured in epitaxial silicon layers deposited on buried silicon nitride produced by high-dose nitrogen implantation at 330 keV. The values were in the range 20-200 μs. The results are remarkable taking into account the high density of crystal defects in the epitaxial layers. Comparing with other SOI technologies the measured lifetimes are higher by 1-2 orders of magnitude. (author)

  2. Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits

    International Nuclear Information System (INIS)

    Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S.; Uren, M.J.; Brunson, K.M.

    1999-01-01

    This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

  3. Novel high-voltage power lateral MOSFET with adaptive buried electrodes

    International Nuclear Information System (INIS)

    Zhang Wen-Tong; Wu Li-Juan; Qiao Ming; Luo Xiao-Rong; Zhang Bo; Li Zhao-Ji

    2012-01-01

    A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and −587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  4. Growth and characterization of InP/GaAs on SOI by MOCVD

    International Nuclear Information System (INIS)

    Karam, N.H.; Haven, V.; Vernon, S.M.; Namavar, F.; El-Masry, N.; Haegel, N.; Al-Jassin, M.M.

    1990-01-01

    This paper reports that epitaxial InP films have been successfully deposited on GaAs coated silicon wafers with a buried oxide for the first time by MOCVD. The SOI wafers were prepared using the Separation by Implantation of Oxygen (SIMOX) process. The quality of InP on SIMOX is comparable to the best of InP on Si deposited in the same reactor. Preliminary results on defect reduction techniques such as Thermal Cycle Growth (TCG) show an order of magnitude increase in the photoluminescence intensity and a factor of five reduction in the defect density. TCG has been found more effective than Thermal Cycle Annealing (TCA) in improving the crystalline perfection and optical properties of the deposited films

  5. Universal trench design method for a high-voltage SOI trench LDMOS

    Institute of Scientific and Technical Information of China (English)

    Hu Xiarong; Zhang Bo; Luo Xiaorong; Li Zhaoji

    2012-01-01

    The design method for a high-voltage SOl trench LDMOS for various trench permittivities,widths and depths is introduced.A universal method for efficient design is presented for the first time,taking the trade-off between breakdown voltage (BV) and specific on-resistance (Rs,on) into account.The high-k (relative permittivity)dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench.An SOI LDMOS with a vacuum trench in the drift region is also discussed.Simulation results show that the high FOM BV2/Rs,on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

  6. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    International Nuclear Information System (INIS)

    Trimpl, M.; Deptuch, G.; Yarema, R.

    2010-01-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm 2 large detector array with 20 (micro)m and 40 (micro)m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  7. Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

    International Nuclear Information System (INIS)

    Dehzangi, Arash; Larki, Farhad; Naseri, Mahmud G.; Navasery, Manizheh; Majlis, Burhanuddin Y.; Razip Wee, Mohd F.; Halimah, M.K.; Islam, Md. Shabiul; Md Ali, Sawal H.; Saion, Elias

    2015-01-01

    Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated

  8. Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

    Energy Technology Data Exchange (ETDEWEB)

    Dehzangi, Arash, E-mail: arashd53@hotmail.com [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Larki, Farhad [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Naseri, Mahmud G. [Department of Physics, Faculty of Science, Malayer University, Malayer, Hamedan (Iran, Islamic Republic of); Navasery, Manizheh [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Majlis, Burhanuddin Y.; Razip Wee, Mohd F. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Halimah, M.K. [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Islam, Md. Shabiul; Md Ali, Sawal H. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Saion, Elias [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia)

    2015-04-15

    Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated.

  9. Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

    Directory of Open Access Journals (Sweden)

    Gammon P.M.

    2017-01-01

    Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

  10. Broadband non-polarizing beam splitter based on guided mode resonance effect

    International Nuclear Information System (INIS)

    Ma Jian-Yong; Xu Cheng; Qiang Ying-Huai; Zhu Ya-Bo

    2011-01-01

    A broadband non-polarizing beam splitter (NPBS) operating in the telecommunication C+L band is designed by using the guided mode resonance effect of periodic silicon-on-insulator (SOI) elements. It is shown that this double layer SOI structure can provide ∼50/50 beam ratio with the maximum divergences between reflection and transmission being less than 8% over the spectrum of 1.4 μm∼1.7 μm and 1% in the telecommunication band for both TE and TM polarizations. The physical basis of this broadband non-polarizing property is on the simultaneous excitation of the TE and TM strong modulation waveguide modes near the designed spectrum band. Meanwhile, the electric field distributions for both TE and TM polarizations verify the resonant origin of spectrum in the periodic SOI structure. Furthermore, it is demonstrated with our calculations that the beam splitter proposed here is tolerant to the deviations of incident angle and structure parameters, which make it very easy to be fabricated with current IC technology. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  11. Broadband non-polarizing beam splitter based on guided mode resonance effect

    Science.gov (United States)

    Ma, Jian-Yong; Xu, Cheng; Qiang, Ying-Huai; Zhu, Ya-Bo

    2011-10-01

    A broadband non-polarizing beam splitter (NPBS) operating in the telecommunication C+L band is designed by using the guided mode resonance effect of periodic silicon-on-insulator (SOI) elements. It is shown that this double layer SOI structure can provide ~50/50 beam ratio with the maximum divergences between reflection and transmission being less than 8% over the spectrum of 1.4 μm~1.7 μm and 1% in the telecommunication band for both TE and TM polarizations. The physical basis of this broadband non-polarizing property is on the simultaneous excitation of the TE and TM strong modulation waveguide modes near the designed spectrum band. Meanwhile, the electric field distributions for both TE and TM polarizations verify the resonant origin of spectrum in the periodic SOI structure. Furthermore, it is demonstrated with our calculations that the beam splitter proposed here is tolerant to the deviations of incident angle and structure parameters, which make it very easy to be fabricated with current IC technology.

  12. Jean-Pierre Famose et Jean Bertsch, L’estime de soi : une controverse éducative, Paris, PUF, 2009, 192 p

    OpenAIRE

    Benamar, Aïcha

    2015-01-01

    L’ouvrage porte sur l’estime de soi, dans la sphère sociale en général et le monde éducatif en particulier. L’estime de soi est au cœur du comportement individuel, apportant confiance et assurance, permettant de progresser et in fine de réussir. Une faible estime de soi est fréquemment à l’origine de difficultés pour un individu : doutes, hésitations, ou à l’inverse vanité et arrogance. Un bon niveau d’estime de soi confère à la personnalité : capacité à s’affirmer et respect des autres. Cent...

  13. Physical and electrical characterization of corundum substrates and epitaxial silicon layers in view of fabricating integrated circuits

    International Nuclear Information System (INIS)

    Trilhe, J.; Legal, H.; Rolland, G.

    1975-01-01

    The S.O.S. technology (silicon on insulating substrate) allows compact, radiation hard, fast integrated circuits to be fabricated. It is noticeable that complex integrated circuits on corundum substrates obtained with various fabrication processes have various electrical characteristics. Possible correlations between the macroscopic defects of the substrate and the electrical characteristics of the circuit were investigated [fr

  14. Boron impurity at the Si/SiO2 interface in SOI wafers and consequences for piezoresistive MEMS devices

    International Nuclear Information System (INIS)

    Nafari, A; Karlen, D; Enoksson, P; Rusu, C; Svensson, K

    2009-01-01

    In this work, the electrical performance of piezoresistive devices fabricated on thinned SOI wafers has been investigated. Specifically, SOI wafers manufactured with the standard bond-and-etch back method (BESOI), commonly used for MEMS fabrication, have been studied. Results from electrical measurements and SIMS characterization show the presence of a boron impurity close to the buried oxide, even on unprocessed wafers. If the boron impurity overlaps with the piezoresistors on the device, it can create non-defined pn-junctions and thus allow conduction through the substrate, leading to stray connections and excessive noise. The thickness of the boron impurity can extend up to several µm, thus setting a thickness limit for the thinnest parts of a MEMS device. This work shows how this impurity can fundamentally affect the functionality of piezoresistive devices. Design rules of how to avoid this are presented

  15. Comparison of short-circuit characteristics of trench gate and planar gate U-shaped channel SOI-LIGBTs

    Science.gov (United States)

    Zhang, Long; Zhu, Jing; Sun, Weifeng; Zhao, Minna; Huang, Xuequan; Chen, Jiajun; Shi, Longxing; Chen, Jian; Ding, Desheng

    2017-09-01

    Comparison of short-circuit (SC) characteristics of 500 V rated trench gate U-shaped channel (TGU) SOI-LIGBT and planar gate U-shaped channel (PGU) SOI-LIGBT is made for the first time in this paper. The on-state carrier profile of the TGU structure is reshaped by the dual trenches (a gate trench G1 and a hole barrier trench G2), which leads to a different conduction behavior from that of the PGU structure. The TGU structure exhibits a higher latchup immunity but a severer self-heating effect. At current density (JC) 640 A/cm2. Comparison of layouts and fabrication processes are also made between the two types of devices.

  16. Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

  17. An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

    Science.gov (United States)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2016-10-01

    This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.

  18. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.; Deptuch, G.; Yarema, R.; /Fermilab

    2010-11-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm{sup 2} large detector array with 20 {micro}m and 40 {micro}m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  19. Compact Si-based asymmetric MZI waveguide on SOI as a thermo-optical switch

    Science.gov (United States)

    Rizal, C. S.; Niraula, B.

    2018-03-01

    A compact low power consuming asymmetric MZI based optical modulator with fast response time has been proposed on SOI platform. The geometrical and performance characteristics were analyzed in depth and optimized using coupled mode analysis and FDTD simulation tools, respectively. It was tested with and without implementation of thermo-optic (TO) effect. The device showed good frequency modulating characteristics when tested without the implementation of the TO effect. The fabricated device showed quality factor, Q ≈ 10,000, and this value is comparable to the Q of the device simulated with 25% transmission loss, showing FSR of 0.195 nm, FWHM ≈ 0.16 nm, and ER of 13 dB. With TO effect, it showed temperature sensitivity of 0.01 nm/°C and FSR of 0.19 nm. With the heater length of 4.18 mm, the device required 0.26 mW per π shift power with a switching voltage of 0.309 V, response time of 10 μ, and figure-of-merit of 2.6 mW μs. All of these characteristics make this device highly attractive for use in integrated Si photonics network as optical switch and wavelength modulator.

  20. Design and fabrication of two kind of SOI-based EA-type VOAs

    Science.gov (United States)

    Yuan, Pei; Wang, Yue; Wu, Yuanda; An, Junming; Hu, Xiongwei

    2018-06-01

    SOI-based variable optical attenuators based on electro-absorption mechanism are demonstrated in this paper. Two different doping structures are adopted to realize the attenuation: a structure with a single lateral p-i-n diode and a structure with several lateral p-i-n diodes connected in series. The VOAs with lateral p-i-n diodes connected in series (series VOA) can greatly improve the device attenuation efficiency compared to VOAs with a single lateral p-i-n diode structure (single VOA), which is verified by the experimental results that the attenuation efficiency of the series VOA and the single VOA is 3.76 dB/mA and 0.189 dB/mA respectively. The corresponding power consumption at 20 dB attenuation is 202 mW (series VOA) and 424 mW (single VOA) respectively. The raise time is 34.5 ns (single VOA) and 45.5 ns (series VOA), and the fall time is 37 ns (single VOA) and 48.5 ns (series VOA).

  1. High temperature piezoresistive {beta}-SiC-on-SOI pressure sensor for combustion engines

    Energy Technology Data Exchange (ETDEWEB)

    Berg, J. von; Ziermann, R.; Reichert, W.; Obermeier, E. [Tech. Univ. Berlin (Germany). Microsensor and Actuator Technol. Center; Eickhoff, M.; Kroetz, G. [Daimler Benz AG, Munich (Germany); Thoma, U.; Boltshauser, T.; Cavalloni, C. [Kistler Instrumente AG, Winterthur (Switzerland); Nendza, J.P. [TRW Deutschland GmbH, Barsinghausen (Germany)

    1998-08-01

    For measuring the cylinder pressure in combustion engines of automobiles a high temperature pressure sensor has been developed. The sensor is made of a membrane based piezoresistive {beta}-SiC-on-SOI (SiCOI) sensor chip and a specially designed housing. The SiCOI sensor was characterized under static pressures of up to 200 bar in the temperature range between room temperature and 300 C. The sensitivity of the sensor at room temperature is approximately 0.19 mV/bar and decreases to about 0.12 mV/bar at 300 C. For monitoring the dynamic cylinder pressure the sensor was placed into the combustion chamber of a gasoline engine. The measurements were performed at 1500 rpm under different loads, and for comparison a quartz pressure transducer from Kistler AG was used as a reference. The maximum pressure at partial load operation amounts to about 15 bar. The difference between the calibrated SiCOI sensor and the reference sensor is significantly less than 1 bar during the whole operation. (orig.) 8 refs.

  2. Development of monolithic pixel detector with SOI technology for the ILC vertex detector

    Science.gov (United States)

    Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

    2018-01-01

    We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

  3. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    International Nuclear Information System (INIS)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

    2015-01-01

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10 −9 of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved

  4. Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

    Energy Technology Data Exchange (ETDEWEB)

    Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia (UKM), 43600 UKM Bangi, Selangor (Malaysia)

    2015-04-24

    Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device was then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10{sup −9} of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.

  5. Athermal and wavelength-trimmable photonic filters based on TiO₂-cladded amorphous-SOI.

    Science.gov (United States)

    Lipka, Timo; Moldenhauer, Lennart; Müller, Jörg; Trieu, Hoc Khiem

    2015-07-27

    Large-scale integrated silicon photonic circuits suffer from two inevitable issues that boost the overall power consumption. First, fabrication imperfections even on sub-nm scale result in spectral device non-uniformity that require fine-tuning during device operation. Second, the photonic devices need to be actively corrected to compensate thermal drifts. As a result significant amount of power is wasted if no athermal and wavelength-trimmable solutions are utilized. Consequently, in order to minimize the total power requirement of photonic circuits in a passive way, trimming methods are required to correct the device inhomogeneities from manufacturing and athermal solutions are essential to oppose temperature fluctuations of the passive/active components during run-time. We present an approach to fabricate CMOS backend-compatible and athermal passive photonic filters that can be corrected for fabrication inhomogeneities by UV-trimming based on low-loss amorphous-SOI waveguides with TiO2 cladding. The trimming of highly confined 10 μm ring resonators is proven over a free spectral range retaining athermal operation. The athermal functionality of 2nd-order 5 μm add/drop microrings is demonstrated over 40°C covering a broad wavelength interval of 60 nm.

  6. Analysis of the rectangular resonator with butterfly MMI coupler using SOI

    Science.gov (United States)

    Kim, Sun-Ho; Park, Jun-Hee; Kim, Eudum; Jeon, Su-Jin; Kim, Ji-Hoon; Choi, Young-Wan

    2018-02-01

    We propose a rectangular resonator sensor structure with butterfly MMI coupler using SOI. It consists of the rectangular resonator, total internal reflection (TIR) mirror, and the butterfly MMI coupler. The rectangular resonator is expected to be used as bio and chemical sensors because of the advantages of using MMI coupler and the absence of bending loss unlike ring resonators. The butterfly MMI coupler can miniaturize the device compared to conventional MMI by using a linear butterfly shape instead of a square in the MMI part. The width, height, and slab height of the rib type waveguide are designed to be 1.5 μm, 1.5 μm, and 0.9 μm, respectively. This structure is designed as a single mode. When designing a TIR mirror, we considered the Goos-Hänchen shift and critical angle. We designed 3:1 MMI coupler because rectangular resonator has no bending loss. The width of MMI is designed to be 4.5 μm and we optimize the length of the butterfly MMI coupler using finite-difference time-domain (FDTD) method for higher Q-factor. It has the equal performance with conventional MMI even though the length is reduced by 1/3. As a result of the simulation, Qfactor of rectangular resonator can be obtained as 7381.

  7. On substrate dopant engineering for ET-SOI MOSFETs with UT-BOX

    International Nuclear Information System (INIS)

    Wu Hao; Xu Miao; Wan Guangxing; Zhu Huilong; Zhao Lichuan; Tong Xiaodong; Zhao Chao; Chen Dapeng; Ye Tianchun

    2014-01-01

    The importance of substrate doping engineering for extremely thin SOI MOSFETs with ultra-thin buried oxide (ES-UB-MOSFETs) is demonstrated by simulation. A new substrate/backgate doping engineering, lateral non-uniform dopant distributions (LNDD) is investigated in ES-UB-MOSFETs. The effects of LNDD on device performance, V t -roll-off, channel mobility and random dopant fluctuation (RDF) are studied and optimized. Fixing the long channel threshold voltage (V t ) at 0.3 V, ES-UB-MOSFETs with lateral uniform doping in the substrate and forward back bias can scale only to 35 nm, meanwhile LNDD enables ES-UB-MOSFETs to scale to a 20 nm gate length, which is 43% smaller. The LNDD degradation is 10% of the carrier mobility both for nMOS and pMOS, but it is canceled out by a good short channel effect controlled by the LNDD. Fixing V t at 0.3 V, in long channel devices, due to more channel doping concentration for the LNDD technique, the RDF in LNDD controlled ES-UB-MOSFETs is worse than in back-bias controlled ES-UB-MOSFETs, but in the short channel, the RDF for LNDD controlled ES-UB-MOSFET is better due to its self-adaption of substrate doping engineering by using a fixed thickness inner-spacer. A novel process flow to form LNDD is proposed and simulated. (semiconductor devices)

  8. Line-edge roughness induced single event transient variation in SOI FinFETs

    International Nuclear Information System (INIS)

    Wu Weikang; An Xia; Jiang Xiaobo; Chen Yehua; Liu Jingjing; Zhang Xing; Huang Ru

    2015-01-01

    The impact of process induced variation on the response of SOI FinFET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When FinFET biased at OFF state configuration (V gs = 0, V ds = V dd ) is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse (single event transient, SET) is consequently formed. The results reveal that with the presence of line-edge roughness (LER), which is one of the major variation sources in nano-scale FinFETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered: type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters, correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size. (paper)

  9. The fabrication and characterization of organic light-emitting diodes using transparent single-crystal Si membranes

    International Nuclear Information System (INIS)

    Lee, Su-Hwan; Kim, Dal-Ho; Kim, Ji-Heon; Lee, Gon-Sub; Park, Jea-Gun; Takeo, Katoh

    2009-01-01

    For applications such as solar cells and displays, transparent single-crystal Si membranes were fabricated on a silicon-on-insulator (SOI) wafer. The SOI wafer included a buried layer of SiO 2 and Si 3 N 4 as an etch-stop layer. The etch-stop layer enabled fabrication of transparent single-crystal Si membranes with various thicknesses, and the thinning technology is described. For membranes with thicknesses of 18, 72 and 5000 nm, the respective optical transparent were 96.9%, 93.7% and 9% for R (red, λ = 660 nm), 96.9%, 91.4% and 1% for G (green, λ = 525 nm), and 97.0%, 93.2% and 0% for B (blue, λ = 470 nm). Organic light-emitting diodes (OLEDs) were then fabricated on transparent single-crystal Si membranes with various top Si thicknesses. OLEDs fabricated on 18, 72 and 5000 nm thick membranes and operated at 6 V demonstrated a luminance of 1350, 443 and 27 cd m -2 at the current densities of 148, 131 and 1.5 mA cm -2 , respectively.

  10. Amorphous silicon as high index photonic material

    Science.gov (United States)

    Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

    2009-05-01

    Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

  11. Nanogap biosensors for electrical and label-free detection of biomolecular interactions

    International Nuclear Information System (INIS)

    Kyu Kim, Sang; Cho, Hyunmin; Park, Hye-Jung; Kwon, Dohyoung; Min Lee, Jeong; Hyun Chung, Bong

    2009-01-01

    We demonstrate nanogap biosensors for electrical and label-free detection of biomolecular interactions. Parallel fabrication of nanometer distance gaps has been achieved using a silicon anisotropic wet etching technique on a silicon-on-insulator (SOI) wafer with a finely controllable silicon device layer. Since silicon anisotropic wet etching resulted in a trapezoid-shaped structure whose end became narrower during the etching, the nanogap structure was simply fabricated on the device layer of a SOI wafer. The nanogap devices were individually addressable and a gap size of less than 60 nm was obtained. We demonstrate that the nanogap biosensors can electrically detect biomolecular interactions such as biotin/streptavidin and antigen/antibody pairs. The nanogap devices show a current increase when the proteins are bound to the surface. The current increases proportionally depending upon the concentrations of the molecules in the range of 100 fg ml -1 -100 ng ml -1 at 1 V bias. It is expected that the nanogap developed here could be a highly sensitive biosensor platform for label-free detection of biomolecular interactions.

  12. InP on SOI devices for optical communication and optical network on chip

    Science.gov (United States)

    Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

    2011-01-01

    For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

  13. Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

    International Nuclear Information System (INIS)

    Kranti, Abhinav; Hao Ying; Armstrong, G Alastair

    2008-01-01

    In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (I on /I off ). Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices

  14. Blog : un journal intime comme mémoire de soi

    Directory of Open Access Journals (Sweden)

    Nolwenn Hénaff

    2011-08-01

    Full Text Available Tenir un journal est devenu, pour un individu, une manière possible de vivre, ou d’accompagner un moment de sa vie (Lejeune, 2006. Les usages sont donc multiples : construction d’une identité narrative, fixation du temps, libération du moi, introspection, outil de contrôle, de soutien, méthode d’organisation de la pensée, plaisir d’écrire. Si l’écriture papier reste la forme la plus courante du récit biographique, d’autres supports médiatiques comme la télévision ou la radio sont venus offrir de nouveaux terrains d’expérimentation de ces récits de soi. Plus récemment, l’avènement d’Internet et de ses outils simplifiés de publication ont fait émerger des formes biographiques innovantes. Pourtant, qu’il s’agisse de traverser une crise, de garder la mémoire d’une expérience forte, ou, plus ordinairement, de relater ses vacances et ses voyages, le journal se positionne avant tout, et résolument, comme un espace de liberté : on écrit quand on veut, comme on veut. Le « Souci de soi » comme dirait Foucault, l’espace dominé par les sensations, et la temporalité marquée par la notion d’instants, de moments ayant une connotation expressément personnelle sont autant d’indices révélant la pratique de l’écriture intime en ligne. Le blog apparaît à des moments de vie et accompagne souvent des tournants biographiques (ruptures, questionnement mais aussi nouveaux apprentissages, nouvelles rencontres, etc.. Nous proposons dans cet article d’analyser le blog en tant que support de mémoire personnelle et d’étudier à travers des exemples concrets les stratégies développées par les blogueurs pour se créer via ce dispositif communicationnel innovant un « espace de conserverie de soi » en ligne.Keeping a journal has become a way of live, or to moment a moment in one’s life (Lejeune, 2006. It has multiple uses: construction of a narrative identity, marking time, liberating the

  15. Modulation of the SSTA decadal variation on ENSO events and relationships of SSTA With LOD,SOI, etc

    Science.gov (United States)

    Liao, D. C.; Zhou, Y. H.; Liao, X. H.

    2007-01-01

    Interannual and decadal components of the length of day (LOD), Southern Oscillation Index (SOI) and Sea Surface Temperature anomaly (SSTA) in Nino regions are extracted by band-pass filtering, and used for research of the modulation of the SSTA on the ENSO events. Results show that besides the interannual components, the decadal components in SSTA have strong impacts on monitoring and representing of the ENSO events. When the ENSO events are strong, the modulation of the decadal components of the SSTA tends to prolong the life-time of the events and enlarge the extreme anomalies of the SST, while the ENSO events, which are so weak that they can not be detected by the interannual components of the SSTA, can also be detected with the help of the modulation of the SSTA decadal components. The study further draws attention to the relationships of the SSTA interannual and decadal components with those of LOD, SOI, both of the sea level pressure anomalies (SLPA) and the trade wind anomalies (TWA) in tropic Pacific, and also with those of the axial components of the atmospheric angular momentum (AAM) and oceanic angular momentum (OAM). Results of the squared coherence and coherent phases among them reveal close connections with the SSTA and almost all of the parameters mentioned above on the interannual time scales, while on the decadal time scale significant connections are among the SSTA and SOI, SLPA, TWA, ?3w and ?3w+v as well, and slight weaker connections between the SSTA and LOD, ?3pib and ?3bp

  16. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  17. Modeling and analysis of surface potential of single gate fully depleted SOI MOSFET using 2D-Poisson's equation

    Science.gov (United States)

    Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant

    2016-03-01

    In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.

  18. Une dialectique de la pudeur : les pratiques de mise en visibilité de soi sur Facebook

    OpenAIRE

    Mell , Laurent

    2017-01-01

    L’amplification des usages des technologies de l’information et de la communication (TIC), et plus particulièrement des réseaux socionumériques, ont induit des évolutions significatives dans le rapport des individus aux normes relatives à la pudeur. Dans cet article, nous proposons de discuter des pratiques de mise en visibilité de soi sur le réseau socionumérique Facebook. Tout d’abord, nous montrons que l’augmentation de la considération pour la vie privée amène à une sélection des informat...

  19. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  20. Improved the Surface Roughness of Silicon Nanophotonic Devices by Thermal Oxidation Method

    Energy Technology Data Exchange (ETDEWEB)

    Shi Zujun; Shao Shiqian; Wang Yi, E-mail: ywangwnlo@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, No. 1037, Luoyu Street, Wuhan 430074 (China)

    2011-02-01

    The transmission loss of the silicon-on-insulator (SOI) waveguide and the coupling loss of the SOI grating are determined to a large extent by the surface roughness. In order to obtain smaller loss, thermal oxidation is a good choice to reduce the surface roughness of the SOI waveguide and grating. Before the thermal oxidation, the root mean square of the surface roughness is over 11 nm. After the thermal oxidation, the SEM figure shows that the bottom of the grating is as smooth as quartz surface, while the AFM shows that the root mean square of the surface is less than 5 nm.

  1. Impact of technology scaling in SOI back-channel total dose tolerance. A 2-D numerical study using a self-consistent oxide code; Effet du facteur d'echelle sur la tolerance en dose de rayonnement dans le cas du courant de fuite arriere des transistors MOS/SOI. Une etude d'un oxyde utilise un code auto coherent en deux dimensions

    Energy Technology Data Exchange (ETDEWEB)

    Leray, J.L.; Paillet, Ph.; Ferlet-Cavrois, V. [CEA Bruyeres le Chatel DRIF, 91 (France); Tavernier, C.; Belhaddad, K. [ISE Integrated System Engineering AG (Switzerland); Penzin, O. [ISE Integrated System Engineering Inc., San Jose (United States)

    1999-07-01

    A new 2-D and 3-D self-consistent code has been developed and is applied to understanding the charge trapping in SOI buried oxide causing back-channel MOS leakage in SOI transistors. Clear indications on scaling trends are obtained with respect to supply voltage and oxide thickness. (authors)

  2. Directly Modulated and ER Enhanced Hybrid III-V/SOI DFB Laser Operating up to 20 Gb/s for Extended Reach Applications in PONs

    DEFF Research Database (Denmark)

    Cristofori, Valentina; Da Ros, Francesco; Chaibi, Mohamed E.

    2017-01-01

    We demonstrate error-free performance of an MRR filtered DML on the SOI platform over 40- and 81-km of SSW. The device operates up to 17.5 Gb/s over 81 km and 20 Gb/s over 40 km.......We demonstrate error-free performance of an MRR filtered DML on the SOI platform over 40- and 81-km of SSW. The device operates up to 17.5 Gb/s over 81 km and 20 Gb/s over 40 km....

  3. A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

    Science.gov (United States)

    Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

    2007-06-01

    waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

  4. A CMOS/SOI Single-input PWM Discriminator for Low-voltage Body-implanted Applications

    Directory of Open Access Journals (Sweden)

    Jader A. De Lima

    2002-01-01

    Full Text Available A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 μm single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm2. Measured resolution of encoding parameter α is better than 10% at 6 MHz and VDD = 3.3 V. Idle-mode consumption is 340 μW. Pulses of frequencies up to15 MHz and α =10% can be discriminated for 2.3 V ≤ VDD ≤ 3.3 V. Such an excellent immunity to VDD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

  5. One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

    International Nuclear Information System (INIS)

    Zhang Jun; Guo Yu-Feng; Xu Yue; Lin Hong; Yang Hui; Hong Yang; Yao Jia-Fei

    2015-01-01

    A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device. (paper)

  6. Emerging heterogeneous integrated photonic platforms on silicon

    Directory of Open Access Journals (Sweden)

    Fathpour Sasan

    2015-05-01

    Full Text Available Silicon photonics has been established as a mature and promising technology for optoelectronic integrated circuits, mostly based on the silicon-on-insulator (SOI waveguide platform. However, not all optical functionalities can be satisfactorily achieved merely based on silicon, in general, and on the SOI platform, in particular. Long-known shortcomings of silicon-based integrated photonics are optical absorption (in the telecommunication wavelengths and feasibility of electrically-injected lasers (at least at room temperature. More recently, high two-photon and free-carrier absorptions required at high optical intensities for third-order optical nonlinear effects, inherent lack of second-order optical nonlinearity, low extinction ratio of modulators based on the free-carrier plasma effect, and the loss of the buried oxide layer of the SOI waveguides at mid-infrared wavelengths have been recognized as other shortcomings. Accordingly, several novel waveguide platforms have been developing to address these shortcomings of the SOI platform. Most of these emerging platforms are based on heterogeneous integration of other material systems on silicon substrates, and in some cases silicon is integrated on other substrates. Germanium and its binary alloys with silicon, III–V compound semiconductors, silicon nitride, tantalum pentoxide and other high-index dielectric or glass materials, as well as lithium niobate are some of the materials heterogeneously integrated on silicon substrates. The materials are typically integrated by a variety of epitaxial growth, bonding, ion implantation and slicing, etch back, spin-on-glass or other techniques. These wide range of efforts are reviewed here holistically to stress that there is no pure silicon or even group IV photonics per se. Rather, the future of the field of integrated photonics appears to be one of heterogenization, where a variety of different materials and waveguide platforms will be used for

  7. Resonant Varifocal Micromirror with Piezoresistive Focus Sensor

    Directory of Open Access Journals (Sweden)

    Kenta Nakazawa

    2016-03-01

    Full Text Available This paper reports a microelectromechanical systems (MEMS resonant varifocal mirror integrated with piezoresistive focus sensor. The varifocal mirror is driven electrostatically at a resonant frequency of a mirror plate to obtain the wide scanning range of a focal length. A piezoresistor is used to monitor the focal length of the varifocal mirror. The device is made of a silicon-on-insulator (SOI wafer and a glass wafer. A mirror plate and a counter electrode are fabricated by a top silicon layer of the SOI wafer and on the glass wafer, respectively. The piezoresistor is fabricated by ion implantation on a supporting beam of the mirror plate. The stress variation of the beam, which is detected by the piezoresistor, correspond the focal length of the varifocal mirror. The focus length varies from −41 to 35 mm at the resonant frequency of 9.5 kHz. The focal length of the varifocal mirror is monitored by the piezoresistor in real time.

  8. Extreme implanting in Si: A study of ion-induced damage at high temperature and high dose

    International Nuclear Information System (INIS)

    Holland, O.W.

    1994-01-01

    Ion-solid interactions near room temperature and below have been well studied in single-crystal Si. While this has led to a better understanding of the mechanisms responsible for nucleation and growth of lattice damage during irradiation, these studies have not, in general, been extended to high temperatures (e.g., >200 degrees C). This is the case despite the commercialization of ion beam technologies which utilize high-temperature processing, such as separation by implantation of oxygen (SIMOX). In this process, a silicon-on-insulator (SOI) material is produced by implanting a high dose of oxygen ions into a Si wafer to form a buried, stoichiometric oxide layer. Results will be presented of a study of damage accumulation during high-dose implantation of Si at elevated temperatures. In particular, O + -ions were used because of the potential impact of the results on the SIMOX technology. It will be shown that the nature of the damage accumulation at elevated temperatures is quite distinctive and portends the presence of a new mechanism, one which is only dominant under the extreme conditions encountered during ion beam synthesis (i.e., high temperature and high dose). This mechanism is discussed and shown to be quite general and not dependent on the chemical identity of the ions. Also, techniques for suppressing this mechanism by open-quotes defect engineeringclose quotes are discussed. Such techniques are technologically relevant because they offer the possibility of reducing the defect density of the SOI produced by SIMOX

  9. Error-free Dispersion-uncompensated Transmission at 20 Gb/s over SSMF using a Hybrid III-V/SOI DML with MRR Filtering

    DEFF Research Database (Denmark)

    Cristofori, Valentina; Kamchevska, Valerija; Ding, Yunhong

    2016-01-01

    Error-free 20-Gb/s directly-modulated transmission is achieved by enhancing the dispersion tolerance of a III-V/SOI DFB laser with a silicon micro-ring resonator. Low (∼0.4 dB) penalty compared to back-to-back without ring is demonstrated after 5-km SSMF....

  10. Structural Make-up, Biopolymer Conformation, and Biodegradation Characteristics of Newly Developed Super Genotype of Oats (CDC SO-I vs. Conventional Varieties): Novel Approach

    International Nuclear Information System (INIS)

    Damiran, D.; Yu, P.

    2010-01-01

    Recently, a new 'super' genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE L3x , 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  11. Structural makeup, biopolymer conformation, and biodegradation characteristics of a newly developed super genotype of oats (CDC SO-I versus conventional varieties): a novel approach.

    Science.gov (United States)

    Damiran, Daalkhaijav; Yu, Peiqiang

    2010-02-24

    Recently, a new "super" genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE(L3x), 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

  12. 125-GHz Microwave Signal Generation Employing an Integrated Pulse Shaper

    DEFF Research Database (Denmark)

    Liao, Shasha; Ding, Yunhong; Dong, Jianji

    2017-01-01

    We propose and experimentally demonstrate an on-chip pulse shaper for 125-GHz microwave waveform generation. The pulse shaper is implemented based on a silicon-on-insulator (SOI) platform that has a structure with eight-tap finite impulse response (FIR) and there is an amplitude modulator on each...... of the generated microwave waveforms is larger than 100 GHz, and it has wide bandwidth when changing the time delay of the adjacent taps and compactness, capability for integration with electronics and small power consumption are also its merits.......We propose and experimentally demonstrate an on-chip pulse shaper for 125-GHz microwave waveform generation. The pulse shaper is implemented based on a silicon-on-insulator (SOI) platform that has a structure with eight-tap finite impulse response (FIR) and there is an amplitude modulator on each...

  13. Le tourisme gay : aller ailleurs pour être soi-même ?

    Directory of Open Access Journals (Sweden)

    Emmanuel Jaurand

    2010-02-01

    Full Text Available L’orientation dominante des études sur le tourisme, longtemps marquées par l’importance de la dimension économique et par un désintérêt pour les questions touchant au corps, au sexe ou au genre, explique le silence autour du tourisme gay (qui n’est pas le tourisme des gays jusqu’aux années 1990. Pourtant, ce tourisme identitaire existe depuis longtemps et sa visibilité se développe, surtout dans les pays développés occidentaux. La métaphore du voyage et la recherche du paradis (sexuel perdu sont au cœur de l’identité homosexuelle depuis le 19 e siècle. Le tourisme gay se caractérise par des structures (tour-opérateurs, hébergements, croisières… et des destinations spécifiques. Pour les gays il s’agit, dans l’espace-temps des vacances, propice au relâchement et à la recréation de soi, de fuir un monde structuré par le système hétérosexiste et de rejoindre les autres (gays. La recherche de la rencontre du semblable et la sexualisation assumée du tourisme gay, à travers la libération et la dénudation des corps, participent d’une véritable quête pour valider son identité de gay. Elles font que les destinations préférées par les gays sont les stations balnéaires et les grandes villes : elles sont en effet dotées d’espaces publics, d’équipements commerciaux et de formes d’hébergement fermées favorables aux interactions et à la réalisation d’une éphémère « communauté gay ». The mainstream orientation of tourism studies, focused on the sole economic dimension for a long time, without any interest for questions about the body, sex or gender, explains the silence surrounding gay tourism (which is not the tourism of gay men since the 1990s. However, this identity tourism has existed for a long time and its visibility is growing, especially in Western developed countries. The metaphor of the journey and the search for a (sexual paradise lost have been at the core of the

  14. Direct synthesis of ultrathin SOI structure by extremely low-energy oxygen implantation

    Energy Technology Data Exchange (ETDEWEB)

    Hoshino, Yasushi, E-mail: yhoshino@kanagawa-u.ac.jp; Yachida, Gosuke; Inoue, Kodai; Toyohara, Taiga; Nakata, Jyoji [Department of mathematics and physics, Kanagawa University, 2946, Tsuchiya, Hiratsuka, Kanagawa 259-1293 (Japan)

    2016-06-15

    We performed extremely low-energy {sup 16}O{sup +} implantation at 10 keV (R{sub p} ∼ 25 nm) followed by annealing aiming at directly synthesizing an ultrathin Si layer separated by a buried SiO{sub 2} layer in Si(001) substrates, and then investigated feasible condition of recrystallization and stabilization of the superficial Si and the buried oxide layer by significantly low temperature annealing. The elemental compositions were analyzed by Rutherford backscattering (RBS) and secondary ion mass spectroscopy (SIMS). The crystallinity of the superficial Si layer was quantitatively confirmed by ananlyzing RBS-channeling spectra. Cross-sectional morphologies and atomic configurations were observed by transmission electron microscope (TEM). As a result, we succeeded in directly synthesizing an ultrathin single-crystalline silicon layer with ≤20 nm thick separated by a thin buried stoichiometric SiO{sub 2} layer with ≤20 nm thick formed by extremely low-energy {sup 16}O{sup +} implantation followed by surprisingly low temperature annealing at 1050{sup ∘} C.

  15. New insights on SOI Tunnel FETs with low-temperature process flow for CoolCube™ integration

    Science.gov (United States)

    Diaz Llorente, C.; Le Royer, C.; Batude, P.; Fenouillet-Beranger, C.; Martinie, S.; Lu, C.-M. V.; Allain, F.; Colinge, J.-P.; Cristoloveanu, S.; Ghibaudo, G.; Vinet, M.

    2018-06-01

    This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual ID-VDS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage VTH and low supply voltage VDD.

  16. Deep Trek High Temperature Electronics Project

    Energy Technology Data Exchange (ETDEWEB)

    Bruce Ohme

    2007-07-31

    This report summarizes technical progress achieved during the cooperative research agreement between Honeywell and U.S. Department of Energy to develop high-temperature electronics. Objects of this development included Silicon-on-Insulator (SOI) wafer process development for high temperature, supporting design tools and libraries, and high temperature integrated circuit component development including FPGA, EEPROM, high-resolution A-to-D converter, and a precision amplifier.

  17. Dynamic control of chaotic resonators

    KAUST Repository

    Di Falco, A.; Bruck, R.; Liu, C.; Muskens, O.; Fratalocchi, Andrea

    2016-01-01

    We report on the all-optical control of chaotic optical resonators based on silicon on insulator (SOI) platform. We show that simple non-chaotic cavities can be tuned to exhibit chaotic behavior via intense optical pump- ing, inducing a local change of refractive index. To this extent we have fabricated a number of devices and demonstrated experimentally and theoretically that chaos can be triggered on demand on an optical chip. © 2016 SPIE.

  18. Six-beam homodyne laser Doppler vibrometry based on silicon photonics technology.

    Science.gov (United States)

    Li, Yanlu; Zhu, Jinghao; Duperron, Matthieu; O'Brien, Peter; Schüler, Ralf; Aasmul, Soren; de Melis, Mirko; Kersemans, Mathias; Baets, Roel

    2018-02-05

    This paper describes an integrated six-beam homodyne laser Doppler vibrometry (LDV) system based on a silicon-on-insulator (SOI) full platform technology, with on-chip photo-diodes and phase modulators. Electronics and optics are also implemented around the integrated photonic circuit (PIC) to enable a simultaneous six-beam measurement. Measurement of a propagating guided elastic wave in an aluminum plate (speed ≈ 909 m/s @ 61.5 kHz) is demonstrated.

  19. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; hide

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  20. Dynamic control of chaotic resonators

    KAUST Repository

    Di Falco, A.

    2016-02-16

    We report on the all-optical control of chaotic optical resonators based on silicon on insulator (SOI) platform. We show that simple non-chaotic cavities can be tuned to exhibit chaotic behavior via intense optical pump- ing, inducing a local change of refractive index. To this extent we have fabricated a number of devices and demonstrated experimentally and theoretically that chaos can be triggered on demand on an optical chip. © 2016 SPIE.

  1. Food security among individuals experiencing homelessness and mental illness in the At Home/Chez Soi Trial.

    Science.gov (United States)

    O'Campo, Patricia; Hwang, Stephen W; Gozdzik, Agnes; Schuler, Andrée; Kaufman-Shriqui, Vered; Poremski, Daniel; Lazgare, Luis Ivan Palma; Distasio, Jino; Belbraouet, Slimane; Addorisio, Sindi

    2017-08-01

    Individuals experiencing homelessness are particularly vulnerable to food insecurity. The At Home/Chez Soi study provides a unique opportunity to first examine baseline levels of food security among homeless individuals with mental illness and second to evaluate the effect of a Housing First (HF) intervention on food security in this population. At Home/Chez Soi was a 2-year randomized controlled trial comparing the effectiveness of HF compared with usual care among homeless adults with mental illness, stratified by level of need for mental health services (high or moderate). Logistic regressions tested baseline associations between food security (US Food Security Survey Module), study site, sociodemographic variables, duration of homelessness, alcohol/substance use, physical health and service utilization. Negative binomial regression determined the impact of the HF intervention on achieving levels of high or marginal food security over an 18-month follow-up period (6 to 24 months). Community settings at five Canadian sites (Moncton, Montreal, Toronto, Winnipeg and Vancouver). Homeless adults with mental illness (n 2148). Approximately 41 % of our sample reported high or marginal food security at baseline, but this figure varied with gender, age, mental health issues and substance use problems. High need participants who received HF were more likely to achieve marginal or high food security than those receiving usual care, but only at the Toronto and Moncton sites. Our large multi-site study demonstrated low levels of food security among homeless experiencing mental illness. HF showed promise for improving food security among participants with high levels of need for mental health services, with notable site differences.

  2. Defect formation and recrystallization in the silicon on sapphire films under Si{sup +} irradiation

    Energy Technology Data Exchange (ETDEWEB)

    Shemukhin, A.A., E-mail: shemuhin@gmail.com [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Nazarov, A.V.; Balakshin, Yu. V. [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Chernysh, V.S. [Skobeltsyn Institute of Nuclear Physics, Lomonosov Moscow State University, Moscow (Russian Federation); Faculty of Physics, Lomonosov Moscow State University, Moscow (Russian Federation)

    2015-07-01

    Silicon-on-sapphire (SOS) is one of the most promising silicon-on-insulator (SOI) technologies. SOS structures are widely used in microelectronics, but to meet modern requirements the silicon layer should be 100 nm thick or less. The problem is in amount of damage in the interface layer, which decreases the quality of the produced devices. In order to improve the crystalline structure quality SOS samples with 300 nm silicon layers were implanted with Si{sup +} ions with energies in the range from 180 up to 230 keV with fluences in the range from 10{sup 14} up to 5 × 10{sup 15} cm{sup −2} at 0 °C. The crystalline structure of the samples was studied with RBS and the interface layer was studied with SIMS after subsequent annealing. It has been found out that to obtain silicon films with high lattice quality it is necessary to damage the sapphire lattice near the silicon–sapphire interface. Complete destruction of the strongly defected area and subsequent recrystallization depends on the energy of implanted ions and the substrate temperature. No significant mixing in the interface layer was observed with the SIMS.

  3. Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

    International Nuclear Information System (INIS)

    Kim, Tae-Hyun; Park, Jea-Gun

    2013-01-01

    We investigated the combined effect of the strained Si channel and hole confinement on the memory margin enhancement for a capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator (ε-Si SGOI). The memory margin for the ε-Si SGOI capacitor-less memory cell was higher than that of the memory cell fabricated on an unstrained Si-on-insulator (SOI) and increased with increasing Ge concentration of the relaxed SiGe layer; i.e. the memory margin for the ε-Si SGOI capacitor-less memory cell (138.6 µA) at a 32 at% Ge concentration was 3.3 times higher than the SOI capacitor-less memory cell (43 µA). (paper)

  4. Reactions and Diffusion During Annealing-Induced H(+) Generation in SOI Buried Oxides

    International Nuclear Information System (INIS)

    Devine, R.A.B.; Fleetwood, D.M.; Vanheusden, K; Warren, W.L.

    1999-01-01

    We report experimental results suggesting that mobile protons are generated at strained Si-O-Si bonds near the Si/SiO 2 interface during annealing in forming gas. Our data further suggest that the presence of the top Si layer plays a crucial role in the mobile H + generation process. Finally, we show that the diffusion of the reactive species (presumably H 2 or H 0 ) towards the H + generation sites occurs laterally along the buried oxide layer, and can be impeded significantly due to the presence of trapping sites in the buried oxide

  5. The role of implantation damage in the production of silicon-on-insulator films by co-implantation of He+ and H+

    International Nuclear Information System (INIS)

    Venezia, V.C.; Agarwal, A.; Lucent Technologies, Murray Hill, NJ; Haynes, T.E.; Holland, O.W.; Eaglesham, D.J.; Weldon, M.K.; Chabal, Y.J.

    1998-01-01

    Recent work has demonstrated that the process of silicon thin film separation by hydrogen implantation, as well as the more basic phenomenon of surface blistering, can occur at a much lower total dose when H and He are co-implanted than when H is implanted alone. Building on that work, this paper investigates the role of implantation damage in this process by separating the contributions of gas pressure from those of damage. Three different experiments using co-implantation were designed. In the first of these experiments, H and He implants were spatially separated thereby separating the damage from each implant. The second experiment involved co-implantation of H and He at a temperature of 77 K to retain a larger amount of damage for the same gas dose. In the third experiment, Li was co-implanted with H, to create additional damage without introducing additional gas. These experiments together show that increasing the implantation damage itself hampers the formation of surface blisters, and that the increased efficiency observed for He co-implantation with H is due to the supplementary source of gas provided by the He

  6. A Laboratory Project on the Theory, Fabrication, and Characterization of a Silicon-on-Insulator Micro-Comb Drive Actuator with Fixed-Fixed Beams

    Science.gov (United States)

    Abbas, K.; Leseman, Z. C.

    2012-01-01

    A laboratory course on the theory, fabrication, and characterization of microelectromechanical systems (MEMS) devices for a multidisciplinary audience of graduate students at the University of New Mexico, Albuquerque, has been developed. Hands-on experience in the cleanroom has attracted graduate students from across the university's engineering…

  7. Exceptional cracking behavior in H-implanted Si/B-doped Si0.70Ge0.30/Si heterostructures

    Science.gov (United States)

    Chen, Da; Wang, Dadi; Chang, Yongwei; Li, Ya; Ding, Rui; Li, Jiurong; Chen, Xiao; Wang, Gang; Guo, Qinglei

    2018-01-01

    The cracking behavior in H-implanted Si/B-doped Si0.70Ge0.30/Si structures after thermal annealing was investigated. The crack formation position is found to closely correlate with the thickness of the buried Si0.70Ge0.30 layer. For H-implanted Si containing a buried 3-nm-thick B-doped Si0.70Ge0.30 layer, localized continuous cracking occurs at the interfaces on both sides of the Si0.70Ge0.30 interlayer. Once the thickness of the buried Si0.70Ge0.30 layer increases to 15 and 70 nm, however, a continuous sharp crack is individually observed along the interface between the Si substrate and the B-doped Si0.70Ge0.30 interlayer. We attribute this exceptional cracking behavior to the existence of shear stress on both sides of the buried Si0.70Ge0.30 layer and the subsequent trapping of hydrogen, which leads to a crack in a well-controlled manner. This work may pave the way for high-quality Si or SiGe membrane transfer in a feasible manner, thus expediting its potential applications to ultrathin silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI) production.

  8. On-chip grating coupler array on the SOI platform for fan-in/fan-out of multi-core fibers with low insertion loss and crosstalk

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ye, Feihong; Peucheret, Christophe

    2014-01-01

    We design and fabricate a compact multi-core fiber fan-in/fan-out using a fully-etched grating coupler array on the SOI platform. Lowest coupling loss of 6.8 dB with 3 dB bandwidth of 48 nm and crosstalk lower than ×32 dB are demonstrated.......We design and fabricate a compact multi-core fiber fan-in/fan-out using a fully-etched grating coupler array on the SOI platform. Lowest coupling loss of 6.8 dB with 3 dB bandwidth of 48 nm and crosstalk lower than ×32 dB are demonstrated....

  9. Low Voltage, High-Q SOI MEMS Varactors for RF Applications

    DEFF Research Database (Denmark)

    Yalcinkaya, Arda Deniz; Jensen, Søren; Hansen, Ole

    2003-01-01

    A micro electromechanical tunable capacitor with a low control voltage, a wide tuning range and high electrical quality factor is presented with detailed characterizations. A 50μm thick single-crystalline silicon layer was etched using deep reactive ion etching (DRIE) for obtaining high-aspect ra...... is a suitable passive component to be used in band-pass filtering, voltage controlled oscillator or impedance matching applications on the very high frequency(VHF) and ultra high frequency (UHF) bands....

  10. Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

    Science.gov (United States)

    Jain, Neeraj; Raj, Balwinder

    2017-12-01

    Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

  11. A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

    Directory of Open Access Journals (Sweden)

    Saeid Marjani

    2016-09-01

    Full Text Available In this paper, a silicon–on–insulator (SOI p–n–p–n tunneling field–effect transistor (TFET with a silicon doped hafnium oxide (Si:HfO2 ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3 and strontium bismuth tantalate (SrBi2Ta2O9 provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

  12. Evaluation of a silicon 5 MHz p–n diode actuator with a laterally vibrating extensional mode

    Science.gov (United States)

    Miyazaki, Fumito; Baba, Kazuki; Tanigawa, Hiroshi; Furutsuka, Takashi; Suzuki, Kenichiro

    2018-05-01

    In this paper, we describe p–n diode actuators that are laterally driven by the force induced in a depletion layer. The previously reported p–n diode actuators have been vertically driven. Because the resonant frequency depends on the thickness of the vibrating plate, the integration of resonators with different frequencies on a chip has been difficult. The resonators in this work are driven laterally by using length-extensional vibration. We have developed a compact model based on an analytical expression, in which p–n diode actuators are driven by the forces induced by the spread of the depletion layer. The deflection generated by the p–n diode actuators was proportional to the ratio of the depletion layer width to the resonator thickness as well as the position of the p–n junction. Good agreement of experimental results with the theory was confirmed by comparing the measured values for silicon p–n diode rectangular-plate actuators fabricated using a silicon-on-insulator (SOI) substrate. The displacement amplitude of the actuators was proportional to the DC bias, while the resonant frequency was independent of the DC bias. The latter characteristic is very different from that of widely used electrostatic actuators. Although the amplitude of the actuator measured in this work was very small, it is expected that the amplitude will increase greatly by increasing the doping of the p–n diode actuators.

  13. Fabrication of double-dot single-electron transistor in silicon nanowire

    International Nuclear Information System (INIS)

    Jo, Mingyu; Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Ono, Yukinori; Inokawa, Hiroshi; Choi, Jung-Bum; Takahashi, Yasuo

    2010-01-01

    We propose a simple method for fabricating Si single-electron transistors (SET) with coupled dots by means of a pattern-dependent-oxidation (PADOX) method. The PADOX method is known to convert a small one-dimensional Si wire formed on a silicon-on-insulator (SOI) substrate into a SET automatically. We fabricated a double-dot Si SET when we oxidized specially designed Si nanowires formed on SOI substrates. We analyzed the measured electrical characteristics by fitting the measurement and simulation results and confirmed the double-dot formation and the position of the two dots in the Si wire.

  14. Photographie et représentation de soi dans W ou le Souvenir d’enfance de Georges Perec

    Directory of Open Access Journals (Sweden)

    Siriki Ouattara

    2014-04-01

    Full Text Available W ou le souvenir d’enfance convoque ouvertement en son sein des éléments paralittéraires comme la photographie qui le déconstruit. Le désir de Georges Perec de reconstituer ou de reconstruire son histoire est si ardent qu’il lui a consacré ce roman particulier. Dans cette œuvre autobiographique atypique, l’auteur fait appel à diverses techniques de représentation de soi, la photographie. Cette dernière est un élément nouveau en littérature (même s´elle y est prise en compte depuis le dix-neuvième siècle qui redéfinit nombre d´habitudes littéraires. Ainsi, elle occasionne un renouvellement de l´écriture à travers l´institution de nouveaux rapports qui, tout en changeant les vieux rôles narratifs, invitent à dire autrement, voire à raconter différemment. La photographie offre alors l´occasion d´expérimenter une nouvelle discursivité de la représentation.

  15. Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2013-01-01

    Full Text Available Ultrathin body (UTB and nanoscale body (NSB SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

  16. Fabrication and characterization of large arrays of mesoscopic gold rings on large-aspect-ratio cantilevers

    Energy Technology Data Exchange (ETDEWEB)

    Ngo, D. Q.; Petković, I., E-mail: ivana.petkovic@yale.edu; Lollo, A. [Department of Physics, Yale University, New Haven, Connecticut 06520 (United States); Castellanos-Beltran, M. A. [National Institute for Standards and Technology, Boulder, Colorado 80305 (United States); Harris, J. G. E. [Department of Physics, Yale University, New Haven, Connecticut 06520 (United States); Department of Applied Physics, Yale University, New Haven, Connecticut 06520 (United States)

    2014-10-15

    We have fabricated large arrays of mesoscopic metal rings on ultrasensitive cantilevers. The arrays are defined by electron beam lithography and contain up to 10{sup 5} rings. The rings have a circumference of 1 μm, and are made of ultrapure (6N) Au that is deposited onto a silicon-on-insulator wafer without an adhesion layer. Subsequent processing of the SOI wafer results in each array being supported at the end of a free-standing cantilever. To accommodate the large arrays while maintaining a low spring constant, the cantilevers are nearly 1 mm in both lateral dimensions and 100 nm thick. The extreme aspect ratio of the cantilevers, the large array size, and the absence of a sticking layer are intended to enable measurements of the rings' average persistent current in the presence of relatively small magnetic fields. We describe the motivation for these measurements, the fabrication of the devices, and the characterization of the cantilevers' mechanical properties. We also discuss the devices' expected performance in measurements of .

  17. Invention de soi et compétences à l’ère des réseaux sociaux

    Directory of Open Access Journals (Sweden)

    Daniel Apollon

    2011-06-01

    Full Text Available Les réseaux sociaux en ligne encouragent de nouvelles approches de la compétence centrées sur la construction biographique de l’individu et l’invention de soi. Ce nouvel art de faire des « produsagers », répond au besoin d’inventer une réponse individuelle et collective au sentiment aliénant de vacuité des sociétés post-industrielles et post-traditionnelles. Combinant opposition et soumission aux éléments structurants et aliénants de cette modernité tardive, ces produsagers réactualisent diverses ruses, tactiques et schèmes immémoriaux déjà explorés par divers auteurs avant Internet. Sur cette toile de fond, l’auteur propose une réinterprétation plus large de la notion de compétence.Social media practices encourage new approaches and visions of competence focusing on the construction of individual biography and the "invention of oneself". The new "artful skills" of "produsers" address the need to invent individual and collective responses to the sense of alienating emptiness pervading postindustrial and posttraditional societies. Combining and submission and opposition to both structuring and alienating aspects of late modernity, these produsagers actualize various tricks, tactics and immemorial schemes already mapped by various authors before the Internet. On this backdrop the author proposes a broader reinterpretation of the concept of competence.

  18. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    Science.gov (United States)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  19. Analysis of photonic spot profile converter and bridge structure on SOI platform for horizontal and vertical integration

    Science.gov (United States)

    Majumder, Saikat; Jha, Amit Kr.; Biswas, Aishik; Banerjee, Debasmita; Ganguly, Dipankar; Chakraborty, Rajib

    2017-08-01

    Horizontal spot size converter required for horizontal light coupling and vertical bridge structure required for vertical integration are designed on high index contrast SOI platform in order to form more compact integrated photonic circuits. Both the structures are based on the concept of multimode interference. The spot size converter can be realized by successive integration of multimode interference structures with reducing dimension on horizontal plane, whereas the optical bridge structure consists of a number of vertical multimode interference structure connected by single mode sections. The spot size converter can be modified to a spot profile converter when the final single mode waveguide is replaced by a slot waveguide. Analysis have shown that by using three multimode sections in a spot size converter, an Gaussian input having spot diameter of 2.51 μm can be converted to a spot diameter of 0.25 μm. If the output single mode section is replaced by a slot waveguide, this input profile can be converted to a flat top profile of width 50 nm. Similarly, vertical displacement of 8μm is possible by using a combination of two multimode sections and three single mode sections in the vertical bridge structure. The analyses of these two structures are carried out for both TE and TM modes at 1550 nm wavelength using the semi analytical matrix method which is simple and fast in computation time and memory. This work shows that the matrix method is equally applicable for analysis of horizontally as well as vertically integrated photonic circuit.

  20. Reduced Pressure-Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

    International Nuclear Information System (INIS)

    Hartmann, J.M.; Andrieu, F.; Lafond, D.; Ernst, T.; Bogumilowicz, Y.; Delaye, V.; Weber, O.; Rouchon, D.; Papon, A.M.; Cherkashin, N.

    2008-01-01

    We have first of all quantified the impact of pressure on Si and SiGe growth kinetics. Definite growth rate and Ge concentration increases with the pressure have been evidenced at low temperatures (650-750 deg. C). By contrast, the high temperature (950-1050 deg. C) Si growth rate either increases or decreases with pressure (gaseous precursor depending). We have then described the selective epitaxial growth process we use to form Si or Si 0.7 Ge 0.3 :B raised sources and drains on ultra-thin patterned Silicon-On-Insulator (SOI) substrates. We have afterwards presented the specifics of SiGe virtual substrates and of the tensile-strained Si layers grown on top (used as templates for the elaboration of tensily strained-SOI wafers). The tensile strain, which can be tailored from 1.3 up to 3 GPa, leads to an electron mobility gain by a factor of 2 in n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) built on top. High Ge content SiGe virtual substrates can also be used for the elaboration of compressively strained Ge channels, with impressive hole mobility gains (x9) compared to bulk Si. After that, we have described the main structural features of thick Ge layers grown directly on Si (that can be used as donor wafers for the elaboration of GeOI wafers or as the active medium of near infrared photo-detectors). Finally, we have shown how Si/SiGe multilayers can be used for the formation of high performance 3D devices such as multi-bridge channel or nano-beam gate-all-around FETs, the SiGe sacrificial layers being removed thanks to plasma dry etching, wet etching or in situ gaseous HCl etching

  1. Enhanced spectroscopic gas sensors using in-situ grown carbon nanotubes

    Energy Technology Data Exchange (ETDEWEB)

    De Luca, A.; Cole, M. T.; Milne, W. I. [Department of Engineering, University of Cambridge, Cambridge CB3 0FA (United Kingdom); Hopper, R. H.; Boual, S.; Ali, S. Z. [Cambridge CMOS Sensors Ltd., Deanland House, 160 Cowley Road, Cambridge CB4 0DL (United Kingdom); Warner, J. H.; Robertson, A. R. [Department of Materials, University of Oxford, Oxford OX1 3PH (United Kingdom); Udrea, F. [Department of Engineering, University of Cambridge, Cambridge CB3 0FA (United Kingdom); Cambridge CMOS Sensors Ltd., Deanland House, 160 Cowley Road, Cambridge CB4 0DL (United Kingdom); Gardner, J. W. [School of Engineering, University of Warwick, Coventry CV4 7AL (United Kingdom)

    2015-05-11

    In this letter, we present a fully complementary-metal-oxide-semiconductor (CMOS) compatible microelectromechanical system thermopile infrared (IR) detector employing vertically aligned multi-walled carbon nanotubes (CNT) as an advanced nano-engineered radiation absorbing material. The detector was fabricated using a commercial silicon-on-insulator (SOI) process with tungsten metallization, comprising a silicon thermopile and a tungsten resistive micro-heater, both embedded within a dielectric membrane formed by a deep-reactive ion etch following CMOS processing. In-situ CNT growth on the device was achieved by direct thermal chemical vapour deposition using the integrated micro-heater as a micro-reactor. The growth of the CNT absorption layer was verified through scanning electron microscopy, transmission electron microscopy, and Raman spectroscopy. The functional effects of the nanostructured ad-layer were assessed by comparing CNT-coated thermopiles to uncoated thermopiles. Fourier transform IR spectroscopy showed that the radiation absorbing properties of the CNT adlayer significantly enhanced the absorptivity, compared with the uncoated thermopile, across the IR spectrum (3 μm–15.5 μm). This led to a four-fold amplification of the detected infrared signal (4.26 μm) in a CO{sub 2} non-dispersive-IR gas sensor system. The presence of the CNT layer was shown not to degrade the robustness of the uncoated devices, whilst the 50% modulation depth of the detector was only marginally reduced by 1.5 Hz. Moreover, we find that the 50% normalized absorption angular profile is subsequently more collimated by 8°. Our results demonstrate the viability of a CNT-based SOI CMOS IR sensor for low cost air quality monitoring.

  2. Influence of Bipolar Pulse Poling Technique for Piezoelectric Vibration Energy Harvesters using Pb(Zr,Ti)O3 Films on 200 mm SOI Wafers

    International Nuclear Information System (INIS)

    Moriwaki, N; Fujimoto, K; Suzuki, K; Kobayashi, T; Itoh, T; Maeda, R; Suzuki, Y; Makimoto, N

    2013-01-01

    Piezoelectric vibration energy harvester arrays using Pb(Zr,Ti)O 3 thin films on 200 mm SOI wafers were fabricated. In-plane distribution of influence of bipolar pulse poling technique on direct current (DC) power output from the harvesters was investigated. The results indicate that combination poling treatment of DC and bipolar pulse poling increases a piezoelectric property and reduces a dielectric constant. It means that this poling technique improves the figure of merit of sensors and harvesters. Maximum DC power from a harvester treated by DC poling after bipolar pulse poling is about five times larger than a one treated by DC poling only

  3. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

    Science.gov (United States)

    Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

    2018-07-01

    This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

  4. Fully-etched apodized fiber-to-chip grating coupler on the SOI platform with -0.78 dB coupling efficiency using photonic crystals and bonded Al mirror

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Peucheret, Christophe

    2014-01-01

    We design and fabricate an ultra-high coupling efficiency fully-etched apodized grating coupler on the SOI platform using photonic crystals and bonded aluminum mirror. Ultra-high coupling efficiency of -0.78 dB with a 3 dB bandwidth of 74 nm are demonstrated.......We design and fabricate an ultra-high coupling efficiency fully-etched apodized grating coupler on the SOI platform using photonic crystals and bonded aluminum mirror. Ultra-high coupling efficiency of -0.78 dB with a 3 dB bandwidth of 74 nm are demonstrated....

  5. Batch-processed carbon nanotube wall as pressure and flow sensor

    International Nuclear Information System (INIS)

    Choi, Jungwook; Kim, Jongbaeg

    2010-01-01

    A pressure and flow sensor based on the electrothermal-thermistor effect of a batch-processed carbon nanotube wall (CNT wall) is presented. The negative temperature coefficient of resistance (TCR) of CNTs and the temperature dependent tunneling rate through the CNT/silicon junction enable vacuum pressure and flow velocity sensing because the heat transfer rate between CNTs and the surrounding gas molecules differs depending on pressure and flow rate. The CNT walls are synthesized by thermal chemical vapor deposition (CVD) on an array of microelectrodes fabricated on a silicon-on-insulator (SOI) wafer. The CNTs are self-assembled between the microelectrodes and substrate across the thickness of a buried oxide layer during the synthesis process, and the simple batch fabrication results in high throughput and yield. A wide pressure range, down to 3 x 10 -3 from 10 5 Pa, and a nitrogen flow velocity range between 1 and 52.4 mm s -1 , are sensed. Further experimental characterizations of the bias voltage dependent response of the sensor as a vacuum pressure gauge are presented.

  6. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators.

    Science.gov (United States)

    Mizumoto, Tetsuya; Shoji, Yuya; Takei, Ryohei

    2012-05-24

    This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO₃. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI) waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  7. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators

    Directory of Open Access Journals (Sweden)

    Ryohei Takei

    2012-05-01

    Full Text Available This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO3. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  8. Effect of TMAH Etching Duration on the Formation of Silicon Nano wire Transistor Patterned by AFM Nano lithography

    International Nuclear Information System (INIS)

    Hutagalung, S.D.; Lew, K.C.

    2012-01-01

    Atomic force microscopy (AFM) lithography was applied to produce nano scale pattern for silicon nano wire transistor fabrication. This technique takes advantage of imaging facility of AFM and the ability of probe movement controlling over the sample surface to create nano patterns. A conductive AFM tip was used to grow the silicon oxide nano patterns on silicon on insulator (SOI) wafer. The applied tip-sample voltage and writing speed were well controlled in order to form pre-designed silicon oxide nano wire transistor structures. The effect of tetra methyl ammonium hydroxide (TMAH) etching duration on the oxide covered silicon nano wire transistor structure has been investigated. A completed silicon nano wire transistor was obtained by removing the oxide layer via hydrofluoric acid etching process. The fabricated silicon nano wire transistor consists of a silicon nano wire that acts as a channel with source and drain pads. A lateral gate pad with a nano wire head was fabricated very close to the channel in the formation of transistor structures. (author)

  9. Performance of the THS4302 and the Class V Radiation-Tolerant THS4304-SP Silicon Germanium Wideband Amplifiers at Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard L.; Elbuluk, Malik; Hammoud, Ahmad; VanKeuls, Frederick W.

    2009-01-01

    This report discusses the performance of silicon germanium, wideband gain amplifiers under extreme temperatures. The investigated devices include Texas Instruments THS4304-SP and THS4302 amplifiers. Both chips are manufactured using the BiCom3 process based on silicon germanium technology along with silicon-on-insulator (SOI) buried oxide layers. The THS4304-SP device was chosen because it is a Class V radiation-tolerant (150 kRad, TID silicon), voltage-feedback operational amplifier designed for use in high-speed analog signal applications and is very desirable for NASA missions. It operates with a single 5 V power supply [1]. It comes in a 10-pin ceramic flatpack package, and it provides balanced inputs, low offset voltage and offset current, and high common mode rejection ratio. The fixed-gain THS4302 chip, which comes in a 16-pin leadless package, offers high bandwidth, high slew rate, low noise, and low distortion [2]. Such features have made the amplifier useful in a number of applications such as wideband signal processing, wireless transceivers, intermediate frequency (IF) amplifier, analog-to-digital converter (ADC) preamplifier, digital-to-analog converter (DAC) output buffer, measurement instrumentation, and medical and industrial imaging.

  10. Thin-film piezoelectric-on-silicon resonators for high-frequency reference oscillator applications.

    Science.gov (United States)

    Abdolvand, Reza; Lavasani, Hossein M; Ho, Gavin K; Ayazi, Farrokh

    2008-12-01

    This paper studies the application of lateral bulk acoustic thin-film piezoelectric-on-substrate (TPoS) resonators in high-frequency reference oscillators. Low-motional-impedance TPoS resonators are designed and fabricated in 2 classes--high-order and coupled-array. Devices of each class are used to assemble reference oscillators and the performance characteristics of the oscillators are measured and discussed. Since the motional impedance of these devices is small, the transimpedance amplifier (TIA) in the oscillator loop can be reduced to a single transistor and 3 resistors, a format that is very power-efficient. The lowest reported power consumption is approximately 350 microW for an oscillator operating at approximately 106 MHz. A passive temperature compensation method is also utilized by including the buried oxide layer of the silicon-on-insulator (SOI) substrate in the structural resonant body of the device, and a very small (-2.4 ppm/ degrees C) temperature coefficient of frequency is obtained for an 82-MHz oscillator.

  11. An electrostatic scanning micromirror with diaphragm mirror plate and diamond-shaped reinforcement frame

    Science.gov (United States)

    Ji, Chang-Hyeon; Choi, Moongoo; Kim, Sang-Cheon; Lee, See-Hyung; Kim, Seong-Hyok; Yee, Youngjoo; Bu, Jong-Uk

    2006-05-01

    We present the design, fabrication and measurement results of a comb-driven electrostatic scanning micromirror. Instead of a conventional micromirror having uniform thickness across the entire reflective surface, a diaphragm mirror plate supported by an array of diamond-shaped frame structures is fabricated monolithically. The fabrication process is a simple sequence of silicon deep etch processes on both sides of the silicon-on-insulator (SOI) substrate without the substrate bonding process. The micromirror is fabricated on the device layer of the substrate. The mirror plate undergoes a rotational motion by an electrostatic force between the movable comb electrodes connected to the micromirror and stationary comb electrode formed on the handle wafer. A scanning micromirror with a 10 µm thick diaphragm mirror plate, having a planar dimension of 1.5 × 1.5 mm2, supported by an array of 110 µm thick rhombic support frames, was fabricated and tested. A mechanical deflection angle of 8.5° at a resonance frequency of 19.55 kHz and a pressure of 7 mTorr was obtained. A prototype of the raster scanning laser projection display system was developed using the fabricated micromirror as the horizontal scanner and a galvanomirror as the vertical scanner, respectively.

  12. Low Power Resistive Oxygen Sensor Based on Sonochemical SrTi0.6Fe0.4O2.8 (STFO40

    Directory of Open Access Journals (Sweden)

    Alisa Stratulat

    2015-07-01

    Full Text Available The current paper reports on a sonochemical synthesis method for manufacturing nanostructured (typical grain size of 50 nm SrTi0.6Fe0.4O2.8 (Sono-STFO40 powder. This powder is characterized using X ray-diffraction (XRD, Mössbauer spectroscopy and Scanning Electron Microscopy (SEM, and results are compared with commercially available SrTi0.4Fe0.6O2.8 (STFO60 powder. In order to manufacture resistive oxygen sensors, both Sono-STFO40 and STFO60 are deposited, by dip-pen nanolithography (DPN method, on an SOI (Silicon-on-Insulator micro-hotplate, employing a tungsten heater embedded within a dielectric membrane. Oxygen detection tests are performed in both dry (RH = 0% and humid (RH = 60% nitrogen atmosphere, varying oxygen concentrations between 1% and 16% (v/v, at a constant heater temperature of 650 °C. The oxygen sensor, based on the Sono-STFO40 sensing layer, shows good sensitivity, low power consumption (80 mW, and short response time (25 s. These performance are comparable to those exhibited by state-of-the-art O2 sensors based on STFO60, thus proving Sono-STFO40 to be a material suitable for oxygen detection in harsh environments.

  13. A Study of Mach-Zehnder Interferometer Type Optical Modulator Applicable to an Accelerometer

    Science.gov (United States)

    Suzuki, Masato; Takahashi, Tomokazu; Aoyagi, Seiji; Amemiya, Yoshiteru; Fukuyama, Masataka; Yokoyama, Shin

    2011-04-01

    A novel Mach-Zehnder interferometer (MZI)-type optical modulator based on micro electro mechanical systems (MEMS) technology is developed in this study. In this optical modulator, one of two branched waveguides in the MZI has a floating beam structure (air-bridge type). Additionally, a cantilever supporting a proof mass intersects with the floating optical waveguide. When an inertial force due to acceleration is applied to the proof mass, the floating waveguide is expanded and the output of the MZI is modulated. Therefore, this optical modulator will be applicable to an accelerometer in the future. To decrease optical loss at the intersectional point between the floating waveguide and the cantilever in the MZI, the multi-mode interference (MMI) waveguide is serially connected with the floating waveguide and the cantilever crosses to the MMI waveguide. An optimization of the MMI waveguide and an estimation of deflection of the floating waveguide due to applying force are carried out by using optical and mechanical simulation, respectively. The proposed optical modulator is fabricated by inductively coupled plasma (ICP) etching of the top layer of a silicon-on-insulator (SOI) wafer, which is made of crystal Si. The floating waveguide in the modulator is formed by removal of its underlying buried oxide (BOX) layer of SOI. As a result of evaluation, we have succeeded in changing the output of the MZI by applying a force to the cantilever. However, the modulation is smaller than the expected value. Improvement of the modulation and detection of the inertial force due to the applied acceleration are future tasks.

  14. L’empathie comme outil herméneutique du soi: Note sur Paul Ricœur et Heinz Kohut

    Directory of Open Access Journals (Sweden)

    Michel Dupuis

    2011-01-01

    Full Text Available Le bref texte que Paul Ricœur consacre en 1986 à la psychanalyse développée par Heinz Kohut révèle une réinterprétation phénoménologique à la fois du contenu et des fonctions de l'empathie, au total considérée comme un véritable outil à l'œuvre dans l'herméneutique du soi. La vision kohutienne de la constitution du soi et du processus thérapeutique analytique produit une espèce de “dé-sentimentalisation” de l'empathie, en soulignant le rôle crucial du transfert intersubjectif, fort à distance de la théorie (freudienne solipsiste de l'ego.The short text published in 1986 by Paul Ricoeur about Heinz Kohut's psychoanalysis of the self reveals a phenomenological reinterpretation of the content and the functions of empathy, finally considered as an effective tool of the hermeneutics of the self. Kohut's model of constitution of the self and of the therapeutic analytical process produces a kind of “de-sentimentalization” of empathy, pointing to the crucial role of intersubjective transfer, far from a (Freudian solipsistic theory of the ego.

  15. Effect of the Ion Mass and Energy on the Response of 70-nm SOI Transistors to the Ion Deposited Charge by Direct Ionization

    International Nuclear Information System (INIS)

    Raine, M.; Gaillardin, M.; Sauvestre, J.E.; Flament, O.; Bournel, A.; Aubry-Fortuna, V.

    2010-01-01

    The response of SOI transistors under heavy ion irradiation is analyzed using Geant4 and Synopsys Sentaurus device simulations. The ion mass and energy have a significant impact on the radial ionization profile of the ion deposited charge. For example, for an identical LET, the higher the ion energy per nucleon, the wider the radial ionization track. For a 70-nm SOI technology, the track radius of high energy ions (≥ 10 MeV/a) is larger than the transistor sensitive volume; part of the ion charge recombines in the highly doped source or drain regions and does not participate to the transistor electric response. At lower energy (≤ 10 MeV/a), as often used for ground testing, the track radius is smaller than the transistor sensitive volume, and the entire charge is used for the transistor response. The collected charge is then higher, corresponding to a worst-case response of the transistor. Implications for the hardness assurance of highly-scaled generations are discussed. (authors)

  16. An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

    Science.gov (United States)

    Saramekala, G. K.; Santra, Abirmoya; Dubey, Sarvesh; Jit, Satyabrata; Tiwari, Pramod Kumar

    2013-08-01

    In this paper, an analytical short-channel threshold voltage model is presented for a dual-metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first time, the advantages of recessed source/drain (Re-S/D) and of dual-metal-gate structure are incorporated simultaneously in a fully depleted SOI MOSFET. The analytical surface potential model at Si-channel/SiO2 interface and Si-channel/buried-oxide (BOX) interface have been developed by solving the 2-D Poisson’s equation in the channel region with appropriate boundary conditions assuming parabolic potential profile in the transverse direction of the channel. Thereupon, a threshold voltage model is derived from the minimum surface potential in the channel. The developed model is analyzed extensively for a variety of device parameters like the oxide and silicon channel thicknesses, thickness of source/drain extension in the BOX, control and screen gate length ratio. The validity of the present 2D analytical model is verified with ATLAS™, a 2D device simulator from SILVACO Inc.

  17. Layered materials

    Science.gov (United States)

    Johnson, David; Clarke, Simon; Wiley, John; Koumoto, Kunihito

    2014-06-01

    Layered compounds, materials with a large anisotropy to their bonding, electrical and/or magnetic properties, have been important in the development of solid state chemistry, physics and engineering applications. Layered materials were the initial test bed where chemists developed intercalation chemistry that evolved into the field of topochemical reactions where researchers are able to perform sequential steps to arrive at kinetically stable products that cannot be directly prepared by other approaches. Physicists have used layered compounds to discover and understand novel phenomena made more apparent through reduced dimensionality. The discovery of charge and spin density waves and more recently the remarkable discovery in condensed matter physics of the two-dimensional topological insulating state were discovered in two-dimensional materials. The understanding developed in two-dimensional materials enabled subsequent extension of these and other phenomena into three-dimensional materials. Layered compounds have also been used in many technologies as engineers and scientists used their unique properties to solve challenging technical problems (low temperature ion conduction for batteries, easy shear planes for lubrication in vacuum, edge decorated catalyst sites for catalytic removal of sulfur from oil, etc). The articles that are published in this issue provide an excellent overview of the spectrum of activities that are being pursued, as well as an introduction to some of the most established achievements in the field. Clusters of papers discussing thermoelectric properties, electronic structure and transport properties, growth of single two-dimensional layers, intercalation and more extensive topochemical reactions and the interleaving of two structures to form new materials highlight the breadth of current research in this area. These papers will hopefully serve as a useful guideline for the interested reader to different important aspects in this field and

  18. Mask-less deposition of Au–SnO_2 nanocomposites on CMOS MEMS platform for ethanol detection

    International Nuclear Information System (INIS)

    Santra, S; Sinha, A K; Ray, S K; De Luca, A; Udrea, F; Ali, S Z; Gardner, J W; Guha, P K

    2016-01-01

    Here we report on the mask-less deposition of Au–SnO_2 nanocomposites with a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) micro electro mechanical system (MEMS) platform through the use of dip pen nanolithography (DPN) to create a low-cost ethanol sensor. MEMS technology is used in order to achieve low power consumption, by the employment of a membrane structure formed using deep reactive ion etching technique. The device consists of an embedded tungsten micro-heater with gold interdigitated electrodes on top of the SOI membrane. The tungsten micro-heater is used to raise the membrane temperature up to its operating temperature and the electrodes are used to measure the resistance of the nanocomposite sensing layer. The CMOS MEMS devices have high electro-thermal efficiency, with 8.2 °C temperature increase per mW power of consumption. The sensing material (Au–SnO_2 nanocomposite) was synthesised starting from SnO nanoplates, then Au nanoparticles were attached chemically to the surface of SnO nanoplates, finally the mixture was heated at 700 °C in an oven in air for 4 h. This composite material was sonicated for 2 h in terpineol to make a viscous homogeneous slurry and then ‘written’ directly across the electrode area using the DPN technique without any mask. The devices were characterised by exposure to ethanol vapour in humid air in the concentration range of 100–1000 ppm. The sensitivity varied from 1.2 to 0.27 ppm"−"1 for 100–1000 ppm of ethanol at 10% relative humid air. Selectivity measurements showed that the sensors were selective towards ethanol when they were exposed to acetone and toluene. (paper)

  19. Double positive effect of adding hexaethyelene glycol when optimizing the hybridization efficiency of a microring DNA detection assay

    Energy Technology Data Exchange (ETDEWEB)

    Van Eeghem, Anabelle, E-mail: anabelle.vaneeghem@gmail.com [Polymer Chemistry and Biomaterials Research Group, Department of Organic and Macromolecular Chemistry, Ghent University (Belgium); Center for Nano- and Biophotonics, Ghent University (Belgium); Werquin, Sam [Center for Nano- and Biophotonics, Ghent University (Belgium); Photonics Research Group, Department of Information Technology, Ghent University – IMEC (Belgium); Hoste, Jan-Willem, E-mail: janwillem.hoste@ugent.be [Center for Nano- and Biophotonics, Ghent University (Belgium); Photonics Research Group, Department of Information Technology, Ghent University – IMEC (Belgium); Goes, Arne [Polymer Chemistry and Biomaterials Research Group, Department of Organic and Macromolecular Chemistry, Ghent University (Belgium); Agrosavfe NV, Technologiepark 4 (Bio-incubator), Zwijnaarde (Belgium); Vanderleyden, Els [Polymer Chemistry and Biomaterials Research Group, Department of Organic and Macromolecular Chemistry, Ghent University (Belgium); Center for Nano- and Biophotonics, Ghent University (Belgium); Bienstman, Peter [Center for Nano- and Biophotonics, Ghent University (Belgium); Photonics Research Group, Department of Information Technology, Ghent University – IMEC (Belgium); Dubruel, Peter [Polymer Chemistry and Biomaterials Research Group, Department of Organic and Macromolecular Chemistry, Ghent University (Belgium); Center for Nano- and Biophotonics, Ghent University (Belgium)

    2017-05-31

    Highlights: • The hybridization efficiency of a DNA assay was investigated based on SOI microring resonators. • A 4-fold increase in efficiency was obtained by using HEG as backfilling agent, as well as improving robustness. • The dual polarization microring technique shows that HEG reorients the DNA in an upright position. • Hybridizing at 35 °C and with a buffer containing 50 v/v% of formamide greatly improves the robustness. - Abstract: In this paper, a method for detection of DNA molecules using silicon-on-insulator (SOI) microring resonators is described. The influence of temperature and the use of formamide on the hybridization efficiency were studied. It was shown that 50 v/v% of formamide in the hybridization buffer can ensure hybridization when working close to physiological temperature. Furthermore, the use of hexaethylene glycol (HEG) as backfilling agent was studied in order to resolve issues of non-specific adsorption to the surface. The results indicated that not only non-specific binding was reduced significantly but also that HEG improves the orientation of the DNA probes on the surface. This led to a 4-fold increase in hybridization efficiency and thus in an equal decrease in the detection limit, compared to hybridization without the use of HEG. An improvement in robustness of the assay was also observed. This DNA reorientation hypothesis was confirmed by studying the thickness and density of the layers by using dual polarization microring sensing. Finally, the different steps in the sensing experiment were characterized in more detail by static contact angle (SCA) and X-ray photoelectron spectroscopy (XPS) analysis. The results showed quantitatively that the surface modifications were successful.

  20. Determined Initial lead for South Of Isua (SOI) terrain suggests a single homogeneous source for it and possibly other archaean rocks

    Science.gov (United States)

    Tera, F.

    2011-12-01

    A Thorogenic-Uranogenic Lead Isotope Plane (TULIP), which entails plotting 206/208 (or its reverse) vs 207/208 (or its reverse), was applied to the Pb data on South of Isua (SOI) by Kamber et al., (1). When the data on 20 samples of these rocks and feldspars are plotted in pairs (each pair is a rock and its feldspar) on TULIP, they fall on 10 mixing lines that converge on a single spot (Fig. 1). This is the end member initial lead (EMIL). The 206/208 & 207/208 so determined are 0.3675 and 0.43525, respectively. From these values one calculates 207/206 = 1.1843 ± 0.0007, for EMIL. This pattern requires either: A) each pair has a singular kappa, K = 232Th/238U, different from others, or B) a pair's in situ decay Pb was homogenized in recent times. On 204/206 vs 207/206 diagram, the whole rocks of SOI define a 3.776 Ga isochron (2). From this and EMIL's 207/206, one obtains: 206/204 = 10.977, 207/204 = 12.974; and 208/204 = 29.756. This singularity of initial Pb contrasts with a deduced variability by the original authors (1). EMIL's radiogenic *(207/206) = 1.6220, gives a single-stage age = 5.9 Ga, indicating inapplicability of its evolution in one stage. Also, the μ calculated from 238U-206Pb for the single stage is different from that inferred from 235U-207Pb, confirming disqualification of this scenario. Reconciliation of the two decay schemes necessitates assumption of EMIL evolution in a minimum of two stages. Starting at 4.563 Ga, five scenarios were assumed: First stage ends and second starts at 4.55, 4.54, 4.53, 4.52 or 4.51 Ga. Second stages end at 3.776 Ga. The calculated μ1 for the first stage are 106, 59.5, 44.6, 36.3 and 30.9 respectively. For μ2 the change is limited, from 5.45 to 5.28. Only an average calculated K for both stages is possible. For the five outlined scenarios it ranges from 1.118 to 1.111. Earlier, Tera (3) observed that initial Pb of the oldest terrestrial reservoir requires evolution in two stages. There too μ1 >> μ2. Data on

  1. On-chip grating coupler array on the SOI platform for fan-in/fan-out of MCFs with low insertion loss and crosstalk

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ye, Feihong; Peucheret, Christophe

    2015-01-01

    We report the design and fabrication of a compact multi-core fiber fan-in/fan-out using a grating coupler array on the SOI platform. The grating couplers are fully-etched, enabling the whole circuit to be fabricated in a single lithography and etching step. Thanks to the apodized design...... for the grating couplers and the introduction of an aluminum reflective mirror, a highest coupling efficiency of -3.8 dB with 3 dB coupling bandwidth of 48 nm and 1.5 dB bandwidth covering the whole C band, together with crosstalk lower than -32 dB are demonstrated. (C)2015 Optical Society of America...

  2. Total dose behavior of partially depleted SOI dynamic threshold voltage MOS (DTMOS) for very low supply voltage applications (0.6 - 1 V)

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Musseau, O.; Leray, J.L.; Faynot, O.; Raynaud, C.; Pelloie, J.L.

    1999-01-01

    In this paper, we presented two DTMOS architectures processed with a partially depleted SOI technology. The first architecture, DTMOS without limiting transistor, is dedicated to ultra-low voltage applications, at 0.6 V. For 1V applications, the second architecture, DTMOS with limiting transistor, needs an additional transistor to limit the body-source diode current. The total dose irradiation of both DTMOS architectures induces no change of the drain current, but an increase of the body-source diode current. Total dose induced trapped charge in the buried oxide increases the body potential of the DTMOS transistor. It induces an increase of the current flow at the back interface of the silicon film. Irradiation of complex circuits using DTMOS transistors would lead to a degradation of the stand-by consumption. (authors)

  3. Assembly of Ge nanocrystals on SiO2 via a stress-induced dewetting process

    International Nuclear Information System (INIS)

    Sutter, E; Sutter, P

    2006-01-01

    We use epitaxial Ge islands on silicon-on-insulator (001) to initiate and drive the dewetting of the ultrathin ( 2 layer and transforms the Ge islands into oxide-supported, electrically isolated, Ge-rich nanocrystals. We investigate the process of dewetting and demonstrate that it can be used for the controlled assembly of nanocrystals-from isolated single ones to dense arrays

  4. Gap-closing test structures for temperature budget determination

    NARCIS (Netherlands)

    Faber, Erik Jouwert; Wolters, Robertus A.M.; Schmitz, Jurriaan

    2011-01-01

    We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer

  5. Silicon-photonics light source realized by III-V/Si grating-mirror laser

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2010-01-01

    waveguide are made in the Si layer of a silicon-on-insulator wafer by using Si-electronics-compatible processing. The HCG works as a highly-reflective mirror for vertical resonance and at the same time routes light to the in-plane output waveguide. Numerical simulations show superior performance compared...... to existing silicon light sources....

  6. Highly tunable NEMS shallow arches

    KAUST Repository

    Kazmi, Syed N. R.; Hajjaj, Amal Z.; Da Costa, Pedro M. F. J.; Younis, Mohammad I.

    2017-01-01

    and surface nanomachining of a highly conductive device layer on a silicon-on-insulator wafer. By designing the structures to have gap to thickness ratio of more than four, the mid-plane stretching of the nano arches is maximized such that an increase

  7. Nonlinear optical properties of silicon waveguides

    International Nuclear Information System (INIS)

    Tsang, H K; Liu, Y

    2008-01-01

    Recent work on two-photon absorption (TPA), stimulated Raman scattering (SRS) and optical Kerr effect in silicon-on-insulator (SOI) waveguides is reviewed and some potential applications of these optical nonlinearities, including silicon-based autocorrelation detectors, optical amplifiers, high speed optical switches, optical wavelength converters and self-phase modulation (SPM), are highlighted. The importance of free carriers generated by TPA in nonlinear devices is discussed, and a generalized definition of the nonlinear effective length to cater for nonlinear losses is proposed. How carrier lifetime engineering, and in particular the use of helium ion implantation, can enhance the nonlinear effective length for nonlinear devices is also discussed

  8. Grazing-incident PIXE Analysis Technology

    International Nuclear Information System (INIS)

    Li Hongri; Wang Guangpu; Liang Kun; Yang Ru; Han Dejun

    2009-01-01

    In the article, the grazing incidence technology is first applied to the PIXE (proton induced X-ray emission) analysis. Three pieces of samples were investigated, including the contaminated aluminium substrate, the SIMOX (separated by oxygen implantation) SOI (Silicon on Insulator) sample and the silicon wafer implanted with Fe + . The results reveal that the grazing-incident proton can improve the sensitivity of PIXE in trace analysis, especially for samples contaminated on surface. With the penetration depth of the proton bean decreased, the ratio of the peak area to the detection limit raised observably and the sensitivity near the sample surface increased. (authors)

  9. High-contrast grating hollow-core waveguide splitter applied to optical phased array

    Science.gov (United States)

    Zhao, Che; Xue, Ping; Zhang, Hanxing; Chen, Te; Peng, Chao; Hu, Weiwei

    2014-11-01

    A novel hollow-core (HW) Y-branch waveguide splitter based on high-contrast grating (HCG) is presented. We calculated and designed the HCG-HW splitter using Rigorous Coupled Wave Analysis (RCWA). Finite-different timedomain (FDTD) simulation shows that the splitter has a broad bandwidth and the branching loss is as low as 0.23 dB. Fabrication is accomplished with standard Silicon-On-Insulator (SOI) process. The experimental measurement results indicate its good performance on beam splitting near the central wavelength λ = 1550 nm with a total insertion loss of 7.0 dB.

  10. Low-loss slot waveguides with silicon (111 surfaces realized using anisotropic wet etching

    Directory of Open Access Journals (Sweden)

    Kapil Debnath

    2016-11-01

    Full Text Available We demonstrate low-loss slot waveguides on silicon-on-insulator (SOI platform. Waveguides oriented along the (11-2 direction on the Si (110 plane were first fabricated by a standard e-beam lithography and dry etching process. A TMAH based anisotropic wet etching technique was then used to remove any residual side wall roughness. Using this fabrication technique propagation loss as low as 3.7dB/cm was realized in silicon slot waveguide for wavelengths near 1550nm. We also realized low propagation loss of 1dB/cm for silicon strip waveguides.

  11. Micro-and Nano-Optomechanical Devices for Sensors, Oscillators, and Photonics

    Science.gov (United States)

    2015-10-26

    which the optical and acoustic fields interact strongly. Such circuits can be readily adapted to wafer formats such as silicon-on- insulator (SOI) or...a  so-­‐called  ‘Chern   insulator ’  (a  variety  of  a  topological   insulator )  for   sound .  If  realized,  this...with dielectric and elastic properties, resulting in strong dispersion and interaction between optical and acoustic waves with wavelengths on the

  12. Interfacing Dielectric-Loaded Plasmonic and Silicon Photonic Waveguides: Theoretical Analysis and Experimental Demonstration

    DEFF Research Database (Denmark)

    Tsilipakos, O.; Pitilakis, A.; Yioultsis, T. V.

    2012-01-01

    A comprehensive theoretical analysis of end-fire coupling between dielectric-loaded surface plasmon polariton and rib/wire silicon-on-insulator (SOI) waveguides is presented. Simulations are based on the 3-D vector finite element method. The geometrical parameters of the interface are varied...... in order to identify the ones leading to optimum performance, i.e., maximum coupling efficiency. Fabrication tolerances about the optimum parameter values are also assessed. In addition, the effect of a longitudinal metallic stripe gap on coupling efficiency is quantified, since such gaps have been...

  13. A Temperature-Hardened Sensor Interface with a 12-Bit Digital Output Using a Novel Pulse Width Modulation Technique

    Directory of Open Access Journals (Sweden)

    Emna Chabchoub

    2018-04-01

    Full Text Available A fully integrated sensor interface for a wide operational temperature range is presented. It translates the sensor signal into a pulse width modulated (PWM signal that is then converted into a 12-bit digital output. The sensor interface is based on a pair of injection locked oscillators used to implement a differential time-domain architecture with low sensitivity to temperature variations. A prototype has been fabricated using a 180 nm partially depleted silicon-on-insulator (SOI technology. Experimental results demonstrate a thermal stability as low as 65 ppm/°C over a large temperature range from −20 °C up to 220 °C.

  14. A new spin-functional MOSFET based on magnetic tunnel junction technology: pseudo-spin-MOSFET

    OpenAIRE

    Shuto, Yusuke; Nakane, Ryosho; Wang, Wenhong; Sukegawa, Hiroaki; Yamamoto, Shuu'ichirou; Tanaka, Masaaki; Inomata, Koichiro; Sugahara, Satoshi

    2009-01-01

    We fabricated and characterized a new spin-functional MOSFET referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit using an ordinary MOSFET and magnetic tunnel junction (MTJ) for reproducing functions of spin-transistors. Device integration techniques for a bottom gate MOSFET using a silicon-on-insulator (SOI) substrate and for an MTJ with a full-Heusler alloy electrode and MgO tunnel barrier were developed. The fabricated PS-MOSFET exhibited high and low transconductanc...

  15. Second harmonic generation spectroscopy on Si surfaces and interfaces

    DEFF Research Database (Denmark)

    Pedersen, Kjeld

    2010-01-01

    Optical second harmonic generation (SHG) spectroscopy studies of Si(111) surfaces and interfaces are reviewed for two types of systems: (1) clean 7 x 7 and root 3 x root 3-Ag reconstructed surfaces prepared under ultra-high vacuum conditions where surface states are excited and (2) interfaces...... in silicon-on-insulator (SOI) structures and thin metal films on Si surfaces where several interfaces contribute to the SHG. In all the systems resonances are seen at interband transitions near the bulk critical points E-1 and E-2. On the clean surfaces a number of resonances appear below the onset of bulk...

  16. High efficiency and broad bandwidth grating coupler between nanophotonic waveguide and fibre

    International Nuclear Information System (INIS)

    Yu, Zhu; Xue-Jun, Xu; Zhi-Yong, Li; Liang, Zhou; Yu-De, Yu; Jin-Zhong, Yu; Wei-Hua, Han; Zhong-Chao, Fan

    2010-01-01

    A high efficiency and broad bandwidth grating coupler between a silicon-on-insulator (SOI) nanophotonic waveguide and fibre is designed and fabricated. Coupling efficiencies of 46% and 25% at a wavelength of 1.55 μm are achieved by simulation and experiment, respectively. An optical 3 dB bandwidth of 45 nm from 1530 nm to 1575 nm is also obtained in experiment. Numerical calculation shows that a tolerance to fabrication error of 10 nm in etch depth is achievable. The measurement results indicate that the alignment error of ±2 μm results in less than 1 dB additional coupling loss. (classical areas of phenomenology)

  17. High-temperature MEMS Heater Platforms: Long-term Performance of Metal and Semiconductor Heater Materials

    Directory of Open Access Journals (Sweden)

    Theodor Doll

    2006-04-01

    Full Text Available Micromachined thermal heater platforms offer low electrical power consumptionand high modulation speed, i.e. properties which are advantageous for realizing non-dispersive infrared (NDIR gas- and liquid monitoring systems. In this paper, we report oninvestigations on silicon-on-insulator (SOI based infrared (IR emitter devices heated byemploying different kinds of metallic and semiconductor heater materials. Our resultsclearly reveal the superior high-temperature performance of semiconductor over metallicheater materials. Long-term stable emitter operation in the vicinity of 1300 K could beattained using heavily antimony-doped tin dioxide (SnO2:Sb heater elements.

  18. Vécu des situations scolaires, estime de soi et Développement : du jugement moral a la période de la latence

    Directory of Open Access Journals (Sweden)

    Emile-Henri Riard

    2011-06-01

    Full Text Available Suivant une approche de psychologie sociale clinique, le point de vue adopté dans cet article est triple : 1- considérer les situations scolaires “ ordinaires ” comme potentiellement génératrices de difficultés; 2- s’inscrire en amont de l’adolescence afin d’améliorer la compréhension de cette dernière; 3 – considérer le vécu des élèves. La recherche menée en France (enfants de 6 à 11 ans, par questionnaire (48 situations relevant de la scolarité : classe, cour de récréation, trajet domicile/école et domicile ont été proposées ; test d’estime de soi (Coopersmith ; développement moral (Kohlberg. Variables : âge, sexe, mode d’habitat, position scolaire, classement, département. Les résultats (analyse de variance démontrent un fonctionnement “ en bloc ” du niveau de vécu de difficulté. Ressortent comme variables significatives, par ordre d’importance décroissante: le sexe (les garçons ressentent davantage les difficultés que les filles; l’âge (le niveau de difficulté vécue décroît avec l’âge mais concerne surtout la cour de récréation ; le mode d’habitat (collectif. La classe est l’espace le plus porteur de différences de vécu de difficultés indépendamment des variables. Le niveau d’autonomie et l’estime de soi sont schématiquement inversement proportionnés au niveau de difficulté vécu. La conclusion met l’accent sur l’importance des effets interactif et d’accumulation des situations.

  19. A 60 GOPS/W, -1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

    Science.gov (United States)

    Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca

    2016-03-01

    Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from -1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range -40 °C to 120 °C exploiting -1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors

  20. Layering and Ordering in Electrochemical Double Layers

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Yihua [Materials Science Division, Argonne National Laboratory, Argonne, Illinois 60439, United States; Kawaguchi, Tomoya [Materials Science Division, Argonne National Laboratory, Argonne, Illinois 60439, United States; Pierce, Michael S. [Rochester Institute of Technology, School of Physics and Astronomy, Rochester, New York 14623, United States; Komanicky, Vladimir [Faculty of Science, Safarik University, 041 54 Kosice, Slovakia; You, Hoydoo [Materials Science Division, Argonne National Laboratory, Argonne, Illinois 60439, United States

    2018-02-26

    Electrochemical double layers (EDL) form at electrified interfaces. While Gouy-Chapman model describes moderately charged EDL, formation of Stern layers was predicted for highly charged EDL. Our results provide structural evidence for a Stern layer of cations, at potentials close to hydrogen evolution in alkali fluoride and chloride electrolytes. Layering was observed by x-ray crystal truncation rods and atomic-scale recoil responses of Pt(111) surface layers. Ordering in the layer is confirmed by glancing-incidence in-plane diffraction measurements.

  1. Écritures de soi en souffrance: une lecture des régimes structurant l’imaginaire du texte social vivant

    Directory of Open Access Journals (Sweden)

    Orazio Maria Valastro

    2010-02-01

    Full Text Available Les études ici réunies vont nous permettre d’examiner différentes genres d’écritures et typologies d’écrivains (poétique et épistolaire, roman autobiographique et autofiction, narratif et témoignage, explorant un corpus considérable (œuvres littéraires et littératures personnelles et des pratiques significatives (activités narratives et autobiographiques. Le thème proposé, les écritures de soi en souffrance, se dénoue sollicitant une réflexion sur les rapports entre les œuvres et les différents contextes sociaux et historiques. Nous pouvons envisager et saisir l’ensemble du corpus et des pratiques considérées en tant que texte social vivant, inscrivant l’expérience de l’existence et du monde dans la pratique de l’écriture. (... Nous allons solliciter et proposer une lecture sociologique et anthropologique de l’ensemble des études proposés au sein du numéro monographique, privilégiant une analyse de la matrice du discours social structurant la conscience individuelle et collective.

  2. Housing First for People With Severe Mental Illness Who Are Homeless: A Review of the Research and Findings From the At Home–Chez soi Demonstration Project

    Science.gov (United States)

    Aubry, Tim; Nelson, Geoffrey; Tsemberis, Sam

    2015-01-01

    Objective: To provide a review of the extant research literature on Housing First (HF) for people with severe mental illness (SMI) who are homeless and to describe the findings of the recently completed At Home (AH)–Chez soi (CS) demonstration project. HF represents a paradigm shift in the delivery of community mental health services, whereby people with SMI who are homeless are supported through assertive community treatment or intensive case management to move into regular housing. Method: The AH–CS demonstration project entailed a randomized controlled trial conducted in 5 Canadian cities between 2009 and 2013. Mixed methods were used to examine the implementation of HF programs and participant outcomes, comparing 1158 people receiving HF to 990 people receiving standard care. Results: Initial research conducted in the United States shows HF to be a promising approach, yielding superior outcomes in helping people to rapidly exit homelessness and establish stable housing. Findings from the AH–CS demonstration project reveal that HF can be successfully adapted to different contexts and for different populations without losing its fidelity. People receiving HF achieved superior housing outcomes and showed more rapid improvements in community functioning and quality of life than those receiving treatment as usual. Conclusions: Knowledge translation efforts have been undertaken to disseminate the positive findings and lessons learned from the AH–CS project and to scale up the HF approach across Canada. PMID:26720504

  3. Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime Using Y and Z Functions

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2014-01-01

    Full Text Available The saturation regime of two types of fully depleted (FD SOI MOSFET devices was studied. Ultrathin body (UTB and gate recessed channel (GRC devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the same W/L ratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics (IDS-VDS and IDS-VGS of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using a Y-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of the Y-function analysis and show that a new function called Z can be used to extract the series resistance in the saturation regime.

  4. Compliments, motivation et estime de soi : l'effet paradoxal de féliciter les capacités des enfants

    DEFF Research Database (Denmark)

    Hansen, Mikkel

    2014-01-01

    motivation may suffer when given feedback that evaluates their person. We discuss links between different types of feedback and children’s motivational frameworks, including their self-esteem. // RÉSUMÉ L’objectif de compliments tels que « T’es très fort, très intelligent » est d’encourager les enfants, mais...... des recherches récentes montrent que de telles propositions en feedback peuvent dissuader les enfants de s’engager dans des tâches difficiles, réduisant ainsi leurs apprentissages. Nous exposerons les travaux de Dweck (e.g., 2000) qui démontrent comment les compliments centrés sur l’évaluation de la...... personne influent négativement sur la motivation intrinsèque du sujet. Nous discuterons des liens existant entre différents types de feedback et les cadres motivationnels où évoluent les enfants, ainsi que de leur estime de soi....

  5. Effects of size and defects on the elasticity of silicon nanocantilevers

    International Nuclear Information System (INIS)

    Sadeghian, Hamed; Goosen, Johannes F L; Van Keulen, Fred; Yang, Chung-Kai; Bossche, Andre; French, Paddy J; Staufer, Urs

    2010-01-01

    The size-dependent elastic behavior of silicon nanocantilevers and nanowires, specifically the effective Young's modulus, has been determined by experimental measurements and theoretical investigations. The size dependence becomes more significant as the devices scale down from micro- to nano-dimensions, which has mainly been attributed to surface effects. However, discrepancies between experimental measurements and computational investigations show that there could be other influences besides surface effects. In this paper, we try to determine to what extent the surface effects, such as surface stress, surface elasticity, surface contamination and native oxide layers, influence the effective Young's modulus of silicon nanocantilevers. For this purpose, silicon cantilevers were fabricated in the top device layer of silicon on insulator (SOI) wafers, which were thinned down to 14 nm. The effective Young's modulus was extracted with the electrostatic pull-in instability method, recently developed by the authors (H Sadeghian et al 2009 Appl. Phys. Lett. 94 221903). In this work, the drop in the effective Young's modulus was measured to be significant at around 150 nm thick cantilevers. The comparison between theoretical models and experimental measurements demonstrates that, although the surface effects influence the effective Young's modulus of silicon to some extent, they alone are insufficient to explain why the effective Young's modulus decreases prematurely. It was observed that the fabrication-induced defects abruptly increased when the device layer was thinned to below 100 nm. These defects became visible as pinholes during HF-etching. It is speculated that they could be the origin of the reduced effective Young's modulus experimentally observed in ultra-thin silicon cantilevers.

  6. Factors Influencing Self-Regulation in E-learning 2.0: Confirmatory Factor Model | Facteurs qui influencent la maîtrise de soi en cyberapprentissage 2.0 : modèle de facteur confirmative

    Directory of Open Access Journals (Sweden)

    Hong Zhao

    2016-04-01

    Full Text Available The importance of self-regulation in e-learning has been well noted in research. Relevant studies have shown a consistent positive correlation between learners’ self-regulation and their success rate in e-learning. Increasing attention has been paid to developing learners’ self-regulated abilities in e-learning. For students, what and how to learn are largely predetermined by the learning environment provided by their institutions. Environmental determinants play a key role in shaping self-regulation in the learning process. This paper reports a study on the influences of the e-learning 2.0 environment on self-regulation. The study identified the factors that influence self-regulation in such an environment and determine the relationships between the factors and self-regulation. A theoretical model to categorize the success factors for self-regulated learning was proposed for this kind of environment. Based on the model, a questionnaire was designed and administered to more than two hundred and fifty distance learning students in Beijing and Hong Kong. Through structural equation modeling (SEM technique, relationships between environmental factors and self-regulation were analyzed. Statistical results showed that several factors affect self-regulation in the e-learning 2.0 environment. They include system quality, information quality, service quality, and user satisfaction. L’importance de la maîtrise de soi en cyberapprentissage a été bien étudiée. Les études pertinentes ont démontré une corrélation positive uniforme entre la maîtrise de soi des apprenants et leurs taux de réussite en apprentissage en ligne. Une attention croissante a été portée au développement des aptitudes de maîtrise de soi des élèves en cyberapprentissage. Pour les élèves, quoi apprendre et comment sont des questions principalement prédéterminées par l’environnement d’apprentissage qu’offrent leurs établissements. Les d

  7. Fiber-chip edge coupler with large mode size for silicon photonic wire waveguides.

    Science.gov (United States)

    Papes, Martin; Cheben, Pavel; Benedikovic, Daniel; Schmid, Jens H; Pond, James; Halir, Robert; Ortega-Moñux, Alejandro; Wangüemert-Pérez, Gonzalo; Ye, Winnie N; Xu, Dan-Xia; Janz, Siegfried; Dado, Milan; Vašinek, Vladimír

    2016-03-07

    Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO 2 upper cladding thin high-index Si 3 N 4 layers. The Si 3 N 4 layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.

  8. FEM for modelling 193 nm excimer laser treatment of SiO{sub 2}/Si/Si{sub (1-x)}Ge{sub x} heterostructures on SOI substrates

    Energy Technology Data Exchange (ETDEWEB)

    Conde, J.C.; Chiussi, S.; Gontad, F.; Gonzalez, P. [Dpto. Fisica Aplicada, E.T.S.I.I. University of Vigo, Campus Universitario, Rua Maxwell s/n, 36310 Vigo (Spain); Martin, E. [Dpto. de Mecanica, Maquinas, Motores Termicos y Fluidos, E.T.S.I.I. University of Vigo, Campus Universitario, Rua Maxwell s/n, 36310 Vigo (Spain)

    2011-03-15

    Research on epitaxial crystalline silicon (c-Si) and silicon-germanium (Si{sub 1-x}Ge{sub x}) alloys growth and annealing for microelectronic purposes, such as Micro- or Nano-Electro-Mechanical Systems (MEMS or NEMS) and Silicon-On-Nothing (SON) devices is continuously in progress. Laser assisted annealing techniques using commercial ArF Excimer Laser sources are based on ultra-rapid heating and cooling cycles induced by the 193 nm pulses of 20 ns, which are absorbed in the near surface region of the heterostructures. During and after the absorption of these laser pulses, complex physical processes appear that strongly depend on sample structure and applied laser pulse energy densities. The control of the experimental parameters is therefore a key task for obtaining high quality alloys. The Finite ElementsMethod (FEM) is a powerful tool for the optimization of such treatments, because it provides the spatial and temporal temperature fields that are produced by the laser pulses. In this work, we have used a FEM commercial software, to predict the temperatures gradients induced by ArF excimer laser over a wide energy densities range, 0.1<{phi}<0.4 J/cm{sup 2}, on different SiO{sub 2}/Si/Si{sub (1-x)}Ge{sub (x)} thin films deposited on SOI substrate. These numerical results allow us to predict the threshold energies needed to reach the melting point (MP) of the Si and SiGe alloy without oxidation of the thin films system. Therefore, it is possible to optimize the conditions to achieve high quality epitaxy films. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  9. Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Zerrouk, D.

    1997-07-18

    Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

  10. Novel detectors for silicon based microdosimetry, their concepts and applications

    Science.gov (United States)

    Rosenfeld, Anatoly B.

    2016-02-01

    This paper presents an overview of the development of semiconductor microdosimetry and the most current (state-of-the-art) Silicon on Insulator (SOI) detectors for microdosimetry based mainly on research and development carried out at the Centre for Medical Radiation Physics (CMRP) at the University of Wollongong with collaborators over the last 18 years. In this paper every generation of CMRP SOI microdosimeters, including their fabrication, design, and electrical and charge collection characterisation are presented. A study of SOI microdosimeters in various radiation fields has demonstrated that under appropriate geometrical scaling, the response of SOI detectors with the well-known geometry of microscopically sensitive volumes will record the energy deposition spectra representative of tissue cells of an equivalent shape. This development of SOI detectors for microdosimetry with increased complexity has improved the definition of microscopic sensitive volume (SV), which is modelling the deposition of ionising energy in a biological cell, that are led from planar to 3D SOI detectors with an array of segmented microscopic 3D SVs. The monolithic ΔE-E silicon telescope, which is an alternative to the SOI silicon microdosimeter, is presented, and as an example, applications of SOI detectors and ΔE-E monolithic telescope for microdosimetery in proton therapy field and equivalent neutron dose measurements out of field are also presented. An SOI microdosimeter "bridge" with 3D SVs can derive the relative biological effectiveness (RBE) in 12C ion radiation therapy that matches the tissue equivalent proportional counter (TEPC) quite well, but with outstanding spatial resolution. The use of SOI technology in experimental microdosimetry offers simplicity (no gas system or HV supply), high spatial resolution, low cost, high count rates, and the possibility of integrating the system onto a single device with other types of detectors.

  11. VSWI Wetlands Advisory Layer

    Data.gov (United States)

    Vermont Center for Geographic Information — This dataset represents the DEC Wetlands Program's Advisory layer. This layer makes the most up-to-date, non-jurisdictional, wetlands mapping avaiable to the public...

  12. Layer-by-layer cell membrane assembly

    Science.gov (United States)

    Matosevic, Sandro; Paegel, Brian M.

    2013-11-01

    Eukaryotic subcellular membrane systems, such as the nuclear envelope or endoplasmic reticulum, present a rich array of architecturally and compositionally complex supramolecular targets that are as yet inaccessible. Here we describe layer-by-layer phospholipid membrane assembly on microfluidic droplets, a route to structures with defined compositional asymmetry and lamellarity. Starting with phospholipid-stabilized water-in-oil droplets trapped in a static droplet array, lipid monolayer deposition proceeds as oil/water-phase boundaries pass over the droplets. Unilamellar vesicles assembled layer-by-layer support functional insertion both of purified and of in situ expressed membrane proteins. Synthesis and chemical probing of asymmetric unilamellar and double-bilayer vesicles demonstrate the programmability of both membrane lamellarity and lipid-leaflet composition during assembly. The immobilized vesicle arrays are a pragmatic experimental platform for biophysical studies of membranes and their associated proteins, particularly complexes that assemble and function in multilamellar contexts in vivo.

  13. High-contrast gratings for long-wavelength laser integration on silicon

    Science.gov (United States)

    Sciancalepore, Corrado; Descos, Antoine; Bordel, Damien; Duprez, Hélène; Letartre, Xavier; Menezo, Sylvie; Ben Bakir, Badhise

    2014-02-01

    Silicon photonics is increasingly considered as the most promising way-out to the relentless growth of data traffic in today's telecommunications infrastructures, driving an increase in transmission rates and computing capabilities. This is in fact challenging the intrinsic limit of copper-based, short-reach interconnects and microelectronic circuits in data centers and server architectures to offer enough modulation bandwidth at reasonable power dissipation. In the context of the heterogeneous integration of III-V direct-bandgap materials on silicon, optics with high-contrast metastructures enables the efficient implementation of optical functions such as laser feedback, input/output (I/O) to active/passive components, and optical filtering, while heterogeneous integration of III-V layers provides sufficient optical gain, resulting in silicon-integrated laser sources. The latest ensure reduced packaging costs and reduced footprint for the optical transceivers, a key point for the short reach communications. The invited talk will introduce the audience to the latest breakthroughs concerning the use of high-contrast gratings (HCGs) for the integration of III-V-on-Si verticalcavity surface-emitting lasers (VCSELs) as well as Fabry-Perot edge-emitters (EELs) in the main telecom band around 1.55 μm. The strong near-field mode overlap within HCG mirrors can be exploited to implement unique optical functions such as dense wavelength division multiplexing (DWDM): a 16-λ100-GHz-spaced channels VCSEL array is demonstrated. On the other hand, high fabrication yields obtained via molecular wafer bonding of III-V alloys on silicon-on-insulator (SOI) conjugate excellent device performances with cost-effective high-throughput production, supporting industrial needs for a rapid research-to-market transfer.

  14. Reduction of charge trapping and electron tunneling in SIMOX by supplemental implantation of oxygen

    International Nuclear Information System (INIS)

    Stahlbush, R.E.; Hughes, H.L.; Krull, W.A.

    1993-01-01

    Silicon-on-insulator, SOI, technologies are being aggressively pursued to produce high density, high speed, radiation tolerant electronics. The dielectric isolation of the buried oxide makes it possible to design integrated circuits that greatly minimize single event upset and eliminate dose-rate induced latchup and upset. The reduction of excess-silicon related defects in SIMOX by the supplemental implantation of oxygen has been examined. The supplemental implant is 6% of the oxygen dose used to form the buried oxide, and is followed by a 1,000 C anneal, in contrast to the >1,300 C anneal used to form the buried oxide layer of SIMOX. The defects examined include shallow electron traps, deep hole traps, and silicon clusters. The radiation-induced shallow electron and deep hole trapping are measured by cryogenic detrapping and isothermal annealing techniques. The low-field (3 to 6 MV/cm) electron tunneling is interpreted as due to a two phase mixture of stoichiometric SiO 2 and Si clusters a few nm in size. Single and triple SIMOS samples have been examined. All of the defects are reduced by the supplemental oxygen processing. Shallow electron trapping is reduced by an order of magnitude. Because of the larger capture cross section for hole trapping, hole trapping is not reduced as much. The low-field electron tunneling due to Si clusters is also significantly reduced. Both uniform and nonuniform electron tunneling have been observed in SIMOX samples without supplement processing. In samples exhibiting only uniform tunneling, electron capture at holes has been observed. The nonuniform tunneling is superimposed upon the uniform tunneling and is characterized by current spiking

  15. Ending homelessness among people with mental illness: the At Home/Chez Soi randomized trial of a Housing First intervention in Toronto

    Directory of Open Access Journals (Sweden)

    Hwang Stephen W

    2012-09-01

    Full Text Available Abstract Background The At Home/Chez Soi (AH/CS Project is a randomized controlled trial of a Housing First intervention to meet the needs of homeless individuals with mental illness in five cities across Canada. The objectives of this paper are to examine the approach to participant recruitment and community engagement at the Toronto site of the AH/CS Project, and to describe the baseline demographics of participants in Toronto. Methods Homeless individuals (n = 575 with either high needs (n = 197 or moderate needs (n = 378 for mental health support were recruited through service providers in the city of Toronto. Participants were randomized to Housing First interventions or Treatment as Usual (control groups. Housing First interventions were offered at two different mental health service delivery levels: Assertive Community Treatment for high needs participants and Intensive Case Management for moderate needs participants. Demographic data were collected via quantitative questionnaires at baseline interviews. Results The effectiveness of the recruitment strategy was influenced by a carefully designed referral system, targeted recruitment of specific groups, and an extensive network of pre-existing services. Community members, potential participants, service providers, and other stakeholders were engaged through active outreach and information sessions. Challenges related to the need for different sectors to work together were resolved through team building strategies. Randomization produced similar demographic, mental health, cognitive and functional impairment characteristics in the intervention and control groups for both the high needs and moderate needs groups. The majority of participants were male (69%, aged >40 years (53%, single/never married (69%, without dependent children (71%, born in Canada (54%, and non-white (64%. Many participants had substance dependence (38%, psychotic disorder (37%, major depressive episode (36

  16. Exploring the value of mixed methods within the At Home/Chez Soi housing first project: a strategy to evaluate the implementation of a complex population health intervention for people with mental illness who have been homeless.

    Science.gov (United States)

    Macnaughton, Eric L; Goering, Paula N; Nelson, Geoffrey B

    2012-05-02

    This paper is a methodological case study that describes the At Home/Chez Soi (Housing First) Initiative's mixed-methods strategy for implementation evaluation and discusses the value of these methods in evaluating the implementation of such complex population health interventions. The Housing First (HF) model is being implemented in five cities: Vancouver, Winnipeg, Toronto, Montréal and Moncton. At Home/Chez Soi is an intervention trial that aims to address the issue of homelessness in people with mental health issues. The HF model emphasizes choices, hopefulness and connecting people with resources that make a difference to their quality of life. A component of HF is supported housing, which provides a rent subsidy and rapid access to housing of choice in private apartments; a second component is support. Quantitative and qualitative methods were used to evaluate HF implementation. The findings of this case study illustrate how the critical ingredients of complex interventions, such as HF, can be adapted to different contexts while implementation fidelity is maintained at a theoretical level. The findings also illustrate how the project's mixed methods approach helped to facilitate the adaptation process. Another value of this approach is that it identifies systemic and organizational factors (e.g., housing supply, discrimination, housing procurement strategy) that affect implementation of key elements of HF. In general, the approach provides information about both whether and how key aspects of the intervention are implemented effectively across different settings. It thus provides implementation data that are rigorous, contextually relevant and practical.

  17. The role of advocacy coalitions in a project implementation process: the example of the planning phase of the At Home/Chez Soi project dealing with homelessness in Montreal.

    Science.gov (United States)

    Fleury, Marie-Josée; Grenier, Guy; Vallée, Catherine; Hurtubise, Roch; Lévesque, Paul-André

    2014-08-01

    This study analyzed the planning process (summer 2008 to fall 2009) of a Montreal project that offers housing and community follow-up to homeless people with mental disorders, with or without substance abuse disorders. With the help of the Advocacy Coalition Framework (ACF), advocacy groups that were able to navigate a complex intervention implementation process were identified. In all, 25 people involved in the Montreal At Home/Chez Soi project were surveyed through interviews (n=18) and a discussion group (n=7). Participant observations and documentation (minutes and correspondence) were also used for the analysis. The start-up phase of the At Home/Chez may be broken down into three separate periods qualified respectively as "honeymoon;" "clash of cultures;" and "acceptance & commitment". In each of the planning phases of the At Home/Chez Soi project in Montreal, at least two advocacy coalitions were in confrontation about their specific belief systems concerning solutions to address the recurring homelessness social problem, while a third, more moderate one contributed in rallying most key actors under specified secondary aspects. The study confirms the importance of policy brokers in achieving compromises acceptable to all advocacy coalitions. Copyright © 2014 Elsevier Ltd. All rights reserved.

  18. Mushroom-free selective epitaxial growth of Si, SiGe and SiGe:B raised sources and drains

    Science.gov (United States)

    Hartmann, J. M.; Benevent, V.; Barnes, J. P.; Veillerot, M.; Lafond, D.; Damlencourt, J. F.; Morvan, S.; Prévitali, B.; Andrieu, F.; Loubet, N.; Dutartre, D.

    2013-05-01

    We have evaluated various Cyclic Selective Epitaxial Growth/Etch (CSEGE) processes in order to grow "mushroom-free" Si and SiGe:B Raised Sources and Drains (RSDs) on each side of ultra-short gate length Extra-Thin Silicon-On-Insulator (ET-SOI) transistors. The 750 °C, 20 Torr Si CSEGE process we have developed (5 chlorinated growth steps with four HCl etch steps in-between) yielded excellent crystalline quality, typically 18 nm thick Si RSDs. Growth was conformal along the Si3N4 sidewall spacers, without any poly-Si mushrooms on top of unprotected gates. We have then evaluated on blanket 300 mm Si(001) wafers the feasibility of a 650 °C, 20 Torr SiGe:B CSEGE process (5 chlorinated growth steps with four HCl etch steps in-between, as for Si). As expected, the deposited thickness decreased as the total HCl etch time increased. This came hands in hands with unforeseen (i) decrease of the mean Ge concentration (from 30% down to 26%) and (ii) increase of the substitutional B concentration (from 2 × 1020 cm-3 up to 3 × 1020 cm-3). They were due to fluctuations of the Ge concentration and of the atomic B concentration [B] in such layers (drop of the Ge% and increase of [B] at etch step locations). Such blanket layers were a bit rougher than layers grown using a single epitaxy step, but nevertheless of excellent crystalline quality. Transposition of our CSEGE process on patterned ET-SOI wafers did not yield the expected results. HCl etch steps indeed helped in partly or totally removing the poly-SiGe:B mushrooms on top of the gates. This was however at the expense of the crystalline quality and 2D nature of the ˜45 nm thick Si0.7Ge0.3:B recessed sources and drains selectively grown on each side of the imperfectly protected poly-Si gates. The only solution we have so far identified that yields a lesser amount of mushrooms while preserving the quality of the S/D is to increase the HCl flow during growth steps.

  19. Double layers in space

    International Nuclear Information System (INIS)

    Carlqvist, P.

    1982-07-01

    For more than a decade it has been realised that electrostatic double layers are likely to occur in space. We briefly discuss the theoretical background of such double layers. Most of the paper is devoted to an account of the observational evidence for double layers in the ionosphere and magnetosphere of the Earth. Several different experiments are reviewed including rocket and satellite measurements and ground based observations. It is concluded that the observational evidence for double layers in space is very strong. The experimental results indicate that double layers with widely different properties may exist in space. (Author)

  20. Double layers in space

    International Nuclear Information System (INIS)

    Carlqvist, P.

    1982-01-01

    For more than a decade it has been realised that electrostatic double layers are likely to occur in space. The author briefly discusses the theoretical background of such double layers. Most of the paper is devoted to an account of the observational evidence for double layers in the ionosphere and magnetosphere of the Earth. Several different experiments are reviewed including rocket and satellite measurements and ground based observations. It is concluded that the observational evidence for double layers in space is very strong. The experimental results indicate that double layers with widely different properties may exist in space. (Auth.)