Silicon-to-silicon wafer bonding using evaporated glass

DEFF Research Database (Denmark)

Weichel, Steen; Reus, Roger De; Lindahl, M.

1998-01-01

Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

Science.gov (United States)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

International Nuclear Information System (INIS)

Vega, M; Lasorsa, C; Lerner, B; Perez, M; Granell, P

2016-01-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production. (paper)

DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

Directory of Open Access Journals (Sweden)

V. A. Solodukha

2016-01-01

Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

Science.gov (United States)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

Report on achievements in fiscal 1999. Development of energy usage rationalizing silicon manufacturing process (Development of manufacturing technology for mass production of silicon for solar cells); 1999 nendo energy shiyo gorika silicon seizo process kaihatsu seika hokokusho. Taiyo denchiyo silicon ryosanka seizo gijutsu no kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

Discussions were given on manufacture of raw material silicon for solar cells with regard to boron removal, solidification, finishing and refining of metallic impurities, refining of unutilized silicon scraps, and making them into wafers and solar cells after refining. This paper summarizes the achievements in fiscal 1999. With regard to purity deterioration due to contamination by boron containing silica powder generated during the boron removal in the manufacturing process, the facilities were modified resulting in the reduction thereof to 0.04 ppmw or less. Regarding the repetitive use of boron removing crucibles, the experiment identified the possibility of using them for more than three times. In trial fabrication of samples by using the solidification refining and cast integrated process, ingots of 550 mm square and about 300 mm high were obtained, which were sliced into 10-cm square materials for use as wafers. Measurement of the conversion efficiency has resulted in 13% or more which is almost equivalent in the center and edges of the ingot. It was revealed that solar cell wafers may be fabricated by using this process, which can use either the p-type low-resistance silicon scraps or the metallic silicon as the starting material. (NEDO)

Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Annual Subcontract Report, 1 October 2003--30 September 2004

Energy Technology Data Exchange (ETDEWEB)

Wohlgemuth, J.; Narayanan, M.

2005-03-01

The major objectives of this program are to continue the advancement of BP Solar polycrystalline silicon manufacturing technology. The program includes work in the following areas: Efforts in the casting area to increase ingot size, improve ingot material quality, and improve handling of silicon feedstock as it is loaded into the casting stations; developing wire saws to slice 100- m-thick silicon wafers on 290- m centers; developing equipment for demounting and subsequent handling of very thin silicon wafers; developing cell processes using 100- m-thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%; expanding existing in-line manufacturing data reporting systems to provide active process control; establishing a 50-MW (annual nominal capacity) green-field Mega-plant factory model template based on this new thin polycrystalline silicon technology; facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock.

Industrial Silicon Wafer Solar Cells

OpenAIRE

Neuhaus, Dirk-Holger; Münzer, Adolf

2007-01-01

In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

Direct Electroplating on Highly Doped Patterned Silicon Wafers

NARCIS (Netherlands)

Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

NARCIS (Netherlands)

Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

2005-01-01

The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

Science.gov (United States)

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Annual Subcontract Report, 1 April 2002--30 September 2003 (Revised)

Energy Technology Data Exchange (ETDEWEB)

Wohlgemuth, J.; Shea, S. P.

2004-04-01

The goal of BP Solar's Crystalline PVMaT program is to improve the present polycrystalline silicon manufacturing facility to reduce cost, improve efficiency, and increase production capacity. Key components of the program are: increasing ingot size; improving ingot material quality; improving material handling; developing wire saws to slice 100 ..mu..m thick silicon wafers on 200 ..mu..m centers; developing equipment for demounting and subsequent handling of very thin silicon wafers; developing cell processes using 100 ..mu..m thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%; expanding existing in-line manufacturing data reporting systems to provide active process control; establishing a 50 MW (annual nominal capacity) green-field Mega plant factory model template based on this new thin polycrystalline silicon technology; and facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock.

Surface etching technologies for monocrystalline silicon wafer solar cells

Science.gov (United States)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Final Subcontract Report, 1 April 2002--28 February 2006

Energy Technology Data Exchange (ETDEWEB)

Wohlgemuth, J.; Narayanan, M.

2006-07-01

The major objectives of this program were to continue advances of BP Solar polycrystalline silicon manufacturing technology. The Program included work in the following areas. (1) Efforts in the casting area to increase ingot size, improve ingot material quality, and improve handling of silicon feedstock as it is loaded into the casting stations. (2) Developing wire saws to slice 100-..mu..m-thick silicon wafers on 290-..mu..m-centers. (3) Developing equipment for demounting and subsequent handling of very thin silicon wafers. (4) Developing cell processes using 100-..mu..m-thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%. (5) Expanding existing in-line manufacturing data reporting systems to provide active process control. (6) Establishing a 50-MW (annual nominal capacity) green-field Mega-plant factory model template based on this new thin polycrystalline silicon technology. (7) Facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock..

High frequency guided wave propagation in monocrystalline silicon wafers

Science.gov (United States)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

Science.gov (United States)

Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

2012-03-01

Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

Low-cost silicon wafer dicing using a craft cutter

KAUST Repository

Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

2014-01-01

feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

Preparation and characterisation of immobilised humic acid on silicon wafer

International Nuclear Information System (INIS)

Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

2005-01-01

Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

Directory of Open Access Journals (Sweden)

Shisheng Cai

2017-03-01

Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

Sample pretreatment for the determination of metal impurities in silicon wafer

International Nuclear Information System (INIS)

Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

1999-01-01

The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Science.gov (United States)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Sol-gel bonding of silicon wafers

International Nuclear Information System (INIS)

Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

2005-01-01

Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

KAUST Repository

Yang, Xiaoming

2014-10-01

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

KAUST Repository

Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

2014-01-01

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

Silicon waveguides produced by wafer bonding

DEFF Research Database (Denmark)

Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

2005-01-01

X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

Radiation hardness of silicon detectors manufactured on wafers from various sources

International Nuclear Information System (INIS)

Dezillie, B.; Bates, S.; Glaser, M.; Lemeilleur, F.; Leroy, C.

1997-01-01

Impurity concentrations in the initial silicon material are expected to play an important role for the radiation hardness of silicon detectors, during their irradiation and for their evolution with time after irradiation. This work reports on the experimental results obtained with detectors manufactured using various float-zone (FZ) and epitaxial-grown material. Preliminary results comparing the changes in leakage current and full depletion voltage of FZ and epitaxial detectors as a function of fluence and of time after 10 14 cm -2 proton irradiation are given. The measurement of charge collection efficiency for epitaxial detectors is also presented. (orig.)

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

Science.gov (United States)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

The uses of Man-Made diamond in wafering applications

Science.gov (United States)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

2009-07-01

Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Lamb wave propagation in monocrystalline silicon wafers.

Science.gov (United States)

Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

CERN Multimedia

Honma, Alan

1999-01-01

Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

Silicon-Film(TM) Solar Cells by a Flexible Manufacturing System: Final Report, 16 April 1998 -- 31 March 2001

Energy Technology Data Exchange (ETDEWEB)

Rand, J.

2002-02-01

This report describes the overall goal to engineer and develop flexible manufacturing methods and equipment to process Silicon-Film solar cells and modules. Three major thrusts of this three-year effort were to: develop a new larger-area (208 mm x 208 mm) Silicon-Film solar cell, the APx-8; construct and operate a new high-throughput wafer-making system; and develop a 15-MW single-thread manufacturing process. Specific technical accomplishments from this period are: Increase solar cell area by 80%, increase the generation capacity of a Silicon-Film wafer-making system by 350%, use a new in-line HF etch system in solar cell production, design and develop an in-line NaOH etch system, eliminate cassettes in solar cell processing, and design a new family of module products.

Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

International Nuclear Information System (INIS)

Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

2006-01-01

The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

International Nuclear Information System (INIS)

Brehm, L.; Kregsamer, P.; Pianetta, P.

2000-01-01

It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

International Nuclear Information System (INIS)

Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

1999-01-01

The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

CERN Multimedia

Honma, Alan

1999-01-01

Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

Preliminary reduction of chromium ore using Si sludge generated in silicon wafer manufacturing process

Directory of Open Access Journals (Sweden)

Jung W.-G.

2018-01-01

Full Text Available In order to promote the recycling of by-product from Si wafer manufacturing process and to develop environment-friend and low cost process for ferrochrome alloy production, a basic study was performed on the preliminary reduction reaction between chromium ore and the Si sludge, comprised of SiC and Si particles, which is recovered from the Si wafer manufacturing process for the semiconductor and solar cell industries. Pellets were first made by mixing chromium ore, Si sludge, and some binders in the designed mixing ratios and were then treated at different temperatures in the 1116°C–1388°C range in an ambient atmosphere. Cordierite and SiO2 were confirmed to be formed in the products after the reduction. Additionally, metal particles were observed in the product with Fe, Cr, and Si components. It is found that temperatures above 1300°C are necessary for the reduction of the chromium ore by the Si sludge. The reduction ratio for Fe was evaluated quantitatively for our experimental conditions, and the proper mixing ratio was suggested for the pre-reduction of the chromium ore by the Si sludge. This study provides basic information for the production of ferrochrome alloys on the pre-reduction of chromium ore using Si sludge.

Cohesive zone model for direct silicon wafer bonding

Science.gov (United States)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

International Nuclear Information System (INIS)

Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

2014-01-01

Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

Fiscal 2000 achievement report. Development of energy use rationalization-oriented silicon manufacturing process (Development of silicon substrate manufacturing technology for high-quality solar cell); 2000 nendo shin energy sangyo gijutsu sogo kaihatsu kiko kyodo kenkyu gyomu seika hokokusho. Energy shiyo gorika silicon seizo process kaihatsu (Kohinshitsu taiyodenchiyou silicon kiban seizo gijutsu no kaihatsu)

Energy Technology Data Exchange (ETDEWEB)

NONE

2001-03-01

Research and development was conducted for enhancing productivity and energy conservation by rendering continuous and automatic the electromagnetic casting process for manufacturing polycrystalline silicon substrates for solar cells. In the manufacture of ingots for substrates by continuous electromagnetic casting, the chuck type system for feeding power to the melt plasma was replaced by a roller type system, and the power feeding position was moved to the high temperature region. Also, an on-line ingot slicing technique was established. In the manufacture of substrates at a slicing rate of 300 {mu}m/minute, productivity of 115,000 wafers/month, yield of 98%, and thickness tolerance of 30 {mu}m were achieved. A high-speed cleaning technique was developed using a jet stream, by which the cleaning time was reduced to 5 minutes and the slurry recovery rate was elevated to 95%. Based on these, substrate-related costs in the case of 100 MW/year production was calculated, which resulted in a cost of 98.8 yen/wafer (target: 103.3 yen/wafer) for manufacturing 15 cm square substrates from ingots and in a 15 cm square substrate slicing and cleaning cost of 135.1 yen/wafer (target: 135.4 yen/wafer). (NEDO)

High Volume Manufacturing of Silicon-Film Solar Cells and Modules; Final Subcontract Report, 26 February 2003 - 30 September 2003

Energy Technology Data Exchange (ETDEWEB)

Rand, J. A.; Culik, J. S.

2005-10-01

The objective of the PV Manufacturing R&D subcontract was to continue to improve AstroPower's technology for manufacturing Silicon-Film* wafers, solar cells, and modules to reduce costs, and increase production yield, throughput, and capacity. As part of the effort, new technology such as the continuous back metallization screen-printing system and the laser scribing system were developed and implemented. Existing processes, such as the silicon nitride antireflection coating system and the fire-through process were optimized. Improvements were made to the statistical process control (SPC) systems of the major manufacturing processes: feedstock preparation, wafer growth, surface etch, diffusion, and the antireflection coating process. These process improvements and improved process control have led to an increase of 5% relative power, and nearly 15% relative improvement in mechanical and visual yield.

Decade of PV Industry R and D Advances in Silicon Module Manufacturing

Energy Technology Data Exchange (ETDEWEB)

Symko-Davis, M.; Mitchell, R.L.; Witt, C.E.; Thomas, H.P. [National Renewable Energy Laboratory; King, R.[U.S. Department of Energy; Ruby, D.S. [Sandia National Laboratories

2001-01-18

The US Photovoltaic (PV) industry has made significant technical advances in crystalline silicon (Si) module manufacturing through the PV Manufacturing R and D Project during the past decade. Funded Si technologies in this project have been Czochralski, cast polycrystalline, edge-defined film-fed growth (EFG) ribbon, string ribbon, and Si-film. Specific R and D Si module-manufacturing categories that have shown technical growth and will be discussed are in crystal growth and processing, wafering, cell fabrication, and module manufacturing. These R and D advancements since 1992 have contributed to a 30% decrease in PV manufacturing costs and stimulated a sevenfold increase in PV production capacity.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

International Nuclear Information System (INIS)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-01-01

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

Science.gov (United States)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

External self-gettering of nickel in float zone silicon wafers

Science.gov (United States)

Gay, N.; Martinuzzi, S.

1997-05-01

During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

2016-02-16

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

Characterization of silicon-on-insulator wafers

Science.gov (United States)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

International Nuclear Information System (INIS)

Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

2003-01-01

Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

Chemical polishing of epitoxial silicon wafer

International Nuclear Information System (INIS)

Osada, Shohei

1978-01-01

SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

A review of manufacturing metrology for improved reliability of silicon photovoltaic modules

Science.gov (United States)

Davis, Kristopher O.; Walters, Joseph; Schneller, Eric; Seigneur, Hubert; Brooker, R. Paul; Scardera, Giuseppe; Rodgers, Marianne P.; Mohajeri, Nahid; Shiradkar, Narendra; Dhere, Neelkanth G.; Wohlgemuth, John; Rudack, Andrew C.; Schoenfeld, Winston V.

2014-10-01

In this work, the use of manufacturing metrology across the supply chain to improve crystalline silicon (c-Si) photovoltaic (PV) module reliability and durability is addressed. Additionally, an overview and summary of a recent extensive literature survey of relevant measurement techniques aimed at reducing or eliminating the probability of field failures is presented. An assessment of potential gaps is also given, wherein the PV community could benefit from new research and demonstration efforts. This review is divided into three primary areas representing different parts of the c-Si PV supply chain: (1) feedstock production, crystallization and wafering; (2) cell manufacturing; and (3) module manufacturing.

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

Science.gov (United States)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

International Nuclear Information System (INIS)

Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

2006-01-01

An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

Industrial Silicon Wafer Solar Cells

Directory of Open Access Journals (Sweden)

Dirk-Holger Neuhaus

2007-01-01

Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

Directory of Open Access Journals (Sweden)

S. A. Chizhik

2013-01-01

Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

Science.gov (United States)

Kulshreshtha, Prashant Kumar

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

Science.gov (United States)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Peptide and protein loading into porous silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

2008-02-15

The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

Science.gov (United States)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

Science.gov (United States)

Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

2013-04-01

In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

Science.gov (United States)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Eutectic and solid-state wafer bonding of silicon with gold

International Nuclear Information System (INIS)

Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

2012-01-01

Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

Science.gov (United States)

Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

2018-06-01

Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

Directory of Open Access Journals (Sweden)

Kae Dal Kwack

2011-01-01

Full Text Available A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

Science.gov (United States)

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

Science.gov (United States)

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light. PMID:22319353

"Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

Science.gov (United States)

Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

2013-04-01

During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

NARCIS (Netherlands)

Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

Science.gov (United States)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

International Nuclear Information System (INIS)

Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

2017-01-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

International Nuclear Information System (INIS)

Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

2007-01-01

The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

2014-02-07

Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

Contacting graphene in a 200 mm wafer silicon technology environment

Science.gov (United States)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

Science.gov (United States)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Pulsed Laser Interactions with Silicon Nano structures in Emitter Formation

International Nuclear Information System (INIS)

Huat, V.L.C.; Leong, C.S.; Kamaruzzaman Sopian, Saleem Hussain Zaidi

2015-01-01

Silicon wafer thinning is now approaching fundamental limits for wafer thickness owing to thermal expansion mismatch between Al and Si, reduced yields in wet-chemical processing as a result of fragility, and reduced optical absorption. An alternate manufacturing approach is needed to eliminate current manufacturing issues. In recent years, pulsed lasers have become readily available and costs have been significantly reduced. Pulsed laser interactions with silicon, in terms of micromachining, diffusions, and edge isolation, are well known, and have become industrial manufacturing tools. In this paper, pulsed laser interactions with silicon nano structures were identified as the most desirable solution for the fundamental limitations discussed above. Silicon nano structures have the capability for extremely high absorption that significantly reduces requirements for laser power, as well as thermal shock to the thinner wafer. Laser-assisted crystallization, in the presence of doping materials, leads to nano structure profiles that are highly desirable for sunlight absorption. The objective of this paper is the replacement of high temperature POCl_3 diffusion by laser-assisted phosphorus layers. With these improvements, complete low-temperature processing of thinner wafers was achievable with 3.7 % efficiency. Two-dimensional laser scanning was proved to be able to form uniformly annealed surfaces with higher fill factor and open-circuit voltage. (author)

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

Science.gov (United States)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

Process induced sub-surface damage in mechanically ground silicon wafers

International Nuclear Information System (INIS)

Yang Yu; De Munck, Koen; Teixeira, Ricardo Cotrin; Swinnen, Bart; De Wolf, Ingrid; Verlinden, Bert

2008-01-01

Micro-Raman spectroscopy, scanning electron microcopy, atomic force microscopy and preferential etching were used to characterize the sub-surface damage induced by the rough and fine grinding steps used to make ultra-thin silicon wafers. The roughly and ultra-finely ground silicon wafers were examined on both the machined (1 0 0) planes and the cross-sectional (1 1 0) planes. They reveal similar multi-layer damage structures, consisting of amorphous, plastically deformed and elastically stressed layers. However, the thickness of each layer in the roughly ground sample is much higher than its counterpart layers in the ultra-finely ground sample. The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30 MPa, respectively. In each case, the top amorphous layer is believed to be the result of sequential phase transformations (Si-I to Si-II to amorphous Si). These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in rough grinding, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks

Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

Directory of Open Access Journals (Sweden)

Di Di

2014-01-01

Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

Directory of Open Access Journals (Sweden)

Min-Kyoo Song

2013-01-01

Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

PV Cz silicon manufacturing technology improvements

Science.gov (United States)

Jester, T.

1995-09-01

This describes work done in the final phase of a 3-y, 3-phase contract to demonstrate cost reductions and improvements in manufacturing technology. The work focused on near-term projects in the SSI (Siemens Solar Industries) Czochralski (Cz) manufacturing facility in Camarillo, CA; the final phase was concentrated in areas of crystal growth, wafer technology, and environmental, safety, and health issues. During this period: (1) The crystal-growing operation improved with increased growth capacity; (2) Wafer processing with wire saws continued to progress; the wire saws yielded almost 50 percent more wafers per inch in production. The wire saws needs less etching, too; (3) Cell processing improvements focused on better handling and higher mechanical yield. The cell electrical distribution improved with a smaller standard deviation in the distribution; and (4) Module designs for lower material and labor costs continued, with focus on a new junction box, larger modules with larger cells, and less costly framing techniques. Two modules demonstrating these cost reductions were delivered during this phase.

Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

Energy Technology Data Exchange (ETDEWEB)

Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

2012-09-15

We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

Tests of a silicon wafer based neutron collimator

International Nuclear Information System (INIS)

Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

2001-01-01

A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

Tests of a silicon wafer based neutron collimator

CERN Document Server

Cussen, L D; Anderson, I S; Hoeghoj, P

2001-01-01

A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

Coherent spin transport through a 350 micron thick silicon wafer.

Science.gov (United States)

Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

2007-10-26

We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

Science.gov (United States)

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

Science.gov (United States)

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

Silicon hybrid integration

International Nuclear Information System (INIS)

Li Xianyao; Yuan Taonu; Shao Shiqian; Shi Zujun; Wang Yi; Yu Yude; Yu Jinzhong

2011-01-01

Recently,much attention has concentrated on silicon based photonic integrated circuits (PICs), which provide a cost-effective solution for high speed, wide bandwidth optical interconnection and optical communication.To integrate III-V compounds and germanium semiconductors on silicon substrates,at present there are two kinds of manufacturing methods, i.e., heteroepitaxy and bonding. Low-temperature wafer bonding which can overcome the high growth temperature, lattice mismatch,and incompatibility of thermal expansion coefficients during heteroepitaxy, has offered the possibility for large-scale heterogeneous integration. In this paper, several commonly used bonding methods are reviewed, and the future trends of low temperature wafer bonding envisaged. (authors)

Multiproject wafers: not just for million-dollar mask sets

Science.gov (United States)

Morse, Richard D.

2003-06-01

With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

Science.gov (United States)

Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

2017-09-01

Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

Ambient plasma treatment of silicon wafers for surface passivation recovery

Science.gov (United States)

Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

2017-08-01

In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

Science.gov (United States)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Electrical Interconnections Through CMOS Wafers

DEFF Research Database (Denmark)

Rasmussen, Frank Engel

2003-01-01

Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

Denuded zone in Czochralski silicon wafer with high carbon content

International Nuclear Information System (INIS)

Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

2006-01-01

The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

Denuded zone in Czochralski silicon wafer with high carbon content

Science.gov (United States)

Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

2006-12-01

The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

Directory of Open Access Journals (Sweden)

Gnilenko A. B.

2012-02-01

Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

Directory of Open Access Journals (Sweden)

Xianshu eLuo

2015-04-01

Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

A Reuse Evaluation for Solar-Cell Silicon Wafers via Shift Revolution and Tool Rotation Using Magnetic Assistance in Ultrasonic Electrochemical Micromachining

Directory of Open Access Journals (Sweden)

P. S. Pa

2013-01-01

Full Text Available A new reuse fabrication using a tool module with rotation and revolution through a process of magnetic assistance in ultrasonic electrochemical micromachining (UEMM for removal of the surface layers from silicon wafers of solar cells is demonstrated. The target of the proposed reuse fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach to removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. The high revolution speed of the shift with the high rotation speed of the designed tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. High frequency and high power of ultrasonic with large electrolyte flow rate and high magnetic strengths with a small distance between the two magnets provide a large discharge effect and good removal; only a short period of time is required to remove the epoxy film and Si3N4 layer easily and cleanly.

Effect of PECVD SiNx/SiOy Nx –Si interface property on surface passivation of silicon wafer

International Nuclear Information System (INIS)

Jia Xiao-Jie; Zhou Chun-Lan; Zhou Su; Wang Wen-Jing; Zhu Jun-Jie

2016-01-01

It is studied in this paper that the electrical characteristics of the interface between SiO y N x /SiN x stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiO y N x layer on interface parameters, such as interface state density Di t and fixed charge Q f , and the surface passivation quality of silicon are observed. Capacitance–voltage measurements reveal that inserting a thin SiO y N x layer between the SiN x and the silicon wafer can suppress Q f in the film and D it at the interface. The positive Q f and D it and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiO y N x film increasing. Prepared by deposition at a low temperature and a low ratio of N 2 O/SiH 4 flow rate, the SiO y N x /SiN x stacks result in a low effective surface recombination velocity (S eff ) of 6 cm/s on a p-type 1 Ω·cm–5 Ω·cm FZ silicon wafer. The positive relationship between S eff and D it suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. (paper)

Detection of trace contamination of copper on a silicon wafer with TXRF

International Nuclear Information System (INIS)

Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

2000-01-01

The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

Formation of cross-cutting structures with different porosity on thick silicon wafers

Directory of Open Access Journals (Sweden)

Vera A. Yuzova

2017-06-01

The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

NTD Silicon; Product Characteristics, Main Uses and Growth Potential

International Nuclear Information System (INIS)

Hansen, M. G.; Bjorling, C. F.

2013-01-01

Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain

NTD Silicon; Product Characteristics, Main Uses and Growth Potential

Energy Technology Data Exchange (ETDEWEB)

Hansen, M. G.; Bjorling, C. F. [Topsil Semiconductor Materials A/S, Odense (Denmark)

2013-07-01

Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain.

The impact of silicon feedstock on the PV module cost

NARCIS (Netherlands)

del Coso, G.; del Cañizo, C.; Sinke, W.C.

2010-01-01

The impact of the use of new (solar grade) silicon feedstock materials on the manufacturing cost of wafer-based crystalline silicon photovoltaic modules is analyzed considering effects of material cost, efficiency of utilisation, and quality. Calculations based on data provided by European industry

High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

CERN Document Server

Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

2003-01-01

Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

Methods and mechanisms of gettering of silicon structures in the production of integrated circuits

Directory of Open Access Journals (Sweden)

Pilipenko V. A.

2013-05-01

Full Text Available Increasing the degree of integration of hardware components imposes more stringent requirements for the reduction of the concentration of contaminants and oxidation stacking faults in the original silicon wafers with its preservation in the IC manufacturing process cycle. This causes high relevance of the application of gettering in modern microelectronic technology. The existing methods of silicon wafers gettering and the mechanisms of their occurrence are considered.

A repeatable and scalable fabrication method for sharp, hollow silicon microneedles

Science.gov (United States)

Kim, H.; Theogarajan, L. S.; Pennathur, S.

2018-03-01

Scalability and manufacturability are impeding the mass commercialization of microneedles in the medical field. Specifically, microneedle geometries need to be sharp, beveled, and completely controllable, difficult to achieve with microelectromechanical fabrication techniques. In this work, we performed a parametric study using silicon etch chemistries to optimize the fabrication of scalable and manufacturable beveled silicon hollow microneedles. We theoretically verified our parametric results with diffusion reaction equations and created a design guideline for a various set of miconeedles (80-160 µm needle base width, 100-1000 µm pitch, 40-50 µm inner bore diameter, and 150-350 µm height) to show the repeatability, scalability, and manufacturability of our process. As a result, hollow silicon microneedles with any dimensions can be fabricated with less than 2% non-uniformity across a wafer and 5% deviation between different processes. The key to achieving such high uniformity and consistency is a non-agitated HF-HNO3 bath, silicon nitride masks, and surrounding silicon filler materials with well-defined dimensions. Our proposed method is non-labor intensive, well defined by theory, and straightforward for wafer scale mass production, opening doors to a plethora of potential medical and biosensing applications.

Development of thin film measurement program of wafer for spin etcher

International Nuclear Information System (INIS)

Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

2001-01-01

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

Development of thin film measurement program of wafer for spin etcher

Energy Technology Data Exchange (ETDEWEB)

Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

2001-11-15

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

Science.gov (United States)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

Science.gov (United States)

Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

2013-05-06

Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

Physical mechanisms of Cu-Cu wafer bonding

International Nuclear Information System (INIS)

Rebhan, B.

2014-01-01

Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

Science.gov (United States)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

International Nuclear Information System (INIS)

Moslehi, M.M.; Davis, C.

1989-01-01

Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

International Nuclear Information System (INIS)

Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

2006-01-01

The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

Analysis of the silicon market: Will thin films profit?

International Nuclear Information System (INIS)

Sark, W.G.J.H.M. van; Brandsen, G.W.; Fleuster, M.; Hekkert, M.P.

2007-01-01

The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010

Analysis of the silicon market: Will thin films profit?

Energy Technology Data Exchange (ETDEWEB)

Sark, W.G.J.H.M. van; Brandsen, G.W. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Science, Technology and Society; Fleuster, M. [Solland Solar Energy, Heerlen (Netherlands); Hekkert, M.P. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Innovation Studies

2007-06-15

The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010. (author)

Sol-gel bonding of silicon wafers

International Nuclear Information System (INIS)

Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

2005-01-01

Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

KAUST Repository

Bahabry, Rabab R.

2018-01-02

Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

KAUST Repository

Bahabry, Rabab R.; Kutbee, Arwa T.; Khan, Sherjeel M.; Sepulveda, Adrian C.; Wicaksono, Irmandy; Nour, Maha A.; Wehbe, Nimer; Almislem, Amani Saleh Saad; Ghoneim, Mohamed T.; Sevilla, Galo T.; Syed, Ahad; Shaikh, Sohail F.; Hussain, Muhammad Mustafa

2018-01-01

Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

Energy Technology Data Exchange (ETDEWEB)

Hegedus, Steven S. [Univ. of Delaware, Newark, DE (United States)

2015-09-08

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerfless techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to

Low cost back contact heterojunction solar cells on thin c-Si wafers. Integrating laser and thin film processing for improved manufacturability

Energy Technology Data Exchange (ETDEWEB)

Hegedus, Steven S. [Univ. of Delaware, Newark, DE (United States)

2015-09-08

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerfless techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to

Quantitative analysis of phosphosilicate glass films on silicon wafers for calibration of x-ray fluorescence spectrometry standards

International Nuclear Information System (INIS)

Weissman, S.H.

1983-01-01

The phosphorus and silicon contents of phosphosilicate glass films deposited by chemical vapor deposition (CVD) on silicon wafers were determined. These films were prepared for use as x-ray fluorescence (XRF) spectrometry standards. The thin films were removed from the wafer by etching with dilute hydrofluoric acid, and the P and Si concentrations in solution were determined by inductively coupled plasma atomic emission spectroscopy (ICP). The calculated phosphorus concentration ranged from 2.2 to 12 wt %, with an uncertainty of 2.73 to 10.1 relative percent. Variation between the calculated weight loss (summation of P 2 O 5 and SiO 2 amounts as determined by ICP) and the measured weight loss (determined gravimetrically) averaged 4.9%. Results from the ICP method, Fourier transform-infrared spectroscopy (FT-IR), dispersive infrared spectroscopy, electron microprobe, and x-ray fluorescence spectroscopy for the same samples are compared

Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

2016-02-15

Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

Silicon pore optics for future x-ray telescopes

DEFF Research Database (Denmark)

Wille, Eric; Bavdaz, Marcos; Wallace, Kotska

2017-01-01

arcsec or better. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is being developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor...... industry. We present the recent upgrades made to the manufacturing processes and equipment, ranging from the manufacture of single mirror plates towards complete focusing mirror modules mounted in flight configuration, and results from first vibration tests. The performance of the mirror modules is tested...

Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

Science.gov (United States)

Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

2018-01-01

Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

Synthesis of thermoresponsive poly(N-isopropylacrylamide) brush on silicon wafer surface via atom transfer radical polymerization

Energy Technology Data Exchange (ETDEWEB)

Turan, Eylem; Demirci, Serkan [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey); Caykara, Tuncer, E-mail: caykara@gazi.edu.t [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey)

2010-08-31

Thermoresponsive poly(N-isopropylacrylamide) [poly(NIPAM)] brush on silicon wafer surface was prepared by combining the self-assembled monolayer of initiator and atom transfer radical polymerization (ATRP). The resulting polymer brush was characterized by in situ reflectance Fourier transform infrared spectroscopy, atomic force microscopy and ellipsometry techniques. Gel permeation chromatography determination of the number-average molecular weight and polydispersity index of the brush detached from the silicon wafer surface suggested that the surface-initiated ATRP method can provide relatively homogeneous polymer brush. Contact angle measurements exhibited a two-stage increase upon heating over the board temperature range 25-45 {sup o}C, which is in contrast to the fact that free poly(NIPAM) homopolymer in aqueous solution exhibits a phase transition at ca. 34 {sup o}C within a narrow temperature range. The first de-wetting transition takes place at 27 {sup o}C, which can be tentatively attributed to the n-cluster induced collapse of the inner region of poly(NIPAM) brush close to the silicon surface; the second de-wetting transition occurs at 38 {sup o}C, which can be attributed to the outer region of poly(NIPAM) brush, possessing much lower chain density compared to that of the inner part.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

Science.gov (United States)

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Analysis of borophosphosilicate glass layers on silicon wafers by X-ray emission from photon and electron excitation

International Nuclear Information System (INIS)

Elgersma, O.; Borstrok, J.J.M.

1989-01-01

Phosphorus and oxygen concentrations in the homogeneous layer of borosilicate glass (BPSG) deposited on Si-integrated circuits are determined by X-ray fluorescence from photon excitation. The X-ray emission from electron excitation in an open X-ray tube instrument yields a sufficiently precise determination of the boron content. The thickness of the layer can be derived from silicon Kα-fluorescence. A calibration model is proposed for photon as well as for electron excitation. The experimentally determined parameters in this model well agree with those derived from fundamental parameters for X-ray absorption and emission. The chemical surrounding of silicon affects strongly the peak profile of the silicon Kβ-emission. This enables to distinguish emission from the silicon atoms in the wafer and from the silicon atoms in the silicon oxide complexes of the BPSG-layer. (author)

Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

International Nuclear Information System (INIS)

Mou, Chun-Yueh; Yuan, Wei-Li; Shih, Chih-Hsin

2013-01-01

Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate

Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Mou, Chun-Yueh, E-mail: cymou165@gmail.com; Yuan, Wei-Li; Shih, Chih-Hsin

2013-06-30

Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate.

Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

International Nuclear Information System (INIS)

Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

2005-01-01

This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

CHARACTERIZATION OF THE ELECTROPHYSICAL PROPERTIES OF SILICON-SILICON DIOXIDE INTERFACE USING PROBE ELECTROMETRY METHODS

Directory of Open Access Journals (Sweden)

V. А. Pilipenko

2017-01-01

Full Text Available Introduction of submicron design standards into microelectronic industry and a decrease of the gate dielectric thickness raise the importance of the analysis of microinhomogeneities in the silicon-silicon dioxide system. However, there is very little to no information on practical implementation of probe electrometry methods, and particularly scanning Kelvin probe method, in the interoperational control of real semiconductor manufacturing process. The purpose of the study was the development of methods for nondestructive testing of semiconductor wafers based on the determination of electrophysical properties of the silicon-silicon dioxide interface and their spatial distribution over wafer’s surface using non-contact probe electrometry methods.Traditional C-V curve analysis and scanning Kelvin probe method were used to characterize silicon- silicon dioxide interface. The samples under testing were silicon wafers of KEF 4.5 and KDB 12 type (orientation <100>, diameter 100 mm.Probe electrometry results revealed uniform spatial distribution of wafer’s surface potential after its preliminary rapid thermal treatment. Silicon-silicon dioxide electric potential values were also higher after treatment than before it. This potential growth correlates with the drop in interface charge density. At the same time local changes in surface potential indicate changes in surface layer structure.Probe electrometry results qualitatively reflect changes of interface charge density in silicon-silicon dioxide structure during its technological treatment. Inhomogeneities of surface potential distribution reflect inhomogeneity of damaged layer thickness and can be used as a means for localization of interface treatment defects.

Wafer of Intel Pentium 4 Prescott Chips

CERN Multimedia

Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

International Nuclear Information System (INIS)

Takahara, Hikari; Mori, Yoshihiro; Shibata, Harumi; Shimazaki, Ayako; Shabani, Mohammad B.; Yamagami, Motoyuki; Yabumoto, Norikuni; Nishihagi, Kazuo; Gohshi, Yohichi

2013-01-01

Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10 9 and 5 × 10 10 atoms/cm 2 Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO 2 , silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10 10 atoms/cm 2 . • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

Science.gov (United States)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Safety procedures used during the manufacturing of amorphous silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Dickson, C R

1987-01-01

The Solarex Thin Film Division is a leader in the manufacturing of amorphous-silicon products for sale in domestic and foreign markets. Similarly, Solarex assumes a leadership role in recognizing the importance of safety in a manufacturing environment. Although many of the safety issues are similar to those in the semiconductor industry, this paper presents topics specific to amorphous silicon technology and the manufacturing ,f amorphous-silicon products. These topics are deposition of conducting transparent oxides (CTOs), amorphous silicon deposition, laser scribing, processing chemicals, fire prevention and administrative responsibilities.

Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

Science.gov (United States)

Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

Use of porous silicon to minimize oxidation induced stacking fault defects in silicon

International Nuclear Information System (INIS)

Shieh, S.Y.; Evans, J.W.

1992-01-01

This paper presents methods for minimizing stacking fault defects, generated during oxidation of silicon, include damaging the back of the wafer or depositing poly-silicon on the back. In either case a highly defective structure is created and this is capable of gettering either self-interstitials or impurities which promote nucleation of stacking fault defects. A novel method of minimizing these defects is to form a patch of porous silicon on the back of the wafer by electrochemical etching. Annealing under inert gas prior to oxidation may then result in the necessary gettering. Experiments were carried out in which wafers were subjected to this treatment. Subsequent to oxidation, the wafers were etched to remove oxide and reveal defects. The regions of the wafer adjacent to the porous silicon patch were defect-free, whereas remote regions had defects. Deep level transient spectroscopy has been used to examine the gettering capability of porous silicon, and the paper discusses the mechanism by which the porous silicon getters

Locally-enhanced light scattering by a monocrystalline silicon wafer

Directory of Open Access Journals (Sweden)

Li Ma

2018-03-01

Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

Manufacturing: SiC Power Electronics for Variable Frequency Motor Drives

Energy Technology Data Exchange (ETDEWEB)

Horowitz, Kelsey A [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Bench Reese, Samantha R [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Remo, Timothy W [National Renewable Energy Laboratory (NREL), Golden, CO (United States)

2017-08-15

This brochure, published as an annual research highlight of the Clean Energy Manufacturing Analysis Center (CEMAC), summarizes CEMAC analysis of silicon carbide (SiC) power electronics for variable frequency motor drives. The key finding presented is that variations in manufacturing expertise, yields, and access to existing facilities impact regional costs and manufacturing location decisions for SiC ingots, wafers, chips, and power modules more than do core country-specific factors such as labor and electricity costs.

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

Science.gov (United States)

Lee, Jeffrey; McGarvey, Steve

2013-04-01

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

Manufacturing and characterization of bent silicon crystals for studies of coherent interactions with negatively charged particles beams

Energy Technology Data Exchange (ETDEWEB)

Germogli, G.; Mazzolari, A.; Bandiera, L.; Bagli, E.; Guidi, V.

2015-07-15

Efficient steering of GeV-energy negatively charged particle beams was demonstrated to be possible with a new generation of thin bent silicon crystals. Suitable crystals were produced at the Sensor Semiconductor Laboratory of Ferrara starting from Silicon On Insulator wafers, adopting proper revisitation of silicon micromachining techniques such as Low Pressure Chemical Vapor Deposition, photolithography and anisotropic chemical etching. Mechanical holders, which allow to properly bend the crystal and to reduce unwanted torsions, were employed. Crystallographic directions and crystal holder design were optimized in order to excite quasi-mosaic effect along (1 1 1) planes. Prior to exposing the crystal to particle beams, a full set of characterizations were performed. Infrared interferometry was used to measure crystal thickness with high accuracy. White-light interferometry was employed to characterize surface deformational state and its torsion. High-resolution X-rays diffraction was used to precisely measure crystal bending angle along the beam. Manufactured crystals were installed and tested at the MAMI MAinz MIcrotron to steer sub-GeV electrons, and at SLAC to deflect an electron beam in the 1 to 10 GeV energy range.

Cost-effective method of manufacturing a 3D MEMS optical switch

Science.gov (United States)

Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

2009-02-01

growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto

2014-02-25

In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

Science.gov (United States)

Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

2018-02-01

We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

Wafer bonding applications and technology

CERN Document Server

Gösele, Ulrich

2004-01-01

During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

International Nuclear Information System (INIS)

Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

2014-01-01

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

Science.gov (United States)

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

Science.gov (United States)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

Science.gov (United States)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

Energy Technology Data Exchange (ETDEWEB)

Tiriolo, Raffaele [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Rangnekar, Neel [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Zhang, Han [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Shete, Meera [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Bai, Peng [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Nelson, John [Characterization Facility, University of Minnesota, 12 Shepherd Labs, 100 Union St. S.E. Minneapolis MN 55455 USA; Karapetrova, Evguenia [Surface Scattering and Microdiffraction, X-ray Science Division, Argonne National Laboratory, 9700 S. Cass Ave, Building 438-D002 Argonne IL 60439 USA; Macosko, Christopher W. [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Siepmann, Joern Ilja [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Lamanna, Ernesto [Department of Health Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Lavano, Angelo [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Tsapatsis, Michael [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA

2017-05-08

A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.

Interfacial Characteristics of TiN Coatings on SUS304 and Silicon Wafer Substrates with Pulsed Laser Thermal Shock

International Nuclear Information System (INIS)

Seo, Nokun; Jeon, Seol; Choi, Youngkue; Shin, Hyun-Gyoo; Lee, Heesoo; Jeon, Min-Seok

2014-01-01

TiN coatings prepared on different substrates that had different coefficients of thermal expansion were subjected to pulsed laser thermal shock and observed by using FIB milling to compare the deterioration behaviors. TiN coating on SUS304, which had a larger CTE (⁓17.3 × 10 - 6 /℃) than the coating was degraded with pores and cracks on the surface and showed significant spalling of the coating layer over a certain laser pulses. TiN coating on silicon wafer with a smaller CTE value, ⁓4.2 × 10‒6 /℃, than the coating exhibited less degradation of the coating layer at the same ablation condition. Cracks propagated at the interface were observed in the coating on the silicon wafer, which induced a compressive stress to the coating. The coating on the SUS304 showed less interface cracks while the tensile stress was applied to the coating. Delamination of the coating layer related to the intercolumnar cracks at the interface was observed in both coatings through bright-field TEM analysis.

Floating Silicon Method

Energy Technology Data Exchange (ETDEWEB)

Kellerman, Peter

2013-12-21

The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

International Nuclear Information System (INIS)

Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

2012-01-01

Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

International Nuclear Information System (INIS)

Ngo, H-D; Hiess, Andre; Seidemann, Volker; Studzinski, Daniel; Lange, Martin; Leib, Juergen; Shariff, Dzafir; Ashraf, Huma; Steel, Mike; Atabo, Lilian; Reast, Jon

2006-01-01

This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained and plasma configurations are described elsewhere. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters

Solid state laser applications in photovoltaics manufacturing

Science.gov (United States)

Dunsky, Corey; Colville, Finlay

2008-02-01

Photovoltaic energy conversion devices are on a rapidly accelerating growth path driven by increasing government and societal pressure to use renewable energy as part of an overall strategy to address global warming attributed to greenhouse gas emissions. Initially supported in several countries by generous tax subsidies, solar cell manufacturers are relentlessly pushing the performance/cost ratio of these devices in a quest to reach true cost parity with grid electricity. Clearly this eventual goal will result in further acceleration in the overall market growth. Silicon wafer based solar cells are currently the mainstay of solar end-user installations with a cost up to three times grid electricity. But next-generation technology in the form of thin-film devices promises streamlined, high-volume manufacturing and greatly reduced silicon consumption, resulting in dramatically lower per unit fabrication costs. Notwithstanding the modest conversion efficiency of thin-film devices compared to wafered silicon products (around 6-10% versus 15-20%), this cost reduction is driving existing and start-up solar manufacturers to switch to thin-film production. A key aspect of these devices is patterning large panels to create a monolithic array of series-interconnected cells to form a low current, high voltage module. This patterning is accomplished in three critical scribing processes called P1, P2, and P3. Lasers are the technology of choice for these processes, delivering the desired combination of high throughput and narrow, clean scribes. This paper examines these processes and discusses the optimization of industrial lasers to meet their specific needs.

Free-world microelectronic manufacturing equipment

Science.gov (United States)

Kilby, J. S.; Arnold, W. H.; Booth, W. T.; Cunningham, J. A.; Hutcheson, J. D.; Owen, R. W.; Runyan, W. R.; McKenney, Barbara L.; McGrain, Moira; Taub, Renee G.

1988-12-01

Equipment is examined and evaluated for the manufacture of microelectronic integrated circuit devices and sources for that equipment within the Free World. Equipment suitable for the following are examined: single-crystal silicon slice manufacturing and processing; required lithographic processes; wafer processing; device packaging; and test of digital integrated circuits. Availability of the equipment is also discussed, now and in the near future. Very adequate equipment for most stages of the integrated circuit manufacturing process is available from several sources, in different countries, although the best and most widely used versions of most manufacturing equipment are made in the United States or Japan. There is also an active market in used equipment, suitable for manufacture of capable integrated circuits with performance somewhat short of the present state of the art.

Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

Science.gov (United States)

Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

2013-08-20

To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

Reduction of absorption loss in multicrystalline silicon via combination of mechanical grooving and porous silicon

Energy Technology Data Exchange (ETDEWEB)

Ben Rabha, Mohamed; Mohamed, Seifeddine Belhadj; Dimassi, Wissem; Gaidi, Mounir; Ezzaouia, Hatem; Bessais, Brahim [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, Technopole de Borj-Cedria, BP 95, 2050 Hammam-Lif (Tunisia)

2011-03-15

Surface texturing of silicon wafer is a key step to enhance light absorption and to improve the solar cell performances. While alkaline-texturing of single crystalline silicon wafers was well established, no efficient chemical solution has been successfully developed for multicrystalline silicon wafers. Thus, the use of alternative new methods for effective texturization of multicrystalline silicon is worth to be investigated. One of the promising texturing techniques of multicrystalline silicon wafers is the use of mechanical grooves. However, most often, physical damages occur during mechanical grooves of the wafer surface, which in turn require an additional step of wet processing-removal damage. Electrochemical surface treatment seems to be an adequate solution for removing mechanical damage throughout porous silicon formation. The topography of untreated and porous silicon-treated mechanically textured surface was investigated using scanning electron microscopy (SEM). As a result of the electrochemical surface treatment, the total reflectivity drops to about 5% in the 400-1000 nm wavelength range and the effective minority carrier diffusion length enhances from 190 {mu}m to about 230 {mu}m (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Achievement Report for fiscal 1997 on developing a silicon manufacturing process with reduced energy consumption. Development of silicon mass-production manufacturing technology for solar cells; 1997 nendo energy shiyo gorika silicon seizo process kaihatsu. Taiyo denchiyo silicon ryosanka seizo gijutsu no kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

1998-03-01

In order to manufacture silicon for solar cells, development is intended on a technology to manufacture silicon (SOG-Si) for solar cells by means of metallurgical methods using metallic silicon with purity generally available as an interim starting material. The silicon is required of p-type electric conductivity characteristics with specific resistance of 0.5 to 1.5 ohm per cm, to be sufficient even with 6-7N as compared to silicon for semiconductors (11-N), and to be low in cost. While the NEDO fluid bed process and the metallurgical NEDO direct reduction process have been developed based on the technology to manufacture silicon for semiconductors, the basic policy was established to develop a new manufacturing method using commercially available high-purity metallic silicon as an interim starting material, with an objective to achieve cost as low as capable of responding to small-quantity phase production for proliferation purpose. Removal of boron and phosphor has been the main issue in the development, whereas SOG-Si was manufactured in a laboratory scale by combining with the conventional component technologies in fiscal 1991 and 1992. The scale was expanded to 20 kg since fiscal 1993, and a five year plan starting fiscal 1996 was decided to develop the technology for industrial scale. Fiscal 1997 has promoted the development by using the 20-kg scale device, and introduced facilities to develop technology for mass-production scale. (NEDO)

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

Science.gov (United States)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

On the design and implementation of a wafer yield editor

NARCIS (Netherlands)

Pineda de Gyvez, J.; Jess, J.A.G.

1989-01-01

An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

A convenient way of manufacturing silicon nanotubes on a silicon substrate

Energy Technology Data Exchange (ETDEWEB)

Zhang, Changchang; Cheng, Heming; Liu, Xiang, E-mail: liuxiang@ahut.edu.cn

2016-07-01

A convenient approach of preparing silicon nanotubes (SiNTs) on a silicon substrate is described in this work in detail. Firstly, a porous silicon (PSi) slice is prepared by a galvanic displacement reaction. Then it is put into aqueous solutions of 20% (w%) ammonium fluoride and 2.5 mM cobalt nitrate for a predetermined time. The cobalt ions are reduced and the resulted cobalt particles are deposited on the PSi slice. After the cobalt particles are removed with 5 M nitric acid a plenty of SiNTs come out and exhibit disorderly on the silicon substrate, which are illustrated by scanning electron microscopy (SEM). The compositions of the SiNTs are examined by energy-dispersive X-ray spectroscopy. Based on the SEM images, a suggested mechanism is put forward to explain the generation of the SiNTs on the PSi substrate. - Highlights: • A facile approach of preparing silicon nano tubes was invented. • The experimental results demonstrated the strong reducibility of Si-H{sub x} species. • It provided a new way of manufacturing silicon-contained hybrids.

Internal Friction and Young's Modulus Measurements on SiO2 and Ta2O5 Films Done with an Ultra-High Q Silicon-Wafer Suspension

Directory of Open Access Journals (Sweden)

Granata M.

2015-04-01

Full Text Available In order to study the internal friction of thin films a nodal suspension system called GeNS (Gentle Nodal Suspension has been developed. The key features of this system are: i the possibility to use substrates easily available like silicon wafers; ii extremely low excess losses coming from the suspension system which allows to measure Q factors in excess of 2×108 on 3” diameter wafers; iii reproducibility of measurements within few percent on mechanical losses and 0.01% on resonant frequencies; iv absence of clamping; v the capability to operate at cryogenic temperatures. Measurements at cryogenic temperatures on SiO2 and at room temperature only on Ta2O5 films deposited on silicon are presented.

Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

Science.gov (United States)

Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

2013-01-02

Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

Developing silicon strip detectors with a large-scale commercial foundry

Energy Technology Data Exchange (ETDEWEB)

König, A., E-mail: axel.koenig@oeaw.ac.at [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Bartl, U. [Infineon Technologies Austria AG, Villach (Austria); Bergauer, T.; Dragicevic, M. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Hacker, J. [Infineon Technologies Austria AG, Villach (Austria); Treberspurg, W. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria)

2016-07-11

Since 2009 the Institute of High Energy Physics (HEPHY) in Vienna is developing a production process for planar silicon strip sensors on 6-in. wafers together with the semiconductor manufacturer Infineon Technologies. Four runs with several batches of wafers, each comprising six different sensors, were manufactured and characterized. A brief summary of the recently completed 6-in. campaign is given. Milestones in sensor development as well as techniques to improve the sensor quality are discussed. Particular emphasis is placed on a failure causing areas of defective strips which accompanied the whole campaign. Beam tests at different irradiation facilities were conducted to validate the key capability of particle detection. Another major aspect is to prove the radiation hardness of sensors produced by Infineon. Therefore, neutron irradiation studies were performed.

The importance of silicon photovoltaic manufacturing in Saudi Arabia

International Nuclear Information System (INIS)

Elani, U.A.; Bagazi, S.A.

1998-01-01

In this paper, the potential of silicon development for photovoltaics will be discussed in conjunction with the availability of raw material and photovoltaic demand in Saudi Arabia. Recent studies suggest that silicon raw material for photovoltaic production should be considered for further investigation towards solar cells manufacturing in Saudi Arabia. (author)

Strengthening the Competitiveness and Sustainability of a Semiconductor Manufacturer with Cloud Manufacturing

Directory of Open Access Journals (Sweden)

Toly Chen

2014-01-01

Full Text Available Cloud manufacturing (CMfg is a new-generation service-oriented networked manufacturing model that provides distributed users centralized managed manufacturing resources, ability, and services. CMfg is applied here to a semiconductor manufacturing factory. Benefits are classified into five aspects: cost savings, efficiency, additional data analysis capabilities, flexibility, and closer partner relationships. A strength, weakness, opportunity, and threat (SWOT analysis is done which guides a semiconductor manufacturer in planning CMfg implementation projects. Simulation of a wafer fabrication factory (wafer fab is used as an example. Several CMfg services are proposed for assisting the fab simulation activities through the collaboration of cloud service providers, software vendors, equipment suppliers, and the wafer fab. The connection with the competitiveness and sustainability of a wafer fab is also stressed.

Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

Energy Technology Data Exchange (ETDEWEB)

Trushin, Maxim

2011-07-15

The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

Automated reticle inspection data analysis for wafer fabs

Science.gov (United States)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

Science.gov (United States)

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

Silicon-based metallic micro grid for electron field emission

International Nuclear Information System (INIS)

Kim, Jaehong; Jeon, Seok-Gy; Kim, Jung-Il; Kim, Geun-Ju; Heo, Duchang; Shin, Dong Hoon; Sun, Yuning; Lee, Cheol Jin

2012-01-01

A micro-scale metal grid based on a silicon frame for application to electron field emission devices is introduced and experimentally demonstrated. A silicon lattice containing aperture holes with an area of 80 × 80 µm 2 and a thickness of 10 µm is precisely manufactured by dry etching the silicon on one side of a double-polished silicon wafer and by wet etching the opposite side. Because a silicon lattice is more rigid than a pure metal lattice, a thin layer of Au/Ti deposited on the silicon lattice for voltage application can be more resistant to the geometric stress caused by the applied electric field. The micro-fabrication process, the images of the fabricated grid with 88% geometric transparency and the surface profile measurement after thermal feasibility testing up to 700 °C are presented. (paper)

Reliability assessment of ultra-thin HfO{sub 2} films deposited on silicon wafer

Energy Technology Data Exchange (ETDEWEB)

Fu, Wei-En [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Chang, Chia-Wei [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Chang, Yong-Qing [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Yao, Chih-Kai [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Liao, Jiunn-Der, E-mail: jdliao@mail.ncku.edu.tw [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China)

2012-09-01

Highlights: Black-Right-Pointing-Pointer Nano-mechanical properties on annealed ultra-thin HfO{sub 2} film are studied. Black-Right-Pointing-Pointer By AFM analysis, hardness of the crystallized HfO{sub 2} film significantly increases. Black-Right-Pointing-Pointer By nano-indention, the film hardness increases with less contact stiffness. Black-Right-Pointing-Pointer Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO{sub 2}) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO{sub 2} films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO{sub 2} films deposited on silicon wafers (HfO{sub 2}/SiO{sub 2}/Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO{sub 2} (nominal thickness Almost-Equal-To 10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO{sub 2} phases for the atomic layer deposited HfO{sub 2}. The HfSi{sub x}O{sub y} complex formed at the interface between HfO{sub 2} and SiO{sub 2}/Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO{sub 2} film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically

Silicon epitaxy on textured double layer porous silicon by LPCVD

International Nuclear Information System (INIS)

Cai Hong; Shen Honglie; Zhang Lei; Huang Haibin; Lu Linfeng; Tang Zhengxia; Shen Jiancang

2010-01-01

Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521 cm -1 have a width of 7.8 cm -1 , which reveals the high crystalline quality of the silicon epitaxy.

Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

Science.gov (United States)

Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

2013-11-22

Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

Wafer-shape metrics based foundry lithography

Science.gov (United States)

Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

2017-03-01

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

Science.gov (United States)

Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

2016-10-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

Science.gov (United States)

Norris, D J; Myronov, M; Leadley, D R; Walther, T

2017-12-01

We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

Crystallization behavior of polyethylene on silicon wafers in solution casting processes traced by time-resolved measurements of synchrotron grazing-incidence small-angle and wide-angle X-ray scattering

International Nuclear Information System (INIS)

Sasaki, S; Masunaga, H; Takata, M; Itou, K; Tashiro, K; Okuda, H; Takahara, A

2009-01-01

Crystallization behavior of polyethylene (PE) on silicon wafers in solution casting processes has been successfully traced by time-resolved grazing-incidence small-angle and wide-angle X-ray scattering (GISWAXS) measurements utilizing synchrotron radiation. A p-xylene solution of PE kept at ca. 343 K was dropped on a silicon wafer at ca. 298 K. While the p-xylene evaporated naturally from the dropped solution sample, PE chains crystallized to be a thin film. Raman spectral measurements were performed simultaneously with the GISWAXS measurements to evaluate quantitatively the p-xylene the dropped solution contained. Grazing-incidence wide-angle X-ray scattering (GIWAXS) patterns indicated nucleation and crystal growth in the dropped solution and the following as-cast film. GIWAXS and Raman spectral data revealed that crystallization of PE was enhanced after complete evaporation of the p-xylene from the dropped solution. The [110] and [200] directions of the orthorhombic PE crystal became relatively parallel to the wafer surface with time, which implied that the flat-on lamellae with respect to the wafer surface were mainly formed in the as-cast film. On the other hand, grazing-incidence small-angle X-ray scattering (GISAXS) patterns implied formation of isolated lamellae in the dropped solution. The lamellae and amorphous might alternatively be stacked in the preferred direction perpendicular to the wafer surface. The synchrotron GISWAXS experimental method could be applied for kinetic study on hierarchical structure of polymer thin films.

Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

OpenAIRE

Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

2018-01-01

A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

Porous Silicon Nanowires

Science.gov (United States)

Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

2011-01-01

In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

Science.gov (United States)

Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

2004-10-01

The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

Energy Technology Data Exchange (ETDEWEB)

Rouault de Coligny, P.

2002-09-15

This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

Probing and irradiation tests of ALICE pixel chip wafers and sensors

CERN Document Server

Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

2004-01-01

In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

In-house manufacturing of cylindrical silicone models for hemodynamic research

Science.gov (United States)

Denisenko, Nikita S.; Kulik, Viktor M.

2017-10-01

Laboratory studies of fluid motion in artificial vessels modeling a distinct part of circulatory system of human are of a great importance for fundamental biomechanics and for medical applications. In the medicine they are used for advancing known and developing new methods for curing cardiovascular diseases. In biomechanics, the phantoms of blood vessels are used for studying the fluid motion. However, they are quite expensive. Therefore, a development of technique for in-house manufacturing of phantoms is quite attractive. In this paper methods of manufacturing cylindrical channels of silicone rubbers (the model of the straight part of an artery) and determination of their elastic properties are described. A specially developed acrylic mold is used for this purpose. The phantoms are cast from a mixture of SKTN-A silicone and PMS-5 oil (Penta-91, Novosibirsk, Russia). The oil is used for changing elasticity properties of the silicone.

Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

International Nuclear Information System (INIS)

Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

2005-01-01

Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

Hybrid Integrated Platforms for Silicon Photonics

Science.gov (United States)

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

Science.gov (United States)

Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

2017-09-01

The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

Silicon nanowire-based solar cells

Energy Technology Data Exchange (ETDEWEB)

Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S [Institute of Photonic Technology, Albert-Einstein-Strasse 9, D-07745 Jena (Germany)], E-mail: thomas.stelzner@ipht-jena.de

2008-07-23

The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm{sup 2} open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm{sup -2} were obtained.

Silicon nanowire-based solar cells

International Nuclear Information System (INIS)

Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S

2008-01-01

The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm 2 open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm -2 were obtained

Characterizing SOI Wafers By Use Of AOTF-PHI

Science.gov (United States)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

International Nuclear Information System (INIS)

Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

1993-01-01

The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

Neurovascular Modeling: Small-Batch Manufacturing of Silicone Vascular Replicas

Science.gov (United States)

Chueh, J.Y.; Wakhloo, A.K.; Gounis, M.J.

2009-01-01

BACKGROUND AND PURPOSE Realistic, population based cerebrovascular replicas are required for the development of neuroendovascular devices. The objective of this work was to develop an efficient methodology for manufacturing realistic cerebrovascular replicas. MATERIALS AND METHODS Brain MR angiography data from 20 patients were acquired. The centerline of the vasculature was calculated, and geometric parameters were measured to describe quantitatively the internal carotid artery (ICA) siphon. A representative model was created on the basis of the quantitative measurements. Using this virtual model, we designed a mold with core-shell structure and converted it into a physical object by fused-deposit manufacturing. Vascular replicas were created by injection molding of different silicones. Mechanical properties, including the stiffness and luminal coefficient of friction, were measured. RESULTS The average diameter, length, and curvature of the ICA siphon were 4.15 ± 0.09 mm, 22.60 ± 0.79 mm, and 0.34 ± 0.02 mm-1 (average ± standard error of the mean), respectively. From these image datasets, we created a median virtual model, which was transformed into a physical replica by an efficient batch-manufacturing process. The coefficient of friction of the luminal surface of the replica was reduced by up to 55% by using liquid silicone rubber coatings. The modulus ranged from 0.67 to 1.15 MPa compared with 0.42 MPa from human postmortem studies, depending on the material used to make the replica. CONCLUSIONS Population-representative, smooth, and true-to-scale silicone arterial replicas with uniform wall thickness were successfully built for in vitro neurointerventional device-testing by using a batch-manufacturing process. PMID:19321626

Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

Science.gov (United States)

Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

2018-01-01

Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

Solar cell fabricated on welded thin flexible silicon

Directory of Open Access Journals (Sweden)

Hessmann Maik Thomas

2015-01-01

Full Text Available We present a thin-film crystalline silicon solar cell with an AM1.5 efficiency of 11.5% fabricated on welded 50 μm thin silicon foils. The aperture area of the cell is 1.00 cm2. The cell has an open-circuit voltage of 570 mV, a short-circuit current density of 29.9 mA cm-2 and a fill factor of 67.6%. These are the first results ever presented for solar cells on welded silicon foils. The foils were welded together in order to create the first thin flexible monocrystalline band substrate. A flexible band substrate offers the possibility to overcome the area restriction of ingot-based monocrystalline silicon wafers and the feasibility of a roll-to-roll manufacturing. In combination with an epitaxial and layer transfer process a decrease in production costs can be achieved.

Polycrystalline Silicon Gettered by Porous Silicon and Heavy Phosphorous Diffusion

Institute of Scientific and Technical Information of China (English)

LIU Zuming(刘祖明); Souleymane K Traore; ZHANG Zhongwen(张忠文); LUO Yi(罗毅)

2004-01-01

The biggest barrier for photovoltaic (PV) utilization is its high cost, so the key for scale PV utilization is to further decrease the cost of solar cells. One way to improve the efficiency, and therefore lower the cost, is to increase the minority carrier lifetime by controlling the material defects. The main defects in grain boundaries of polycrystalline silicon gettered by porous silicon and heavy phosphorous diffusion have been studied. The porous silicon was formed on the two surfaces of wafers by chemical etching. Phosphorous was then diffused into the wafers at high temperature (900℃). After the porous silicon and diffusion layers were removed, the minority carrier lifetime was measured by photo-conductor decay. The results show that the lifetime's minority carriers are increased greatly after such treatment.

Silicon Photomultipliers: Dark Current and its Statistical Spread

Directory of Open Access Journals (Sweden)

Roberto PAGANO

2012-03-01

Full Text Available Aim of this paper is to investigate on a statistical basis at the wafer level the relationship existing among the dark currents of the single pixel compared to the whole Silicon Photomultiplier array. This is the first time to our knowledge that such a comparison is made, crucial to pass this new technology to the semiconductor manufacturing standards. In particular, emission microscopy measurements and current measurements allowed us to conclude that optical trenches strongly improve the device performances.

Analysis of temperature profiles and the mechanism of silicon substrate plastic deformation under epitaxial growth

International Nuclear Information System (INIS)

Mirkurbanov, H.A.; Sazhnev, S.V.; Timofeev, V.N.

2004-01-01

Full text: Thermal treatment of silicon wafers holds one of the major place in the manufacturing of semi-conductor devices. Thermal treatment includes wafer annealing, thermal oxidation, epitaxial growing etc. Quality of wafers in the high-temperature processes (900-1200 deg C) is estimated by the density of structural defects, including areas of plastic deformation, which are shown as the slip lines appearance. Such areas amount to 50-60 % of total wafer surface. The plastic deformation is caused by the thermal stresses. Experimental and theoretical researches allowed to determine thermal balance and to construct a temperature profiles throughout the plate surface. Thermal stresses are caused by temperature drop along the radius of a wafer and at the basic peripheral ring. The threshold temperature drop between center f a wafer and its peripherals (ΔT) for slip lines appearance, amounts to 15-17 deg. C. At the operating temperature of 900-1200 deg. C and ΔT>20 deg. C, the stresses reach the silicon yield point. According to the results of the researches of structure and stress profiles in a wafer, the mechanism of slip lines formation has been constructed. A source of dislocations is the rear broken layer of thickness 8-10 microns, formed after polishing. The micro-fissures with a density 10 5 -10 6 cm -2 are the sources of dislocations. Dislocations move on a surface of a wafer into a slip plane (111). On a wafer surface with orientation (111) it is possible to allocate zones where the tangential stress vector is most favorably directed with respect to a slip plane leaving on a surface, i.e. the shift stresses are maximal in the slip plane. The way to eliminate plastic deformation is to lower the temperature drop to a level of <15 deg. C and elimination of the broken layer in wafer

Silicon materials outlook study for 1980-85 calendar years

Energy Technology Data Exchange (ETDEWEB)

Costogue, E.; Ferber, R.; Hasbach, W.; Pellin, R.; Yaws, C.

1979-11-01

Photovoltaic solar cell arrays converting solar energy into electrical energy can become a cost-effective, alternative energy source provided that an adequate supply of low-priced solar cell materials and automated fabrication techniques are available. Presently, the photovoltaic industry is dependent upon polycrystalline silicon which is produced primarily for the discrete semiconductor device industry. This dependency is expected to continue until DOE-sponsored new technology developments mature. Recent industry forecasts have predicted a limited supply of polycrystalline silicon material and a shortage could occur in the early 80's. The Jet Propulsion Laboratory's Technology Development and Application Lead Center formed an ad hoc committee at JPL, SERI and consultant personnel to conduct interviews with key polycrystalline manufacturers and a large cross-section of single crystal ingot growers and wafer manufacturers. Industry consensus and conclusions reached from the analysis of the data obtained by the committee are reported. The highlight of the study is that there is a high probability of polycrystalline silicon shortage by the end of CY 1982 and a strong seller's market after CY 1981 which will foster price competition for available silicon.

Hybrid Integrated Platforms for Silicon Photonics

Directory of Open Access Journals (Sweden)

John E. Bowers

2010-03-01

Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Silicon pore optics for future x-ray telescopes

Science.gov (United States)

Wille, Eric; Bavdaz, Marcos; Wallace, Kotska; Shortt, Brian; Collon, Maximilien; Ackermann, Marcelo; Günther, Ramses; Olde Riekerink, Mark; Koelewijn, Arenda; Haneveld, Jeroen; van Baren, Coen; Erhard, Markus; Kampf, Dirk; Christensen, Finn; Krumrey, Michael; Freyberg, Michael; Burwitz, Vadim

2017-11-01

Lightweight X-ray Wolter optics with a high angular resolution will enable the next generation of X-ray telescopes in space. The candidate mission ATHENA (Advanced Telescope for High Energy Astrophysics) required a mirror assembly of 1 m2 effective area (at 1 keV) and an angular resolution of 10 arcsec or better. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is being developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor industry. We present the recent upgrades made to the manufacturing processes and equipment, ranging from the manufacture of single mirror plates towards complete focusing mirror modules mounted in flight configuration, and results from first vibration tests. The performance of the mirror modules is tested at X-ray facilities that were recently extended to measure optics at a focal distance up to 20 m.

Quality evaluation of resistivity-controlled silicon crystals

Science.gov (United States)

Wang, Jong Hoe

2006-01-01

The segregation phenomenon of dopants causes a low production yield of silicon crystal that meets the resistivity tolerance required by device manufacturers. In order to control the macroscopic axial resistivity distribution in bulk crystal growth, numerous studies including continuous Czochralski method and double crucible technique have been studied. The simple B-P codoping method for improving the productivity of p-type silicon single-crystal growth by controlling axial specific resistivity distribution was proposed by Wang [Jpn. J. Appl. Phys. 43 (2004) 4079]. In this work, the quality of Czochralski-grown silicon single crystals with a diameter 200 mm using B-P codoping method was studied from the chemical and structural points of view. It was found that the characteristics of B-P codoped wafers including the oxygen precipitation behavior and the grown-in defects are same as that of conventional B-doped Czochralski crystals.

Study on structural properties of epitaxial silicon films on annealed double layer porous silicon

International Nuclear Information System (INIS)

Yue Zhihao; Shen Honglie; Cai Hong; Lv Hongjie; Liu Bin

2012-01-01

In this paper, epitaxial silicon films were grown on annealed double layer porous silicon by LPCVD. The evolvement of the double layer porous silicon before and after thermal annealing was investigated by scanning electron microscope. X-ray diffraction and Raman spectroscopy were used to investigate the structural properties of the epitaxial silicon thin films grown at different temperature and different pressure. The results show that the surface of the low-porosity layer becomes smooth and there are just few silicon-bridges connecting the porous layer and the substrate wafer. The qualities of the epitaxial silicon thin films become better along with increasing deposition temperature. All of the Raman peaks of silicon films with different deposition pressure are situated at 521 cm -1 under the deposition temperature of 1100 °C, and the Raman intensity of the silicon film deposited at 100 Pa is much closer to that of the monocrystalline silicon wafer. The epitaxial silicon films are all (4 0 0)-oriented and (4 0 0) peak of silicon film deposited at 100 Pa is more symmetric.

Compton recoil electron tracking with silicon strip detectors

International Nuclear Information System (INIS)

O'Neill, T.J.; Ait-Ouamer, F.; Schwartz, I.; Tumer, O.T.; White, R.S.; Zych, A.D.

1992-01-01

The application of silicon strip detectors to Compton gamma ray astronomy telescopes is described in this paper. The Silicon Compton Recoil Telescope (SCRT) tracks Compton recoil electrons in silicon strip converters to provide a unique direction for Compton scattered gamma rays above 1 MeV. With strip detectors of modest positional and energy resolutions of 1 mm FWHM and 3% at 662 keV, respectively, 'true imaging' can be achieved to provide an order of magnitude improvement in sensitivity to 1.6 x 10 - 6 γ/cm 2 -s at 2 MeV. The results of extensive Monte Carlo calculations of recoil electrons traversing multiple layers of 200 micron silicon wafers are presented. Multiple Coulomb scattering of the recoil electron in the silicon wafer of the Compton interaction and the next adjacent wafer is the basic limitation to determining the electron's initial direction

CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

Directory of Open Access Journals (Sweden)

Pei-Zen Chang

2012-12-01

Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

Fabrication of novel AFM probe with high-aspect-ratio ultra-sharp three-face silicon nitride tips

NARCIS (Netherlands)

Vermeer, Rolf; Berenschot, Johan W.; Sarajlic, Edin; Tas, Niels Roelof; Jansen, Henricus V.

In this paper we present the wafer-scale fabrication of molded AFM probes with high aspect ratio ultra-sharp three-plane silicon nitride tips. Using $\\langle$111$\\rangle$ silicon wafers a dedicated process is developed to fabricate molds in the silicon wafer that have a flat triangular bottom

Silicon heterojunction solar cells with novel fluorinated n-type nanocrystalline silicon oxide emitters on p-type crystalline silicon

Science.gov (United States)

Dhar, Sukanta; Mandal, Sourav; Das, Gourab; Mukhopadhyay, Sumita; Pratim Ray, Partha; Banerjee, Chandan; Barua, Asok Kumar

2015-08-01

A novel fluorinated phosphorus doped silicon oxide based nanocrystalline material have been used to prepare heterojunction solar cells on flat p-type crystalline silicon (c-Si) Czochralski (CZ) wafers. The n-type nc-SiO:F:H material were deposited by radio frequency plasma enhanced chemical vapor deposition. Deposited films were characterized in detail by using atomic force microscopy (AFM), high resolution transmission electron microscopy (HRTEM), Raman, fourier transform infrared spectroscopy (FTIR) and optoelectronics properties have been studied using temperature dependent conductivity measurement, Ellipsometry, UV-vis spectrum analysis etc. It is observed that the cell fabricated with fluorinated silicon oxide emitter showing higher initial efficiency (η = 15.64%, Jsc = 32.10 mA/cm2, Voc = 0.630 V, FF = 0.77) for 1 cm2 cell area compare to conventional n-a-Si:H emitter (14.73%) on flat c-Si wafer. These results indicate that n type nc-SiO:F:H material is a promising candidate for heterojunction solar cell on p-type crystalline wafers. The high Jsc value is associated with excellent quantum efficiencies at short wavelengths (<500 nm).

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

Science.gov (United States)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

A Manufacturing Cost and Supply Chain Analysis of SiC Power Electronics Applicable to Medium-Voltage Motor Drives

Energy Technology Data Exchange (ETDEWEB)

Horowitz, Kelsey [National Renewable Energy Lab. (NREL), Golden, CO (United States); Remo, Timothy [National Renewable Energy Lab. (NREL), Golden, CO (United States); Reese, Samantha [National Renewable Energy Lab. (NREL), Golden, CO (United States)

2017-03-24

Wide bandgap (WBG) semiconductor devices are increasingly being considered for use in certain power electronics applications, where they can improve efficiency, performance, footprint, and, potentially, total system cost compared to systems using traditional silicon (Si) devices. Silicon carbide (SiC) devices in particular -- which are currently more mature than other WBG devices -- are poised for growth in the coming years. Today, the manufacturing of SiC wafers is concentrated in the United States, and chip production is split roughly equally between the United States, Japan, and Europe. Established contract manufacturers located throughout Asia typically carry out manufacturing of WBG power modules. We seek to understand how global manufacturing of SiC components may evolve over time by illustrating the regional cost drivers along the supply chain and providing an overview of other factors that influence where manufacturing is sited. We conduct this analysis for a particular case study where SiC devices are used in a medium-voltage motor drive.

Wafer-level testing and test during burn-in for integrated circuits

CERN Document Server

Bahukudumbi, Sudarshan

2010-01-01

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

Results from a beam test of silicon strip sensors manufactured by Infineon Technologies AG

Energy Technology Data Exchange (ETDEWEB)

Dragicevic, M., E-mail: marko.dragicevic@oeaw.ac.at [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Auzinger, G. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); CERN, Geneva (Switzerland); Bartl, U. [Infineon Technologies Austria AG, Villach (Austria); Bergauer, T. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Gamerith, S.; Hacker, J. [Infineon Technologies Austria AG, Villach (Austria); König, A. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Infineon Technologies Austria AG, Villach (Austria); Kröner, F.; Kucher, E.; Moser, J.; Neidhart, T. [Infineon Technologies Austria AG, Villach (Austria); Schulze, H.-J. [Infineon Technologies AG, Munich (Germany); Schustereder, W. [Infineon Technologies Austria AG, Villach (Austria); Treberspurg, W. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Wübben, T. [Infineon Technologies Austria AG, Villach (Austria)

2014-11-21

Most modern particle physics experiments use silicon based sensors for their tracking systems. These sensors are able to detect particles generated in high energy collisions with high spatial resolution and therefore allow the precise reconstruction of particle tracks. So far only a few vendors were capable of producing silicon strip sensors with the quality needed in particle physics experiments. Together with the European-based semiconductor manufacturer Infineon Technologies AG (Infineon) the Institute of High Energy Physics of the Austrian Academy of Sciences (HEPHY) developed planar silicon strip sensors in p-on-n technology. This work presents the first results from a beam test of strip sensors manufactured by Infineon.

Liquid phase epitaxial growth of silicon on porous silicon for photovoltaic applications

International Nuclear Information System (INIS)

Berger, S.; Quoizola, S.; Fave, A.; Kaminski, A.; Perichon, S.; Barbier, D.; Laugier, A.

2001-01-01

The aim of this experiment is to grow a thin silicon layer ( 2 atmosphere, and finally LPE silicon growth with different temperature profiles in order to obtain a silicon layer on the sacrificial porous silicon (p-Si). We observed a pyramidal growth on the surface of the (100) porous silicon but the coalescence was difficult to obtain. However, on a p-Si (111) oriented wafer, homogeneous layers were obtained. (orig.)

A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

Energy Technology Data Exchange (ETDEWEB)

Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

2016-12-15

In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Wafer scale integration of catalyst dots into nonplanar microsystems

DEFF Research Database (Denmark)

Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

2007-01-01

In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

a Study of Oxygen Precipitation in Heavily Doped Silicon.

Science.gov (United States)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation

Silicon (100)/SiO2 by XPS

Energy Technology Data Exchange (ETDEWEB)

Jensen, David S.; Kanyal, Supriya S.; Madaan, Nitesh; Vail, Michael A.; Dadson, Andrew; Engelhard, Mark H.; Linford, Matthew R.

2013-09-25

Silicon (100) wafers are ubiquitous in microfabrication and, accordingly, their surface characteristics are important. Herein, we report the analysis of Si (100) via X-ray photoelectron spectroscopy (XPS) using monochromatic Al K radiation. Survey scans show that the material is primarily silicon and oxygen, and the Si 2p region shows two peaks that correspond to elemental silicon and silicon dioxide. Using these peaks the thickness of the native oxide (SiO2) was estimated using the equation of Strohmeier.1 The oxygen peak is symmetric. The material shows small amounts of carbon, fluorine, and nitrogen contamination. These silicon wafers are used as the base material for subsequent growth of templated carbon nanotubes.

Wafer level packaging of MEMS

International Nuclear Information System (INIS)

Esashi, Masayoshi

2008-01-01

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

Efficiency Enhancement of Silicon Solar Cells by Porous Silicon Technology

Directory of Open Access Journals (Sweden)

Eugenijus SHATKOVSKIS

2012-09-01

Full Text Available Silicon solar cells produced by a usual technology in p-type, crystalline silicon wafer were investigated. The manufactured solar cells were of total thickness 450 mm, the junction depth was of 0.5 mm – 0.7 mm. Porous silicon technologies were adapted to enhance cell efficiency. The production of porous silicon layer was carried out in HF: ethanol = 1 : 2 volume ratio electrolytes, illuminating by 50 W halogen lamps at the time of processing. The etching current was computer-controlled in the limits of (6 ÷ 14 mA/cm2, etching time was set in the interval of (10 ÷ 20 s. The characteristics and performance of the solar cells samples was carried out illuminating by Xenon 5000 K lamp light. Current-voltage characteristic studies have shown that porous silicon structures produced affect the extent of dark and lighting parameters of the samples. Exactly it affects current-voltage characteristic and serial resistance of the cells. It has shown, the formation of porous silicon structure causes an increase in the electric power created of solar cell. Conversion efficiency increases also respectively to the initial efficiency of cell. Increase of solar cell maximum power in 15 or even more percent is found. The highest increase in power have been observed in the spectral range of Dl @ (450 ÷ 850 nm, where ~ 60 % of the A1.5 spectra solar energy is located. It has been demonstrated that porous silicon technology is effective tool to improve the silicon solar cells performance.DOI: http://dx.doi.org/10.5755/j01.ms.18.3.2428

Quasimetallic silicon micromachined photonic crystals

International Nuclear Information System (INIS)

Temelkuran, B.; Bayindir, Mehmet; Ozbay, E.; Kavanaugh, J. P.; Sigalas, M. M.; Tuttle, G.

2001-01-01

We report on fabrication of a layer-by-layer photonic crystal using highly doped silicon wafers processed by semiconductor micromachining techniques. The crystals, built using (100) silicon wafers, resulted in an upper stop band edge at 100 GHz. The transmission and defect characteristics of these structures were found to be analogous to metallic photonic crystals. We also investigated the effect of doping concentration on the defect characteristics. The experimental results agree well with predictions of the transfer matrix method simulations

Effect of potential steps on porous silicon formation

International Nuclear Information System (INIS)

Cheng Xuan; Feng Zude; Luo Guangfeng

2003-01-01

Porous silicon microstructures were fabricated by applying potential steps through which both anodic and cathodic potentials were periodically applied to silicon wafers. The electrochemical behaviors of porous silicon layers were examined by performing polarization measurements, followed by analyzing the open-circuit potential (E ocp ) and the reaction rate in terms of corrosion current density (j corr ). The surface morphologies and surface products of porous silicon were characterized by scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). It was found that the values of E ocp and j corr varied more significantly and irregularly during different polarization stages when the potentials were continuously applied to the wafer surface, while virtually unchanged after 2 min of periodic potential application. In addition, slower reaction rates were observed with applying potential steps, as indicated by smaller values of j corr . The enhancement on refreshment of silicon surfaces by periodic potential polarization significantly accelerated the growth of porous silicon. The microstructures became more uniformed and better defined due to the improved passivating nature of wafer surfaces

Low temperature spalling of silicon: A crack propagation study

Energy Technology Data Exchange (ETDEWEB)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

Science.gov (United States)

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

Proposed method of assembly for the BCD silicon strip vertex detector modules

International Nuclear Information System (INIS)

Lindenmeyer, C.

1989-01-01

The BCD Silicon strip Vertex Detector is constructed of 10 identical central region modules and 18 similar forward region modules. This memo describes a method of assembling these modules from individual silicon wafers. Each wafer is fitted with associated front end electronics and cables and has been tested to insure that only good wafers reach the final assembly stage. 5 figs

Cost of Czochralski wafers as a function of diameter

Science.gov (United States)

Leipold, M. H.; Radics, C.; Kachare, A.

1980-02-01

The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

Development in fiscal 1998 of silicon manufacturing process to rationalize energy usage. Surveys and researches on analysis of practical application of technology to manufacture silicon raw materials for solar cells; 1998 nendo energy shiyo gorika silicon seizo process kaihatsu seika hokokusho. Taiyo denchi silicon genryo seizo gijutsu no jitsuyoka kaiseki ni kansuru chosa kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

1999-03-01

With an objective to develop a mass production technology to manufacture silicon raw materials for solar cells, and assist its practical application, surveys and analyses were performed on trends in development of the related technologies, the problems therein , market trends and industrial trends thereof. This paper summarizes the achievements in fiscal 1998. The worldwide production amount of solar cells in 1998 is estimated to have achieved 150 MW, and the silicon consumption reached the level of 2,300 tons. In spite of the economic recession environment, there was no change in the expansion trend. In developing an SOG-Si mass production and manufacturing technology, construction of pilot plants for each process has been completed, and entered into the operation research phase. In developing a technology to manufacture high quality poly-crystalline silicon substrates, fabrication has been completed on the on-line ingot cutting equipment and the plasma heating equipment, and the stage is now in operation research of continuous electromagnetic casting process. The conversion efficiency of the poly-crystalline silicon solar cells is 14 to 16% at the mass production level, whose enhancement requires indispensably the improvement in quality of the substrate. Discussions are required on the ingot manufacturing conditions in coordination with improvement in the cell manufacturing technology. (NEDO)

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

Science.gov (United States)

Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

2017-04-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

International Nuclear Information System (INIS)

Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

2017-01-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

Directory of Open Access Journals (Sweden)

Ali Attaran

2014-01-01

Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

Directory of Open Access Journals (Sweden)

Azrul Azlan Hamzah

2008-11-01

Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

Fabrication and Modification of Nanoporous Silicon Particles

Science.gov (United States)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

Science.gov (United States)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Sacrificial wafer bonding for planarization after very deep etching

NARCIS (Netherlands)

Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

Ion-implanted capacitively coupled silicon strip detectors with integrated polysilicon bias resistors processed on a 100 mm wafer

International Nuclear Information System (INIS)

Hietanen, I.; Lindgren, J.; Orava, R.; Tuuva, T.; Voutilainen, M.; Brenner, R.; Andersson, M.; Leinonen, K.; Ronkainen, H.

1991-01-01

Double-sided silicon strip detectors with integrated coupling capacitors and polysilicon resistors have been processed on a 100 mm wafer. A detector with an active area of 19x19 mm 2 was connected to LSI readout electronics and tested. The strip pitch of the detector is 25 μm on the p-side and 50 μm on the n-side. The readout pitch is 50 μm on both sides. The number of readout strips is 774 and the total number of strips is 1161. On the p-side a signal-to-noise of 35 has been measured using a 90 Sr β-source. The n-side has been studied using a laser. (orig.)

Seedless electroplating on patterned silicon

NARCIS (Netherlands)

Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

2006-01-01

Nickel thin films have been electrodeposited without the use of an additional seed layer, on highly doped silicon wafers. These substrates conduct sufficiently well to allow deposition using a peripherical electrical contact on the wafer. Films 2 μm thick have been deposited using a nickel sulfamate

Achievement report for fiscal 1999 on the development of silicon manufacturing process rationalizing energy utilization. Research and study on analysis to put silicon raw material manufacturing technology for solar cells into practical use; 1999 nendo energy shiyo gorika silicon seizo process kaihatsu seika hokokusho. Taiyo denchi silicon genryo seizo gijutsu no jitsuyoka kaiseki ni kansuru chosa kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

In order to support the development and practical application of a mass production technology for manufacturing silicon raw materials for solar cells, research and study were performed on trends of developing the related technologies, and movements in markets and industries. This paper reports the achievements thereof in fiscal 1999. Markets for solar cells are growing favorably, and the worldwide solar cell production in 1999 was 200 MWp, of which 80% or more is occupied by crystalline silicon solar cell. While development of the manufacturing technology for SOG-Si mass-production is in the stage of operation research of pilot plants, it has been verified that problems of impurity contamination was resolved, and high-purity silicon can be manufactured. In developing the silicon scrap utilization technology and a technology to integrate silicon refinement with casting, a conversion efficiency of 14% or higher was acquired in prototype sample substrates. It has been verified that a variety of raw materials can be dealt with by using the above technology, which has a possibility of cost reduction. In developing a substrate manufacturing technology, a great progress has been made in enhancing the productivity and reducing the cost by developing the continuous casting in the electromagnetic casting and the automation technology. (NEDO)

Bias-assisted KOH etching of macroporous silicon membranes

International Nuclear Information System (INIS)

Mathwig, K; Geilhufe, M; Müller, F; Gösele, U

2011-01-01

This paper presents an improved technique to fabricate porous membranes from macroporous silicon as a starting material. A crucial step in the fabrication process is the dissolution of silicon from the backside of the porous wafer by aqueous potassium hydroxide to open up the pores. We improved this step by biasing the silicon wafer electrically against the KOH. By monitoring the current–time characteristics a good control of the process is achieved and the yield is improved. Also, the etching can be stopped instantaneously and automatically by short-circuiting Si and KOH. Moreover, the bias-assisted etching allows for the controlled fabrication of silicon dioxide tube arrays when the silicon pore walls are oxidized and inverted pores are released.

Increasing the radiation resistance of single-crystal silicon epitaxial layers

Directory of Open Access Journals (Sweden)

Kurmashev Sh. D.

2014-12-01

Full Text Available The authors investigate the possibility of increasing the radiation resistance of silicon epitaxial layers by creating radiation defects sinks in the form of dislocation networks of the density of 109—1012 m–2. Such networks are created before the epitaxial layer is applied on the front surface of the silicon substrate by its preliminary oxidation and subsequent etching of the oxide layer. The substrates were silicon wafers KEF-4.5 and KDB-10 with a diameter of about 40 mm, grown by the Czochralski method. Irradiation of the samples was carried out using electron linear accelerator "Electronics" (ЭЛУ-4. Energy of the particles was 2,3—3,0 MeV, radiation dose 1015—1020 m–2, electron beam current 2 mA/m2. It is shown that in structures containing dislocation networks, irradiation results in reduction of the reverse currents by 5—8 times and of the density of defects by 5—10 times, while the mobility of the charge carriers is increased by 1,2 times. Wafer yield for operation under radiation exposure, when the semiconductor structures are formed in the optimal mode, is increased by 7—10% compared to the structures without dislocation networks. The results obtained can be used in manufacturing technology for radiation-resistant integrated circuits (bipolar, CMOS, BiCMOS, etc..

Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

NARCIS (Netherlands)

Haneveld, J.; Berenschot, Johan W.; Maury, P.A.; Jansen, Henricus V.

2005-01-01

A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7-20 nm wide, 40-100 nm high and centimeters long. All dimensions are easily

Hydrogen-induced structural changes in polycrystalline silicon as revealed by positron lifetime spectroscopy

International Nuclear Information System (INIS)

Arole, V.M.; Takwale, M.G.; Bhide, V.G.

1989-01-01

Hydrogen passivation of polycrystalline silicon wafer is carried out in order to reduce the deleterious effects of grain boundaries. A systematic variation is made in the process parameters implemented during hydrogen passivation and the results of room temperature resistivity measurements are reported. As an efficient tool to study the structure change, positron lifetime spectroscopic measurements are performed on original and hydrogenated polycrystalline silicon wafers and a systematic correlation is sought between the changes that take place in the electrical and structural properties of polycrystalline silicon wafer, brought about by hydrogen passivation. (author)

Xe{sup +} ion beam induced rippled structures on Si miscut wafers

Energy Technology Data Exchange (ETDEWEB)

Hanisch, Antje; Grenzer, Joerg [Forschungszentrum Dresden-Rossendorf, Dresden (Germany); Biermanns, Andreas; Pietsch, Ullrich [Institute of Physics, University of Siegen (Germany)

2009-07-01

We report on the influence of the initial roughness and crystallography of the substrate on the formation of self-organized ripple structures on semiconductors surfaces by noble gas ion bombardment. The Bradley-Harper theory predicts that an initial roughness is most important for starting the sputtering process which in the ends leads to the evolution of regular patterns. We produced periodic structures with intermediate Xe{sup +} ion energies (5-70 keV) at different incidence and azimuthal angles which lead to the assumption that also crystallography plays a role at the beginning of ripple evolution. Most of the previous investigations started from the original roughness of a polished silicon wafer. We used (001) silicon wafers with a miscut angle of 1 , 5 and 10 towards[110]. We studied the ripple formation keeping the ion beam parallel to the[111],[-1-11] or[-111] direction, i.e. parallel, antiparallel or perpendicular to the miscut direction[110]. The parallel and antiparallel case implies a variation of the incidence angle with increased roughness over the surface step terraces. The perpendicular orientation means almost no roughness. The results were compared to normal Si(001) and Si(111) wafers.

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

CERN Document Server

Bronuzzi, J.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

Infrared birefringence imaging of residual stress and bulk defects in multicrystalline silicon

Energy Technology Data Exchange (ETDEWEB)

Ganapati, Vidya; Schoenfelder, Stephan; Castellanos, Sergio; Oener, Sebastian; Koepge, Ringo; Sampson, Aaron; Marcus, Matthew A.; Lai, Barry; Morhenn, Humphrey; Hahn, Giso; Bagdahn, Joerg; Buonassisi1, Tonio

2010-05-05

This manuscript concerns the application of infrared birefringence imaging (IBI) to quantify macroscopic and microscopic internal stresses in multicrystalline silicon (mc-Si) solar cell materials. We review progress to date, and advance four closely related topics. (1) We present a method to decouple macroscopic thermally-induced residual stresses and microscopic bulk defect related stresses. In contrast to previous reports, thermally-induced residual stresses in wafer-sized samples are generally found to be less than 5 MPa, while defect-related stresses can be several times larger. (2) We describe the unique IR birefringence signatures, including stress magnitudes and directions, of common microdefects in mc-Si solar cell materials including: {beta}-SiC and {beta}-Si{sub 3}N{sub 4} microdefects, twin bands, nontwin grain boundaries, and dislocation bands. In certain defects, local stresses up to 40 MPa can be present. (3) We relate observed stresses to other topics of interest in solar cell manufacturing, including transition metal precipitation, wafer mechanical strength, and minority carrier lifetime. (4) We discuss the potential of IBI as a quality-control technique in industrial solar cell manufacturing.

Cast polycrystalline silicon photovoltaic module manufacturing technology improvements. Annual subcontract report, 1 January 1996--31 December 1996

Energy Technology Data Exchange (ETDEWEB)

Wohlgemuth, J. [Solarex Corp., Frederick, MD (United States)

1997-10-01

This report describes Solarex`s accomplishments during this phase of the Photovoltaic Manufacturing Technology (PVMaT) program. During this reporting period, Solarex researchers converted 79% of production casting stations to increase ingot size and operated them at equivalent yields and cell efficiencies; doubled the casting capacity at 20% the cost of buying new equipment to achieve the same capacity increase; operated the wire saws in a production mode with higher yields and lower costs than achieved on the ID saws; purchased additional wire saws; developed and qualified a new wire-guide coating material that doubles the wire-guide lifetime and produces significantly less scatter in wafer thickness; ran an Al paste back-surface-field process on 25% of all cells in manufacturing; completed environmental qualification of modules using cells produced by an all-print metallization process; qualified a vendor-supplied Tedlar/ethylene vinyl acetate (EVA) laminate to replace the combination of separate sheets of EVA and Tedlar backsheet; substituted RTV adhesive for the 3M Very High Bond tape after several field problems with the tape; demonstrated the operation of a prototype unit to trim/lead attach/test modules; demonstrated the use of light soldering for solar cells; demonstrated the operation of a wafer pull-down system for cassetting wet wafers; and presented three PVMaT-related papers at the 25th IEEE Photovoltaic Specialists Conference.

Electroless porous silicon formation applied to fabrication of boron-silica-glass cantilevers

DEFF Research Database (Denmark)

Teva, Jordi; Davis, Zachary James; Hansen, Ole

2010-01-01

This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5-1 mm3) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases...... where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing...... for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH...

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

Science.gov (United States)

Grant, Nicholas E.

2016-01-01

A procedure to measure the bulk lifetime (>100 µsec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (<1012 cm-3). PMID:26779939

Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

Science.gov (United States)

Egelkrout, D. W.

1981-01-01

Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

Linear self-assembly and grafting of gold nanorods into arrayed micrometer-long nanowires on a silicon wafer via a combined top-down/bottom-up approach.

Science.gov (United States)

Lestini, Elena; Andrei, Codrin; Zerulla, Dominic

2018-01-01

Macroscopically long wire-like arrangements of gold nanoparticles were obtained by controlled evaporation and partial coalescence of an aqueous colloidal solution of capped CTAB-Au nanorods onto a functionalised 3-mercaptopropyl trimethoxysilane (MPTMS) silicon substrate, using a removable, silicon wafer with a hydrophobic surface that serves as a "handrail" for the initial nanorods' linear self-assembly. The wire-like structures display a quasi-continuous pattern by thermal annealing of the gold nanorods when the solvent (i.e. water) is evaporated at temperatures rising from 20°C to 140°C. Formation of both single and self-replicating parallel 1D-superstructures consisting of two or even three wires is observed and explained under such conditions.

TXRF analysis of trace metals in thin silicon nitride films

International Nuclear Information System (INIS)

Vereecke, G.; Arnauts, S.; Verstraeten, K.; Schaekers, M.; Heyrts, M.M.

2000-01-01

As critical dimensions of integrated circuits continue to decrease, high dielectric constant materials such as silicon nitride are being considered to replace silicon dioxide in capacitors and transistors. The achievement of low levels of metal contamination in these layers is critical for high performance and reliability. Existing methods of quantitative analysis of trace metals in silicon nitride require high amounts of sample (from about 0.1 to 1 g, compared to a mass of 0.2 mg for a 2 nm thick film on a 8'' silicon wafer), and involve digestion steps not applicable to films on wafers or non-standard techniques such as neutron activation analysis. A novel approach has recently been developed to analyze trace metals in thin films with analytical techniques currently used in the semiconductor industry. Sample preparation consists of three steps: (1) decomposition of the silicon nitride matrix by moist HF condensed at the wafer surface to form ammonium fluosilicate. (2) vaporization of the fluosilicate by a short heat treatment at 300 o C. (3) collection of contaminants by scanning the wafer surface with a solution droplet (VPD-DSC procedure). The determination of trace metals is performed by drying the droplet on the wafer and by analyzing the residue by TXRF, as it offers the advantages of multi-elemental analysis with no dilution of the sample. The lower limits of detection for metals in 2 nm thick films on 8'' silicon wafers range from about 10 to 200 ng/g. The present study will focus on the matrix effects and the possible loss of analyte associated with the evaporation of the fluosilicate salt, in relation with the accuracy and the reproducibility of the method. The benefits of using an internal standard will be assessed. Results will be presented from both model samples (ammonium fluoride contaminated with metallic salts) and real samples (silicon nitride films from a production tool). (author)

Homogeneity analysis of high yield manufacturing process of mems-based pzt thick film vibrational energy harvesters

DEFF Research Database (Denmark)

Lei, Anders; Xu, Ruichao; Pedersen, C.M.

2011-01-01

This work presents a high yield wafer scale fabrication of MEMS-based unimorph silicon/PZT thick film vibrational energy harvesters aimed towards vibration sources with peak frequencies in the range of a few hundred Hz. By combining KOH etching with mechanical front side protection, SOI wafer...... to accurately define the thickness of the silicon part of the harvester and a silicon compatible PZT thick film screen-printing technique, we are able to fabricate energy harvesters on wafer scale with a yield higher than 90%. The characterization of the fabricated harvesters is focused towards the full wafer....../mass-production aspect; hence the analysis of uniformity in harvested power and resonant frequency....

Report on 1979 result of Sunshine Project. R and D on solar power generation system (R and D on particle non-accelerated growth type silicon thin film crystal); 1979 nendo taiyoko hatsuden system no kenkyu kaihatsu seika hokokusho. Ryushi hikasoku seichogata silicon usumaku kessho no kenkyu kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

1980-03-01

The R and D was intended to establish the manufacturing technology of a particle non-accelerated growth type silicon thin film crystal, for the purpose of developing a technology for enabling the production of a solar power generation system, whose price is practically 1/100 compared with that of building the system with the current technology, and the R and D was also intended to build the system using such silicon material. While a simple purification method was examined for a low purity metallurgical-grade silicon, a solar-grade silicon (SOG) was developed as the new material this year, with a solar cell experimentally manufactured having a structure directly joined to the substrate material and with evaluation carried out on the characteristic of such solar cell. The application of 'gettering' was tried which was for removing harmful impurities from the substrate obtained from such material, bringing an outlook of manufacturing a solar cell with a conversion efficiency of 10%. Concerning the SOG-Si, the efficiency of 13% or higher was attained through the improvement of the manufacturing process. This was the value comparable to the case of using a conventional high purity monocrystal wafer. Further, the application of an ion implantation method was studied for the purpose of getting a low cost. (NEDO)

GeSn-on-insulator substrate formed by direct wafer bonding

Energy Technology Data Exchange (ETDEWEB)

Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

2016-07-11

GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

Mechanically flexible optically transparent porous mono-crystalline silicon substrate

KAUST Repository

Rojas, Jhonathan Prieto; Syed, Ahad A.; Hussain, Muhammad Mustafa

2012-01-01

For the first time, we present a simple process to fabricate a thin (≥5μm), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon <100> wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates. © 2012 IEEE.

Automatic Semiconductor Wafer Image Segmentation for Defect Detection Using Multilevel Thresholding

Directory of Open Access Journals (Sweden)

Saad N.H.

2016-01-01

Full Text Available Quality control is one of important process in semiconductor manufacturing. A lot of issues trying to be solved in semiconductor manufacturing industry regarding the rate of production with respect to time. In most semiconductor assemblies, a lot of wafers from various processes in semiconductor wafer manufacturing need to be inspected manually using human experts and this process required full concentration of the operators. This human inspection procedure, however, is time consuming and highly subjective. In order to overcome this problem, implementation of machine vision will be the best solution. This paper presents automatic defect segmentation of semiconductor wafer image based on multilevel thresholding algorithm which can be further adopted in machine vision system. In this work, the defect image which is in RGB image at first is converted to the gray scale image. Median filtering then is implemented to enhance the gray scale image. Then the modified multilevel thresholding algorithm is performed to the enhanced image. The algorithm worked in three main stages which are determination of the peak location of the histogram, segmentation the histogram between the peak and determination of first global minimum of histogram that correspond to the threshold value of the image. The proposed approach is being evaluated using defected wafer images. The experimental results shown that it can be used to segment the defect correctly and outperformed other thresholding technique such as Otsu and iterative thresholding.

Silicon-Rich Silicon Carbide Hole-Selective Rear Contacts for Crystalline-Silicon-Based Solar Cells.

Science.gov (United States)

Nogay, Gizem; Stuckelberger, Josua; Wyss, Philippe; Jeangros, Quentin; Allebé, Christophe; Niquille, Xavier; Debrot, Fabien; Despeisse, Matthieu; Haug, Franz-Josef; Löper, Philipp; Ballif, Christophe

2016-12-28

The use of passivating contacts compatible with typical homojunction thermal processes is one of the most promising approaches to realizing high-efficiency silicon solar cells. In this work, we investigate an alternative rear-passivating contact targeting facile implementation to industrial p-type solar cells. The contact structure consists of a chemically grown thin silicon oxide layer, which is capped with a boron-doped silicon-rich silicon carbide [SiC x (p)] layer and then annealed at 800-900 °C. Transmission electron microscopy reveals that the thin chemical oxide layer disappears upon thermal annealing up to 900 °C, leading to degraded surface passivation. We interpret this in terms of a chemical reaction between carbon atoms in the SiC x (p) layer and the adjacent chemical oxide layer. To prevent this reaction, an intrinsic silicon interlayer was introduced between the chemical oxide and the SiC x (p) layer. We show that this intrinsic silicon interlayer is beneficial for surface passivation. Optimized passivation is obtained with a 10-nm-thick intrinsic silicon interlayer, yielding an emitter saturation current density of 17 fA cm -2 on p-type wafers, which translates into an implied open-circuit voltage of 708 mV. The potential of the developed contact at the rear side is further investigated by realizing a proof-of-concept hybrid solar cell, featuring a heterojunction front-side contact made of intrinsic amorphous silicon and phosphorus-doped amorphous silicon. Even though the presented cells are limited by front-side reflection and front-side parasitic absorption, the obtained cell with a V oc of 694.7 mV, a FF of 79.1%, and an efficiency of 20.44% demonstrates the potential of the p + /p-wafer full-side-passivated rear-side scheme shown here.

Flexible Thermoelectric Generators on Silicon Fabric

KAUST Repository

Sevilla, Galo T.

2012-11-01

In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

International Nuclear Information System (INIS)

Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

2000-01-01

Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

Science.gov (United States)

Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

2018-05-01

An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

Achievement report for fiscal 1997 on developing a silicon manufacturing process with reduced energy consumption. Investigation and research on analyzing practical application of a technology to manufacture solar cell silicon raw materials; 1997 nendo energy shiyo gorika silicon seizo process kaihatsu. Taiyo denchi silicon genryo seizo gijutsu no jitsuyoka kaiseki ni kansuru chosa kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

1998-03-01

This paper describes the achievement in fiscal 1997 of analyzing practical application of a technology to manufacture solar cell silicon raw materials. Silicon consumption for solar cells in fiscal 1997 has increased to 2000-ton level, and the supply has been very tight. For drastic improvement in the demand and supply situation, development of SOG-Si manufacturing technology and its early practical application are desired. The development of the NEDO mass-production technology using melting and refining has completed constructing the process facilities in fiscal 1998, and will enter the stage of operational research. However, insufficiency in the basic data about behavior of impurities is inhibiting the development. In the substrate manufacturing technology, discussions have shown progress on use of diversifying silicons outside the standard by using the electromagnetic casting process. For slicing and processing the substrates, development of a high-performance slicing equipment and automatic rough rinsing machine is under way. Properties required on silicon raw materials vary considerably widely because of difference in cell making systems and conditions, which is attributable to unknown impurity behavior. When 1GW production is assumed, the cell module manufacturing cost is calculated as 137 yen/W, for which low-cost mass production for its realization, slicing productivity enhancement, and cost reduction are required. The paper also describes site surveys in overseas countries. (NEDO)

Wafer integrated micro-scale concentrating photovoltaics

Science.gov (United States)

Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

2017-09-01

Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

Effect of silicon solar cell processing parameters and crystallinity on mechanical strength

Energy Technology Data Exchange (ETDEWEB)

Popovich, V.A.; Yunus, A.; Janssen, M.; Richardson, I.M. [Delft University of Technology, Department of Materials Science and Engineering, Delft (Netherlands); Bennett, I.J. [Energy Research Centre of the Netherlands, Solar Energy, PV Module Technology, Petten (Netherlands)

2011-01-15

Silicon wafer thickness reduction without increasing the wafer strength leads to a high breakage rate during subsequent handling and processing steps. Cracking of solar cells has become one of the major sources of solar module failure and rejection. Hence, it is important to evaluate the mechanical strength of solar cells and influencing factors. The purpose of this work is to understand the fracture behavior of silicon solar cells and to provide information regarding the bending strength of the cells. Triple junctions, grain size and grain boundaries are considered to investigate the effect of crystallinity features on silicon wafer strength. Significant changes in fracture strength are found as a result of metallization morphology and crystallinity of silicon solar cells. It is observed that aluminum paste type influences the strength of the solar cells. (author)

I-line stepper based overlay evaluation method for wafer bonding applications

Science.gov (United States)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

Geometric accuracy of wax bade models manufactured in silicon moulds

Directory of Open Access Journals (Sweden)

G. Budzik

2010-01-01

Full Text Available The article presents the test results of the geometric accuracy of wax blade models manufactured in silicon moulds in the Rapid Tooling process, with the application of the Vacuum Casting technology. In batch production casting waxes are designed for the manufacture of models and components of model sets through injection into a metal die. The objective of the tests was to determine the possibility of using traditional wax for the production of casting models in the rapid prototyping process. Blade models made of five types of casting wax were measured. The definition of the geometric accuracy of wax blade models makes it possible to introduce individual modifications aimed at improving their shape in order to increase the dimensional accuracy of blade models manufactured in the rapid prototyping process.

Surface Passivation for Silicon Heterojunction Solar Cells

NARCIS (Netherlands)

Deligiannis, D.

2017-01-01

Silicon heterojunction solar cells (SHJ) are currently one of the most promising solar cell technologies in the world. The SHJ solar cell is based on a crystalline silicon (c-Si) wafer, passivated on both sides with a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer. Subsequently, p-type

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

Science.gov (United States)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

Science.gov (United States)

Balpande, Suresh S.; Pande, Rajesh S.

2016-04-01

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of harvester and

Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

International Nuclear Information System (INIS)

Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

2013-01-01

This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

Directory of Open Access Journals (Sweden)

Nigel T. Maidment

2008-08-01

Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

Science.gov (United States)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

Low temperature sacrificial wafer bonding for planarization after very deep etching

NARCIS (Netherlands)

Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

1994-01-01

A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

Silicon Nanowire Fabrication Using Edge and Corner Lithography

NARCIS (Netherlands)

Yagubizade, H.; Berenschot, Johan W.; Jansen, Henricus V.; Elwenspoek, Michael Curt; Tas, Niels Roelof

2010-01-01

This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features

Silicon pore optics for the international x-ray observatory

Science.gov (United States)

Wille, E.; Wallace, K.; Bavdaz, M.; Collon, M. J.; Günther, R.; Ackermann, M.; Beijersbergen, M. W.; Riekerink, M. O.; Blom, M.; Lansdorp, B.; de Vreede, L.

2017-11-01

Lightweight X-ray Wolter optics with a high angular resolution will enable the next generation of X-ray telescopes in space. The International X-ray Observatory (IXO) requires a mirror assembly of 3 m2 effective area (at 1.5 keV) and an angular resolution of 5 arcsec. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor industry. We present the manufacturing process ranging from single mirror plates towards complete focusing mirror modules mounted in flight configuration. The performance of the mirror modules is tested using X-ray pencil beams or full X-ray illumination. In 2009, an angular resolution of 9 arcsec was achieved, demonstrating the improvement of the technology compared to 17 arcsec in 2007. Further development activities of Silicon Pore Optics concentrate on ruggedizing the mounting system and performing environmental tests, integrating baffles into the mirror modules and assessing the mass production.

Fabrication of a silicon oxide stamp by edge lithography reinforced with silicon nitride for nanoimprint lithography

NARCIS (Netherlands)

Zhao, Yiping; Berenschot, Johan W.; de Boer, M.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

2008-01-01

The fabrication of a stamp reinforced with silicon nitride is presented for its use in nanoimprint lithography. The fabrication process is based on edge lithography using conventional optical lithography and wet anisotropic etching of 110 silicon wafers. SiO2 nano-ridges of 20 nm in width were

The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

International Nuclear Information System (INIS)

Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

2004-01-01

We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

Science.gov (United States)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

Material Properties of Laser-Welded Thin Silicon Foils

Directory of Open Access Journals (Sweden)

M. T. Hessmann

2013-01-01

Full Text Available An extended monocrystalline silicon base foil offers a great opportunity to combine low-cost production with high efficiency silicon solar cells on a large scale. By overcoming the area restriction of ingot-based monocrystalline silicon wafer production, costs could be decreased to thin film solar cell range. The extended monocrystalline silicon base foil consists of several individual thin silicon wafers which are welded together. A comparison of three different approaches to weld 50 μm thin silicon foils is investigated here: (1 laser spot welding with low constant feed speed, (2 laser line welding, and (3 keyhole welding. Cross-sections are prepared and analyzed by electron backscatter diffraction (EBSD to reveal changes in the crystal structure at the welding side after laser irradiation. The treatment leads to the appearance of new grains and boundaries. The induced internal stress, using the three different laser welding processes, was investigated by micro-Raman analysis. We conclude that the keyhole welding process is the most favorable to produce thin silicon foils.

Wafer-scale micro-optics fabrication

Science.gov (United States)

Voelkel, Reinhard

2012-07-01

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

International Nuclear Information System (INIS)

Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

2006-01-01

A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

Results from a first production of enhanced Silicon Sensor Test Structures produced by ITE Warsaw

Science.gov (United States)

Bergauer, T.; Dragicevic, M.; Frey, M.; Grabiec, P.; Grodner, M.; Hänsel, S.; Hartmann, F.; Hoffmann, K.-H.; Hrubec, J.; Krammer, M.; Kucharski, K.; Macchiolo, A.; Marczewski, J.

2009-01-01

Monitoring the manufacturing process of silicon sensors is essential to ensure stable quality of the produced detectors. During the CMS silicon sensor production we were utilising small Test Structures (TS) incorporated on the cut-away of the wafers to measure certain process-relevant parameters. Experience from the CMS production and quality assurance led to enhancements of these TS. Another important application of TS is the commissioning of new vendors. The measurements provide us with a good understanding of the capabilities of a vendor's process. A first batch of the new TS was produced at the Institute of Electron Technology in Warsaw Poland. We will first review the improvements to the original CMS test structures and then discuss a selection of important measurements performed on this first batch.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

Science.gov (United States)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Modification of the properties of porous silicon on adsorption of iodine molecules

International Nuclear Information System (INIS)

Vorontsov, A. S.; Osminkina, L. A.; Tkachenko, A. E.; Konstantinova, E. A.; Elenskii, V. G.; Timoshenko, V. Yu.; Kashkarov, P. K.

2007-01-01

Infrared spectroscopy and electron spin resonance measurements are used to study the properties of porous silicon layers on adsorption of the I 2 iodine molecules. The layers are formed on the p-an n-Si single-crystal wafers. It is established that, in the atmosphere of I 2 molecules, the charge-carrier concentration in the layers produced on the p-type wafers can be noticeably increased: the concentration of holes can attain values on the order of ∼10 18 -10 19 cm -3 . In porous silicon layers formed on the n-type wafers, the adsorption-induced inversion of the type of charge carriers and the partial substitution of silicon-hydrogen bonds by silicon-iodine bonds are observed. A decrease in the concentration of surface paramagnetic defects, P b centers, is observed in the samples with adsorbed iodine. The experimental data are interpreted in the context of the model in which it is assumed that both deep and shallow acceptor states are formed at the surface of silicon nanocrystals upon the adsorption of I 2 molecules

Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

International Nuclear Information System (INIS)

Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

2013-01-01

The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

NARCIS (Netherlands)

Popovich, V.A.

2013-01-01

Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

Metallisation Technology of Silicon Solar Cells Using the Convectional and Laser Technique

Directory of Open Access Journals (Sweden)

Leszek A. Dobrzanski

2013-07-01

Full Text Available The aim of the paper was to optimize the Selective Laser Sintering (SLS and co-firing in the infrared conveyor furnace parameters in front Screen Printed (SP contacts. The co-firing in the infrared conveyor furnace was carried out at various temperature. The SLS was carried out at various a laser beam, scanning speed of the laser beam and front electrode thickness. The investigations were carried out on monocrystalline silicon wafers. During investigations was applied a silver powder with the grain size of 40 μm. The contacts parameters are obtained according to the Transmission Line Model (TLM measurements. Firstly, this paper shows the comparison between the convectional an unconventional method of manufacturing front contacts of monocrystalline silicon solar cells with the different morphology of silicon for comparative purposes. Secondly, the papers shows technological recommendations for both methods in relation to parameters such as: the optimal paste composition, the morphology of the silicon substrate to produce the front electrode of silicon solar cells, which were selected experimentally in order to produce a uniformly melted structure, well adhering to the substrate, with the low resistance of the front electrode-to-substrate joint zone.

In-line high-rate evaporation of aluminum for the metallization of silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Mader, Christoph Paul

2012-07-11

This work focuses on the in-line high-rate evaporation of aluminum for contacting rear sides of silicon solar cells. The substrate temperature during the deposition process, the wafer bow after deposition, and the electrical properties of evaporated contacts are investigated. Furthermore, this work demonstrates for the first time the formation of aluminum-doped silicon regions by the in-line high-rate evaporation of aluminum without any further temperature treatment. The temperature of silicon wafers during in-line high-rate evaporation of aluminum is investigated in this work. The temperatures are found to depend on the wafer thickness W, the aluminum layer thickness d, and on the wafer emissivity {epsilon}. Two-dimensional finite-element simulations reproduce the measured peak temperatures with an accuracy of 97%. This work also investigates the wafer bow after in-line high-rate evaporation and shows that the elastic theory overestimates the wafer bow of planar Si wafers. The lower bow is explained with plastic deformation in the Al layer. Due to the plastic deformation only the first 79 K in temperature decrease result in a bow formation. Furthermore the electrical properties of evaporated point contacts are examined in this work. Parameterizations for the measured saturation currents of contacted p-type Si wafers and of contacted boron-diffused p{sup +}-type layers are presented. The contact resistivity of the deposited Al layers to silicon for various deposition processes and silicon surface concentrations are presented and the activation energy of the contact formation is determined. The measured saturation current densities and contact resistivities of the evaporated contacts are used in one-dimensional numerical Simulations and the impact on energy conversion efficiency of replacing a screen-printed rear side by an evaporated rear side is presented. For the first time the formation of aluminum-doped p{sup +}-type (Al-p{sup +}) silicon regions by the in

Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

International Nuclear Information System (INIS)

Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

2010-01-01

This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

Application Of Artificial Neural Networks In Modeling Of Manufactured Front Metallization Contact Resistance For Silicon Solar Cells

Directory of Open Access Journals (Sweden)

Musztyfaga-Staszuk M.

2015-09-01

Full Text Available This paper presents the application of artificial neural networks for prediction contact resistance of front metallization for silicon solar cells. The influence of the obtained front electrode features on electrical properties of solar cells was estimated. The front electrode of photovoltaic cells was deposited using screen printing (SP method and next to manufactured by two methods: convectional (1. co-fired in an infrared belt furnace and unconventional (2. Selective Laser Sintering. Resistance of front electrodes solar cells was investigated using Transmission Line Model (TLM. Artificial neural networks were obtained with the use of Statistica Neural Network by Statsoft. Created artificial neural networks makes possible the easy modelling of contact resistance of manufactured front metallization and allows the better selection of production parameters. The following technological recommendations for the screen printing connected with co-firing and selective laser sintering technology such as optimal paste composition, morphology of the silicon substrate, co-firing temperature and the power and scanning speed of the laser beam to manufacture the front electrode of silicon solar cells were experimentally selected in order to obtain uniformly melted structure well adhered to substrate, of a small front electrode substrate joint resistance value. The prediction possibility of contact resistance of manufactured front metallization is valuable for manufacturers and constructors. It allows preserving the customers’ quality requirements and bringing also measurable financial advantages.

Development of an In-Line Minority-Carrier Lifetime Monitoring Tool for Process Control during Fabrication of Crystalline Silicon Solar Cells: Annual Subcontract Report, June 2003 (Revised)

Energy Technology Data Exchange (ETDEWEB)

Sinton, R. A.

2004-04-01

Under the PV Manufacturing R&D subcontract''Development of an In-Line, Minority-Carrier Lifetime Monitoring Tool for Process Control during Fabrication of Crystalline Silicon Solar Cells'', Sinton Consulting developed prototypes for several new instruments for use in the manufacture of silicon solar cells. These instruments are based on two families of R&D instruments that were previously available, an illumination vs. open-circuit-voltage technique and the quasi-steady state RF photoconductance technique for measuring minority-carrier lifetime. Compared to the previous instruments, the new prototypes are about 20 times faster per measurement, and have automated data analysis that does not require user intervention even when confronted by challenging cases. For example, un-passivated multi-crystalline wafers with large variations in lifetime and trapping behavior can be measured sequentially without error. Five instruments have been prototyped in this project to date, including a block tester for evaluating cast or HEM silicon blocks, a CZ ingot tester, an FZ boule tester for use with long-lifetime silicon, and an in-line sample head for measuring wafers. The CZ ingot tester and the FZ boule tester are already being used within industry and there is interest in the other prototypes. For each instrument, substantial R&D work was required in developing the device physics and analysis as well as for the hardware. This work has been documented in a series of application notes and conference publications, and will result in significant improvements for both the R&D and the industrial types of instruments.

Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

International Nuclear Information System (INIS)

Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

2009-01-01

Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

Report on achievements in fiscal 1998. Development of silicon manufacturing process to rationalize energy usage (Development of mass production technology for solar-grade silicon); 1998 nendo energy shiyo gorika silicon seizo process kaihatsu seika hokokusho. Taiyo denchiyo silicon ryosanka seizo gijutsu no kaihatsu

Energy Technology Data Exchange (ETDEWEB)

NONE

1999-03-01

In the proliferation stage of solar cells, a technology is required to manufacture low-cost SOG-Si that can handle small quantity production. Development is being made on a manufacturing technology using high purity metallic silicon (99.5%) as the raw material. Considering that the subject impurities are P, B and metallic impurities (Fe, Ti and Al), a manufacturing method consisting of the following processes is being developed: metallic silicon/phosphorus removal, solidification and rough refining/boron removal, solidification and fine refining. Discussions are being advanced on phosphorus removal by using a large electron beam fusion equipment, and at the same time, the discussions are supported by fabricating and installing a large equipment intended of removing boron and the metallic impurities. Boron is removed by oxidizing it with steam. Therefore, the basic mechanism of the equipment is to spray argon plasma added with steam onto the molten silicon surface. In boron removal, diffusion of boron onto the reaction interface in the primary reaction determines the rate. A boron removal rate for B/10 to 0.1 ppm of 45 kg/h as maximum was achieved. The derived silicon has met the requirement. (NEDO)

Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

Science.gov (United States)

Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

2017-06-01

In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

Science.gov (United States)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

International Nuclear Information System (INIS)

Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

2004-01-01

Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

Science.gov (United States)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

Application of a layout/material handling design method to a furnace area in a 300 mm wafer fab

NARCIS (Netherlands)

Hesen, P.M.C.; Renders, P.J.J.; Rooda, J.E.

2001-01-01

For many years, material handling within the semiconductor industry has become increasingly important. With the introduction of 300 mm wafer production, ergonomics and product safety become more critical. Therefore, the manufacturers of semiconductor wafer fabs are considering the automation of

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

A new approach to measure the temperature in rapid thermal processing

Science.gov (United States)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is acoustic method is

Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

Science.gov (United States)

Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

2011-07-12

An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Science and technology of plasma activated direct wafer bonding

Science.gov (United States)

Roberds, Brian Edward

This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

Science.gov (United States)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

Science.gov (United States)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

Science.gov (United States)

Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

2015-04-06

Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca

2015-09-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

2015-01-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Micro-spectroscopy on silicon wafers and solar cells

Directory of Open Access Journals (Sweden)

Gundel Paul

2011-01-01

Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

Additive Manufacturing of Overhang Structures Using Moisture-Cured Silicone with Support Material

Directory of Open Access Journals (Sweden)

Mohan Muthusamy

2018-04-01

Full Text Available Additive manufacturing (AM of soft materials has a wide variety of applications, such as customized or wearable devices. Silicone is one popular material for these applications given its favorable material properties. However, AM of silicone parts with overhang structures remains challenging due to the soft nature of the material. Overhang structures are the areas where there is no underlying structure. Typically, a support material is used and built in the underlying space so that the overhang structures can be built upon it. Currently, there is no support structure that has been used for AM of silicone. The goal of this study is to develop an AM process to fabricate silicone parts with overhang structures. We first identified and confirmed poly-vinyl alcohol (PVA, a water-soluble material, as a suitable support material for silicone by evaluating the adhesion strength between silicone and PVA. Process parameters for the support material, including critical overhang angle and minimum infill density for the support material, are identified. However, overhang angle alone is not the only determining factor for support material. As silicone is a soft material, it deflects due to its own weight when the height of the overhang structure increases. A finite element model is developed to estimate the critical overhang height paired with different overhang angles to determine whether the use of support material is needed. Finally, parts with overhang structures are printed to demonstrate the capability of the developed process.

Lattice location of impurities in silicon Carbide

CERN Document Server

AUTHOR|(CDS)2085259; Correia Martins, João Guilherme

The presence and behaviour of transition metals (TMs) in SiC has been a concern since the start of producing device-grade wafers of this wide band gap semiconductor. They are unintentionally introduced during silicon carbide (SiC) production, crystal growth and device manufacturing, which makes them difficult contaminants to avoid. Once in SiC they easily form deep levels, either when in the isolated form or when forming complexes with other defects. On the other hand, using intentional TM doping, it is possible to change the electrical, optical and magnetic properties of SiC. TMs such as chromium, manganese or iron have been considered as possible candidates for magnetic dopants in SiC, if located on silicon lattice sites. All these issues can be explored by investigating the lattice site of implanted TMs. This thesis addresses the lattice location and thermal stability of the implanted TM radioactive probes 56Mn, 59Fe, 65Ni and 111Ag in both cubic 3C- and hexagonal 6H SiC polytypes by means of emission cha...

Manipulation of polystyrene nanoparticles on a silicon wafer in the peak force tapping mode in water: pH-dependent friction and adhesion force

Energy Technology Data Exchange (ETDEWEB)

Schiwek, Simon; Stark, Robert W., E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de; Dietz, Christian, E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany); Physics of Surfaces, Institute of Materials Science, Technische Universität Darmstadt, Alarich-Weiss-Str. 16, 64287 Darmstadt (Germany); Heim, Lars-Oliver [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany)

2015-03-14

The friction force between nanoparticles and a silicon wafer is a crucial parameter for cleaning processes in the semiconductor industry. However, little is known about the pH-dependency of the friction forces and the shear strength at the interface. Here, we push polystyrene nanoparticles, 100 nm in diameter, with the tip of an atomic force microscope and measure the pH-dependency of the friction, adhesion, and normal forces on a silicon substrate covered with a native silicon dioxide layer. The peak force tapping mode was applied to control the vertical force on these particles. We successively increased the applied load until the particles started to move. The main advantage of this technique over single manipulation processes is the achievement of a large number of manipulation events in short time and in a straightforward manner. Geometrical considerations of the interaction forces at the tip-particle interface allowed us to calculate the friction force and shear strength from the applied normal force depending on the pH of an aqueous solution. The results clearly demonstrated that particle removal should be performed with a basic solution at pH 9 because of the low interaction forces between particle and substrate.

Electroless porous silicon formation applied to fabrication of boron–silica–glass cantilevers

International Nuclear Information System (INIS)

Teva, J; Davis, Z J; Hansen, O

2010-01-01

This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5–1 mm 3 ) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing the etching rate and reproducibility of the etching. In addition to that, a study of the morphology of the pore that is obtained by this technique is presented. The results from the characterization of the process are applied to the fabrication of boron–silica–glass cantilevers that serve as a platform for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH solution

Increasing the efficiency of silicon heterojunction solar cells and modules by light soaking

KAUST Repository

Kobayashi, Eiji; De Wolf, Stefaan; Levrat, Jacques; Descoeudres, Antoine; Despeisse, Matthieu; Haug, Franz-Josef; Ballif, Christophe

2017-01-01

Silicon heterojunction solar cells use crystalline silicon (c-Si) wafers as optical absorbers and employ bilayers of doped/intrinsic hydrogenated amorphous silicon (a-Si:H) to form passivating contacts. Recently, we demonstrated that such solar

Results from a first production of enhanced Silicon Sensor Test Structures produced by ITE Warsaw

Energy Technology Data Exchange (ETDEWEB)

Bergauer, T. [Institute of High Energy Physics, Austrian Academy of Sciences, Nikolsdorfergasse 18, 1050 Vienna (Austria); Dragicevic, M. [Institute of High Energy Physics, Austrian Academy of Sciences, Nikolsdorfergasse 18, 1050 Vienna (Austria)], E-mail: dragicevic@oeaw.ac.at; Frey, M. [Institut fuer Experimentelle Kernphysik (IEKP), Universitaet Karlsruhe (Thailand) (Germany); Grabiec, P.; Grodner, M. [Institute of Electron Technology (ITE), Warsaw (Poland); Haensel, S. [Institute of High Energy Physics, Austrian Academy of Sciences, Nikolsdorfergasse 18, 1050 Vienna (Austria); Hartmann, F.; Hoffmann, K.-H. [Institut fuer Experimentelle Kernphysik (IEKP), Universitaet Karlsruhe (Thailand) (Germany); Hrubec, J.; Krammer, M. [Institute of High Energy Physics, Austrian Academy of Sciences, Nikolsdorfergasse 18, 1050 Vienna (Austria); Kucharski, K. [Institute of Electron Technology (ITE), Warsaw (Poland); Macchiolo, A. [Max-Planck-Institut fuer Physik (MPI), Munich (Germany); Marczewski, J. [Institute of Electron Technology (ITE), Warsaw (Poland)

2009-01-01

Monitoring the manufacturing process of silicon sensors is essential to ensure stable quality of the produced detectors. During the CMS silicon sensor production we were utilising small Test Structures (TS) incorporated on the cut-away of the wafers to measure certain process-relevant parameters. Experience from the CMS production and quality assurance led to enhancements of these TS. Another important application of TS is the commissioning of new vendors. The measurements provide us with a good understanding of the capabilities of a vendor's process. A first batch of the new TS was produced at the Institute of Electron Technology in Warsaw Poland. We will first review the improvements to the original CMS test structures and then discuss a selection of important measurements performed on this first batch.

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

Energy Technology Data Exchange (ETDEWEB)

Balpande, Suresh S., E-mail: balpandes@rknec.edu [Ph.D.. Scholar, Department of Electronics Engineering Shri Ramdeobaba College of Engineering & Management, Nagpur-13, (M.S.) (India); Pande, Rajesh S. [Professor, Department of Electronics Engineering Shri Ramdeobaba College of Engineering & Management, Nagpur-13, (M.S.) (India)

2016-04-13

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of

Design and fabrication of non silicon substrate based MEMS energy harvester for arbitrary surface applications

International Nuclear Information System (INIS)

Balpande, Suresh S.; Pande, Rajesh S.

2016-01-01

Internet of Things (IoT) uses MEMS sensor nodes and actuators to sense and control objects through Internet. IOT deploys millions of chemical battery driven sensors at different locations which are not reliable many times because of frequent requirement of charging & battery replacement in case of underground laying, placement at harsh environmental conditions, huge count and difference between demand (24 % per year) and availability (energy density growing rate 8% per year). Energy harvester fabricated on silicon wafers have been widely used in manufacturing MEMS structures. These devices require complex fabrication processes, costly chemicals & clean room. In addition to this silicon wafer based devices are not suitable for curved surfaces like pipes, human bodies, organisms, or other arbitrary surface like clothes, structure surfaces which does not have flat and smooth surface always. Therefore, devices based on rigid silicon wafers are not suitable for these applications. Flexible structures are the key solution for this problems. Energy transduction mechanism generates power from free surrounding vibrations or impact. Sensor nodes application has been purposefully selected due to discrete power requirement at low duty cycle. Such nodes require an average power budget in the range of about 0.1 microwatt to 1 mW over a period of 3-5 seconds. Energy harvester is the best alternate source in contrast with battery for sensor node application. Novel design of Energy Harvester based on cheapest flexible non silicon substrate i.e. cellulose acetate substrate have been modeled, simulated and analyzed on COMSOL multiphysics and fabricated using sol-gel spin coating setup. Single cantilever based harvester generates 60-75 mV peak electric potential at 22Hz frequency and approximately 22 µW power at 1K-Ohm load. Cantilever array can be employed for generating higher voltage by replicating this structure. This work covers design, optimization, fabrication of

Femtosecond versus nanosecond laser machining: comparison of induced stresses and structural changes in silicon wafers

International Nuclear Information System (INIS)

Amer, M.S.; El-Ashry, M.A.; Dosser, L.R.; Hix, K.E.; Maguire, J.F.; Irwin, Bryan

2005-01-01

Laser micromachining has proven to be a very successful tool for precision machining and microfabrication with applications in microelectronics, MEMS, medical device, aerospace, biomedical, and defense applications. Femtosecond (FS) laser micromachining is usually thought to be of minimal heat-affected zone (HAZ) local to the micromachined feature. The assumption of reduced HAZ is attributed to the absence of direct coupling of the laser energy into the thermal modes of the material during irradiation. However, a substantial HAZ is thought to exist when machining with lasers having pulse durations in the nanosecond (NS) regime. In this paper, we compare the results of micromachining a single crystal silicon wafer using a 150-femtosecond and a 30-nanosecond lasers. Induced stress and amorphization of the silicon single crystal were monitored using micro-Raman spectroscopy as a function of the fluence and pulse duration of the incident laser. The onset of average induced stress occurs at lower fluence when machining with the femtosecond pulse laser. Induced stresses were found to maximize at fluence of 44 J cm -2 and 8 J cm -2 for nanosecond and femtosecond pulsed lasers, respectively. In both laser pulse regimes, a maximum induced stress is observed at which point the induced stress begins to decrease as the fluence is increased. The maximum induced stress was comparable at 2.0 GPa and 1.5 GPa for the two lasers. For the nanosecond pulse laser, the induced amorphization reached a plateau of approximately 20% for fluence exceeding 22 J cm -2 . For the femtosecond pulse laser, however, induced amorphization was approximately 17% independent of the laser fluence within the experimental range. These two values can be considered nominally the same within experimental error. For femtosecond laser machining, some effect of the laser polarization on the amount of induced stress and amorphization was also observed

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

Science.gov (United States)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

Science.gov (United States)

Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

2018-01-01

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

Excellent Silicon Surface Passivation Achieved by Industrial Inductively Coupled Plasma Deposited Hydrogenated Intrinsic Amorphous Silicon Suboxide

Directory of Open Access Journals (Sweden)

Jia Ge

2014-01-01

Full Text Available We present an alternative method of depositing a high-quality passivation film for heterojunction silicon wafer solar cells, in this paper. The deposition of hydrogenated intrinsic amorphous silicon suboxide is accomplished by decomposing hydrogen, silane, and carbon dioxide in an industrial remote inductively coupled plasma platform. Through the investigation on CO2 partial pressure and process temperature, excellent surface passivation quality and optical properties are achieved. It is found that the hydrogen content in the film is much higher than what is commonly reported in intrinsic amorphous silicon due to oxygen incorporation. The observed slow depletion of hydrogen with increasing temperature greatly enhances its process window as well. The effective lifetime of symmetrically passivated samples under the optimal condition exceeds 4.7 ms on planar n-type Czochralski silicon wafers with a resistivity of 1 Ωcm, which is equivalent to an effective surface recombination velocity of less than 1.7 cms−1 and an implied open-circuit voltage (Voc of 741 mV. A comparison with several high quality passivation schemes for solar cells reveals that the developed inductively coupled plasma deposited films show excellent passivation quality. The excellent optical property and resistance to degradation make it an excellent substitute for industrial heterojunction silicon solar cell production.

Electro-optical properties of dislocations in silicon and their possible application for light emitters

Energy Technology Data Exchange (ETDEWEB)

Arguirov, Tzanimir Vladimirov

2007-10-14

This thesis addresses the electro-optical properties of silicon, containing dislocations. The work demonstrates that dislocation specific radiation may provide a means for optical diagnostics of solar cell grade silicon. It provides insight into the mechanisms governing the dislocation recombination activity, their radiation, and how are they influenced by other defects present in silicon. We demonstrate that photoluminescence mapping is useful for monitoring the recombination activity in solar cell grade silicon and can be applied for identification of contaminants, based on their photoluminescence signatures. It is shown that the recombination at dislocations is strongly influenced by the presence of metals at the dislocation sites. The dislocation radiation activity correlates with their electrical activity. It is shown that the dislocation and band-to-band luminescence are essentially anti-correlated. {beta}FeSi{sub 2} precipitates, with a luminescence at 0.8 eV, were detected within the grains of block cast materials. They exhibit a characteristic feature of quantum dots, namely blinking. The second aspect of the thesis concerns the topic of silicon based light emitters for on-chip optical interconnects. The goal is an enhancement of sub-band-gap or band-to-band radiation by controlled formation of dislocation-rich areas in microelectronics-grade silicon as well as understanding of the processes governing such enhancement. For light emitters based on band-to-band emission it is shown, that internal quantum efficiency of nearly 2 % can be achieved, but the emission is essentially generated in the bulk of the wafer. On the other hand, light emitters utilizing the emission from dislocation-rich areas of a well localized wafer depth were explored. Three different methods for reproducible formation of a dislocation-rich region beneath the wafer surface were investigated and evaluated in view of their room temperature sub-band-gap radiation: (1) silicon implantation

Comparative Study on Electronic, Emission, Spontaneous Property of Porous Silicon in Different Solvents

Directory of Open Access Journals (Sweden)

M. Naziruddin Khan

2014-01-01

Full Text Available Luminescent porous silicon (Psi fabricated by simple chemical etching technique in different organic solvents was studied. By quantifying the silicon wafer piece, optical properties of the Psi in solutions were investigated. Observation shows that no photoluminescence light of Psi in all solvents is emitted. Morphology of Psi in different solvents indicates that the structure and distribution of Psi are differently observed. Particles are uniformly dispersive with the sizes around more or less 5–8 nm. The crystallographic plane and high crystalline nature of Psi is observed by selected area diffraction (SED and XRD. Electronic properties of Psi in solutions are influenced due to the variation of quantity of wafer and nature of solvent. Influence in band gaps of Psi calculated by Tauc’s method is obtained due to change of absorption edge of Psi in solvents. PL intensities are observed to be depending on quantity of silicon wafer, etched cross-section area on wafer surface. Effects on emission peaks and bands of Psi under temperature annealing are observed. The spontaneous signals of Psi measured under high power Pico second laser 355 nm source are significant, influenced by the nature of solvent, pumped energy, and quantity of Si wafer piece used in etching process.

Selective etching of n-type silicon in pn junction structure in hydrofluoric acid and its application in silicon nanowire fabrication

International Nuclear Information System (INIS)

Wang Huiquan; Jin Zhonghe; Zheng Yangming; Ma Huilian; Wang Yuelin; Li Tie

2008-01-01

Boron is selectively implanted on the surface of an n-type silicon wafer to form a p-type area surrounded by an n-type area. The wafer is then put into a buffered oxide etch solution. It is found that the n-type area can be selectively etched without illumination, with an etching rate lower than 1 nm min -1 , while the p-type area can be selectively etched under illumination with a much higher etching rate. The possible mechanism of the etching phenomenon is discussed. A simple fabrication process of silicon nanowires is proposed according to the above phenomenon. In this process only traditional micro-electromechanical system technology is used. Dimensions of the fabricated nanowire can be controlled well. A 50 nm wide and 50 nm thick silicon nanowire has been formed using this method

120 mm Single-crystalline perovskite and wafers: towards viable applications

Institute of Scientific and Technical Information of China (English)

Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

2017-01-01

As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75％ RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

Synchronizing decentralized control loops for overall performance enhancement : a Youla framework applied to a wafer scanner

NARCIS (Netherlands)

Evers, E.; van de Wal, M.M.J.; Oomen, T.A.E.

2017-01-01

Manufacturing equipment often consists of multiple subsystems. For instance, in lithographic IC manufacturing, both a reticle stage and a wafer stage move synchronously. Traditionally, these subsystems are divided into manageable subproblems, at the expense of a suboptimal overall solution. The aim

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

Science.gov (United States)

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Single wafer rapid thermal multiprocessing

International Nuclear Information System (INIS)

Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

1989-01-01

Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

Science.gov (United States)

Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

2011-01-01

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

Nanopatterned Silicon Substrate Use in Heterojunction Thin Film Solar Cells Made by Magnetron Sputtering

Directory of Open Access Journals (Sweden)

Shao-Ze Tseng

2014-01-01

Full Text Available This paper describes a method for fabricating silicon heterojunction thin film solar cells with an ITO/p-type a-Si : H/n-type c-Si structure by radiofrequency magnetron sputtering. A short-circuit current density and efficiency of 28.80 mA/cm2 and 8.67% were achieved. Novel nanopatterned silicon wafers for use in cells are presented. Improved heterojunction cells are formed on a nanopatterned silicon substrate that is prepared with a self-assembled monolayer of SiO2 nanospheres with a diameter of 550 nm used as an etching mask. The efficiency of the nanopattern silicon substrate heterojunction cells was 31.49% greater than that of heterojunction cells on a flat silicon wafer.

Serial section scanning electron microscopy (S3EM) on silicon wafers for ultra-structural volume imaging of cells and tissues.

Science.gov (United States)

Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

2012-01-01

High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3)EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3) volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3)EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3)EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

Directory of Open Access Journals (Sweden)

Heinz Horstmann

Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

Directory of Open Access Journals (Sweden)

Liu Haijun

2015-12-01

Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

A simple chemical method for the separation of phosphorus interfering the trace element determinations by neutron activation analysis in high doped silicon wafers

International Nuclear Information System (INIS)

Wagler, H.; Flachowsky, J.

1986-01-01

Neutron activation analysis is one of the most available method for the determination of trace elements, but in the case of P-doped silicon wafers the 32 P-activity interferes the gamma spectrometry. It is not possible to determine the trace elements without chemical manipulations. On the other hand, time consuming chemical separations should be avoided. Therefore, a simple and rapid P-separation method has to be developed, in which the following twelve trace elements should be taken into consideration: Ag, As, Au, Co, Cr, Cu, Fe, Mo, Na, Sb, W, and Zn. After acid oxidative dissolution of the activated sample, P is present as phosphate ion. The phosphate ion is removed by precipitation as BiPO 4 . (author)

Highly Sensitive Bulk Silicon Chemical Sensors with Sub-5 nm Thin Charge Inversion Layers.

Science.gov (United States)

Fahad, Hossain M; Gupta, Niharika; Han, Rui; Desai, Sujay B; Javey, Ali

2018-03-27

There is an increasing demand for mass-producible, low-power gas sensors in a wide variety of industrial and consumer applications. Here, we report chemical-sensitive field-effect-transistors (CS-FETs) based on bulk silicon wafers, wherein an electrostatically confined sub-5 nm thin charge inversion layer is modulated by chemical exposure to achieve a high-sensitivity gas-sensing platform. Using hydrogen sensing as a "litmus" test, we demonstrate large sensor responses (>1000%) to 0.5% H 2 gas, with fast response (<60 s) and recovery times (<120 s) at room temperature and low power (<50 μW). On the basis of these performance metrics as well as standardized benchmarking, we show that bulk silicon CS-FETs offer similar or better sensing performance compared to emerging nanostructures semiconductors while providing a highly scalable and manufacturable platform.

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

Science.gov (United States)

Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

2018-05-01

Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

Directory of Open Access Journals (Sweden)

Zhiwei Zhang

2018-05-01

Full Text Available Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young’s modulus, ultimate tensile strength (UTS, and strain at fracture is observed.

Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

International Nuclear Information System (INIS)

Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

2011-01-01

This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

International Nuclear Information System (INIS)

Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

2002-01-01

Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

Advances in Contactless Silicon Defect and Impurity Diagnostics Based on Lifetime Spectroscopy and Infrared Imaging

Directory of Open Access Journals (Sweden)

Jan Schmidt

2007-01-01

Full Text Available This paper gives a review of some recent developments in the field of contactless silicon wafer characterization techniques based on lifetime spectroscopy and infrared imaging. In the first part of the contribution, we outline the status of different lifetime spectroscopy approaches suitable for the identification of impurities in silicon and discuss—in more detail—the technique of temperature- and injection-dependent lifetime spectroscopy. The second part of the paper focuses on the application of infrared cameras to analyze spatial inhomogeneities in silicon wafers. By measuring the infrared signal absorbed or emitted from light-generated free excess carriers, high-resolution recombination lifetime mappings can be generated within seconds to minutes. In addition, mappings of non-recombination-active trapping centers can be deduced from injection-dependent infrared lifetime images. The trap density has been demonstrated to be an important additional parameter in the characterization and assessment of solar-grade multicrystalline silicon wafers, as areas of increased trap density tend to deteriorate during solar cell processing.

Laser shock ignition of porous silicon based nano-energetic films

International Nuclear Information System (INIS)

Plummer, A.; Gascooke, J.; Shapter, J.; Kuznetsov, V. A.; Voelcker, N. H.

2014-01-01

Nanoporous silicon films on a silicon wafer were loaded with sodium perchlorate and initiated using illumination with infrared laser pulses to cause laser thermal ignition and laser-generated shock waves. Using Photon Doppler Velocimetry, it was determined that these waves are weak stress waves with a threshold intensity of 131 MPa in the silicon substrate. Shock generation was achieved through confinement of a plasma, generated upon irradiation of an absorptive paint layer held against the substrate side of the wafer. These stress waves were below the threshold required for sample fracturing. Exploiting either the laser thermal or laser-generated shock mechanisms of ignition may permit use of pSi energetic materials in applications otherwise precluded due to their environmental sensitivity

Laser shock ignition of porous silicon based nano-energetic films

Energy Technology Data Exchange (ETDEWEB)

Plummer, A.; Gascooke, J.; Shapter, J. [School of Chemical and Physical Sciences, Flinders University, 5042, Bedford Park (Australia); Centre of Expertise in Energetic Materials (CEEM), Bedford Park (Australia); Kuznetsov, V. A., E-mail: nico.voelcker@unisa.edu.au, E-mail: Valerian.Kuznetsov@dsto.defence.gov.au [School of Chemical and Physical Sciences, Flinders University, 5042, Bedford Park (Australia); Centre of Expertise in Energetic Materials (CEEM), Bedford Park (Australia); Weapons and Combat Systems Division, Defence Science and Technology Organisation, Edinburgh 5111 (Australia); Voelcker, N. H., E-mail: nico.voelcker@unisa.edu.au, E-mail: Valerian.Kuznetsov@dsto.defence.gov.au [Mawson Institute, University of South Australia, 5095, Mawson Lakes (Australia)

2014-08-07

Nanoporous silicon films on a silicon wafer were loaded with sodium perchlorate and initiated using illumination with infrared laser pulses to cause laser thermal ignition and laser-generated shock waves. Using Photon Doppler Velocimetry, it was determined that these waves are weak stress waves with a threshold intensity of 131 MPa in the silicon substrate. Shock generation was achieved through confinement of a plasma, generated upon irradiation of an absorptive paint layer held against the substrate side of the wafer. These stress waves were below the threshold required for sample fracturing. Exploiting either the laser thermal or laser-generated shock mechanisms of ignition may permit use of pSi energetic materials in applications otherwise precluded due to their environmental sensitivity.

Silicon heterojunction solar cell passivation in combination with nanocrystalline silicon oxide emitters

NARCIS (Netherlands)

Gatz, H.A.; Rath, J.K.; Verheijen, M.A.; Kessels, W.M.M.; Schropp, R.E.I.

2016-01-01

Silicon heterojunction solar cells (SHJ) are well known for their high efficiencies, enabled by their remarkably high open-circuit voltages (VOC). A key factor in achieving these values is a good passivation of the crystalline wafer interface. One of the restrictions during SHJ solar cell production

Fundamentals of semiconductor manufacturing and process control

CERN Document Server

May, Gary S

2006-01-01

A practical guide to semiconductor manufacturing from process control to yield modeling and experimental design Fundamentals of Semiconductor Manufacturing and Process Control covers all issues involved in manufacturing microelectronic devices and circuits, including fabrication sequences, process control, experimental design, process modeling, yield modeling, and CIM/CAM systems. Readers are introduced to both the theory and practice of all basic manufacturing concepts. Following an overview of manufacturing and technology, the text explores process monitoring methods, including those that focus on product wafers and those that focus on the equipment used to produce wafers. Next, the text sets forth some fundamentals of statistics and yield modeling, which set the foundation for a detailed discussion of how statistical process control is used to analyze quality and improve yields. The discussion of statistical experimental design offers readers a powerful approach for systematically varying controllable p...

Nanostructured silicon ferromagnet collected by a permanent neodymium magnet.

Science.gov (United States)

Okuno, Takahisa; Thürmer, Stephan; Kanoh, Hirofumi

2017-11-30

Nanostructured silicon (N-Si) was prepared by anodic electroetching of p-type silicon wafers. The obtained magnetic particles were separated by a permanent neodymium magnet as a magnetic nanostructured silicon (mN-Si). The N-Si and mN-Si exhibited different magnetic properties: the N-Si exhibited ferromagnetic-like behaviour, whereas the mN-Si exhibited superparamagnetic-like behaviour.

Silicon Nanowire Field-effect Chemical Sensor

OpenAIRE

Chen, S.

2011-01-01

This thesis describes the work that has been done on the project “Design and optimization of silicon nanowire for chemical sensing‿, including Si-NW fabrication, electrical/electrochemical modeling, the application as ISFET, and the build-up of Si- NW/LOC system for automatic sample delivery. A novel top-down fabrication technique was presented for single-crystal Si-NW fabrication realized with conventional microfabrication technique. High quality triangular Si-NWs were made with high wafer-s...

Silicon on insulator self-aligned transistors

Science.gov (United States)

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Development of Novel Front Contract Pastes for Crystalline Silicon Solar Cells

Energy Technology Data Exchange (ETDEWEB)

Duty, C.; Jellison, D. G.E. P.; Joshi, P.

2012-04-05

In order to improve the efficiencies of silicon solar cells, paste to silicon contact formation mechanisms must be more thoroughly understood as a function of paste chemistry, wafer properties and firing conditions. Ferro Corporation has been involved in paste development for over 30 years and has extensive expertise in glass and paste formulations. This project has focused on the characterization of the interface between the top contact material (silver paste) and the underlying silicon wafer. It is believed that the interface between the front contact silver and the silicon wafer plays a dominant role in the electrical performance of the solar cell. Development of an improved front contact microstructure depends on the paste chemistry, paste interaction with the SiNx, and silicon (“Si”) substrate, silicon sheet resistivity, and the firing profile. Typical front contact ink contains silver metal powders and flakes, glass powder and other inorganic additives suspended in an organic medium of resin and solvent. During fast firing cycles glass melts, wets, corrodes the SiNx layer, and then interacts with underlying Si. Glass chemistry is also a critical factor in the development of an optimum front contact microstructure. Over the course of this project, several fundamental characteristics of the Ag/Si interface were documented, including a higher-than-expected distribution of voids along the interface, which could significantly impact electrical conductivity. Several techniques were also investigated for the interfacial analysis, including STEM, EDS, FIB, EBSD, and ellipsometry.

Highly Manufacturable Deep (Sub-Millimeter) Etching Enabled High Aspect Ratio Complex Geometry Lego-Like Silicon Electronics

KAUST Repository

Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2017-01-01

A highly manufacturable deep reactive ion etching based process involving a hybrid soft/hard mask process technology shows high aspect ratio complex geometry Lego-like silicon electronics formation enabling free-form (physically flexible

Impedance-based structural health monitoring of additive manufactured structures with embedded piezoelectric wafers

Science.gov (United States)

Scheyer, Austin G.; Anton, Steven R.

2017-04-01

Embedding sensors within additive manufactured (AM) structures gives the ability to develop smart structures that are capable of monitoring the mechanical health of a system. AM provides an opportunity to embed sensors within a structure during the manufacturing process. One major limitation of AM technology is the ability to verify the geometric and material properties of fabricated structures. Over the past several years, the electromechanical impedance (EMI) method for structural health monitoring (SHM) has been proven to be an effective method for sensing damage in structurers. The EMI method utilizes the coupling between the electrical and mechanical properties of a piezoelectric transducer to detect a change in the dynamic response of a structure. A piezoelectric device, usually a lead zirconate titanate (PZT) ceramic wafer, is bonded to a structure and the electrical impedance is measured across as range of frequencies. A change in the electrical impedance is directly correlated to changes made to the mechanical condition of the structure. In this work, the EMI method is employed on piezoelectric transducers embedded inside AM parts to evaluate the feasibility of performing SHM on parts fabricated using additive manufacturing. The fused deposition modeling (FDM) method is used to print specimens for this feasibility study. The specimens are printed from polylactic acid (PLA) in the shape of a beam with an embedded monolithic piezoelectric ceramic disc. The specimen is mounted as a cantilever while impedance measurements are taken using an HP 4194A impedance analyzer. Both destructive and nondestructive damage is simulated in the specimens by adding an end mass and drilling a hole near the free end of the cantilever, respectively. The Root Mean Square Deviation (RMSD) method is utilized as a metric for quantifying damage to the system. In an effort to determine a threshold for RMSD, the values are calculated for the variation associated with taking multiple

Porous silicon: Synthesis and optical properties

International Nuclear Information System (INIS)

Naddaf, M.; Awad, F.

2006-01-01

Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

Porous silicon: Synthesis and optical properties

International Nuclear Information System (INIS)

Naddaf, M.; Awad, F.

2006-06-01

Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

International Nuclear Information System (INIS)

Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

Science.gov (United States)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

Fiscal 2000 achievement report. Development of energy use rationalization-oriented silicon manufacturing process (Survey and study of analysis of commercialization of solar-grade silicon material manufacturing technology); 2000 nendo shin energy sangyo gijutsu sogo kaihatsu kiko kyodo kenkyu gyomu seika hokokusho. Energy shiyo gorika silicon seizo process kaihatsu (Taiyodenchiyou silicon genryo seizo gijutsu no jitsuyoka kaiseki ni kansuru chosa kenkyu)

Energy Technology Data Exchange (ETDEWEB)

NONE

2001-03-01

The trend of technology development, problems harbored therein, trend of the market, and the like were investigated for supporting the development of technologies for the mass production and commercialization of solar-grade silicon materials. Concerning the future of production enhancement and cost reduction in the manufacture of polycrystalline silicon solar cells, studies were made from the technological viewpoint. The results are shown below. It is estimated that approximately 4,500 tons of material silicon will be necessary in 2005 and 6,500-10,700 tons in 2010. Since the melting purification method of NEDO (New Energy and Industrial Technology Development Organization) now under development step by step toward commercialization as well as the conventional source will provide the necessary amount of material silicon, it is inferred that the development of solar cells will go on without any restraint originating in the semiconductor industry. With the commercialization of the technologies so far developed and the development/commercialization of the fast-acting high-performance solar cell technology, probabilities are high that the polycrystalline silicon solar cell manufacturing cost in 2010 will be as low as to be on the 100 yen/W (93-118 yen/W) level which is the level now held up as the goal. (NEDO)

Tunnel Oxides Formed by Field-Induced Anodisation for Passivated Contacts of Silicon Solar Cells

Directory of Open Access Journals (Sweden)

Jingnan Tong

2018-02-01

Full Text Available Tunnel silicon oxides form a critical component for passivated contacts for silicon solar cells. They need to be sufficiently thin to allow carriers to tunnel through and to be uniform both in thickness and stoichiometry across the silicon wafer surface, to ensure uniform and low recombination velocities if high conversion efficiencies are to be achieved. This paper reports on the formation of ultra-thin silicon oxide layers by field-induced anodisation (FIA, a process that ensures uniform oxide thickness by passing the anodisation current perpendicularly through the wafer to the silicon surface that is anodised. Spectroscopical analyses show that the FIA oxides contain a lower fraction of Si-rich sub-oxides compared to wet-chemical oxides, resulting in lower recombination velocities at the silicon and oxide interface. This property along with its low temperature formation highlights the potential for FIA to be used to form low-cost tunnel oxide layers for passivated contacts of silicon solar cells.

Toward Annealing-Stable Molybdenum-Oxide-Based Hole-Selective Contacts For Silicon Photovoltaics

KAUST Repository

Essig, Stephanie

2018-02-21

Molybdenum oxide (MoOX) combines a high work function with broadband optical transparency. Sandwiched between a hydrogenated intrinsic amorphous silicon passivation layer and a transparent conductive oxide, this material allows a highly efficient hole-selective front contact stack for crystalline silicon solar cells. However, hole extraction from the Si wafer and transport through this stack degrades upon annealing at 190 °C, which is needed to cure the screen-printed Ag metallization applied to typical Si solar cells. Here, we show that effusion of hydrogen from the adjacent layers is a likely cause for this degradation, highlighting the need for hydrogen-lean passivation layers when using such metal-oxide-based carrier-selective contacts. Pre-MoOX-deposition annealing of the passivating a-Si:H layer is shown to be a straightforward approach to manufacturing MoOX-based devices with high fill factors using screen-printed metallization cured at 190 °C.

Study of irradiation induced defects in silicon

International Nuclear Information System (INIS)

Pal, Gayatri; Sebastian, K.C.; Somayajulu, D.R.S.; Chintalapudi, S.N.

2000-01-01

Pure high resistivity (6000 ohm-cm) silicon wafers were recoil implanted with 1.8 MeV 111 In ions. As-irradiated wafers showed a 13 MHz quadrupole interaction frequency, which was not observed earlier. The annealing behaviour of these defects in the implanted wafers was studied between room temperature and 1073 K. At different annealing temperatures two more interaction frequencies corresponding to defect complexes D2 and D3 are observed. Even though the experimental conditions were different, these are identical to the earlier reported ones. Based on an empirical point charge model calculation, an attempt is made to identify the configuration of these defect complexes. (author)

Microeconomics of process control in semiconductor manufacturing

Science.gov (United States)

Monahan, Kevin M.

2003-06-01

Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

Propagation of resist heating mask error to wafer level

Science.gov (United States)

Babin, S. V.; Karklin, Linard

2006-10-01

As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

Science.gov (United States)

Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

2018-02-01

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

Silicon Nanowires for Solar Thermal Energy Harvesting: an Experimental Evaluation on the Trade-off Effects of the Spectral Optical Properties.

Science.gov (United States)

Sekone, Abdoul Karim; Chen, Yu-Bin; Lu, Ming-Chang; Chen, Wen-Kai; Liu, Chia-An; Lee, Ming-Tsang

2016-12-01

Silicon nanowire possesses great potential as the material for renewable energy harvesting and conversion. The significantly reduced spectral reflectivity of silicon nanowire to visible light makes it even more attractive in solar energy applications. However, the benefit of its use for solar thermal energy harvesting remains to be investigated and has so far not been clearly reported. The purpose of this study is to provide practical information and insight into the performance of silicon nanowires in solar thermal energy conversion systems. Spectral hemispherical reflectivity and transmissivity of the black silicon nanowire array on silicon wafer substrate were measured. It was observed that the reflectivity is lower in the visible range but higher in the infrared range compared to the plain silicon wafer. A drying experiment and a theoretical calculation were carried out to directly evaluate the effects of the trade-off between scattering properties at different wavelengths. It is clearly seen that silicon nanowires can improve the solar thermal energy harnessing. The results showed that a 17.8 % increase in the harvest and utilization of solar thermal energy could be achieved using a silicon nanowire array on silicon substrate as compared to that obtained with a plain silicon wafer.

Silicon Microleaks for Inlets of Mass Spectrometers

Science.gov (United States)

Harpold, Dan; Hasso, Niemann; Jamieson, Brian G.; Lynch, Bernard A.

2009-01-01

Microleaks for inlets of mass spectrometers used to analyze atmospheric gases can be fabricated in silicon wafers by means of photolithography, etching, and other techniques that are commonly used in the manufacture of integrated circuits and microelectromechanical systems. The microleaks serve to limit the flows of the gases into the mass-spectrometer vacuums to specified very small flow rates consistent with the capacities of the spectrometer vacuum pumps. There is a need to be able to precisely tailor the dimensions of each microleak so as to tailor its conductance to a precise low value. (As used here, "conductance" signifies the ratio between the rate of flow in the leak and the pressure drop from the upstream to the downstream end of the leak.) To date, microleaks have been made, variously, of crimped metal tubes, pulled glass tubes, or frits. Crimped-metal and pulled-glass-tube microleaks cannot readily be fabricated repeatably to precise dimensions and are susceptible to clogging with droplets or particles. Frits tend to be differentially chemically reactive with various gas constituents and, hence, to distort the gas mixtures to be analyzed. The present approach involving microfabrication in silicon largely overcomes the disadvantages of the prior approaches.

Modification of inkjet printer for polymer sensitive layer preparation on silicon-based gas sensors

Directory of Open Access Journals (Sweden)

Tianjian Li

2015-04-01

Full Text Available Inkjet printing is a versatile, low cost deposition technology with the capabilities for the localized deposition of high precision, patterned deposition in a programmable way, and the parallel deposition of a variety of materials. This paper demonstrates a new method of modifying the consumer inkjet printer to prepare polymer-sensitive layers on silicon wafer for gas sensor applications. A special printing tray for the modified inkjet printer to support a 4-inch silicon wafer is designed. The positioning accuracy of the deposition system is tested, based on the newly modified printer. The experimental data show that the positioning errors in the horizontal direction are negligibly small, while the positioning errors in the vertical direction rise with the increase of the printing distance of the wafer. The method for making suitable ink to be deposited to form the polymer-sensitive layer is also discussed. In the testing, a solution of 0.1 wt% polyvinyl alcohol (PVA was used as ink to prepare a sensitive layer with certain dimensions at a specific location on the surface of the silicon wafer, and the results prove the feasibility of the methods presented in this article.

Comparison of aggregation behaviors between ionic liquid-type imidazolium gemini surfactant [C12-4-C12im]Br2 and its monomer [C12mim]Br on silicon wafer.

Science.gov (United States)

Ao, Mingqi; Xu, Guiying; Pang, Jinyu; Zhao, Taotao

2009-09-01

The aggregation of ionic liquid-type imidazolium gemini surfactant [C(12)-4-C(12)im]Br(2) on silicon wafer, which is compared with its monomer [C(12)mim]Br, have been studied. AFM morphology images and contact angle measurements suggest that the aggregations of [C(12)-4-C(12)im]Br(2) and [C(12)mim]Br on silicon wafer follow different mechanisms. Below the critical surface aggregation concentrations (CSAC), both surfactant molecules are adsorbed with their hydrophobic tails facing the air. But above the CSAC, [C(12)-4-C(12)im]Br(2) molecules finally form a bilayer structure with hydrophilic head groups facing the air, whereas [C(12)mim]Br molecules form a multilayer structure, and with increasing its concentration, the layer numbers increase with the hydrophobic chains and hydrophilic head groups facing the air by turns. Besides, the watery wettability of [C(12)-4-C(12)im]Br(2)-treated silica surface is lower than that of [C(12)mim]Br at the concentration of 5.0 cmc, and the infrared spectroscopy suggests that the poorer watery wettability of [C(12)-4-C(12)im]Br(2) may be relative to the less-ordered packing of methylene chains inside the aggregate. These different aggregation behaviors for the two surfactants ascribe to the different molecular structures and electrostatic interactions. This work would have certain theoretical guidance meaning on the modification of solid surface.

An overview of crystalline silicon solar cell technology: Past, present, and future

Science.gov (United States)

Sopian, K.; Cheow, S. L.; Zaidi, S. H.

2017-09-01

Crystalline silicon (c-Si) solar cell, ever since its inception, has been identified as the only economically and environmentally sustainable renewable resource to replace fossil fuels. Performance c-Si based photovoltaic (PV) technology has been equal to the task. Its price has been reduced by a factor of 250 over last twenty years (from ˜ 76 USD to ˜ 0.3 USD); its market growth is expected to reach 100 GWP by 2020. Unfortunately, it is still 3-4 times higher than carbon-based fuels. With the matured PV manufacturing technology as it exists today, continuing price reduction poses stiff challenges. Alternate manufacturing approaches in combination with thin wafers, low (< 10 x) optical enhancement with Fresnel lenses, band-gap engineering for enhanced optical absorption, and newer, advanced solar cell configurations including partially transparent bifacial and back contact solar cells will be required. This paper will present a detailed, cost-based analysis of advanced solar cell manufacturing technologies aimed at higher (˜ 22 %) efficiency with existing equipment and processes.

Effects of laser fluence on silicon modification by four-beam laser interference

International Nuclear Information System (INIS)

Zhao, Le; Li, Dayou; Wang, Zuobin; Yue, Yong; Zhang, Jinjin; Yu, Miao; Li, Siwei

2015-01-01

This paper discusses the effects of laser fluence on silicon modification by four-beam laser interference. In this work, four-beam laser interference was used to pattern single crystal silicon wafers for the fabrication of surface structures, and the number of laser pulses was applied to the process in air. By controlling the parameters of laser irradiation, different shapes of silicon structures were fabricated. The results were obtained with the single laser fluence of 354 mJ/cm 2 , 495 mJ/cm 2 , and 637 mJ/cm 2 , the pulse repetition rate of 10 Hz, the laser exposure pulses of 30, 100, and 300, the laser wavelength of 1064 nm, and the pulse duration of 7–9 ns. The effects of the heat transfer and the radiation of laser interference plasma on silicon wafer surfaces were investigated. The equations of heat flow and radiation effects of laser plasma of interfering patterns in a four-beam laser interference distribution were proposed to describe their impacts on silicon wafer surfaces. The experimental results have shown that the laser fluence has to be properly selected for the fabrication of well-defined surface structures in a four-beam laser interference process. Laser interference patterns can directly fabricate different shape structures for their corresponding applications

Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

International Nuclear Information System (INIS)

Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

2015-01-01

Graphical abstract: - Highlights: • How Ag transfers F − to the adjacent Si atom was investigated and deduced by DFT at atomic scale. • Three-electrode CV tests proved the transferring function of Ag in the etching reaction. • Uniform SiNWAs were fabricated on unpolished silicon wafers with KOH pretreatment. - Abstract: Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F − ) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F − , smaller azimuth angle of F−Ag(T4)−Si, shorter bond length of F−Si compared with F−Ag. As F − was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF 4 when it bonded with enough F − while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F − to Si

Highly Manufacturable Deep (Sub-Millimeter) Etching Enabled High Aspect Ratio Complex Geometry Lego-Like Silicon Electronics

KAUST Repository

Ghoneim, Mohamed T.

2017-02-01

A highly manufacturable deep reactive ion etching based process involving a hybrid soft/hard mask process technology shows high aspect ratio complex geometry Lego-like silicon electronics formation enabling free-form (physically flexible, stretchable, and reconfigurable) electronic systems.

Performance tests of developed silicon strip detector by using a 150 GeV electron beam

International Nuclear Information System (INIS)

Hyun, Hyojung; Jung, Sunwoo; Kah, Dongha; Kang, Heedong; Kim, Hongjoo; Park, Hwanbae

2008-01-01

We manufactured and characterized a silicon micro-strip detector to be used in a beam tracker. A silicon detector features a DC-coupled silicon strip sensor with VA1 Prime2 analog readout chips. The silicon strip sensors have been fabricated on 5-in. wafers at Electronics and Telecommunications Research Institute (Daejeon, Korea). The silicon strip sensor is single-sided and has 32 channels with a 1 mm pitch, and its active area is 3.2 by 3.2 cm 2 with 380 μm thickness. The readout electronics consists of VA hybrid, VA Interface, and FlashADC and Control boards. Analog signals from the silicon strip sensor were being processed by the analog readout chips on the VA hybrid board. Analog signals were then changed into digital signals by a 12 bit 25 MHz FlashADC. The digital signals were read out by the Linux-operating PC through the FlashADC-USB2 interface. The DAQ system and analysis programs were written in the framework of ROOT package. The beam test with the silicon detector had been performed at CERN beam facility. We used a 150 GeV electron beam out of the SPS(Super Proton Synchrotron) H2 beam line. We present beam test setup and measurement result of signal-to-noise ratio of each strip channel. (author)

Combination of gettering and etching in multicrystalline silicon used in solar cells processing

International Nuclear Information System (INIS)

Dimassi, W.; Bouaicha, M.; Nouri, H.; Ben Nasrallah, S.; Bessais, B.

2006-01-01

Undesired impurities can be removed away from multicrystalline silicon (mc-Si) wafers by combining porous silicon (PS) formation and heat treatments. The gettering procedure used in this work is based on the formation of a PS film at both back and front sides of the mc-Si wafers, followed by a heat treatment. The latter was achieved in an infrared furnace at different temperatures and during various periods. We show that when the based material undergoes such a gettering, the electrical properties (short-circuit current, open-circuit voltage, serial and shunt resistances) and the electronic parameters (diffusion length and grain boundary recombination velocity) of the corresponding solar cells can be improved only if some regions of the wafers are etched. Compared to reference cells based on untreated wafers, the diffusion length and grain boundary recombination velocity of solar cells fabricated from gettered and etched samples was improved by about 30% and reduced by a factor of 10, respectively

Reducing the porosity and reflection loss of silicon nanowires by a sticky tape

International Nuclear Information System (INIS)

Liu, Junjun; Huang, Zhifeng

2015-01-01

Engineering the porosity of silicon nanowires (SiNWs) is of fundamental importance, and this work introduces a new method for doing so. Metal-assisted chemical etching (MACE) of heavily doped Si(100) creates mesoporous silicon nanowires (mp-SiNWs). mp-SiNWs are transferred from the MACE-treated wafer to a sticky tape, leaving residues composed of broken mp-SiNWs and a mesoporous Si layer on the wafer. Then the taped wafer is re-treated by MACE, without changing the etching conditions. The second MACE treatment generates mp-SiNWs that are less porous and longer than those generated by the first MACE treatment, which can be attributed to the difference in the surface topography at the beginning of the etching process. Less porous mp-SiNWs reduce optical scattering from the porous Si skeletons, and vertically protrude on the wafer without aggregation to facilitate optical trapping. Consequently, less porous mp-SiNWs effectively reduce ultraviolet-visible reflection loss. (paper)

Particle precipitation in connection with KOH etching of silicon

DEFF Research Database (Denmark)

Nielsen, Christian Bergenstof; Christensen, Carsten; Pedersen, Casper

2004-01-01

This paper considers the precipitation of iron oxide particles in connection with the KOH etching of cavities in silicon wafers. The findings presented in this paper suggest that the source to the particles is the KOH pellets used for making the etching solution. Experiments show that the precipi......This paper considers the precipitation of iron oxide particles in connection with the KOH etching of cavities in silicon wafers. The findings presented in this paper suggest that the source to the particles is the KOH pellets used for making the etching solution. Experiments show...... that the precipitation is independent of KOH etching time, but that the amount of deposited material varies with dopant type and dopant concentration. The experiments also suggest that the precipitation occurs when the silicon wafers are removed from the KOH etching solution and not during the etching procedure. When...... not removed, the iron oxide particles cause etch pits on the Si surface when later processed and exposed to phosphoric acid. It has been found that the particles can be removed in an HCl solution, but not completely in an H2SO4- H2O2 solution. The paper discusses the involved precipitation mechanism in terms...

Beam delivery system with a non-digitized diffractive beam splitter for laser-drilling of silicon

Science.gov (United States)

Amako, J.; Fujii, E.

2016-02-01

We report a beam-delivery system consisting of a non-digitized diffractive beam splitter and a Fourier transform lens. The system is applied to the deep-drilling of silicon using a nanosecond pulse laser in the manufacture of inkjet printer heads. In this process, a circularly polarized pulse beam is divided into an array of uniform beams, which are then delivered precisely to the process points. To meet these requirements, the splitter was designed to be polarization-independent with an efficiency>95%. The optical elements were assembled so as to allow the fine tuning of the effective overall focal length by adjusting the wavefront curvature of the beam. Using the system, a beam alignment accuracy ofbeam array and the throughput was substantially improved (10,000 points on a silicon wafer drilled in ~1 min). This beam-delivery scheme works for a variety of laser applications that require parallel processing.

Optical and passivating properties of hydrogenated amorphous silicon nitride deposited by plasma enhanced chemical vapour deposition for application on silicon solar cells

Energy Technology Data Exchange (ETDEWEB)

Wight, Daniel Nilsen

2008-07-01

Within this thesis, several important subjects related to the use of amorphous silicon nitride made by plasma enhanced chemical vapour deposition as an anti-reflective coating on silicon solar cells are presented. The first part of the thesis covers optical simulations to optimise single and double layer anti-reflective coatings with respect to optical performance when situated on a silicon solar cell. The second part investigates the relationship between important physical properties of silicon nitride films when deposited under different conditions. The optical simulations were either based on minimising the reflectance off a silicon nitride/silicon wafer stack or maximising the transmittance through the silicon nitride into the silicon wafer. The former method allowed consideration of the reflectance off the back surface of the wafer, which occurs typically at wavelengths above 1000 nm due to the transparency of silicon at these wavelengths. However, this method does not take into consideration the absorption occurring in the silicon nitride, which is negligible at low refractive indexes but quite significant when the refractive index increases above 2.1. For high-index silicon nitride films, the latter method is more accurate as it considers both reflectance and absorbance in the film to calculate the transmittance into the Si wafer. Both methods reach similar values for film thickness and refractive index for optimised single layer anti-reflective coatings, due to the negligible absorption occurring in these films. For double layer coatings, though, the reflectance based simulations overestimated the optimum refractive index for the bottom layer, which would have lead to excessive absorption if applied to real anti-reflective coatings. The experimental study on physical properties for silicon nitride films deposited under varying conditions concentrated on the estimation of properties important for its applications, such as optical properties, passivation

Review of the Potential of the Ni/Cu Plating Technique for Crystalline Silicon Solar Cells

Directory of Open Access Journals (Sweden)

Atteq ur Rehman

2014-02-01

Full Text Available Developing a better method for the metallization of silicon solar cells is integral part of realizing superior efficiency. Currently, contact realization using screen printing is the leading technology in the silicon based photovoltaic industry, as it is simple and fast. However, the problem with metallization of this kind is that it has a lower aspect ratio and higher contact resistance, which limits solar cell efficiency. The mounting cost of silver pastes and decreasing silicon wafer thicknesses encourages silicon solar cell manufacturers to develop fresh metallization techniques involving a lower quantity of silver usage and not relying pressing process of screen printing. In recent times nickel/copper (Ni/Cu based metal plating has emerged as a metallization method that may solve these issues. This paper offers a detailed review and understanding of a Ni/Cu based plating technique for silicon solar cells. The formation of a Ni seed layer by adopting various deposition techniques and a Cu conducting layer using a light induced plating (LIP process are appraised. Unlike screen-printed metallization, a step involving patterning is crucial for opening the masking layer. Consequently, experimental procedures involving patterning methods are also explicated. Lastly, the issues of adhesion, back ground plating, process complexity and reliability for industrial applications are also addressed.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

International Nuclear Information System (INIS)

Holland, S.E.

2000-01-01

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels

Optimization of Controllable Factors in the Aluminum Silicon Eutectic Paste and Rear Silicon Nitride Mono-Passivation Layer of PERC Solar Cells

Science.gov (United States)

Park, Sungeun; Park, Hyomin; Kim, Dongseop; Yang, JungYup; Lee, Dongho; Kim, Young-Su; Kim, Hyun-Jong; Suh, Dongchul; Min, Byoung Koun; Kim, Kyung Nam; Park, Se Jin; Kim, Donghwan; Lee, Hae-Seok; Nam, Junggyu; Kang, Yoonmook

2018-05-01

Passivated emitter and rear contact (PERC) is a promising technology owing to high efficiency can be achieved with p-type wafer and their easily applicable to existing lines. In case of using p-type mono wafer, 0.5-1% efficiency increase is expected with PERC technologies compared to existing Al BSF solar cells, while for multi-wafer solar cells it is 0.5-0.8%. We addressed the optimization of PERC solar cells using the Al paste. The paste was prepared from the aluminum-silicon alloy with eutectic composition to avoid the formation of voids that degrade the open-circuit voltage. The glass frit of the paste was changed to improve adhesion. Scanning electron microscopy revealed voids and local back surface field between the aluminum electrode and silicon base. We confirmed the conditions on the SiNx passivation layer for achieving higher efficiency and better adhesion for long-term stability. The cell characteristics were compared across cells containing different pastes. PERC solar cells with the Al/Si eutectic paste exhibited the efficiency of 19.6%.

Optimization of the Surface Structure on Black Silicon for Surface Passivation.

Science.gov (United States)

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-12-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al 2 O 3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH 4 OH/H 2 O 2 /H 2 O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Improvement of silicon direct bonding using surfaces activated by hydrogen plasma treatment

CERN Document Server

Choi, W B; Lee Jae Sik; Sung, M Y

2000-01-01

The plasma surface treatment, using hydrogen gas, of silicon wafers was studied as a pretreatment for silicon direct bonding. Chemical reactions of the hydrogen plasma with the surfaces were used for both surface activation and removal of surface contaminants. Exposure of the silicon wafers to the plasma formed an active oxide layer on the surface. This layer was hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposure time and power. The surface became smoother with shorter plasma exposure time and lower power. In addition, the plasma surface treatment was very efficient in removing the carbon contaminants on the silicon surface. The value of the initial surface energy, as estimated by using the crack propagation method, was 506 mJ/M sup 2 , which was up to about three times higher than the value for the conventional direct bonding method using wet chemical treatments.

Additive Manufacturing of Silicon Carbide-Based Ceramic Matrix Composites: Technical Challenges and Opportunities

Science.gov (United States)

Singh, Mrityunjay; Halbig, Michael C.; Grady, Joseph E.

2016-01-01

Advanced SiC-based ceramic matrix composites offer significant contributions toward reducing fuel burn and emissions by enabling high overall pressure ratio (OPR) of gas turbine engines and reducing or eliminating cooling air in the hot-section components, such as shrouds, combustor liners, vanes, and blades. Additive manufacturing (AM), which allows high value, custom designed parts layer by layer, has been demonstrated for metals and polymer matrix composites. However, there has been limited activity on additive manufacturing of ceramic matrix composites (CMCs). In this presentation, laminated object manufacturing (LOM), binder jet process, and 3-D printing approaches for developing ceramic composite materials are presented. For the laminated object manufacturing (LOM), fiber prepreg laminates were cut into shape with a laser and stacked to form the desired part followed by high temperature heat treatments. For the binder jet, processing optimization was pursued through silicon carbide powder blending, infiltration with and without SiC nano powder loading, and integration of fibers into the powder bed. Scanning electron microscopy was conducted along with XRD, TGA, and mechanical testing. Various technical challenges and opportunities for additive manufacturing of ceramics and CMCs will be presented.

Production of Solar Grade (SoG) Silicon by Refining Liquid Metallurgical Grade (MG) Silicon: Final Report, 19 April 2001; FINAL

International Nuclear Information System (INIS)

Khattack, C. P.; Joyce, D. B.; Schmid, F.

2001-01-01

This report summarizes the results of the developed technology for producing SoG silicon by upgrading MG silicon with a cost goal of$20/kg in large-scale production. A Heat Exchanger Method (HEM) furnace originally designed to produce multicrystalline ingots was modified to refine molten MG silicon feedstock prior to directional solidification. Based on theoretical calculations, simple processing techniques, such as gas blowing through the melt, reaction with moisture, and slagging have been used to remove B from molten MG silicon. The charge size was scaled up from 1 kg to 300 kg in incremental steps and effective refining was achieved. After the refining parameters were established, improvements to increase the impurity reduction rates were emphasized. With this approach, 50 kg of commercially available as-received MG silicon was processed for a refining time of about 13 hours. A half life of and lt;2 hours was achieved, and the B concentration was reduced to 0.3 ppma and P concentration to 10 ppma from the original values of 20 to 60 ppma, and all other impurities to and lt;0.1 ppma. Achieving and lt;1 ppma B by this simple refining technique is a breakthrough towards the goal of achieving low-cost SoG silicon for PV applications. While the P reduction process was being optimized, the successful B reduction process was applied to a category of electronics industry silicon scrap previously unacceptable for PV feedstock use because of its high B content (50-400 ppma). This material after refining showed that its B content was reduced by several orders of magnitude, to(approx)1 ppma (0.4 ohm-cm, or about 5x1016 cm-3). NREL's Silicon Materials Research team grew and wafered small and lt;100 and gt; dislocation-free Czochralski (Cz) crystals from the new feedstock material for diagnostic tests of electrical properties, C and O impurity levels, and PV performance relative to similar crystals grown from EG feedstock and commercial Cz wafers. The PV conversion

Silicon-micromachined microchannel plates

CERN Document Server

Beetz, C P; Steinbeck, J; Lemieux, B; Winn, D R

2000-01-01

Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of approx 0.5 to approx 25 mu m, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposite...

Organization of silicon nanocrystals by localized electrochemical etching

International Nuclear Information System (INIS)

Ayari-Kanoun, Asma; Drouin, Dominique; Beauvais, Jacques; Lysenko, Vladimir; Nychyporuk, Tetyana; Souifi, Abdelkader

2009-01-01

An approach to form a monolayer of organized silicon nanocrystals on a monocrystalline Si wafer is reported. Ordered arrays of nanoholes in a silicon nitride layer were obtained by combining electron beam lithography and plasma etching. Then, a short electrochemical etching current pulse led to formation of a single Si nanocrystal per each nanohole. As a result, high quality silicon nanocrystal arrays were formed with well controlled and reproducible morphologies. In future, this approach can be used to fabricate single electron devices.

Porous silicon carbide (SIC) semiconductor device

Science.gov (United States)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Homogeneity Analysis of a MEMS-based PZT Thick Film Vibration Energy Harvester Manufacturing Process

DEFF Research Database (Denmark)

Lei, Anders; Xu, Ruichao; Borregaard, Louise M.

2012-01-01

This paper presents a homogeneity analysis of a high yield wafer scale fabrication of MEMS-based unimorph silicon/PZT thick film vibration energy harvesters aimed towards vibration sources with peak vibrations in the range of around 300Hz. A wafer with a yield of 91% (41/45 devices) has been...

Temperature-dependent interface characteristic of silicon wafer bonding based on an amorphous germanium layer deposited by DC-magnetron sputtering

Science.gov (United States)

Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

2018-03-01

We report a near-bubble-free low-temperature silicon (Si) wafer bonding with a thin amorphous Ge (a-Ge) intermediate layer. The DC-magnetron-sputtered a-Ge film on Si is demonstrated to be extremely flat (RMS = 0.28 nm) and hydrophilic (contact angle = 3°). The effect of the post-annealing temperature on the surface morphology and crystallinity of a-Ge film at the bonded interface is systematically identified. The relationship among the bubble density, annealing temperature, and crystallinity of a-Ge film is also clearly clarified. The crystallization of a-Ge film firstly appears at the bubble region. More interesting feature is that the crystallization starts from the center of the bubbles and sprawls to the bubble edge gradually. The H2 by-product is finally absorbed by intermediate Ge layer with crystalline phase after post annealing. Moreover, the whole a-Ge film out of the bubble totally crystallizes when the annealing time increases. This Ge integration at the bubble region leads to the decrease of the bubble density, which in turn increases the bonding strength.

Silicon photonics: some remaining challenges

Science.gov (United States)

Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

2016-03-01

This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

Laser direct writing of oxide structures on hydrogen-passivated silicon surfaces

DEFF Research Database (Denmark)

Müllenborn, Matthias; Birkelund, Karen; Grey, Francois

1996-01-01

on amorphous and crystalline silicon surfaces in order to determine the depassivation mechanism. The minimum linewidth achieved is about 450 nm using writing speeds of up to 100 mm/s. The process is fully compatible with local oxidation of silicon by scanning probe lithography. Wafer-scale patterns can...

Fabrication of micromirrors with pyramidal shape using anisotropic etching of silicon

OpenAIRE

Moktadir, Z.; Vijaya Prakash, G.; Trupke, M.; Koukharenko, E.; Kraft, M.; Baumberg, J.J.; Eriksson, S.; Hinds, E.A.

2005-01-01

Gold micro-mirrors have been formed in silicon in an inverted pyramidal shape. The pyramidal structures are created in the (100) surface of a silicon wafer by anisotropic etching in potassium hydroxide. High quality micro-mirrors are then formed by sputtering gold onto the smooth silicon (111) faces of the pyramids. These mirrors show great promise as high quality optical devices suitable for integration into MOEMS systems.

Superconducting Super Collider silicon tracking subsystem research and development

International Nuclear Information System (INIS)

Miller, W.O.; Thompson, T.C.; Ziock, H.J.; Gamble, M.T.

1990-12-01

The Alamos National Laboratory Mechanical Engineering and Electronics Division has been investigating silicon-based elementary particle tracking device technology as part of the Superconducting Super Collider-sponsored silicon subsystem collaboration. Structural, materials, and thermal issues have been addressed. This paper explores detector structural integrity and stability, including detailed finite element models of the silicon wafer support and predictive methods used in designing with advanced composite materials. The current design comprises a magnesium metal matrix composite (MMC) truss space frame to provide a sparse support structure for the complex array of silicon detectors. This design satisfies the 25-μm structural stability requirement in a 10-Mrad radiation environment. This stability is achieved without exceeding the stringent particle interaction constraints set at 2.5% of a radiation length. Materials studies have considered thermal expansion, elastic modulus, resistance to radiation and chemicals, and manufacturability of numerous candidate materials. Based on optimization of these parameters, the MMC space frame will possess a coefficient of thermal expansion (CTE) near zero to avoid thermally induced distortions, whereas the cooling rings, which support the silicon detectors and heat pipe network, will probably be constructed of a graphite/epoxy composite whose CTE is engineered to match that of silicon. Results from radiation, chemical, and static loading tests are compared with analytical predictions and discussed. Electronic thermal loading and its efficient dissipation using heat pipe cooling technology are discussed. Calculations and preliminary designs for a sprayed-on graphite wick structure are presented. A hydrocarbon such as butane appears to be a superior choice of heat pipe working fluid based on cooling, handling, and safety criteria

Single crystalline silicon solar cells with rib structure

Directory of Open Access Journals (Sweden)

Shuhei Yoshiba

2017-02-01

Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

Microscratch testing method for systematic evaluation of the adhesion of atomic layer deposited thin films on silicon

Energy Technology Data Exchange (ETDEWEB)

Kilpi, Lauri, E-mail: Lauri.Kilpi@vtt.fi; Ylivaara, Oili M. E.; Vaajoki, Antti; Puurunen, Riikka L.; Ronkainen, Helena [VTT Technical Research Centre of Finland Ltd., P.O. Box 1000, FI-02044 VTT (Finland); Malm, Jari [Department of Physics, University of Jyväskylä, P.O. Box 35, Jyväskylä 40014 (Finland); Sintonen, Sakari [Department of Micro- and Nanosciences, Aalto University School of Electrical Engineering, P.O. Box 13500, FI-00076 AALTO (Finland); Tuominen, Marko [ASM Microchemistry Oy, Pietari Kalmin katu 1 F 2, FIN-00560 Helsinki (Finland)

2016-01-15

The scratch test method is widely used for adhesion evaluation of thin films and coatings. Usual critical load criteria designed for scratch testing of coatings were not applicable to thin atomic layer deposition (ALD) films on silicon wafers. Thus, the bases for critical load evaluation were established and the critical loads suitable for ALD coating adhesion evaluation on silicon wafers were determined in this paper as L{sub CSi1}, L{sub CSi2}, L{sub CALD1}, and L{sub CALD2}, representing the failure points of the silicon substrate and the coating delamination points of the ALD coating. The adhesion performance of the ALD Al{sub 2}O{sub 3}, TiO{sub 2}, TiN, and TaCN+Ru coatings with a thickness range between 20 and 600 nm and deposition temperature between 30 and 410 °C on silicon wafers was investigated. In addition, the impact of the annealing process after deposition on adhesion was evaluated for selected cases. The tests carried out using scratch and Scotch tape test showed that the coating deposition and annealing temperature, thickness of the coating, and surface pretreatments of the Si wafer had an impact on the adhesion performance of the ALD coatings on the silicon wafer. There was also an improved load carrying capacity due to Al{sub 2}O{sub 3}, the magnitude of which depended on the coating thickness and the deposition temperature. The tape tests were carried out for selected coatings as a comparison. The results show that the scratch test is a useful and applicable tool for adhesion evaluation of ALD coatings, even when carried out for thin (20 nm thick) coatings.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

Science.gov (United States)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-03-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Atomic and electronic structures of novel silicon surface structures

Energy Technology Data Exchange (ETDEWEB)

Terry, J.H. Jr.

1997-03-01

The modification of silicon surfaces is presently of great interest to the semiconductor device community. Three distinct areas are the subject of inquiry: first, modification of the silicon electronic structure; second, passivation of the silicon surface; and third, functionalization of the silicon surface. It is believed that surface modification of these types will lead to useful electronic devices by pairing these modified surfaces with traditional silicon device technology. Therefore, silicon wafers with modified electronic structure (light-emitting porous silicon), passivated surfaces (H-Si(111), Cl-Si(111), Alkyl-Si(111)), and functionalized surfaces (Alkyl-Si(111)) have been studied in order to determine the fundamental properties of surface geometry and electronic structure using synchrotron radiation-based techniques.

Material synthesis for silicon integrated-circuit applications using ion implantation

Science.gov (United States)

Lu, Xiang

of microscopic images. The underlying hydrogen profiles for between 250sp°C and 500sp°C annealing are characterized by SIMS and HFS experiments. An ideal gas law model calculation suggests that the internal pressure of molecular hydrogen filled microcavities is in the range of Giga-Pascal, high enough to break the silicon crystal bond. A dose threshold which prevents cleavage is observed at 1.6× 10sp{17} cmsp{-2} for 40 kV hydrogen implantation. A initial defect, in a silicon substrate, induced by a hydrogen microcavity is modeled as a circular crack which is embedded at a certain depth from the top silicon surface. A two-dimensional finite element model is made to calculate energy release rate along the crack surfaces. This numerical model predicts that the energy release rate is sufficient to overcome the silicon fracture toughness. The model further identifies the factors that can enhance the energy release rate. Ion-Cut SOI wafer fabrication technique is implemented using Pm. The hydrogen implantation rate, which is independent of the wafer size, is considerably higher than that of conventional implantation. The simple Pm reactor setup and its compatibility with cluster-tool IC manufacturing system offer other Ion-Cut process optimization opportunities. The feasibility of Pm Ion-Cut process has been demonstrated with successful fabrication of SOI structures. The hydrogen plasma can be optimized so that only one ion species is dominant in concentration, with minimal effect on the Ion-Cut process by the residual ion components. We have also demonstrated the feasibility of performing Ion-Cut using Pm in helium plasma.

Big data driven cycle time parallel prediction for production planning in wafer manufacturing

Science.gov (United States)

Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

2018-07-01

Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

TEM investigation of aluminium containing precipitates in high aluminium doped silicon carbide

International Nuclear Information System (INIS)

Wong-Leung, J.; FitzGerald, J.D.

2002-01-01

Full text: Silicon carbide is a promising semiconductor material for applications in high temperature and high power devices. The successful growth of good quality epilayers in this material has enhanced its potential for device applications. As a novel semiconductor material, there is a need for studying its basic physical properties and the role of dopants in this material. In this study, silicon carbide epilayers were grown on 4H-SiC wafers of (0001) orientation with a miscut angle of 8 deg at a temperature of 1550 deg C. The epilayers contained regions of high aluminium doping well above the solubility of aluminium in silicon carbide. High temperature annealing of this material resulted in the precipitation of aluminium in the wafers. The samples were analysed by secondary ion mass spectrometry and transmission electron microscopy. Selected area diffraction studies show the presence of aluminium carbide and aluminium silicon carbide phases. Copyright (2002) Australian Society for Electron Microscopy Inc

Hard times; Schwere Zeiten

Energy Technology Data Exchange (ETDEWEB)

Grunwald, Markus

2012-10-02

The prices of silicon and solar wafers keep dropping. According to market research specialist IMS research, this is the result of weak traditional solar markets and global overcapacities. While many manufacturers are facing hard times, big producers of silicon are continuing to expand.

Thin Single Crystal Silicon Solar Cells on Ceramic Substrates: November 2009 - November 2010

Energy Technology Data Exchange (ETDEWEB)

Kumar, A.; Ravi, K. V.

2011-06-01

In this program we have been developing a technology for fabricating thin (< 50 micrometres) single crystal silicon wafers on foreign substrates. We reverse the conventional approach of depositing or forming silicon on foreign substrates by depositing or forming thick (200 to 400 micrometres) ceramic materials on high quality single crystal silicon films ~ 50 micrometres thick. Our key innovation is the fabrication of thin, refractory, and self-adhering 'handling layers or substrates' on thin epitaxial silicon films in-situ, from powder precursors obtained from low cost raw materials. This 'handling layer' has sufficient strength for device and module processing and fabrication. Successful production of full sized (125 mm X 125 mm) silicon on ceramic wafers with 50 micrometre thick single crystal silicon has been achieved and device process flow developed for solar cell fabrication. Impurity transfer from the ceramic to the silicon during the elevated temperature consolidation process has resulted in very low minority carrier lifetimes and resulting low cell efficiencies. Detailed analysis of minority carrier lifetime, metals analysis and device characterization have been done. A full sized solar cell efficiency of 8% has been demonstrated.

11th Workshop on Crystalline Silicon Solar Cell Materials and Processes, Extended Abstracts and Papers, 19-22 August 2001, Estes Park, Colorado

Energy Technology Data Exchange (ETDEWEB)

Sopori, B.

2001-08-16

The 11th Workshop will provide a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and non-photovoltaic fields. Discussions will include the various aspects of impurities and defects in silicon--their properties, the dynamics during device processing, and their application for developing low-cost processes for manufacturing high-efficiency silicon solar cells. Sessions and panel discussions will review impurities and defects in crystalline-silicon PV, advanced cell structures, new processes and process characterization techniques, and future manufacturing demands. The workshop will emphasize some of the promising new technologies in Si solar cell fabrication that can lower PV energy costs and meet the throughput demands of the future. The three-day workshop will consist of presentations by invited speakers, followed by discussion sessions. Topics to be discussed are: Si Mechanical properties and Wafer Handling, Advanced Topics in PV Fundamentals, Gettering and Passivation, Impurities and Defects, Advanced Emitters, Crystalline Silicon Growth, and Solar Cell Processing. The workshop will also include presentations by NREL subcontractors who will review the highlights of their research during the current subcontract period. In addition, there will be two poster sessions presenting the latest research and development results. Some presentations will address recent technologies in the microelectronics field that may have a direct bearing on PV.

Damage-free polishing of monocrystalline silicon wafers without chemical additives

International Nuclear Information System (INIS)

Biddut, A.Q.; Zhang, L.C.; Ali, Y.M.; Liu, Z.

2008-01-01

This investigation explores the possibility and identifies the mechanism of damage-free polishing of monocrystalline silicon without chemical additives. Using high resolution electron microscopy and contact mechanics, the study concludes that a damage-free polishing process without chemicals is feasible. All forms of damages, such as amorphous Si, dislocations and plane shifting, can be eliminated by avoiding the initiation of the β-tin phase of silicon during polishing. When using 50 nm abrasives, the nominal pressure to achieve damage-free polishing is 20 kPa

Worker exposure to methanol vapors during cleaning of semiconductor wafers in a manufacturing setting.

Science.gov (United States)

Gaffney, Shannon; Moody, Emily; McKinley, Meg; Knutsen, Jeffrey; Madl, Amy; Paustenbach, Dennis

2008-05-01

An exposure simulation was conducted to characterize methanol exposure of workers who cleaned wafers in quality control departments within the semiconductor industry. Short-term (15 min) and long-term (2-4 hr) personal and area samples (at distances of 1 m and 3-6 m from the source) were collected during the 2-day simulation. On the first day, 45 mL of methanol were used per hour by a single worker washing wafers in a 102 m(3) room with a ventilation rate of about 10 air changes per hour (ACH). Virtually all methanol volatilized. To assess exposures under conditions associated with higher productivity, on the second day, two workers cleaned wafers simultaneously, together using methanol at over twice the rate of the first day (95 mL/hr). On this day, the ventilation rate was halved (5 ACH). Personal concentrations on the first day averaged 60 ppm (SD = 46 ppm) and ranged from 10-140 ppm. On the second day, personal concentrations for both workers averaged 118 ppm (SD = 50 ppm; range: 64-270 ppm). Area concentrations measured on the first day at 1 m from the source and throughout the balance of the room averaged 29 ppm (SD = 19 ppm; range: 4-83 ppm) and 18 ppm (SD = 12 ppm; range: 3-42 ppm), respectively. As expected, area concentrations measured on the second day were higher than the first and averaged 73 ppm (SD = 25 ppm; range: 27-140 ppm) at 1 meter and 48 ppm (SD = 13 ppm; range: 21-67 ppm) throughout the balance of the room. The results of this simulation suggest that the use of methanol to clean semiconductor wafers without the use of local exhaust ventilation and with relatively low room ventilation rates is unlikely to result in worker exposures exceeding the current ACGIH(R) threshold limit value of 200 ppm. This study also confirmed prior studies suggesting that when a relatively volatile chemical is located within arm's length (near field), breathing zone concentrations will be about two- to threefold greater than the room concentration when the air

Alternative method for steam generation for thermal oxidation of silicon

Science.gov (United States)

Spiegelman, Jeffrey J.