WorldWideScience

Sample records for silicon wafer bonding

  1. Silicon waveguides produced by wafer bonding

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  2. Sol-gel bonding of silicon wafers

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  3. Sol-gel bonding of silicon wafers

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  4. Silicon-to-silicon wafer bonding using evaporated glass

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  5. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  6. Cohesive zone model for direct silicon wafer bonding

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  7. Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

    Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

    2003-01-01

    Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

  8. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  9. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  10. Eutectic and solid-state wafer bonding of silicon with gold

    Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

    2012-01-01

    Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  11. Wafer bonding applications and technology

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  12. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  13. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

    2010-01-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  14. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  15. Handbook of wafer bonding

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  16. Fabrication of an integrated ΔE-E-silicon detector by wafer bonding using cobalt disilicide

    Thungstroem, G.; Veldhuizen, E.J. van; Westerberg, L.; Norlin, L.-O.; Petersson, C.S.

    1997-01-01

    The problem concerning mechanical stability of thin self-supporting ΔE detector in a ΔE-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The ΔE-detector has a thickness of 6.5 μm and the E detector 290 μm with an area of 24.8 mm 2 . The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.)

  17. Fabrication of an integrated {Delta}E-E-silicon detector by wafer bonding using cobalt disilicide

    Thungstroem, G. [Mid-Sweden Univ., Sundsvall (Sweden). Dept. of Inf. Technol.]|[Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden); Veldhuizen, E.J. van [Uppsala University, Department of Radiation Science, Box 535, S-751 21 Uppsala (Sweden); Westerberg, L. [Uppsala University, The Svedberg Laboratory, Box 533, S-751 21 Uppsala (Sweden); Norlin, L.-O. [Royal Institute of Technology, Department of Physics, Frescativaegen 24, S-104 05 Stockholm (Sweden); Petersson, C.S. [Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden)

    1997-06-01

    The problem concerning mechanical stability of thin self-supporting {Delta}E detector in a {Delta}E-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The {Delta}E-detector has a thickness of 6.5 {mu}m and the E detector 290 {mu}m with an area of 24.8 mm{sup 2}. The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.).

  18. Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

    2013-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

  19. Laser wafering for silicon solar

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  20. Laser wafering for silicon solar.

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  1. Nature of bonding forces between two hydrogen-passivated silicon wafers

    Stokbro, Kurt; Nielsen, E.; Hult, E.

    1998-01-01

    The nature and strength of the bonding forces between two II-passivated Si surfaces are studied with the density-functional theory, using an approach based on recent theoretical advances in understanding of van der Waals forces between two surfaces. Contrary to previous suggestions of van der Waals...

  2. Industrial Silicon Wafer Solar Cells

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  3. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  4. Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

    Egelkrout, D. W.

    1981-01-01

    Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

  5. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  6. Characterization of silicon-on-insulator wafers

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  7. Silicon wafers for integrated circuit process

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  8. Sacrificial wafer bonding for planarization after very deep etching

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  9. Industrial Silicon Wafer Solar Cells

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  10. Temperature-dependent interface characteristic of silicon wafer bonding based on an amorphous germanium layer deposited by DC-magnetron sputtering

    Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

    2018-03-01

    We report a near-bubble-free low-temperature silicon (Si) wafer bonding with a thin amorphous Ge (a-Ge) intermediate layer. The DC-magnetron-sputtered a-Ge film on Si is demonstrated to be extremely flat (RMS = 0.28 nm) and hydrophilic (contact angle = 3°). The effect of the post-annealing temperature on the surface morphology and crystallinity of a-Ge film at the bonded interface is systematically identified. The relationship among the bubble density, annealing temperature, and crystallinity of a-Ge film is also clearly clarified. The crystallization of a-Ge film firstly appears at the bubble region. More interesting feature is that the crystallization starts from the center of the bubbles and sprawls to the bubble edge gradually. The H2 by-product is finally absorbed by intermediate Ge layer with crystalline phase after post annealing. Moreover, the whole a-Ge film out of the bubble totally crystallizes when the annealing time increases. This Ge integration at the bubble region leads to the decrease of the bubble density, which in turn increases the bonding strength.

  11. Physical mechanisms of Cu-Cu wafer bonding

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  12. Lamb wave propagation in monocrystalline silicon wafers

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  13. Voltage-assisted polymer wafer bonding

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  14. Science and technology of plasma activated direct wafer bonding

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  15. Mechanics of wafer bonding: Effect of clamping

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  16. Making Porous Luminescent Regions In Silicon Wafers

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  17. Low-temperature Au/a-Si wafer bonding

    Jing, Errong; Xiong, Bin; Wang, Yuelin

    2011-01-01

    The Si/SiO 2 /Ti/Au–Au/Ti/a-Si/SiO 2 /Si bonding structure, which can also be used for the bonding of non-silicon material, was investigated for the first time in this paper. The bond quality test showed that the bond yield, bond repeatability and average shear strength are higher for this bonding structure. The interfacial microstructure analysis indicated that the Au-induced crystallization of the amorphous silicon process leads to big Si grains extending across the bond interface and Au filling the other regions of the bond interface, which result into a strong and void-free bond interface. In addition, the Au-induced crystallization reaction leads to a change in the IR images of the bond interface. Therefore, the IR microscope can be used to evaluate and compare the different bond strengths qualitatively. Furthermore, in order to verify the superiority of the bonding structure, the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si (i.e. no Ti/Au layer on the a-Si surface) and Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structures (i.e. Au thermocompression bonding) were also investigated. For the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si bonding structure, the poor bond quality is due to the native oxide layer on the a-Si surface, and for the Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structure, the poor bond quality is caused by the wafer surface roughness which prevents intimate contact and limits the interdiffusion at the bond interface.

  18. Surface etching technologies for monocrystalline silicon wafer solar cells

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  19. Low-cost silicon wafer dicing using a craft cutter

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  20. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  1. Lamb wave propagation in monocrystalline silicon wafers.

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  2. Chemical polishing of epitoxial silicon wafer

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  3. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  4. Si-to-Si wafer bonding using evaporated glass

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  5. Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

    Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

    2017-10-01

    Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

  6. High frequency guided wave propagation in monocrystalline silicon wafers

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  7. Impact of SiO2 on Al–Al thermocompression wafer bonding

    Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

    2015-01-01

    Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

  8. Low temperature sacrificial wafer bonding for planarization after very deep etching

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  9. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  10. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  11. Low-cost silicon wafer dicing using a craft cutter

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  12. Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

    Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

    2017-06-01

    In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

  13. Guided ultrasonic wave beam skew in silicon wafers

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  14. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  15. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  16. Preparation and characterisation of immobilised humic acid on silicon wafer

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  17. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  18. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  19. Fusion bonding of Si wafers investigated by x ray diffraction

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

  20. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  1. Physical mechanisms of copper-copper wafer bonding

    Rebhan, B.; Hingerl, K.

    2015-01-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing

  2. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    Xianshu eLuo

    2015-04-01

    Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

  3. GeSn-on-insulator substrate formed by direct wafer bonding

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  4. I-line stepper based overlay evaluation method for wafer bonding applications

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  5. High frequency guided wave propagation in monocrystalline silicon wafers

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  6. Simplified nonplanar wafer bonding for heterogeneous device integration

    Geske, Jon; Bowers, John E.; Riley, Anton

    2004-07-01

    We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

  7. Automotive SOI-BCD Technology Using Bonded Wafers

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  8. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  9. Denuded zone in Czochralski silicon wafer with high carbon content

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  10. Denuded zone in Czochralski silicon wafer with high carbon content

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  11. Peptide and protein loading into porous silicon wafers

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  12. Contacting graphene in a 200 mm wafer silicon technology environment

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  13. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  14. Residual stress in silicon wafer using IR polariscope

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  15. Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding

    Xiaoqing Wang

    2016-12-01

    Full Text Available This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs by wafer direct bonding, which utilizes both the wet chemical and O2plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC substrates.

  16. Tests of a silicon wafer based neutron collimator

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  17. Tests of a silicon wafer based neutron collimator

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  18. Coherent spin transport through a 350 micron thick silicon wafer.

    Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

    2007-10-26

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  19. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  20. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators.

    Mizumoto, Tetsuya; Shoji, Yuya; Takei, Ryohei

    2012-05-24

    This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO₃. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI) waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  1. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators

    Ryohei Takei

    2012-05-01

    Full Text Available This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO3. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  2. Reaction-bonded silicon nitride

    Porz, F.

    1982-10-01

    Reaction-bonded silicon nitride (RBSN) has been characterized. The oxidation behaviour in air up to 1500 0 C and 3000 h and the effects of static and cyclic oxidation on room-temperature strength have been studied. (orig./IHOE) [de

  3. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  4. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  5. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  6. Integrated optical MEMS using through-wafer vias and bump-bonding.

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  7. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

  8. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  9. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

  10. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

  11. Reliable four-point flexion test and model for die-to-wafer direct bonding

    Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.; Moriceau, H. [Univ. Grenoble Alpes, F-38000 Grenoble, France and CEA, LETI, MINATEC Campus, F-38054 Grenoble (France)

    2015-07-07

    For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, both D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.

  12. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    Bronuzzi, J.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

  13. Hexacoordinate bonding and aromaticity in silicon phthalocyanine.

    Yang, Yang

    2010-12-23

    Si-E bondings in hexacoordinate silicon phthalocyanine were analyzed using bond order (BO), energy partition, atoms in molecules (AIM), electron localization function (ELF), and localized orbital locator (LOL). Bond models were proposed to explain differences between hexacoordinate and tetracoordinate Si-E bondings. Aromaticity of silicon phthalocyanine was investigated using nucleus-independent chemical shift (NICS), harmonic oscillator model of aromaticity (HOMA), conceptual density functional theory (DFT), ring critical point (RCP) descriptors, and delocalization index (DI). Structure, energy, bonding, and aromaticity of tetracoordinate silicon phthalocyanine were studied and compared with hexacoordinate one.

  14. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  15. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  16. A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

    Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

    1990-01-01

    The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

  17. Fusion bonding of silicon nitride surfaces

    Reck, Kasper; Østergaard, Christian; Thomsen, Erik Vilain

    2011-01-01

    While silicon nitride surfaces are widely used in many micro electrical mechanical system devices, e.g. for chemical passivation, electrical isolation or environmental protection, studies on fusion bonding of two silicon nitride surfaces (Si3N4–Si3N4 bonding) are very few and highly application...

  18. Bonding of Si wafers by surface activation method for the development of high efficiency high counting rate radiation detectors

    Kanno, Ikuo; Yamashita, Makoto; Onabe, Hideaki

    2006-01-01

    Si wafers with two different resistivities ranging over two orders of magnitude were bonded by the surface activation method. The resistivities of bonded Si wafers were measured as a function of annealing temperature. Using calculations based on a model, the interface resistivities of bonded Si wafers were estimated as a function of the measured resistivities of bonded Si wafers. With thermal treatment from 500degC to 900degC, all interfaces showed high resistivity, with behavior that was close to that of an insulator. Annealing at 1000degC decreased the interface resistivity and showed close to ideal bonding after thermal treatment at 1100degC. (author)

  19. Development of a classical force field for the oxidized Si surface: application to hydrophilic wafer bonding.

    Cole, Daniel J; Payne, Mike C; Csányi, Gábor; Spearing, S Mark; Colombi Ciacchi, Lucio

    2007-11-28

    We have developed a classical two- and three-body interaction potential to simulate the hydroxylated, natively oxidized Si surface in contact with water solutions, based on the combination and extension of the Stillinger-Weber potential and of a potential originally developed to simulate SiO(2) polymorphs. The potential parameters are chosen to reproduce the structure, charge distribution, tensile surface stress, and interactions with single water molecules of a natively oxidized Si surface model previously obtained by means of accurate density functional theory simulations. We have applied the potential to the case of hydrophilic silicon wafer bonding at room temperature, revealing maximum room temperature work of adhesion values for natively oxidized and amorphous silica surfaces of 97 and 90 mJm(2), respectively, at a water adsorption coverage of approximately 1 ML. The difference arises from the stronger interaction of the natively oxidized surface with liquid water, resulting in a higher heat of immersion (203 vs 166 mJm(2)), and may be explained in terms of the more pronounced water structuring close to the surface in alternating layers of larger and smaller densities with respect to the liquid bulk. The computed force-displacement bonding curves may be a useful input for cohesive zone models where both the topographic details of the surfaces and the dependence of the attractive force on the initial surface separation and wetting can be taken into account.

  20. Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

    Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

    2018-01-01

    The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

  1. Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

    Kubair, D. V.; Spearing, S. M.

    2006-03-01

    Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

  2. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  3. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  4. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  5. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  6. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

    2014-01-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  7. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  8. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    N. Daix

    2014-08-01

    Full Text Available We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  9. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Daix, N., E-mail: dai@zurich.ibm.com; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J. [IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Hartmann, J. M. [CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France); Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D. [IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  10. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  11. Low temperature anodic bonding to silicon nitride

    Weichel, Steen; Reus, Roger De; Bouaidat, Salim

    2000-01-01

    Low-temperature anodic bonding to stoichiometric silicon nitride surfaces has been performed in the temperature range from 3508C to 4008C. It is shown that the bonding is improved considerably if the nitride surfaces are either oxidized or exposed to an oxygen plasma prior to the bonding. Both bu...

  12. Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

    Shisheng Cai

    2017-03-01

    Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

  13. Improvement of silicon direct bonding using surfaces activated by hydrogen plasma treatment

    Choi, W B; Lee Jae Sik; Sung, M Y

    2000-01-01

    The plasma surface treatment, using hydrogen gas, of silicon wafers was studied as a pretreatment for silicon direct bonding. Chemical reactions of the hydrogen plasma with the surfaces were used for both surface activation and removal of surface contaminants. Exposure of the silicon wafers to the plasma formed an active oxide layer on the surface. This layer was hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposure time and power. The surface became smoother with shorter plasma exposure time and lower power. In addition, the plasma surface treatment was very efficient in removing the carbon contaminants on the silicon surface. The value of the initial surface energy, as estimated by using the crack propagation method, was 506 mJ/M sup 2 , which was up to about three times higher than the value for the conventional direct bonding method using wet chemical treatments.

  14. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  15. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  16. DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

    V. A. Solodukha

    2016-01-01

    Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

  17. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  18. Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

    Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

    2018-06-01

    Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

  19. Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

    Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

    2018-05-01

    Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

  20. Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-30

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  1. Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

    Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

    2006-01-01

    The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

  2. Formation of III–V-on-insulator structures on Si by direct wafer bonding

    Yokoyama, Masafumi; Iida, Ryo; Ikku, Yuki; Kim, Sanghyeon; Takenaka, Mitsuru; Takagi, Shinichi; Takagi, Hideki; Yasuda, Tetsuji; Yamada, Hisashi; Ichikawa, Osamu; Fukuhara, Noboru; Hata, Masahiko

    2013-01-01

    We have studied the formation of III–V-compound-semiconductors-on-insulator (III–V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III–V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O 2 plasma-assisted DWB process with ECR sputtered SiO 2 BOX layers and a DWB process based on atomic-layer-deposition Al 2 O 3 (ALD-Al 2 O 3 ) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO 2 and ALD-Al 2 O 3 BOX layers are desorption of Ar and H 2 O gas, respectively. In order to suppress micro-void generation in the ECR-SiO 2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al 2 O 3 BOX layers to increase the deposition temperature of the ALD-Al 2 O 3 BOX layers. It is also another possible solution to deposit ALD-Al 2 O 3 BOX layers on thermally oxidized SiO 2 layers, which can absorb the desorption gas from ALD-Al 2 O 3 BOX layers. (invited paper)

  3. Sample pretreatment for the determination of metal impurities in silicon wafer

    Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

    1999-01-01

    The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

  4. Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

    Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

    2012-03-01

    Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

  5. Accurate characterization of wafer bond toughness with the double cantilever specimen

    Turner, Kevin T.; Spearing, S. Mark

    2008-01-01

    The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

  6. Fabrication of silicon condenser microphones using single wafer technology

    Scheeper, P.R.; van der Donk, A.G.H.; Olthuis, Wouter; Bergveld, Piet

    1992-01-01

    A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-¿m plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm2), covered with a thin

  7. Bonding silicon nitride using glass-ceramic

    Dobedoe, R.S.

    1995-01-01

    Silicon nitride has been successfully bonded to itself using magnesium-aluminosilicate glass and glass-ceramic. For some samples, bonding was achieved using a diffusion bonder, but in other instances, following an initial degassing hold, higher temperatures were used in a nitrogen atmosphere with no applied load. For diffusion bonding, a small applied pressure at a temperature below which crystallisation occurs resulted in intimate contact. At slightly higher temperatures, the extent of the reaction at the interface and the microstructure of the glass-ceramic joint was highly sensitive to the bonding temperature. Bonding in a nitrogen atmosphere resulted in a solution-reprecipitation reaction. A thin layer of glass produced a ''dry'', glass-free joint, whilst a thicker layer resulted in a continuous glassy join across the interface. The chromium silicide impurities within the silicon nitride react with the nucleating agent in the glass ceramic, which may lead to difficulty in producing a fine glass-ceramic microstructure. Slightly lower temperatures in nitrogen resulted in a polycrystalline join but the interfacial contact was poor. It is hoped that one of the bonds produced may be developed to eventually form part of a graded joint between silicon nitride and a high temperature nickel alloy. (orig.)

  8. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  9. Characterization of bulk-micromachined direct-bonded silicon nanofilters

    Tu, Jay K.; Huen, Tony; Szema, Robert; Ferrari, Mauro

    1998-03-01

    The ability to separate 30-100 nm particles - nanofiltration - is critical for many biomedical applications. Where this filtration needs to be absolute, such as for viral elimination in the blood fractionation process, the large variations in pore size found with conventional polymeric filters can lead to the unwanted presence of viruses in the filtrate. To overcome this problem, we have developed a filter with micromachined channels sandwiched between two bonded silicon wafers. These channels are formed through the selective deposition and then removal of a thermally-grown oxide, the thickness of which can be controlled to +/- 4 percent for 30 nm pores. In this paper, we will present both the gas and liquid characterization, and the filtration studies done on 44 and 100 nm beads.

  10. The Evolution of Wafer Bonding Moving from the back-end further to the front-end

    Thomas Glinsner; Peter Hangweier

    2009-01-01

    @@ 1 Introduction As the nanoscale era progresses, innovative new materials and processes continue to be developed and implemented as a means of keeping the industry on the path of Moore's Law. Wafer bonding - literally, the temporary or permanent joining of two wafers or substrates using a suitable combination of process technologies, chemicals and adhesives - is one such innovation.

  11. Micro-spectroscopy on silicon wafers and solar cells

    Gundel Paul

    2011-01-01

    Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

  12. Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

    Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

    2012-09-15

    We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

  13. External self-gettering of nickel in float zone silicon wafers

    Gay, N.; Martinuzzi, S.

    1997-05-01

    During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

  14. Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

    Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

    2018-06-01

    Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

  15. An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

    Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

    2007-01-01

    The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

  16. Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

    Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

    2018-01-01

    Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

  17. High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

    Antoniadis, H.

    2011-03-01

    Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink high efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.

  18. III-V/Si wafer bonding using transparent, conductive oxide interlayers

    Tamboli, Adele C., E-mail: Adele.Tamboli@nrel.gov; Hest, Maikel F. A. M. van; Steiner, Myles A.; Essig, Stephanie; Norman, Andrew G.; Bosco, Nick; Stradins, Paul [National Center for Photovoltaics, National Renewable Energy Laboratory, 15013 Denver West Pkwy, Golden, Colorado 80401 (United States); Perl, Emmett E. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106-9560 (United States)

    2015-06-29

    We present a method for low temperature plasma-activated direct wafer bonding of III-V materials to Si using a transparent, conductive indium zinc oxide interlayer. The transparent, conductive oxide (TCO) layer provides excellent optical transmission as well as electrical conduction, suggesting suitability for Si/III-V hybrid devices including Si-based tandem solar cells. For bonding temperatures ranging from 100 °C to 350 °C, Ohmic behavior is observed in the sample stacks, with specific contact resistivity below 1 Ω cm{sup 2} for samples bonded at 200 °C. Optical absorption measurements show minimal parasitic light absorption, which is limited by the III-V interlayers necessary for Ohmic contact formation to TCOs. These results are promising for Ga{sub 0.5}In{sub 0.5}P/Si tandem solar cells operating at 1 sun or low concentration conditions.

  19. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  20. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  1. Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

    Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

    2014-02-07

    Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

  2. The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

    Gnilenko A. B.

    2012-02-01

    Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

  3. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    Vega, M; Lasorsa, C; Lerner, B; Perez, M; Granell, P

    2016-01-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production. (paper)

  4. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  5. Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

    Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

    2005-01-01

    This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

  6. Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

    Ngo, H-D; Hiess, Andre; Seidemann, Volker; Studzinski, Daniel; Lange, Martin; Leib, Juergen; Shariff, Dzafir; Ashraf, Huma; Steel, Mike; Atabo, Lilian; Reast, Jon

    2006-01-01

    This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained and plasma configurations are described elsewhere. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters

  7. Fusion-bonded fluidic interconnects

    Fazal, I.; Elwenspoek, Michael Curt

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are

  8. Detection of trace contamination of copper on a silicon wafer with TXRF

    Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

    2000-01-01

    The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

  9. Formation of cross-cutting structures with different porosity on thick silicon wafers

    Vera A. Yuzova

    2017-06-01

    The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

  10. EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

    S. A. Chizhik

    2013-01-01

    Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

  11. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  12. Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

    Tanake, Katsuaki

    We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of

  13. Investigation of Surface Pre-Treatment Methods for Wafer-Level Cu-Cu Thermo-Compression Bonding

    Koki Tanaka

    2016-12-01

    Full Text Available To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS measurement of the H2/Ar plasma–treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.

  14. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  15. Process induced sub-surface damage in mechanically ground silicon wafers

    Yang Yu; De Munck, Koen; Teixeira, Ricardo Cotrin; Swinnen, Bart; De Wolf, Ingrid; Verlinden, Bert

    2008-01-01

    Micro-Raman spectroscopy, scanning electron microcopy, atomic force microscopy and preferential etching were used to characterize the sub-surface damage induced by the rough and fine grinding steps used to make ultra-thin silicon wafers. The roughly and ultra-finely ground silicon wafers were examined on both the machined (1 0 0) planes and the cross-sectional (1 1 0) planes. They reveal similar multi-layer damage structures, consisting of amorphous, plastically deformed and elastically stressed layers. However, the thickness of each layer in the roughly ground sample is much higher than its counterpart layers in the ultra-finely ground sample. The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30 MPa, respectively. In each case, the top amorphous layer is believed to be the result of sequential phase transformations (Si-I to Si-II to amorphous Si). These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in rough grinding, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks

  16. Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

    Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

    2005-01-01

    Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

  17. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    Bahabry, Rabab R.

    2018-01-02

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  18. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    Bahabry, Rabab R.; Kutbee, Arwa T.; Khan, Sherjeel M.; Sepulveda, Adrian C.; Wicaksono, Irmandy; Nour, Maha A.; Wehbe, Nimer; Almislem, Amani Saleh Saad; Ghoneim, Mohamed T.; Sevilla, Galo T.; Syed, Ahad; Shaikh, Sohail F.; Hussain, Muhammad Mustafa

    2018-01-01

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  19. A quality quantitative method of silicon direct bonding based on wavelet image analysis

    Tan, Xiao; Tao, Zhi; Li, Haiwang; Xu, Tiantong; Yu, Mingxing

    2018-04-01

    The rapid development of MEMS (micro-electro-mechanical systems) has received significant attention from researchers in various fields and subjects. In particular, the MEMS fabrication process is elaborate and, as such, has been the focus of extensive research inquiries. However, in MEMS fabrication, component bonding is difficult to achieve and requires a complex approach. Thus, improvements in bonding quality are relatively important objectives. A higher quality bond can only be achieved with improved measurement and testing capabilities. In particular, the traditional testing methods mainly include infrared testing, tensile testing, and strength testing, despite the fact that using these methods to measure bond quality often results in low efficiency or destructive analysis. Therefore, this paper focuses on the development of a precise, nondestructive visual testing method based on wavelet image analysis that is shown to be highly effective in practice. The process of wavelet image analysis includes wavelet image denoising, wavelet image enhancement, and contrast enhancement, and as an end result, can display an image with low background noise. In addition, because the wavelet analysis software was developed with MATLAB, it can reveal the bonding boundaries and bonding rates to precisely indicate the bond quality at all locations on the wafer. This work also presents a set of orthogonal experiments that consist of three prebonding factors, the prebonding temperature, the positive pressure value and the prebonding time, which are used to analyze the prebonding quality. This method was used to quantify the quality of silicon-to-silicon wafer bonding, yielding standard treatment quantities that could be practical for large-scale use.

  20. Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

    Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

    This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

  1. Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

    Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

    2017-02-15

    An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

  2. High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

    Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

    2003-01-01

    Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

  3. Effect of Processing Parameters on Thickness of Columnar Structured Silicon Wafers Directly Grown from Silicon Melts

    Jin-Seok Lee

    2012-01-01

    Full Text Available In order to obtain optimum growth conditions for desired thickness and more effective silicon feedstock usage, effects of processing parameters such as preheated substrate temperatures, time intervals, moving velocity of substrates, and Ar gas blowing rates on silicon ribbon thickness were investigated in the horizontal growth process. Most of the parameters strongly affected in the control of ribbon thickness with columnar grain structure depended on the solidification rate. The thickness of the silicon ribbon decreased with an increasing substrate temperature, decreasing time interval, and increasing moving velocity of the substrate. However, the blowing of Ar gas onto a liquid layer existing on the surface of solidified ribbon contributed to achieving smooth surface roughness but did not closely affect the change of ribbon thickness in the case of a blowing rate of ≥0.65 Nm3/h because the thickness of the solidified layer was already determined by the exit height of the reservoir.

  4. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    Mou, Chun-Yueh; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-01-01

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate

  5. Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

    Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

    2014-07-21

    Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

  6. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    Mou, Chun-Yueh, E-mail: cymou165@gmail.com; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-06-30

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate.

  7. Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

    Wang, Shing-Dar; Chen, Ting-Wei

    2018-06-01

    In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

  8. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  9. Wafer-level packaging with compression-controlled seal ring bonding

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  10. Analysis of borophosphosilicate glass layers on silicon wafers by X-ray emission from photon and electron excitation

    Elgersma, O.; Borstrok, J.J.M.

    1989-01-01

    Phosphorus and oxygen concentrations in the homogeneous layer of borosilicate glass (BPSG) deposited on Si-integrated circuits are determined by X-ray fluorescence from photon excitation. The X-ray emission from electron excitation in an open X-ray tube instrument yields a sufficiently precise determination of the boron content. The thickness of the layer can be derived from silicon Kα-fluorescence. A calibration model is proposed for photon as well as for electron excitation. The experimentally determined parameters in this model well agree with those derived from fundamental parameters for X-ray absorption and emission. The chemical surrounding of silicon affects strongly the peak profile of the silicon Kβ-emission. This enables to distinguish emission from the silicon atoms in the wafer and from the silicon atoms in the silicon oxide complexes of the BPSG-layer. (author)

  11. Effect of PECVD SiNx/SiOy Nx –Si interface property on surface passivation of silicon wafer

    Jia Xiao-Jie; Zhou Chun-Lan; Zhou Su; Wang Wen-Jing; Zhu Jun-Jie

    2016-01-01

    It is studied in this paper that the electrical characteristics of the interface between SiO y N x /SiN x stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiO y N x layer on interface parameters, such as interface state density Di t and fixed charge Q f , and the surface passivation quality of silicon are observed. Capacitance–voltage measurements reveal that inserting a thin SiO y N x layer between the SiN x and the silicon wafer can suppress Q f in the film and D it at the interface. The positive Q f and D it and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiO y N x film increasing. Prepared by deposition at a low temperature and a low ratio of N 2 O/SiH 4 flow rate, the SiO y N x /SiN x stacks result in a low effective surface recombination velocity (S eff ) of 6 cm/s on a p-type 1 Ω·cm–5 Ω·cm FZ silicon wafer. The positive relationship between S eff and D it suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. (paper)

  12. Wafer level packaging of MEMS

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  13. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  14. Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

    Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

    2012-01-01

    Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

  15. Reliability assessment of ultra-thin HfO{sub 2} films deposited on silicon wafer

    Fu, Wei-En [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Chang, Chia-Wei [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Chang, Yong-Qing [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Yao, Chih-Kai [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Liao, Jiunn-Der, E-mail: jdliao@mail.ncku.edu.tw [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China)

    2012-09-01

    Highlights: Black-Right-Pointing-Pointer Nano-mechanical properties on annealed ultra-thin HfO{sub 2} film are studied. Black-Right-Pointing-Pointer By AFM analysis, hardness of the crystallized HfO{sub 2} film significantly increases. Black-Right-Pointing-Pointer By nano-indention, the film hardness increases with less contact stiffness. Black-Right-Pointing-Pointer Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO{sub 2}) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO{sub 2} films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO{sub 2} films deposited on silicon wafers (HfO{sub 2}/SiO{sub 2}/Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO{sub 2} (nominal thickness Almost-Equal-To 10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO{sub 2} phases for the atomic layer deposited HfO{sub 2}. The HfSi{sub x}O{sub y} complex formed at the interface between HfO{sub 2} and SiO{sub 2}/Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO{sub 2} film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically

  16. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  17. Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

    Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

    2016-02-15

    Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

  18. Magnetic Induction Machines Embedded in Fusion-Bonded Silicon

    Arnold, David P; Cros, Florent; Zana, Iulica; Allen, Mark G; Das, Sauparna; Lang, Jeffrey H

    2004-01-01

    ...) within etched and fusion-bonded silicon to form the machine structure. The induction machines were characterized in motoring mode using tethered rotors, and exhibited a maximum measured torque...

  19. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  20. Wafer-level hermetic thermo-compression bonding using electroplated gold sealing frame planarized by fly-cutting

    Farisi, Muhammad Salman Al; Hirano, Hideki; Frömel, Jörg; Tanaka, Shuji

    2017-01-01

    In this paper, a novel wafer-level hermetic packaging technology for heterogeneous device integration is presented. Hermetic sealing is achieved by low-temperature thermo-compression bonding using electroplated Au micro-sealing frame planarized by single-point diamond fly-cutting. The proposed technology has significant advantages compared to other established processes in terms of integration of micro-structured wafer, vacuum encapsulation and electrical interconnection, which can be achieved at the same time. Furthermore, the technology is also achievable for a bonding frame width as narrow as 30 μm, giving it an advantage from a geometry perspective, and bonding temperatures as low as 300 °C, making it advantageous for temperature-sensitive devices. Outgassing in vacuum sealed cavities is studied and a cavity pressure below 500 Pa is achieved by introducing annealing steps prior to bonding. The pressure of the sealed cavity is measured by zero-balance method utilizing diaphragm-structured bonding test devices. The leak rate into the packages is determined by long-term sealed cavity pressure measurement for 1500 h to be less than 2.0× {{10}-14} Pa m3s-1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

  1. Determination of wafer bonding mechanisms for plasma activated SiN films with x-ray reflectivity

    Hayashi, S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Sandhu, R [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Wojtowicz, M [Northrop Grumman Space Technology, Redondo Beach, CA 90278 (United States); Sun, Y [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Hicks, R [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Goorsky, M S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States)

    2005-05-21

    Specular and diffuse x-ray reflectivity measurements were employed for wafer bonding studies of surface and interfacial reactions in {approx}800 A thick SiN films deposited on III-V substrates. CuK{sub {alpha}}{sub 1} radiation was employed for these measurements. The as-deposited films show very low surface roughness and uniform, high density SiN. Reflectivity measurements show that an oxygen plasma treatment converts the nitride surface to a somewhat porous SiO{sub x} layer (67 A thick, at 80% of SiO{sub 2} density), with confirmation of the oxide formation from x-ray photoelectron spectroscopy. Reactions at the bonded interface of two oxygen plasma treated SiN layers were examined using a bonded structure from which one of the III-V wafers is removed. Reflectivity measurements of bonded structures annealed at 150 deg. C and 300 deg. C show an increase in the SiO{sub x} layer density and thickness and even a density gradient across this interface. The increase in density is correlated with an increase in bond strength, where after the 300 deg. C anneal, a high interfacial bond strength, exceeding the bulk strength, was achieved.

  2. Quantitative analysis of phosphosilicate glass films on silicon wafers for calibration of x-ray fluorescence spectrometry standards

    Weissman, S.H.

    1983-01-01

    The phosphorus and silicon contents of phosphosilicate glass films deposited by chemical vapor deposition (CVD) on silicon wafers were determined. These films were prepared for use as x-ray fluorescence (XRF) spectrometry standards. The thin films were removed from the wafer by etching with dilute hydrofluoric acid, and the P and Si concentrations in solution were determined by inductively coupled plasma atomic emission spectroscopy (ICP). The calculated phosphorus concentration ranged from 2.2 to 12 wt %, with an uncertainty of 2.73 to 10.1 relative percent. Variation between the calculated weight loss (summation of P 2 O 5 and SiO 2 amounts as determined by ICP) and the measured weight loss (determined gravimetrically) averaged 4.9%. Results from the ICP method, Fourier transform-infrared spectroscopy (FT-IR), dispersive infrared spectroscopy, electron microprobe, and x-ray fluorescence spectroscopy for the same samples are compared

  3. Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

    Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

    2013-05-06

    Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

  4. Gelcasting of SiC/Si for preparation of silicon nitride bonded silicon carbide

    Xie, Z.P.; Tsinghua University, Beijing,; Cheng, Y.B.; Lu, J.W.; Huang, Y.

    2000-01-01

    In the present paper, gelcasting of aqueous slurry with coarse silicon carbide(1mm) and fine silicon particles was investigated to fabricate silicon nitride bonded silicon carbide materials. Through the examination of influence of different polyelectrolytes on the Zeta potential and viscosity of silicon and silicon carbide suspensions, a stable SiC/Si suspension with 60 vol% solid loading could be prepared by using polyelectrolyte of D3005 and sodium alginate. Gelation of this suspension can complete in 10-30 min at 60-80 deg C after cast into mold. After demolded, the wet green body can be dried directly in furnace and the green strength will develop during drying. Complex shape parts with near net size were prepared by the process. Effects of the debindering process on nitridation and density of silicon nitride bonded silicon carbide were also examined. Copyright (2000) The Australian Ceramic Society

  5. Femtosecond versus nanosecond laser machining: comparison of induced stresses and structural changes in silicon wafers

    Amer, M.S.; El-Ashry, M.A.; Dosser, L.R.; Hix, K.E.; Maguire, J.F.; Irwin, Bryan

    2005-01-01

    Laser micromachining has proven to be a very successful tool for precision machining and microfabrication with applications in microelectronics, MEMS, medical device, aerospace, biomedical, and defense applications. Femtosecond (FS) laser micromachining is usually thought to be of minimal heat-affected zone (HAZ) local to the micromachined feature. The assumption of reduced HAZ is attributed to the absence of direct coupling of the laser energy into the thermal modes of the material during irradiation. However, a substantial HAZ is thought to exist when machining with lasers having pulse durations in the nanosecond (NS) regime. In this paper, we compare the results of micromachining a single crystal silicon wafer using a 150-femtosecond and a 30-nanosecond lasers. Induced stress and amorphization of the silicon single crystal were monitored using micro-Raman spectroscopy as a function of the fluence and pulse duration of the incident laser. The onset of average induced stress occurs at lower fluence when machining with the femtosecond pulse laser. Induced stresses were found to maximize at fluence of 44 J cm -2 and 8 J cm -2 for nanosecond and femtosecond pulsed lasers, respectively. In both laser pulse regimes, a maximum induced stress is observed at which point the induced stress begins to decrease as the fluence is increased. The maximum induced stress was comparable at 2.0 GPa and 1.5 GPa for the two lasers. For the nanosecond pulse laser, the induced amorphization reached a plateau of approximately 20% for fluence exceeding 22 J cm -2 . For the femtosecond pulse laser, however, induced amorphization was approximately 17% independent of the laser fluence within the experimental range. These two values can be considered nominally the same within experimental error. For femtosecond laser machining, some effect of the laser polarization on the amount of induced stress and amorphization was also observed

  6. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  7. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  8. Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

    Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

    2017-09-01

    SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

  9. Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

    Di Di

    2014-01-01

    Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

  10. Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

    Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

    2009-01-01

    Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

  11. A full-wafer fabrication process for glass microfluidic chips with integrated electroplated electrodes by direct bonding of dry film resist

    Vulto, Paul; Urban, G A; Huesgen, Till; Albrecht, Björn

    2009-01-01

    A full-wafer process is presented for fast and simple fabrication of glass microfluidic chips with integrated electroplated electrodes. The process employs the permanent dry film resist (DFR) Ordyl SY300 to create microfluidic channels, followed by electroplating of silver and subsequent chlorination. The dry film resist is bonded directly to a second substrate, without intermediate gluing layers, only by applying pressure and moderate heating. The process of microfluidic channel fabrication, electroplating and wafer bonding can be completed within 1 day, thus making it one of the fastest and simplest full-wafer fabrication processes. (note)

  12. Glass frit bonding with controlled width and height using a two-step wet silicon etching procedure

    Yifang, Liu; Daner, Chen; Liwei, Lin; Gaofeng, Zheng; Jianyi, Zheng; Lingyun, Wang; Daoheng, Sun

    2016-03-01

    A simple and versatile two-step silicon wet etching technique for the control of the width and height of the glass frit bonding layer has been developed to improve bonding strength and reliability in wafer-level microelectromechanical systems (MEMS) packaging processes. The height of the glass frit bonding layer is set by the design of a vertical reference wall which regulates the distance between the silicon wafer and the encapsulation capping substrate. On the other hand, the width of the bonding layer is constrained between two micro grooves which are used to accommodate the spillages of extra glass frit during the bonding process. An optimized thermal bonding process, including the formation of glass liquid, removal of gas bubbles under vacuum and the filling of voids under normal atmospheric condition has been developed to suppress the formation of the bubbles/voids. The stencil printing and pre-sintering processes for the glass frit have been characterized before the thermal bonding process under different magnitudes of bonding pressure. The bonding gap thickness is found to be equal to the height of the reference wall of 10 μm in the prototype design. The bubbles/voids are found to be suppressed effectively and the bonding strength increases from 10.2 to 19.1 MPa as compared with a conventional thermal annealing process in air. Experimentally, prototype samples are measured to have passed the high hermetic sealing leakage tests of 5  ×  10-8 atm cc s-1.

  13. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  14. Hybrid Integrated Platforms for Silicon Photonics

    Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

    2010-01-01

    A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  15. Hybrid Integrated Platforms for Silicon Photonics

    John E. Bowers

    2010-03-01

    Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  16. Sealing of cavities with lateral feed-throughs by anodic bonding

    Fléron, René; Jensen, Flemming

    2003-01-01

    The SESiBon(1)) project under the EU Growth programme has focussed on the investigation and exploitation of various silicon bonding techniques. Both standard silicon to pyrex wafer bonding and the more advanced silicon-to-silicon thin film anodic bonding has been investigated. Here we present...... the results of the work done to enable bonding of structured wafer surfaces, allowing lateral feed-throughs into sealed cavities.Lateral feed throughs are formed by means of RIE in a high-doped poly-silicon film deposited on an oxidized 4" silicon wafer. Next a BPSG (Boron Phosphorus Silicate Glass) layer...... is deposited in a PECVD reaction chamber onto the structured surface. The BPSG is used as an intermediate planarization layer. Planarization is done by annealing the wafer in a N2-O2-H2O ambient for 4 - 8h @ 900 degreesC. After planarization the two wafers are bonded together, sealing the cavities.Our work...

  17. Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

    Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

    2013-01-02

    Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

  18. Investigation of room-temperature wafer bonded GaInP/GaAs/InGaAsP triple-junction solar cells

    Yang, Wen-xian; Dai, Pan; Ji, Lian; Tan, Ming; Wu, Yuan-yuan [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Uchida, Shiro [Department of Mechanical Science and Engineering Faculty of Engineering, Chiba Institute of Technology, 2-17-1, Tsudanuma, Narashino, Chiba 275-0016 (Japan); Lu, Shu-long, E-mail: sllu2008@sinano.ac.cn [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Yang, Hui [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China)

    2016-12-15

    Highlights: • High quality InGaAsP material with a bandgap of 1.0 eV was grown by MBE. • Room-temperature wafer-bonded GaInP/GaAs/InGaAsP SCs were fabricated. • An efficiency of 30.3% of wafer-bonded triple-junction SCs was obtained. - Abstract: We report on the fabrication of III–V compound semiconductor multi-junction solar cells using the room-temperature wafer bonding technique. GaInP/GaAs dual-junction solar cells on GaAs substrate and InGaAsP single junction solar cell on InP substrate were separately grown by all-solid state molecular beam epitaxy (MBE). The two cells were then bonded to a triple-junction solar cell at room-temperature. A conversion efficiency of 30.3% of GaInP/GaAs/InGaAsP wafer-bonded solar cell was obtained at 1-sun condition under the AM1.5G solar simulator. The result suggests that the room-temperature wafer bonding technique and MBE technique have a great potential to improve the performance of multi-junction solar cell.

  19. Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

    Norris, D J; Myronov, M; Leadley, D R; Walther, T

    2017-12-01

    We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

  20. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  1. Synthesis of thermoresponsive poly(N-isopropylacrylamide) brush on silicon wafer surface via atom transfer radical polymerization

    Turan, Eylem; Demirci, Serkan [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey); Caykara, Tuncer, E-mail: caykara@gazi.edu.t [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey)

    2010-08-31

    Thermoresponsive poly(N-isopropylacrylamide) [poly(NIPAM)] brush on silicon wafer surface was prepared by combining the self-assembled monolayer of initiator and atom transfer radical polymerization (ATRP). The resulting polymer brush was characterized by in situ reflectance Fourier transform infrared spectroscopy, atomic force microscopy and ellipsometry techniques. Gel permeation chromatography determination of the number-average molecular weight and polydispersity index of the brush detached from the silicon wafer surface suggested that the surface-initiated ATRP method can provide relatively homogeneous polymer brush. Contact angle measurements exhibited a two-stage increase upon heating over the board temperature range 25-45 {sup o}C, which is in contrast to the fact that free poly(NIPAM) homopolymer in aqueous solution exhibits a phase transition at ca. 34 {sup o}C within a narrow temperature range. The first de-wetting transition takes place at 27 {sup o}C, which can be tentatively attributed to the n-cluster induced collapse of the inner region of poly(NIPAM) brush close to the silicon surface; the second de-wetting transition occurs at 38 {sup o}C, which can be attributed to the outer region of poly(NIPAM) brush, possessing much lower chain density compared to that of the inner part.

  2. Hysteresis-free high-temperature precise bimorph actuators produced by direct bonding of lithium niobate wafers

    Shur, V. Ya.; Baturin, I. S.; Mingaliev, E. A.; Zorikhin, D. V.; Udalov, A. R.; Greshnyakov, E. D. [Ferroelectric Laboratory, Institute of Natural Sciences, Ural Federal University, 51 Lenin Ave., 620000 Ekaterinburg (Russian Federation)

    2015-02-02

    The current paper presents a piezoelectric bimorph actuator produced by direct bonding of lithium niobate wafers with the mirrored Y and Z axes. Direct bonding technology allowed to fabricate bidomain plate with precise positioning of ideally flat domain boundary. By optimizing the cutting angle (128° Y-cut), the piezoelectric constant became as large as 27.3 pC/N. Investigation of voltage dependence of bending displacement confirmed that bimorph actuator has excellent linearity and hysteresis-free. Decrease of the applied voltage down to mV range showed the perfect linearity up to the sub-nm deflection amplitude. The frequency and temperature dependences of electromechanical transmission coefficient in wide temperature range (from 300 to 900 K) were investigated.

  3. Silicon hybrid integration

    Li Xianyao; Yuan Taonu; Shao Shiqian; Shi Zujun; Wang Yi; Yu Yude; Yu Jinzhong

    2011-01-01

    Recently,much attention has concentrated on silicon based photonic integrated circuits (PICs), which provide a cost-effective solution for high speed, wide bandwidth optical interconnection and optical communication.To integrate III-V compounds and germanium semiconductors on silicon substrates,at present there are two kinds of manufacturing methods, i.e., heteroepitaxy and bonding. Low-temperature wafer bonding which can overcome the high growth temperature, lattice mismatch,and incompatibility of thermal expansion coefficients during heteroepitaxy, has offered the possibility for large-scale heterogeneous integration. In this paper, several commonly used bonding methods are reviewed, and the future trends of low temperature wafer bonding envisaged. (authors)

  4. Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

    Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

    2018-05-01

    Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

  5. Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

    Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

    2013-04-01

    In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

  6. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  7. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  8. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  9. Interfacial Characteristics of TiN Coatings on SUS304 and Silicon Wafer Substrates with Pulsed Laser Thermal Shock

    Seo, Nokun; Jeon, Seol; Choi, Youngkue; Shin, Hyun-Gyoo; Lee, Heesoo; Jeon, Min-Seok

    2014-01-01

    TiN coatings prepared on different substrates that had different coefficients of thermal expansion were subjected to pulsed laser thermal shock and observed by using FIB milling to compare the deterioration behaviors. TiN coating on SUS304, which had a larger CTE (⁓17.3 × 10 - 6 /℃) than the coating was degraded with pores and cracks on the surface and showed significant spalling of the coating layer over a certain laser pulses. TiN coating on silicon wafer with a smaller CTE value, ⁓4.2 × 10‒6 /℃, than the coating exhibited less degradation of the coating layer at the same ablation condition. Cracks propagated at the interface were observed in the coating on the silicon wafer, which induced a compressive stress to the coating. The coating on the SUS304 showed less interface cracks while the tensile stress was applied to the coating. Delamination of the coating layer related to the intercolumnar cracks at the interface was observed in both coatings through bright-field TEM analysis.

  10. Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

    Takahara, Hikari; Mori, Yoshihiro; Shibata, Harumi; Shimazaki, Ayako; Shabani, Mohammad B.; Yamagami, Motoyuki; Yabumoto, Norikuni; Nishihagi, Kazuo; Gohshi, Yohichi

    2013-01-01

    Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10 9 and 5 × 10 10 atoms/cm 2 Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO 2 , silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10 10 atoms/cm 2 . • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies

  11. Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

    Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

    2002-01-01

    Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

  12. Pressure bonding molybdenum alloy (TZM) to reaction-bonded silicon nitride

    Huffsmith, S.A.; Landingham, R.L.

    1978-01-01

    Topping cycles could boost the energy efficiencies of a variety of systems by using what is now waste heat. One such topping cycle uses a ceramic helical expander and would require that a reaction-bonded silicon nitride (RBSN) rotor be bonded to a shaft of TZM (Mo-0.5 wt % Ti-0.08 wt % Zr). Coupon studies show that TZM can be bonded to RBSN at 1300 0 C and 69 MPa if there is an interlayer of MoSi 2 . A layer of finely ground (10 μm) MoSi 2 facilitates bond formation and provides a thicker bond interface. The hardness and grain structure of the TZM and RBSN were not affected by the temperature and pressure required to bond the coupons

  13. Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

    Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

    2013-08-20

    To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

  14. Sidewall patterning - A new wafer-scale method for accurate patterning of vertical silicon structures

    Westerik, P. J.; Vijselaar, W. J.C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G.E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that

  15. Wafer-level hermetic vacuum packaging by bonding with a copper-tin thin film sealing ring

    Akashi, Teruhisa; Funabashi, Hirofumi; Takagi, Hideki; Omura, Yoshiteru; Hata, Yoshiyuki

    2018-04-01

    A wafer-level hermetic vacuum packaging technology intended for use with MEMS devices was developed based on a copper-tin (CuSn) thin film sealing ring. To allow hermetic packaging, the shear strength of the CuSn thin film bond was improved by optimizing the pretreatment conditions. As a result, an average shear strength of 72.3 MPa was obtained and a cavity that had been hermetically sealed using wafer-level packaging (WLP) maintained its vacuum for 1.84 years. The total pressures in the cavities and the partial pressures of residual gases were directly determined with an ultra-low outgassing residual gas analyzer (RGA) system. Hermeticity was evaluated based on helium leak rates, which were calculated from helium pressures determined with the RGA system. The resulting data showed that a vacuum cavity following 1.84 years storage had a total pressure of 83.1 Pa, contained argon as the main residual gas and exhibited a helium leak rate as low as 1.67  ×  10-17 Pa · m3 s-1, corresponding to an air leak rate of 6.19  ×  10-18 Pa · m3 s-1. The RGA data demonstrate that WLP using a CuSn thin film sealing ring permits ultra-high hermeticity in conjunction with long-term vacuum packaging that is applicable to MEMS devices.

  16. Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

    Rouault de Coligny, P.

    2002-09-15

    This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

  17. Interaction between dangling bonds in vacancy-defects in silicon

    Caldas, M.J.; Fazzio, A.

    1983-01-01

    The 'defect-molecule' model in the simplest scheme (without configuration interaction) is reviewed and the concept of 'delocalized dangling-bonds' is explorated in the study of the interaction between the unsaturated hybrids of the mono and divacancy in silicon. The 'defect-molecule' hamiltonian is written in parametric form, and the parameters are extracted from full self-consistent calculations for both systems carried out through the MS-Xα molecular cluster model. (Author) [pt

  18. A Reuse Evaluation for Solar-Cell Silicon Wafers via Shift Revolution and Tool Rotation Using Magnetic Assistance in Ultrasonic Electrochemical Micromachining

    P. S. Pa

    2013-01-01

    Full Text Available A new reuse fabrication using a tool module with rotation and revolution through a process of magnetic assistance in ultrasonic electrochemical micromachining (UEMM for removal of the surface layers from silicon wafers of solar cells is demonstrated. The target of the proposed reuse fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach to removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. The high revolution speed of the shift with the high rotation speed of the designed tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. High frequency and high power of ultrasonic with large electrolyte flow rate and high magnetic strengths with a small distance between the two magnets provide a large discharge effect and good removal; only a short period of time is required to remove the epoxy film and Si3N4 layer easily and cleanly.

  19. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  20. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

    2017-01-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

  1. Ion-implanted capacitively coupled silicon strip detectors with integrated polysilicon bias resistors processed on a 100 mm wafer

    Hietanen, I.; Lindgren, J.; Orava, R.; Tuuva, T.; Voutilainen, M.; Brenner, R.; Andersson, M.; Leinonen, K.; Ronkainen, H.

    1991-01-01

    Double-sided silicon strip detectors with integrated coupling capacitors and polysilicon resistors have been processed on a 100 mm wafer. A detector with an active area of 19x19 mm 2 was connected to LSI readout electronics and tested. The strip pitch of the detector is 25 μm on the p-side and 50 μm on the n-side. The readout pitch is 50 μm on both sides. The number of readout strips is 774 and the total number of strips is 1161. On the p-side a signal-to-noise of 35 has been measured using a 90 Sr β-source. The n-side has been studied using a laser. (orig.)

  2. Examining the free radical bonding mechanism of benzoquinone– and hydroquinone–methanol passivation of silicon surfaces

    Kotulak, Nicole A.; Chen, Meixi; Schreiber, Nikolas; Jones, Kevin; Opila, Robert L.

    2015-01-01

    Highlights: • Photons are required for high levels of c-Si passivation by both BQ/ME and HQ/ME solutions. • Protons are required for high levels of c-Si passivation by both BQ/ME and HQ/ME solutions. • The free radical QH· is the likely passivating species for c-Si surfaces from BQ/ME and HQ/ME solutions. - Abstract: The surface passivation of p-benzoquinone (BQ) and hydroquinone (HQ) when dissolved in methanol (ME) has been examined through effective lifetime testing of crystalline silicon (c-Si) wafers treated with the aforementioned solutions. Changes in the availability of both photons and protons in the solutions were demonstrated to affect the level of passivation achieved. The requirement of both excess protons and ambient light exposure to maintain high effective lifetimes supports the presence of a free radical species that drives the surface passivation. Surface analysis suggests a 1:1 ratio of HQ-like bonds to methoxy bonds on the c-Si surface after treatment with a BQ/ME solution.

  3. Hydrogen concentration profiles and chemical bonding in silicon nitride

    Peercy, P.S.; Stein, H.J.; Doyle, B.L.; Picraux, S.T.

    1978-01-01

    The complementary technique of nuclear reaction analysis and infrared absorption were used to study the concentration profile and chemical bonding of hydrogen in silicon nitride for different preparation and annealing conditions. Silicon nitride prepared by chemical vapor deposition from ammonia-silane mixtures is shown to have hydrogen concentrations of 8.1 and 6.5 at.% for deposition temperatures of 750 and 900 0 C, respectively. Plasma deposition at 300 0 C from these gases results in hydrogen concentrations of approximately 22 at.%. Comparison of nuclear reaction analysis and infrared absorption measurements after isothermal annealing shows that all of the hydrogen retained in the films remains bonded to either silicon or nitrogen and that hydrogen release from the material on annealing is governed by various trap energies involving at least two N-H and one Si-H trap. Reasonable estimates of the hydrogen release rates can be made from the effective diffusion coefficient obtained from measurements of hydrogen migration in hydrogen implanted and annealed films

  4. Material size effects on crack growth along patterned wafer-level Cu–Cu bonds

    Tvergaard, Viggo; Niordson, Christian Frithiof; Hutchinson, John W.

    2013-01-01

    together. Crack growth along the bond interface is here studied numerically using finite element analyses. The experiments have shown that plasticity in the Cu films makes a major contribution to the macroscopic interface toughness. To account for the size dependence of the plastic flow a strain gradient...... plasticity model is applied here for the metal. A cohesive zone model is applied to represent the crack growth along the bond between the two Cu films. This cohesive zone model incorporates the effect of higher order stresses in the continuum, such that the higher order tractions on the crack faces decay...... the toughness peak and the subsequent plateau level are highly sensitive to the value of the characteristic material length. A small material length, relative to the thickness of the Cu film, gives high toughness whereas a length comparable to the film thickness gives much reduced crack growth resistance...

  5. Preliminary reduction of chromium ore using Si sludge generated in silicon wafer manufacturing process

    Jung W.-G.

    2018-01-01

    Full Text Available In order to promote the recycling of by-product from Si wafer manufacturing process and to develop environment-friend and low cost process for ferrochrome alloy production, a basic study was performed on the preliminary reduction reaction between chromium ore and the Si sludge, comprised of SiC and Si particles, which is recovered from the Si wafer manufacturing process for the semiconductor and solar cell industries. Pellets were first made by mixing chromium ore, Si sludge, and some binders in the designed mixing ratios and were then treated at different temperatures in the 1116°C–1388°C range in an ambient atmosphere. Cordierite and SiO2 were confirmed to be formed in the products after the reduction. Additionally, metal particles were observed in the product with Fe, Cr, and Si components. It is found that temperatures above 1300°C are necessary for the reduction of the chromium ore by the Si sludge. The reduction ratio for Fe was evaluated quantitatively for our experimental conditions, and the proper mixing ratio was suggested for the pre-reduction of the chromium ore by the Si sludge. This study provides basic information for the production of ferrochrome alloys on the pre-reduction of chromium ore using Si sludge.

  6. Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

    Aono, T.; Kazama, A.; Okada, R.; Iwasaki, T.; Isono, Y.

    2018-03-01

    We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

  7. Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

    Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

    2016-11-01

    The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

  8. Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

    Ali Attaran

    2014-01-01

    Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

  9. Possibility of whole-surface analysis of a silicon wafer with ordinary straight TXRF

    Mori, Y.; Uemura, K.; Iizuka, Y.

    2000-01-01

    For the analysis of average metal concentration on a semiconductor surface, we customarily use the wet techniques (AAS, typically), that require skilled operators or expensive automated machines for sample pretreatment. The straight TXRF require no pretreatment, on the other hand. However, its detection area is too small (1-2 cm 2 ) to conduct a whole-surface analysis. In fact, it takes more than one day per one wafer (500 s/point x 100-300 points) for a complete mapping. Therefore it has been believed that the whole-surface analysis with straight TXRF is impracticable. It should be noted that the absolute lower limit of detection (LLD) of the straight TXRF is superior to AAS. As an example, the absolute LLD of TXRF for Fe is 0.2 pg (500 s integration), while that of AAS is l0 pg. The required integration time for TXRF to obtain the same LLD of AAS is calculated to be only 0.2 s. This means, in principle, that the whole-surface contamination can be measured in some ten seconds by accumulating 0.2 s mapping. But actually, the adjustment of glancing angle requires several ten seconds per one point, so the above mapping still takes several hours. That is why such a measurement has not been applied to daily analysis so far. However, the influence of glancing angle errors is expected to be reduced through the multi-point measurement. Figure 1 shows an accumulated spectrum of 20 s x 25 points mapping for an IAP wafer doped with Ni. In this measurement, glancing angles were not precisely controlled (the error of glancing angle is ±15 %). A spectrum of 500 s x 1 point measurement for the same wafer is shown in Figure 2. Figures 1 and 2 are almost identical. This suggests that the reduction of glancing angle errors actually works well through multi-points measurement. This method is expected to give better results by increasing the number of measuring points. The overall variation for the final measurement value obtained by multi-point measurement can be assessed by the

  10. Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

    Takaura, Norikatsu

    1997-10-01

    As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular

  11. Radiation hardness of silicon detectors manufactured on wafers from various sources

    Dezillie, B.; Bates, S.; Glaser, M.; Lemeilleur, F.; Leroy, C.

    1997-01-01

    Impurity concentrations in the initial silicon material are expected to play an important role for the radiation hardness of silicon detectors, during their irradiation and for their evolution with time after irradiation. This work reports on the experimental results obtained with detectors manufactured using various float-zone (FZ) and epitaxial-grown material. Preliminary results comparing the changes in leakage current and full depletion voltage of FZ and epitaxial detectors as a function of fluence and of time after 10 14 cm -2 proton irradiation are given. The measurement of charge collection efficiency for epitaxial detectors is also presented. (orig.)

  12. Damage-free polishing of monocrystalline silicon wafers without chemical additives

    Biddut, A.Q.; Zhang, L.C.; Ali, Y.M.; Liu, Z.

    2008-01-01

    This investigation explores the possibility and identifies the mechanism of damage-free polishing of monocrystalline silicon without chemical additives. Using high resolution electron microscopy and contact mechanics, the study concludes that a damage-free polishing process without chemicals is feasible. All forms of damages, such as amorphous Si, dislocations and plane shifting, can be eliminated by avoiding the initiation of the β-tin phase of silicon during polishing. When using 50 nm abrasives, the nominal pressure to achieve damage-free polishing is 20 kPa

  13. Oxidation Protection of Porous Reaction-Bonded Silicon Nitride

    Fox, D. S.

    1994-01-01

    Oxidation kinetics of both as-fabricated and coated reaction-bonded silicon nitride (RBSN) were studied at 900 and 1000 C with thermogravimetry. Uncoated RBSN exhibited internal oxidation and parabolic kinetics. An amorphous Si-C-O coating provided the greatest degree of protection to oxygen, with a small linear weight loss observed. Linear weight gains were measured on samples with an amorphous Si-N-C coating. Chemically vapor deposited (CVD) Si3N4 coated RBSN exhibited parabolic kinetics, and the coating cracked severely. A continuous-SiC-fiber-reinforced RBSN composite was also coated with the Si-C-O material, but no substantial oxidation protection was observed.

  14. Evaluation of bonding between oxygen plasma treated polydimethyl siloxane and passivated silicon

    Tang, K C [Bioelectronics/BioMEMS Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore); Liao, E [Semiconductor Process Technologies Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore); Ong, W L [Bioelectronics/BioMEMS Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore); Wong, J D S [Semiconductor Process Technologies Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore); Agarwal, A [Bioelectronics/BioMEMS Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore); Nagarajan, R [Semiconductor Process Technologies Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore); Yobas, L [Bioelectronics/BioMEMS Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, Singapore 117685 (Singapore)

    2006-04-01

    Oxygen plasma treatment has been used extensively to bond polydimethyl siloxane to polydimethyl siloxane or glass in the rapid prototyping of microfluidic devices. This study aimed to improve the bonding quality of polydimethyl siloxane to passivated silicon using oxygen plasma treatment, and also to evaluate the bonding quality. Four types of passivated silicon were used: phosphosilicate glass, undoped silicate glass, silicon nitride and thermally grown silicon dioxide. Bonding strength was evaluated qualitatively and quantitatively using manual peel and mechanical shear tests respectively. Through peel tests we found that the lowering of plasma pressure from 500 to 30 mTorr and using a plasma power between 20 to 60 W helped to improve the bond quality for the first three types of passivation. Detailed analysis and discussion were conducted to explain the discrepancy between the bonding strength results and peeling results. Our results suggested that polydimethyl siloxane can be effectively bonded to passivated silicon, just as to polydimethyl siloxane or glass.

  15. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  16. High-κ Al{sub 2}O{sub 3} material in low temperature wafer-level bonding for 3D integration application

    Fan, J., E-mail: fanji@hust.edu.cn; Tu, L. C. [MOE Key Laboratory of Fundamental Physical Quantities Measurement, School of Physics, Huazhong University of Science and Technology, Wuhan 430074 (China); Tan, C. S. [School of Electrical and Electronics Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2014-03-15

    This work systematically investigated a high-κ Al{sub 2}O{sub 3} material for low temperature wafer-level bonding for potential applications in 3D microsystems. A clean Si wafer with an Al{sub 2}O{sub 3} layer thickness of 50 nm was applied as our experimental approach. Bonding was initiated in a clean room ambient after surface activation, followed by annealing under inert ambient conditions at 300 °C for 3 h. The investigation consisted of three parts: a mechanical support study using the four-point bending method, hermeticity measurements using the helium bomb test, and thermal conductivity analysis for potential heterogeneous bonding. Compared with samples bonded using a conventional oxide bonding material (SiO{sub 2}), a higher interfacial adhesion energy (∼11.93 J/m{sup 2}) and a lower helium leak rate (∼6.84 × 10{sup −10} atm.cm{sup 3}/sec) were detected for samples bonded using Al{sub 2}O{sub 3}. More importantly, due to the excellent thermal conductivity performance of Al{sub 2}O{sub 3}, this technology can be used in heterogeneous direct bonding, which has potential applications for enhancing the performance of Si photonic integrated devices.

  17. Density functional study of the bonding in small silicon clusters

    Fournier, R.; Sinnott, S.B.; DePristo, A.E.

    1992-01-01

    We report the ground electronic state, equilibrium geometry, vibrational frequencies, and binding energy for various isomers of Si n (n = 2--8) obtained with the linear combination of atomic orbitals-density functional method. We used both a local density approximation approach and one with gradient corrections. Our local density approximation results concerning the relative stability of electronic states and isomers are in agreement with Hartree--Fock and Moller--Plesset (MP2) calculations [K. Raghavachari and C. M. Rohlfing, J. Chem. Phys. 89, 2219 (1988)]. The binding energies calculated with the gradient corrected functional are in good agreement with experiment (Si 2 and Si 3 ) and with the best theoretical estimates. Our analysis of the bonding reveals two limiting modes of bonding and classes of silicon clusters. One class of clusters is characterized by relatively large s atomic populations and a large number of weak bonds, while the other class of clusters is characterized by relatively small s atomic populations and a small number of strong bonds

  18. Internal Friction and Young's Modulus Measurements on SiO2 and Ta2O5 Films Done with an Ultra-High Q Silicon-Wafer Suspension

    Granata M.

    2015-04-01

    Full Text Available In order to study the internal friction of thin films a nodal suspension system called GeNS (Gentle Nodal Suspension has been developed. The key features of this system are: i the possibility to use substrates easily available like silicon wafers; ii extremely low excess losses coming from the suspension system which allows to measure Q factors in excess of 2×108 on 3” diameter wafers; iii reproducibility of measurements within few percent on mechanical losses and 0.01% on resonant frequencies; iv absence of clamping; v the capability to operate at cryogenic temperatures. Measurements at cryogenic temperatures on SiO2 and at room temperature only on Ta2O5 films deposited on silicon are presented.

  19. Neutron activation analysis of low-level element contents in silicon wafers

    Goerner, W [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Berger, A [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Niese, S [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Koehler, M [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Matthes, M [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Gawlik, D [Hahn-Meitner-Institut, Berlin (Germany)

    1997-03-01

    Semiconductor silicon is among the purest materials having ever been produced by modern technology. Thus, it is quite suitable as a primary reference material validating the correctness and the detection capabilities of developed analytical methods. Among them neutron activation analysis plays a competitive role. The U.S. National Institute of Science and Technology (NIST) has initiated and carried out an interlaboratory comparison in order to study the spread of analytical results worldwide evolved by several laboratories dealing with specimens of extreme purity. The outcome of the experiment was intended to review the capabilities of NAA as well as to differentiate between bulk and surface contamination. (orig./DG)

  20. Laser-fired contact formation on metallized and passivated silicon wafers under short pulse durations

    Raghavan, Ashwin S.

    The objective of this work is to develop a comprehensive understanding of the physical processes governing laser-fired contact (LFC) formation under microsecond pulse durations. Primary emphasis is placed on understanding how processing parameters influence contact morphology, passivation layer quality, alloying of Al and Si, and contact resistance. In addition, the research seeks to develop a quantitative method to accurately predict the contact geometry, thermal cycles, heat and mass transfer phenomena, and the influence of contact pitch distance on substrate temperatures in order to improve the physical understanding of the underlying processes. Finally, the work seeks to predict how geometry for LFCs produced with microsecond pulses will influence fabrication and performance factors, such as the rear side contacting scheme, rear surface series resistance and effective rear surface recombination rates. The characterization of LFC cross-sections reveals that the use of microsecond pulse durations results in the formation of three-dimensional hemispherical or half-ellipsoidal contact geometries. The LFC is heavily alloyed with Al and Si and is composed of a two-phase Al-Si microstructure that grows from the Si wafer during resolidification. As a result of forming a large three-dimensional contact geometry, the total contact resistance is governed by the interfacial contact area between the LFC and the wafer rather than the planar contact area at the original Al-Si interface within an opening in the passivation layer. By forming three-dimensional LFCs, the total contact resistance is significantly reduced in comparison to that predicted for planar contacts. In addition, despite the high energy densities associated with microsecond pulse durations, the passivation layer is well preserved outside of the immediate contact region. Therefore, the use of microsecond pulse durations can be used to improve device performance by leading to lower total contact resistances

  1. Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

    Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

    2013-03-25

    n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

  2. Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

    Nigel T. Maidment

    2008-08-01

    Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

  3. Barrier reduction via implementation of InGaN interlayer in wafer-bonded current aperture vertical electron transistors consisting of InGaAs channel and N-polar GaN drain

    Kim, Jeonghee; Laurent, Matthew A.; Li, Haoran; Lal, Shalini; Mishra, Umesh K.

    2015-01-01

    This letter reports the influence of the added InGaN interlayer on reducing the inherent interfacial barrier and hence improving the electrical characteristics of wafer-bonded current aperture vertical electron transistors consisting of an InGaAs channel and N-polar GaN drain. The current-voltage characteristics of the transistors show that the implementation of N-polar InGaN interlayer effectively reduces the barrier to electron transport across the wafer-bonded interface most likely due to its polarization induced downward band bending, which increases the electron tunneling probability. Fully functional wafer-bonded transistors with nearly 600 mA/mm of drain current at V GS  = 0 V and L go  = 2 μm have been achieved, and thus demonstrate the feasibility of using wafer-bonded heterostructures for applications that require active carrier transport through both materials

  4. Corporate array of micromachined dipoles on silicon wafer for 60 GHz communication systems

    Sallam, M. O.

    2013-03-01

    In this paper, an antenna array operating at 60 GHz and realized on 0.675 mm thick silicon substrate is presented. The array is constructed using four micromachined half-wavelength dipoles fed by a corporate feeding network. Isolation between the antenna array and its feeding network is achieved via a ground plane. This arrangement leads to maximizing the broadside radiation with relatively high front-to-back ratio. Simulations have been carried out using both HFSS and CST, which showed very good agreement. Results reveal that the proposed antenna array has good radiation characteristics, where the directivity, gain, and radiation efficiency are around 10.5 dBi, 9.5 dBi, and 79%, respectively. © 2013 IEEE.

  5. Removal of dangling bonds and surface states on silicon (001) with a monolayer of selenium

    Tao Meng; Udeshi, Darshak; Basit, Nasir; Maldonado, Eduardo; Kirk, Wiley P.

    2003-01-01

    Dangling bonds and surface states are inherent to semiconductor surfaces. By passivating dangling bonds on the silicon (001) surface with a monolayer of selenium, surface states are removed from the band gap. Magnesium contacts on selenium-passivated silicon (001) behave ohmically, as expected from the work function of magnesium and the electron affinity of silicon. After rapid thermal annealing and hot-plate annealing, magnesium contacts on selenium-passivated silicon (001) show better thermal stability than on hydrogen-passivated silicon (001), which is attributed to the suppression of silicide formation by selenium passivation

  6. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  7. Si-H bond dynamics in hydrogenated amorphous silicon

    Scharff, R. Jason; McGrane, Shawn D.

    2007-08-01

    The ultrafast structural dynamics of the Si-H bond in the rigid solvent environment of an amorphous silicon thin film is investigated using two-dimensional infrared four-wave mixing techniques. The two-dimensional infrared (2DIR) vibrational correlation spectrum resolves the homogeneous line shapes ( 4ps waiting times. The Si-H stretching mode anharmonic shift is determined to be 84cm-1 and decreases slightly with vibrational frequency. The 1→2 linewidth increases with vibrational frequency. Frequency dependent vibrational population times measured by transient grating spectroscopy are also reported. The narrow homogeneous line shape, large inhomogeneous broadening, and lack of spectral diffusion reported here present the ideal backdrop for using a 2DIR probe following electronic pumping to measure the transient structural dynamics implicated in the Staebler-Wronski degradation [Appl. Phys. Lett. 31, 292 (1977)] in a-Si:H based solar cells.

  8. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

    2018-01-01

    A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

  9. Ductile mode grinding of reaction-bonded silicon carbide mirrors.

    Dong, Zhichao; Cheng, Haobo

    2017-09-10

    The demand for reaction-bonded silicon carbide (RB-SiC) mirrors has escalated recently with the rapid development of space optical remote sensors used in astronomy or Earth observation. However, RB-SiC is difficult to machine due to its high hardness. This study intends to perform ductile mode grinding to RB-SiC, which produces superior surface integrity and fewer subsurface damages, thus minimizing the workload of subsequent lapping and polishing. For this purpose, a modified theoretical model for grain depth of cut of grinding wheels is presented, which correlates various processing parameters and the material characteristics (i.e., elastic module) of a wheel's bonding matrix and workpiece. Ductile mode grinding can be achieved as the grain depth of cut of wheels decreases to be less than the critical cut depth of workpieces. The theoretical model gives a roadmap to optimize the grinding parameters for ductile mode grinding of RB-SiC and other ultra-hard brittle materials. Its feasibility was validated by experiments. With the optimized grinding parameters for RB-SiC, the ductile mode grinding produced highly specular surfaces (with roughness of ∼2.2-2.8  nm Ra), which means the material removal mechanism of RB-SiC is dominated by plastic deformation rather than brittle fracture. Contrast experiments were also conducted on fused silica, using the same grinding parameters; this produced only very rough surfaces, which further validated the feasibility of the proposed model.

  10. The diffusion bonding of silicon carbide and boron carbide using refractory metals

    Cockeram, B.V.

    1999-01-01

    Joining is an enabling technology for the application of structural ceramics at high temperatures. Metal foil diffusion bonding is a simple process for joining silicon carbide or boron carbide by solid-state, diffusive conversion of the metal foil into carbide and silicide compounds that produce bonding. Metal diffusion bonding trials were performed using thin foils (5 microm to 100 microm) of refractory metals (niobium, titanium, tungsten, and molybdenum) with plates of silicon carbide (both α-SiC and β-SiC) or boron carbide that were lapped flat prior to bonding. The influence of bonding temperature, bonding pressure, and foil thickness on bond quality was determined from metallographic inspection of the bonds. The microstructure and phases in the joint region of the diffusion bonds were evaluated using SEM, microprobe, and AES analysis. The use of molybdenum foil appeared to result in the highest quality bond of the metal foils evaluated for the diffusion bonding of silicon carbide and boron carbide. Bonding pressure appeared to have little influence on bond quality. The use of a thinner metal foil improved the bond quality. The microstructure of the bond region produced with either the α-SiC and β-SiC polytypes were similar

  11. Wafer of Intel Pentium 4 Prescott Chips

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  12. Electrical Interconnections Through CMOS Wafers

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  13. Fusion-bonded fluidic interconnects

    Fazal, I; Elwenspoek, M C

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are discussed in terms of the homogeneity and strength of fusion bond. High pressure testing shows that the bond strength is large enough for most applications of fluidic interconnects. The bond strength for 525 µm thick silicon, with glass tubes having an outer diameter of 6 mm and with a wall thickness of 2 mm, is more than 60 bars after annealing at a temperature of 800 °C

  14. Reaction sintering of a clay-containing silicon nitride bonded silicon carbide refractory

    Swenser, S.P.; Cheng, Y.B.

    1998-01-01

    Aspects of the reaction sequence for the reaction bonding of a cast refractory, which in the green state was composed of 79 wt-% SiC grit, 16 wt-% Si powder and 5 wt-% clay were established. As it was fired up to 1600 deg C in flowing N 2 (g), weight gains were noted and phase evolution was monitored by X-ray diffraction. However, details of the reaction sequence were not determined directly from this material because several reaction-bonding processes occurred simultaneously. Reaction features were ascertained by contrasting the weight changes and phase evolution in the refractory with those observed during reaction-bonding of (a) Si and clay without the SiC and (b) SiC and clay without the Si. In addition to silicon nitridation and the development of sialon phases by silicothermal and carbothermal reduction-nitridation processes, indirect evidence suggested that α-Si 3 N 4 formed by the carbothermal reduction-nitridation (CRN) of SiO(g). Copyright (1998) Australasian Ceramic Society

  15. 1.3 μm wavelength vertical cavity surface emitting laser fabricated by orientation-mismatched wafer bonding: A prospect for polarization control

    Okuno, Yae L.; Geske, Jon; Gan, Kian-Giap; Chiu, Yi-Jen; DenBaars, Steven P.; Bowers, John E.

    2003-04-01

    We propose and demonstrate a long-wavelength vertical cavity surface emitting laser (VCSEL) which consists of a (311)B InP-based active region and (100) GaAs-based distributed Bragg reflectors (DBRs), with an aim to control the in-plane polarization of output power. Crystal growth on (311)B InP substrates was performed under low-migration conditions to achieve good crystalline quality. The VCSEL was fabricated by wafer bonding, which enables us to combine different materials regardless of their lattice and orientation mismatch without degrading their quality. The VCSEL was polarized with a power extinction ratio of 31 dB.

  16. Aberration-corrected transmission electron microscopy analyses of GaAs/Si interfaces in wafer-bonded multi-junction solar cells

    Häussler, Dietrich [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Houben, Lothar [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Essig, Stephanie [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Kurttepeli, Mert [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Dimroth, Frank [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Dunin-Borkowski, Rafal E. [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Jäger, Wolfgang, E-mail: wolfgang.jaeger@tf.uni-kiel.de [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany)

    2013-11-15

    Aberration-corrected scanning transmission electron microscopy (STEM) and electron energy loss spectroscopy (EELS) investigations have been applied to investigate the structure and composition fluctuations near interfaces in wafer-bonded multi-junction solar cells. Multi-junction solar cells are of particular interest since efficiencies well above 40% have been obtained for concentrator solar cells which are based on III-V compound semiconductors. In this methodologically oriented investigation, we explore the potential of combining aberration-corrected high-angle annular dark-field STEM imaging (HAADF-STEM) with spectroscopic techniques, such as EELS and energy-dispersive X-ray spectroscopy (EDXS), and with high-resolution transmission electron microscopy (HR-TEM), in order to analyze the effects of fast atom beam (FAB) and ion beam bombardment (IB) activation treatments on the structure and composition of bonding interfaces of wafer-bonded solar cells on Si substrates. Investigations using STEM/EELS are able to measure quantitatively and with high precision the widths and the fluctuations in element distributions within amorphous interface layers of nanometer extensions, including those of light elements. Such measurements allow the control of the activation treatments and thus support assessing electrical conductivity phenomena connected with impurity and dopant distributions near interfaces for optimized performance of the solar cells. - Highlights: • Aberration-corrected TEM and EELS reveal structural and elemental profiles across GaAs/Si bond interfaces in wafer-bonded GaInP/GaAs/Si - multi-junction solar cells. • Fluctuations in elemental concentration in nanometer-thick amorphous interface layers, including the disrubutions of light elements, are measured using EELS. • The projected widths of the interface layers are determined on the atomic scale from STEM-HAADF measurements. • The effects of atom and ion beam activation treatment on the bonding

  17. Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

    Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

    1993-01-01

    The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

  18. High-density plasma-induced etch damage of wafer-bonded AlGaInP/mirror/Si light-emitting diodes

    Wuu, D S; Huang, S H; Chung, C R

    2002-01-01

    Dry etch of wafer-bonded AlGaInP/mirror/Si light-emitting diodes (LEDs) with planar electrodes was performed by high-density plasma using an inductively coupled plasma (ICP) etcher. The etching characteristics were investigated by varying process parameters such as Cl sub 2 /N sub 2 gas combination, chamber pressure, ICP power and substrate-bias power. The corresponding plasma properties (ion flux and dc bias), in situ measured by a Langmuir probe, show a strong relationship to the etch results. With a moderate etch rate of 1.3 mu m/min, a near vertical and smooth sidewall profile can be achieved under a Cl sub 2 /(Cl sub 2 +N sub 2) gas mixture of 0.5, ICP power of 800 W, substrate-bias power of 100 W, and chamber pressure of 0.67 Pa. Quantitative analysis of the plasma-induced damage was attempted to provide a means to study the mechanism of leakage current and brightness with various dc bias voltages (-110 to -328 V) and plasma duration (3-5 min) on the wafer-bonded LEDs. It is found that the reverse leaka...

  19. Linear self-assembly and grafting of gold nanorods into arrayed micrometer-long nanowires on a silicon wafer via a combined top-down/bottom-up approach.

    Lestini, Elena; Andrei, Codrin; Zerulla, Dominic

    2018-01-01

    Macroscopically long wire-like arrangements of gold nanoparticles were obtained by controlled evaporation and partial coalescence of an aqueous colloidal solution of capped CTAB-Au nanorods onto a functionalised 3-mercaptopropyl trimethoxysilane (MPTMS) silicon substrate, using a removable, silicon wafer with a hydrophobic surface that serves as a "handrail" for the initial nanorods' linear self-assembly. The wire-like structures display a quasi-continuous pattern by thermal annealing of the gold nanorods when the solvent (i.e. water) is evaporated at temperatures rising from 20°C to 140°C. Formation of both single and self-replicating parallel 1D-superstructures consisting of two or even three wires is observed and explained under such conditions.

  20. Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

    Tiriolo, Raffaele [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Rangnekar, Neel [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Zhang, Han [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Shete, Meera [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Bai, Peng [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Nelson, John [Characterization Facility, University of Minnesota, 12 Shepherd Labs, 100 Union St. S.E. Minneapolis MN 55455 USA; Karapetrova, Evguenia [Surface Scattering and Microdiffraction, X-ray Science Division, Argonne National Laboratory, 9700 S. Cass Ave, Building 438-D002 Argonne IL 60439 USA; Macosko, Christopher W. [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Siepmann, Joern Ilja [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Lamanna, Ernesto [Department of Health Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Lavano, Angelo [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Tsapatsis, Michael [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA

    2017-05-08

    A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.

  1. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  2. Influence of silicon dangling bonds on germanium thermal diffusion within SiO{sub 2} glass

    Barba, D.; Martin, F.; Ross, G. G. [INRS Centre for Energy, Materials and Telecommunications, 1650 Boul. Lionel-Boulet, Varennes, Québec J3X 1S2 (Canada); Cai, R. S.; Wang, Y. Q. [The Cultivation Base for State Key Laboratory, Qingdao University, Qingdao 266071 (China); Demarche, J.; Terwagne, G. [LARN, Centre de Recherche en Physique de la Matière et du Rayonnement (PMR), University of Namur (FUNDP), B-5000 Namur (Belgium); Rosei, F. [INRS Centre for Energy, Materials and Telecommunications, 1650 Boul. Lionel-Boulet, Varennes, Québec J3X 1S2 (Canada); Center for Self-Assembled Chemical Structures, McGill University, Montreal, Quebec H3A 2K6 (Canada)

    2014-03-17

    We study the influence of silicon dangling bonds on germanium thermal diffusion within silicon oxide and fused silica substrates heated to high temperatures. By using scanning electron microscopy and Rutherford backscattering spectroscopy, we determine that the lower mobility of Ge found within SiO{sub 2}/Si films can be associated with the presence of unsaturated SiO{sub x} chemical bonds. Comparative measurements obtained by x-ray photoelectron spectroscopy show that 10% of silicon dangling bonds can reduce Ge desorption by 80%. Thus, the decrease of the silicon oxidation state yields a greater thermal stability of Ge inside SiO{sub 2} glass, which could enable to considerably extend the performance of Ge-based devices above 1300 K.

  3. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  4. Role of the bond defect for structural transformations between crystalline and amorphous silicon: A molecular-dynamics study

    Stock, D. M.; Weber, B.; Gaertner, K.

    2000-01-01

    The relation between the bond defect, which is a topological defect, and structural transformations between crystalline and amorphous silicon, is studied by molecular-dynamics simulations. The investigation of 1-keV boron implantation into crystalline silicon proves that the bond defect can also be generated directly by collisional-induced bond switching in addition to its formation by incomplete recombination of primary defects. This supports the assumption that the bond defect may play an important role in the amorphization process of silicon by light ions. The analysis of the interface between (001) silicon and amorphous silicon shows that there are two typical defect configurations at the interface which result from two different orientations of the bond defect with respect to the interface. Thus the bond defect appears to be a characteristic structural feature of the interface. Moreover, annealing results indicate that the bond defect acts as a growth site for interface-mediated crystallization

  5. Morphology and stress at silicon-glass interface in anodic bonding

    Tang, Jiali [Key Laboratory of Pressure Systems and Safety (MOE), School of Mechanical Engineering, East China University of Science and Technology, Shanghai 200237 (China); Cai, Cheng [State Key Laboratory of Chemical Engineering, East China University of Science and Technology, Shanghai (China); Ming, Xiaoxiang [Key Laboratory of Pressure Systems and Safety (MOE), School of Mechanical Engineering, East China University of Science and Technology, Shanghai 200237 (China); State Key Laboratory of Bioreactor Engineering, East China University of Science and Technology, Shanghai 200237 (China); State Key Laboratory of Chemical Engineering, East China University of Science and Technology, Shanghai (China); Yu, Xinhai, E-mail: yxhh@ecust.edu.cn [Key Laboratory of Pressure Systems and Safety (MOE), School of Mechanical Engineering, East China University of Science and Technology, Shanghai 200237 (China); State Key Laboratory of Bioreactor Engineering, East China University of Science and Technology, Shanghai 200237 (China); Zhao, Shuangliang, E-mail: szhao@ecust.edu.cn [State Key Laboratory of Chemical Engineering, East China University of Science and Technology, Shanghai (China); Tu, Shan-Tung [Key Laboratory of Pressure Systems and Safety (MOE), School of Mechanical Engineering, East China University of Science and Technology, Shanghai 200237 (China); Liu, Honglai [State Key Laboratory of Chemical Engineering, East China University of Science and Technology, Shanghai (China)

    2016-11-30

    Highlights: • Amorphous SiO{sub 2} is the most probable silica morphology generated in anodic bonding. • Amorphous SiO{sub 2} thickness at the interface is at least 2 nm for 90 min anodic bonding. • Silicon oxidation rate at the interface is 0.022 nm min{sup −1} from 30 to 90 min. - Abstract: The morphologies and structural details of formed silica at the interface of silicon-glass anodic bonding determine the stress at the interface but they have been rarely clarified. In this study, a miniaturized anodic bonding device was developed and coupled with a Raman spectrometer. The silicon-glass anodic bonding was carried out and the evolution of the stress at the bonding interface was measured in situ by a Raman spectrometer. In addition, large-scale atomistic simulations were conducted by considering the formed silica with different morphologies. The most conceivable silica morphology was identified as the corresponding silicon-glass interfacial stress presents qualitatively agreement with the experimental observation. It was found that amorphous SiO{sub 2} is the silica morphology generated in anodic bonding. The amorphous SiO{sub 2} thickness is at least 2 nm in the case of 90 min anodic bonding at 400 °C with the DC voltage of −1000 V. The combination of experimental and simulation results can ascertain the silicon oxidation reaction rate in anodic bonding process, and under the above-mentioned condition, the reaction rate was estimated as 0.022 nm min{sup −1} from 30 to 90 min.

  6. An experimental and theoretical study of pendellösung fringes in synchrotron section topographs of silicon wafers.

    Partanen, J; Tuomi, T

    1990-01-01

    X-ray section topographs of nearly perfect Czochralski-grown wafers were made with synchrotron radiation having a continuous spectrum. An intensity curve measured from the x-ray film is compared to the calculated curve obtained using the dynamical theory of x-ray diffraction. A computer simulation of the topograph is also presented. A good agreement between theory and experiment is found except in the middle part of the topograph.

  7. Manipulation of polystyrene nanoparticles on a silicon wafer in the peak force tapping mode in water: pH-dependent friction and adhesion force

    Schiwek, Simon; Stark, Robert W., E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de; Dietz, Christian, E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany); Physics of Surfaces, Institute of Materials Science, Technische Universität Darmstadt, Alarich-Weiss-Str. 16, 64287 Darmstadt (Germany); Heim, Lars-Oliver [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany)

    2015-03-14

    The friction force between nanoparticles and a silicon wafer is a crucial parameter for cleaning processes in the semiconductor industry. However, little is known about the pH-dependency of the friction forces and the shear strength at the interface. Here, we push polystyrene nanoparticles, 100 nm in diameter, with the tip of an atomic force microscope and measure the pH-dependency of the friction, adhesion, and normal forces on a silicon substrate covered with a native silicon dioxide layer. The peak force tapping mode was applied to control the vertical force on these particles. We successively increased the applied load until the particles started to move. The main advantage of this technique over single manipulation processes is the achievement of a large number of manipulation events in short time and in a straightforward manner. Geometrical considerations of the interaction forces at the tip-particle interface allowed us to calculate the friction force and shear strength from the applied normal force depending on the pH of an aqueous solution. The results clearly demonstrated that particle removal should be performed with a basic solution at pH 9 because of the low interaction forces between particle and substrate.

  8. Implementation Challenges for Sintered Silicon Carbide Fiber Bonded Ceramic Materials for High Temperature Applications

    Singh, M.

    2011-01-01

    During the last decades, a number of fiber reinforced ceramic composites have been developed and tested for various aerospace and ground based applications. However, a number of challenges still remain slowing the wide scale implementation of these materials. In addition to continuous fiber reinforced composites, other innovative materials have been developed including the fibrous monoliths and sintered fiber bonded ceramics. The sintered silicon carbide fiber bonded ceramics have been fabricated by the hot pressing and sintering of silicon carbide fibers. However, in this system reliable property database as well as various issues related to thermomechanical performance, integration, and fabrication of large and complex shape components has yet to be addressed. In this presentation, thermomechanical properties of sintered silicon carbide fiber bonded ceramics (as fabricated and joined) will be presented. In addition, critical need for manufacturing and integration technologies in successful implementation of these materials will be discussed.

  9. Elastocapillary folding of three dimensional micro-structures using water pumped through the wafer via a silicon nitride tube

    Legrain, A.B.H.; Berenschot, Johan W.; Sanders, Remco G.P.; Ma, Kechun; Tas, Niels Roelof; Abelmann, Leon

    2011-01-01

    In this paper we present the first investigation of a batch method for folding of threedimensional micrometer-sized silicon nitride structures by capillary forces. Silicon nitride tubes have been designed and fabricated using DRIE at the center of the planar origami patterns of the structures. Water

  10. Serial section scanning electron microscopy (S3EM) on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

    2012-01-01

    High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3)EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3) volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3)EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3)EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  11. Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Heinz Horstmann

    Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  12. A simple chemical method for the separation of phosphorus interfering the trace element determinations by neutron activation analysis in high doped silicon wafers

    Wagler, H.; Flachowsky, J.

    1986-01-01

    Neutron activation analysis is one of the most available method for the determination of trace elements, but in the case of P-doped silicon wafers the 32 P-activity interferes the gamma spectrometry. It is not possible to determine the trace elements without chemical manipulations. On the other hand, time consuming chemical separations should be avoided. Therefore, a simple and rapid P-separation method has to be developed, in which the following twelve trace elements should be taken into consideration: Ag, As, Au, Co, Cr, Cu, Fe, Mo, Na, Sb, W, and Zn. After acid oxidative dissolution of the activated sample, P is present as phosphate ion. The phosphate ion is removed by precipitation as BiPO 4 . (author)

  13. Study of gluing and wire bonding for the Belle II Silicon Vertex Detector

    Kang, K.H.; Hara, K.; Higuchi, T.; Hyun, H.J.; Jeon, H.B.; Joo, C.W.; Kah, D.H.; Kim, H.J.; Mibe, T.; Onuki, Y.; Park, H.; Rao, K.K.; Sato, N.; Shimizu, N.; Tanida, K.; Tsuboyama, T.; Uozumi, S.

    2014-01-01

    This paper describes an investigation into gluing and wire bonding for assembling the Silicon Vertex Detector (SVD) for the Belle II experiment at KEK in Japan. Optimizing the gluing of the silicon microstrip sensors, the support frame, and the readout flex cables is important for achieving the required mechanical precision. The wire bonding between the sensors and the readout electronic chips also needs special care to maximize the physics capability of the SVD. The silicon sensors and signal fan out flex circuits (pitch adapters) are glued and connected using wire bonding. We determine that gluing quality is important for achieving good bonding efficiency. The standard deviation in the glue thickness for the best result is measured to be 3.11 μm. Optimal machine parameters for wire bonding are determined to be 70 mW power, 20 gf force, and 20 ms for the pitch adapter and 60 mW power, 20 gf force, and 20 ms for the silicon strip sensors; these parameters provide a pull force of (10.92±0.72) gf. With these settings, 75% of the pitch adapters and 25% of the strip sensors experience the neck-broken type of break

  14. Preservation of atomically clean silicon surfaces in air by contact bonding

    Grey, Francois; Ljungberg, Karin

    1997-01-01

    When two hydrogen-passivated silicon surfaces are placed in contact under cleanroom conditions, a weak bond is formed. Cleaving this bond under ultrahigh vacuum (UHV) conditions, and observing the surfaces with low energy electron diffraction and scanning tunneling microscopy, we find that the or...... reconstruction from oxidation in air, Contact bonding opens the way to novel applications of reconstructed semiconductor surfaces, by preserving their atomic structure intact outside of a UHV chamber. (C) 1997 American Institute of Physics.......When two hydrogen-passivated silicon surfaces are placed in contact under cleanroom conditions, a weak bond is formed. Cleaving this bond under ultrahigh vacuum (UHV) conditions, and observing the surfaces with low energy electron diffraction and scanning tunneling microscopy, we find...... that the ordered atomic structure of the surfaces is protected from oxidation, even after the bonded samples have been in air for weeks. Further, we show that silicon surfaces that have been cleaned and hydrogen-passivated in UHV can be contacted in UHV in a similarly hermetic fashion, protecting the surface...

  15. Effect of light aging on silicone-resin bond strength in maxillofacial prostheses.

    Polyzois, Gregory; Pantopoulos, Antonis; Papadopoulos, Triantafillos; Hatamleh, Muhanad

    2015-04-01

    The aim of this study was to investigate the effect of accelerated light aging on bond strength of a silicone elastomer to three types of denture resin. A total of 60 single lap joint specimens were fabricated with auto-, heat-, and photopolymerized (n = 20) resins. An addition-type silicone elastomer (Episil-E) was bonded to resins treated with the same primer (A330-G). Thirty specimens served as controls and were tested after 24 hours, and the remaining were aged under accelerated exposure to daylight for 546 hours (irradiance 765 W/m(2) ). Lap shear joint tests were performed to evaluate bond strength at 50 mm/min crosshead speed. Two-way ANOVA and Tukey's test were carried out to detect statistical significance (p Accelerated light aging for 546 hours affects the bond strength of an addition-type silicone elastomer to three different denture resins. The bond strength significantly increased after aging for photo- and autopolymerized resins. All the bonds failed adhesively. © 2014 by the American College of Prosthodontists.

  16. Crystallization behavior of polyethylene on silicon wafers in solution casting processes traced by time-resolved measurements of synchrotron grazing-incidence small-angle and wide-angle X-ray scattering

    Sasaki, S; Masunaga, H; Takata, M; Itou, K; Tashiro, K; Okuda, H; Takahara, A

    2009-01-01

    Crystallization behavior of polyethylene (PE) on silicon wafers in solution casting processes has been successfully traced by time-resolved grazing-incidence small-angle and wide-angle X-ray scattering (GISWAXS) measurements utilizing synchrotron radiation. A p-xylene solution of PE kept at ca. 343 K was dropped on a silicon wafer at ca. 298 K. While the p-xylene evaporated naturally from the dropped solution sample, PE chains crystallized to be a thin film. Raman spectral measurements were performed simultaneously with the GISWAXS measurements to evaluate quantitatively the p-xylene the dropped solution contained. Grazing-incidence wide-angle X-ray scattering (GIWAXS) patterns indicated nucleation and crystal growth in the dropped solution and the following as-cast film. GIWAXS and Raman spectral data revealed that crystallization of PE was enhanced after complete evaporation of the p-xylene from the dropped solution. The [110] and [200] directions of the orthorhombic PE crystal became relatively parallel to the wafer surface with time, which implied that the flat-on lamellae with respect to the wafer surface were mainly formed in the as-cast film. On the other hand, grazing-incidence small-angle X-ray scattering (GISAXS) patterns implied formation of isolated lamellae in the dropped solution. The lamellae and amorphous might alternatively be stacked in the preferred direction perpendicular to the wafer surface. The synchrotron GISWAXS experimental method could be applied for kinetic study on hierarchical structure of polymer thin films.

  17. Comprehensive Die Shear Test of Silicon Packages Bonded by Thermocompression of Al Layers with Thin Sn Capping or Insertions

    Shiro Satoh

    2018-04-01

    Full Text Available Thermocompression bonding for wafer-level hermetic packaging was demonstrated at the lowest temperature of 370 to 390 °C ever reported using Al films with thin Sn capping or insertions as bonding layer. For shrinking the chip size of MEMS (micro electro mechanical systems, a smaller size of wafer-level packaging and MEMS–ASIC (application specific integrated circuit integration are of great importance. Metal-based bonding under the temperature of CMOS (complementary metal-oxide-semiconductor backend process is a key technology, and Al is one of the best candidates for bonding metal in terms of CMOS compatibility. In this study, after the thermocompression bonding of two substrates, the shear fracture strength of dies was measured by a bonding tester, and the shear-fractured surfaces were observed by SEM (scanning electron microscope, EDX (energy dispersive X-ray spectrometry, and a surface profiler to clarify where the shear fracture took place. We confirmed two kinds of fracture mode. One mode is Si bulk fracture mode, where the die shear strength is 41.6 to 209 MPa, proportionally depending on the area of Si fracture. The other mode is bonding interface fracture mode, where the die shear strength is 32.8 to 97.4 MPa. Regardless of the fracture modes, the minimum die shear strength is practical for wafer-level MEMS packaging.

  18. Non-silicon substrate bonding mediated by poly(dimethylsiloxane) interfacial coating

    Zhang, Hainan [Department of BioNano Technology, Gachon University, Gyeonggi-do 461-701 (Korea, Republic of); Lee, Nae Yoon, E-mail: nylee@gachon.ac.kr [Department of BioNano Technology, Gachon University, Gyeonggi-do 461-701 (Korea, Republic of); Gachon Medical Research Institute, Gil Medical Center, Inchon 405-760 (Korea, Republic of)

    2015-02-01

    Graphical abstract: Low-molecular-weight PDMS coating on the surfaces of non-silicon substrates such as thermoplastics ensures permanent sealing with a silicone elastomer, PDMS, simply by surface oxidization followed by ambient condition bonding, mediated by a robust siloxane bond formation at the interface. - Highlights: • Non-silicon thermoplastic was bonded with poly(dimethylsiloxane) silicone elastomer. • Low-molecular-weight PDMS interfacial layer was chemically coated on thermoplastic. • Bonding was realized by corona treatment and physical contact under ambient condition. • Bonding is universally applicable regardless of thermoplastic type and property. • Homogeneous PDMS-like microchannel was obtained inside the thermoplastic-PDMS microdevice. - Abstract: In this paper, we introduce a simple and robust strategy for bonding poly(dimethylsiloxane) (PDMS) with various thermoplastic substrates to fabricate a thermoplastic-based closed microfluidic device and examine the feasibility of using the proposed method for realizing plastic–plastic bonding. The proposed bonding strategy was realized by first coating amine functionality on an oxidized thermoplastic surface. Next, the amine-functionalized surface was reacted with a monolayer of low-molecular-weight PDMS, terminated with epoxy functionality, by forming a robust amine-epoxy bond. Both the PDMS-coated thermoplastic and PDMS were then oxidized and permanently assembled at 25 °C under a pressure of 0.1 MPa for 15 min, resulting in PDMS-like surfaces on all four inner walls of the microchannel. Surface characterizations were conducted, including water contact angle measurement, X-ray photoelectron spectroscopy (XPS), and fluorescence measurement, to confirm the successful coating of the thin PDMS layer on the plastic surface, and the bond strength was analyzed by conducting a peel test, burst test, and leakage test. Using the proposed method, we could successfully bond various thermoplastics such

  19. The relationship of microstructure and temperature to fracture mechanics parameters in reaction bonded silicon nitride

    Jennings, H.M.; Dalgleish, B.J.; Pratt, P.L.

    1978-01-01

    The development of physical properties in reaction bonded silicon nitride has been investigated over a range of temperatures and correlated with microstructure. Fracture mechanics parameters, elastic moduli, strength and critical defect size have been determined. The nitrided microstructure is shown to be directly related to these observed properties and these basic relationships can be used to produce material with improved properties. (orig.) [de

  20. A Microsystem Based on Porous Silicon-Glass Anodic Bonding for Gas and Liquid Optical Sensing

    Ivo Rendina

    2006-06-01

    Full Text Available We have recently presented an integrated silicon-glass opto-chemical sensor forlab-on-chip applications, based on porous silicon and anodic bonding technologies. In thiswork, we have optically characterized the sensor response on exposure to vapors of severalorganic compounds by means of reflectivity measurements. The interaction between theporous silicon, which acts as transducer layer, and the organic vapors fluxed into the glasssealed microchamber, is preserved by the fabrication process, resulting in optical pathincrease, due to the capillary condensation of the vapors into the pores. Using theBruggemann theory, we have calculated the filled pores volume for each substance. Thesensor dynamic has been described by time-resolved measurements: due to the analysischamber miniaturization, the response time is only of 2 s. All these results have beencompared with data acquired on the same PSi structure before the anodic bonding process.

  1. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  2. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers.

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K(alpha)0.28 keV and Al K(alpha)1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K(alpha) (approximately 6 nm rms) is significantly larger than approximately 1 nm at Al K(alpha). This can be explained by different coherent lengths at two energies.

  3. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y.; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K{alpha}0.28 keV and Al K{alpha}1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K{alpha} ({approx}6 nm rms) is significantly larger than {approx}1 nm at Al K{alpha}. This can be explained by different coherent lengths at two energies.

  4. Characterization of the first double-sided 3D radiation sensors fabricated at FBK on 6-inch silicon wafers

    Sultan, D.M.S.; Mendicino, R.; Betta, G.-F. Dalla; Boscardin, M.; Ronchin, S.; Zorzi, N.

    2015-01-01

    Following 3D pixel sensor production for the ATLAS Insertable B-Layer, Fondazione Bruno Kessler (FBK) fabrication facility has recently been upgraded to process 6-inch wafers. In 2014, a test batch was fabricated to check for possible issues relevant to this upgrade. While maintaining a double-sided fabrication technology, some process modifications have been investigated. We report here on the technology and the design of this batch, and present selected results from the electrical characterization of sensors and test structures. Notably, the breakdown voltage is shown to exceed 200 V before irradiation, much higher than in earlier productions, demonstrating robustness in terms of radiation hardness for forthcoming productions aimed at High Luminosity LHC upgrades

  5. Effects of bond primers on bending strength and bonding of glass fibers in fiber-embedded maxillofacial silicone prostheses.

    Hatamleh, Muhanad M; Watts, David C

    2011-02-01

    To evaluate the effect of three commonly used bond primers on the bending strength of glass fibers and their bond strength to maxillofacial silicone elastomer after 360 hours of accelerated daylight aging. Eighty specimens were fabricated by embedding resin-impregnated fiber bundles (1.5-mm diameter, 20-mm long) into maxillofacial silicone elastomer M511 (Cosmesil). Twenty fiber bundles served as control and did not receive surface treatment with primers, whereas the remaining 60 fibers were treated with three primers (n = 20): G611 (Principality Medical), A-304 (Factor II), and A-330-Gold (Factor II). Forty specimens were dry stored at room temperature (23 ± 1°C) for 24 hours, and the remaining specimens were aged using an environmental chamber under accelerated exposure to artificial daylight for 360 hours. The aging cycle included continuous exposure to quartz-filtered visible daylight (irradiance 760 W/m(2) ) under an alternating weathering cycle (wet for 18 minutes, dry for 102 minutes). Pull-out tests were performed to evaluate bond strength between fiber bundles and silicone using a universal testing machine at 1 mm/min crosshead speed. A 3-point bending test was performed to evaluate the bending strength of the fiber bundles. One-way Analysis of Variance (ANOVA), Bonferroni post hoc test, and an independent t-test were carried out to detect statistical significances (p accelerated daylight aging. Treatment with primer and accelerated daylight aging increased bending strength of glass fibers. © 2011 by The American College of Prosthodontists.

  6. Silicon on insulator self-aligned transistors

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  7. Steel bonded dense silicon nitride compositions and method for their fabrication

    Landingham, Richard L.; Shell, Thomas E.

    1987-01-01

    A two-stage bonding technique for bonding high density silicon nitride and other ceramic materials to stainless steel and other hard metals, and multilayered ceramic-metal composites prepared by the technique are disclosed. The technique involves initially slurry coating a surface of the ceramic material at about 1500.degree. C. in a vacuum with a refractory material and the stainless steel is then pressure bonded to the metallic coated surface by brazing it with nickel-copper-silver or nickel-copper-manganese alloys at a temperature in the range of about 850.degree. to 950.degree. C. in a vacuum. The two-stage bonding technique minimizes the temperature-expansion mismatch between the dissimilar materials.

  8. Simultaneous On-State Voltage and Bond-Wire Resistance Monitoring of Silicon Carbide MOSFETs

    Baker, Nick; Luo, Haoze; Iannuzzo, Francesco

    2017-01-01

    the voltage between the kelvin-source and power-source can be used to specifically monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A Silicon Carbide Metal......-Oxide-Semiconductor-Field-Effect Transistors (MOSFETs), it is shown that there are opposing trends in the evolution of the on-state resistances of both the bond-wires and the MOSFET die. In summary, after 50,000 temperature cycles, the resistance of the bond-wires increased by up to 2 mΩ, while the on-state resistance of the MOSFET dies...... decreased by approximately 1 mΩ. The conventional failure precursor (monitoring a single forward voltage) cannot distinguish between semiconductor die or bond-wire degradation. Therefore, the ability to monitor both these parameters due to the presence of an auxiliary-source terminal can provide more...

  9. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  10. Electrodeposition of three-dimensionally assembled platinum spheres on a gold-coated silicon wafer, and its application to nonenzymatic sensing of glucose

    Roh, Seongjin; Kim, Jongwon

    2015-01-01

    We report on a method of single-step electrodeposition of three-dimensionally (3-D) assembled Pt spheres on a gold-coated silicon wafer. The 3-D interconnected Pt spheres could be electrodeposited by applying a negative potential (−0.8 V, vs. Ag/AgCl) in neutral electrolytes containing KClO 4 . The application of such a negative potential is not possible in acidic solutions because of the formation of hydrogen. Scanning electron microscopy revealed that the seed Pt particles first grew to a certain size, and then form Pt spheres interconnected in multiple layers. The resulting 3-D assembled Pt sphere structures warrants a high surface area, and this property was utilized for the selective and sensitive amperometric determination of glucose at a working potential of 0.4 V (vs. Ag/AgCl), at near neutral pH values and in the presence of 0.1 M chloride. This straightforward method for the fabrication of 3-D assembled Pt sphere structures offers new opportunities for electroanalytical and electrocatalytic sensing based on porous Pt surfaces (author)

  11. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  12. Effect of hot isostatic pressing on reaction-bonded silicon nitride

    Watson, G. K.; Moore, T. J.; Millard, M. L.

    1984-01-01

    Specimens of nearly theoretical density have been obtained through the isostatic hot pressing of reaction-bonded silicon nitride under 138 MPa of pressure for two hours at 1850, 1950, and 2050 C. An amorphous phase that is introduced by the hot isostatic pressing partly accounts for the fact that while room temperature flexural strength more than doubles, the 1200 C flexural strength increases significantly only after pressing at 2050 C.

  13. Unanticipated C=C bonds in covalent monolayers on silicon revealed by NEXAFS.

    Lee, Michael V; Lee, Jonathan R I; Brehmer, Daniel E; Linford, Matthew R; Willey, Trevor M

    2010-02-02

    Interfaces are crucial to material properties. In the case of covalent organic monolayers on silicon, molecular structure at the interface controls the self-assembly of the monolayers, which in turn influences the optical properties and electrical transport. These properties intrinsically affect their application in biology, tribology, optics, and electronics. We use near-edge X-ray absorption fine structure spectroscopy to show that the most basic covalent monolayers formed from 1-alkenes on silicon retain a double bond in one-fifth to two-fifths of the resultant molecules. Unsaturation in the predominantly saturated monolayers will perturb the regular order and affect the dependent properties. The presence of unsaturation in monolayers produced by two different methods also prompts the re-evaluation of other radical-based mechanisms for forming covalent monolayers on silicon.

  14. In situ metalation of free base phthalocyanine covalently bonded to silicon surfaces

    Fabio Lupo

    2014-11-01

    Full Text Available Free 4-undecenoxyphthalocyanine molecules were covalently bonded to Si(100 and porous silicon through thermic hydrosilylation of the terminal double bonds of the undecenyl chains. The success of the anchoring strategy on both surfaces was demonstrated by the combination of X-ray photoelectron spectroscopy with control experiments performed adopting the commercially available 2,3,9,10,16,17,23,24-octakis(octyloxy-29H,31H-phthalocyanine, which is not suited for silicon anchoring. Moreover, the study of the shape of the XPS N 1s band gave relevant information on the interactions occurring between the anchored molecules and the substrates. The spectra suggest that the phthalocyanine ring interacts significantly with the flat Si surface, whilst ring–surface interactions are less relevant on porous Si. The surface-bonded molecules were then metalated in situ with Co by using wet chemistry. The efficiency of the metalation process was evaluated by XPS measurements and, in particular, on porous silicon, the complexation of cobalt was confirmed by the disappearance in the FTIR spectra of the band at 3290 cm−1 due to –NH stretches. Finally, XPS results revealed that the different surface–phthalocyanine interactions observed for flat and porous substrates affect the efficiency of the in situ metalation process.

  15. Transistors using crystalline silicon devices on glass

    McCarthy, Anthony M.

    1995-01-01

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

  16. Development of new assembly techniques for a silicon micro-vertex detector unit using the flip-chip bonding method

    Saitoh, Y.; Takeuchi, H.; Mandai, M.; Kanazawa, H.; Yamanaka, J.; Miyahara, S.; Kamiya, M.; Fujita, Y.; Higashi, Y.; Ikeda, H.; Ikeda, M.; Koike, S.; Matsuda, T.; Ozaki, H.; Tanaka, M.; Tsuboyama, T.; Avrillon, S.; Okuno, S.; Haba, J.; Hanai, H.; Mori, S.; Yusa, K.; Fukunaga, C.

    1994-01-01

    Full-size models of a detector unit for a silicon micro-vertex detector were built for the KEK B factory. The Flip-Chip Bonding (FCB) method using a new type anisotropic conductive film was examined. The structure using the FCB method successfully provides a new architecture for the silicon micro-vertex detector unit. (orig.)

  17. Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

    Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

    2003-06-01

    We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

  18. Research on the Effects of Process Parameters on Surface Roughness in Wet-Activated Silicon Direct Bonding Base on Orthogonal Experiments

    Lei NIE

    2015-11-01

    Full Text Available Surface roughness is a very important index in silicon direct bonding and it is affected by processing parameters in the wet-activated process. These parameters include the concentration of activation solution, holding time and treatment temperature. The effects of these parameters were investigated by means of orthogonal experiments. In order to analyze the wafer roughness more accurately, the bear ratio of the surface was used as the evaluation index. From the results of the experiments, it could be concluded that the concentration of the activation solution affected the roughness directly and the higher the concentration, the lower the roughness. Holding time did not affect the roughness as acutely as that of the concentration, but a reduced activation time decreased the roughness perceptibly. It was also discovered that the treatment temperature had a weak correlation with the surface roughness. Based on these conclusions, the parameters of concentration, temperature and holding time were optimized respectively as NH4OH:H2O2=1:1 (without water, 70 °C and 5 min. The results of bonding experiments proved the validity of the conclusions of orthogonal experiments.DOI: http://dx.doi.org/10.5755/j01.ms.21.4.9711

  19. A bonding study toward the quality assurance of Belle-II silicon vertex detector modules

    Kang, K.H.; Jeon, H.B.; Park, H.; Uozumi, S.; Adamczyk, K.; Aihara, H.; Angelini, C.; Aziz, T.; Babu, V.; Bacher, S.; Bahinipati, S.; Barberio, E.; Baroncelli, T.; Basith, A.K.; Batignani, G.; Bauer, A.; Behera, P.K.; Bergauer, T.; Bettarini, S.; Bhuyan, B.

    2016-01-01

    A silicon vertex detector (SVD) for the Belle-II experiment comprises four layers of double-sided silicon strip detectors (DSSDs), assembled in a ladder-like structure. Each ladder module of the outermost SVD layer has four rectangular and one trapezoidal DSSDs supported by two carbon-fiber ribs. In order to achieve a good signal-to-noise ratio and minimize material budget, a novel chip-on-sensor “Origami” method has been employed for the three rectangular sensors that are sandwiched between the backward rectangular and forward (slanted) trapezoidal sensors. This paper describes the bonding procedures developed for making electrical connections between sensors and signal fan-out flex circuits (i.e., pitch adapters), and between pitch adapters and readout chips as well as the results in terms of the achieved bonding quality and pull force. - Highlights: • Gluing and wire binding for Belle-II SVD are studied. • Gluing robot and Origami module are used. • QA are satisfied in terms of the achieved bonding throughput and the pull force. • Result will be applied for L6 ladder assembly.

  20. A bonding study toward the quality assurance of Belle-II silicon vertex detector modules

    Kang, K.H.; Jeon, H.B. [RSRI, Department of Physics, Kyungpook National University, Daegu 702-701 (Korea, Republic of); Park, H., E-mail: sunshine@knu.ac.kr [RSRI, Department of Physics, Kyungpook National University, Daegu 702-701 (Korea, Republic of); Uozumi, S. [RSRI, Department of Physics, Kyungpook National University, Daegu 702-701 (Korea, Republic of); Adamczyk, K. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Aihara, H. [Department of Physics, University of Tokyo, Tokyo 113-0033 (Japan); Angelini, C. [Dipartimento di Fisica, Universitá di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Aziz, T.; Babu, V. [Tata Institute of Fundamental Research, Mumbai 400005 (India); Bacher, S. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Bahinipati, S. [Indian Institute of Technology Bhubaneswar, Satya Nagar (India); Barberio, E.; Baroncelli, T. [School of Physics, University of Melbourne, Melbourne, Victoria 3010 (Australia); Basith, A.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Batignani, G. [Dipartimento di Fisica, Universitá di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bauer, A. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Behera, P.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Bergauer, T. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Bettarini, S. [Dipartimento di Fisica, Universitá di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bhuyan, B. [Indian Institute of Technology Guwahati, Assam 781039 (India); and others

    2016-09-21

    A silicon vertex detector (SVD) for the Belle-II experiment comprises four layers of double-sided silicon strip detectors (DSSDs), assembled in a ladder-like structure. Each ladder module of the outermost SVD layer has four rectangular and one trapezoidal DSSDs supported by two carbon-fiber ribs. In order to achieve a good signal-to-noise ratio and minimize material budget, a novel chip-on-sensor “Origami” method has been employed for the three rectangular sensors that are sandwiched between the backward rectangular and forward (slanted) trapezoidal sensors. This paper describes the bonding procedures developed for making electrical connections between sensors and signal fan-out flex circuits (i.e., pitch adapters), and between pitch adapters and readout chips as well as the results in terms of the achieved bonding quality and pull force. - Highlights: • Gluing and wire binding for Belle-II SVD are studied. • Gluing robot and Origami module are used. • QA are satisfied in terms of the achieved bonding throughput and the pull force. • Result will be applied for L6 ladder assembly.

  1. Bondability of processed glass wafers

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  2. Annealing effects on recombinative activity of nickel at direct silicon bonded interface

    Kojima, Takuto, E-mail: tkojima@toyota-ti.ac.jp; Ohshita, Yoshio; Yamaguchi, Masafumi [Toyota Technological Institute, 2-12-1 Hisakata, Tempaku-ku, Nagoya, 468-8511 (Japan)

    2015-09-15

    By performing capacitance transient analyses, the recombination activity at a (110)/(100) direct silicon bonded (DSB) interface contaminated with nickel diffused at different temperatures, as a model of grain boundaries in multicrystalline silicon, was studied. The trap level depth from the valence band, trap density of states, and hole capture cross section peaked at an annealing temperature of 300 °C. At temperatures ⩾400 °C, the hole capture cross section increased with temperature, but the density of states remained unchanged. Further, synchrotron-based X-ray analyses, microprobe X-ray fluorescence (μ-XRF), and X-ray absorption near edge structure (XANES) analyses were performed. The analysis results indicated that the chemical phase after the sample was annealed at 200 °C was a mixture of NiO and NiSi{sub 2}.

  3. Surface/subsurface observation and removal mechanisms of ground reaction bonded silicon carbide

    Yao, Wang; Zhang, Yu-Min; Han, Jie-cai; Zhang, Yun-long; Zhang, Jian-han; Zhou, Yu-feng; Han, Yuan-yuan

    2006-01-01

    Reaction Bonded Silicon Carbide (RBSiC) has long been recognized as a promising material for optical applications because of its unique combination of favorable properties and low-cost fabrication. Grinding of silicon carbide is difficult because of its high hardness and brittleness. Grinding often induces surface and subsurface damage, residual stress and other types of damage, which have great influence on the ceramic components for optical application. In this paper, surface integrity, subsurface damage and material removal mechanisms of RBSiC ground using diamond grinding wheel on creep-feed surface grinding machine are investigated. The surface and subsurface are studied with scanning electron microscopy (SEM) and optical microscopy. The effects of grinding conditions on surface and subsurface damage are discussed. This research links the surface roughness, surface and subsurface cracks to grinding parameters and provides valuable insights into the material removal mechanism and the dependence of grind induced damage on grinding conditions.

  4. Annealing effects on recombinative activity of nickel at direct silicon bonded interface

    Kojima, Takuto; Ohshita, Yoshio; Yamaguchi, Masafumi

    2015-01-01

    By performing capacitance transient analyses, the recombination activity at a (110)/(100) direct silicon bonded (DSB) interface contaminated with nickel diffused at different temperatures, as a model of grain boundaries in multicrystalline silicon, was studied. The trap level depth from the valence band, trap density of states, and hole capture cross section peaked at an annealing temperature of 300 °C. At temperatures ⩾400 °C, the hole capture cross section increased with temperature, but the density of states remained unchanged. Further, synchrotron-based X-ray analyses, microprobe X-ray fluorescence (μ-XRF), and X-ray absorption near edge structure (XANES) analyses were performed. The analysis results indicated that the chemical phase after the sample was annealed at 200 °C was a mixture of NiO and NiSi 2

  5. Interface bonding in silicon oxide nanocontacts: interaction potentials and force measurements

    Wierez-Kien, M.; Craciun, A. D.; Pinon, A. V.; Le Roux, S.; Gallani, J. L.; Rastei, M. V.

    2018-04-01

    The interface bonding between two silicon-oxide nanoscale surfaces has been studied as a function of atomic nature and size of contacting asperities. The binding forces obtained using various interaction potentials are compared with experimental force curves measured in vacuum with an atomic force microscope. In the limit of small nanocontacts (typically contact area which is altered by stretching speeds. The mean unbinding force is found to decrease as the contact spends time in the attractive regime. This contact weakening is featured by a negative aging coefficient which broadens and shifts the thermal-induced force distribution at low stretching speeds.

  6. Processing development for ceramic structural components: the influence of a presintering of silicon on the final properties of reaction bonded silicon nitride. Final technical report

    1982-03-01

    The influence of a presintering of silicon on the final properties of reaction bonded silicon nitride has been studied using scanning electron and optical microscopy, x-ray diffraction analysis, 4 pt. bend test, and mecury intrusion porosimetry. It has been shown that presintering at 1050/sup 0/C will not affect the final nitrided properties. At 1200/sup 0/C, the oxide layer is removed, promoting the formation of B-phase silicon nitride. Presintering at 1200/sup 0/C also results in compact weight loss due to the volatilization of silicon, and the formation of large pores which severely reduce nitrided strength. The development of the structure of sintered silicon compacts appears to involve a temperature gradient, with greater sintering observed near the surface.

  7. Simultaneous On-State Voltage and Bond-Wire Resistance Monitoring of Silicon Carbide MOSFETs

    Nick Baker

    2017-03-01

    Full Text Available In fast switching power semiconductors, the use of a fourth terminal to provide the reference potential for the gate signal—known as a kelvin-source terminal—is becoming common. The introduction of this terminal presents opportunities for condition monitoring systems. This article demonstrates how the voltage between the kelvin-source and power-source can be used to specifically monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A Silicon Carbide Metal-Oxide-Semiconductor-Field-Effect Transistors (MOSFETs, it is shown that there are opposing trends in the evolution of the on-state resistances of both the bond-wires and the MOSFET die. In summary, after 50,000 temperature cycles, the resistance of the bond-wires increased by up to 2 mΩ, while the on-state resistance of the MOSFET dies decreased by approximately 1 mΩ. The conventional failure precursor (monitoring a single forward voltage cannot distinguish between semiconductor die or bond-wire degradation. Therefore, the ability to monitor both these parameters due to the presence of an auxiliary-source terminal can provide more detailed information regarding the aging process of a device.

  8. Design and implementation of a novel conical electrode for fast anodic bonding

    Yang, Chii-Rong; Chang, Long-Yin; Wu, Jim-Wei

    2014-01-01

    Anodic bonding is a frequently used nonintermediate wafer-bonding technique for use in MEMS. However, it has a minimum bonding time for a 4 in silicon/glass wafer that is generally limited to the order of several minutes because of the gas-trapping problem that occurs in the bonded interface when a conventional bonding electrode is used. Therefore, the purpose of this study was to develop a novel conical bonding electrode, which shortens the bonding time and solves the gas-trapping problem of the bonded interface. The 4 in silicon/glass wafers fitted with the proposed electrode exhibited a bonding ratio of 99.89% and an average bonding strength of around 15 MPa, which was attained within 15 s, at a bonding voltage of 900 V and a bonding temperature of 400 °C. A comprehensive series of experiments was performed to validate the excellent bonding performance of the proposed conical electrode. (paper)

  9. Direct bonding of ALD Al2O3 to silicon nitride thin films

    Laganà, Simone; Mikkelsen, E. K.; Marie, Rodolphe

    2017-01-01

    microscopy (TEM) by improving low temperature annealing bonding strength when using atomic layer deposition of aluminum oxide. We have investigated and characterized bonding of Al2O3-SixNy (low stress silicon rich nitride) and Al2O3-Si3N4 (stoichiometric nitride) thin films annealed from room temperature up......O3 can be bonded to. Preliminary tests demonstrating a well-defined nanochannel system with-100 nm high channels successfully bonded and tests against leaks using optical fluorescence technique and transmission electron microscopy (TEM) characterization of liquid samples are also reported. Moreover...

  10. The Covalent Binding of Photosensitive Dyes to Monocrystalline Silicon Surface and Their Spectral Response

    郭志新; 郝纪祥; 张祖训; 曹子祥

    1993-01-01

    A chemical method is proposed to bond photo-sensitive dyes directly to the surface of polished monocrystalline silicon. A methincyanine dye and a trimethincyanine dye have been bonded covalently onto silicon surface through Si—N bond, which are characterized by XPS technique and laser Raman spectra. Photovoltaic effect has been observed with the In/dye/n-Si sandwich devices composed of the dye-bonded n-Si wafers. Significant spectral response shows the characteristic absorptance maxima of the bonded dyes.

  11. Fabrication and characterization of reaction bonded silicon carbide/carbon nanotube composites

    Thostenson, Erik T; Karandikar, Prashant G; Chou, T.-W.

    2005-01-01

    Carbon nanotubes have generated considerable excitement in the scientific and engineering communities because of their exceptional mechanical and physical properties observed at the nanoscale. Carbon nanotubes possess exceptionally high stiffness and strength combined with high electrical and thermal conductivities. These novel material properties have stimulated considerable research in the development of nanotube-reinforced composites (Thostenson et al 2001 Compos. Sci. Technol. 61 1899, Thostenson et al 2005 Compos. Sci. Technol. 65 491). In this research, novel reaction bonded silicon carbide nanocomposites were fabricated using melt infiltration of silicon. A series of multi-walled carbon nanotube-reinforced ceramic matrix composites (NT-CMCs) were fabricated and the structure and properties were characterized. Here we show that carbon nanotubes are present in the as-fabricated NT-CMCs after reaction bonding at temperatures above 1400 deg. C. Characterization results reveal that a very small volume content of carbon nanotubes, as low as 0.3 volume %, results in a 75% reduction in electrical resistivity of the ceramic composites. A 96% decrease in electrical resistivity was observed for the ceramics with the highest nanotube volume fraction of 2.1%

  12. Doping of silicon by carbon during laser ablation process

    Raciukaitis, G.; Brikas, M.; Kazlauskiene, V.; Miskinis, J.

    2007-04-01

    Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

  13. Doping of silicon by carbon during laser ablation process

    Raciukaitis, G; Brikas, M; Kazlauskiene, V; Miskinis, J

    2007-01-01

    Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting

  14. Comparison of aggregation behaviors between ionic liquid-type imidazolium gemini surfactant [C12-4-C12im]Br2 and its monomer [C12mim]Br on silicon wafer.

    Ao, Mingqi; Xu, Guiying; Pang, Jinyu; Zhao, Taotao

    2009-09-01

    The aggregation of ionic liquid-type imidazolium gemini surfactant [C(12)-4-C(12)im]Br(2) on silicon wafer, which is compared with its monomer [C(12)mim]Br, have been studied. AFM morphology images and contact angle measurements suggest that the aggregations of [C(12)-4-C(12)im]Br(2) and [C(12)mim]Br on silicon wafer follow different mechanisms. Below the critical surface aggregation concentrations (CSAC), both surfactant molecules are adsorbed with their hydrophobic tails facing the air. But above the CSAC, [C(12)-4-C(12)im]Br(2) molecules finally form a bilayer structure with hydrophilic head groups facing the air, whereas [C(12)mim]Br molecules form a multilayer structure, and with increasing its concentration, the layer numbers increase with the hydrophobic chains and hydrophilic head groups facing the air by turns. Besides, the watery wettability of [C(12)-4-C(12)im]Br(2)-treated silica surface is lower than that of [C(12)mim]Br at the concentration of 5.0 cmc, and the infrared spectroscopy suggests that the poorer watery wettability of [C(12)-4-C(12)im]Br(2) may be relative to the less-ordered packing of methylene chains inside the aggregate. These different aggregation behaviors for the two surfactants ascribe to the different molecular structures and electrostatic interactions. This work would have certain theoretical guidance meaning on the modification of solid surface.

  15. Experimental investigation on material migration phenomena in micro-EDM of reaction-bonded silicon carbide

    Liew, Pay Jun [Department of Mechanical Systems and Design, Tohoku University, Aramaki Aoba 6-6-01, Aoba-ku, Sendai, 980-8579 (Japan); Manufacturing Process Department, Faculty of Manufacturing Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100, Durian Tunggal, Melaka (Malaysia); Yan, Jiwang, E-mail: yan@mech.keio.ac.jp [Department of Mechanical Engineering, Faculty of Science and Technology, Keio University, Hiyoshi 3-14-1, Kohoku-ku, Yokohama, 223-8522 (Japan); Kuriyagawa, Tsunemoto [Department of Mechanical Systems and Design, Tohoku University, Aramaki Aoba 6-6-01, Aoba-ku, Sendai, 980-8579 (Japan)

    2013-07-01

    Material migration between tool electrode and workpiece material in micro electrical discharge machining of reaction-bonded silicon carbide was experimentally investigated. The microstructural changes of workpiece and tungsten tool electrode were examined using scanning electron microscopy, cross sectional transmission electron microscopy and energy dispersive X-ray under various voltage, capacitance and carbon nanofibre concentration in the dielectric fluid. Results show that tungsten is deposited intensively inside the discharge-induced craters on the RB-SiC surface as amorphous structure forming micro particles, and on flat surface region as a thin interdiffusion layer of poly-crystalline structure. Deposition of carbon element on tool electrode was detected, indicating possible material migration to the tool electrode from workpiece material, carbon nanofibres and dielectric oil. Material deposition rate was found to be strongly affected by workpiece surface roughness, voltage and capacitance of the electrical discharge circuit. Carbon nanofibre addition in the dielectric at a suitable concentration significantly reduced the material deposition rate.

  16. Experimental investigation on material migration phenomena in micro-EDM of reaction-bonded silicon carbide

    Liew, Pay Jun; Yan, Jiwang; Kuriyagawa, Tsunemoto

    2013-01-01

    Material migration between tool electrode and workpiece material in micro electrical discharge machining of reaction-bonded silicon carbide was experimentally investigated. The microstructural changes of workpiece and tungsten tool electrode were examined using scanning electron microscopy, cross sectional transmission electron microscopy and energy dispersive X-ray under various voltage, capacitance and carbon nanofibre concentration in the dielectric fluid. Results show that tungsten is deposited intensively inside the discharge-induced craters on the RB-SiC surface as amorphous structure forming micro particles, and on flat surface region as a thin interdiffusion layer of poly-crystalline structure. Deposition of carbon element on tool electrode was detected, indicating possible material migration to the tool electrode from workpiece material, carbon nanofibres and dielectric oil. Material deposition rate was found to be strongly affected by workpiece surface roughness, voltage and capacitance of the electrical discharge circuit. Carbon nanofibre addition in the dielectric at a suitable concentration significantly reduced the material deposition rate.

  17. Effect of loading rate on dynamic fracture of reaction bonded silicon nitride

    Liaw, B. M.; Kobayashi, A. S.; Emery, A. F.

    1986-01-01

    Wedge-loaded, modified tapered double cantilever beam (WL-MTDCB) specimens under impact loading were used to determine the room temperature dynamic fracture response of reaction bonded silicon nitride (RBSN). The crack extension history, with the exception of the terminal phase, was similar to that obtained under static loading. Like its static counterpart, a distinct crack acceleration phase, which was not observed in dynamic fracture of steel and brittle polymers, was noted. Unlike its static counterpart, the crack continued to propagate at nearly its terminal velocity under a low dynamic stress intensity factor during the terminal phase of crack propagation. These and previously obtained results for glass and RBSN show that dynamic crack arrest under a positive dynamic stress intensity factor is unlikely in static and impact loaded structural ceramics.

  18. Thermal shock behaviour of mullite-bonded porous silicon carbide ceramics with yttria addition

    Ding Shuqiang; Zeng Yuping; Jiang Dongliang

    2007-01-01

    Thermal shock resistance of mullite (3Al 2 O 3 · 2SiO 2 )-bonded porous silicon carbide (SiC) ceramics with 3.0 wt% yttria (Y 2 O 3 ) addition was evaluated by a water-quenching technique. The thermal shock damage was investigated as a function of the quenching temperature, quenching cycles and specimen thickness. The residual flexural strength of the quenched specimens decreases with increasing quenching temperature and specimen thickness due to the larger thermal stress caused by thermal shock. However, quenching cycles at the temperature difference of 1200 deg. C have no effect on the residual strength since the same thermal stress was produced in repeated thermal shock processes. The good thermal shock damage resistance of the specimens is contributed mainly by the low strength and moderate elastic modulus. Moreover, the pores prevent the continuous propagation of cracks and alleviate further damage

  19. Formation of porous surface layers in reaction bonded silicon nitride during processing

    Shaw, N. J.; Glasgow, T. K.

    1979-01-01

    Microstructural examination of reaction bonded silicon nitride (RBSN) has shown that there is often a region adjacent to the as-nitrided surfaces that is even more porous than the interior of this already quite porous material. Because this layer of large porosity is considered detrimental to both the strength and oxidation resistance of RBSN, a study was undertaken to determine if its formation could be prevented during processing. All test bars studied were made from a single batch of Si powder which was milled for 4 hours in heptane in a vibratory mill using high density alumina cylinders as the grinding media. After air drying the powder, bars were compacted in a single acting die and hydropressed.

  20. Structural, dynamical, electronic, and bonding properties of laser-heated silicon: An ab initio molecular-dynamics study

    Silvestrelli, P.-L.; Alavi, A.; Parrinello, M.; Frenkel, D.

    1997-01-01

    The method of ab initio molecular dynamics, based on finite-temperature density-functional theory, is used to simulate laser heating of crystalline silicon. We found that a high concentration of excited electrons dramatically weakens the covalent bonding. As a result the system undergoes a melting

  1. The uses of Man-Made diamond in wafering applications

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  2. SOI silicon on glass for optical MEMS

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  3. Doping of silicon with carbon during laser ablation process

    Račiukaitis, G.; Brikas, M.; Kazlauskienė, V.; Miškinis, J.

    2006-12-01

    The effect of laser ablation on properties of remaining material in silicon was investigated. It was found that laser cutting of wafers in the air induced the doping of silicon with carbon. The effect was more distinct when using higher laser power or UV radiation. Carbon ions created bonds with silicon atoms in the depth of the material. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion to clarify its depth profile in silicon was performed. Photochemical reactions of such type changed the structure of material and could be the reason of the reduced machining quality. The controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

  4. MEMS silicon-based micro-evaporator with diamond-shaped fins

    Mihailovic, M.; Rops, C.; Creemer, J.F.; Sarro, P.M.

    2010-01-01

    A new design of micro-evaporators, with 45 channels (100 μm deep) and diamond-shaped fins (40μm wide, 160μm long, 20μm separation), is fabricated by anodic bonding of silicon and glass wafers, in a five masks process. This new design improves stability of the working conditions, and has a localized

  5. GaN microring waveguide resonators bonded to silicon substrate by a two-step polymer process.

    Hashida, Ryohei; Sasaki, Takashi; Hane, Kazuhiro

    2018-03-20

    Using a polymer bonding technique, GaN microring waveguide resonators were fabricated on a Si substrate for future hybrid integration of GaN and Si photonic devices. The designed GaN microring consisted of a rib waveguide having a core of 510 nm in thickness, 1000 nm in width, and a clad of 240 nm in thickness. A GaN crystalline layer of 1000 nm in thickness was grown on a Si(111) substrate by metal organic chemical vapor deposition using a buffer layer of 300 nm in thickness for the compensation of lattice constant mismatch between GaN and Si crystals. The GaN/Si wafer was bonded to a Si(100) wafer by a two-step polymer process to prevent it from trapping air bubbles. The bonded GaN layer was thinned from the backside by a fast atom beam etching to remove the buffer layer and to generate the rib waveguides. The transmission characteristics of the GaN microring waveguide resonators were measured. The losses of the straight waveguides were measured to be 4.0±1.7  dB/mm around a wavelength of 1.55 μm. The microring radii ranged from 30 to 60 μm, where the measured free-spectral ranges varied from 2.58 to 5.30 nm. The quality factors of the microring waveguide resonators were from 1710 to 2820.

  6. Room temperature Cu-Cu direct bonding using surface activated bonding method

    Kim, T.H.; Howlader, M.M.R.; Itoh, T.; Suga, T.

    2003-01-01

    Thin copper (Cu) films of 80 nm thickness deposited on a diffusion barrier layered 8 in. silicon wafers were directly bonded at room temperature using the surface activated bonding method. A low energy Ar ion beam of 40-100 eV was used to activate the Cu surface prior to bonding. Contacting two surface-activated wafers enables successful Cu-Cu direct bonding. The bonding process was carried out under an ultrahigh vacuum condition. No thermal annealing was required to increase the bonding strength since the bonded interface was strong enough at room temperature. The chemical constitution of the Cu surface was examined by Auger electron spectroscope. It was observed that carbon-based contaminations and native oxides on copper surface were effectively removed by Ar ion beam irradiation for 60 s without any wet cleaning processes. An atomic force microscope study shows that the Ar ion beam process causes no surface roughness degradation. Tensile test results show that high bonding strength equivalent to bulk material is achieved at room temperature. The cross-sectional transmission electron microscope observations reveal the presence of void-free bonding interface without intermediate layer at the bonded Cu surfaces

  7. Wafer-level manufacturing technology of glass microlenses

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  8. Interfacial bonding and friction in silicon carbide (filament)-reinforced ceramic- and glass-matrix composites

    Bright, J.D.; Shetty, D.K.

    1989-01-01

    This paper reports interfacial shear strength and interfacial sliding friction stress assessed in unidirectional SiC-filament-reinforced reaction-bonded silicon nitride (RBSN) and borosilicate glass composites and 0/90 cross-ply reinforced borosilicate glass composite using a fiber pushout test technique. The interface debonding load and the maximum sliding friction load were measured for varying lengths of the embedded fibers by continuously monitoring the load during debonding and pushout of single fibers in finite-thickness specimens. The dependences of the debonding load and the maximum sliding friction load on the initial embedded lengths of the fibers were in agreement with nonlinear shear-lag models. An iterative regression procedure was used to evaluate the interfacial properties, shear debond strength (τ d ), and sliding friction stress (τ f ), from the embedded fiber length dependences of the debonding load and the maximum frictional sliding load, respectively. The shear-lag model and the analysis of sliding friction permit explicit evaluation of a coefficient of sliding friction (μ) and a residual compressive stress on the interface (σ 0 ). The cross-ply composite showed a significantly higher coefficient of interfacial friction as compared to the unidirectional composites

  9. Comparative evaluation of tensile bond strength of silicone-based denture liners after thermocycling and surface treatment.

    Kaur, Harsimran; Datta, Kusum

    2015-01-01

    To examine, evaluate, and compare the tensile bond strength of two silicone-based liners; one autopolymerizing and one heat cured, when treated with different chemical etchants to improve their adhesion with denture base resin. Hundred and sixty test specimens of heat-cured polymethyl methacrylate (PMMA) were fabricated; out of which 80 specimens were tested for tensile bond strength after bonding it to autopolymerizing resilient liner (Ufigel P) and rest 80 to heat-cured resilient liner (Molloplast B). Each main group was further divided into four subgroups of 20 specimens each, one to act as a control and three were subjected to surface treatment with different chemical etchants namely dichloromethane, MMA monomer, and chloroform. The two silicone-based denture liners were processed between 2 PMMA specimens (10 mm × 10 mm × 40 mm) in the space provided by a spacer of 3 mm, thermocycled (5-55°C) for 500 cycles, and then their tensile strength measurements were done in the universal testing machine. One-way ANOVA technique showed a highly significant difference in the mean tensile bond strength values for all the groups. The Student's t-test computed values of statistics for the compared groups were greater than the critical values both at 5% and at 1% levels. Surface treatment of denture base resin with chemical etchants prior to the application of silicone-based liner (Ufigel P and Molloplast-B) increased the tensile bond strength. The increase was the highest with specimens subjected to 180 s of MMA surface treatment and the lowest with control group specimens.

  10. Comparative evaluation of tensile bond strength of silicone-based denture liners after thermocycling and surface treatment

    Harsimran Kaur

    2015-01-01

    Full Text Available Purpose: To examine, evaluate, and compare the tensile bond strength of two silicone-based liners; one autopolymerizing and one heat cured, when treated with different chemical etchants to improve their adhesion with denture base resin. Materials and Methods: Hundred and sixty test specimens of heat-cured polymethyl methacrylate (PMMA were fabricated; out of which 80 specimens were tested for tensile bond strength after bonding it to autopolymerizing resilient liner (Ufigel P and rest 80 to heat-cured resilient liner (Molloplast B. Each main group was further divided into four subgroups of 20 specimens each, one to act as a control and three were subjected to surface treatment with different chemical etchants namely dichloromethane, MMA monomer, and chloroform. The two silicone-based denture liners were processed between 2 PMMA specimens (10 mm × 10 mm × 40 mm in the space provided by a spacer of 3 mm, thermocycled (5-55°C for 500 cycles, and then their tensile strength measurements were done in the universal testing machine. Results: One-way ANOVA technique showed a highly significant difference in the mean tensile bond strength values for all the groups. The Student′s t-test computed values of statistics for the compared groups were greater than the critical values both at 5% and at 1% levels. Conclusion: Surface treatment of denture base resin with chemical etchants prior to the application of silicone-based liner (Ufigel P and Molloplast-B increased the tensile bond strength. The increase was the highest with specimens subjected to 180 s of MMA surface treatment and the lowest with control group specimens.

  11. Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

    Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

    2004-01-01

    Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

  12. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  13. Micro benchtop optics by bulk silicon micromachining

    Lee, Abraham P.; Pocha, Michael D.; McConaghy, Charles F.; Deri, Robert J.

    2000-01-01

    Micromachining of bulk silicon utilizing the parallel etching characteristics of bulk silicon and integrating the parallel etch planes of silicon with silicon wafer bonding and impurity doping, enables the fabrication of on-chip optics with in situ aligned etched grooves for optical fibers, micro-lenses, photodiodes, and laser diodes. Other optical components that can be microfabricated and integrated include semi-transparent beam splitters, micro-optical scanners, pinholes, optical gratings, micro-optical filters, etc. Micromachining of bulk silicon utilizing the parallel etching characteristics thereof can be utilized to develop miniaturization of bio-instrumentation such as wavelength monitoring by fluorescence spectrometers, and other miniaturized optical systems such as Fabry-Perot interferometry for filtering of wavelengths, tunable cavity lasers, micro-holography modules, and wavelength splitters for optical communication systems.

  14. Ultrathin silicon oxynitride layer on GaN for dangling-bond-free GaN/insulator interface.

    Nishio, Kengo; Yayama, Tomoe; Miyazaki, Takehide; Taoka, Noriyuki; Shimizu, Mitsuaki

    2018-01-23

    Despite the scientific and technological importance of removing interface dangling bonds, even an ideal model of a dangling-bond-free interface between GaN and an insulator has not been known. The formation of an atomically thin ordered buffer layer between crystalline GaN and amorphous SiO 2 would be a key to synthesize a dangling-bond-free GaN/SiO 2 interface. Here, we predict that a silicon oxynitride (Si 4 O 5 N 3 ) layer can epitaxially grow on a GaN(0001) surface without creating dangling bonds at the interface. Our ab initio calculations show that the GaN/Si 4 O 5 N 3 structure is more stable than silicon-oxide-terminated GaN(0001) surfaces. The electronic properties of the GaN/Si 4 O 5 N 3 structure can be tuned by modifying the chemical components near the interface. We also propose a possible approach to experimentally synthesize the GaN/Si 4 O 5 N 3 structure.

  15. Distribution of species and Ga–N bonds in silicon co-implanted with gallium and nitrogen ions

    Surodin, S. I.; Nikolitchev, D. E.; Kryukov, R. N.; Belov, A. I.; Korolev, D. S.; Mikhaylov, A. N.; Tetelbaum, D. I.

    2016-01-01

    The concentration profiles of species in silicon subjected to gallium and nitrogen co-implantation and subsequent annealing have been investigated by the method of X-ray photoelectron spectroscopy combined with the layer-by-layer ion etching of the implanted layer. It is shown that practically entire implanted gallium undergoes out-diffusion, but the preliminary implantation of nitrogen for the synthesis of a barrier SiN_x layer makes it possible to avoid the essential loss of gallium. In this case, about 14 % of implanted gallium bond to nitrogen. The obtained data are discussed from the viewpoint of the possibility of ion synthesis of GaN inclusions in silicon matrix.

  16. Distribution of species and Ga–N bonds in silicon co-implanted with gallium and nitrogen ions

    Surodin, S. I., E-mail: surodin.bsn@mail.ru; Nikolitchev, D. E.; Kryukov, R. N.; Belov, A. I.; Korolev, D. S.; Mikhaylov, A. N.; Tetelbaum, D. I., E-mail: tetelbaum@phys.unn.ru [Lobachevsky University, 23 Prospekt Gagarina, Nizhny Novgorod, 603950 (Russian Federation)

    2016-06-17

    The concentration profiles of species in silicon subjected to gallium and nitrogen co-implantation and subsequent annealing have been investigated by the method of X-ray photoelectron spectroscopy combined with the layer-by-layer ion etching of the implanted layer. It is shown that practically entire implanted gallium undergoes out-diffusion, but the preliminary implantation of nitrogen for the synthesis of a barrier SiN{sub x} layer makes it possible to avoid the essential loss of gallium. In this case, about 14 % of implanted gallium bond to nitrogen. The obtained data are discussed from the viewpoint of the possibility of ion synthesis of GaN inclusions in silicon matrix.

  17. Development of thin film measurement program of wafer for spin etcher

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  18. Development of thin film measurement program of wafer for spin etcher

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  19. Application of the O-lattice theory for the reconstruction of the high-angle near 90° tilt Si(1 1 0)/(0 0 1) boundary created by wafer bonding

    Cherkashin, N.; Kononchuk, O.; Reboh, S.; Hÿtch, M.

    2012-01-01

    This work presents an experimental and theoretical identification of defects and morphologies of a high-angle near-90° tilt Si (1 ¯ 10)//(001) boundary created by direct wafer bonding. Two samples with different twist misorientations, between the (1 ¯ 10) layer and the (0 0 1) substrate, were studied using conventional transmission electron microscopy (TEM) and geometric phase analysis of high-resolution TEM images. The O-lattice theory was used for atom reconstruction of the interface along the [11 ¯ 0] sub //[001] lay direction. It is demonstrated that to preserve covalent bonding across the interface, it should consist of {11 ¯ 1} sub,lay //{1 ¯ 12} lay,sub facets intersected by maximum of six {11 ¯ 1} lay,sub planes with three 90° Shockley dislocations per facet. It is shown that a particular atom reconstruction is needed at transition points from one facet to another. The presence or absence of deviation from exact 90° tilt of the layer with respect to the substrate is shown to be related directly to the undulations of the interface. It is demonstrated that the latter has an influence on the Burgers vector of the dislocations adjusting in-plane twist misorientation. A general model for cubic face-centered materials for an arbitrary 〈1 1 0〉 sub,lay tilt interface is proposed, which predicts the net Burgers vector and the spacing between dislocations necessary to realize transition from the lattice of the substrate (layer) to the layer (substrate).

  20. Investigations of the electrical neutralization and bonding mechanisms of shallow impurities in silicon grain boundaries

    Kazmerski, L.L.; Nelson, A.J.; Dhere, R.G.; Abou-Elfotouh, F.

    1987-01-01

    Interactions between shallow acceptors (B, Al, Ga and In) and hydrogen in polycrystalline Si are investigated. The bonding mechanisms involved in the acceptor neutralization process at grain boundaries are examined using microanalytical techniques. Differences in the incorporation of molecular and atomic hydrogen, and corresponding variations in electrical passivation at grain boundaries, are observed. Low-temperature Auger difference spectroscopy confirms Si-H bonding to dominate B, Ga and In-doped cases, with no direct acceptor-hydrogen bonding. Al-rich grain boundaries show H-complex and hydroxyl bonding. The data confirm chemical bond strength trends with B< Ga< In. Volume-indexed AES is utilized to compare bonding and H-distributions in B- and Al-rich grain boundary regions

  1. Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

    Kwang Hong Lee

    2015-01-01

    Full Text Available A method to remove the misfit dislocations and reduce the threading dislocations density (TDD in the germanium (Ge epilayer growth on a silicon (Si substrate is presented. The Ge epitaxial film is grown directly on the Si (001 donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001 handle wafer to form a germanium-on-insulator (GOI substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

  2. Reticle variation influence on manufacturing line and wafer device performance

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  3. Porous silicon technology for integrated microsystems

    Wallner, Jin Zheng

    With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially

  4. Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

    Kim, Jong Cheol; Kim, Jongsik; Xin, Yan; Lee, Jinhyung; Kim, Young-Gyun; Subhash, Ghatu; Singh, Rajiv K.; Arjunan, Arul C.; Lee, Haigun

    2018-05-01

    The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (˜3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

  5. Non-silicon substrate bonding mediated by poly(dimethylsiloxane) interfacial coating

    Zhang, Hainan; Lee, Nae Yoon

    2015-02-01

    In this paper, we introduce a simple and robust strategy for bonding poly(dimethylsiloxane) (PDMS) with various thermoplastic substrates to fabricate a thermoplastic-based closed microfluidic device and examine the feasibility of using the proposed method for realizing plastic-plastic bonding. The proposed bonding strategy was realized by first coating amine functionality on an oxidized thermoplastic surface. Next, the amine-functionalized surface was reacted with a monolayer of low-molecular-weight PDMS, terminated with epoxy functionality, by forming a robust amine-epoxy bond. Both the PDMS-coated thermoplastic and PDMS were then oxidized and permanently assembled at 25 °C under a pressure of 0.1 MPa for 15 min, resulting in PDMS-like surfaces on all four inner walls of the microchannel. Surface characterizations were conducted, including water contact angle measurement, X-ray photoelectron spectroscopy (XPS), and fluorescence measurement, to confirm the successful coating of the thin PDMS layer on the plastic surface, and the bond strength was analyzed by conducting a peel test, burst test, and leakage test. Using the proposed method, we could successfully bond various thermoplastics such as poly(methylmethacrylate) (PMMA), polycarbonate (PC), polystyrene (PS), and poly(ethylene terephthalate) (PET) with PDMS without the collapse or deformation of the microchannel, and the proposed method was successfully extended to the bonding of two thermoplastics, PMMA, and PC.

  6. Study of the processes of carbonization and oxidation of porous silicon by Raman and IR spectroscopy

    Vasin, A. V.; Okholin, P. N.; Verovsky, I. N.; Nazarov, A. N.; Lysenko, V. S.; Kholostov, K. I.; Bondarenko, V. P.; Ishikawa, Y.

    2011-01-01

    Porous silicon layers were produced by electrochemical etching of single-crystal silicon wafers with the resistivity 10 Ω cm in the aqueous-alcohol solution of hydrofluoric acid. Raman spectroscopy and infrared absorption spectroscopy are used to study the processes of interaction of porous silicon with undiluted acetylene at low temperatures and the processes of oxidation of carbonized porous silicon by water vapors. It is established that, even at the temperature 550°C, the silicon-carbon bonds are formed at the pore surface and the graphite-like carbon condensate emerges. It is shown that the carbon condensate inhibits oxidation of porous silicon by water vapors and contributes to quenching of white photoluminescence in the oxidized carbonized porous silicon nanocomposite layer.

  7. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    Zhuhao Gong

    2018-02-01

    Full Text Available A radio-frequency micro-electro-mechanical system (RF MEMS wafer-level packaging (WLP method using pre-patterned benzo-cyclo-butene (BCB polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100–400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz.

  8. Strength and leak testing of plasma activated bonded interfaces

    Visser, M.M.; Weichel, Steen; Reus, Roger De

    2002-01-01

    on detection of changes in membrane deflections. The detection limit for leak was 8E-13 mbar l/s. For comparison, strength and leak tests were also performed with regular fusion bonded wafers annealed at 1100 degreesC. The PAB was found to withstand post-processing steps such as RCA cleaning, 24 h in de......-ionised water (DIW), 24 h in 2.5% HF, 24 h in acetone and 60 s in a resist developer. By analysing the thin silicon oxide present on the surfaces to be bonded with optical methods, the influence of pre-cleaning and activation process parameters was investigated....

  9. Oxide-Free Bonding of III-V-Based Material on Silicon and Nano-Structuration of the Hybrid Waveguide for Advanced Optical Functions

    Konstantinos Pantzas

    2015-10-01

    Full Text Available Oxide-free bonding of III-V-based materials for integrated optics is demonstrated on both planar Silicon (Si surfaces and nanostructured ones, using Silicon on Isolator (SOI or Si substrates. The hybrid interface is characterized electrically and mechanically. A hybrid InP-on-SOI waveguide, including a bi-periodic nano structuration of the silicon guiding layer is demonstrated to provide wavelength selective transmission. Such an oxide-free interface associated with the nanostructured design of the guiding geometry has great potential for both electrical and optical operation of improved hybrid devices.

  10. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  11. Technology for bonding silicon nitride ceramics. Heat treatment technology to improve diffusion bonding strength; Chikka keiso ceramics no setsugo gijutsu. Kakusan setsugo kyodo kaizen no tame no metsushori gijutsu

    Nakamura, M.; Shigematsu, K. [National Industrial Research Institute of Nagoya,Nagoya (Japan)

    1999-01-25

    Silicon nitride ceramics is a structural ceramics with excellent high temperature strength and tenacity, being expected of expansion of application as a high temperature material. However, its processibility is poor, and special sintering technique is required to manufacture members of complex shapes. Therefore, development has been made on a technology to manufacture bonded materials with high mechanical strength, by which diffusion bonding in high temperature nitrogen gas and heat treatment are combined, and crystalline structure in the vicinity of bonding interface is controlled. (translated by NEDO)

  12. Materials preparation and fabrication of pyroelectric polymer/silicon MOSFET detector arrays. Final report

    Bloomfield, P.

    1992-01-01

    The authors have delivered several 64-element linear arrays of pyroelectric elements fully integrated on silicon wafers with MOS readout devices. They have delivered detailed drawings of the linear arrays to LANL. They have processed a series of two inch wafers per submitted design. Each two inch wafer contains two 64 element arrays. After spin-coating copolymer onto the arrays, vacuum depositing the top electrodes, and polarizing the copolymer films so as to make them pyroelectrically active, each wafer was split in half. The authors developed a thicker oxide coating separating the extended gate electrode (beneath the polymer detector) from the silicon. This should reduce its parasitic capacitance and hence improve the S/N. They provided LANL three processed 64 element sensor arrays. Each array was affixed to a connector panel and selected solder pads of the common ground, the common source voltage supply connections, the 64 individual drain connections, and the 64 drain connections (for direct pyroelectric sensing response rather than the MOSFET action) were wire bonded to the connector panel solder pads. This entails (64 + 64 + 1 + 1) = 130 possible bond connections per 64 element array. This report now details the processing steps and the progress of the individual wafers as they were carried through from beginning to end

  13. Effects of indium concentration on the properties of In-doped ZnO films: Applications to silicon wafer solar cells

    Djessas, K. [Université de Perpignan Via Domitia (UPVD), Laboratoire Procédés, Matériaux et Energie Solaire (PROMES—CNRS), TECNOSUD, Rambla de la thermodynamique, 66100 Perpignan (France); Bouchama, I., E-mail: bouchama.idris@yahoo.fr [Université de Perpignan Via Domitia (UPVD), Laboratoire Procédés, Matériaux et Energie Solaire (PROMES—CNRS), TECNOSUD, Rambla de la thermodynamique, 66100 Perpignan (France); Département d' Electronique, Faculté de Technologie, Université de Msila, 28000 (Algeria); Gauffier, J.L. [Département de Physique, INSA de Toulouse, 135 Avenue de Rangueil, 31077 Toulouse Cedex 4 (France); Ayadi, Z. Ben [Laboratoire de Physique des Matériaux et des Nanomatériaux appliquée à l' Environnement (LaPhyMNE), Université de Gabès, Faculté des Sciences de Gabès, Cité Erriadh Manara Zrig, 6072 Gabès (Tunisia)

    2014-03-31

    In the present paper, high-quality In-doped ZnO (ZnO:In) thin films have been prepared by rf-magnetron sputtering on glass and p-type monocrystalline silicon substrates from an aerogel nanopowder target material. The nanoparticles with the [In]/[Zn] ratio varying between 0.01 and 0.05 were synthesized by the sol–gel method and the structural properties have been analyzed. The effect of different dopant concentrations on the electrical, optical, structural and morphological properties of the films has been investigated. The obtained ZnO:In films at room temperature are polycrystalline with a hexagonal structure and a highly preferred orientation with the c-axis perpendicular to the substrate. Scanning electron microscopy and atomic force microscopy have been applied for a morphology characterization of the films' cross-section and surface. The results revealed a typical columnar structure and very smooth surface. Films with good optical transmittance, around 85%, within the visible wavelength region, and low resistivity in the range of 10{sup −3} Ω·cm and high mobility of 4 cm{sup 2}/Vs, were produced at low substrate temperature. On the other hand, we have studied the position of the p–n junction involved in an Au/In{sub 2}O{sub 3}:SnO{sub 2}/ZnO:In(n)/c-Si(p)/Al structure by electron beam induced current. Current density–voltage characterizations in the dark and under illumination were also performed. The cell exhibits an efficiency of 6%. - Highlights: • ZnO:In thin films were prepared by rf-magnetron sputtering. • No significant changes were observed in the ZnO:In properties. • In-doped ZnO shows superior electric properties compared with pure ZnO. • Interesting photovoltaic effect observed in ITO/ZnO:In(n)/c-Si(p) heterostructure • Good quality of p–n junction in the ZnO:In(n)/c-Si(p) solar cell.

  14. Genesis of nanostructured, magnetically tunable ceramics from the pyrolysis of cross-linked polyferrocenylsilane networks and formation of shaped macroscopic objects and micron scale patterns by micromolding inside silicon wafers.

    Ginzburg, Madlen; MacLachlan, Mark J; Yang, San Ming; Coombs, Neil; Coyle, Thomas W; Raju, Nandyala P; Greedan, John E; Herber, Rolfe H; Ozin, Geoffrey A; Manners, Ian

    2002-03-20

    The ability to form molded or patterned metal-containing ceramics with tunable properties is desirable for many applications. In this paper we describe the evolution of a ceramic from a metal-containing polymer in which the variation of pyrolysis conditions facilitates control of ceramic structure and composition, influencing magnetic and mechanical properties. We have found that pyrolysis under nitrogen of a well-characterized cross-linked polyferrocenylsilane network derived from the ring-opening polymerization (ROP) of a spirocyclic [1]ferrocenophane precursor gives shaped macroscopic magnetic ceramics consisting of alpha-Fe nanoparticles embedded in a SiC/C/Si(3)N(4) matrix in greater than 90% yield up to 1000 degrees C. Variation of the pyrolysis temperature and time permitted control over the nucleation and growth of alpha-Fe particles, which ranged in size from around 15 to 700 A, and the crystallization of the surrounding matrix. The ceramics contained smaller alpha-Fe particles when prepared at temperatures lower than 900 degrees C and displayed superparamagnetic behavior, whereas the materials prepared at 1000 degrees C contained larger alpha-Fe particles and were ferromagnetic. This flexibility may be useful for particular materials applications. In addition, the composition of the ceramic was altered by changing the pyrolysis atmosphere to argon, which yielded ceramics that contain Fe(3)Si(5). The ceramics have been characterized by a combination of physical techniques, including powder X-ray diffraction, TEM, reflectance UV-vis/near-IR spectroscopy, elemental analysis, XPS, SQUID magnetometry, Mössbauer spectroscopy, nanoindentation, and SEM. Micromolding of the spirocyclic [1]ferrocenophane precursor within soft lithographically patterned channels housed inside silicon wafers followed by thermal ROP and pyrolysis enabled the formation of predetermined micron scale designs of the magnetic ceramic.

  15. Porous silicon: Synthesis and optical properties

    Naddaf, M.; Awad, F.

    2006-01-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  16. Porous silicon: Synthesis and optical properties

    Naddaf, M.; Awad, F.

    2006-06-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  17. Modification of the properties of porous silicon on adsorption of iodine molecules

    Vorontsov, A. S.; Osminkina, L. A.; Tkachenko, A. E.; Konstantinova, E. A.; Elenskii, V. G.; Timoshenko, V. Yu.; Kashkarov, P. K.

    2007-01-01

    Infrared spectroscopy and electron spin resonance measurements are used to study the properties of porous silicon layers on adsorption of the I 2 iodine molecules. The layers are formed on the p-an n-Si single-crystal wafers. It is established that, in the atmosphere of I 2 molecules, the charge-carrier concentration in the layers produced on the p-type wafers can be noticeably increased: the concentration of holes can attain values on the order of ∼10 18 -10 19 cm -3 . In porous silicon layers formed on the n-type wafers, the adsorption-induced inversion of the type of charge carriers and the partial substitution of silicon-hydrogen bonds by silicon-iodine bonds are observed. A decrease in the concentration of surface paramagnetic defects, P b centers, is observed in the samples with adsorbed iodine. The experimental data are interpreted in the context of the model in which it is assumed that both deep and shallow acceptor states are formed at the surface of silicon nanocrystals upon the adsorption of I 2 molecules

  18. Wafer-Level Vacuum Packaging of Smart Sensors

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  19. Wafer-Level Vacuum Packaging of Smart Sensors.

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  20. Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

    Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

    2015-01-01

    Graphical abstract: - Highlights: • How Ag transfers F − to the adjacent Si atom was investigated and deduced by DFT at atomic scale. • Three-electrode CV tests proved the transferring function of Ag in the etching reaction. • Uniform SiNWAs were fabricated on unpolished silicon wafers with KOH pretreatment. - Abstract: Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F − ) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F − , smaller azimuth angle of F−Ag(T4)−Si, shorter bond length of F−Si compared with F−Ag. As F − was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF 4 when it bonded with enough F − while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F − to Si

  1. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  2. Assembly and evaluation of a pyroelectric detector bonded to vertically aligned multiwalled carbon nanotubes over thin silicon.

    Theocharous, E; Theocharous, S P; Lehman, J H

    2013-11-20

    A novel pyroelectric detector consisting of a vertically aligned nanotube array on thin silicon (VANTA/Si) bonded to a 60 μm thick crystal of LiTaO₃ has been fabricated. The performance of the VANTA/Si-coated pyroelectric detector was evaluated using National Physical Laboratory's (NPL's) detector-characterization facilities. The relative spectral responsivity of the detector was found to be spectrally flat in the 0.8-24 μm wavelength range, in agreement with directional-hemispherical reflectance measurements of witness samples of the VANTA. The spatial uniformity of response of the test detector exhibited good uniformity, although the nonuniformity increased with increasing modulation frequency. The nonuniformity may be assigned either to the dimensions of the VANTA or the continuity of the bond between the VANTA/Si coating and the pyroelectric crystal substrate. The test detector exhibited a small superlinear response, which is similar to that of pyroelectric detectors coated with good quality gold-black coatings.

  3. Oxidation effects on the mechanical properties of SiC fiber-reinforced reaction-bonded silicon nitride matrix composites

    Bhatt, Ramakrishna T.

    1989-01-01

    The room temperature mechanical properties of SiC fiber reinforced reaction bonded silicon nitride composites were measured after 100 hrs exposure at temperatures to 1400 C in nitrogen and oxygen environments. The composites consisted of approx. 30 vol percent uniaxially aligned 142 micron diameter SiC fibers in a reaction bonded Si3N4 matrix. The results indicate that composites heat treated in a nitrogen environment at temperatures to 1400 C showed deformation and fracture behavior equivalent to that of the as-fabricated composites. Also, the composites heat treated in an oxidizing environment beyond 400 C yielded significantly lower tensile strength values. Specifically in the temperature range from 600 to 1000 C, composites retained approx. 40 percent of their as-fabricated strength, and those heat treated in the temperatures from 1200 to 1400 C retained 70 percent. Nonetheless, for all oxygen heat treatment conditions, composite specimens displayed strain capability beyond the matrix fracture stress; a typical behavior of a tough composite.

  4. Internal-strain effect on the valence band of strained silicon and its correlation with the bond angles

    Inaoka, Takeshi, E-mail: inaoka@phys.u-ryukyu.ac.jp; Yanagisawa, Susumu; Kadekawa, Yukihiro [Department of Physics and Earth Sciences, Faculty of Science, University of the Ryukyus, 1 Senbaru, Nishihara, Okinawa 903-0213 (Japan)

    2014-02-14

    By means of the first-principles density-functional theory, we investigate the effect of relative atom displacement in the crystal unit cell, namely, internal strain on the valence-band dispersion of strained silicon, and find close correlation of this effect with variation in the specific bond angles due to internal strain. We consider the [111] ([110]) band dispersion for (111) ((110)) biaxial tensility and [111] ([110]) uniaxial compression, because remarkably small values of hole effective mass m* can be obtained in this dispersion. Under the practical condition of no normal stress, biaxial tensility (uniaxial compression) involves additional normal compression (tensility) and internal strain. With an increase in the internal-strain parameter, the energy separation between the highest and second-highest valence bands becomes strikingly larger, and the highest band with conspicuously small m* extends remarkably down to a lower energy region, until it intersects or becomes admixed with the second band. This is closely correlated with the change in the specific bond angles, and this change can reasonably explain the above enlargement of the band separation.

  5. Formation of apatite on hydrogenated amorphous silicon (a-Si:H) film deposited by plasma-enhanced chemical vapor deposition

    Liu Xuanyong; Chu, Paul K.; Ding Chuanxian

    2007-01-01

    Hydrogenated amorphous silicon films were fabricated on p-type, 100 mm diameter silicon wafers by plasma-enhanced chemical vapor deposition (PECVD) using silane and hydrogen. The structure and composition of the hydrogenated amorphous silicon films were investigated using micro-Raman spectroscopy and cross-sectional transmission electron microscopy (XTEM). The hydrogenated amorphous silicon films were subsequently soaked in simulated body fluids to evaluate apatite formation. Carbonate-containing hydroxyapatite (bone-like apatite) was formed on the surface suggesting good bone conductivity. The amorphous structure and presence of surface Si-H bonds are believed to induce apatite formation on the surface of the hydrogenated amorphous silicon film. A good understanding of the surface bioactivity of silicon-based materials and means to produce a bioactive surface is important to the development of silicon-based biosensors and micro-devices that are implanted inside humans

  6. Formation of apatite on hydrogenated amorphous silicon (a-Si:H) film deposited by plasma-enhanced chemical vapor deposition

    Liu Xuanyong [Shanghai Institute of Ceramics, Chinese Academy of Sciences, 1295 Dingxi Road, Shanghai 200050 (China) and Department of Physics and Materials Science, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong (China)]. E-mail: xyliu@mail.sic.ac.cn; Chu, Paul K. [Department of Physics and Materials Science, City University of Hong Kong, Tat Chee Avenue, Kowloon, Hong Kong (China)]. E-mail: paul.chu@cityu.edu.hk; Ding Chuanxian [Shanghai Institute of Ceramics, Chinese Academy of Sciences, 1295 Dingxi Road, Shanghai 200050 (China)

    2007-01-15

    Hydrogenated amorphous silicon films were fabricated on p-type, 100 mm diameter <1 0 0> silicon wafers by plasma-enhanced chemical vapor deposition (PECVD) using silane and hydrogen. The structure and composition of the hydrogenated amorphous silicon films were investigated using micro-Raman spectroscopy and cross-sectional transmission electron microscopy (XTEM). The hydrogenated amorphous silicon films were subsequently soaked in simulated body fluids to evaluate apatite formation. Carbonate-containing hydroxyapatite (bone-like apatite) was formed on the surface suggesting good bone conductivity. The amorphous structure and presence of surface Si-H bonds are believed to induce apatite formation on the surface of the hydrogenated amorphous silicon film. A good understanding of the surface bioactivity of silicon-based materials and means to produce a bioactive surface is important to the development of silicon-based biosensors and micro-devices that are implanted inside humans.

  7. Optimizing shape uniformity and increasing structure heights of deep reactive ion etched silicon x-ray lenses

    Stöhr, Frederik; Wright, Jonathan; Simons, Hugh

    2015-01-01

    Line-focusing compound silicon x-ray lenses with structure heights exceeding 300 μm were fabricated using deep reactive ion etching. To ensure profile uniformity over the full height, a new strategy was developed in which the perimeter of the structures was defined by trenches of constant width....... The remaining sacrificial material inside the lens cavities was removed by etching through the silicon wafer. Since the wafers become fragile after through-etching, they were then adhesively bonded to a carrier wafer. Individual chips were separated using laser micro machining and the 3D shape of fabricated...... analysis, where a slight bowing of the lens sidewalls and an insufficiently uniform apex region are identified as resolution-limiting factors. Despite these, the proposed fabrication route proved a viable approach for producing x-ray lenses with large structure heights and provides the means to improve...

  8. Wafer integrated micro-scale concentrating photovoltaics

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  9. Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

    Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

    2018-03-01

    In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

  10. MEMS silicon-based micro-evaporator with diamond-shaped fins

    Mihailovic, M.; Rops, C.; Creemer, J.F.; Sarro, P.M.

    2010-01-01

    A new design of micro-evaporators, with 45 channels (View the MathML source100?m deep) and diamond-shaped fins (View the MathML source40?m wide, View the MathML source160?m long, View the MathML source20?m separation), is fabricated by anodic bonding of silicon and glass wafers, in a five masks

  11. Effects of accelerated artificial daylight aging on bending strength and bonding of glass fibers in fiber-embedded maxillofacial silicone prostheses.

    Hatamleh, Muhanad M; Watts, David C

    2010-07-01

    The purpose of this study was to test the effect of different periods of accelerated artificial daylight aging on bond strength of glass fiber bundles embedded into maxillofacial silicone elastomer and on bending strength of the glass fiber bundles. Forty specimens were fabricated by embedding resin-impregnated fiber bundles (1.5-mm diameter, 20-mm long) into maxillofacial silicone elastomer. Specimens were randomly allocated into four groups, and each group was subjected to different periods of accelerated daylight aging as follows (in hours); 0, 200, 400, and 600. The aging cycle included continuous exposure to quartz-filtered visible daylight (irradiance 760 W/m(2)) under an alternating weathering cycle (wet for 18 minutes, dry for 102 minutes). Pull-out tests were performed to evaluate bond strength between fiber bundles and silicone using a universal testing machine at 1 mm/min crosshead speed. Also a three-point bending test was performed to evaluate bending strength of the fiber bundles. One-way ANOVA and Bonferroni post hoc tests were carried out to detect statistical significance (p aging only. After 200 hours of exposure to artificial daylight and moisture conditions, bond strength between glass fibers and heat-cured silicones is optimal, and the bending strength of the glass fiber bundles is enhanced.

  12. Cost of Czochralski wafers as a function of diameter

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  13. Bio-inspired co-catalysts bonded to a silicon photocathode for solar hydrogen evolution

    Hou, Yidong; Abrams, Billie; Vesborg, Peter Christian Kjærgaard

    2011-01-01

    The production of fuels directly or indirectly from sunlight represents one of the major challenges to the development of a sustainable energy system. Hydrogen is the simplest fuel to produce and while platinum and other noble metals are efficient catalysts for photoelectrochemical hydrogen...... at the reversible potential match the requirement of a photoelectrochemical hydrogen production system with a solar-to-hydrogen efficiency in excess of 10%. The experimental observations are supported by DFT calculations of the Mo3S4 cluster adsorbed on the hydrogen-terminated silicon surface providing insights...... deposited on various supports. It will be demonstrated how this overpotential can be eliminated by depositing the same type of hydrogen evolution catalyst on p-type Si which can harvest the red part of the solar spectrum. Such a system could constitute the cathode part of a tandem dream device where the red...

  14. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    Heib, F.; Hempelmann, R.; Munief, W.M.; Ingebrandt, S.; Fug, F.; Possart, W.; Groß, K.; Schmitt, M.

    2015-01-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ a and the receding θ r contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple line dis

  15. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    Heib, F., E-mail: f.heib@mx.uni-saarland.de [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Hempelmann, R. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Munief, W.M.; Ingebrandt, S. [Department of Informatics and Microsystem Technology, University of Applied Sciences, Kaiserslautern, 66482 Zweibrücken (Germany); Fug, F.; Possart, W. [Department of Adhesion and Interphases in Polymers, Saarland University, 66123 Saarbrücken (Germany); Groß, K.; Schmitt, M. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany)

    2015-07-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ{sub a} and the receding θ{sub r} contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple

  16. Development of an Indium Bump Bond Process for Silicon Pixel Detectors at PSI

    Brönnimann, C; Gobrecht, J; Heising, S; Horisberger, M; Horisberger, R P; Kästli, H C; Lehmann, J; Rohe, T; Streuli, S; Broennimann, Ch.

    2006-01-01

    The hybrid pixel detectors used in the high energy physics experiments currently under construction use a three dimensional connection technique, the so-called bump bonding. As the pitch below 100um, required in these applications, cannot be fullfilled with standard industrial processes (e.g. the IBM C4 process), an in-house bump bond process using reflown indium bumps was developed at PSI as part of the R&D for the CMS-pixel detector. The bump deposition on the sensor is performed in two subsequent lift-off steps. As the first photolithographic step a thin under bump metalization (UBM) is sputtered onto bump pads. It is wettable by indium and defines the diameter of the bump. The indium is evaporated via a second photolithographic step with larger openings and is reflown afterwards. The height of the balls is defined by the volume of the indium. On the readout chip only one photolithographic step is carried out to deposit the UBM and a thin indium layer for better adhesion. After mating both parts a seco...

  17. Silicon Wafer X-ray Mirror Project

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  18. Silicon Wafer X-ray Mirror

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  19. BCB Bonding Technology of Back-Side Illuminated COMS Device

    Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

    2018-03-01

    Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

  20. Ultra-thin silicon oxide layers on crystalline silicon wafers: Comparison of advanced oxidation techniques with respect to chemically abrupt SiO{sub 2}/Si interfaces with low defect densities

    Stegemann, Bert, E-mail: bert.stegemann@htw-berlin.de [HTW Berlin - University of Applied Sciences, 12459 Berlin (Germany); Gad, Karim M. [University of Freiburg, Department of Microsystems Engineering - IMTEK, 79110 Freiburg (Germany); Balamou, Patrice [HTW Berlin - University of Applied Sciences, 12459 Berlin (Germany); Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany); Sixtensson, Daniel [Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany); Vössing, Daniel; Kasemann, Martin [University of Freiburg, Department of Microsystems Engineering - IMTEK, 79110 Freiburg (Germany); Angermann, Heike [Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany)

    2017-02-15

    Highlights: • Fabrication of ultrathin SiO{sub 2} tunnel layers on c-Si. • Correlation of electronic and chemical SiO{sub 2}/Si interface properties revealed by XPS/SPV. • Chemically abrupt SiO{sub 2}/Si interfaces generate less interface defect states considerable. - Abstract: Six advanced oxidation techniques were analyzed, evaluated and compared with respect to the preparation of high-quality ultra-thin oxide layers on crystalline silicon. The resulting electronic and chemical SiO{sub 2}/Si interface properties were determined by a combined x-ray photoemission (XPS) and surface photovoltage (SPV) investigation. Depending on the oxidation technique, chemically abrupt SiO{sub 2}/Si interfaces with low densities of interface states were fabricated on c-Si either at low temperatures, at short times, or in wet-chemical environment, resulting in each case in excellent interface passivation. Moreover, the beneficial effect of a subsequent forming gas annealing (FGA) step for the passivation of the SiO{sub 2}/Si interface of ultra-thin oxide layers has been proven. Chemically abrupt SiO{sub 2}/Si interfaces have been shown to generate less interface defect states.

  1. Effect of deposition temperature on the bonding configurations and properties of fluorine doped silicon oxide film

    Lu, Wei-Lun; Kuo, Ting-Wei; Huang, Chun-Hsien; Wang, Na-Fu; Tsai, Yu-Zen; Wang, Ming-Wei; Hung, Chen-I.; Houng, Mau-Phon

    2011-01-01

    In our study, fluorine-doped silicon oxide (SiOF) films were prepared using a mixture of SiH 4 , N 2 O, and CF 4 in a conventional plasma enhanced chemical vapor deposition system at various deposition temperatures. Deposition behaviors are determined by the deposition temperature. Our results show that for temperatures below 300 deg. C the process is surface-reaction-limited controlled, but becomes diffusion-limited when the deposition temperature exceeds 300 deg. C. The surface topography images obtained using an atomic force microscope show that a large amount of free volume space was created in the film with a low temperature deposition. The optical microscope and secondary ion mass spectrometer analyses show that precipitates were produced at the near-surface at the deposition temperature of 150 deg. C with a higher fluorine concentration of 2.97 at.%. Our results show that the properties of the SiOF film are controlled not only by the free volume space but also by the fluorine concentration. An optimal SiOF film prepared at a temperature of 200 deg. C shows a low dielectric constant of 3.55, a leakage current of 1.21 x 10 -8 A/cm 2 at 1 MV/cm, and a fluorine concentration of 2.5 at.%.

  2. Organoactinides-new type of catalysts for carbon-silicon bond formation

    Dash, Aswini K.; Wang, Ji.Q.; Wang, Jiaxi; Gourevich, Ilya; Eisen, Moris S.

    2002-01-01

    Organoactinide complexes of the type Cp 2 * AnMe 2 (An=Th, U) have been found to be efficient catalysts for the hydrosilylation of terminal alkynes. The chemoselectivity and regiospecificity of the reactions depend strongly on the nature of the catalyst, the nature of the alkyne, the silane substituents, the ratio between the silane and alkyne, the solvent and the reaction temperature. The hydrosilylation reaction of the terminal alkynes with PhSiH 3 at room temperature produces the trans-vinylsilane as the major product along with the silylalkyne and the corresponding alkene. At higher temperatures the cis-vinylsilane and the double hydrosilylated alkene, in which the two silicon moieties are connected at the same carbon atom, are also obtained. Replacing the pentamethylcyclopentadienyl ligand by the bridge ligation [Me 2 SiCp'' 2 ] 2- 2[Li] + (Cp''=C 5 Me 4 ) affords the synthesis of ansa-Me 2 SiCp'' 2 ThBu 2 , which was found to react extremely fast for the hydrosilylation of terminal alkynes or alkenes with PhSiH 3 . Besides the rapidity of the processes using the bridge organoactinide, as compared to Cp * 2 ThMe 2 , the chemo- and regio-selectivity of the products were increased allowing the production of only the trans-vinylsilane and the 1-silylated alkane for the hydrosilylation of alkyne and alkene, respectively. (author)

  3. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  4. The interaction of reaction-bonded silicon carbide and inconel 600 with a nickel-based brazing alloy

    McDermid, J. R.; Pugh, M. D.; Drew, R. A. L.

    1989-09-01

    The objective of the present research was to join reaction-bonded silicon carbide (RBSC) to INCONEL 600 (a nickel-based superalloy) for use in advanced heat engine applications using either direct brazing or composite interlayer joining. Direct brazing experiments employed American Welding Society (AWS) BNi-5, a commercial nickel-based brazing alloy, as a filler material; composite interlayers consisted of intimate mixtures of α-SiC and BNi-5 powders. Both methods resulted in the liquid filler metal forming a Ni-Si liquid with the free Si in the RBSC, which, in turn, reacted vigorously with the SiC component of the RBSC to form low melting point constituents in both starting materials and Cr carbides at the metal-ceramic interface. Using solution thermodynamics, it was shown that a Ni-Si liquid of greater than 60 at. pct Ni will decompose a-SiC at the experimental brazing temperature of 1200 ‡C; these calculations are consistent with the experimentally observed composition profiles and reaction morphology within the ceramic. It was concluded that the joining of RBSC to INCONEL 600 using a nickel-based brazing alloy is not feasible due to the inevitability of the filler metal reacting with the ceramic, degrading the high-temperature properties of the base materials.

  5. Fabrication of novel AFM probe with high-aspect-ratio ultra-sharp three-face silicon nitride tips

    Vermeer, Rolf; Berenschot, Johan W.; Sarajlic, Edin; Tas, Niels Roelof; Jansen, Henricus V.

    In this paper we present the wafer-scale fabrication of molded AFM probes with high aspect ratio ultra-sharp three-plane silicon nitride tips. Using $\\langle$111$\\rangle$ silicon wafers a dedicated process is developed to fabricate molds in the silicon wafer that have a flat triangular bottom

  6. Electro-optical properties of dislocations in silicon and their possible application for light emitters

    Arguirov, Tzanimir Vladimirov

    2007-10-14

    This thesis addresses the electro-optical properties of silicon, containing dislocations. The work demonstrates that dislocation specific radiation may provide a means for optical diagnostics of solar cell grade silicon. It provides insight into the mechanisms governing the dislocation recombination activity, their radiation, and how are they influenced by other defects present in silicon. We demonstrate that photoluminescence mapping is useful for monitoring the recombination activity in solar cell grade silicon and can be applied for identification of contaminants, based on their photoluminescence signatures. It is shown that the recombination at dislocations is strongly influenced by the presence of metals at the dislocation sites. The dislocation radiation activity correlates with their electrical activity. It is shown that the dislocation and band-to-band luminescence are essentially anti-correlated. {beta}FeSi{sub 2} precipitates, with a luminescence at 0.8 eV, were detected within the grains of block cast materials. They exhibit a characteristic feature of quantum dots, namely blinking. The second aspect of the thesis concerns the topic of silicon based light emitters for on-chip optical interconnects. The goal is an enhancement of sub-band-gap or band-to-band radiation by controlled formation of dislocation-rich areas in microelectronics-grade silicon as well as understanding of the processes governing such enhancement. For light emitters based on band-to-band emission it is shown, that internal quantum efficiency of nearly 2 % can be achieved, but the emission is essentially generated in the bulk of the wafer. On the other hand, light emitters utilizing the emission from dislocation-rich areas of a well localized wafer depth were explored. Three different methods for reproducible formation of a dislocation-rich region beneath the wafer surface were investigated and evaluated in view of their room temperature sub-band-gap radiation: (1) silicon implantation

  7. Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

    Gammon P.M.

    2017-01-01

    Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

  8. Optical and passivating properties of hydrogenated amorphous silicon nitride deposited by plasma enhanced chemical vapour deposition for application on silicon solar cells

    Wight, Daniel Nilsen

    2008-07-01

    Within this thesis, several important subjects related to the use of amorphous silicon nitride made by plasma enhanced chemical vapour deposition as an anti-reflective coating on silicon solar cells are presented. The first part of the thesis covers optical simulations to optimise single and double layer anti-reflective coatings with respect to optical performance when situated on a silicon solar cell. The second part investigates the relationship between important physical properties of silicon nitride films when deposited under different conditions. The optical simulations were either based on minimising the reflectance off a silicon nitride/silicon wafer stack or maximising the transmittance through the silicon nitride into the silicon wafer. The former method allowed consideration of the reflectance off the back surface of the wafer, which occurs typically at wavelengths above 1000 nm due to the transparency of silicon at these wavelengths. However, this method does not take into consideration the absorption occurring in the silicon nitride, which is negligible at low refractive indexes but quite significant when the refractive index increases above 2.1. For high-index silicon nitride films, the latter method is more accurate as it considers both reflectance and absorbance in the film to calculate the transmittance into the Si wafer. Both methods reach similar values for film thickness and refractive index for optimised single layer anti-reflective coatings, due to the negligible absorption occurring in these films. For double layer coatings, though, the reflectance based simulations overestimated the optimum refractive index for the bottom layer, which would have lead to excessive absorption if applied to real anti-reflective coatings. The experimental study on physical properties for silicon nitride films deposited under varying conditions concentrated on the estimation of properties important for its applications, such as optical properties, passivation

  9. Wafer scale integration of catalyst dots into nonplanar microsystems

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  10. Magnetically enhanced triode etching of large area silicon membranes in a molecular bromine plasma

    Wolfe, J.C.; Sen, S.; Pendharkar, S.V.; Mauger, P.; Shimkunas, A.R.

    1992-01-01

    The optimization of a process for etching 125 mm silicon membranes formed on 150 mm wafers and bonded to Pyrex rings is discussed. A magnetically enhanced triode etching system was designed to provide an intense, remote plasma surrounding the membrane while, at the same time, suppressing the discharge over the membrane itself. For the optimized molecular bromine process, the silicon etch rate is 40 nm/min and the selectivity relative to SiO 2 is 160:1. 14 refs., 6 figs

  11. Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

    Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

    2013-11-15

    We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

  12. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  13. Hybrid III-V/silicon lasers

    Kaspar, P.; Jany, C.; Le Liepvre, A.; Accard, A.; Lamponi, M.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Shen, A.; Charbonnier, P.; Mallecot, F.; Duan, G.-H.; Gentner, J.-.; Fedeli, J.-M.; Olivier, S.; Descos, A.; Ben Bakir, B.; Messaoudene, S.; Bordel, D.; Malhouitre, S.; Kopp, C.; Menezo, S.

    2014-05-01

    The lack of potent integrated light emitters is one of the bottlenecks that have so far hindered the silicon photonics platform from revolutionizing the communication market. Photonic circuits with integrated light sources have the potential to address a wide range of applications from short-distance data communication to long-haul optical transmission. Notably, the integration of lasers would allow saving large assembly costs and reduce the footprint of optoelectronic products by combining photonic and microelectronic functionalities on a single chip. Since silicon and germanium-based sources are still in their infancy, hybrid approaches using III-V semiconductor materials are currently pursued by several research laboratories in academia as well as in industry. In this paper we review recent developments of hybrid III-V/silicon lasers and discuss the advantages and drawbacks of several integration schemes. The integration approach followed in our laboratory makes use of wafer-bonded III-V material on structured silicon-on-insulator substrates and is based on adiabatic mode transfers between silicon and III-V waveguides. We will highlight some of the most interesting results from devices such as wavelength-tunable lasers and AWG lasers. The good performance demonstrates that an efficient mode transfer can be achieved between III-V and silicon waveguides and encourages further research efforts in this direction.

  14. Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

    Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki; Park, Jae-Hyoung

    2013-01-01

    We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test. (paper)

  15. Seedless electroplating on patterned silicon

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2006-01-01

    Nickel thin films have been electrodeposited without the use of an additional seed layer, on highly doped silicon wafers. These substrates conduct sufficiently well to allow deposition using a peripherical electrical contact on the wafer. Films 2 μm thick have been deposited using a nickel sulfamate

  16. Sequential plasma activation methods for hydrophilic direct bonding at sub-200 °C

    He, Ran; Yamauchi, Akira; Suga, Tadatomo

    2018-02-01

    We present our newly developed sequential plasma activation methods for hydrophilic direct bonding of silica glasses and thermally grown SiO2 films. N2 plasma was employed to introduce a metastable oxynitride layer on wafer surfaces for the improvement of bond energy. By using either O2-plasma/N2-plasma/N-radical or N2-plasma/N-radical sequential activation, the quartz-quartz bond energy was increased from 2.7 J/m2 to close to the quartz bulk fracture energy that was estimated to be around 9.0 J/m2 after post-bonding annealing at 200 °C. The silicon bulklike bond energy between thermal SiO2 films was also obtained. We suggest that the improvement is attributable to surface modification such as N-related defect formation and asperity softening by the N2 plasma surface treatment.

  17. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  18. A review of recent progress in heterogeneous silicon tandem solar cells

    Yamaguchi, Masafumi; Lee, Kan-Hua; Araki, Kenji; Kojima, Nobuaki

    2018-04-01

    Silicon solar cells are the most established solar cell technology and are expected to dominate the market in the near future. As state-of-the-art silicon solar cells are approaching the Shockley-Queisser limit, stacking silicon solar cells with other photovoltaic materials to form multi-junction devices is an obvious pathway to further raise the efficiency. However, many challenges stand in the way of fully realizing the potential of silicon tandem solar cells because heterogeneously integrating silicon with other materials often degrades their qualities. Recently, above or near 30% silicon tandem solar cell has been demonstrated, showing the promise of achieving high-efficiency and low-cost solar cells via silicon tandem. This paper reviews the recent progress of integrating solar cell with other mainstream solar cell materials. The first part of this review focuses on the integration of silicon with III-V semiconductor solar cells, which is a long-researched topic since the emergence of III-V semiconductors. We will describe the main approaches—heteroepitaxy, wafer bonding and mechanical stacking—as well as other novel approaches. The second part introduces the integration of silicon with polycrystalline thin-film solar cells, mainly perovskites on silicon solar cells because of its rapid progress recently. We will also use an analytical model to compare the material qualities of different types of silicon tandem solar cells and project their practical efficiency limits.

  19. BONDING ALUMINUM METALS

    Noland, R.A.; Walker, D.E.

    1961-06-13

    A process is given for bonding aluminum to aluminum. Silicon powder is applied to at least one of the two surfaces of the two elements to be bonded, the two elements are assembled and rubbed against each other at room temperature whereby any oxide film is ruptured by the silicon crystals in the interface; thereafter heat and pressure are applied whereby an aluminum-silicon alloy is formed, squeezed out from the interface together with any oxide film, and the elements are bonded.

  20. Transformational silicon electronics

    Rojas, Jhonathan Prieto

    2014-02-25

    In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

  1. Characterizing SOI Wafers By Use Of AOTF-PHI

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  2. Quasimetallic silicon micromachined photonic crystals

    Temelkuran, B.; Bayindir, Mehmet; Ozbay, E.; Kavanaugh, J. P.; Sigalas, M. M.; Tuttle, G.

    2001-01-01

    We report on fabrication of a layer-by-layer photonic crystal using highly doped silicon wafers processed by semiconductor micromachining techniques. The crystals, built using (100) silicon wafers, resulted in an upper stop band edge at 100 GHz. The transmission and defect characteristics of these structures were found to be analogous to metallic photonic crystals. We also investigated the effect of doping concentration on the defect characteristics. The experimental results agree well with predictions of the transfer matrix method simulations

  3. Proposed method of assembly for the BCD silicon strip vertex detector modules

    Lindenmeyer, C.

    1989-01-01

    The BCD Silicon strip Vertex Detector is constructed of 10 identical central region modules and 18 similar forward region modules. This memo describes a method of assembling these modules from individual silicon wafers. Each wafer is fitted with associated front end electronics and cables and has been tested to insure that only good wafers reach the final assembly stage. 5 figs

  4. Hybrid integrated single-wavelength laser with silicon micro-ring reflector

    Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

    2018-02-01

    A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

  5. Increasing the efficiency of silicon heterojunction solar cells and modules by light soaking

    Kobayashi, Eiji; De Wolf, Stefaan; Levrat, Jacques; Descoeudres, Antoine; Despeisse, Matthieu; Haug, Franz-Josef; Ballif, Christophe

    2017-01-01

    Silicon heterojunction solar cells use crystalline silicon (c-Si) wafers as optical absorbers and employ bilayers of doped/intrinsic hydrogenated amorphous silicon (a-Si:H) to form passivating contacts. Recently, we demonstrated that such solar

  6. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  7. Low-Temperature Cu-Cu Bonding Using Silver Nanoparticles Fabricated by Physical Vapor Deposition

    Wu, Zijian; Cai, Jian; Wang, Junqiang; Geng, Zhiting; Wang, Qian

    2018-02-01

    Silver nanoparticles (Ag NPs) fabricated by physical vapor deposition (PVD) were introduced in Cu-Cu bonding as surface modification layer. The bonding structure consisted of a Ti adhesive/barrier layer and a Cu substrate layer was fabricated on the silicon wafer. Ag NPs were deposited on the Cu surface by magnetron sputtering in a high-pressure environment and a loose structure with NPs was obtained. Shear tests were performed after bonding, and the influences of PVD pressure, bonding pressure, bonding temperature and annealing time on shear strength were assessed. Cu-Cu bonding with Ag NPs was accomplished at 200°C for 3 min under the pressure of 30 MPa without a post-annealing process, and the average bonding strength of 13.99 MPa was reached. According to cross-sectional observations, a void-free bonding interface with an Ag film thickness of around 20 nm was achieved. These results demonstrated that a reliable low-temperature short-time Cu-Cu bonding was realized by the sintering process of Ag NPs between the bonding pairs, which indicated that this bonding method could be a potential candidate for future ultra-fine pitch 3D integration.

  8. Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

    Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

    2018-08-01

    In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

  9. Design, simulation and fabrication of a flexible bond pad with a hollow annular protuberance to improve the thermal fatigue lifetime for through-silicon vias

    Wang, Guilian; Ding, Guifu; Luo, Jiangbo; Niu, Di; Zhao, Junhong; Zhao, Xiaolin; Wang, Yan; Liu, Rui

    2014-01-01

    This paper presents a flexible bond pad (FBP) with a hollow annular protuberance to improve the thermal fatigue lifetime for its application to through-silicon vias (TSVs). The hollow annular protuberance structure across the interface between the filled copper in TSV and silicon substrate not only isolates the FBP from stress/strain concentration regions (the corners of the TSV) but also disperses TSV-induced deformation. The plastic strain distributions of the FBP and conventional plate-type bond pad (CPBP) were simulated by finite element method (FEM) under the temperature cycles. Based on the simulation results, the thermal fatigue lifetimes of the CPBP and the FBP with different TSV diameters were predicted by the Coffin–Manson equation. The results indicate that thermal fatigue lifetimes of the FBP are significantly greater than those of the CPBP and their fatigue lifetimes both decrease with the increase of TSV diameter. To examine the reliability of the predicted results, the CPBP and the FBP with TSV diameter of 100 µm were fabricated by MEMS technology and temperature cycling tests (TCTs) were performed to obtain their thermal fatigue lifetimes. The test results are in good agreement with the numerical simulation results, and it shows that the proposed FBP can effectively improve the thermal fatigue lifetime for TSVs. (paper)

  10. Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

    Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

    2015-08-01

    Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F-) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F-, smaller azimuth angle of Fsbnd Ag(T4)sbnd Si, shorter bond length of Fsbnd Si compared with Fsbnd Ag. As F- was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF4 when it bonded with enough F- while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F- to Si.

  11. Estimation of interface resistivity in bonded Si for the development of high performance radiation detectors

    Kanno, Ikuo; Yamashita, Makoto; Nomiya, Seiichiro; Onabe, Hideaki

    2007-01-01

    For the development of high performance radiation detectors, direct bonding of Si wafers would be an useful method. Previously, p-n bonded Si were fabricated and they showed diode characteristics. The interface resistivity was, however, not investigated in detail. For the study of interface resistivity, n-type Si wafers with different resistivities were bonded. The resistivity of bonded Si wafers were measured and the interface resistivity was estimated by comparing with the results of model calculations. (author)

  12. Development and Property Evaluation of Selected HfO2-Silicon and Rare Earth-Silicon Based Bond Coats and Environmental Barrier Coating Systems for SiC/SiC Ceramic Matrix Composites

    Zhu, Dongming

    2016-01-01

    Ceramic environmental barrier coatings (EBC) and SiC/SiC ceramic matrix composites (CMCs) will play a crucial role in future aircraft propulsion systems because of their ability to significantly increase engine operating temperatures, improve component durability, reduce engine weight and cooling requirements. Advanced EBC systems for SiC/SiC CMC turbine and combustor hot section components are currently being developed to meet future turbine engine emission and performance goals. One of the significant material development challenges for the high temperature CMC components is to develop prime-reliant, high strength and high temperature capable environmental barrier coating bond coat systems, since the current silicon bond coat cannot meet the advanced EBC-CMC temperature and stability requirements. In this paper, advanced NASA HfO2-Si and rare earth Si based EBC bond coat EBC systems for SiC/SiC CMC combustor and turbine airfoil applications are investigated. High temperature properties of the advanced EBC systems, including the strength, fracture toughness, creep and oxidation resistance have been studied and summarized. The advanced NASA EBC systems showed some promise to achieve 1500C temperature capability, helping enable next generation turbine engines with significantly improved engine component temperature capability and durability.

  13. Porous Silicon Nanowires

    Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

    2011-01-01

    In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

  14. Surface Passivation for Silicon Heterojunction Solar Cells

    Deligiannis, D.

    2017-01-01

    Silicon heterojunction solar cells (SHJ) are currently one of the most promising solar cell technologies in the world. The SHJ solar cell is based on a crystalline silicon (c-Si) wafer, passivated on both sides with a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer. Subsequently, p-type

  15. 29-Silicon NMR evidence for the improved chromatographic siloxane bond stability of bulky alkylsilane ligands on a silica surface

    Scholten, A.B.; Haan, de J.W.; Claessens, H.A.; Ven, van de L.J.M.; Cramers, C.A.

    1994-01-01

    A stable bond stationary phase for reversed-phase HPLC, with a diisobutyl-n-octadecylsilane derivatized surface, was studied using 29Si CPMAS NMR. Fumed silica surfaces (Aerosil), trimethylsilylated to different extents, were used to illustrate the effect of ligand surface loading on the hydrogen

  16. Liquid phase epitaxial growth of silicon on porous silicon for photovoltaic applications

    Berger, S.; Quoizola, S.; Fave, A.; Kaminski, A.; Perichon, S.; Barbier, D.; Laugier, A.

    2001-01-01

    The aim of this experiment is to grow a thin silicon layer ( 2 atmosphere, and finally LPE silicon growth with different temperature profiles in order to obtain a silicon layer on the sacrificial porous silicon (p-Si). We observed a pyramidal growth on the surface of the (100) porous silicon but the coalescence was difficult to obtain. However, on a p-Si (111) oriented wafer, homogeneous layers were obtained. (orig.)

  17. Trace analysis for 300 MM wafers and processes with TXRF

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  18. Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

    Haneveld, J.; Berenschot, Johan W.; Maury, P.A.; Jansen, Henricus V.

    2005-01-01

    A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7-20 nm wide, 40-100 nm high and centimeters long. All dimensions are easily

  19. Silicon nitride films fabricated by a plasma-enhanced chemical vapor deposition method for coatings of the laser interferometer gravitational wave detector

    Pan, Huang-Wei; Kuo, Ling-Chi; Huang, Shu-Yu; Wu, Meng-Yun; Juang, Yu-Hang; Lee, Chia-Wei; Chen, Hsin-Chieh; Wen, Ting Ting; Chao, Shiuh

    2018-01-01

    Silicon is a potential substrate material for the large-areal-size mirrors of the next-generation laser interferometer gravitational wave detector operated in cryogenics. Silicon nitride thin films uniformly deposited by a chemical vapor deposition method on large-size silicon wafers is a common practice in the silicon integrated circuit industry. We used plasma-enhanced chemical vapor deposition to deposit silicon nitride films on silicon and studied the physical properties of the films that are pertinent to application of mirror coatings for laser interferometer gravitational wave detectors. We measured and analyzed the structure, optical properties, stress, Young's modulus, and mechanical loss of the films, at both room and cryogenic temperatures. Optical extinction coefficients of the films were in the 10-5 range at 1550-nm wavelength. Room-temperature mechanical loss of the films varied in the range from low 10-4 to low 10-5 within the frequency range of interest. The existence of a cryogenic mechanical loss peak depended on the composition of the films. We measured the bond concentrations of N - H , Si - H , Si - N , and Si - Si bonds in the films and analyzed the correlations between bond concentrations and cryogenic mechanical losses. We proposed three possible two-level systems associated with the N - H , Si - H , and Si - N bonds in the film. We inferred that the dominant source of the cryogenic mechanical loss for the silicon nitride films is the two-level system of exchanging position between a H+ and electron lone pair associated with the N - H bond. Under our deposition conditions, superior properties in terms of high refractive index with a large adjustable range, low optical absorption, and low mechanical loss were achieved for films with lower nitrogen content and lower N - H bond concentration. Possible pairing of the silicon nitride films with other materials in the quarter-wave stack is discussed.

  20. Silicon nanowire-based solar cells

    Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S [Institute of Photonic Technology, Albert-Einstein-Strasse 9, D-07745 Jena (Germany)], E-mail: thomas.stelzner@ipht-jena.de

    2008-07-23

    The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm{sup 2} open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm{sup -2} were obtained.

  1. Silicon nanowire-based solar cells

    Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S

    2008-01-01

    The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm 2 open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm -2 were obtained

  2. Temperature Dependent Electrical Properties of PZT Wafer

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  3. Electrical, structural, and bonding changes induced in silicon by H, Ar, and Kr ion-beam etching

    Singh, R.; Fonash, S.J.; Ashok, S.; Caplan, P.; Shappirio, J.; Hage-Ali, M.; Ponpon, J.

    1983-01-01

    A study to elucidate the role of processing-induced changes in Si, subjected to ion-beam etching has been made. It is shown that these changes can be related to the primary ion beam used in ion-beam etching. Using ESR, trivalently bonded Si has been shown to be present. Fe and Cr have been found to be the main contaminants. An annealing study revealed that the damage can be annealed out at relatively high temperatures

  4. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

    Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

    2013-11-22

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  5. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  6. Characterization of electrical and optical properties of silicon based materials

    Jia, Guobin

    2009-12-04

    characteristic DRL lines D1 to D4 has been detected, indicating the dislocations in the Alile sample are relatively clean. Test p-n junction diodes with dislocation networks (DNs) produced by silicon wafer direct bonding have been investigated by EBIC technique. Charge carriers collection and electrical conduction phenomena by the DNs were observed. Inhomogeneities in the charge collection were detected in n- and p-type samples under appropriate beam energy. The diffusion lengths in the thin top layer of silicon-on-insulator (SOI) have been measured by EBIC with full suppression of the surface recombination at the buried oxide (BOX) layer and at surface of the top layer by biasing method. The measured diffusion length is several times larger than the layer thickness. Silicon nanostructures are another important subject of this work. Electrical and optical properties of various silicon based materials like silicon nanowires, silicon nano rods, porous silicon, and Si/SiO{sub 2} multi quantum wells (MQWs) samples were investigated in this work. Silicon sub-bandgap infrared (IR) luminescence around 1570 nm was found in silicon nanowires, nano rods and porous silicon. PL measurements with samples immersed in different liquid media, for example, in aqueous HF (50%), concentrated H{sub 2}SO{sub 4} (98%) and H{sub 2}O{sub 2} established that the subbandgap IR luminescence originated from the Si/SiO{sub x} interface. EL in the sub-bandgap IR range has been observed in simple devices prepared on porous silicon and MQWs at room temperature. (orig.)

  7. High energy X-ray diffraction analysis of strain and residual stress in silicon nitride ceramic diffusion bonds

    Vila, M.; Prieto, C.; Miranzo, P.; Osendi, M.I.; Terry, A.E.; Vaughan, G.B.M.

    2005-01-01

    High resolution X-ray scanning diffractometry is used to study the residual stress in binary metal/ceramic (Ni/Si 3 N 4 ) diffusion bonds fabricated by simultaneous high temperature heating and uniaxial pressing. In order to diminish the experimental error on the stress determination, the method consists of three steps: (i) to measure the axial and radial strains following some selected lines at the inner volume of the ceramic; (ii) to fit the strain data using finite element method (FEM) analysis and (iii) to determinate stresses by using the results obtained from the FEM method in the strain calculation

  8. Hydrides of Alkaline Earth–Tetrel (AeTt) Zintl Phases: Covalent Tt–H Bonds from Silicon to Tin

    Auer, Henry; Guehne, Robin; Bertmer, Marko; Weber, Sebastian; Wenderoth, Patrick; Hansen, Thomas Christian; Haase, Jürgen; Kohlmann, Holger (Leipzig); (Saarland-MED); (ILL)

    2017-01-18

    Zintl phases form hydrides either by incorporating hydride anions (interstitial hydrides) or by covalent bonding of H to the polyanion (polyanionic hydrides), which yields a variety of different compositions and bonding situations. Hydrides (deuterides) of SrGe, BaSi, and BaSn were prepared by hydrogenation (deuteration) of the CrB-type Zintl phases AeTt and characterized by laboratory X-ray, synchrotron, and neutron diffraction, NMR spectroscopy, and quantum-chemical calculations. SrGeD4/3–x and BaSnD4/3–x show condensed boatlike six-membered rings of Tt atoms, formed by joining three of the zigzag chains contained in the Zintl phase. These new polyanionic motifs are terminated by covalently bound H atoms with d(Ge–D) = 1.521(9) Å and d(Sn–D) = 1.858(8) Å. Additional hydride anions are located in Ae4 tetrahedra; thus, the features of both interstitial hydrides and polyanionic hydrides are represented. BaSiD2–x retains the zigzag Si chain as in the parent Zintl phase, but in the hydride (deuteride), it is terminated by H (D) atoms, thus forming a linear (SiD) chain with d(Si–D) = 1.641(5) Å.

  9. III-V-on-silicon solar cells reaching 33% photoconversion efficiency in two-terminal configuration

    Cariou, Romain; Benick, Jan; Feldmann, Frank; Höhn, Oliver; Hauser, Hubert; Beutel, Paul; Razek, Nasser; Wimplinger, Markus; Bläsi, Benedikt; Lackner, David; Hermle, Martin; Siefer, Gerald; Glunz, Stefan W.; Bett, Andreas W.; Dimroth, Frank

    2018-04-01

    Silicon dominates the photovoltaic industry but the conversion efficiency of silicon single-junction solar cells is intrinsically constrained to 29.4%, and practically limited to around 27%. It is possible to overcome this limit by combining silicon with high-bandgap materials, such as III-V semiconductors, in a multi-junction device. Significant challenges associated with this material combination have hindered the development of highly efficient III-V/Si solar cells. Here, we demonstrate a III-V/Si cell reaching similar performances to standard III-V/Ge triple-junction solar cells. This device is fabricated using wafer bonding to permanently join a GaInP/GaAs top cell with a silicon bottom cell. The key issues of III-V/Si interface recombination and silicon's weak absorption are addressed using poly-silicon/SiOx passivating contacts and a novel rear-side diffraction grating for the silicon bottom cell. With these combined features, we demonstrate a two-terminal GaInP/GaAs//Si solar cell reaching a 1-sun AM1.5G conversion efficiency of 33.3%.

  10. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  11. Performance characterization of silicon pore optics

    Collon, M. J.; Kraft, S.; Günther, R.; Maddox, E.; Beijersbergen, M.; Bavdaz, M.; Lumb, D.; Wallace, K.; Krumrey, M.; Cibik, L.; Freyberg, M.

    2006-06-01

    The characteristics of the latest generation of assembled silicon pore X-ray optics are discussed in this paper. These very light, stiff and modular high performance pore optics (HPO) have been developed [1] for the next generation of astronomical X-ray telescopes, which require large collecting areas whilst achieving angular resolutions better than 5 arcseconds. The suitability of 12 inch silicon wafers as high quality optical mirrors and the automated assembly process are discussed elsewhere in this conference. HPOs with several tens of ribbed silicon plates are assembled by bending the plates into an accurate cylindrical shape and directly bonding them on top of each other. The achievable figure accuracy is measured during assembly and in test campaigns at X-ray testing facilities like BESSY-II and PANTER. Pencil beam measurements allow gaining information on the quality achieved by the production process with high spatial resolution. In combination with full beam illumination a complete picture of the excellent performance of these optics can be derived. Experimental results are presented and discussed in detail. The results of such campaigns are used to further improve the production process in order to match the challenging XEUS requirements [2] for imaging resolution and mass.

  12. Physical and electrical characteristics of silicon oxynitride films with various refractive indices

    Liao, Jeng-Hwa; Hsieh, Jung-Yu; Lin, Hsing-Ju; Tang, Wei-Yao; Chiang, Chun-Ling; Yang, Ling-Wu; Yang, Tahone; Chen, Kuang-Chao; Lu, Chih-Yuan [Macronix International Co. Ltd, No 16, Li-Hsin Road, Hsinchu Science Park, Hsinchu 300, Taiwan (China); Lo, Yun-Shan; Wu, Tai-Bor, E-mail: jhliao@mxic.com.t [Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 300, Taiwan (China)

    2009-09-07

    This study explores the relationship between both the physical and the electrical characteristics of silicon oxynitride (SiON) films and the refractive index. The single wafer rapid thermal process modules were used for low pressure chemical vapour deposition of SiON films. A series of SiON films with refractive index between 1.50 and 1.83 were fabricated. Fourier transform infrared absorption spectroscopy and x-ray photoelectron spectroscopy identified the chemical bonding configurations of different SiON films: the Si-N bonds are replaced by Si-O bonds as the refractive index of the SiON films declines. Moreover, the Si atomic ratio is kept between 35% and 40% while the oxygen atomic ratio increases and the nitrogen atomic ratio decreases as the refractive index of the SiON film declines. The electrical characteristics of different SiON-based silicon-oxide-nitride-oxide-silicon (SONOS) devices suggest that (1) the dielectric constant increases with increasing refractive index of the SiON film and (2) the charge-trap density is inversely proportional to the oxygen concentration in the SiON film. Based on these results, the SiON films with various refractive indices can provide a wider application for silicon-based devices, such as SONOS and MOS devices.

  13. Physical and electrical characteristics of silicon oxynitride films with various refractive indices

    Liao, Jeng-Hwa; Hsieh, Jung-Yu; Lin, Hsing-Ju; Tang, Wei-Yao; Chiang, Chun-Ling; Yang, Ling-Wu; Yang, Tahone; Chen, Kuang-Chao; Lu, Chih-Yuan; Lo, Yun-Shan; Wu, Tai-Bor

    2009-01-01

    This study explores the relationship between both the physical and the electrical characteristics of silicon oxynitride (SiON) films and the refractive index. The single wafer rapid thermal process modules were used for low pressure chemical vapour deposition of SiON films. A series of SiON films with refractive index between 1.50 and 1.83 were fabricated. Fourier transform infrared absorption spectroscopy and x-ray photoelectron spectroscopy identified the chemical bonding configurations of different SiON films: the Si-N bonds are replaced by Si-O bonds as the refractive index of the SiON films declines. Moreover, the Si atomic ratio is kept between 35% and 40% while the oxygen atomic ratio increases and the nitrogen atomic ratio decreases as the refractive index of the SiON film declines. The electrical characteristics of different SiON-based silicon-oxide-nitride-oxide-silicon (SONOS) devices suggest that (1) the dielectric constant increases with increasing refractive index of the SiON film and (2) the charge-trap density is inversely proportional to the oxygen concentration in the SiON film. Based on these results, the SiON films with various refractive indices can provide a wider application for silicon-based devices, such as SONOS and MOS devices.

  14. Thermal effects on the mechanical properties of SiC fibre reinforced reaction-bonded silicon nitride matrix composites

    Bhatt, R. T.; Phillips, R. E.

    1990-01-01

    The elevated temperature four-point flexural strength and the room temperature tensile and flexural strength properties after thermal shock were measured for ceramic composites consisting of 30 vol pct uniaxially aligned 142 micron diameter SiC fibers in a reaction bonded Si3N4 matrix. The elevated temperature strengths were measured after 15 min of exposure in air at temperatures to 1400 C. Thermal shock treatment was accomplished by heating the composite in air for 15 min at temperatures to 1200 C and then quenching in water at 25 C. The results indicate no significant loss in strength properties either at temperature or after thermal shock when compared with the strength data for composites in the as-fabricated condition.

  15. Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

    Kae Dal Kwack

    2011-01-01

    Full Text Available A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

  16. Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

    Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

    2011-01-01

    A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

  17. Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

    Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

    2011-01-01

    A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light. PMID:22319353

  18. Laser plasma generation of hydrogen-free diamond-like carbon thin films on Zr-2.5Nb CANDU pressure tube materials and silicon wafers with a pulsed high-power CO2 laser

    Ebrahim, N.A.; Mouris, J.F.; Hoffmann, C.R.J.; Davis, R.W.

    1995-06-01

    We report the first experiments on the laser plasma deposition of hydrogen-free, diamond-like carbon (DLC) films on Zr-2.5Nb CANDU pressure-tube materials and silicon substrates, using the short-pulse, high-power, CO 2 laser in the High-Power Laser Laboratory at Chalk River Laboratories. The films were (AFM). The thin films show the characteristic signature of DLC films in the Raman spectra obtained using a krypton-ion (Kr + ) laser. The Vickers ultra-low-load microhardness tests show hardness of the coated surface of approximately 7000 Kg force mm -2 , which is consistent with the hardness associated with DLC films. AFM examination of the film morphology shows diamond-like crystals distributed throughout the film, with film thicknesses of up to 0.5 μm generated with 50 laser pulses. With significantly more laser pulses, it is expected that very uniform diamond-like films would be produced. These experiments suggest that it should be possible to deposit hydrogen-free, diamond-like films of relevance to nuclear reactor components with a high-power and high-repetition-rate laser facility. (author). 7 refs., 2 tabs., 15 figs

  19. Wafer scale oblique angle plasma etching

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  20. Silicon Drift Detectors - A Novel Technology for Vertex Detectors

    Lynn, D.

    1996-10-01

    Silicon Drift Detectors (SDD) are novel position sensing silicon detectors which operate in a manner analogous to gas drift detectors. Single SDD's were shown in the CERN NA45 experiment to permit excellent spatial resolution (pseudo-rapidity. Over the last three years we undertook a concentrated R+D effort to optimize the performance of the detector by minimizing the inactive area, the operating voltage and the data volume. We will present test results from several wafer prototypes. The charge produced by the passage of ionizing particles through the bulk of the detectors is collected on segmented anodes, with a pitch of 250 μm, on the far edges of the detector. The anodes are wire-bonded to a thick film multi-chip module which contains preamplifier/shaper chips and CMOS based switched capacitor arrays used as an analog memory pipeline. The ADC is located off-detector. The complete readout chain from the wafer to the DAQ will be presented. Finally we will show physics performance simulations based on the resolution achieved by the SVT prototypes.

  1. Silicon epitaxy on textured double layer porous silicon by LPCVD

    Cai Hong; Shen Honglie; Zhang Lei; Huang Haibin; Lu Linfeng; Tang Zhengxia; Shen Jiancang

    2010-01-01

    Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521 cm -1 have a width of 7.8 cm -1 , which reveals the high crystalline quality of the silicon epitaxy.

  2. High Speed On-Wafer Characterization Laboratory

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  3. Effects of Interface Coating and Nitride Enhancing Additive on Properties of Hi-Nicalon SiC Fiber Reinforced Reaction-Bonded Silicon Nitride Composites

    Bhatt, Ramakrishana T.; Hull, David R.; Eldridge, Jeffrey I.; Babuder, Raymond

    2000-01-01

    Strong and tough Hi-Nicalon SiC fiber reinforced reaction-bonded silicon nitride matrix composites (SiC/ RBSN) have been fabricated by the fiber lay-up approach. Commercially available uncoated and PBN, PBN/Si-rich PBN, and BN/SiC coated SiC Hi-Nicalon fiber tows were used as reinforcement. The composites contained approximately 24 vol % of aligned 14 micron diameter SiC fibers in a porous RBSN matrix. Both one- and two-dimensional composites were characterized. The effects of interface coating composition, and the nitridation enhancing additive, NiO, on the room temperature physical, tensile, and interfacial shear strength properties of SiC/RBSN matrix composites were evaluated. Results indicate that for all three coated fibers, the thickness of the coatings decreased from the outer periphery to the interior of the tows, and that from 10 to 30 percent of the fibers were not covered with the interface coating. In the uncoated regions, chemical reaction between the NiO additive and the SiC fiber occurs causing degradation of tensile properties of the composites. Among the three interface coating combinations investigated, the BN/SiC coated Hi-Nicalon SiC fiber reinforced RBSN matrix composite showed the least amount of uncoated regions and reasonably uniform interface coating thickness. The matrix cracking stress in SiC/RBSN composites was predicted using a fracture mechanics based crack bridging model.

  4. Knudsen pump produced via silicon deep RIE, thermal oxidation, and anodic bonding processes for on-chip vacuum pumping

    Van Toan, Nguyen; Inomata, Naoki; Trung, Nguyen Huu; Ono, Takahito

    2018-05-01

    This work describes the fabrication and evaluation of the Knudsen pump for on-chip vacuum pumping that works based on the principle of a thermal transpiration. Three AFM (atomic force microscope) cantilevers are integrated into small chambers with a size of 5 mm  ×  3 mm  ×  0.4 mm for the pump’s evaluation. Knudsen pump is fabricated using deep RIE (reactive ion etching), wet thermal oxidation and anodic bonding processes. The fabricated device is evaluated by monitoring the quality (Q) factor of the integrated cantilevers. The Q factor of the cantilever is increased from 300 -1150 in cases without and with a temperature difference approximately 25 °C between the top (the hot side at 40 °C) and bottom (the cold side at 15 °C) sides of the fabricated device, respectively. The evacuated chamber pressure of around 10 kPa is estimated from the Q factor of the integrated cantilevers.

  5. Multiproject wafers: not just for million-dollar mask sets

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  6. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  7. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  8. Polycrystalline Silicon Gettered by Porous Silicon and Heavy Phosphorous Diffusion

    LIU Zuming(刘祖明); Souleymane K Traore; ZHANG Zhongwen(张忠文); LUO Yi(罗毅)

    2004-01-01

    The biggest barrier for photovoltaic (PV) utilization is its high cost, so the key for scale PV utilization is to further decrease the cost of solar cells. One way to improve the efficiency, and therefore lower the cost, is to increase the minority carrier lifetime by controlling the material defects. The main defects in grain boundaries of polycrystalline silicon gettered by porous silicon and heavy phosphorous diffusion have been studied. The porous silicon was formed on the two surfaces of wafers by chemical etching. Phosphorous was then diffused into the wafers at high temperature (900℃). After the porous silicon and diffusion layers were removed, the minority carrier lifetime was measured by photo-conductor decay. The results show that the lifetime's minority carriers are increased greatly after such treatment.

  9. Proof of concept of an epitaxy-free layer-transfer process for silicon solar cells based on the reorganisation of macropores upon annealing

    Depauw, V.; Gordon, I.; Beaucarne, G.; Poortmans, J.; Mertens, R.; Celis, J.-P.

    2009-01-01

    To answer the challenge of less expensive renewable electricity, the photovoltaics community is focusing on producing thinner silicon solar cells. A few years ago, in the field of silicon-on-nothing structures, micron-thick monocrystalline layers suspended over their parent wafer were produced by high-temperature annealing of specific arrays of macropores. Those macropores reorganise into one single void and leave a thin overlayer on top. Since this method may be an inexpensive way of fabricating high-quality silicon films, this paper investigates its potential for photovoltaic applications. In particular, we investigated if large surfaces can be produced and transferred to foreign substrates with this method. We fabricated basic solar cells, without rear-surface passivation, on 5 cm x 5 cm-large and 1-μm-thick films transferred to glass, that showed energy-conversion efficiencies up to 2.6%. These cells demonstrate the feasibility of the presented concept as a layer-transfer process for solar-cell application. After formation by annealing, the film is only barely attached to its parent wafer, but can still safely be handled provided that any abrupt gas flow or pumping to vacuum is avoided. After transfer and permanent bonding, the sample can be handled as any bulk wafer.

  10. Reduction of absorption loss in multicrystalline silicon via combination of mechanical grooving and porous silicon

    Ben Rabha, Mohamed; Mohamed, Seifeddine Belhadj; Dimassi, Wissem; Gaidi, Mounir; Ezzaouia, Hatem; Bessais, Brahim [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, Technopole de Borj-Cedria, BP 95, 2050 Hammam-Lif (Tunisia)

    2011-03-15

    Surface texturing of silicon wafer is a key step to enhance light absorption and to improve the solar cell performances. While alkaline-texturing of single crystalline silicon wafers was well established, no efficient chemical solution has been successfully developed for multicrystalline silicon wafers. Thus, the use of alternative new methods for effective texturization of multicrystalline silicon is worth to be investigated. One of the promising texturing techniques of multicrystalline silicon wafers is the use of mechanical grooves. However, most often, physical damages occur during mechanical grooves of the wafer surface, which in turn require an additional step of wet processing-removal damage. Electrochemical surface treatment seems to be an adequate solution for removing mechanical damage throughout porous silicon formation. The topography of untreated and porous silicon-treated mechanically textured surface was investigated using scanning electron microscopy (SEM). As a result of the electrochemical surface treatment, the total reflectivity drops to about 5% in the 400-1000 nm wavelength range and the effective minority carrier diffusion length enhances from 190 {mu}m to about 230 {mu}m (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  11. Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

    Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

    2017-09-01

    The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

  12. Design, development and tests of high-performance silicon vapor chamber

    Cai, Qingjun; Chen, Bing-chung; Tsai, Chialun

    2012-01-01

    This paper presents a novel triple stack process to develop an all-silicon thermal ground plane (TGP) vapor chamber that enables fabrication of compact, large scale, low thermal expansion coefficient mismatch and high-performance heat transfer devices. The TGP vapor chamber is formed through bonding three etched silicon wafers. On both the top and bottom wafers, microscale and high aspect ratio wick structures are etched for liquid transport. The 1.5 mm thick middle layer contains the cavities for vapor flow. To achieve hermetic seal, glass frit with four sealing rings, approximately 300 µm wide and 30 µm thick, is used to bond the edges and supporting posts. For experimental evaluations, 3 mm × 38 mm × 38 mm TGP vapor chambers are developed. The volume density of the heat transfer device is approximately 1.5 × 10 3 kg m −3 . Measurement of mass loss and stability studies of heat transfer indicates that the vapor chamber system is hermetically sealed. Using ethanol as the operating liquid, high heat transfer performance is demonstrated. Effective thermal conductivity reaches over 2500 W m −1  ⋅ K −1 . Under high g environment, experimental results show good liquid transport capabilities of the wick structures. (paper)

  13. Design, development and tests of high-performance silicon vapor chamber

    Cai, Qingjun; Chen, Bing-chung; Tsai, Chialun

    2012-03-01

    This paper presents a novel triple stack process to develop an all-silicon thermal ground plane (TGP) vapor chamber that enables fabrication of compact, large scale, low thermal expansion coefficient mismatch and high-performance heat transfer devices. The TGP vapor chamber is formed through bonding three etched silicon wafers. On both the top and bottom wafers, microscale and high aspect ratio wick structures are etched for liquid transport. The 1.5 mm thick middle layer contains the cavities for vapor flow. To achieve hermetic seal, glass frit with four sealing rings, approximately 300 µm wide and 30 µm thick, is used to bond the edges and supporting posts. For experimental evaluations, 3 mm × 38 mm × 38 mm TGP vapor chambers are developed. The volume density of the heat transfer device is approximately 1.5 × 103 kg m-3. Measurement of mass loss and stability studies of heat transfer indicates that the vapor chamber system is hermetically sealed. Using ethanol as the operating liquid, high heat transfer performance is demonstrated. Effective thermal conductivity reaches over 2500 W m-1 ṡ K-1. Under high g environment, experimental results show good liquid transport capabilities of the wick structures.

  14. Methane production using resin-wafer electrodeionization

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  15. Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

    Popovich, V.A.

    2013-01-01

    Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

  16. Silicon Nanowire Fabrication Using Edge and Corner Lithography

    Yagubizade, H.; Berenschot, Johan W.; Jansen, Henricus V.; Elwenspoek, Michael Curt; Tas, Niels Roelof

    2010-01-01

    This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features

  17. 1366 Project Silicon: Reclaiming US Silicon PV Leadership

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2016-02-16

    1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

  18. Method to improve commercial bonded SOI material

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  19. Morphological and optical properties of n-type porous silicon

    type silicon wafer have been reported in the present article. Method of PS fabrication is by photo-assisted electrochemical etching with different etching current densities ( J ). Porosity and PS layer thickness, obtained by the gravimetric method, ...

  20. Use of porous silicon to minimize oxidation induced stacking fault defects in silicon

    Shieh, S.Y.; Evans, J.W.

    1992-01-01

    This paper presents methods for minimizing stacking fault defects, generated during oxidation of silicon, include damaging the back of the wafer or depositing poly-silicon on the back. In either case a highly defective structure is created and this is capable of gettering either self-interstitials or impurities which promote nucleation of stacking fault defects. A novel method of minimizing these defects is to form a patch of porous silicon on the back of the wafer by electrochemical etching. Annealing under inert gas prior to oxidation may then result in the necessary gettering. Experiments were carried out in which wafers were subjected to this treatment. Subsequent to oxidation, the wafers were etched to remove oxide and reveal defects. The regions of the wafer adjacent to the porous silicon patch were defect-free, whereas remote regions had defects. Deep level transient spectroscopy has been used to examine the gettering capability of porous silicon, and the paper discusses the mechanism by which the porous silicon getters

  1. Fabrication of a silicon oxide stamp by edge lithography reinforced with silicon nitride for nanoimprint lithography

    Zhao, Yiping; Berenschot, Johan W.; de Boer, M.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

    2008-01-01

    The fabrication of a stamp reinforced with silicon nitride is presented for its use in nanoimprint lithography. The fabrication process is based on edge lithography using conventional optical lithography and wet anisotropic etching of 110 silicon wafers. SiO2 nano-ridges of 20 nm in width were

  2. Lightwave Circuits in Lithium Niobate through Hybrid Waveguides with Silicon Photonics.

    Weigel, Peter O; Savanier, Marc; DeRose, Christopher T; Pomerene, Andrew T; Starbuck, Andrew L; Lentine, Anthony L; Stenger, Vincent; Mookherjea, Shayan

    2016-03-01

    We demonstrate a photonic waveguide technology based on a two-material core, in which light is controllably and repeatedly transferred back and forth between sub-micron thickness crystalline layers of Si and LN bonded to one another, where the former is patterned and the latter is not. In this way, the foundry-based wafer-scale fabrication technology for silicon photonics can be leveraged to form lithium-niobate based integrated optical devices. Using two different guided modes and an adiabatic mode transition between them, we demonstrate a set of building blocks such as waveguides, bends, and couplers which can be used to route light underneath an unpatterned slab of LN, as well as outside the LN-bonded region, thus enabling complex and compact lightwave circuits in LN alongside Si photonics with fabrication ease and low cost.

  3. Lightwave Circuits in Lithium Niobate through Hybrid Waveguides with Silicon Photonics

    Weigel, Peter O.; Savanier, Marc; DeRose, Christopher T.; Pomerene, Andrew T.; Starbuck, Andrew L.; Lentine, Anthony L.; Stenger, Vincent; Mookherjea, Shayan

    2016-01-01

    We demonstrate a photonic waveguide technology based on a two-material core, in which light is controllably and repeatedly transferred back and forth between sub-micron thickness crystalline layers of Si and LN bonded to one another, where the former is patterned and the latter is not. In this way, the foundry-based wafer-scale fabrication technology for silicon photonics can be leveraged to form lithium-niobate based integrated optical devices. Using two different guided modes and an adiabatic mode transition between them, we demonstrate a set of building blocks such as waveguides, bends, and couplers which can be used to route light underneath an unpatterned slab of LN, as well as outside the LN-bonded region, thus enabling complex and compact lightwave circuits in LN alongside Si photonics with fabrication ease and low cost. PMID:26927022

  4. Single crystalline silicon solar cells with rib structure

    Shuhei Yoshiba

    2017-02-01

    Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  5. Single wafer rapid thermal multiprocessing

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  6. Study of irradiation induced defects in silicon

    Pal, Gayatri; Sebastian, K.C.; Somayajulu, D.R.S.; Chintalapudi, S.N.

    2000-01-01

    Pure high resistivity (6000 ohm-cm) silicon wafers were recoil implanted with 1.8 MeV 111 In ions. As-irradiated wafers showed a 13 MHz quadrupole interaction frequency, which was not observed earlier. The annealing behaviour of these defects in the implanted wafers was studied between room temperature and 1073 K. At different annealing temperatures two more interaction frequencies corresponding to defect complexes D2 and D3 are observed. Even though the experimental conditions were different, these are identical to the earlier reported ones. Based on an empirical point charge model calculation, an attempt is made to identify the configuration of these defect complexes. (author)

  7. Effect of illumination on photoluminescence properties of porous silicon

    Naddaf, M.; Hamadeh, H.

    2008-11-01

    Porous silicon (PS) layers were formed by photo-electrochemical etching of both p-type and n-type single crystal wafers in HF based solution. During the etching process, the silicon wafer was illuminated by a halogen lamp light guided by an optical fiber through a monochromator or diode lasers at different power density and wavelengths (480,533,580 and 635 nm). The optical and structural properties of the prepared PS samples have been investigated by using temperature dependent photoluminescence (PL) spectroscopy, Fourier Transform Infrared (FTIR) spectroscopy, contact angle (CA) measurements, optical microscope and atomic force microscope (AFM). Beside the strong red-yellow PL band, a blue PL band has been observed only in the PS samples formed under the illumination with low power and short wavelengths (480-580 nm) light. In the near infrared (IR) spectral range, a new PL band at 850 nm was observed in p-type PS samples, which prepared under darkness or illumination with 635 nm of low power light. Temperature dependent PL measurements showed that, in contrast to the main IR PL band at around 1100 nm, the intensity of this new band increases on increasing the temperature. These changes in the PL properties was correlated with the illumination induced-structural and morphological modifications in the PS skeleton. In particular, the FTIR analysis showed that the chemical groups and bonds constituting the PS skeleton, such as, SiH, SiO bonds and silanol SiOH group play key role in deciding the PL emission intensity and blue shift. The study proved that the illumination parameters during the photo-electrochemical etching process can be utilized for tailoring a porous layer with novel optical and structural properties. (Authors)

  8. Effect of illumination on photoluminescence properties of porous silicon

    Naddaf, M.; Hamadeh, H.

    2009-01-01

    Porous silicon (PS) layers were formed by photo-electrochemical etching of both p-type and n-type single crystal wafers in HF based solution. During the etching process, the silicon wafer was illuminated by a halogen lamp light guided by an optical fiber through a monochromator or diode lasers at different power density and wavelengths (480,533,580 and 635 nm). The optical and structural properties of the prepared PS samples have been investigated by using temperature dependent photoluminescence (PL) spectroscopy, Fourier Transform Infrared (FTIR) spectroscopy, contact angle (CA) measurements, optical microscope and atomic force microscope (AFM). Beside the strong red-yellow PL band, a blue PL band has been observed only in the PS samples formed under the illumination with low power and short wavelengths (480-580 nm) light. In the near infrared (IR) spectral range, a new PL band at 850 nm was observed in p-type PS samples, which prepared under darkness or illumination with 635 nm of low power light. Temperature dependent PL measurements showed that, in contrast to the main IR PL band at around 1100 nm, the intensity of this new band increases on increasing the temperature. These changes in the PL properties was correlated with the illumination induced-structural and morphological modifications in the PS skeleton. In particular, the FTIR analysis showed that the chemical groups and bonds constituting the PS skeleton, such as, SiH, SiO bonds and silanol SiOH group play key role in deciding the PL emission intensity and blue shift. The study proved that the illumination parameters during the photo-electrochemical etching process can be utilized for tailoring a porous layer with novel optical and structural properties. (Authors)

  9. Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

    Cao Yuhan; Luo Le

    2009-01-01

    A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu 6 Sn 5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 x 10 -9 atm cc/s are possible, meeting the demands of MIL-STD-883E. (semiconductor technology)

  10. Modelling deformation and fracture in confectionery wafers

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  11. Switchable static friction of piezoelectric composite-silicon wafer contacts

    Ende, D.A. van den; Fischer, H.R.; Groen, W.A.; Zwaag, S. van der

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  12. Switchable static friction of piezoelectric composite—silicon wafer contacts

    Van den Ende, D.A.; Fischer, H.R.; Groen, W.A.; Van der Zwaag, S.

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  13. Improvement of multicrystalline silicon wafer solar cells by post ...

    Administrator

    post-fabrication wet-chemical etching in phosphoric acid. A MEFOUED1,2,*, M FATHI1, ... and RCA decontamination stages by putting them in a bath made of ... found to be decreasing after chemical attack as shown in figure 2. In order to ...

  14. Wafer Cakes of Improved Amino Acid Structure

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  15. On the design and implementation of a wafer yield editor

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  16. Optical and microstructural characterization of porous silicon using photoluminescence, SEM and positron annihilation spectroscopy

    Cheung, C K; Nahid, F; Cheng, C C; Beling, C D; Fung, S; Ling, C C; Djurisic, A B; Pramanik, C; Saha, H; Sarkar, C K

    2007-01-01

    We have studied the dependence of porous silicon morphology and porosity on fabrication conditions. N-type (100) silicon wafers with resistivity of 2-5 Ω cm were electrochemically etched at various current densities and anodization times. Surface morphology and the thickness of the samples were examined by scanning electron microscopy (SEM). Detailed information of the porous silicon layer morphology with variation of preparation conditions was obtained by positron annihilation spectroscopy (PAS): the depth-defect profile and open pore interconnectivity on the sample surface has been studied using a slow positron beam. Coincidence Doppler broadening spectroscopy (CDBS) was used to study the chemical environment of the samples. The presence of silicon micropores with diameter varying from 1.37 to 1.51 nm was determined by positron lifetime spectroscopy (PALS). Visible luminescence from the samples was observed, which is considered to be a combination effect of quantum confinement and the effect of Si = O double bond formation near the SiO 2 /Si interface according to the results from photoluminescence (PL) and positron annihilation spectroscopy measurements. The work shows that the study of the positronium formed when a positron is implanted into the porous surface provides valuable information on the pore distribution and open pore interconnectivity, which suggests that positron annihilation spectroscopy is a useful tool in the porous silicon micropores' characterization

  17. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  18. Compton recoil electron tracking with silicon strip detectors

    O'Neill, T.J.; Ait-Ouamer, F.; Schwartz, I.; Tumer, O.T.; White, R.S.; Zych, A.D.

    1992-01-01

    The application of silicon strip detectors to Compton gamma ray astronomy telescopes is described in this paper. The Silicon Compton Recoil Telescope (SCRT) tracks Compton recoil electrons in silicon strip converters to provide a unique direction for Compton scattered gamma rays above 1 MeV. With strip detectors of modest positional and energy resolutions of 1 mm FWHM and 3% at 662 keV, respectively, 'true imaging' can be achieved to provide an order of magnitude improvement in sensitivity to 1.6 x 10 - 6 γ/cm 2 -s at 2 MeV. The results of extensive Monte Carlo calculations of recoil electrons traversing multiple layers of 200 micron silicon wafers are presented. Multiple Coulomb scattering of the recoil electron in the silicon wafer of the Compton interaction and the next adjacent wafer is the basic limitation to determining the electron's initial direction

  19. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  20. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  1. Porous solid ion exchange wafer for immobilizing biomolecules

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  2. Carbon elimination from silicon kerf: Thermogravimetric analysis and mechanistic considerations.

    Vazquez-Pufleau, Miguel; Chadha, Tandeep S; Yablonsky, Gregory; Biswas, Pratim

    2017-01-18

    40% of ultrapure silicon is lost as kerf during slicing to produce wafers. Kerf is currently not being recycled due to engineering challenges and costs associated with removing its abundant impurities. Carbon left behind from the lubricant remains as one of the most difficult contaminants to remove in kerf without significant silicon oxidation. The present work enables to better understand the mechanism of carbon elimination in kerf which can aid the design of better processes for kef recycling and low cost photovoltaics. In this paper, we studied the kinetics of carbon elimination from silicon kerf in two atmospheres: air and N 2, under a regime of no-diffusion-limitation. We report the apparent activation energy in both atmospheres using three methods: Kissinger, and two isoconversional approaches. In both atmospheres, a bimodal apparent activation energy is observed, suggesting a two stage process. A reaction mechanism is proposed in which (a) C-C and C-O bond cleavage reactions occur in parallel with polymer formation; (b) at higher temperatures, this polymer fully degrades in air but leaves a tarry residue in N 2 that accounts for about 12% of the initial total carbon.

  3. Flexible Thermoelectric Generators on Silicon Fabric

    Sevilla, Galo T.

    2012-11-01

    In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

  4. Low temperature spalling of silicon: A crack propagation study

    Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

    2017-06-08

    Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.

  5. Nanoshaving and Nanografting of Water Soluble Polymers on Glass and Silicon Dioxide Surfaces with Applications to DNA Localization

    Davis, Brian; Conley, Hiram; Ochoa, Rosie; Hurd, Katie; Linford, Matthew R.; Davis, Robert C.

    2008-10-01

    Chemical surface patterning at the nanoscale is a critical component of chemically directed assembly of nanoscale devices or sensitive biological molecules onto surfaces. Here we present a scanning probe lithography technique that allows for patterning of aqueous polymers on glass or silicon dioxide surfaces. The surfaces were functionalized by covalently bonding a silane monolayer with a known surface charge to either a glass slide or a silicon wafer. A polymer layer less then 2 nm in thickness was electrostatically bound to the silane layer, passivating the functionalized surface. An Atomic Force Microscope (AFM) probe was used to remove a portion of the polymer layer, exposing the functional silane layer underneath. Employing this method we made chemically active submicron regions. These regions were backfilled with a fluorescent polymer and Lambda-DNA. Chemical differentiation was verified through tapping mode AFM and optical fluorescent microscopy. Lines with a pitch as small as 20nm were observed with AFM height and phase mode data.

  6. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  7. 120 mm Single-crystalline perovskite and wafers: towards viable applications

    Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

    2017-01-01

    As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75% RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

  8. Note: Anodic bonding with cooling of heat-sensitive areas

    Vesborg, Peter Christian Kjærgaard; Olsen, Jakob Lind; Henriksen, Toke Riishøj

    2010-01-01

    Anodic bonding of silicon to glass always involves heating the glass and device to high temperatures so that cations become mobile in the electric field. We present a simple way of bonding thin silicon samples to borosilicate glass by means of heating from the glass side while locally cooling hea......-sensitive areas from the silicon side. Despite the high thermal conductivity of silicon, this method allows a strong anodic bond to form just millimeters away from areas essentially at room temperature....

  9. Porous silicon carbide (SIC) semiconductor device

    Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

    1996-01-01

    Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

  10. Floating Silicon Method

    Kellerman, Peter

    2013-12-21

    The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

  11. Hydrogen-induced structural changes in polycrystalline silicon as revealed by positron lifetime spectroscopy

    Arole, V.M.; Takwale, M.G.; Bhide, V.G.

    1989-01-01

    Hydrogen passivation of polycrystalline silicon wafer is carried out in order to reduce the deleterious effects of grain boundaries. A systematic variation is made in the process parameters implemented during hydrogen passivation and the results of room temperature resistivity measurements are reported. As an efficient tool to study the structure change, positron lifetime spectroscopic measurements are performed on original and hydrogenated polycrystalline silicon wafers and a systematic correlation is sought between the changes that take place in the electrical and structural properties of polycrystalline silicon wafer, brought about by hydrogen passivation. (author)

  12. Hollow Microtube Resonators via Silicon Self-Assembly toward Subattogram Mass Sensing Applications.

    Kim, Joohyun; Song, Jungki; Kim, Kwangseok; Kim, Seokbeom; Song, Jihwan; Kim, Namsu; Khan, M Faheem; Zhang, Linan; Sader, John E; Park, Keunhan; Kim, Dongchoul; Thundat, Thomas; Lee, Jungchul

    2016-03-09

    Fluidic resonators with integrated microchannels (hollow resonators) are attractive for mass, density, and volume measurements of single micro/nanoparticles and cells, yet their widespread use is limited by the complexity of their fabrication. Here we report a simple and cost-effective approach for fabricating hollow microtube resonators. A prestructured silicon wafer is annealed at high temperature under a controlled atmosphere to form self-assembled buried cavities. The interiors of these cavities are oxidized to produce thin oxide tubes, following which the surrounding silicon material is selectively etched away to suspend the oxide tubes. This simple three-step process easily produces hollow microtube resonators. We report another innovation in the capping glass wafer where we integrate fluidic access channels and getter materials along with residual gas suction channels. Combined together, only five photolithographic steps and one bonding step are required to fabricate vacuum-packaged hollow microtube resonators that exhibit quality factors as high as ∼ 13,000. We take one step further to explore additionally attractive features including the ability to tune the device responsivity, changing the resonator material, and scaling down the resonator size. The resonator wall thickness of ∼ 120 nm and the channel hydraulic diameter of ∼ 60 nm are demonstrated solely by conventional microfabrication approaches. The unique characteristics of this new fabrication process facilitate the widespread use of hollow microtube resonators, their translation between diverse research fields, and the production of commercially viable devices.

  13. Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

    Liu Haijun

    2015-12-01

    Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

  14. Silicon-micromachined microchannel plates

    Beetz, C P; Steinbeck, J; Lemieux, B; Winn, D R

    2000-01-01

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of approx 0.5 to approx 25 mu m, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposite...

  15. A metallic buried interconnect process for through-wafer interconnection

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G

    2008-01-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated

  16. Wafer level 3-D ICs process technology

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  17. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  18. The impact of silicon feedstock on the PV module cost

    del Coso, G.; del Cañizo, C.; Sinke, W.C.

    2010-01-01

    The impact of the use of new (solar grade) silicon feedstock materials on the manufacturing cost of wafer-based crystalline silicon photovoltaic modules is analyzed considering effects of material cost, efficiency of utilisation, and quality. Calculations based on data provided by European industry

  19. A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

    Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

    2016-12-15

    In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  20. InGaAs-OI Substrate Fabrication on a 300 mm Wafer

    Sebastien Sollier

    2016-09-01

    Full Text Available In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs wafer on insulator (InGaAs-OI substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM, scanning acoustic microscopy (SAM, and HR-XRD, to insure the crystalline quality of the post transferred layer.