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Sample records for silicon gate mos

  1. A split accumulation gate architecture for silicon MOS quantum dots

    Science.gov (United States)

    Rochette, Sophie; Rudolph, Martin; Roy, Anne-Marie; Curry, Matthew; Ten Eyck, Gregory; Dominguez, Jason; Manginell, Ronald; Pluym, Tammy; King Gamble, John; Lilly, Michael; Bureau-Oxton, Chloé; Carroll, Malcolm S.; Pioro-Ladrière, Michel

    We investigate tunnel barrier modulation without barrier electrodes in a split accumulation gate architecture for silicon metal-oxide-semiconductor quantum dots (QD). The layout consists of two independent accumulation gates, one gate forming a reservoir and the other the QD. The devices are fabricated with a foundry-compatible, etched, poly-silicon gate stack. We demonstrate 4 orders of magnitude of tunnel-rate control between the QD and the reservoir by modulating the reservoir gate voltage. Last electron charging energies of app. 10 meV and tuning of the ST splitting in the range 100-200 ueV are observed in two different split gate layouts and labs. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  2. Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances

    International Nuclear Information System (INIS)

    Suat, J.P.; Borel, J.

    1976-01-01

    The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr

  3. Solar cell array for driving MOS type FET gate. MOS gata EFT gate kudoyo taiyo denchi array

    Energy Technology Data Exchange (ETDEWEB)

    Murakami, S; Yoshida, K; Yoshiki, T; Yamaguchi, Y; Nakayama, T; Owada, Y

    1990-03-12

    There has been a semiconductor relay utilizing MOS type FET (field effect transistor). Concerning the solar cells used for a semiconductor relay, it is required to separate the cells by forming insulating oxide films first and to form semiconductor layers by using many mask patterns, since a crystal semiconductor is used. Thereby its manufacturing process becomes complicated and laminification as well as thin film formation are difficult, In view of the above, this invention proposes a solar cell array for driving a MOS type FET gate consisting of amorphous silicon semiconductor cells, which are used for a semiconductor relay with solar cells generating electromotive power by the light of a light emitting diode and a MOS type FET that the power output of the above solar cells is supplied to its gate, and which are connected in series with many steps. 9 figs.

  4. SWNT array resonant gate MOS transistor

    Energy Technology Data Exchange (ETDEWEB)

    Arun, A; Salet, P; Ionescu, A M [NanoLab, Ecole Polytechnique Federale de Lausanne, CH-1015, Lausanne (Switzerland); Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F, E-mail: marcelo.goffman@cea.fr [Laboratoire d' Electronique Moleculaire, SPEC (CNRS URA 2454), IRAMIS, CEA, Gif-sur-Yvette (France)

    2011-02-04

    We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

  5. SWNT array resonant gate MOS transistor.

    Science.gov (United States)

    Arun, A; Campidelli, S; Filoramo, A; Derycke, V; Salet, P; Ionescu, A M; Goffman, M F

    2011-02-04

    We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

  6. SWNT array resonant gate MOS transistor

    International Nuclear Information System (INIS)

    Arun, A; Salet, P; Ionescu, A M; Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F

    2011-01-01

    We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

  7. Chemical sensitivity of Mo gate Mos capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Lombardi, R.M.; Aragon, R. [Laboratorio de Peliculas delgadas, Facultad de Ingenieria, Paseo Colon 850, 1063, Buenos Aires (Argentina)

    2006-07-01

    Mo gate Mos capacitors exhibit a negative shift of their C-V characteristic by up to 240 mV, at 125 C, in response to 1000 ppm hydrogen, in controlled nitrogen atmospheres. The experimental methods for obtaining capacitance and conductance, as a function of polarisation voltage, as well as the relevant equivalent circuits are reviewed. The single-state interface state density, at the semiconductor-dielectric interface, decreases from 2.66 x 10{sup 11} cm{sup -2} e-v{sup -1}, in pure nitrogen, to 2.5 x 10{sup 11} cm{sup -2} e-v{sup -1} in 1000 ppm hydrogen in nitrogen mixtures, at this temperature. (Author)

  8. Cobalt micro-magnet integration on silicon MOS quantum dots

    Science.gov (United States)

    Camirand Lemyre, Julien; Rochette, Sophie; Anderson, John; Manginell, Ronald P.; Pluym, Tammy; Ward, Dan; Carroll, Malcom S.; Pioro-Ladrière, Michel

    Integration of cobalt micro-magnets on silicon metal-oxide-semiconductor (MOS) quantum dot devices has been investigated. The micro-magnets are fabricated in a lift-off process with e-beam lithography and deposited directly on top of an etched poly-silicon gate stack. Among the five resist stacks tested, one is found to be compatible with our MOS specific materials (Si and SiO2) . Moreover, devices with and without additional Al2O3 insulating layer show no additional gate leakage after processing. Preliminary transport data indicates electrostatic stability of our devices with integrated magnets. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  9. Capacitance-voltage characterization of fully silicided gated MOS capacitor

    International Nuclear Information System (INIS)

    Wang Baomin; Ru Guoping; Jiang Yulong; Qu Xinping; Li Bingzong; Liu Ran

    2009-01-01

    This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leakage current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic. A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation factor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this paper investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to

  10. Development and characterization of vertical double-gate MOS field-effect transistors

    International Nuclear Information System (INIS)

    Trellenkamp, S.

    2004-07-01

    Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)

  11. Rendering high charge density of states in ionic liquid-gated MoS 2 transistors

    NARCIS (Netherlands)

    Lee, Y.; Lee, J.; Kim, S.; Park, H.S.

    2014-01-01

    We investigated high charge density of states (DOS) in the bandgap of MoS2 nanosheets with variable temperature measurements on ionic liquid-gated MoS2 transistors. The thermally activated charge transport indicates that the electrical current in the two-dimensional MoS 2 nanosheets under high

  12. Effects of radiation on MOS structures and silicon devices

    International Nuclear Information System (INIS)

    Braeunig, D.; Fahrner, W.

    1983-02-01

    A comprehensive view of radiation effects on MOS structures and silicon devices is given. In the introduction, the interaction of radiation with semiconductor material is presented. In the next section, the electrical degradation of semiconductor devices due to this interaction is discussed. The commonly used hardening techniques are shown. The last section deals with testing of radiation hardness of devices. (orig.) [de

  13. Analysis of gate underlap channel double gate MOS transistor for electrical detection of bio-molecules

    Science.gov (United States)

    Ajay; Narang, Rakhi; Saxena, Manoj; Gupta, Mridula

    2015-12-01

    In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (Vth). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results.

  14. The effects of gate oxide thickness on radiation damage in MOS system

    International Nuclear Information System (INIS)

    Zhu Hui; Yan Rongliang; Wang Yu; He Jinming

    1988-01-01

    The dependences of the flatband voltage shift (ΔV FB ) and the threshold voltage shift (ΔV TH ) in MOS system on the oxide thickness (T ox ) and on total irradiated dose (D) of electron-beam and 60 Co γ-ray have been studied. It has been found that ΔV FB ∝ T ox 3 , with +10V of gate bias during irradiation for n-Si substrate MOS capacitors; ΔV TH ∝ T ox 3 D 2/3 , with 'on' gate bias during irradiation for n- and P-channel MOS transistors; ΔV TP ∝ T ox 2 D 2/3 , with 'off' gate bias during irradiation for P-channel MOS transistors. These results are explained by Viswanathan model. According to ∼T ox 3 dependence, the optimization of radiation hardening process for MOS system is also simply discussed

  15. The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

    International Nuclear Information System (INIS)

    Sah, C.-T.; Jie Binbin

    2009-01-01

    This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

  16. Low Noise Bias Current/Voltage References Based on Floating-Gate MOS Transistors

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    The exploitation of floating-gate MOS transistors as reference current and voltage sources is investigated. Test structures of common source and common drain floating-gate devices have been implemented in a commercially available 0.8 micron double-poly CMOS process. The measurements performed...

  17. MOS structures containing silicon nanoparticles for memory device applications

    International Nuclear Information System (INIS)

    Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S

    2008-01-01

    Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability

  18. Characterising large area silicon drift detectors with MOS injectors

    International Nuclear Information System (INIS)

    Bonvicini, V.; Rashevsky, A.; Vacchi, A.

    1999-01-01

    In the framework of the INFN DSI project, the first prototypes of a large-area Silicon Drift Detector (SDD) have been designed and produced on 5'' diameter wafers of Neutron Transmutation Doped (NTD) silicon with a resistivity of 3000 Ω·cm. The detector is a 'butterfly' bi-directional structure with a drift length of 32 mm and the drifting charge is collected by two arrays of anodes having a pitch of 200 μm. The high-voltage divider is integrated on-board and is realised with p + implantations. For test and calibration purposes, the detector has a new type of MOS injector. The paper presents results obtained to injecting charge at the maximum drift distance (32mm) from the anodes by means of the MOS injecting structure, As front-end electronics, the authors have used a 32-channels low-noise bipolar VLSI circuit (OLA, Omni-purpose Low-noise Amplifer) specifically designed for silicon drift detectors. The uniformity of the drift time in different regions of the sensitive area and its dependence on the ambient temperature are studied

  19. Contribution to the study of low-energy X-ray-induced degradations on the oxide-silicon interfacial transition layer of MOS structures

    International Nuclear Information System (INIS)

    Boukabache, Ali

    1983-01-01

    The Si-SiO_2 interface is considered as a transition layer. Its thickness is typically about 10 A. It contains traps which exchange charges with silicon by a tunneling mechanism. Its influence on MOS capacitor, gate-controlled diode and MOS transistor is analyzed. Long channel MOST's (P-Substrate) are irradiated with low energy X-ray (between 0 and 240 Krads) in order to validate the model. Capacitance, recombination velocity and 1/f noise measurements indicate that the X- ray induce traps distributed in space and in energy. These traps provoke a decrease in mobility. Additionally, X-rays create a fixed oxide charge which induce a shift in the characteristics of MOS structures. Finally, under irradiation the behaviour of the gate-controlled diode and the MOS capacitor are in accordance with theoretical model of the interfacial layer. The overall noise behaviour cannot be explained by existing theoretical models. (author) [fr

  20. Development of MOS-FET based Marx generator with self-proved gate power

    International Nuclear Information System (INIS)

    Tokuchi, A.; Jiang, W.; Takayama, K.; Arai, T.; Kawakubo, T.; Adachi, T.

    2012-01-01

    New MOS-FET based Marx generator is described. An electric gate power for the MOS-FET is provided from the Marx main circuit itself. Four-stage Marx generator generates -12kV of the output voltage. The Marx Generator is successfully used to drive an Einzel lens chopper to generate a short pulsed ion beam for a KEK digital accelerator. (author)

  1. High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

    KAUST Repository

    Zhang, Qing

    2016-06-21

    Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

  2. High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

    KAUST Repository

    Zhang, Qing; Bao, Wenzhong; Gong, Amy; Gong, Tao; Ma, Dakang; Wan, Jiayu; Dai, Jiaqi; Munday, J; He, Jr-Hau; Hu, Liangbing; Zhang, Daihua

    2016-01-01

    Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

  3. Compensated readout for high-density MOS-gated memristor crossbar array

    KAUST Repository

    Zidan, Mohammed A.

    2015-01-01

    Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array.

  4. Hydrogen and Methane Response of Pd Gate MOS Sensor

    Directory of Open Access Journals (Sweden)

    Preeti Pandey

    2009-04-01

    Full Text Available A sensor based on Pd/SiO2/Si MOS capacitor was fabricated on p type (1-6 ΩCm Si with thermal oxide layer of thickness about 33Ǻ. Sensor properties of the MOS structure were studied towards hydrogen (500- 3500 ppm in air and methane gas (1000-2500 ppm in air at room temperature and 140˚C respectively. The response of the sensor was measured as shift in C-V curve of the MOS structure. The sensitivity of the sensor towards the hydrogen (73 % at 0.03 V bias was better than methane (19.1 % at 0.68 V bias. SEM (Scanning electron microscopy and AFM image of the metal film show the porous structure which believed to be facilitating the catalytic oxidation of the insulator surface and higher gas response. High sensitivity of the sensor can be attributed to the change of interface state density on exposure of gases along with the formation of dipole layer.

  5. Observation of Room-Temperature Magnetoresistance in Monolayer MoS2 by Ferromagnetic Gating.

    Science.gov (United States)

    Jie, Wenjing; Yang, Zhibin; Zhang, Fan; Bai, Gongxun; Leung, Chi Wah; Hao, Jianhua

    2017-07-25

    Room-temperature magnetoresistance (MR) effect is observed in heterostructures of wafer-scale MoS 2 layers and ferromagnetic dielectric CoFe 2 O 4 (CFO) thin films. Through the ferromagnetic gating, an MR ratio of -12.7% is experimentally achieved in monolayer MoS 2 under 90 kOe magnetic field at room temperature (RT). The observed MR ratio is much higher than that in previously reported nonmagnetic metal coupled with ferromagnetic insulator, which generally exhibited MR ratio of less than 1%. The enhanced MR is attributed to the spin accumulation at the heterostructure interface and spin injection to the MoS 2 layers by the strong spin-orbit coupling effect. The injected spin can contribute to the spin current and give rise to the MR by changing the resistance of MoS 2 layers. Furthermore, the MR effect decreases as the thickness of MoS 2 increases, and the MR ratio becomes negligible in MoS 2 with thickness more than 10 layers. Besides, it is interesting to find a magnetic field direction dependent spin Hall magnetoresistance that stems from a combination of the spin Hall and the inverse spin Hall effects. Our research provides an insight into exploring RT MR in monolayer materials, which should be helpful for developing ultrathin magnetic storage devices in the atomically thin limit.

  6. Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

    Directory of Open Access Journals (Sweden)

    Gaspar Casados-Cruz

    2010-11-01

    Full Text Available Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.

  7. Observing the semiconducting band-gap alignment of MoS2 layers of different atomic thicknesses using a MoS2/SiO2/Si heterojunction tunnel diode

    NARCIS (Netherlands)

    Nishiguchi, K.; Castellanos-Gomez, A.; Yamaguchi, H.; Fujiwara, A.; Van der Zant, H.S.J.; Steele, G.A.

    2015-01-01

    We demonstrate a tunnel diode composed of a vertical MoS2/SiO2/Si heterostructure. A MoS2 flake consisting four areas of different thicknesses functions as a gate terminal of a silicon field-effect transistor. A thin gate oxide allows tunneling current to flow between the n-type MoS2 layers and

  8. Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

    Science.gov (United States)

    Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

    2014-02-28

    Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

  9. Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

    Science.gov (United States)

    Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

    2018-04-01

    For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

  10. Piezophototronic Effect in Single-Atomic-Layer MoS 2 for Strain-Gated Flexible Optoelectronics

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Wenzhuo [School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta GA 30332-0245 USA; Wang, Lei [Department of Electrical Engineering, Columbia University, New York NY 10027 USA; Yu, Ruomeng [School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta GA 30332-0245 USA; Liu, Yuanyue [National Renewable Energy Laboratory (NREL), Golden CO 80401 USA; Wei, Su-Huai [National Renewable Energy Laboratory (NREL), Golden CO 80401 USA; Hone, James [Department of Mechanical Engineering, Columbia University, New York NY 10027 USA; Wang, Zhong Lin [School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta GA 30332-0245 USA; Beijing Institute of Nanoenergy and Nanosystems, Chinese Academy of Sciences, 100083 Beijing China

    2016-08-03

    Strain-gated flexible optoelectronics are reported based on monolayer MoS2. Utilizing the piezoelectric polarization created at metal-MoS2 interface to modulate the separation/transport of photogenerated carriers, the piezophototronic effect is applied to implement atomic-layer-thick phototransistor. Coupling between piezoelectricity and photogenerated carriers may enable the development of novel optoelectronics.

  11. Capacitance-voltage characteristics of MOS capacitors with Ge nanocrystals embedded in ZrO2 gate material

    International Nuclear Information System (INIS)

    Lee, Hye-Ryoung; Choi, Samjong; Cho, Kyoungah; Kim, Sangsig

    2007-01-01

    Capacitance versus voltage (C-V) curves of Ge-nanocrystals (NCs)-embedded metal-oxide-semiconductor (MOS) capacitors are characterized in this work. Ge NCs were formed in 20-nm thick ZrO 2 gate layers by ion implantation and subsequent annealing procedures. The formation of the Ge NCs in the ZrO 2 gate layers was confirmed by high-resolution transmission electron microscopy and energy dispersive spectroscopy. The C-V curves obtained from a representative MOS capacitor embedded with the Ge NCs exhibit a 3 V memory window as bias voltage varied from 9 to - 9 V and then back to the initial positive voltage, whereas MOS capacitors without Ge NCs show negligible memory windows at the same voltage range. This indicates the presence of charge storages in the Ge NCs. The counterclockwise hysteresis observed from the C-V curves implies that electrons are trapped in Ge NCs presented inside the ZrO 2 gate layer. And our experimental results obtained from capacitance versus time measurements show good retention characteristics of Ge-NCs-embedded MOS capacitors with ZrO 2 gate material for the application of NFGM

  12. Valley qubit in a gated MoS2 monolayer quantum dot

    Science.gov (United States)

    Pawłowski, J.; Żebrowski, D.; Bednarek, S.

    2018-04-01

    The aim of the presented research is to design a nanodevice, based on a MoS2 monolayer, performing operations on a well-defined valley qubit. We show how to confine an electron in a gate-induced quantum dot within the monolayer, and to perform the not operation on its valley degree of freedom. The operations are carried out all electrically via modulation of the confinement potential by oscillating voltages applied to the local gates. Such quantum dot structure is modeled realistically. Through these simulations we investigate the possibility of realization of a valley qubit in analogy with a realization of the spin qubit. We accurately model the potential inside the nanodevice accounting for proper boundary conditions on the gates and space-dependent materials permittivity by solving the generalized Poisson's equation. The time evolution of the system is supported by realistic self-consistent Poisson-Schrödinger tight-binding calculations. The tight-binding calculations are further confirmed by simulations within the effective continuum model.

  13. Boron diffusion into nitrogen doped silicon films for P{sup +} polysilicon gate structures

    Energy Technology Data Exchange (ETDEWEB)

    Mansour, Farida; Mahamdi, Ramdane; Jalabert, Laurent; Temple-Boyer, Pierre

    2003-06-23

    This paper deals with the study of the boron diffusion in nitrogen doped silicon (NIDOS) deposited from disilane Si{sub 2}H{sub 6} and ammonia NH{sub 3} for the development of P{sup +} polysilicon gate metal oxide semiconductor (MOS) devices. NIDOS films with varied nitrogen content have been boron implanted, then annealed and finally analysed by secondary ion mass spectroscopy (SIMS). In order to simulate the experimental SIMS of boron concentration profiles in the NIDOS films, a model adapted to the particular conditions of the samples elaboration, i.e. the very high boron concentration and the nitrogen content, has been established. The boron diffusion reduction in NIDOS films with increasing nitrogen rates has been evidenced by the profiles as well as by the obtained diffusion coefficients, which shows that the nitrogen incorporation reduces the boron diffusion. This has been confirmed by capacitance-voltage (C-V) measurements performed on MOS capacitors: the higher the nitrogen content, the lower the flat-band voltage. Finally, these results demonstrate that the improvement of the gate oxide quality occurs with the suppression of the boron penetration.

  14. Silicon photonic crystal all-optical logic gates

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Yulan [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Hu, Xiaoyong, E-mail: xiaoyonghu@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Gong, Qihuang, E-mail: qhgong@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)

    2013-01-03

    All-optical logic gates, including OR, XOR, NOT, XNOR, and NAND gates, are realized theoretically in a two-dimensional silicon photonic crystal using the light beam interference effect. The ingenious photonic crystal waveguide component design, the precisely controlled optical path difference, and the elaborate device configuration ensure the simultaneous realization of five types of logic gate with low-power and a contrast ratio between the logic states of “1” and “0” as high as 20 dB. High power is not necessary for operation of these logic gate devices. This offers a simple and effective approach for the realization of integrated all-optical logic devices.

  15. Investigation on nonlinear optical properties of MoS2 nanoflakes grown on silicon and quartz substrates

    Science.gov (United States)

    Bayesteh, Samaneh; Zahra Mortazavi, Seyedeh; Reyhani, Ali

    2018-05-01

    In this study, MoS2 nanoflakes were directly grown on different substrates—Si/SiO2 and quartz—by one-step thermal chemical vapor deposition using MoO3 and sulfide powders as precursors. Scanning electron microscopy and x-ray diffraction patterns demonstrated the formation of MoS2 structures on both substrates. Moreover, UV-visible and photoluminescence analysis confirmed the formation of MoS2 few-layer structures. According to Raman spectroscopy, by assessment of the line width and frequency shift differences between the and A 1g, it was inferred that the MoS2 grown on the silicon substrate was monolayer and that grown on the quartz substrate was multilayer. In addition, open-aperture and close-aperture Z-scan techniques were employed to study the nonlinear optical properties including nonlinear absorption and nonlinear refraction of the grown MoS2. All experiments were performed using a diode laser with a wavelength of 532 nm as the light source. It is noticeable that both samples demonstrate obvious self-defocusing behavior. The monolayer MoS2 grown on the silicon substrate displayed considerable two-photon absorption while, the multilayer MoS2 synthesized on the quartz exhibited saturable absorption. In general, few-layered MoS2 would be useful for the development of nanophotonic devices like optical limiters, optical switchers, etc.

  16. Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

    Science.gov (United States)

    Guerfi, Youssouf; Larrieu, Guilhem

    2016-04-01

    Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

  17. Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

    DEFF Research Database (Denmark)

    Igor, Mucha

    1997-01-01

    A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe degradat......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...... degradation of the performance of the circuit and without the need for a repeating programming. In this way the noise originating from any resistance previously used for the definition of the operating point is avoided completely and, moreover, by avoiding the input high-pass filter both the saturation...

  18. Comparative studies of MOS-gate/oxide-passivated AlGaAs/InGaAs pHEMTs by using ozone water oxidation technique

    International Nuclear Information System (INIS)

    Lee, Ching-Sung; Hung, Chun-Tse; Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lai, Ying-Nan

    2012-01-01

    Al 0.22 Ga 0.78 As/In 0.24 Ga 0.76 As pseudomorphic high-electron-mobility transistors (pHEMTs) with metal-oxide-semiconductor (MOS)-gate structure or oxide passivation by using ozone water oxidation treatment have been comprehensively investigated. Annihilated surface states, enhanced gate insulating property and improved device gain have been achieved by the devised MOS-gate structure and oxide passivation. The present MOS-gated or oxide-passivated pHEMTs have demonstrated superior device performances, including superior breakdown, device gain, noise figure, high-frequency characteristics and power performance. Temperature-dependent device characteristics of the present designs at 300–450 K are also studied. (paper)

  19. Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

    Science.gov (United States)

    Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

    2016-06-09

    Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

  20. Silicon Mie resonators for highly directional light emission from monolayer MoS2

    Science.gov (United States)

    Cihan, Ahmet Fatih; Curto, Alberto G.; Raza, Søren; Kik, Pieter G.; Brongersma, Mark L.

    2018-05-01

    Controlling light emission from quantum emitters has important applications, ranging from solid-state lighting and displays to nanoscale single-photon sources. Optical antennas have emerged as promising tools to achieve such control right at the location of the emitter, without the need for bulky, external optics. Semiconductor nanoantennas are particularly practical for this purpose because simple geometries such as wires and spheres support multiple, degenerate optical resonances. Here, we start by modifying Mie scattering theory developed for plane wave illumination to describe scattering of dipole emission. We then use this theory and experiments to demonstrate several pathways to achieve control over the directionality, polarization state and spectral emission that rely on a coherent coupling of an emitting dipole to optical resonances of a silicon nanowire. A forward-to-backward ratio of 20 was demonstrated for the electric dipole emission at 680 nm from a monolayer MoS2 by optically coupling it to a silicon nanowire.

  1. A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

    Science.gov (United States)

    Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

    2018-06-15

    Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

  2. Electrical properties of MOS structures on nitrogen-doped Czochralski-grown silicon: A positron annihilation study

    International Nuclear Information System (INIS)

    Slugen, V.; Harmatha, L.; Tapajna, M.; Ballo, P.; Pisecny, P.; Sik, J.; Koegel, G.; Krsjak, V.

    2006-01-01

    Measurements of interface trap density, effective generation lifetime (GL) and effective surface generation velocity have been performed using different methods on selected MOS structures prepared on nitrogen-doped Czochralski-grown (NCz) silicon. The application of the positron annihilation technique using a pulsed low energy positron system (PLEPS) focused on the detection of nitrogen-related defects in NCz silicon in the near surface region. In the case of p-type Cz silicon, all the results could be used for the testing of homogeneity. In n-type Cz silicon, positron annihilation was found insensitive to nitrogen doping

  3. Radiation-induced interface state generation in MOS devices with reoxidised nitrided SiO2 gate dielectrics

    International Nuclear Information System (INIS)

    Lo, G.Q.; Shih, D.K.; Ting, W.; Kwong, D.L.

    1989-01-01

    In this letter, the radiation-induced interface state generation ΔD it in MOS devices with reoxidised nitrided gate oxides has been studied. The reoxidised nitrided oxides were fabricated by rapid thermal reoxidation (RTO) of rapidly thermal nitrided (RTN) SiO 2 . The devices were irradiated by exposure to X-rays at doses of 0.5-5.0 Mrad (Si). It is found that the RTO process improves the radiation hardness of RTN oxides in terms of interface state generation. The enhanced interface ''hardness'' of reoxidised nitrided oxides is attributed to the strainless interfacial oxide regrowth or reduction of hydrogen concentration during RTO of RTN oxides. (author)

  4. Radiation-hard silicon gate bulk CMOS cell family

    International Nuclear Information System (INIS)

    Gibbon, C.F.; Habing, D.H.; Flores, R.S.

    1980-01-01

    A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved

  5. Highly Stable, Dual-Gated MoS2 Transistors Encapsulated by Hexagonal Boron Nitride with Gate-Controllable Contact, Resistance, and Threshold Voltage.

    Science.gov (United States)

    Lee, Gwan-Hyoung; Cui, Xu; Kim, Young Duck; Arefe, Ghidewon; Zhang, Xian; Lee, Chul-Ho; Ye, Fan; Watanabe, Kenji; Taniguchi, Takashi; Kim, Philip; Hone, James

    2015-07-28

    Emerging two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS2) have been intensively studied because of their novel properties for advanced electronics and optoelectronics. However, 2D materials are by nature sensitive to environmental influences, such as temperature, humidity, adsorbates, and trapped charges in neighboring dielectrics. Therefore, it is crucial to develop device architectures that provide both high performance and long-term stability. Here we report high performance of dual-gated van der Waals (vdW) heterostructure devices in which MoS2 layers are fully encapsulated by hexagonal boron nitride (hBN) and contacts are formed using graphene. The hBN-encapsulation provides excellent protection from environmental factors, resulting in highly stable device performance, even at elevated temperatures. Our measurements also reveal high-quality electrical contacts and reduced hysteresis, leading to high two-terminal carrier mobility (33-151 cm(2) V(-1) s(-1)) and low subthreshold swing (80 mV/dec) at room temperature. Furthermore, adjustment of graphene Fermi level and use of dual gates enable us to separately control contact resistance and threshold voltage. This novel vdW heterostructure device opens up a new way toward fabrication of stable, high-performance devices based on 2D materials.

  6. Gate-stack engineering for self-organized Ge-dot/SiO2/SiGe-shell MOS capacitors

    Directory of Open Access Journals (Sweden)

    Wei-Ting eLai

    2016-02-01

    Full Text Available We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5−90 nm, the SiO2 thickness (3−4 nm, and as well the SiGe-shell thickness (2−15 nm has been demonstrated, enabling a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5x10^11 cm^-2·eV^-1 and fixed charge densities of 1-5x10^11 cm^-2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5 in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge MOS nanoelectronic and nanophotonic applications.

  7. The TDDB Characteristics of Ultra-Thin Gate Oxide MOS Capacitors under Constant Voltage Stress and Substrate Hot-Carrier Injection

    Directory of Open Access Journals (Sweden)

    Jingyu Shen

    2018-01-01

    Full Text Available The breakdown characteristics of ultra-thin gate oxide MOS capacitors fabricated in 65 nm CMOS technology under constant voltage stress and substrate hot-carrier injection are investigated. Compared to normal thick gate oxide, the degradation mechanism of time-dependent dielectric breakdown (TDDB of ultra-thin gate oxide is found to be different. It is found that the gate current (Ig of ultra-thin gate oxide MOS capacitor is more likely to be induced not only by Fowler-Nordheim (F-N tunneling electrons, but also by electrons surmounting barrier and penetrating electrons in the condition of constant voltage stress. Moreover it is shown that the time to breakdown (tbd under substrate hot-carrier injection is far less than that under constant voltage stress when the failure criterion is defined as a hard breakdown according to the experimental results. The TDDB mechanism of ultra-thin gate oxide will be detailed. The differences in TDDB characteristics of MOS capacitors induced by constant voltage stress and substrate hot-carrier injection will be also discussed.

  8. Comparative studies of AlGaN/GaN MOS-HEMTs with stacked gate dielectrics by the mixed thin film growth method

    International Nuclear Information System (INIS)

    Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lee, Ching-Sung

    2013-01-01

    This paper reports Al 0.27 Ga 0.73 N/GaN metal–oxide–semiconductor high electron mobility transistors (MOS-HEMTs) with stacked Al 2 O 3 /HfO 2 gate dielectrics by using hydrogen peroxideoxidation/sputtering techniques. The Al 2 O 3 employed as a gate dielectric and surface passivation layer effectively suppresses the gate leakage current, improves RF drain current collapse and exhibits good thermal stability. Moreover, by stacking the good insulating high-k HfO 2 dielectric further suppresses the gate leakage, enhances the dielectric breakdown field and power-added efficiency, and decreases the equivalent oxide thickness. The present MOS-HEMT design has demonstrated superior improvements of 10.1% (16.4%) in the maximum drain–source current (I DS,max ), 11.4% (22.5%) in the gate voltage swing and 12.5%/14.4% (21.9%/22.3%) in the two-terminal gate–drain breakdown/turn-on voltages (BV GD /V ON ), and the present design also demonstrates the lowest gate leakage current and best thermal stability characteristics as compared to two reference MOS-HEMTs with a single Al 2 O 3 /(HfO 2 ) dielectric layer of the same physical thickness. (invited paper)

  9. Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

    Science.gov (United States)

    Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

    2016-01-26

    Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

  10. Strong dopant dependence of electric transport in ion-gated MoS2

    NARCIS (Netherlands)

    Piatti, Erik; Chen, Qihong; Ye, Jianting

    2017-01-01

    We report modifications of the temperature-dependent transport properties of MoS2 thin flakes via field-driven ion intercalation in an electric double layer transistor. We find that intercalation with Li+ ions induces the onset of an inhomogeneous superconducting state. Intercalation with K+ leads

  11. Electrochemical synthesis of MoS2 quantum dots embedded nanostructured porous silicon with enhanced electroluminescence property

    Science.gov (United States)

    Shrivastava, Megha; Kumari, Reeta; Parra, Mohammad Ramzan; Pandey, Padmini; Siddiqui, Hafsa; Haque, Fozia Z.

    2017-11-01

    In this report we present the successful enhancement in electroluminescence (EL) in nanostructured n-type porous silicon (PS) with an idea of embedding luminophorous Molybdenum disulfide (MoS2) quantum dots (QD's). Electrochemical anodization technique was used for the formation of PS surface and MoS2 QD's were prepared using the electrochemical route. Spin coating technique was employed for the proper incorporation of MoS2 QD's within the PS nanostructures. The crystallographic analysis was performed using X-ray diffraction (XRD), Raman and Fourier transform infrared (FT-IR) spectroscopy techniques. However, surface morphology was determined using Transmission electron microscopy (TEM) and Atomic force microscopy (AFM). The optical measurements were performed on photoluminescence (PL) spectrophotometer; additionally for electroluminescence (EL) study special arrangement of instrumental setup was made at laboratory level which provides novelty to this work. A diode prototype was made comprising Ag/MoS2:PS/Silicon/Ag for EL study. The MoS2:PS shows a remarkable concentration dependent enhancement in PL as well as in EL intensities, which paves a way to better utilize this strategy in optoelectronic device applications.

  12. Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

    Directory of Open Access Journals (Sweden)

    Xiaojun Cheng

    2014-05-01

    Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

  13. Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors

    CERN Document Server

    Gaioni, L; Ratti, L; Re, V; Speziali, V; Traversi, G

    2008-01-01

    This work describes a measuring system that was developed to characterize the gate current noise performances of CMOS devices with minimum feature size in the 100 nm span. These devices play an essential role in the design of present daymixedsignal integrated circuits, because of the advantages associated with the scaling process. The reduction in the gate oxide thickness brought about by CMOS technology downscaling leads to a non-negligible gate current due to direct tunneling phenomena; this current represents a noise source which requires an accurate characterization for optimum analog design. In this paper, two instruments able to perform measurements in two different ranges of gate current values will be discussed. Some of the results of gate current noise characterization will also be presented.

  14. SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

    Science.gov (United States)

    Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-06-01

    Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

  15. Current linearity and operation stability in Al2O3-gate AlGaN/GaN MOS high electron mobility transistors

    Science.gov (United States)

    Nishiguchi, Kenya; Kaneki, Syota; Ozaki, Shiro; Hashizume, Tamotsu

    2017-10-01

    To investigate current linearity and operation stability of metal-oxide-semiconductor (MOS) AlGaN/GaN high electron mobility transistors (HEMTs), we have fabricated and characterized the Al2O3-gate MOS-HEMTs without and with a bias annealing in air at 300 °C. Compared with the as-fabricated (unannealed) MOS HEMTs, the bias-annealed devices showed improved linearity of I D-V G curves even in the forward bias regime, resulting in increased maximum drain current. Lower subthreshold slope was also observed after bias annealing. From the precise capacitance-voltage analysis on a MOS diode fabricated on the AlGaN/GaN heterostructure, it was found that the bias annealing effectively reduced the state density at the Al2O3/AlGaN interface. This led to efficient modulation of the AlGaN surface potential close to the conduction band edge, resulting in good gate control of two-dimensional electron gas density even at forward bias. In addition, the bias-annealed MOS HEMT showed small threshold voltage shift after applying forward bias stress and stable operation even at high temperatures.

  16. Generation lifetime investigation of ion-damage gettered silicon using MOS structure

    International Nuclear Information System (INIS)

    Nassibian, A.G.; Browne, V.A.; Perkins, K.D.

    1976-01-01

    Gettering of undesirable generation impurities by O and Ar implant damage layer has been investigated by transient response of MOS capacitors. One-half of each Si wafer was masked against the implanting ion beam and comparison was made between the two halves of each wafer by deducing the generation lifetime from the C-t measurements. The implant dosage was 10 16 cm -2 and ion energy 200 keV. The gettering anneal at 1070 0 C was also the gate oxidation. The generation lifetime from 1 to 15 μs of the control half was increased to as high as 200 μs after both O and Ar implants. The results with O were more reproducible than with the Ar-implanted Si wafers; however, the largest increase in generation lifetime was observed with the Ar getterered wafer. It is proposed that there are generation centers other than the generation impurity centers that cannot be removed by gettering methods

  17. Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

    Science.gov (United States)

    Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

    2018-06-01

    Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

  18. Quantization effects on the inversion mode of a double gate MOS

    Directory of Open Access Journals (Sweden)

    Kalyan Mondol

    Full Text Available We investigate the quantization effects on the gate capacitance and charge distribution of a double gate MOSFET using a self-consistent solution of Poisson and Schrödinger equations of the industry standard simulation package Silvaco. Quantization effects on the gate C–V are simulated by varying the electron and hole effective masses. We notice that the inversion capacitance value decreases as the effective mass goes below 0.1mo and the shape of the C–V curve changes to step like in the inversion. We also notice that the inversion switches from surface inversion to volume inversion for low effective mass, and the quantization effect (step like shape in C–V and volume inversion in charge profile happen at the same effective mass. Keywords: Double gate MOSFETs, Quantum effects, Energy quantization, Channel inversion, Charge density

  19. Burnout and gate rupture of power MOS transistors with fission fragments of 252Cf

    International Nuclear Information System (INIS)

    Tang Benqi; Wang Yanping; Geng Bin; Chen Xiaohua; He Chaohui; Yang Hailiang

    2000-01-01

    A study to determine the single event burnout (SEB) and single event gate rupture (SEGR) sensitivities of power MOSFET devices is carried out by exposure to fission fragments from 252 Cf source. The test method, test results, a description of observed burnout current waveforms and a discussion of a possible failure mechanism are presented. The test results include the observed dependence upon applied drain or gate to source bias and effect of external capacitors and limited resistors

  20. Quantization effects on the inversion mode of a double gate MOS

    Science.gov (United States)

    Mondol, Kalyan; Hasan, Md. Manzurul; Arafath, Yeasir; Alam, Khairul

    We investigate the quantization effects on the gate capacitance and charge distribution of a double gate MOSFET using a self-consistent solution of Poisson and Schrödinger equations of the industry standard simulation package Silvaco. Quantization effects on the gate C-V are simulated by varying the electron and hole effective masses. We notice that the inversion capacitance value decreases as the effective mass goes below 0.1mo and the shape of the C-V curve changes to step like in the inversion. We also notice that the inversion switches from surface inversion to volume inversion for low effective mass, and the quantization effect (step like shape) in C-V and volume inversion in charge profile happen at the same effective mass.

  1. Reliability study of ultra-thin gate oxides on strained-Si/SiGe MOS structures

    International Nuclear Information System (INIS)

    Varzgar, John B.; Kanoun, Mehdi; Uppal, Suresh; Chattopadhyay, Sanatan; Tsang, Yuk Lun; Escobedo-Cousins, Enrique; Olsen, Sarah H.; O'Neill, Anthony; Hellstroem, Per-Erik; Edholm, Jonas; Ostling, Mikael; Lyutovich, Klara; Oehme, Michael; Kasper, Erich

    2006-01-01

    The reliability of gate oxides on bulk Si and strained Si (s-Si) has been evaluated using constant voltage stressing (CVS) to investigate their breakdown characteristics. The s-Si architectures exhibit a shorter life time compared to that of bulk Si, which is attributed to higher bulk oxide charges (Q ox ) and increased surface roughness in the s-Si structures. The gate oxide in the s-Si structure exhibits a hard breakdown (HBD) at 1.9 x 10 4 s, whereas HBD is not observed in bulk Si up to a measurement period of 1.44 x 10 5 s. The shorter lifetime of the s-Si gate oxide is attributed to a larger injected charge (Q inj ) compared to Q inj in bulk Si. Current-voltage (I-V) measurements for bulk Si samples at different stress intervals show an increase in stress induced leakage current (SILC) of two orders in the low voltage regime from zero stress time to up to 5 x 10 4 s. In contrast, superior performance enhancements in terms of drain current, maximum transconductance and effective channel mobility are observed in s-Si MOSFET devices compared to bulk Si. The results from this study indicate that further improvement in gate oxide reliability is needed to exploit the sustained performance enhancement of s-Si devices over bulk Si

  2. Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

    Science.gov (United States)

    Neudeck, Philip G.

    1998-01-01

    The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

  3. Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

    Science.gov (United States)

    Shin, Hyun Wook; Son, Jong Yeog

    2018-01-01

    We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

  4. Highly enhanced avalanche probability using sinusoidally-gated silicon avalanche photodiode

    Energy Technology Data Exchange (ETDEWEB)

    Suzuki, Shingo; Namekata, Naoto, E-mail: nnao@phys.cst.nihon-u.ac.jp; Inoue, Shuichiro [Institute of Quantum Science, Nihon University, 1-8-14 Kanda-Surugadai, Chiyoda-ku, Tokyo 101-8308 (Japan); Tsujino, Kenji [Tokyo Women' s Medical University, 8-1 Kawada-cho, Shinjuku-ku, Tokyo 162-8666 (Japan)

    2014-01-27

    We report on visible light single photon detection using a sinusoidally-gated silicon avalanche photodiode. Detection efficiency of 70.6% was achieved at a wavelength of 520 nm when an electrically cooled silicon avalanche photodiode with a quantum efficiency of 72.4% was used, which implies that a photo-excited single charge carrier in a silicon avalanche photodiode can trigger a detectable avalanche (charge) signal with a probability of 97.6%.

  5. Active Thermal Control for Reliability Improvement of MOS-gated Power Devices

    DEFF Research Database (Denmark)

    Soldati, Alessandro; Concari, Carlo; Dossena, Fabrizio

    2017-01-01

    reliability and lifetime. These figures can then be improved, which eases the adoption of electrification in markets, such as transportation, where they are still below target values. The proposed ATC method leaves electric load parameters untouched, while acting dynamically on gate parameters, namely voltage...... and resistance. A model-predictive control (MPC) strategy is used to determine the most suitable parameters to use. Simulations of the control scheme are presented first, to predict the potential benefits on temperature swing amplitude, and the consequent improvements in terms of device lifetime are inferred...

  6. Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

    Energy Technology Data Exchange (ETDEWEB)

    Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-06-20

    Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

  7. Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

    Energy Technology Data Exchange (ETDEWEB)

    Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

    2017-07-01

    We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

  8. Physical and electrical characterizations of AlGaN/GaN MOS gate stacks with AlGaN surface oxidation treatment

    Science.gov (United States)

    Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-06-01

    The impacts of inserting ultrathin oxides into insulator/AlGaN interfaces on their electrical properties were investigated to develop advanced AlGaN/GaN metal–oxide–semiconductor (MOS) gate stacks. For this purpose, the initial thermal oxidation of AlGaN surfaces in oxygen ambient was systematically studied by synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) and atomic force microscopy (AFM). Our physical characterizations revealed that, when compared with GaN surfaces, aluminum addition promotes the initial oxidation of AlGaN surfaces at temperatures of around 400 °C, followed by smaller grain growth above 850 °C. Electrical measurements of AlGaN/GaN MOS capacitors also showed that, although excessive oxidation treatment of AlGaN surfaces over around 700 °C has an adverse effect, interface passivation with the initial oxidation of the AlGaN surfaces at temperatures ranging from 400 to 500 °C was proven to be beneficial for fabricating high-quality AlGaN/GaN MOS gate stacks.

  9. The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator

    Science.gov (United States)

    Jafar, N.; Soin, N.

    2009-06-01

    This work presents the noise behaviour due to the applied Dual Material Gate (DMG) on the 75 nm n-channel Silicon On Insulator (SOI) device operating in the fully depletion mode, particularly for microwave circuit design. Influences of DMG properties namely the gate length ratio (L1:L2) and gate material workfunction difference (ΔΦM) as well as structural and operational parameters which are silicon thickness (TSi) and threshold voltage (VTH) setting variation on the noise performance were carried out on simulation basis using ATLAS 2D. Results show better noise performance in DMG as compare to the standard gate structure of FD-SOI devices. Higher VTH for DMG design is recommended for minimized noise figure in line with the advantage of inverse VTH roll-off characteristics for short channel effects suppression.

  10. Silicon integrated circuits part A : supplement 2

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

  11. Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

    International Nuclear Information System (INIS)

    Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

    2008-01-01

    The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

  12. In vivo time-gated fluorescence imaging with biodegradable luminescent porous silicon nanoparticles.

    Science.gov (United States)

    Gu, Luo; Hall, David J; Qin, Zhengtao; Anglin, Emily; Joo, Jinmyoung; Mooney, David J; Howell, Stephen B; Sailor, Michael J

    2013-01-01

    Fluorescence imaging is one of the most versatile and widely used visualization methods in biomedical research. However, tissue autofluorescence is a major obstacle confounding interpretation of in vivo fluorescence images. The unusually long emission lifetime (5-13 μs) of photoluminescent porous silicon nanoparticles can allow the time-gated imaging of tissues in vivo, completely eliminating shorter-lived (50-fold in vitro and by >20-fold in vivo when imaging porous silicon nanoparticles. Time-gated imaging of porous silicon nanoparticles accumulated in a human ovarian cancer xenograft following intravenous injection is demonstrated in a live mouse. The potential for multiplexing of images in the time domain by using separate porous silicon nanoparticles engineered with different excited state lifetimes is discussed.

  13. Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

    Science.gov (United States)

    Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

    2018-04-01

    Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

  14. Design rules for RCA self-aligned silicon-gate CMOS/SOS process

    Science.gov (United States)

    1977-01-01

    The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

  15. Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

    DEFF Research Database (Denmark)

    Pfreundt, Andrea

    This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

  16. Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

    DEFF Research Database (Denmark)

    Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

    2016-01-01

    This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

  17. Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

    Energy Technology Data Exchange (ETDEWEB)

    Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)

    2013-12-23

    Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

  18. Germanium MOS capacitors grown on Silicon using low temperature RF-PECVD

    Science.gov (United States)

    Dushaq, Ghada; Rasras, Mahmoud; Nayfeh, Ammar

    2017-10-01

    In this paper, Ge metal-oxide-semiconductor capacitors (MOSCAPs) are fabricated on Si using a low temperature two-step deposition technique by radio frequency plasma enhanced chemical vapor deposition. The MOSCAP gate stack consists of atomic layer deposition of Al2O3 as the gate oxide and a Ti/Al metal gate electrode. The electrical characteristics of 9 nm Al2O3/i-Ge/Si MOSCAPs exhibit an n-type (p-channel) behavior and normal high frequency C-V responses. In addition to CV measurements, the gate leakage versus the applied voltage is measured and discussed. Moreover, the electrical behavior is discussed in terms of the material and interface quality. The Ge/high-k interface trap density versus the surface potential is extracted using the most commonly used methods in detemining the interface traps based on the capacitance-voltage (C-V) curves. The discussion included the Dit calculation from the conductance method, the high-low frequency (Castagné-Vapaille) method, and the Terman (high-frequency) method. Furthermore, the origins of the discrepancies in the interface trap densities determined from the different methods are discussed. The study of the post annealed Ge layers at different temperatures in H2 and N2 gas ambient revealed an improved electrical and transport properties of the films treated at T  Ge/Si demonstrates a great potential for p-channel transistor applications in a monolithically integrated CMOS platform.

  19. Gamma-ray irradiation and post-irradiation at room and elevated temperature response of pMOS dosimeters with thick gate oxides

    Directory of Open Access Journals (Sweden)

    Pejović Momčilo M.

    2011-01-01

    Full Text Available Gamma-ray irradiation and post-irradiation response at room and elevated temperature have been studied for radiation sensitive pMOS transistors with gate oxide thickness of 100 and 400 nm, respectively. Their response was followed based on the changes in the threshold voltage shift which was estimated on the basis of transfer characteristics in saturation. The presence of radiation-induced fixed oxide traps and switching traps - which lead to a change in the threshold voltage - was estimated from the sub-threshold I-V curves, using the midgap technique. It was shown that fixed oxide traps have a dominant influence on the change in the threshold voltage shift during gamma-ray irradiation and annealing.

  20. Implementation of atomic layer deposition-based AlON gate dielectrics in AlGaN/GaN MOS structure and its physical and electrical properties

    Science.gov (United States)

    Nozaki, Mikito; Watanabe, Kenta; Yamada, Takahiro; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-06-01

    Alumina incorporating nitrogen (aluminum oxynitride; AlON) for immunity against charge injection was grown on a AlGaN/GaN substrate through the repeated atomic layer deposition (ALD) of AlN layers and in situ oxidation in ozone (O3) ambient under optimized conditions. The nitrogen distribution was uniform in the depth direction, the composition was controllable over a wide range (0.5–32%), and the thickness could be precisely controlled. Physical analysis based on synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) revealed that harmful intermixing at the insulator/AlGaN interface causing Ga out-diffusion in the gate stack was effectively suppressed by this method. AlON/AlGaN/GaN MOS capacitors were fabricated, and they had excellent electrical properties and immunity against electrical stressing as a result of the improved interface stability.

  1. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    KAUST Repository

    Sevilla, Galo T.

    2016-02-29

    Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

  2. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Science.gov (United States)

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  3. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  4. Hybrid graphene/silicon Schottky photodiode with intrinsic gating effect

    Science.gov (United States)

    Di Bartolomeo, Antonio; Luongo, Giuseppe; Giubileo, Filippo; Funicello, Nicola; Niu, Gang; Schroeder, Thomas; Lisker, Marco; Lupina, Grzegorz

    2017-06-01

    We propose a hybrid device consisting of a graphene/silicon (Gr/Si) Schottky diode in parallel with a Gr/SiO2/Si capacitor for high-performance photodetection. The device, fabricated by transfer of commercial graphene on low-doped n-type Si substrate, achieves a photoresponse as high as 3 \\text{A} {{\\text{W}}-1} and a normalized detectivity higher than 3.5× {{10}12} \\text{cm} \\text{H}{{\\text{z}}1/2} {{\\text{W}}-1} in the visible range. It exhibits a photocurrent exceeding the forward current because photo-generated minority carriers, accumulated at Si/SiO2 interface of the Gr/SiO2/Si capacitor, diffuse to the Gr/Si junction. We show that the same mechanism, when due to thermally generated carriers, although usually neglected or disregarded, causes the increased leakage often measured in Gr/Si heterojunctions. We perform extensive I-V and C-V characterization at different temperatures and we measure a zero-bias Schottky barrier height of 0.52 eV at room temperature, as well as an effective Richardson constant A **  =  4× {{10}-5} \\text{A} \\text{c}{{\\text{m}}-2} {{\\text{K}}-2} and an ideality factor n≈ 3.6 , explained by a thin (<1 nm) oxide layer at the Gr/Si interface.

  5. Formation of oxide-trapped charges in 6H-SiC MOS structures

    Energy Technology Data Exchange (ETDEWEB)

    Yoshikawa, Masahito; Ohshima, Takeshi; Itoh, Hisayoshi; Nashiyama, Isamu [Japan Atomic Energy Research Inst., Takasaki, Gunma (Japan). Takasaki Radiation Chemistry Research Establishment; Okumura, Hajime; Yoshida, Sadafumi

    1997-03-01

    The silicon and the carbon faces of hexagonal silicon carbide (6H-SiC) substrates were oxidized pyrogenically at 1100degC, and the metal-oxide-semiconductor structures were formed on these faces. The MOS capacitors developed using the silicon and the carbon faces were irradiated with {sup 60}Co gamma-rays under argon atmosphere at room temperature. The bias voltages with the different polarity were applied to the gate electrode during irradiation to examine the formation mechanisms of the trapped charges in the oxides of these MOS capacitors. The amount of the trapped charges in the oxide were obtained from capacitance pulse voltage characteristics. The generation of the trapped charges are affects with not only the absorbed dose but also the bias polarity applied to the gate electrodes during irradiation. The formation mechanisms of the trapped charges in the oxides were estimated in conjunction with the surface orientation of 6H-SiC substrates. (author)

  6. Investigation on nonlinear optical properties of MoS2 nanoflake, grown on silicon and quartz substrates

    Science.gov (United States)

    Bayesteh, S.; Mortazavi, S. Z.; Reyhani, A.

    2018-03-01

    In this study, MoS2 was directly synthesized by one-step thermal chemical vapour deposition (TCVD), on different substrates including Si/SiO2 and quartz, using MoO3 and sulfide powders as precursor. The XRD patterns demonstrate the high crystallinity of MoS2 on Si/SiO2 and quartz substrates. SEM confirmed the formation of MoS2 grown on both substrates. According to line width and frequency difference between the E1 2g and A1g in Raman spectroscopy, it is inferred that the MoS2 grown on Si/SiO2 substrate is monolayer and the MoS2 grown on quartz substrate is multilayer. Moreover, by assessment of MoS2 nanoflake band gap via UV-visible analysis, it verified the formation of few layer structures. In addition, the open-aperture and close-aperture Z-scan techniques were employed to study the nonlinear optical properties including nonlinear absorption and nonlinear refraction of the synthesized MoS2. All experiments were performed using a diode laser with a wavelength of 532 nm as light source. The monolayer MoS2 synthesized on Si/SiO2, display considerable two-photon absorption. However, the multilayer MoS2 synthesized on quartz displayed saturable absorption (SA). It is noticeable that both samples demonstrate obvious self-defocusing behaviour.

  7. Memory effect in silicon time-gated single-photon avalanche diodes

    International Nuclear Information System (INIS)

    Dalla Mora, A.; Contini, D.; Di Sieno, L.; Tosi, A.; Boso, G.; Villa, F.; Pifferi, A.

    2015-01-01

    We present a comprehensive characterization of the memory effect arising in thin-junction silicon Single-Photon Avalanche Diodes (SPADs) when exposed to strong illumination. This partially unknown afterpulsing-like noise represents the main limiting factor when time-gated acquisitions are exploited to increase the measurement dynamic range of very fast (picosecond scale) and faint (single-photon) optical signals following a strong stray one. We report the dependences of this unwelcome signal-related noise on photon wavelength, detector temperature, and biasing conditions. Our results suggest that this so-called “memory effect” is generated in the deep regions of the detector, well below the depleted region, and its contribution on detector response is visible only when time-gated SPADs are exploited to reject a strong burst of photons

  8. Memory effect in silicon time-gated single-photon avalanche diodes

    Energy Technology Data Exchange (ETDEWEB)

    Dalla Mora, A.; Contini, D., E-mail: davide.contini@polimi.it; Di Sieno, L. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Tosi, A.; Boso, G.; Villa, F. [Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Pifferi, A. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); CNR, Istituto di Fotonica e Nanotecnologie, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

    2015-03-21

    We present a comprehensive characterization of the memory effect arising in thin-junction silicon Single-Photon Avalanche Diodes (SPADs) when exposed to strong illumination. This partially unknown afterpulsing-like noise represents the main limiting factor when time-gated acquisitions are exploited to increase the measurement dynamic range of very fast (picosecond scale) and faint (single-photon) optical signals following a strong stray one. We report the dependences of this unwelcome signal-related noise on photon wavelength, detector temperature, and biasing conditions. Our results suggest that this so-called “memory effect” is generated in the deep regions of the detector, well below the depleted region, and its contribution on detector response is visible only when time-gated SPADs are exploited to reject a strong burst of photons.

  9. C-V analysis at variable frequency of MOS structures with different gates, containing Hf-Doped Ta2O5

    International Nuclear Information System (INIS)

    Stojanovska-Georgievska, L.; Novkovski, N.; Atanassova, E.

    2012-01-01

    The quality of the interface between the insulating layer and the Si substrate in contemporary submicron MOS technology is a critical issue for device functioning. It is characterized through the electrically active defect centers, known as interface states. Their response to the frequency is discussed here, by analyzing capacitance-voltage and conductance-voltage curves. The C-V method is preferred in many cases, since it offers easy measurement, and it is applied to extract information about interface traps and fixed oxide charge, at different frequencies. This technique, related with frequency dependent G-V measurements, can be very useful in characterizing charge trapped in the dielectric and at the interface with Si. By extracting the value of frequency dependent flat band voltage, we have obtained the fixed oxide charges at flat band condition. A comparison between the results obtained by two different methods is made. The samples that are studied are metal-insulator-semiconductor (MIS) structures that include high-k dielectric as insulating layer (Hf doped Ta 2 O 5 ), with thickness of 8 nm, with different metal used as gate electrode. Here the influence of the top electrode on the generation and behavior of the traps in the oxide layer is discussed. The results show that the value of metal work function of the gate material is an issue that should be considered very carefully, especially in the case of high work function metal gates, when generation of extra positive charge than in the case of other metals is observed. (Author)

  10. All-optical 10 Gb/s AND logic gate in a silicon microring resonator

    DEFF Research Database (Denmark)

    Xiong, Meng; Lei, Lei; Ding, Yunhong

    2013-01-01

    An all-optical AND logic gate in a single silicon microring resonator is experimentally demonstrated at 10 Gb/s with 50% RZ-OOK signals. By setting the wavelengths of two intensity-modulated input pumps on the resonances of the microring resonator, field-enhanced four-wave mixing with a total inp...... power of only 8.5 dBm takes place in the ring, resulting in the generation of an idler whose intensity follows the logic operation between the pumps. Clear and open eye diagrams with a bit-error- ratio below 10−9 are achieved....

  11. An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

    International Nuclear Information System (INIS)

    Liu Ying; He Jin; Chan Mansun; Ye Yun; Zhao Wei; Wu Wen; Deng Wan-Ling; Wang Wen-Ping; Du Cai-Xia

    2014-01-01

    An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane's expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  12. Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

    Science.gov (United States)

    Kapoor, V. J.; Shokrani, M.

    1991-01-01

    A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

  13. Top-gate microcrystalline silicon TFTs processed at low temperature (<200 deg. C)

    International Nuclear Information System (INIS)

    Saboundji, A.; Coulon, N.; Gorin, A.; Lhermite, H.; Mohammed-Brahim, T.; Fonrodona, M.; Bertomeu, J.; Andreu, J.

    2005-01-01

    N-type as well P-type top-gate microcrystalline silicon thin film transistors (TFTs) are fabricated on glass substrates at a maximum temperature of 200 deg. C. The active layer is an undoped μc-Si film, 200 nm thick, deposited by Hot-Wire Chemical Vapor. The drain and source regions are highly phosphorus (N-type TFTs) or boron (P-type TFTs)-doped μc-films deposited by HW-CVD. The gate insulator is a silicon dioxide film deposited by RF sputtering. Al-SiO 2 -N type c-Si structures using this insulator present low flat-band voltage,-0.2 V, and low density of states at the interface D it =6.4x10 10 eV -1 cm -2 . High field effect mobility, 25 cm 2 /V s for electrons and 1.1 cm 2 /V s for holes, is obtained. These values are very high, particularly the hole mobility that was never reached previously

  14. Electro-optical logic gates based on graphene-silicon waveguides

    Science.gov (United States)

    Chen, Weiwei; Yang, Longzhi; Wang, Pengjun; Zhang, Yawei; Zhou, Liqiang; Yang, Tianjun; Wang, Yang; Yang, Jianyi

    2016-08-01

    In this paper, designs of electro-optical AND/NAND, OR/ NOR, XOR/XNOR logic gates based on cascaded silicon graphene switches and regular 2×1 multimode interference combiners are presented. Each switch consists of a Mach-Zehnder interferometer in which silicon slot waveguides embedded with graphene flakes are designed for phase shifters. High-speed switching function is achieved by applying an electrical signal to tune the Fermi levels of graphene flakes causing the variation of modal effective index. Calculation results show the crosstalk in the proposed optical switch is lower than -22.9 dB within a bandwidth from 1510 nm to 1600 nm. The designed six electro-optical logic gates with the operation speed of 10 Gbit/s have a minimum extinction ratio of 35.6 dB and a maximum insertion loss of 0.21 dB for transverse electric modes at 1.55 μm.

  15. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-01-07

    Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. Interface Trap Profiles in 4H- and 6H-SiC MOS Capacitors with Nitrogen- and Phosphorus-Doped Gate Oxides

    Science.gov (United States)

    Jiao, C.; Ahyi, A. C.; Dhar, S.; Morisette, D.; Myers-Ward, R.

    2017-04-01

    We report results on the interface trap density ( D it) of 4H- and 6H-SiC metal-oxide-semiconductor (MOS) capacitors with different interface chemistries. In addition to pure dry oxidation, we studied interfaces formed by annealing thermal oxides in NO or POCl3. The D it profiles, determined by the C- ψ s method, show that, although the as-oxidized 4H-SiC/SiO2 interface has a much higher D it profile than 6H-SiC/SiO2, after postoxidation annealing (POA), both polytypes maintain comparable D it near the conduction band edge for the gate oxides incorporated with nitrogen or phosphorus. Unlike most conventional C- V- or G- ω-based methods, the C- ψ s method is not limited by the maximum probe frequency, therefore taking into account the "fast traps" detected in previous work on 4H-SiC. The results indicate that such fast traps exist near the band edge of 6H-SiC also. For both polytypes, we show that the total interface trap density ( N it) integrated from the C- ψ s method is several times that obtained from the high-low method. The results suggest that the detected fast traps have a detrimental effect on electron transport in metal-oxide-semiconductor field-effect transistor (MOSFET) channels.

  17. Comments on the Huang and Taylor model of ion-implanted silicon-gate depletion-mode IGFET

    International Nuclear Information System (INIS)

    Marciniak, W.; Madura, H.

    1985-01-01

    Recently the Huang and Taylor model (HT model) of built-in channel MOS transistors has been widely used in the analysis of electronic circuits because of its relative simplicity. Huang and Taylor assumed that the effects of the finite channel thickness may be represented by an average semiconductor capacitance in series with the gate oxide capacitance. The derivation of the current-voltage characteristics is based on a linear equation of surface depleted charge density Qsub(s), which is calculated as the sheet charge of constant capacitance C-bar. This is done instead of using the exact solution of the Poisson equation, which has a rather complex form of nonlinear relationship between the charge Qsub(s) and the gate voltage. The basic equation is given. (author)

  18. Electrical characteristics of AlO{sub x}N{sub y} prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

    Energy Technology Data Exchange (ETDEWEB)

    Jeon, Sang Hun; Jang, Hyeon Woo; Kim, Hyun Soo; Noh, Do Young; Hwang, Hyun Sang [Kwangju Institute of Science and Technology, Kwangju (Korea, Republic of)

    2000-12-01

    In this research, the feasibility of ultrathin AlO{sub x}N{sub y} prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO{sub x}N{sub y}, respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO{sub 2}. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO{sub 2}. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

  19. Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

    CERN Document Server

    Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

    2000-01-01

    In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

  20. On the stability of silicon field effect capacitors with phosphate buffered saline electrolytic gate and self assembled monolayer gate insulator

    International Nuclear Information System (INIS)

    Hemed, Nofar Mintz; Inberg, Alexandra; Shacham-Diamand, Yosi

    2013-01-01

    We herein report on the stability of Electrolyte/Insulator/Semiconductor (EIS) devices with Self-Assembled Monolayer (SAM) gate insulator layers, i.e. Electrolyte/SAM/Semiconductor (ESS) devices. ESS devices can be functionalized creating highly specific sensors that can be integrated on standard silicon platform. However, biosensors by their nature are in contact with biological solutions that contain ions and molecules that may affect the device characteristics and cause electrical instability. In this paper we present a list of potential hazards to ESS devices and a study of the device stability under common testing conditions analyzing possible causes for the instabilities. ESS capacitors under open circuit conditions (i.e. open circuit bias of ∼0.6 V vs. Ag/AgCl reference electrode) were periodically characterized. We measured the complex impedance of the capacitors versus bias and extracted the effective capacitance vs. voltage (C–V) curves using two methods. We observed a parallel shift of the C–V curves toward negative bias; showing an effective accumulation of positive charge. The quantitative analysis of the drift vs. time was found to depend on the effective capacitance evaluation method. This effect is discussed and a best-known method is proposed. The devices surface composition was tested before and after the stress experiment by X-ray Photoelectron Spectroscopy (XPS) and sodium accumulation was observed. To further explore the flat-band voltage drift effect and to challenge the assumption that alkali ions are involved in the drift we conceived a novel alkali-free phosphate buffer saline (AF-PBS) where the sodium and potassium ions are replaced by ammonium ion and tested the capacitor under similar conditions to standard PBS. We found that the drift of the AF-PBS solution was much less at the first hour but was similar to that of the conventional PBS for longer stress times; hence, AF-PBS does not solve the long-term instability problem

  1. CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

    International Nuclear Information System (INIS)

    Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

    2011-01-01

    Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

  2. Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

    Science.gov (United States)

    Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

    2016-01-01

    The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

  3. Optical and Electrical Performance of MOS-Structure Silicon Solar Cells with Antireflective Transparent ITO and Plasmonic Indium Nanoparticles under Applied Bias Voltage.

    Science.gov (United States)

    Ho, Wen-Jeng; Sue, Ruei-Siang; Lin, Jian-Cheng; Syu, Hong-Jang; Lin, Ching-Fuh

    2016-08-10

    This paper reports impressive improvements in the optical and electrical performance of metal-oxide-semiconductor (MOS)-structure silicon solar cells through the incorporation of plasmonic indium nanoparticles (In-NPs) and an indium-tin-oxide (ITO) electrode with periodic holes (perforations) under applied bias voltage. Samples were prepared using a plain ITO electrode or perforated ITO electrode with and without In-NPs. The samples were characterized according to optical reflectance, dark current voltage, induced capacitance voltage, external quantum efficiency, and photovoltaic current voltage. Our results indicate that induced capacitance voltage and photovoltaic current voltage both depend on bias voltage, regardless of the type of ITO electrode. Under a bias voltage of 4.0 V, MOS cells with perforated ITO and plain ITO, respectively, presented conversion efficiencies of 17.53% and 15.80%. Under a bias voltage of 4.0 V, the inclusion of In-NPs increased the efficiency of cells with perforated ITO and plain ITO to 17.80% and 16.87%, respectively.

  4. Optical and Electrical Performance of MOS-Structure Silicon Solar Cells with Antireflective Transparent ITO and Plasmonic Indium Nanoparticles under Applied Bias Voltage

    Directory of Open Access Journals (Sweden)

    Wen-Jeng Ho

    2016-08-01

    Full Text Available This paper reports impressive improvements in the optical and electrical performance of metal-oxide-semiconductor (MOS-structure silicon solar cells through the incorporation of plasmonic indium nanoparticles (In-NPs and an indium-tin-oxide (ITO electrode with periodic holes (perforations under applied bias voltage. Samples were prepared using a plain ITO electrode or perforated ITO electrode with and without In-NPs. The samples were characterized according to optical reflectance, dark current voltage, induced capacitance voltage, external quantum efficiency, and photovoltaic current voltage. Our results indicate that induced capacitance voltage and photovoltaic current voltage both depend on bias voltage, regardless of the type of ITO electrode. Under a bias voltage of 4.0 V, MOS cells with perforated ITO and plain ITO, respectively, presented conversion efficiencies of 17.53% and 15.80%. Under a bias voltage of 4.0 V, the inclusion of In-NPs increased the efficiency of cells with perforated ITO and plain ITO to 17.80% and 16.87%, respectively.

  5. Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

    Science.gov (United States)

    Sengupta, Sarmista; Pandit, Soumya

    2015-06-01

    Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

  6. Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

    Science.gov (United States)

    An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

    2016-11-01

    Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

  7. Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

    Science.gov (United States)

    Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

    2013-06-01

    The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

  8. Coaxial-structured ZnO/silicon nanowires extended-gate field-effect transistor as pH sensor

    International Nuclear Information System (INIS)

    Li, Hung-Hsien; Yang, Chi-En; Kei, Chi-Chung; Su, Chung-Yi; Dai, Wei-Syuan; Tseng, Jung-Kuei; Yang, Po-Yu; Chou, Jung-Chuan; Cheng, Huang-Chung

    2013-01-01

    An extended-gate field-effect transistor (EGFET) of coaxial-structured ZnO/silicon nanowires as pH sensor was demonstrated in this paper. The oriented 1-μm-long silicon nanowires with the diameter of about 50 nm were vertically synthesized by the electroless metal deposition method at room temperature and were sequentially capped with the ZnO films using atomic layer deposition at 50 °C. The transfer characteristics (I DS –V REF ) of such ZnO/silicon nanowire EGFET sensor exhibited the sensitivity and linearity of 46.25 mV/pH and 0.9902, respectively for the different pH solutions (pH 1–pH 13). In contrast to the ZnO thin-film ones, the ZnO/silicon nanowire EGFET sensor achieved much better sensitivity and superior linearity. It was attributed to a high surface-to-volume ratio of the nanowire structures, reflecting a larger effective sensing area. The output voltage and time characteristics were also measured to indicate good reliability and durability for the ZnO/silicon nanowires sensor. Furthermore, the hysteresis was 9.74 mV after the solution was changed as pH 7 → pH 3 → pH 7 → pH 11 → pH 7. - Highlights: ► Coaxial-structured ZnO/silicon nanowire EGFET was demonstrated as pH sensor. ► EMD and ALD methods were proposed to fabricate ZnO/silicon nanowires. ► ZnO/silicon nanowire EGFET sensor achieved better sensitivity and linearity. ► ZnO/silicon nanowire EGFET sensor had good reliability and durability

  9. Design method for a digitally trimmable MOS transistor structure

    DEFF Research Database (Denmark)

    Ning, Feng; Bruun, Erik

    1996-01-01

    A digitally trimmable MOS transistor is a MOS transistor consisting of a drain, a source, and a main gate as well as several subgates. The transconductance of the transistor is tunabledigitally by means of connecting subgates either to the main gate or to the source terminal. In this paper, a sys...

  10. Analytical models for total dose ionization effects in MOS devices.

    Energy Technology Data Exchange (ETDEWEB)

    Campbell, Phillip Montgomery; Bogdan, Carolyn W.

    2008-08-01

    MOS devices are susceptible to damage by ionizing radiation due to charge buildup in gate, field and SOI buried oxides. Under positive bias holes created in the gate oxide will transport to the Si / SiO{sub 2} interface creating oxide-trapped charge. As a result of hole transport and trapping, hydrogen is liberated in the oxide which can create interface-trapped charge. The trapped charge will affect the threshold voltage and degrade the channel mobility. Neutralization of oxidetrapped charge by electron tunneling from the silicon and by thermal emission can take place over long periods of time. Neutralization of interface-trapped charge is not observed at room temperature. Analytical models are developed that account for the principal effects of total dose in MOS devices under different gate bias. The intent is to obtain closed-form solutions that can be used in circuit simulation. Expressions are derived for the aging effects of very low dose rate radiation over long time periods.

  11. Nanofabrication of Arrays of Silicon Field Emitters with Vertical Silicon Nanowire Current Limiters and Self-Aligned Gates

    Science.gov (United States)

    2016-08-19

    limiters, MEMS, NEMS, field emission, cold cathodes (Some figures may appear in colour only in the online journal) 1. Introduction Dense arrays of silicon... attention has been given to densely packed, highly ordered, top-down fabricated, single crystal vertical silicon nanowire devices that are embedded

  12. Simulation of current-voltage characteristics of a MOS structure considering the tunnel transport of carriers in semiconductor

    International Nuclear Information System (INIS)

    Vexler, M I

    2006-01-01

    The effect of a tunnel charge transport in the near-surface region of silicon on the electrical characteristics of MOS structures with a 2-3 nm insulator layer is studied theoretically. An equilibrium condition for the substrate is assumed. The cases of an Al and polySi gate are considered. The possibility of a 'double' (in Si and through SiO 2 ) tunnelling expands the energy range of transported particles, which increases one of the components of the total tunnel current. The proposed model allows for the improved simulation of gate current in MOSFETs, which is especially important for highly-doped substrates

  13. Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

    OpenAIRE

    Royer del Barrio, Pablo; López Vallejo, Marisa

    2014-01-01

    Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase f...

  14. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

    Science.gov (United States)

    Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

    2009-03-01

    The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

  15. Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

    International Nuclear Information System (INIS)

    Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

    2015-01-01

    Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  16. Dopant induced single electron tunneling within the sub-bands of single silicon NW tri-gate junctionless n-MOSFET

    Science.gov (United States)

    Uddin, Wasi; Georgiev, Yordan M.; Maity, Sarmistha; Das, Samaresh

    2017-09-01

    We report 1D electron transport of silicon junctionless tri-gate n-type transistor at 4.2 K. The step like curve observed in the current voltage characteristic suggests 1D transport. Besides the current steps for 1D transport, we found multiple spikes within individual steps, which we relate to inter-band single electron tunneling, mediated by the charged dopants available in the channel region. Clear Coulomb diamonds were observed in the stability diagram of the device. It is shown that a uniformly doped silicon nanowire can provide us the window for the single electron tunnelling. Back-gate versus front-gate color plot, where current is in a color scale, shows a crossover of the increased conduction region. This is a clear indication of the dopant-dopant interaction. It has been shown that back-gate biasing can be used to tune the coupling strength between the dopants.

  17. Radiation hardening of MOS devices by boron

    International Nuclear Information System (INIS)

    Danchenko, V.

    1975-01-01

    A novel technique is disclosed for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device of the type having a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. In the preferred embodiment, the novel inventive technique contemplates the introduction of boron into the insulating oxide, the boron being introduced within a layer of the oxide of about 100A to 300A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 atoms/ cm 3 . The novel technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations, which accumulations, if not eliminated, would cause shifting of the gate threshold potential of a radiation subjected MOS device, and thus render the device unstable and/or inoperative. (auth)

  18. Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

    Science.gov (United States)

    Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

    2017-12-01

    This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

  19. Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

    Science.gov (United States)

    Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki

    2018-04-01

    A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.

  20. Evolution of the MOS transistor - From conception to VLSI

    International Nuclear Information System (INIS)

    Sah, C.T.

    1988-01-01

    Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

  1. Silicon nanowire transistors

    CERN Document Server

    Bindal, Ahmet

    2016-01-01

    This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...

  2. Minority Carrier Tunneling and Stress-Induced Leakage Current for p+ gate MOS Capacitors with Poly-Si and PolySi0.7Ge0.3 Gate Material

    NARCIS (Netherlands)

    Houtsma, V.E.; Holleman, J.; Salm, Cora; de Haan, I.R.; Schmitz, Jurriaan; Widdershoven, F.P.; Widdershoven, F.P.; Woerlee, P.H.

    1999-01-01

    In this paper the I-V conduction mechanism for gate injection (-V g), Stress-Induced Leakage Current (SILC) characteristics and time-to-breakdown (tbd) of PMOS capacitors with p+-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier

  3. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    KAUST Repository

    Ghoneim, Mohamed T.

    2015-06-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

  4. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    KAUST Repository

    Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

    2015-01-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

  5. A compact plasmonic MOS-based 2×2 electro-optic switch

    Directory of Open Access Journals (Sweden)

    Ye Chenran

    2015-01-01

    Full Text Available We report on a three-waveguide electro-optic switch for compact photonic integrated circuits and data routing applications. The device features a plasmonic metal-oxide-semiconductor (MOS mode for enhanced light-matter-interactions. The switching mechanism originates from a capacitor-like design where the refractive index of the active medium, indium-tin-oxide, is altered via shifting the plasma frequency due to carrier accumulation inside the waveguide-based MOS structure. This light manipulation mechanism controls the transmission direction of transverse magnetic polarized light into either a CROSS or BAR waveguide port. The extinction ratio of 18 (7 dB for the CROSS (BAR state, respectively, is achieved via a gating voltage bias. The ultrafast broadband fJ/bit device allows for seamless integration with silicon-on-insulator platforms for low-cost manufacturing.

  6. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2013-01-01

    (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

  7. High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor.

    Science.gov (United States)

    Al-Hardan, Naif H; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N

    2016-06-07

    In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

  8. Exploring the Short-Channel Characteristics of Asymmetric Junctionless Double-Gate Silicon-on-Nothing MOSFET

    Science.gov (United States)

    Saha, Priyanka; Banerjee, Pritha; Dash, Dinesh Kumar; Sarkar, Subir Kumar

    2018-03-01

    This paper presents an analytical model of an asymmetric junctionless double-gate (asymmetric DGJL) silicon-on-nothing metal-oxide-semiconductor field-effect transistor (MOSFET). Solving the 2-D Poisson's equation, the expressions for center potential and threshold voltage are calculated. In addition, the response of the device toward the various short-channel effects like hot carrier effect, drain-induced barrier lowering and threshold voltage roll-off has also been examined along with subthreshold swing and drain current characteristics. Performance analysis of the present model is also demonstrated by comparing its short-channel behavior with conventional DGJL MOSFET. The effect of variation of the device features due to the variation of device parameters is also studied. The simulated results obtained using 2D device simulator, namely ATLAS, are in good agreement with the analytical results, hence validating our derived model.

  9. High Sensitivity pH Sensor Based on Porous Silicon (PSi Extended Gate Field-Effect Transistor

    Directory of Open Access Journals (Sweden)

    Naif H. Al-Hardan

    2016-06-01

    Full Text Available In this study, porous silicon (PSi was prepared and tested as an extended gate field-effect transistor (EGFET for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

  10. Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon—germanium substrates

    International Nuclear Information System (INIS)

    Tiwari Pramod Kumar; Saramekala Gopi Krishna; Mukhopadhyay Anand Kumar; Dubey Sarvesh

    2014-01-01

    The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon—germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS™ by Silvaco Inc. (semiconductor devices)

  11. OTFT with pentacene-gate dielectric interface modified by silicon nanoparticles

    International Nuclear Information System (INIS)

    Jakabovic, J.; Kovac, J.; Srnanek, R.; Guldan, S.; Donoval, D.; Weis, M.; Sokolsky, M.; Cirak, J.; Broch, K.; Schreiber, F.

    2011-01-01

    We have for the first time investigated the structural and electrical properties of pentacene OTFT deposited on the semiconductor-gate insulator interface covered with SiNPs monolayer prepared by the LB method and compared these to a reference sample (without SiNPs). The micro-Raman, AFM and XRD measurements confirmed that the pentacene layer deposited on the semiconductor-gate insulator interface covered with a SiNPs monolayer on both hydrophobic and hydrophilic surfaces changes the structure. The Raman measurements show that the average value of α is between 0.8 and 1.0. The different structural quality of pentacene leads to better OTFTs electrical characteristics mainly saturation current of OTFTs with SiNPs increasing (∼ 2.5 x) with storing time (85 days) in comparison to OTFTs without SiNPs, which decrease similarly after 85 days.

  12. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    KAUST Repository

    Sevilla, Galo T.; Almuslem, A. S.; Gumus, Abdurrahman; Hussain, Aftab M.; Hussain, Aftab M.; Cruz, Melvin; Hussain, Muhammad Mustafa

    2016-01-01

    shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using

  13. Application of MOS structures to gamma dosimetry

    International Nuclear Information System (INIS)

    Frank, H.

    1978-01-01

    Lattice disorders induced in SiO 2 layers by irradiation are described, and the possibility of using MOS transistors for gamma dosimetry is discussed. Furthermore, experimental results are given for Czechoslovakian MOS transistors of MH 2009 type after gamma irradiation. Reference measurements with other irradiation sources have shown that the transistors respond only to those types of radiation which induce space charges in the oxide layer. They are, therefore, insensitive to neutrons and thus in contrast to dosimetric silicon diodes. Circuitry, sensitivity, and fading of MOS transistors are given, and a physical functional model is compared with the experimental results. (author)

  14. High-current and low acceleration voltage arsenic ion implanted polysilicon-gate and source-drain electrode Si mos transistor

    International Nuclear Information System (INIS)

    Saito, Yasuyuki; Sugimura, Yoshiro; Sugihara, Michiyuki

    1993-01-01

    The fabrication process of high current arsenic (As) ion implanted polysilicon (Si) gate and source drain (SD) electrode Si n-channel metal oxide-semiconductor field effect transistor (MOSFET) was examined. Poly Si film n-type doping was performed by using high current (typical current: 2mA) and relatively low acceleration voltage (40keV) As ion implantation technique (Lintott series 3). It was observed that high dose As implanted poly Si films as is show refractoriness against radical fluorine excited by microwave. Using GCA MANN4800 (m/c ID No.2, resist: OFPR) mask pattern printing technique, the high current As ion implantation technique and radical fluorine gas phase etching (Chemical dry etching: CDE) technique, the n-channel Poly Si gate (ρs = ≅100Ω/□) enhancement MQSFETs(ρs source drain = ≅50Ω/□, SiO 2 gate=380 angstrom) with off-leak-less were obtained on 3 inch Czochralski grown 2Ωcm boron doped p type wafers (Osaka titanium). By the same process, a 8 bit single chip μ-processor with 26MHz full operation was performed

  15. Flexible high-κ/Metal gate metal/insulator/metal capacitors on silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-10-01

    Implementation of memory on bendable substrates is an important step toward a complete and fully developed notion of mechanically flexible computational systems. In this paper, we have demonstrated a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric. We rely on standard microfabrication processes to release a thin sheet of bendable silicon (area: 18 {\\ m cm}2 and thickness: 25 \\\\mu{\\ m m}) in an inexpensive and reliable way. On such platform, we fabricated and characterized the devices showing mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and nominal strain of 0.125%) and consistent electrical behavior regardless of the applied mechanical stress. Furthermore, and for the first time, we performed a reliability study suggesting no significant difference in performance and showing an improvement in lifetime projections. © 1963-2012 IEEE.

  16. Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions

    Directory of Open Access Journals (Sweden)

    Keyvan Narimani

    2018-04-01

    Full Text Available In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET with gate-all-around (GAA structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm Optimized devices also show excellent current saturation, an important feature for analog performance.

  17. Determination of the hole effective mass in thin silicon dioxide film by means of an analysis of characteristics of a MOS tunnel emitter transistor

    International Nuclear Information System (INIS)

    Vexler, M I; Tyaginov, S E; Shulekin, A F

    2005-01-01

    The value of m h = 0.33 m 0 has been experimentally obtained for hole effective mass in a tunnel-thin (2-3 nm) SiO 2 film. The use of this value ensures the adequate modelling of a direct-tunnelling hole current in MOS devices. For the first time, in order to determine m h , the characteristics of a MOS tunnel emitter transistor have been mathematically processed, that allows for the precise estimation of the effective oxide thickness, as the electron effective mass in SiO 2 is independently known from the literature. The formulae for simulation of currents in a tunnel MOS structure are listed along with the necessary parameter values

  18. SOI Fully complementary BI-JFET-MOS technology for analog-digital applications with vertical BJT's

    International Nuclear Information System (INIS)

    Delevoye, E.; Blanc, J.P.; Bonaime, J.; Pontcharra, J. de; Gautier, J.; Martin, F.; Truche, R.

    1993-01-01

    A silicon-on-insulator, fully complementary, Bi-JFET-MOS technology has been developed for realizing multi-megarad hardened mixed analog-digital circuits. The six different active components plus resistors and capacitors have been successfully integrated in a 25-mask process using SIMOX substrate and 1 μm thick epitaxial layer. Different constraints such as device compatibility, complexity not higher than BiCMOS technology and breakdown voltages suitable for analog applications have been considered. Several process splits have been realized and all the characteristics presented here have been measured on the same split. P + gate is used for PMOS transistor to get N and PMOST symmetrical characteristics. Both NPN and PNP vertical bipolar transistors with poly-emitters show f T > 5 GHz. 2-separated gate JFET's need no additional mask. (authors). 9 figs., 1 tab

  19. MOS memory structures by very-low-energy-implanted Si in thin SiO{sub 2}

    Energy Technology Data Exchange (ETDEWEB)

    Dimitrakis, P.; Kapetanakis, E.; Normand, P.; Skarlatos, D.; Tsoukalas, D.; Beltsios, K.; Claverie, A.; Benassayag, G.; Bonafos, C.; Chassaing, D.; Carrada, M.; Soncini, V

    2003-08-15

    The electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals obtained by low-energy ion beam implantation and subsequent annealing have been investigated through capacitance and current-voltage measurements of MOS capacitors. The effects of the implantation energy (range: 0.65-2 keV), annealing temperature (950-1050 deg. C) and injection oxide characteristics on charge injection and storage are reported. It is shown that the implantation energy allows for a fine control of the memory window characteristics, and various device options are possible including memory operation with charge injection at low gate voltages.

  20. Simulation of 1.5-mm-thick and 15-cm-diameter gated silicon drift X-ray detector operated with a single high-voltage source

    Science.gov (United States)

    Matsuura, Hideharu

    2015-04-01

    High-resolution silicon X-ray detectors with a large active area are required for effectively detecting traces of hazardous elements in food and soil through the measurement of the energies and counts of X-ray fluorescence photons radially emitted from these elements. The thicknesses and areas of commercial silicon drift detectors (SDDs) are up to 0.5 mm and 1.5 cm2, respectively. We describe 1.5-mm-thick gated SDDs (GSDDs) that can detect photons with energies up to 50 keV. We simulated the electric potential distributions in GSDDs with a Si thickness of 1.5 mm and areas from 0.18 to 168 cm2 at a single high reverse bias. The area of a GSDD could be enlarged simply by increasing all the gate widths by the same multiple, and the capacitance of the GSDD remained small and its X-ray count rate remained high.

  1. Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

    KAUST Repository

    Fahad, Hossain M.

    2011-10-12

    We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

  2. Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

    KAUST Repository

    Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2011-01-01

    We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

  3. Computer assisted design of poly-silicon gated enhancement-mode, lateral double quantum dot devices for quantum computing

    Science.gov (United States)

    Bishop, Nathaniel; Young, Ralph; Borras Pinilla, Carlos; Stalford, Harold; Nielsen, Erik; Muller, Richard; Rahman, Rajib; Tracy, Lisa; Wendt, Joel; Lilly, Michael; Carroll, Malcolm

    2012-02-01

    We discuss trade-offs of different double quantum dot and charge sensor lay-outs using computer assisted design (CAD). We use primarily a semi-classical model, augmented with a self-consistent configuration interaction method. Although CAD for quantum dots is difficult due to uncontrolled factors (e.g., disorder), different ideal designs can still be compared. Comparisons of simulation and measured dot characteristics, such as capacitance, show that CAD can agree well with experiment for relevant cases. CAD results comparing several different designs will be discussed including a comparison to measurement results from the same designs. Trade-offs between poly-silicon and metal gate lay-outs will also be discussed. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. The work was supported by the Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

  4. Optimization of process parameter variations on leakage current in in silicon-oninsulator vertical double gate mosfet device

    Directory of Open Access Journals (Sweden)

    K.E. Kaharudin

    2015-12-01

    Full Text Available This paper presents a study of optimizing input process parameters on leakage current (IOFF in silicon-on-insulator (SOI Vertical Double-Gate,Metal Oxide Field-Effect-Transistor (MOSFET by using L36 Taguchi method. The performance of SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF value. An orthogonal array, main effects, signal-to-noise ratio (SNR and analysis of variance (ANOVA are utilized in order to analyze the effect of input process parameter variation on leakage current (IOFF. Based on the results, the minimum leakage current ((IOFF of SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION value at 434 µA/µm. Both the drive current (ION and leakage current (IOFF values yield a higher ION/IOFF ratio (48.22 x 106 for low power consumption application. Meanwhile, polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors with each of the contributing factor effects percentage of 59% and 25%.

  5. Quantum confinement effects and source-to-drain tunneling in ultra-scaled double-gate silicon n-MOSFETs

    International Nuclear Information System (INIS)

    Jiang Xiang-Wei; Li Shu-Shen

    2012-01-01

    By using the linear combination of bulk band (LCBB) method incorporated with the top of the barrier splitting (TBS) model, we present a comprehensive study on the quantum confinement effects and the source-to-drain tunneling in the ultra-scaled double-gate (DG) metal—oxide—semiconductor field-effect transistors (MOSFETs). A critical body thickness value of 5 nm is found, below which severe valley splittings among different X valleys for the occupied charge density and the current contributions occur in ultra-thin silicon body structures. It is also found that the tunneling current could be nearly 100% with an ultra-scaled channel length. Different from the previous simulation results, it is found that the source-to-drain tunneling could be effectively suppressed in the ultra-thin body thickness (2.0 nm and below) by the quantum confinement and the tunneling could be suppressed down to below 5% when the channel length approaches 16 nm regardless of the body thickness. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  6. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-02-12

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  7. Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

    Science.gov (United States)

    Chang, You-Tai; Peng, Kang-Ping; Li, Pei-Wen; Lin, Horng-Chih

    2018-04-01

    In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

  8. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

    2013-01-01

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  9. Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

    Science.gov (United States)

    Tiwari, Vishal A.; Divakaruni, Rama; Hook, Terence B.; Nair, Deleep R.

    2016-04-01

    Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.

  10. A refractory metal gate approach for micronic CMOS technology

    International Nuclear Information System (INIS)

    Lubowiecki, V.; Ledys, J.L.; Plossu, C.; Balland, B.

    1987-01-01

    In the future, devices scaling down, integration density and performance improvements are going to bring a number of conventional circuit design and process techniques to their fundamental limits. To avoid any severe limitations in MOS ULSI (Ultra Large Scale Integration) technologies, interconnection materials and schemes are required to emerge, in order to face the Megabits memory field. Among those, the gate approach will obviously take a keyrole, when the operating speed of ULSI chips will reach the practical upper limits imposed by parasitic resistances and capacitances which stem from the circuit interconnect wiring. Even if fairly suitable for MOS process, doped polycrystalline silicon is being gradually replaced by refractory metal silicide or polycide structures, which match better with low resistivity requirements. However, as we approach the submicronic IC's, higher conductivity materials will be paid more and more attention. Recently, works have been devoted and published on refractory metal gate technologies. Molybdenum or tungsten, deposited either by CVD or PVD methods, are currently reported even if some drawbacks in their process integration still remain. This paper is willing to present such an approach based on tungsten (more reliable than Molybdenum deposited by LPCVD (giving more conductive and more stable films than PVD). Deposition process will be first described. Then CMOS process flow will allow us to focus on specific refractory metal gate issues. Finally, electrical and physical properties will be assessed, which will demonstrate the feasibility of such a technology as well as the compatibility of the tungsten with most of the usual techniques

  11. Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

    Directory of Open Access Journals (Sweden)

    Paul C. McIntyre

    2012-07-01

    Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

  12. Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

    International Nuclear Information System (INIS)

    Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

    2005-01-01

    AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

  13. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  14. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    Science.gov (United States)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  15. Submicron Silicon MOSFET

    Science.gov (United States)

    Daud, T.

    1986-01-01

    Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

  16. Effects of series and parallel resistances on the C-V characteristics of silicon-based metal oxide semiconductor (MOS) devices

    Science.gov (United States)

    Omar, Rejaiba; Mohamed, Ben Amar; Adel, Matoussi

    2015-04-01

    This paper investigates the electrical behavior of the Al/SiO2/Si MOS structure. We have used the complex admittance method to develop an analytical model of total capacitance applied to our proposed equivalent circuit. The charge density, surface potential, semiconductor capacitance, flatband and threshold voltages have been determined by resolving the Poisson transport equations. This modeling is used to predict in particular the effects of frequency, parallel and series resistance on the capacitance-voltage characteristic. Results show that the variation of both frequency and parallel resistance causes strong dispersion of the C-V curves in the inversion regime. It also reveals that the series resistance influences the shape of C-V curves essentially in accumulation and inversion modes. A significant decrease of the accumulation capacitance is observed when R s increases in the range 200-50000 Ω. The degradation of the C-V magnitude is found to be more pronounced when the series resistance depends on the substrate doping density. When R s varies in the range 100 Ω-50 kΩ, it shows a decrease in the flatband voltage from -1.40 to -1.26 V and an increase in the threshold voltage negatively from -0.28 to -0.74 V, respectively. Good agreement has been observed between simulated and measured C-V curves obtained at high frequency. This study is necessary to control the adverse effects that disrupt the operation of the MOS structure in different regimes and optimizes the efficiency of such electronic device before manufacturing.

  17. Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

    Science.gov (United States)

    Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

    2018-04-01

    We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

  18. Intercalation of Si between MoS2 layers

    Directory of Open Access Journals (Sweden)

    Rik van Bremen

    2017-09-01

    Full Text Available We report a combined experimental and theoretical study of the growth of sub-monolayer amounts of silicon (Si on molybdenum disulfide (MoS2. At room temperature and low deposition rates we have found compelling evidence that the deposited Si atoms intercalate between the MoS2 layers. Our evidence relies on several experimental observations: (1 Upon the deposition of Si on pristine MoS2 the morphology of the surface transforms from a smooth surface to a hill-and-valley surface. The lattice constant of the hill-and-valley structure amounts to 3.16 Å, which is exactly the lattice constant of pristine MoS2. (2 The transitions from hills to valleys are not abrupt, as one would expect for epitaxial islands growing on-top of a substrate, but very gradual. (3 I(V scanning tunneling spectroscopy spectra recorded at the hills and valleys reveal no noteworthy differences. (4 Spatial maps of dI/dz reveal that the surface exhibits a uniform work function and a lattice constant of 3.16 Å. (5 X-ray photo-electron spectroscopy measurements reveal that sputtering of the MoS2/Si substrate does not lead to a decrease, but an increase of the relative Si signal. Based on these experimental observations we have to conclude that deposited Si atoms do not reside on the MoS2 surface, but rather intercalate between the MoS2 layers. Our conclusion that Si intercalates upon the deposition on MoS2 is at variance with the interpretation by Chiappe et al. (Adv. Mater. 2014, 26, 2096–2101 that silicon forms a highly strained epitaxial layer on MoS2. Finally, density functional theory calculations indicate that silicene clusters encapsulated by MoS2 are stable.

  19. Development of mos thyristor technological processes for functional integration of new power devices; Developpement de filieres technologiques mos-thyristor adaptees a l`integration fonctionnelle de nouveaux dispositifs de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Berriane, R.

    1997-05-05

    The development of MOS thyristor technological processes for integration of the switching function for high voltage power applications in industrial supply networks, is studied. A MOS-gated optically triggered thyristor is presented, which includes a MOS gated thyristor constituting the power element and a photodiode for optical control detection; protection and control are obtained respectively by a Zener diode and a depletion MOSFET transistor. In order to verify the switching function, a model is proposed and a high voltage planar aluminium gate process technology, compatible with various bipolar and MOSFET devices associations have been developed and optimized. In the framework of industrial supply networks, the integration of a thermal protection element has been investigated. The dual thyristor function application has been also studied, composed of a spontaneously fired, controlled turn off MOS-thyristor association. The early developments of a MOS thyristor polysilicon gate process technology is then presented

  20. I-V and C-V Characterization of a High-Responsivity Graphene/Silicon Photodiode with Embedded MOS Capacitor.

    Science.gov (United States)

    Luongo, Giuseppe; Giubileo, Filippo; Genovese, Luca; Iemmo, Laura; Martucciello, Nadia; Di Bartolomeo, Antonio

    2017-06-27

    We study the effect of temperature and light on the I-V and C-V characteristics of a graphene/silicon Schottky diode. The device exhibits a reverse-bias photocurrent exceeding the forward current and achieves a photoresponsivity as high as 2.5 A / W . We show that the enhanced photocurrent is due to photo-generated carriers injected in the graphene/Si junction from the parasitic graphene/SiO₂/Si capacitor connected in parallel to the diode. The same mechanism can occur with thermally generated carriers, which contribute to the high leakage current often observed in graphene/Si junctions.

  1. I-V and C-V Characterization of a High-Responsivity Graphene/Silicon Photodiode with Embedded MOS Capacitor

    OpenAIRE

    Luongo, Giuseppe; Giubileo, Filippo; Genovese, Luca; Iemmo, Laura; Martucciello, Nadia; Di Bartolomeo, Antonio

    2017-01-01

    We study the effect of temperature and light on the I-V and C-V characteristics of a graphene/silicon Schottky diode. The device exhibits a reverse-bias photocurrent exceeding the forward current and achieves a photoresponsivity as high as 2.5 ? A / W . We show that the enhanced photocurrent is due to photo-generated carriers injected in the graphene/Si junction from the parasitic graphene/SiO2/Si capacitor connected in parallel to the diode. The same mechanism can occur with thermally genera...

  2. Online junction temperature measurement using peak gate current

    DEFF Research Database (Denmark)

    Baker, Nick; Munk-Nielsen, Stig; Iannuzzo, Francesco

    2015-01-01

    A new method for junction temperature measurement of MOS-gated power semiconductor switches is presented. The measurement method involves detecting the peak voltage over the external gate resistor of an IGBT or MOSFET during turn-on. This voltage is directly proportional to the peak gate current...

  3. Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors

    International Nuclear Information System (INIS)

    Jin, Xiaoshi; Liu, Xi; Lee, Jung-Hee; Lee, Jong-Ho

    2014-01-01

    A subthreshold model of short-channel junctionless field effect transistors with cylindrical surrounding-gate nanowire structure has been proposed. It was based on an approximated solution of two-dimensional Poisson's equation. The derivation of this model was introduced and the accuracy of the proposed models have been verified by comparison with both previous models and the SILVACO Atlas TCAD simulation results, which show good agreement. (paper)

  4. Specific features of the switch-on gate current and different switch-on modes in silicon carbide thyristors

    International Nuclear Information System (INIS)

    Yurkov, S N; Mnatsakanov, T T; Levinshtein, M E; Cheng, L; Palmour, J W

    2014-01-01

    The specific features of the temperature and bias dependences of the switch-on gate current in SiC thyristors are examined analytically for two possible switching mechanisms. The so-called γ-mechanism, which is highly typical of the conventional Si thyristors, is characterized by very weak temperature and bias dependences. By contrast, the so-called α-mechanism, which is very characteristic of SiC thyristors, is highly sensitive to changes in temperature and bias. If the thyristor is switched on by the α-mechanism, the switch-on gate current density decreases very steeply with increasing temperature. As a result, the thyristor can lose its working capacity at elevated temperatures due to the instability against even very weak impacts. With decreasing the bias voltage U a , the gate switch-on current increases very steeply, which can make switching the thyristor on difficult. The unintentional shunting, which is apparently present in high-voltage SiC thyristors, causes the transition from the α- to the γ-mechanism at elevated temperatures and high biases. It can be supposed that introduction of a controllable technological shunting of the emitter–thin base junction allows stabilization of the temperature and bias parameters of SiC thyristors. The analytical results are confirmed by computer simulations performed in wide temperature and bias ranges for a 4H-SiC thyristor of the 18 kV class. (paper)

  5. Controlled synthesis of high-quality crystals of monolayer MoS2 for nanoelectronic device application

    DEFF Research Database (Denmark)

    Yang, Xiaonian; Li, Qiang; Hu, Guofeng

    2016-01-01

    . Monolayer MoS2 so far can be obtained by mechanical exfoliation or chemical vapor deposition (CVD). However, controllable synthesis of large area monolayer MoS2 with high quality needs to be improved and their growth mechanism requires more studies. Here we report a systematical study on controlled...... synthesis of high-quality monolayer MoS2 single crystals using low pressure CVD. Large-size monolayer MoS2 triangles with an edge length up to 405 mu m were successfully synthesized. The Raman and photoluminescence spectroscopy studies indicate high homogenous optical characteristic of the synthesized...... monolayer MoS2 triangles. The transmission electron microscopy results demonstrate that monolayer MoS2 triangles are single crystals. The back-gated field effect transistors (FETs) fabricated using the as-grown monolayer MoS2 show typical n-type semiconductor behaviors with carrier mobility up to 21.8 cm(2...

  6. Characterization of epitaxial GaAs MOS capacitors using atomic layer-deposited TiO2/Al2O3 gate stack: study of Ge auto-doping and p-type Zn doping.

    Science.gov (United States)

    Dalapati, Goutam Kumar; Shun Wong, Terence Kin; Li, Yang; Chia, Ching Kean; Das, Anindita; Mahata, Chandreswar; Gao, Han; Chattopadhyay, Sanatan; Kumar, Manippady Krishna; Seng, Hwee Leng; Maiti, Chinmay Kumar; Chi, Dong Zhi

    2012-02-02

    Electrical and physical properties of a metal-oxide-semiconductor [MOS] structure using atomic layer-deposited high-k dielectrics (TiO2/Al2O3) and epitaxial GaAs [epi-GaAs] grown on Ge(100) substrates have been investigated. The epi-GaAs, either undoped or Zn-doped, was grown using metal-organic chemical vapor deposition method at 620°C to 650°C. The diffusion of Ge atoms into epi-GaAs resulted in auto-doping, and therefore, an n-MOS behavior was observed for undoped and Zn-doped epi-GaAs with the doping concentration up to approximately 1017 cm-3. This is attributed to the diffusion of a significant amount of Ge atoms from the Ge substrate as confirmed by the simulation using SILVACO software and also from the secondary ion mass spectrometry analyses. The Zn-doped epi-GaAs with a doping concentration of approximately 1018 cm-3 converts the epi-GaAs layer into p-type since the Zn doping is relatively higher than the out-diffused Ge concentration. The capacitance-voltage characteristics show similar frequency dispersion and leakage current for n-type and p-type epi-GaAs layers with very low hysteresis voltage (approximately 10 mV).PACS: 81.15.Gh.

  7. Online MOS Capacitor Characterization in LabVIEW Environment

    Directory of Open Access Journals (Sweden)

    Chinmay K Maiti

    2009-08-01

    Full Text Available We present an automated evaluation procedure to characterize MOS capacitors involving high-k gate dielectrics. Suitability of LabVIEW environment for online web-based semiconductor device characterization is demonstrated. Developed algorithms have been successfully applied to automate the MOS capacitor measurements for Capacitance-Voltage, Conductance-Voltage and Current-Voltage characteristics. Implementation of the algorithm for use as a remote internet-based characterization tool where the client and server communicate with each other via web services is also shown.

  8. Transfer-less flexible and transparent high-κ/metal gate germanium devices on bulk silicon (100)

    KAUST Repository

    Nassar, Joanna M.; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2014-01-01

    Flexible wearable electronics have been of great interest lately for the development of innovative future technology for various interactive applications in the field of consumer electronics and advanced healthcare, offering the promise of low-cost, lightweight, and multifunctionality. In the pursuit of this trend, high mobility channel materials need to be investigated on a flexible platform, for the development of flexible high performance devices. Germanium (Ge) is one of the most attractive alternatives for silicon (Si) for high-speed computational applications, due its higher hole and electron mobility. Thus, in this work we show a cost effective CMOS compatible process for transforming conventional rigid Ge metal oxide semiconductor capacitors (MOSCAPS) into a mechanically flexible and semi-transparent platform. Devices exhibit outstanding bendability with a bending radius of 0.24 cm, and semi-transparency up to 30 %, varying with respect to the diameter size of the release holes array.

  9. Transfer-less flexible and transparent high-κ/metal gate germanium devices on bulk silicon (100)

    KAUST Repository

    Nassar, Joanna M.

    2014-08-01

    Flexible wearable electronics have been of great interest lately for the development of innovative future technology for various interactive applications in the field of consumer electronics and advanced healthcare, offering the promise of low-cost, lightweight, and multifunctionality. In the pursuit of this trend, high mobility channel materials need to be investigated on a flexible platform, for the development of flexible high performance devices. Germanium (Ge) is one of the most attractive alternatives for silicon (Si) for high-speed computational applications, due its higher hole and electron mobility. Thus, in this work we show a cost effective CMOS compatible process for transforming conventional rigid Ge metal oxide semiconductor capacitors (MOSCAPS) into a mechanically flexible and semi-transparent platform. Devices exhibit outstanding bendability with a bending radius of 0.24 cm, and semi-transparency up to 30 %, varying with respect to the diameter size of the release holes array.

  10. X-ray radiation damage studies and design of a silicon pixel sensor for science at the XFEL

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Jiaguo

    2013-06-15

    Experiments at the European X-ray Free Electron Laser (XFEL) require silicon pixel sensors which can withstand X-ray doses up to 1 GGy. For the investigation of Xray radiation damage up to these high doses, MOS capacitors and gate-controlled diodes built on high resistivity n-doped silicon with crystal orientations left angle 100 right angle and left angle 111 right angle produced by four vendors, CiS, Hamamatsu, Canberra and Sintef have been irradiated with 12 keV X-rays at the DESY DORIS III synchrotron-light source. Using capacitance/ conductance-voltage, current-voltage and thermal dielectric relaxation current measurements, the densities of oxide charges and interface traps at the Si-SiO{sub 2} interface, and the surface-current densities have been determined as function of dose. Results indicate that the dose dependence of the oxide-charge density, the interface-trap density and the surface-current density depend on the crystal orientation and producer. In addition, the influence of the voltage applied to the gates of the MOS capacitor and the gate-controlled diode during X-ray irradiation on the oxide-charge density, the interface-trap density and the surface-current density has been investigated at doses of 100 kGy and 100 MGy. It is found that both strongly depend on the gate voltage if the electric field in the oxide points from the surface of the SiO{sub 2} to the Si-SiO{sub 2} interface. To verify the long-term stability of irradiated silicon sensors, annealing studies have been performed at 60 C and 80 C on MOS capacitors and gate-controlled diodes irradiated to 5 MGy as well, and the annealing kinetics of oxide charges and surface current were determined. Moreover, the macroscopic electrical properties of segmented sensors have slao been investigated as function of dose. It is found that the defects introduced by X-rays increase the full depletion voltage, the surface leakage current and the inter-electrode capacitance of the segmented sensor. An

  11. X-ray radiation damage studies and design of a silicon pixel sensor for science at the XFEL

    International Nuclear Information System (INIS)

    Zhang, Jiaguo

    2013-06-01

    Experiments at the European X-ray Free Electron Laser (XFEL) require silicon pixel sensors which can withstand X-ray doses up to 1 GGy. For the investigation of Xray radiation damage up to these high doses, MOS capacitors and gate-controlled diodes built on high resistivity n-doped silicon with crystal orientations left angle 100 right angle and left angle 111 right angle produced by four vendors, CiS, Hamamatsu, Canberra and Sintef have been irradiated with 12 keV X-rays at the DESY DORIS III synchrotron-light source. Using capacitance/ conductance-voltage, current-voltage and thermal dielectric relaxation current measurements, the densities of oxide charges and interface traps at the Si-SiO 2 interface, and the surface-current densities have been determined as function of dose. Results indicate that the dose dependence of the oxide-charge density, the interface-trap density and the surface-current density depend on the crystal orientation and producer. In addition, the influence of the voltage applied to the gates of the MOS capacitor and the gate-controlled diode during X-ray irradiation on the oxide-charge density, the interface-trap density and the surface-current density has been investigated at doses of 100 kGy and 100 MGy. It is found that both strongly depend on the gate voltage if the electric field in the oxide points from the surface of the SiO 2 to the Si-SiO 2 interface. To verify the long-term stability of irradiated silicon sensors, annealing studies have been performed at 60 C and 80 C on MOS capacitors and gate-controlled diodes irradiated to 5 MGy as well, and the annealing kinetics of oxide charges and surface current were determined. Moreover, the macroscopic electrical properties of segmented sensors have slao been investigated as function of dose. It is found that the defects introduced by X-rays increase the full depletion voltage, the surface leakage current and the inter-electrode capacitance of the segmented sensor. An electron

  12. CMOS-compatible batch processing of monolayer MoS2 MOSFETs

    Science.gov (United States)

    Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

    2018-04-01

    Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

  13. Silicon Qubits

    Energy Technology Data Exchange (ETDEWEB)

    Ladd, Thaddeus D. [HRL Laboratories, LLC, Malibu, CA (United States); Carroll, Malcolm S. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2018-02-28

    Silicon is a promising material candidate for qubits due to the combination of worldwide infrastructure in silicon microelectronics fabrication and the capability to drastically reduce decohering noise channels via chemical purification and isotopic enhancement. However, a variety of challenges in fabrication, control, and measurement leaves unclear the best strategy for fully realizing this material’s future potential. In this article, we survey three basic qubit types: those based on substitutional donors, on metal-oxide-semiconductor (MOS) structures, and on Si/SiGe heterostructures. We also discuss the multiple schema used to define and control Si qubits, which may exploit the manipulation and detection of a single electron charge, the state of a single electron spin, or the collective states of multiple spins. Far from being comprehensive, this article provides a brief orientation to the rapidly evolving field of silicon qubit technology and is intended as an approachable entry point for a researcher new to this field.

  14. Atomic-Monolayer MoS2 Band-to-Band Tunneling Field-Effect Transistor

    KAUST Repository

    Lan, Yann Wen

    2016-09-05

    The experimental observation of band-to-band tunneling in novel tunneling field-effect transistors utilizing a monolayer of MoS2 as the conducting channel is demonstrated. Our results indicate that the strong gate-coupling efficiency enabled by two-dimensional materials, such as monolayer MoS2, results in the direct manifestation of a band-to-band tunneling current and an ambipolar transport.

  15. Silicon-Based Quantum MOS Technology Development

    National Research Council Canada - National Science Library

    Seabaugh, Alan

    2000-01-01

    ...; peak-to-valley current ratio exceeding 2 was achieved at room temperature. The SiO2/Si/SiO2 RTD was studied extensively in a variety of forms, however no room temperature negative differential resistance was observed in the SiO2/Si/SiO2 system...

  16. Enhancement of the electrical characteristics of MOS capacitors by reducing the organic content of H2O-diluted Spin-On-Glass based oxides

    International Nuclear Information System (INIS)

    Molina, Joel; Munoz, Ana; Torres, Alfonso; Landa, Mauro; Alarcon, Pablo; Escobar, Manuel

    2011-01-01

    In this work, the physical, chemical and electrical properties of Metal-Oxide-Semiconductor (MOS) capacitors with Spin-On-Glass (SOG)-based thin films as gate dielectric have been investigated. Experiments of SOG diluted with two different solvents (2-propanol and deionized water) were done in order to reduce the viscosity of the SOG solution so that thinner films (down to ∼20 nm) could be obtained and their general characteristics compared. Thin films of SOG were deposited on silicon by the sol-gel technique and they were thermally annealed using conventional oxidation furnace and Rapid Thermal Processing (RTP) systems within N 2 ambient after deposition. SOG dilution using non-organic solvents like deionized water and further annealing (at relatively high temperatures ≥450 deg. C) are important processes intended to reduce the organic content of the films. Fourier-Transform Infrared (FTIR) Spectroscopy results have shown that water-diluted SOG films have a significant reduction in their organic content after increasing annealing temperature and/or dilution percentage when compared to those of undiluted SOG films. Both current-voltage (I-V) and capacitance-voltage (C-V) measurements show better electrical characteristics for SOG-films diluted in deionized water compared to those diluted in 2-propanol (which is an organic solvent). The electrical characteristics of H 2 O-diluted SOG thin films are very similar to those obtained from high quality thermal oxides so that their application as gate dielectrics in MOS devices is promising. Finally, it has been demonstrated that by reducing the organic content of SOG-based thin films, it is possible to obtain MOS devices with better electrical properties.

  17. Micro-irradiation experiments in MOS transistors using synchrotron radiation

    International Nuclear Information System (INIS)

    Autran, J.L.; Masson, P.; Raynaud, C.; Freud, N.; Riekel, C.

    1999-01-01

    Spatially-resolved total-dose degradation has been performed in MOS transistors by focusing x-ray synchrotron radiation on the gate electrode with micrometer resolution. The influence of the resulting permanent degradation on device electrical properties has been analyzed using current-voltage and charge pumping measurements, in concert with optical characterization (hot-carrier luminescence) and one-dimensional device simulation. (authors)

  18. Réalisation et caractérisation de transistors MOS à base de nanofils verticaux en silicium

    OpenAIRE

    GUERFI , Youssouf

    2015-01-01

    In order to further downscaling of the MOS transistors, the semiconductor industry has anticipated the limitations of miniaturization by the introduction of new materials and new architectures. The advent of triple gate structures (FinFET) allowed mastering the short channel effects and further miniaturization efforts (14 nm technology node in 2014). The ultimate case to the electrostatic control of the gate on the channel is given by a gate completely surrounding the device channel. For this...

  19. A compact T-shaped nanodevice for charge sensing of a tunable double quantum dot in scalable silicon technology

    Energy Technology Data Exchange (ETDEWEB)

    Tagliaferri, M.L.V., E-mail: marco.tagliaferri@mdm.imm.cnr.it [Laboratorio MDM, CNR-IMM, Via C. Olivetti 2, 20864 Agrate Brianza (MB) (Italy); Dipartimento di Scienza dei Materiali, Università di Milano Bicocca, Via Cozzi 53, 20125 Milano (Italy); Crippa, A. [Laboratorio MDM, CNR-IMM, Via C. Olivetti 2, 20864 Agrate Brianza (MB) (Italy); Dipartimento di Scienza dei Materiali, Università di Milano Bicocca, Via Cozzi 53, 20125 Milano (Italy); De Michielis, M. [Laboratorio MDM, CNR-IMM, Via C. Olivetti 2, 20864 Agrate Brianza (MB) (Italy); Mazzeo, G.; Fanciulli, M. [Laboratorio MDM, CNR-IMM, Via C. Olivetti 2, 20864 Agrate Brianza (MB) (Italy); Dipartimento di Scienza dei Materiali, Università di Milano Bicocca, Via Cozzi 53, 20125 Milano (Italy); Prati, E. [Laboratorio MDM, CNR-IMM, Via C. Olivetti 2, 20864 Agrate Brianza (MB) (Italy); Istituto di Fotonica e Nanotecnologie, CNR, Piazza Leonardo da Vinci 32, 20133 Milano (Italy)

    2016-03-11

    We report on the fabrication and the characterization of a tunable complementary-metal oxide semiconductor (CMOS) system consisting of two quantum dots and a MOS single electron transistor (MOSSET) charge sensor. By exploiting a compact T-shaped design and few gates fabricated by electron beam lithography, the MOSSET senses the charge state of either a single or double quantum dot at 4.2 K. The CMOS compatible fabrication process, the simplified control over the number of quantum dots and the scalable geometry make such architecture exploitable for large scale fabrication of multiple spin-based qubits in circuital quantum information processing. - Highlights: • Charge sensing of tunable, by position and number, quantum dots is demonstrated. • A compact T-shaped design with five gates at a single metalization level is proposed. • The electrometer is a silicon-etched nanowire acting as a disorder tolerant MOSSET.

  20. Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

    Science.gov (United States)

    Zhang, Xian-Jun; Yang, Yin-Tang; Duan, Bao-Xing; Chai, Chang-Chun; Song, Kun; Chen, Bin

    2012-09-01

    Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET).

  1. Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

    International Nuclear Information System (INIS)

    Zhang Xian-Jun; Yang Yin-Tang; Duan Bao-Xing; Chai Chang-Chun; Song Kun; Chen Bin

    2012-01-01

    Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET)

  2. Effect of gamma-ray irradiation on the surface states of MOS tunnel junctions

    Science.gov (United States)

    Ma, T. P.; Barker, R. C.

    1974-01-01

    Gamma-ray irradiation with doses up to 8 megarad produces no significant change on either the C(V) or the G(V) characteristics of MOS tunnel junctions with intermediate oxide thicknesses (40-60 A), whereas the expected flat-band shift toward negative electrode voltages occurs in control thick oxide capacitors. A simple tunneling model would explain the results if the radiation-generated hole traps are assumed to lie below the valence band of the silicon. The experiments also suggest that the observed radiation-generated interface states in conventional MOS devices are not due to the radiation damage of the silicon surface.

  3. Silicon on insulator technology. Characteristics. Applications; Technologies silicium sur isolant. Caracteristiques. Exemples d'application

    Energy Technology Data Exchange (ETDEWEB)

    Suat, J. P.; Peccoud, L.; Le Goascoz, V.; Garcia, M.; Mackowiak, E.

    1975-01-31

    The advantages resulting from a SOS (Silicon-on-Sapphire) MOS technology are demonstrated. Experimental results giving the performance of C.MOS and depletion-enrichment P-channel technologies are presented, with an application of Silicon on insulator on development, that is to say a 1024 bits MNOS memory, peripheral circuits being developed according to the depletion-enrichment technology.

  4. Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric.

    Science.gov (United States)

    Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

    2017-01-13

    Two-dimensional layered semiconductors such as molybdenum disulfide (MoS 2 ) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS 2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS 2 and an ultra-thin HfO 2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS 2 -HfO 2 interface is responsible for the generation of interface states with a density (D it ) reaching ~7.03 × 10 11  cm -2  eV -1 . This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS 2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in D it could be achieved by thermally diffusing S atoms to the MoS 2 -HfO 2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS 2 devices with carrier transport enhancement.

  5. Effects on focused ion beam irradiation on MOS transistors

    International Nuclear Information System (INIS)

    Campbell, A.N.; Peterson, K.A.; Fleetwood, D.M.; Soden, J.M.

    1997-01-01

    The effects of irradiation from a focused ion beam (FIB) system on MOS transistors are reported systematically for the first time. Three MOS transistor technologies, with 0.5, 1, and 3 μm minimum feature sizes and with gate oxide thicknesses ranging from 11 to 50 nm, were analyzed. Significant shifts in transistor parameters (such as threshold voltage, transconductance, and mobility) were observed following irradiation with a 30 keV Ga + focused ion beam with ion doses varying by over 5 orders of magnitude. The apparent damage mechanism (which involved the creation of interface traps, oxide trapped charge, or both) and extent of damage were different for each of the three technologies investigated

  6. Protection of MOS capacitors during anodic bonding

    Science.gov (United States)

    Schjølberg-Henriksen, K.; Plaza, J. A.; Rafí, J. M.; Esteve, J.; Campabadal, F.; Santander, J.; Jensen, G. U.; Hanneborg, A.

    2002-07-01

    We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm-1 to 4 × 104 V cm-1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

  7. A complementary MOS process

    International Nuclear Information System (INIS)

    Jhabvala, M.D.

    1977-03-01

    The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included

  8. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  9. Single-layer MoS2 electronics.

    Science.gov (United States)

    Lembke, Dominik; Bertolazzi, Simone; Kis, Andras

    2015-01-20

    CONSPECTUS: Atomic crystals of two-dimensional materials consisting of single sheets extracted from layered materials are gaining increasing attention. The most well-known material from this group is graphene, a single layer of graphite that can be extracted from the bulk material or grown on a suitable substrate. Its discovery has given rise to intense research effort culminating in the 2010 Nobel Prize in physics awarded to Andre Geim and Konstantin Novoselov. Graphene however represents only the proverbial tip of the iceberg, and increasing attention of researchers is now turning towards the veritable zoo of so-called "other 2D materials". They have properties complementary to graphene, which in its pristine form lacks a bandgap: MoS2, for example, is a semiconductor, while NbSe2 is a superconductor. They could hold the key to important practical applications and new scientific discoveries in the two-dimensional limit. This family of materials has been studied since the 1960s, but most of the research focused on their tribological applications: MoS2 is best known today as a high-performance dry lubricant for ultrahigh-vacuum applications and in car engines. The realization that single layers of MoS2 and related materials could also be used in functional electronic devices where they could offer advantages compared with silicon or graphene created a renewed interest in these materials. MoS2 is currently gaining the most attention because the material is easily available in the form of a mineral, molybdenite, but other 2D transition metal dichalcogenide (TMD) semiconductors are expected to have qualitatively similar properties. In this Account, we describe recent progress in the area of single-layer MoS2-based devices for electronic circuits. We will start with MoS2 transistors, which showed for the first time that devices based on MoS2 and related TMDs could have electrical properties on the same level as other, more established semiconducting materials. This

  10. Photon wavelength dependent valley photocurrent in multilayer MoS2

    Science.gov (United States)

    Guan, Hongming; Tang, Ning; Xu, Xiaolong; Shang, LiangLiang; Huang, Wei; Fu, Lei; Fang, Xianfa; Yu, Jiachen; Zhang, Caifeng; Zhang, Xiaoyue; Dai, Lun; Chen, Yonghai; Ge, Weikun; Shen, Bo

    2017-12-01

    The degree of freedom (DOF) of the K (K') valley in transition-metal dichalcogenides, especially molybdenum disulfide (MoS2), offers an opportunity for next-generation valleytronics devices. In this work, the K (K') valley DOF of multilayer MoS2 is studied by means of the photon wavelength dependent circular photogalvanic effect (CPGE) at room temperature upon a strong external out-of-plane electric field induced by an ionic liquid (IL) gate, which breaks the spatial-inversion symmetry. It is demonstrated that only on resonant excitations in the K (K') valley can the valley-related CPGE signals in multilayer MoS2 with an IL gate be detected, indicating that the valley contrast is indeed regenerated between the K and K' valleys when the electric field is applied. As expected, it can also be seen that the K (K') valley DOF in multilayer MoS2 can be modulated by the external electric field. The observation of photon wavelength dependent valley photocurrent in multilayer MoS2, with the help of better Ohmic contacts, may pave a way for optoelectronic applications of valleytronics in the future.

  11. The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

    International Nuclear Information System (INIS)

    Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

    2006-01-01

    This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits

  12. Measurement of MOS current mismatch in the weak inversion region

    International Nuclear Information System (INIS)

    Forti, F.; Wright, M.E.

    1994-01-01

    The MOS transistor matching properties in the weak inversion region have not received, in the past, the attention that the mismatch in the strong inversion region has. The importance of weak inversion biased transistors in low power CMOS analog systems calls for more extensive data on the mismatch in this region of operation. The study presented in this paper was motivated by the need of controlling the threshold matching in a low power, low noise amplifier discriminator circuit used in a silicon radiation detector read-out, where both the transistor dimensions and the currents had to be kept to a minimum. The authors have measured the current matching properties of MOS transistors operated in the weak inversion region. They measured a total of about 1,400 PMOS and NMOS transistors produced in four different processes and report here the results in terms of mismatch dependence on current density, device dimensions, and substrate voltage, without using any specific model for the transistor

  13. Linear gate

    International Nuclear Information System (INIS)

    Suwono.

    1978-01-01

    A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)

  14. Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

    Science.gov (United States)

    Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

    2018-02-01

    In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

  15. The effect of gate length on SOI-MOSFETS operation | Baedi ...

    African Journals Online (AJOL)

    The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

  16. Dosimetric properties of MOS transistors

    International Nuclear Information System (INIS)

    Frank, H.; Petr, I.

    1977-01-01

    The structure of MOS transistors is described and their characteristics given. The experiments performed and data in the literature show the following dosimetric properties of MOS transistors: while for low gamma doses the transistor response to exposure is linear, it shows saturation for higher doses (exceeding 10 3 Gy in tissue). The response is independent of the energy of radiation and of the dose rate (within 10 -2 to 10 5 Gy/s). The spontaneous reduction with time of the spatial charge captured by the oxide layer (fading) is small and acceptable from the point of view of dosimetry. Curves are given of isochronous annealing of the transistors following irradiation with 137 Cs and 18 MeV electrons for different voltages during irradiation. The curves show that in MOS transistors irradiated with high-energy electrons the effect of annealing is less than in transistors irradiated with 137 Cs. In view of the requirement of using higher temperatures (approx. 400 degC) for the complete ''erasing'' of the captured charge, unsealed systems must be used for dosimetric purposes. The effect was also studied of neutron radiation, proton radiation and electron radiation on the MOS transistor structure. For MOS transistor irradiation with 14 MeV neutrons from a neutron generator the response was 4% of that for gamma radiation at the same dose equivalent. The effect of proton radiation was studied as related to the changes in MOS transistor structure during space flights. The response curve shapes are similar to those of gamma radiation curves. The effect of electron radiation on the MOS structure was studied by many authors. The experiments show that for each thickness of the SiO 2 layer an electron energy exists at which the size of the charge captured in SiO 2 is the greatest. All data show that MOS transistors are promising for radiation dosimetry. The main advantage of MOS transistors as gamma dosemeters is the ease and speed of evaluation, low sensitivity to neutron

  17. Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

    International Nuclear Information System (INIS)

    Ni Henan; Wu Liangcai; Song Zhitang; Hui Chun

    2009-01-01

    An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO 2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time. (semiconductor devices)

  18. Modifications of Fowler-Nordheim injection characteristics in γ irradiated MOS devices

    International Nuclear Information System (INIS)

    Scarpa, A.; Paccagnella, A.; Montera, F.; Candelori, A.; Ghidini, G.; Fuochi, P.G.

    1998-01-01

    In this work the authors have investigated how gamma irradiation affects the tunneling conduction mechanism of a 20 nm thick oxide in MOS capacitors. The radiation induced positive charge is rapidly compensated by the injected electrons, and does not impact the gate current under positive injection after the first current-voltage measurement. Only a transient stress induced leakage current at low gate bias is observed. Instead, a radiation induced negative charge has been observed near the polysilicon gate, which enhances the gate voltage needed for Fowler-Nordheim conduction at negative gate bias. No time decay of this charge has been observed. Such charges slightly modify the trapping kinetics of negative charge during subsequent electrical stresses performed at constant current condition

  19. Analogue Building Blocks Based on Digital CMOS Gates

    DEFF Research Database (Denmark)

    Mucha, Igor

    1996-01-01

    Low-performance analogue circuits built of digital MOS gates are presented. Depending on the threshold voltages of the technology used the final circuits can be operated using low supply voltages. The main advantage using the proposed circuits is the simplicity and ultimate compatibility...... with the design of digital circuits....

  20. Improving the Stability of High-Performance Multilayer MoS2 Field-Effect Transistors.

    Science.gov (United States)

    Liu, Na; Baek, Jongyeol; Kim, Seung Min; Hong, Seongin; Hong, Young Ki; Kim, Yang Soo; Kim, Hyun-Suk; Kim, Sunkook; Park, Jozeph

    2017-12-13

    In this study, we propose a method for improving the stability of multilayer MoS 2 field-effect transistors (FETs) by O 2 plasma treatment and Al 2 O 3 passivation while sustaining the high performance of bulk MoS 2 FET. The MoS 2 FETs were exposed to O 2 plasma for 30 s before Al 2 O 3 encapsulation to achieve a relatively small hysteresis and high electrical performance. A MoO x layer formed during the plasma treatment was found between MoS 2 and the top passivation layer. The MoO x interlayer prevents the generation of excess electron carriers in the channel, owing to Al 2 O 3 passivation, thereby minimizing the shift in the threshold voltage (V th ) and increase of the off-current leakage. However, prolonged exposure of the MoS 2 surface to O 2 plasma (90 and 120 s) was found to introduce excess oxygen into the MoO x interlayer, leading to more pronounced hysteresis and a high off-current. The stable MoS 2 FETs were also subjected to gate-bias stress tests under different conditions. The MoS 2 transistors exhibited negligible decline in performance under positive bias stress, positive bias illumination stress, and negative bias stress, but large negative shifts in V th were observed under negative bias illumination stress, which is attributed to the presence of sulfur vacancies. This simple approach can be applied to other transition metal dichalcogenide materials to understand their FET properties and reliability, and the resulting high-performance hysteresis-free MoS 2 transistors are expected to open up new opportunities for the development of sophisticated electronic applications.

  1. Tunable Electrical and Optical Characteristics in Monolayer Graphene and Few-Layer MoS2 Heterostructure Devices.

    Science.gov (United States)

    Rathi, Servin; Lee, Inyeal; Lim, Dongsuk; Wang, Jianwei; Ochiai, Yuichi; Aoki, Nobuyuki; Watanabe, Kenji; Taniguchi, Takashi; Lee, Gwan-Hyoung; Yu, Young-Jun; Kim, Philip; Kim, Gil-Ho

    2015-08-12

    Lateral and vertical two-dimensional heterostructure devices, in particular graphene-MoS2, have attracted profound interest as they offer additional functionalities over normal two-dimensional devices. Here, we have carried out electrical and optical characterization of graphene-MoS2 heterostructure. The few-layer MoS2 devices with metal electrode at one end and monolayer graphene electrode at the other end show nonlinearity in drain current with drain voltage sweep due to asymmetrical Schottky barrier height at the contacts and can be modulated with an external gate field. The doping effect of MoS2 on graphene was observed as double Dirac points in the transfer characteristics of the graphene field-effect transistor (FET) with a few-layer MoS2 overlapping the middle part of the channel, whereas the underlapping of graphene have negligible effect on MoS2 FET characteristics, which showed typical n-type behavior. The heterostructure also exhibits a strongest optical response for 520 nm wavelength, which decreases with higher wavelengths. Another distinct feature observed in the heterostructure is the peak in the photocurrent around zero gate voltage. This peak is distinguished from conventional MoS2 FETs, which show a continuous increase in photocurrent with back-gate voltage. These results offer significant insight and further enhance the understanding of the graphene-MoS2 heterostructure.

  2. Radiation damage of silicon structures with electrons of 900 MeV

    CERN Document Server

    Rachevskaia, I; Bosisio, L; Dittongo, S; Quai, E; Rizzo, G

    2002-01-01

    We present first results on the irradiation of double-sided silicon microstrip detectors and test structures performed at the Elettra synchrotron radiation facility at Trieste, Italy. The devices were irradiated with 900 MeV electrons. The test structures we used for studying bulk, surface and oxide irradiation damage were guard ring diodes, gated diodes and MOS capacitors. The test structures and the double-sided microstrip detectors were produced by Micron Semiconductor Ltd. (England) and IRST (Trento, Italy). For the first time, bulk-type inversion is observed to occur after high-energy electron irradiation. Current and inter-strip resistance measurements performed on the microstrip detectors show that the devices are still usable after type inversion.

  3. Strained Si/SiGe MOS transistor model

    Directory of Open Access Journals (Sweden)

    Tatjana Pešić-Brđanin

    2009-06-01

    Full Text Available In this paper we describe a new model of surfacechannel strained-Si/SiGe MOSFET based on the extension of non-quasi-static (NQS circuit model previously derived for bulk-Si devices. Basic equations of the NQS model have been modified to account for the new physical parameters of strained-Si and relaxed-SiGe layers. From the comparisons with measurements, it is shown that a modified NQS MOS including steady-state self heating can accurately predict DC characteristics of Strained Silicon MOSFETs.

  4. Reevaluating the worst-case radiation response of MOS transistors

    Science.gov (United States)

    Fleetwood, D. M.

    Predicting worst-case response of a semiconductor device to ionizing radiation is a formidable challenge. As processes change and MOS gate insulators become thinner in advanced VLSI and VHSIC technologies, failure mechanisms must be constantly re-examined. Results are presented of a recent study in which more than 100 MOS transistors were monitored for up to 300 days after Co-60 exposure. Based on these results, a reevaluation of worst-case n-channel transistor response (most positive threshold voltage shift) in low-dose-rate and postirradiation environments is required in many cases. It is shown for Sandia hardened n-channel transistors with a 32 nm gate oxide, that switching from zero-volt bias, held during the entire radiation period, to positive bias during anneal clearly leads to a more positive threshold voltage shift (and thus the slowest circuit response) after Co-60 exposure than the standard case of maintaining positive bias during irradiation and anneal. It is concluded that irradiating these kinds of transistors with zero-volt bias, and annealing with positive bias, leads to worst-case postirradiation response. For commercial devices (with few interface states at doses of interest), on the other hand, device response only improves postirradiation, and worst-case response (in terms of device leakage) is for devices irradiated under positive bias and annealed with zero-volts bias.

  5. Simplified tunnelling current calculation for MOS structures with ultra-thin oxides for conductive atomic force microscopy investigations

    International Nuclear Information System (INIS)

    Frammelsberger, Werner; Benstetter, Guenther; Stamp, Richard; Kiely, Janice; Schweinboeck, Thomas

    2005-01-01

    As charge tunnelling through thin and ultra-thin silicon dioxide layers is regarded as the driving force for MOS device degradation the determination and characterisation of electrically week spots is of paramount importance for device reliability and failure analysis. Conductive atomic force microscopy (C-AFM) is able to address this issue with a spatial resolution smaller than the expected breakdown spot. For the determination of the electrically active oxide thickness in practice an easy to use model with sufficient accuracy and which is largely independent of the oxide thickness is required. In this work a simplified method is presented that meets these demands. The electrically active oxide thickness is determined by matching of C-AFM voltage-current curves and a tunnelling current model, which is based on an analytical tunnelling current approximation. The model holds for both the Fowler-Nordheim tunnelling and the direct tunnelling regime with one single tunnelling parameter set. The results show good agreement with macroscopic measurements for gate voltages larger than approximately 0.5-1 V, and with microscopic C-AFM measurements. For this reason arbitrary oxides in the DT and the FNT regime may be analysed with high lateral resolution by C-AFM, without the need of a preselection of the tunnelling regime to be addressed

  6. Ionizing radiation M.O.S. dosimeters: sensibility and stability

    International Nuclear Information System (INIS)

    Gessinn, F.

    1993-12-01

    This thesis is a contribution to the study of the ionizing radiation responsivity of P.O.M.S. dosimeters. Unlike the development of processing hardening techniques, our works goal were to increase, on the one hand, the M.O.S. dosimeters sensitivity in order to detect small radiation doses and on the other hand, the stability with time and temperature of the devices, to minimize the absorbed-dose estimation errors. With this aim in mind, an analysis of all processing parameters has been carried out: the M.O.S. dosimeter sensitivity is primarily controlled by the gate oxide thickness and the irradiation electric field. Thus, P.M.O.S. transistors with 1 and 2 μm thick silica layers have been fabricated for our experiments. The radiation response of our devices in the high-field mode satisfactorily fits a D ox 2 power law. The maximum sensitivity achieved (9,2 V/Gy for 2μm devices) is close to the ideal value obtained when considering only an unitary carrier-trapping level, and allows to measure about 10 -2 Gy radiation doses. Read-time stability has been evaluated under bias-temperature stress conditions: experiments underscore slow fading, corresponding to 10 -3 Gy/h. The temperature response has also been studied: the analytical model we have developed predicts M.O.S. transistors threshold voltage variations over the military specifications range [-50 deg. C, + 150 deg. C]. Finally, we have investigated the possibilities of irradiated dosimeters thermal annealing for reusing. It appears clearly that radiation-induced damage annealing is strongly gate bias dependent. Furthermore, dosimeters radiation sensitivity seems not to be affected by successive annealings. (author). 146 refs., 58 figs., 9 tabs

  7. BATMAN: MOS Spectroscopy on Demand

    Science.gov (United States)

    Molinari, E.; Zamkotsian, F.; Moschetti, M.; Spano, P.; Boschin, W.; Cosentino, R.; Ghedina, A.; González, M.; Pérez, H.; Lanzoni, P.; Ramarijaona, H.; Riva, M.; Zerbi, F.; Nicastro, L.; Valenziano, L.; Di Marcantonio, P.; Coretti, I.; Cirami, R.

    2016-10-01

    Multi-Object Spectrographs (MOS) are the major instruments for studying primary galaxies and remote and faint objects. Current object selection systems are limited and/or difficult to implement in next generation MOS for space and ground-based telescopes. A promising solution is the use of MOEMS devices such as micromirror arrays, which allow the remote control of the multi-slit configuration in real time. TNG is hosting a novelty project for real-time, on-demand MOS masks based on MOEMS programmable slits. We are developing a 2048×1080 Digital-Micromirror-Device-based (DMD) MOS instrument to be mounted on the Galileo telescope, called BATMAN. It is a two-arm instrument designed for providing in parallel imaging and spectroscopic capabilities. With a field of view of 6.8×3.6 arcmin and a plate scale of 0.2 arcsec per micromirror, this astronomical setup can be used to investigate the formation and evolution of galaxies. The wavelength range is in the visible and the spectral resolution is R=560 for a 1 arcsec object, and the two arms will have 2k × 4k CCD detectors. ROBIN, a BATMAN demonstrator, has been designed, realized and integrated. We plan to have BATMAN first light by mid-2016.

  8. The OverMOS project

    Energy Technology Data Exchange (ETDEWEB)

    Das, D.; Dopke, J., E-mail: jens.dopke@stfc.ac.uk; McMahon, S.J.; Turchetta, R.; Villani, G.; Wilson, F.; Worm, S.

    2016-07-11

    The OverMOS project aims to create a fast radiation hard tracking detector sensor, based on High Resistivity CMOS technology. In a first prototype submission, different pixel and charge collection node geometries have been produced, which have lately been returned from fabrication and are currently under test.

  9. Electrical performance of multilayer MoS2 transistors on high-κ Al2O3 coated Si substrates

    Directory of Open Access Journals (Sweden)

    Tao Li

    2015-05-01

    Full Text Available The electrical performance of MoS2 can be engineered by introducing high-κ dielectrics, while the interactions between high-κ dielectrics and MoS2 need to be studied. In this study, multilayer MoS2 field-effect transistors (FETs with a back-gated configuration were fabricated on high-κ Al2O3 coated Si substrates. Compared with MoS2 FETs on SiO2, the field-effect mobility (μFE and subthreshold swing (SS were remarkably improved in MoS2/Al2O3/Si. The improved μFE was thought to result from the dielectric screening effect from high-κ Al2O3. When a HfO2 passivation layer was introduced on the top of MoS2/Al2O3/Si, the field-effect mobility was further enhanced, which was thought to be concerned with the decreased contact resistance between the metal and MoS2. Meanwhile, the interface trap density increased from 2.4×1012 eV−1cm−2 to 6.3×1012 eV−1cm−2. The increase of the off-state current and the negative shift of the threshold voltage may be related to the increase of interface traps.

  10. A high performance gate drive for large gate turn off thyristors

    Energy Technology Data Exchange (ETDEWEB)

    Szilagyi, C.P.

    1993-01-01

    Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

  11. Silicon carbide: A unique platform for metal-oxide-semiconductor physics

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Gang [Institute for Advanced Materials, Devices and Nanotechnology, Rutgers University, Piscataway, New Jersey 08854 (United States); Tuttle, Blair R. [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Dhar, Sarit [Department of Physics, Auburn University, Auburn, Alabama 36849 (United States)

    2015-06-15

    A sustainable energy future requires power electronics that can enable significantly higher efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide (4H-SiC) is one of the most technologically advanced wide bandgap semiconductor that can outperform conventional silicon in terms of power handling, maximum operating temperature, and power conversion efficiency in power modules. While SiC Schottky diode is a mature technology, SiC power Metal Oxide Semiconductor Field Effect Transistors are relatively novel and there is large room for performance improvement. Specifically, major initiatives are under way to improve the inversion channel mobility and gate oxide stability in order to further reduce the on-resistance and enhance the gate reliability. Both problems relate to the defects near the SiO{sub 2}/SiC interface, which have been the focus of intensive studies for more than a decade. Here we review research on the SiC MOS physics and technology, including its brief history, the state-of-art, and the latest progress in this field. We focus on the two main scientific problems, namely, low channel mobility and bias temperature instability. The possible mechanisms behind these issues are discussed at the device physics level as well as the atomic scale, with the support of published physical analysis and theoretical studies results. Some of the most exciting recent progress in interface engineering for improving the channel mobility and fundamental understanding of channel transport is reviewed.

  12. Effect of Dielectric Interface on the Performance of MoS2 Transistors.

    Science.gov (United States)

    Li, Xuefei; Xiong, Xiong; Li, Tiaoyang; Li, Sichao; Zhang, Zhenfeng; Wu, Yanqing

    2017-12-27

    Because of their wide bandgap and ultrathin body properties, two-dimensional materials are currently being pursued for next-generation electronic and optoelectronic applications. Although there have been increasing numbers of studies on improving the performance of MoS 2 field-effect transistors (FETs) using various methods, the dielectric interface, which plays a decisive role in determining the mobility, interface traps, and thermal transport of MoS 2 FETs, has not been well explored and understood. In this article, we present a comprehensive experimental study on the effect of high-k dielectrics on the performance of few-layer MoS 2 FETs from 300 to 4.3 K. Results show that Al 2 O 3 /HfO 2 could boost the mobility and drain current. Meanwhile, MoS 2 transistors with Al 2 O 3 /HfO 2 demonstrate a 2× reduction in oxide trap density compared to that of the devices with the conventional SiO 2 substrate. Also, we observe a negative differential resistance effect on the device with 1 μm-channel length when using conventional SiO 2 as the gate dielectric due to self-heating, and this is effectively eliminated by using the Al 2 O 3 /HfO 2 gate dielectric. This dielectric engineering provides a highly viable route to realizing high-performance transition metal dichalcogenide-based FETs.

  13. 2D MoS2 Neuromorphic Devices for Brain-Like Computational Systems.

    Science.gov (United States)

    Jiang, Jie; Guo, Junjie; Wan, Xiang; Yang, Yi; Xie, Haipeng; Niu, Dongmei; Yang, Junliang; He, Jun; Gao, Yongli; Wan, Qing

    2017-08-01

    Hardware implementation of artificial synapses/neurons with 2D solid-state devices is of great significance for nanoscale brain-like computational systems. Here, 2D MoS 2 synaptic/neuronal transistors are fabricated by using poly(vinyl alcohol) as the laterally coupled, proton-conducting electrolytes. Fundamental synaptic functions, such as an excitatory postsynaptic current, paired-pulse facilitation, and a dynamic filter for information transmission of biological synapse, are successfully emulated. Most importantly, with multiple input gates and one modulatory gate, spiking-dependent logic operation/modulation, multiplicative neural coding, and neuronal gain modulation are also experimentally demonstrated. The results indicate that the intriguing 2D MoS 2 transistors are also very promising for the next-generation of nanoscale neuromorphic device applications. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  14. Enhancing Photoresponsivity of Self-Aligned MoS2 Field-Effect Transistors by Piezo-Phototronic Effect from GaN Nanowires.

    Science.gov (United States)

    Liu, Xingqiang; Yang, Xiaonian; Gao, Guoyun; Yang, Zhenyu; Liu, Haitao; Li, Qiang; Lou, Zheng; Shen, Guozhen; Liao, Lei; Pan, Caofeng; Lin Wang, Zhong

    2016-08-23

    We report high-performance self-aligned MoS2 field-effect transistors (FETs) with enhanced photoresponsivity by the piezo-phototronic effect. The FETs are fabricated based on monolayer MoS2 with a piezoelectric GaN nanowire (NW) as the local gate, and a self-aligned process is employed to define the source/drain electrodes. The fabrication method allows the preservation of the intrinsic property of MoS2 and suppresses the scattering center density in the MoS2/GaN interface, which results in high electrical and photoelectric performances. MoS2 FETs with channel lengths of ∼200 nm have been fabricated with a small subthreshold slope of 64 mV/dec. The photoresponsivity is 443.3 A·W(-1), with a fast response and recovery time of ∼5 ms under 550 nm light illumination. When strain is introduced into the GaN NW, the photoresponsivity is further enhanced to 734.5 A·W(-1) and maintains consistent response and recovery time, which is comparable with that of the mechanical exfoliation of MoS2 transistors. The approach presented here opens an avenue to high-performance top-gated piezo-enhanced MoS2 photodetectors.

  15. Probing low noise at the MOS interface with a spin-orbit qubit.

    Energy Technology Data Exchange (ETDEWEB)

    Jock, Ryan Michael; Jacobson, Noah Tobias; Harvey-Collard, Patrick; Mounce, Andrew; Srinivasa, Vanita; Ward, Daniel Robert; Anderson, John Moses; Manginell, Ronald P.; Wendt, Joel R.; Rudolph, Martin; Pluym, Tammy; Gamble, John King,; Baczewski, Andrew David; Witzel, Wayne; Carroll, Malcolm S.

    2017-07-01

    The silicon metal-oxide-semiconductor (MOS) material system is technologically important for the implementation of electron spin-based quantum information technologies. Researchers predict the need for an integrated platform in order to implement useful computation, and decades of advancements in silicon microelectronics fabrication lends itself to this challenge. However, fundamental concerns have been raised about the MOS interface (e.g. trap noise, variations in electron g-factor and practical implementation of multi-QDs). Furthermore, two-axis control of silicon qubits has, to date, required the integration of non-ideal components (e.g. microwave strip-lines, micro-magnets, triple quantum dots, or introduction of donor atoms). In this paper, we introduce a spin-orbit (SO) driven singlet- triplet (ST) qubit in silicon, demonstrating all-electrical two-axis control that requires no additional integrated elements and exhibits charge noise properties equivalent to other more model, but less commercially mature, semiconductor systems. We demonstrate the ability to tune an intrinsic spin-orbit interface effect, which is consistent with Rashba and Dresselhaus contributions that are remarkably strong for a low spin-orbit material such as silicon. The qubit maintains the advantages of using isotopically enriched silicon for producing a quiet magnetic environment, measuring spin dephasing times of 1.6 μs using 99.95% 28Si epitaxy for the qubit, comparable to results from other isotopically enhanced silicon ST qubit systems. This work, therefore, demonstrates that the interface inherently provides properties for two-axis control, and the technologically important MOS interface does not add additional detrimental qubit noise. isotopically enhanced silicon ST qubit systems

  16. Field-effect piezoresistors for vibration detection of nanobeams by using monolithically integrated MOS capacitors

    International Nuclear Information System (INIS)

    Cheng, Haitao; Yang, Heng; Li, XinXin; Wang, Yuelin

    2013-01-01

    A novel piezoresistive sensing method is presented herein for the detection of nanobeam resonator based on a monolithically integrated MOS (metal–oxide–semiconductor) capacitor structure. The bottom layer of the nanobeam located beneath the MOS capacitor is utilized as a piezoresistor for the detection of internal stress resulting from nanobeam deformation, and therefore the challenging process of ultra-shallow junction doping is avoided. When a bias voltage applied on the MOS gate exceeds the threshold, the depletion layer width is built up to the maximum, and the piezoresistive cancellation effect beside the neutral plane is eliminated. Based on a conventional microelectromechanical (MEMS) process, an MOS capacitor is fabricated at the terminal of a double-clamped nanobeam with dimensions of 46 µm × 7 µm × 149 nm. The measured R–V curve of this MOS structure presents a 64.7 nm thick piezoresistor which closely agrees with the design. This double-clamped nanobeam is excited into mechanical resonance by mounting it on a piezoelectric ceramic, and the amplitude–frequency response is measured by a network analyzer. The measured resonant frequency is 3.97 MHz and the quality (Q)-factor is 82 in atmosphere environment. Besides, this piezoresistive sensing method is verified by a laser-Doppler vibrometry. (paper)

  17. Dosimetric properties of MOS transistors

    International Nuclear Information System (INIS)

    Peter, I.; Frank, G.

    1977-01-01

    The performance of MOS transistors as gamma detectors has been tested. The dosimeter sensitivity has proved to be independent on the doses ranging from 10 3 to 10 6 R, and gamma energy of 137 Cs, 60 Co - sources and 5 - 18 MeV electrons. Fading of the space charge trapped by the SiO 2 layer of the transistor has appeared to be neglegible at room temperature after 400 hrs. The isochronous annealing in the temperature range of 40-260 deg C had a more substantial effect on the space charge of the transistor irradiated with 18 MeV electrons than on the 137 Cs gamma-irradiated transistors. This proved a repeated use of γ-dosemeters. MOS transistors are concluded to be promising for gamma dosimetry [ru

  18. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  19. MOS modeling hierarchy including radiation effects

    International Nuclear Information System (INIS)

    Alexander, D.R.; Turfler, R.M.

    1975-01-01

    A hierarchy of modeling procedures has been developed for MOS transistors, circuit blocks, and integrated circuits which include the effects of total dose radiation and photocurrent response. The models were developed for use with the SCEPTRE circuit analysis program, but the techniques are suitable for other modern computer aided analysis programs. The modeling hierarchy permits the designer or analyst to select the level of modeling complexity consistent with circuit size, parametric information, and accuracy requirements. Improvements have been made in the implementation of important second order effects in the transistor MOS model, in the definition of MOS building block models, and in the development of composite terminal models for MOS integrated circuits

  20. 18O isotopic tracer studies of silicon oxidation in dry oxygen

    International Nuclear Information System (INIS)

    Han, C.J.

    1986-01-01

    Oxidation of silicon in dry oxygen has been an important process in the integrated circuit industry for making gate insulators on metal-oxide-semiconductory (MOS) devices. This work examines this process using isotopic tracers of oxygen to determine the transport mechanisms of oxygen through silicon dioxide. Oxides were grown sequentially using mass-16 and mass-18 oxygen gas sources to label the oxygen molecules from each step. The resulting oxides are analyzed using secondary ion mass spectrometry (SIMS). The results of these analyses suggest two oxidant species are present during the oxidation, each diffuses and oxidizes separately during the process. A model from this finding using a sum of two linear-parabolic growth rates, each representing the growth rate from one of the oxidants, describes the reported oxidation kinetics in the literature closely. A fit of this relationship reveals excellent fits to the data for oxide thicknesses ranging from 30 A to 1 μm and for temperatures ranging from 800 to 1200 0 C. The mass-18 oxygen tracers also enable a direct observation of the oxygen solubility in the silicon dioxide during a dry oxidation process. The SIMS profiles establish a maximum solubility for interstitial oxygen at 1000 0 C at 2 x 10 20 cm -3 . Furthermore, the mass-18 oxygen profiles show negligible network diffusion during an 1000 0 C oxidation

  1. Modification of the optoelectronic properties of two-dimensional MoS2 crystals by ultraviolet-ozone treatment

    Science.gov (United States)

    Yang, Hae In; Park, Seonyoung; Choi, Woong

    2018-06-01

    We report the modification of the optoelectronic properties of mechanically-exfoliated single layer MoS2 by ultraviolet-ozone exposure. Photoluminescence emission of pristine MoS2 monotonically decreased and eventually quenched as ultraviolet-ozone exposure time increased from 0 to 10 min. The reduction of photoluminescence emission accompanied reduction of Raman modes, suggesting structural degradation in ultraviolet-ozone exposed MoS2. Analysis with X-ray photoelectron spectroscopy revealed that the formation of Ssbnd O and Mosbnd O bonding increases with ultraviolet-ozone exposure time. Measurement of electrical transport properties of MoS2 in a bottom-gate thin-film transistor configuration suggested the presence of insulating MoO3 after ultraviolet-ozone exposure. These results demonstrate that ultraviolet-ozone exposure can significantly influence the optoelectronic properties of single layer MoS2, providing important implications on the application of MoS2 and other two-dimensional materials into optoelectronic devices.

  2. Radiation Effects on the Electrical Properties of MOS Device Materials.

    Science.gov (United States)

    1978-02-01

    distance to be collected at the gate so the current is essentially due to holes traversing the oxide to be collected at the silicon cathode . 3.2.2 Dose...CA 94025 San Bernardino, CA 92402 Attn : M.L. Aite l NCA 1-3236 Attn: P.J. Dolan Attn : E.W. Allen 520/141 Science Application s, Inc Stanford Research

  3. Simulation of atomistic processes during silicon oxidation

    OpenAIRE

    Bongiorno, Angelo

    2003-01-01

    Silicon dioxide (SiO2) films grown on silicon monocrystal (Si) substrates form the gate oxides in current Si-based microelectronics devices. The understanding at the atomic scale of both the silicon oxidation process and the properties of the Si(100)-SiO2 interface is of significant importance in state-of-the-art silicon microelectronics manufacturing. These two topics are intimately coupled and are both addressed in this theoretical investigation mainly through first-principles calculations....

  4. Efficient simulation of power MOS transistors

    NARCIS (Netherlands)

    Ugryumova, M.; Schilders, W.H.A.

    2011-01-01

    In this report we present a few industrial problems related to modeling of MOS transistors. We suggest an efficient algorithm for computing output current at the top ports of power MOS transistors for given voltage excitations. The suggested algorithm exploits the connection between the resistor and

  5. A self-aligned gate definition process with submicron gaps

    NARCIS (Netherlands)

    Warmerdam, L.F.P.; Aarnink, Antonius A.I.; Holleman, J.; Wallinga, Hans

    1989-01-01

    A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are

  6. Evolution of electronic structure in highly charge doped MoS2 compounds

    Science.gov (United States)

    Bin Subhan, Mohammed; Watson, Matthew; Liu, Zhongkai; Walters, Andrew; Hoesch, Moritz; Howard, Chris; Diamond I05 beamline Collaboration

    Transition-metal dichalcogenides (TMDCs) are a group of layered materials that exhibit a rich array of electronic ground states including semiconductivity, metallicity, superconductivity and charge density waves. In recent years, 2D TMDCs have attracted considerable attention due to their unique properties and potential applications in optoelectronics. It has been shown that the charge carrier density in few layer MoS2 can be tunably increased via electrostatic gating. At high levels of doping, MoS2 exhibits superconductivity with a dome-like dependence of Tc on doping analogous to that found in the cuprate superconductors. High doping can also be achieved via intercalation of alkali metals in bulk MoS2. The origin of this superconductivity is not yet fully understood with predictions ranging from exotic pairing mechanisms in bulk systems to Ising superconductivity in single layers. Despite these interesting properties, there has been limited research to date on the electronic structure of these doped compounds. Here we present our work on alkali metal intercalated MoS2 using the low temperature metal ammonia solution method. Using X-ray diffraction, Raman spectroscopy and ARPES measurements we will discuss the physical and electronic structure of these materials. EPSRC, Diamond Light Source.

  7. Stacking stability of MoS2 bilayer: An ab initio study

    International Nuclear Information System (INIS)

    Tao Peng; Guo Huai-Hong; Yang Teng; Zhang Zhi-Dong

    2014-01-01

    The study of the stacking stability of bilayer MoS 2 is essential since a bilayer has exhibited advantages over single layer MoS 2 in many aspects for nanoelectronic applications. We explored the relative stability, optimal sliding path between different stacking orders of bilayer MoS 2 , and (especially) the effect of inter-layer stress, by combining first-principles density functional total energy calculations and the climbing-image nudge-elastic-band (CI-NEB) method. Among five typical stacking orders, which can be categorized into two kinds (I: AA, AB and II: AA', AB', A'B), we found that stacking orders with Mo and S superposing from both layers, such as AA' and AB, is more stable than the others. With smaller computational efforts than potential energy profile searching, we can study the effect of inter-layer stress on the stacking stability. Under isobaric condition, the sliding barrier increases by a few eV/(ucGPa) from AA' to AB', compared to 0.1 eV/(ucGPa) from AB to [AB]. Moreover, we found that interlayer compressive stress can help enhance the transport properties of AA'. This study can help understand why inter-layer stress by dielectric gating materials can be an effective means to improving MoS 2 on nanoelectronic applications. (condensed matter: structural, mechanical, and thermal properties)

  8. Gate protective device for SOS array

    Science.gov (United States)

    Meyer, J. E., Jr.; Scott, J. H.

    1972-01-01

    Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

  9. Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

    Science.gov (United States)

    Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

    2017-01-01

    The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

  10. Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

    Science.gov (United States)

    Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

    2018-01-01

    Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

  11. Achieving Ohmic Contact for High-quality MoS2 Devices on Hexagonal Boron Nitride

    Science.gov (United States)

    Cui, Xu

    MoS2, among many other transition metal dichalcogenides (TMDCs), holds great promise for future applications in nano-electronics, opto-electronics and mechanical devices due to its ultra-thin nature, flexibility, sizable band-gap, and unique spin-valley coupled physics. However, there are two main challenges that hinder careful study of this material. Firstly, it is hard to achieve Ohmic contacts to mono-layer MoS2, particularly at low temperatures (T) and low carrier densities. Secondly, materials' low quality and impurities introduced during the fabrication significantly limit the electron mobility of mono- and few-layer MoS2 to be substantially below theoretically predicted limits, which has hampered efforts to observe its novel quantum transport behaviours. Traditional low work function metals doesn't necessary provide good electron injection to thin MoS2 due to metal oxidation, Fermi level pinning, etc. To address the first challenge, we tried multiple contact schemes and found that mono-layer hexagonal boron nitride (h-BN) and cobalt (Co) provide robust Ohmic contact. The mono-layer spacer serves two advantageous purposes: it strongly interacts with the transition metal, reducing its work function by over 1 eV; and breaks the metal-TMDCs interaction to eliminate the interfacial states that cause Fermi level pinning. We measure a flat-band Schottky barrier of 16 meV, which makes thin tunnel barriers upon doping the channels, and thus achieve low-T contact resistance of 3 kohm.um at a carrier density of 5.3x10. 12/cm. 2. Similar to graphene, eliminating all potential sources of disorder and scattering is the key to achieving high performance in MoS2 devices. We developed a van der Waals heterostructure device platform where MoS2 layers are fully encapsulated within h-BN and electrically contacted in a multi-terminal geometry using gate-tunable graphene electrodes. The h-BN-encapsulation provides excellent protection from environmental factors, resulting in

  12. Model for thickness dependence of radiation charging in MOS structures

    Science.gov (United States)

    Viswanathan, C. R.; Maserjian, J.

    1976-01-01

    The model considers charge buildup in MOS structures due to hole trapping in the oxide and the creation of sheet charge at the silicon interface. The contribution of hole trapping causes the flatband voltage to increase with thickness in a manner in which square and cube dependences are limiting cases. Experimental measurements on samples covering a 200 - 1000 A range of oxide thickness are consistent with the model, using independently obtained values of hole-trapping parameters. An important finding of our experimental results is that a negative interface charge contribution due to surface states created during irradiation compensates most of the positive charge in the oxide at flatband. The tendency of the surface states to 'track' the positive charge buildup in the oxide, for all thicknesses, applies both in creation during irradiation and in annihilation during annealing. An explanation is proposed based on the common defect origin of hole traps and potential surface states.

  13. Ballistic transport of graphene pnp junctions with embedded local gates

    International Nuclear Information System (INIS)

    Nam, Seung-Geol; Ki, Dong-Keun; Kim, Youngwook; Kim, Jun Sung; Lee, Hu-Jong; Park, Jong Wan

    2011-01-01

    We fabricated graphene pnp devices, by embedding pre-defined local gates in an oxidized surface layer of a silicon substrate. With neither deposition of dielectric material on the graphene nor electron-beam irradiation, we obtained high-quality graphene pnp devices without degradation of the carrier mobility even in the local-gate region. The corresponding increased mean free path leads to the observation of ballistic and phase-coherent transport across a local gate 130 nm wide, which is about an order of magnitude wider than reported previously. Furthermore, in our scheme, we demonstrated independent control of the carrier density in the local-gate region, with a conductance map very much distinct from those of top-gated devices. This was caused by the electric field arising from the global back gate being strongly screened by the embedded local gate. Our scheme allows the realization of ideal multipolar graphene junctions with ballistic carrier transport.

  14. Investigations of AlGaN/GaN MOS-HEMT with Al2O3 deposition by ultrasonic spray pyrolysis method

    International Nuclear Information System (INIS)

    Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Wu, Yu-Sheng; Lee, Ching-Sung; Sun, Wen-Ching; Wei, Sung-Yen; Yu, Sheng-Min; Chiang, Meng-Hsueh

    2015-01-01

    This work investigates Al 2 O 3 /AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) grown on SiC substrate by using the non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. The Al 2 O 3 was deposited as gate dielectric and surface passivation simultaneously to effectively suppress gate leakage current, enhance output current density, reduce RF drain current collapse, and improve temperature-dependent stabilities performance. The present MOS-HEMT design has shown improved device performances with respect to a Schottky-gate HEMT, including drain-source saturation current density at zero gate bias (I DSS : 337.6 mA mm −1  → 462.9 mA mm −1 ), gate-voltage swing (GVS: 1.55 V → 2.92 V), two-terminal gate-drain breakdown voltage (BV GD : −103.8 V → −183.5 V), unity-gain cut-off frequency (f T : 11.3 GHz → 17.7 GHz), maximum oscillation frequency (f max : 14.2 GHz → 19.1 GHz), and power added effective (P.A.E.: 25.1% → 43.6%). The bias conditions for measuring f T and f max of the studied MOS-HEMT (Schottky-gate HEMT) are V GS  = −2.5 (−2) V and V DS  = 7 V. The corresponding V GS and V DS biases are −2.5 (−2) V and 15 V for measuring the P.A.E. characteristic. Moreover, small capacitance-voltage (C–V) hysteresis is obtained in the Al 2 O 3 -MOS structure by using USPD. Temperature-dependent characteristics of the present designs at 300–480 K are also studied. (paper)

  15. Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

    2009-07-01

    The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

  16. Micro-irradiation experiments in MOS transistors using synchrotron radiation; Experiences de micro-irradiation de transistors MOS a l'aide d'un rayonnement synchrotron

    Energy Technology Data Exchange (ETDEWEB)

    Autran, J.L.; Masson, P.; Raynaud, C. [Institut National des Sciences Appliquees (INSA), 69 - Villeurbanne (France). Lab. de Physique de la Matiere; Masson, P. [Ecole Nationale Superieure d' Electronique et de Radio-Electricite, ENSERG/LPCS, 38 - Grenoble (France); Freud, N. [Institut National des Sciences Appliquees (INSA), CNDRI, 69 - Villeurbanne (France); Riekel, C. [European Synchrotron Radiation Facility ESRF, 38 - Grenoble (France)

    1999-07-01

    Spatially-resolved total-dose degradation has been performed in MOS transistors by focusing x-ray synchrotron radiation on the gate electrode with micrometer resolution. The influence of the resulting permanent degradation on device electrical properties has been analyzed using current-voltage and charge pumping measurements, in concert with optical characterization (hot-carrier luminescence) and one-dimensional device simulation. (authors)

  17. Mimicking Neurotransmitter Release in Chemical Synapses via Hysteresis Engineering in MoS2 Transistors.

    Science.gov (United States)

    Arnold, Andrew J; Razavieh, Ali; Nasr, Joseph R; Schulman, Daniel S; Eichfeld, Chad M; Das, Saptarshi

    2017-03-28

    Neurotransmitter release in chemical synapses is fundamental to diverse brain functions such as motor action, learning, cognition, emotion, perception, and consciousness. Moreover, improper functioning or abnormal release of neurotransmitter is associated with numerous neurological disorders such as epilepsy, sclerosis, schizophrenia, Alzheimer's disease, and Parkinson's disease. We have utilized hysteresis engineering in a back-gated MoS 2 field effect transistor (FET) in order to mimic such neurotransmitter release dynamics in chemical synapses. All three essential features, i.e., quantal, stochastic, and excitatory or inhibitory nature of neurotransmitter release, were accurately captured in our experimental demonstration. We also mimicked an important phenomenon called long-term potentiation (LTP), which forms the basis of human memory. Finally, we demonstrated how to engineer the LTP time by operating the MoS 2 FET in different regimes. Our findings could provide a critical component toward the design of next-generation smart and intelligent human-like machines and human-machine interfaces.

  18. The Positive Effects of Hydrophobic Fluoropolymers on the Electrical Properties of MoS2 Transistors

    Directory of Open Access Journals (Sweden)

    Somayyeh Rahimi

    2016-08-01

    Full Text Available We report the improvement of the electrical performance of field effect transistors (FETs fabricated on monolayer chemical vapor deposited (CVD MoS2, by applying an interacting fluoropolymer capping layer (Teflon-AF. The electrical characterizations of more than 60 FETs, after applying Teflon-AF cap, show significant improvement of the device properties and reduced device to device variation. The improvement includes: 50% reduction of the average gate hysteresis, 30% reduction of the subthreshold swing and about an order of magnitude increase of the current on-off ratio. These favorable changes in device performance are attributed to the reduced exposure of MoS2 channels to the adsorbates in the ambient which can be explained by the polar nature of Teflon-AF cap. A positive shift in the threshold voltage of all the measured FETs is observed, which translates to the more desirable enhancement mode transistor characteristics.

  19. Understanding Coulomb Scattering Mechanism in Monolayer MoS2 Channel in the Presence of h-BN Buffer Layer.

    Science.gov (United States)

    Joo, Min-Kyu; Moon, Byoung Hee; Ji, Hyunjin; Han, Gang Hee; Kim, Hyun; Lee, Gwanmu; Lim, Seong Chu; Suh, Dongseok; Lee, Young Hee

    2017-02-08

    As the thickness becomes thinner, the importance of Coulomb scattering in two-dimensional layered materials increases because of the close proximity between channel and interfacial layer and the reduced screening effects. The Coulomb scattering in the channel is usually obscured mainly by the Schottky barrier at the contact in the noise measurements. Here, we report low-temperature (T) noise measurements to understand the Coulomb scattering mechanism in the MoS 2 channel in the presence of h-BN buffer layer on the silicon dioxide (SiO 2 ) insulating layer. One essential measure in the noise analysis is the Coulomb scattering parameter (α SC ) which is different for channel materials and electron excess doping concentrations. This was extracted exclusively from a 4-probe method by eliminating the Schottky contact effect. We found that the presence of h-BN on SiO 2 provides the suppression of α SC twice, the reduction of interfacial traps density by 100 times, and the lowered Schottky barrier noise by 50 times compared to those on SiO 2 at T = 25 K. These improvements enable us to successfully identify the main noise source in the channel, which is the trapping-detrapping process at gate dielectrics rather than the charged impurities localized at the channel, as confirmed by fitting the noise features to the carrier number and correlated mobility fluctuation model. Further, the reduction in contact noise at low temperature in our system is attributed to inhomogeneous distributed Schottky barrier height distribution in the metal-MoS 2 contact region.

  20. Energy dependence of pMOS dosemeters

    International Nuclear Information System (INIS)

    Savic, Z.; Stankovic, S.; Kovacevic, M.; Petrovic, M.

    1996-01-01

    The results are presented of experimental work and numerical simulations of the energy response for pMOS dosimetric transistors in their custom packages. Specially produced radiation soft pMOS transistors were used in this experimental work. The irradiation of pMOS dosemeters was done using 60 Co and 137 Cs sources, a dosimetric X ray unit, and a radiotherapeutic linear accelerator in the range of photon energies from 21 keV to 8 MeV. The results show that package geometry and materials can significantly affect and smooth the energy dependence of pMOS transistors and that in custom transistor packages they are not tissue-equivalent dosemeters. Their response in the photon energy range of 45 to 250 keV is significantly larger than it should be (maximum dose enhancement factor can be as high as 8) and some energy compensation techniques must be used in order to fulfill the requirements of corresponding standards. (Author)

  1. Contact-Engineered Electrical Properties of MoS2 Field-Effect Transistors via Selectively Deposited Thiol-Molecules.

    Science.gov (United States)

    Cho, Kyungjune; Pak, Jinsu; Kim, Jae-Keun; Kang, Keehoon; Kim, Tae-Young; Shin, Jiwon; Choi, Barbara Yuri; Chung, Seungjun; Lee, Takhee

    2018-05-01

    Although 2D molybdenum disulfide (MoS 2 ) has gained much attention due to its unique electrical and optical properties, the limited electrical contact to 2D semiconductors still impedes the realization of high-performance 2D MoS 2 -based devices. In this regard, many studies have been conducted to improve the carrier-injection properties by inserting functional paths, such as graphene or hexagonal boron nitride, between the electrodes and 2D semiconductors. The reported strategies, however, require relatively time-consuming and low-yield transfer processes on sub-micrometer MoS 2 flakes. Here, a simple contact-engineering method is suggested, introducing chemically adsorbed thiol-molecules as thin tunneling barriers between the metal electrodes and MoS 2 channels. The selectively deposited thiol-molecules via the vapor-deposition process provide additional tunneling paths at the contact regions, improving the carrier-injection properties with lower activation energies in MoS 2 field-effect transistors. Additionally, by inserting thiol-molecules at the only one contact region, asymmetric carrier-injection is feasible depending on the temperature and gate bias. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  2. Integrated amplifying circuit with MOS transistors

    Energy Technology Data Exchange (ETDEWEB)

    Baylac, B; Merckel, G; Meunier, P

    1974-01-25

    The invention relates to a feedback-pass-band amplifier with MOS-transistors. The differential stage of conventional amplifiers is changed into an adding state, whereas the differential amplification stages are changed into amplifier inverter stages. All MOS transistors used in that amplifier are of similar configuration and are interdigitized, whereby the operating speed dispersion is reduced. This can be applied to obtaining a measurement channel for proportional chambers.

  3. Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

    Science.gov (United States)

    Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

    2017-05-01

    A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

  4. Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

    Directory of Open Access Journals (Sweden)

    Mohamed T. Ghoneim

    2015-12-01

    Full Text Available In today’s digital world, complementary metal oxide semiconductor (CMOS technology enabled scaling of bulk mono-crystalline silicon (100 based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm mono-crystalline (100 silicon (detached from bulk substrate by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs with high-κ/metal gate stacks.

  5. Materials preparation and fabrication of pyroelectric polymer/silicon MOSFET detector arrays. Final report

    International Nuclear Information System (INIS)

    Bloomfield, P.

    1992-01-01

    The authors have delivered several 64-element linear arrays of pyroelectric elements fully integrated on silicon wafers with MOS readout devices. They have delivered detailed drawings of the linear arrays to LANL. They have processed a series of two inch wafers per submitted design. Each two inch wafer contains two 64 element arrays. After spin-coating copolymer onto the arrays, vacuum depositing the top electrodes, and polarizing the copolymer films so as to make them pyroelectrically active, each wafer was split in half. The authors developed a thicker oxide coating separating the extended gate electrode (beneath the polymer detector) from the silicon. This should reduce its parasitic capacitance and hence improve the S/N. They provided LANL three processed 64 element sensor arrays. Each array was affixed to a connector panel and selected solder pads of the common ground, the common source voltage supply connections, the 64 individual drain connections, and the 64 drain connections (for direct pyroelectric sensing response rather than the MOSFET action) were wire bonded to the connector panel solder pads. This entails (64 + 64 + 1 + 1) = 130 possible bond connections per 64 element array. This report now details the processing steps and the progress of the individual wafers as they were carried through from beginning to end

  6. Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

    KAUST Repository

    Ghoneim, Mohamed T.; Fahad, Hossain M.; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Sevilla, Galo T.; Alfaraj, Nasir; Lizardo, Ernesto B.; Hussain, Muhammad Mustafa

    2015-01-01

    In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

  7. Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

    KAUST Repository

    Ghoneim, Mohamed T.

    2015-12-11

    In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.

  8. Electroluminescence properties of Si MOS structures with incorporation of FeSi2 precipitates formed by iron implantation

    International Nuclear Information System (INIS)

    Chow, C.F.; Wong, S.P.; Gao, Y.; Ke, N.; Li, Q.; Cheung, W.Y.; Lourenco, M.A.; Homewood, K.P.

    2005-01-01

    Silicon MOS structures with FeSi 2 precipitates embedded in the MOS active region have been fabricated and the electroluminescence (EL) properties from these FeSi 2 -Si MOS structures were measured as a function of temperature from 80 K to 300 K. Clear EL signals were observed even at room temperature for samples prepared at appropriate processing conditions. The EL spectra consist of two peaks, one attributed to FeSi 2 and the other attributed to Si band edge emission. While the intensity of the FeSi 2 peak showed the usual thermal quenching behavior, the Si band edge emission showed the opposite trend with its intensity increased with increasing temperature. Details of the line shapes and their temperature dependence are analyzed and discussed

  9. Photonic characterization of capacitance-voltage characteristics in MOS capacitors and current-voltage characteristics in MOSFETs

    International Nuclear Information System (INIS)

    Kim, H. C.; Kim, H. T.; Cho, S. D.; Song, S. J.; Kim, Y. C.; Kim, S. K.; Chi, S. S.; Kim, D. J.; Kim, D. M.

    2002-01-01

    Based on the photonic high-frequency capacitance-voltage (HF-CV) response of MOS capacitors, a new characterization method is reported for the analysis of interface states in MOS systems. An optical source with a photonic energy less than the silicon band-gap energy (hv g ) is employed for the photonic HF-CV characterization of interface states distributed in the photoresponsive energy band (E C - hv t C ). If a uniform distribution of trap levels is assumed, the density of interface states (D it ) in the photoresponsive energy band of MOS capacitors, characterized by the new photonic HF-CV method, was observed to be D it = 1 ∼ 5 x 10 11 eV -1 cm -2 . Photonic current-voltage characteristics (I D - V GS , V DS ) of MOSFETs, which are under control of the photoconductive and the photovoltaic effects, are also investigated under optical illumination

  10. Nanoscale MOS devices: device parameter fluctuations and low-frequency noise (Invited Paper)

    Science.gov (United States)

    Wong, Hei; Iwai, Hiroshi; Liou, J. J.

    2005-05-01

    It is well-known in conventional MOS transistors that the low-frequency noise or flicker noise is mainly contributed by the trapping-detrapping events in the gate oxide and the mobility fluctuation in the surface channel. In nanoscale MOS transistors, the number of trapping-detrapping events becomes less important because of the large direct tunneling current through the ultrathin gate dielectric which reduces the probability of trapping-detrapping and the level of leakage current fluctuation. Other noise sources become more significant in nanoscale devices. The source and drain resistance noises have greater impact on the drain current noise. Significant contribution of the parasitic bipolar transistor noise in ultra-short channel and channel mobility fluctuation to the channel noise are observed. The channel mobility fluctuation in nanoscale devices could be due to the local composition fluctuation of the gate dielectric material which gives rise to the permittivity fluctuation along the channel and results in gigantic channel potential fluctuation. On the other hand, the statistical variations of the device parameters across the wafer would cause the noise measurements less accurate which will be a challenge for the applicability of analytical flicker noise model as a process or device evaluation tool for nanoscale devices. Some measures for circumventing these difficulties are proposed.

  11. Transformational silicon electronics

    KAUST Repository

    Rojas, Jhonathan Prieto

    2014-02-25

    In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

  12. Ionizing radiation M.O.S. dosimeters: sensibility and stability; Dosimetres M.O.S. de rayonnements ionisants: sensibilite et stabilite

    Energy Technology Data Exchange (ETDEWEB)

    Gessinn, F

    1993-12-01

    This thesis is a contribution to the study of the ionizing radiation responsivity of P.O.M.S. dosimeters. Unlike the development of processing hardening techniques, our works goal were to increase, on the one hand, the M.O.S. dosimeters sensitivity in order to detect small radiation doses and on the other hand, the stability with time and temperature of the devices, to minimize the absorbed-dose estimation errors. With this aim in mind, an analysis of all processing parameters has been carried out: the M.O.S. dosimeter sensitivity is primarily controlled by the gate oxide thickness and the irradiation electric field. Thus, P.M.O.S. transistors with 1 and 2 {mu}m thick silica layers have been fabricated for our experiments. The radiation response of our devices in the high-field mode satisfactorily fits a D{sub ox}{sup 2} power law. The maximum sensitivity achieved (9,2 V/Gy for 2{mu}m devices) is close to the ideal value obtained when considering only an unitary carrier-trapping level, and allows to measure about 10{sup -2} Gy radiation doses. Read-time stability has been evaluated under bias-temperature stress conditions: experiments underscore slow fading, corresponding to 10{sup -3} Gy/h. The temperature response has also been studied: the analytical model we have developed predicts M.O.S. transistors threshold voltage variations over the military specifications range [-50 deg. C, + 150 deg. C]. Finally, we have investigated the possibilities of irradiated dosimeters thermal annealing for reusing. It appears clearly that radiation-induced damage annealing is strongly gate bias dependent. Furthermore, dosimeters radiation sensitivity seems not to be affected by successive annealings. (author). 146 refs., 58 figs., 9 tabs.

  13. Valley- and spin-filter in monolayer MoS2

    Science.gov (United States)

    Majidi, Leyla; Zare, Moslem; Asgari, Reza

    2014-12-01

    We propose a valley- and spin-filter based on a normal/ferromagnetic/normal molybdenum disulfide (MoS2) junction where the polarizations of the valley and the spin can be inverted by reversing the direction of the exchange field in the ferromagnetic region. By using a modified Dirac Hamiltonian and the scattering formalism, we find that the polarizations can be tuned by applying a gate voltage and changing the exchange field in the structure. We further demonstrate that the presence of a topological term (β) in the Hamiltonian results in an enhancement or a reduction of the charge conductance depending on the value of the exchange field.

  14. AlN/GaN-Based MOS-HEMT Technology: Processing and Device Results

    Directory of Open Access Journals (Sweden)

    S. Taking

    2011-01-01

    Full Text Available Process development of AlN/GaN MOS-HEMTs is presented, along with issues and problems concerning the fabrication processes. The developed technology uses thermally grown Al2O3 as a gate dielectric and surface passivation for devices. Significant improvement in device performance was observed using the following techniques: (1 Ohmic contact optimisation using Al wet etch prior to Ohmic metal deposition and (2 mesa sidewall passivation. DC and RF performance of the fabricated devices will be presented and discussed in this paper.

  15. Enhanced interfacial and electrical characteristics of 4H-SiC MOS capacitor with lanthanum silicate passivation interlayer

    International Nuclear Information System (INIS)

    Wang, Qian; Cheng, Xinhong; Zheng, Li; Ye, Peiyi; Li, Menglu; Shen, Lingyan; Li, Jingjie; Zhang, Dongliang; Gu, Ziyue; Yu, Yuehui

    2017-01-01

    Highlights: • The 4H-SiC MOS capacitor with an untra-thin LaSiO_x passivation layer and Al_2O_3 gate dielectric was fabricated. • The detrimental SiO_x interfacial layer could be effectively restrained by the LaSiO_x passivation layer. • The passivation mechanism of LaSiO_x was analyzed by HRTEM, XPS and electrical measurements. • The 4H-SiC MOS capacitor with a LaSiO_x passivation layer shows excellent device characteristics. • This technique provides an efficient path to improve dielectrics/4H-SiC interfaces for future high-power device applications. - Abstract: The detrimental sub-oxide (SiO_x) interfacial layer formed during the 4H-SiC metal-oxide-semiconductor (MOS) capacitor fabrication will drastically damage its device performance. In this work, an ultrathin lanthanum silicate (LaSiO_x) passivation layer was introduced to enhance the interfacial and electrical characteristics of 4H-SiC MOS capacitor with Al_2O_3 gate dielectric. The interfacial LaSiO_x formation was investigated by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy. The 4H-SiC MOS capacitor with ultrathin LaSiO_x passivation interlayer shows excellent interfacial and electrical characteristics, including lower leakage current density, higher dielectric breakdown electric field, smaller C–V hysteresis, and lower interface states density and border traps density. The involved mechanism implies that the LaSiO_x passivation interlayer can effectively restrain SiO_x formation and improve the Al_2O_3/4H-SiC interface quality. This technique provides an efficient path to improve dielectrics/4H-SiC interfaces for future high-power device applications.

  16. Experimental investigation of N-MOS inversion layers in the electric quantum limit

    NARCIS (Netherlands)

    Kalnitsky, A.; Boothroyd, A.R.; Ellul, J.P.; Tarr, N.G.; Weaver, L.; Beerkens, R.G.C.

    1992-01-01

    The authors report on the exptl. detn. of inversion electron charge d., silicon surface potential, and effective electron mobility vs. oxide elec. field, for NMOSFETs with gate oxide thickness Tox = 2.2 nm operating far beyond the limit of applicability of Boltzmann relations in the inversion layer.

  17. MOSFET and MOS capacitor responses to ionizing radiation

    Science.gov (United States)

    Benedetto, J. M.; Boesch, H. E., Jr.

    1984-01-01

    The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of 'slow' states can interfere with the interface-state measurements.

  18. Silicone metalization

    Energy Technology Data Exchange (ETDEWEB)

    Maghribi, Mariam N. (Livermore, CA); Krulevitch, Peter (Pleasanton, CA); Hamilton, Julie (Tracy, CA)

    2008-12-09

    A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

  19. Parametric Conversion Using Custom MOS Varactors

    Directory of Open Access Journals (Sweden)

    Iniewski Krzysztof (Kris

    2006-01-01

    Full Text Available The possible role of customized MOS varactors in amplification, mixing, and frequency control of future millimeter wave CMOS RFICs is outlined. First, the parametric conversion concept is revisited and discussed in terms of modern RF communications systems. Second, the modeling, design, and optimization of MOS varactors are reconsidered in the context of their central role in parametric circuits. Third, a balanced varactor structure is proposed for robust oscillator frequency control in the presence of large extrinsic noise expected in tightly integrated wireless communicators. Main points include the proposal of a subharmonic pumping scheme based on the MOS varactor, a nonequilibrium elastance-voltage model, optimal varactor layout suggestions, custom m-CMOS varactor design and measurement, device-level balanced varactor simulations, and parametric circuit evaluation based on measured device characteristics.

  20. Electrothermal DC characterization of GaN on Si MOS-HEMTs

    Science.gov (United States)

    Rodríguez, R.; González, B.; García, J.; Núñez, A.

    2017-11-01

    DC characteristics of AlGaN/GaN on Si single finger MOS-HEMTs, for different gate geometries, have been measured and numerically simulated with substrate temperatures up to 150 °C. Defect density, depending on gate width, and thermal resistance, depending additionally on temperature, are extracted from transfer characteristics displacement and the AC output conductance method, respectively, and modeled for numerical simulations with Atlas. The thermal conductivity degradation in thin films is also included for accurate simulation of the heating response. With an appropriate methodology, the internal model parameters for temperature dependencies have been established. The numerical simulations show a relative error lower than 4.6% overall, for drain current and channel temperature behavior, and account for the measured device temperature decrease with the channel length increase as well as with the channel width reduction, for a set bias.

  1. Electron microscopy studies on MoS2 nanocrystals

    DEFF Research Database (Denmark)

    Hansen, Lars Pilsgaard

    Industrial-style MoS2-based hydrotreating catalysts are studied using electron microscopy. The MoS2 nanostructures are imaged with single-atom sensitivity to reveal the catalytically important edge structures. Furthermore, the in-situ formation of MoS2 crystals is imaged for the first time....

  2. Large-area few-layer MoS 2 deposited by sputtering

    KAUST Repository

    Huang, Jyun-Hong

    2016-06-06

    Direct magnetron sputtering of transition metal dichalcogenide targets is proposed as a new approach for depositing large-area two-dimensional layered materials. Bilayer to few-layer MoS2 deposited by magnetron sputtering followed by post-deposition annealing shows superior area scalability over 20 cm(2) and layer-by-layer controllability. High crystallinity of layered MoS2 was confirmed by Raman, photo-luminescence, and transmission electron microscopy analysis. The sputtering temperature and annealing ambience were found to play an important role in the film quality. The top-gate field-effect transistor by using the layered MoS2 channel shows typical n-type characteristics with a current on/off ratio of approximately 10(4). The relatively low mobility is attributed to the small grain size of 0.1-1 mu m with a trap charge density in grain boundaries of the order of 10(13) cm(-2).

  3. New gate opening hours

    CERN Multimedia

    GS Department

    2009-01-01

    Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

  4. Tuning on-off current ratio and field-effect mobility in a MoS(2)-graphene heterostructure via Schottky barrier modulation.

    Science.gov (United States)

    Shih, Chih-Jen; Wang, Qing Hua; Son, Youngwoo; Jin, Zhong; Blankschtein, Daniel; Strano, Michael S

    2014-06-24

    Field-effect transistor (FET) devices composed of a MoS2-graphene heterostructure can combine the advantages of high carrier mobility in graphene with the permanent band gap of MoS2 for digital applications. Herein, we investigate the electron transfer, photoluminescence, and gate-controlled carrier transport in such a heterostructure. We show that the junction is a Schottky barrier, whose height can be artificially controlled by gating or doping graphene. When the applied gate voltage (or the doping level) is zero, the photoexcited electron-hole pairs in monolayer MoS2 can be split by the heterojunction, significantly reducing the photoluminescence. By applying negative gate voltage (or p-doping) in graphene, the interlayer impedance formed between MoS2 and graphene exhibits an 100-fold increase. For the first time, we show that the gate-controlled interlayer Schottky impedance can be utilized to modulate carrier transport in graphene, significantly depleting the hole transport, but preserving the electron transport. Accordingly, we demonstrate a new type of FET device, which enables a controllable transition from NMOS digital to bipolar characteristics. In the NMOS digital regime, we report a very high room temperature on/off current ratio (ION/IOFF ∼ 36) in comparison to graphene-based FET devices without sacrificing the field-effect electron mobilities in graphene. By engineering the source/drain contact area, we further estimate that a higher value of ION/IOFF up to 100 can be obtained in the device architecture considered. The device architecture presented here may enable semiconducting behavior in graphene for digital and analogue electronics.

  5. Investigations on MgO-dielectric GaN/AlGaN/GaN MOS-HEMTs by using an ultrasonic spray pyrolysis deposition technique

    International Nuclear Information System (INIS)

    Lee, Ching-Sung; Liu, Han-Yin; Wu, Ting-Ting; Hsu, Wei-Chou; Sun, Wen-Ching; Wei, Sung-Yen; Yu, Sheng-Min

    2016-01-01

    This work investigates GaN/Al 0.24 Ga 0.76 N/GaN metal-oxide-semiconductor high electron mobility transistors (MOS-HEMTs) grown on a Si substrate with MgO gate dielectric by using the non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. The oxide layer thickness is tuned to be 30 nm with the dielectric constant of 8.8. Electron spectroscopy for chemical analysis (ESCA), secondary ion mass spectrometry (SIMS), atomic force microscopy (AFM), transmission electron microscopy (TEM), C–V, low-frequency noise spectra, and pulsed I–V measurements are performed to characterize the interface and oxide quality for the MOS-gate structure. Improved device performances have been successfully achieved for the present MOS-HEMT (Schottky-gate HEMT) design, consisting of a maximum drain-source current density (I DS, max ) of 681 (500) mA/mm at V GS  = 4 (2) V, I DS at V GS  = 0 V (I DSS0 ) of 329 (289) mA/mm, gate-voltage swing (GVS) of 2.2 (1.6) V, two-terminal gate-drain breakdown voltage (BV GD ) of −123 (−104) V, turn-on voltage (V on ) of 1.7 (0.8) V, three-terminal off-state drain-source breakdown voltage (BV DS ) of 119 (96) V, and on/off current ratio (I on /I off ) of 2.5 × 10 8 (1.2 × 10 3 ) at 300 K. Improved high-frequency and power performances are also achieved in the present MOS-HEMT design. (paper)

  6. Electronic structure of silicon superlattices

    International Nuclear Information System (INIS)

    Krishnamurthy, S.; Moriarty, J.A.

    1984-01-01

    Utilizing a new complex-band-structure technique, the electronic structure of model Si-Si/sub 1-x/Ge/sub x/ and MOS superlattices has been obtained over a wide range of layer thickness d (11 less than or equal to d less than or equal to 110 A). For d greater than or equal to 44 A, it is found that these systems exhibit a direct fundamental band gap. Further calculations of band-edge effective masses and impurity scattering rates suggest the possibility of a band-structure-driven enhancement in electron mobility over bulk silicon

  7. Highly sensitive wide bandwidth photodetector based on internal photoemission in CVD grown p-type MoS2/graphene Schottky junction.

    Science.gov (United States)

    Vabbina, PhaniKiran; Choudhary, Nitin; Chowdhury, Al-Amin; Sinha, Raju; Karabiyik, Mustafa; Das, Santanu; Choi, Wonbong; Pala, Nezih

    2015-07-22

    Two dimensional (2D) Molybdenum disulfide (MoS2) has evolved as a promising material for next generation optoelectronic devices owing to its unique electrical and optical properties, such as band gap modulation, high optical absorption, and increased luminescence quantum yield. The 2D MoS2 photodetectors reported in the literature have presented low responsivity compared to silicon based photodetectors. In this study, we assembled atomically thin p-type MoS2 with graphene to form a MoS2/graphene Schottky photodetector where photo generated holes travel from graphene to MoS2 over the Schottky barrier under illumination. We found that the p-type MoS2 forms a Schottky junction with graphene with a barrier height of 139 meV, which results in high photocurrent and wide spectral range of detection with wavelength selectivity. The fabricated photodetector showed excellent photosensitivity with a maximum photo responsivity of 1.26 AW(-1) and a noise equivalent power of 7.8 × 10(-12) W/√Hz at 1440 nm.

  8. Richardson constant and electrostatics in transfer-free CVD grown few-layer MoS2/graphene barristor with Schottky barrier modulation >0.6eV

    Science.gov (United States)

    Jahangir, Ifat; Uddin, M. Ahsan; Singh, Amol K.; Koley, Goutam; Chandrashekhar, M. V. S.

    2017-10-01

    We demonstrate a large area MoS2/graphene barristor, using a transfer-free method for producing 3-5 monolayer (ML) thick MoS2. The gate-controlled diodes show good rectification, with an ON/OFF ratio of ˜103. The temperature dependent back-gated study reveals Richardson's coefficient to be 80.3 ± 18.4 A/cm2/K and a mean electron effective mass of (0.66 ± 0.15)m0. Capacitance and current based measurements show the effective barrier height to vary over a large range of 0.24-0.91 eV due to incomplete field screening through the thin MoS2. Finally, we show that this barristor shows significant visible photoresponse, scaling with the Schottky barrier height. A response time of ˜10 s suggests that photoconductive gain is present in this device, resulting in high external quantum efficiency.

  9. Room-temperature superparamagnetism due to giant magnetic anisotropy in Mo S defected single-layer MoS2

    Science.gov (United States)

    Khan, M. A.; Leuenberger, Michael N.

    2018-04-01

    Room-temperature superparamagnetism due to a large magnetic anisotropy energy (MAE) of a single atom magnet has always been a prerequisite for nanoscale magnetic devices. Realization of two dimensional (2D) materials such as single-layer (SL) MoS2, has provided new platforms for exploring magnetic effects, which is important for both fundamental research and for industrial applications. Here, we use density functional theory (DFT) to show that the antisite defect (Mo S ) in SL MoS2 is magnetic in nature with a magnetic moment μ of  ∼2 μB and, remarkably, exhibits an exceptionally large atomic scale MAE =\\varepsilon\\parallel-\\varepsilon\\perp of  ∼500 meV. Our calculations reveal that this giant anisotropy is the joint effect of strong crystal field and significant spin–orbit coupling (SOC). In addition, the magnetic moment μ can be tuned between 1 μB and 3 μB by varying the Fermi energy \\varepsilonF , which can be achieved either by changing the gate voltage or by chemical doping. We also show that MAE can be raised to  ∼1 eV with n-type doping of the MoS2:Mo S sample. Our systematic investigations deepen our understanding of spin-related phenomena in SL MoS2 and could provide a route to nanoscale spintronic devices.

  10. Energy dependence of pMOS dosemeters

    Energy Technology Data Exchange (ETDEWEB)

    Savic, Z. [Military Technical Institute, Belgrade (Yugoslavia); Stankovic, S.; Kovacevic, M.; Petrovic, M. [Institute of Nuclear Sciences, Belgrade (Yugoslavia). Radiation Protection Dept.

    1996-10-01

    The results are presented of experimental work and numerical simulations of the energy response for pMOS dosimetric transistors in their custom packages. Specially produced radiation soft pMOS transistors were used in this experimental work. The irradiation of pMOS dosemeters was done using {sup 60}Co and {sup 137}Cs sources, a dosimetric X ray unit, and a radiotherapeutic linear accelerator in the range of photon energies from 21 keV to 8 MeV. The results show that package geometry and materials can significantly affect and smooth the energy dependence of pMOS transistors and that in custom transistor packages they are not tissue-equivalent dosemeters. Their response in the photon energy range of 45 to 250 keV is significantly larger than it should be (maximum dose enhancement factor can be as high as 8) and some energy compensation techniques must be used in order to fulfill the requirements of corresponding standards. (Author).

  11. Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

    Science.gov (United States)

    Nagaiah, Padmaja

    As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p

  12. High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

    Science.gov (United States)

    Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

    2018-04-18

    A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

  13. Cleaning Challenges of High-κ/Metal Gate Structures

    KAUST Repository

    Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.

    2010-01-01

    High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

  14. Cleaning Challenges of High-κ/Metal Gate Structures

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-12-20

    High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

  15. Gold nanoparticles on MoS2 layered crystal flakes

    International Nuclear Information System (INIS)

    Cao, Wei; Pankratov, Vladimir; Huttula, Marko; Shi, Xinying; Saukko, Sami; Huang, Zhongjia; Zhang, Meng

    2015-01-01

    Inorganic layered crystal MoS 2 is considered as one of the most promising and efficient semiconductor materials for future transistors, photoelectronics, and electrocatalysis. To boost MoS 2 -based material applications, one direction is to grow physically and chemically reactive nanoparticles onto MoS 2 . Here we report on a simple route to synthesis crystalized MoS 2 –Au complexes. The gold nanoparticles were grown on MoS 2 flakes through a wet method in the oxygen free environment at room temperature. Nanoparticles with diameters varying from 9 nm to 429 nm were controlled by the molar ratios of MoS 2 and HAuCl 4 precursors. MoS 2 host flakes keep intrinsic honeycomb layered structures and the Au nanoparticles cubic-center crystal microstructures. From product chemical states analysis, the synthesis was found driven by redox reactions between the sulphide and the chloroauric acid. Photoluminescence measurement showed that introducing Au nanoparticles onto MoS 2 stacks substantially prompted excitonic transitions of stacks, as an analogy for doping Si wafers with dopants. Such composites may have potential applications in wide ranges similar as the doped Si. - Highlights: • The Au nanoparticles were decorated on MoS 2 in oxygen free ambiences via a wet method. • The Au nanoparticles are size-controllable and crystalized. • Chemical reaction scheme was clarified. • The MoS 2 –Au complexes have strong photoluminescent properties

  16. Defect formation in oxygen- and boron- implanted MOS structures after gamma irradiation

    CERN Document Server

    Kaschieva, S; Skorupa, W

    2003-01-01

    The effect of gamma irradiation on the interface states of ion-implanted MOS structures is studied by means of the thermally stimulated charge method. 10-keV oxygen- or boron- (O sup + or B sup +) implanted samples are gamma-irradiated with sup 6 sup 0 Co. Gamma irradiation creates electron levels at the SiSiO sub 2 interface of the samples in a different way depending on the type of the previously implanted atoms (O sup + or B sup +). The results demonstrate that the concentration of the shallower levels (in the silicon band gap) of oxygen-implanted samples increases more effectively after gamma irradiation. The same irradiation conditions increase more intensively the concentration of the deeper levels (in the silicon band gap) of boron-implanted samples. (orig.)

  17. A novel technique to measure interface trap density in a GaAs MOS capacitor using time-varying magnetic fields

    Energy Technology Data Exchange (ETDEWEB)

    Choudhury, Aditya N. Roy, E-mail: aditya@physics.iisc.ernet.in; Venkataraman, V. [Dept. of Physics, Indian Institute of Science, Bangalore – 560012 (India)

    2016-05-23

    Interface trap density (D{sub it}) in a GaAs metal-oxide-semiconductor (MOS) capacitor can be measured electrically by measuring its impedance, i.e. by exciting it with a small signal voltage source and measuring the resulting current through the circuit. We propose a new method of measuring D{sub it} where the MOS capacitor is subjected to a (time-varying) magnetic field instead, which produces an effect equivalent to a (time-varying) voltage drop across the sample. This happens because the electron chemical potential of GaAs changes with a change in an externally applied magnetic field (unlike that of the gate metal); this is not the voltage induced by Faraday’s law of electromagnetic induction. So, by measuring the current through the MOS, D{sub it} can be found similarly. Energy band diagrams and equivalent circuits of a MOS capacitor are drawn in the presence of a magnetic field, and analyzed. The way in which a magnetic field affects a MOS structure is shown to be fundamentally different compared to an electrical voltage source.

  18. On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs

    Directory of Open Access Journals (Sweden)

    Muhammad Nawaz

    2015-01-01

    Full Text Available This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2 as a gate dielectric for 4H-SiC MOSFETs, high-k gate dielectric such as HfO2 reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High-k gate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2 (k=3.9 to HfO2 (k=25. This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2 to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2 as gate dielectric than high-k dielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.

  19. Trap-mediated electronic transport properties of gate-tunable pentacene/MoS2 p-n heterojunction diodes.

    Science.gov (United States)

    Kim, Jae-Keun; Cho, Kyungjune; Kim, Tae-Young; Pak, Jinsu; Jang, Jingon; Song, Younggul; Kim, Youngrok; Choi, Barbara Yuri; Chung, Seungjun; Hong, Woong-Ki; Lee, Takhee

    2016-11-10

    We investigated the trap-mediated electronic transport properties of pentacene/molybdenum disulphide (MoS 2 ) p-n heterojunction devices. We observed that the hybrid p-n heterojunctions were gate-tunable and were strongly affected by trap-assisted tunnelling through the van der Waals gap at the heterojunction interfaces between MoS 2 and pentacene. The pentacene/MoS 2 p-n heterojunction diodes had gate-tunable high ideality factor, which resulted from trap-mediated conduction nature of devices. From the temperature-variable current-voltage measurement, a space-charge-limited conduction and a variable range hopping conduction at a low temperature were suggested as the gate-tunable charge transport characteristics of these hybrid p-n heterojunctions. Our study provides a better understanding of the trap-mediated electronic transport properties in organic/2-dimensional material hybrid heterojunction devices.

  20. Silicon based ultrafast optical waveform sampling

    DEFF Research Database (Denmark)

    Ji, Hua; Galili, Michael; Pu, Minhao

    2010-01-01

    A 300 nmx450 nmx5 mm silicon nanowire is designed and fabricated for a four wave mixing based non-linear optical gate. Based on this silicon nanowire, an ultra-fast optical sampling system is successfully demonstrated using a free-running fiber laser with a carbon nanotube-based mode-locker as th......A 300 nmx450 nmx5 mm silicon nanowire is designed and fabricated for a four wave mixing based non-linear optical gate. Based on this silicon nanowire, an ultra-fast optical sampling system is successfully demonstrated using a free-running fiber laser with a carbon nanotube-based mode......-locker as the sampling source. A clear eye-diagram of a 320 Gbit/s data signal is obtained. The temporal resolution of the sampling system is estimated to 360 fs....

  1. Target Capture during Mos1 Transposition*

    Science.gov (United States)

    Pflieger, Aude; Jaillet, Jerôme; Petit, Agnès; Augé-Gouillou, Corinne; Renault, Sylvaine

    2014-01-01

    DNA transposition contributes to genomic plasticity. Target capture is a key step in the transposition process, because it contributes to the selection of new insertion sites. Nothing or little is known about how eukaryotic mariner DNA transposons trigger this step. In the case of Mos1, biochemistry and crystallography have deciphered several inverted terminal repeat-transposase complexes that are intermediates during transposition. However, the target capture complex is still unknown. Here, we show that the preintegration complex (i.e., the excised transposon) is the only complex able to capture a target DNA. Mos1 transposase does not support target commitment, which has been proposed to explain Mos1 random genomic integrations within host genomes. We demonstrate that the TA dinucleotide used as the target is crucial both to target recognition and in the chemistry of the strand transfer reaction. Bent DNA molecules are better targets for the capture when the target DNA is nicked two nucleotides apart from the TA. They improve strand transfer when the target DNA contains a mismatch near the TA dinucleotide. PMID:24269942

  2. High-performance silicon nanotube tunneling FET for ultralow-power logic applications

    KAUST Repository

    Fahad, Hossain M.; Hussain, Muhammad Mustafa

    2013-01-01

    To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.

  3. High-performance silicon nanotube tunneling FET for ultralow-power logic applications

    KAUST Repository

    Fahad, Hossain M.

    2013-03-01

    To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET\\'s effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.

  4. Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition

    Science.gov (United States)

    Kelly, David Quest

    After the integrated circuit was invented in 1959, complementary metal-oxide-semiconductor (CMOS) technology soon became the mainstay of the semiconductor industry. Silicon-based CMOS has dominated logic technologies for decades. During this time, chip performance has grown at an exponential rate at the cost of higher power consumption and increased process complexity. The performance gains have been made possible through scaling down circuit dimensions by improvements in lithography capabilities. Since scaling cannot continue forever, researchers have vigorously pursued new ways of improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) without having to shrink gate lengths and reduce the gate insulator thickness. Strained silicon, with its ability to boost transistor current by improving the channel mobility, is one of the methods that has already found its way into production. Although not yet in production, high-kappa dielectrics have also drawn wide interest in industry since they allow for the reduction of the electrical oxide thickness of the gate stack without having to reduce the physical thickness of the dielectric. Further out on the horizon is the incorporation of high-mobility materials such as germanium (Ge), silicon-germanium (Si1-xGe x), and the III-V semiconductors. Among the high-mobility materials, Ge has drawn the most attention because it has been shown to be compatible with high-kappa dielectrics and to produce high drive currents compared to Si. Among the most difficult challenges for integrating Ge on Si is finding a suitable method for reducing the number of crystal defects. The use of strain-relaxed Si1- xGex buffers has proven successful for reducing the threading dislocation density in Ge epitaxial layers, but questions remain as to the viability of this method in terms of cost and process complexity. This dissertation presents research on thin germanium-carbon (Ge 1-yCy layers on Si for the fabrication

  5. Quantum gate decomposition algorithms.

    Energy Technology Data Exchange (ETDEWEB)

    Slepoy, Alexander

    2006-07-01

    Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

  6. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    Science.gov (United States)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  7. Faceted MoS2 nanotubes and nanoflowers

    International Nuclear Information System (INIS)

    Deepak, Francis Leonard; Mayoral, Alvaro; Yacaman, Miguel Jose

    2009-01-01

    A simple synthesis of novel faceted MoS 2 nanotubes (NTs) and nanoflowers (NFs) starting from molybdenum oxide and thiourea as the sulphur source is reported. The MoS 2 nanotubes with the faceted morphology have not been observed before. Further the as-synthesized MoS 2 nanotubes have high internal surface area. The nanostructures have been characterized by a variety of electron microscopy techniques. It is expected that these MoS 2 nanostrutures will find important applications in energy storage, catalysis and field emission.

  8. Tunnel field-effect transistor with two gated intrinsic regions

    Directory of Open Access Journals (Sweden)

    Y. Zhang

    2014-07-01

    Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.

  9. Silicon detectors

    International Nuclear Information System (INIS)

    Klanner, R.

    1984-08-01

    The status and recent progress of silicon detectors for high energy physics is reviewed. Emphasis is put on detectors with high spatial resolution and the use of silicon detectors in calorimeters. (orig.)

  10. Hybrid van der Waals p-n Heterojunctions based on SnO and 2D MoS2

    KAUST Repository

    Wang, Zhenwei

    2016-08-30

    A p-type oxide/2D hybrid van der Waals p-n heterojunction is demonstrated for the first time between SnO (tin monoxide) (the p-type oxide) and 2D MoS2 (molybdenum disulfide), showing an ideality factor of 2 and rectification ratio up to 10(4) . The reported heterojunction is gate-tunable with typical anti-ambipolar transfer characteristics. Surface potential mapping is performed and a current model for such a heterojunction is proposed.

  11. Magnetoresistance in Co/2D MoS2/Co and Ni/2D MoS2/Ni junctions.

    Science.gov (United States)

    Zhang, Han; Ye, Meng; Wang, Yangyang; Quhe, Ruge; Pan, Yuanyuan; Guo, Ying; Song, Zhigang; Yang, Jinbo; Guo, Wanlin; Lu, Jing

    2016-06-28

    Semiconducting single-layer (SL) and few-layer MoS2 have a flat surface, free of dangling bonds. Using density functional theory coupled with non-equilibrium Green's function method, we investigate the spin-polarized transport properties of Co/2D MoS2/Co and Ni/2D MoS2/Ni junctions with MoS2 layer numbers of N = 1, 3, and 5. Well-defined interfaces are formed between MoS2 and metal electrodes. The junctions with a SL MoS2 spacer are almost metallic owing to the strong coupling between MoS2 and the ferromagnets, while those are tunneling with a few layer MoS2 spacer. Both large magnetoresistance and tunneling magnetoresistance are found when fcc or hcp Co is used as an electrode. Therefore, flat single- and few-layer MoS2 can serve as an effective nonmagnetic spacer in a magnetoresistance or tunneling magnetoresistance device with a well-defined interface.

  12. Electron Excess Doping and Effective Schottky Barrier Reduction on the MoS2/h-BN Heterostructure.

    Science.gov (United States)

    Joo, Min-Kyu; Moon, Byoung Hee; Ji, Hyunjin; Han, Gang Hee; Kim, Hyun; Lee, Gwanmu; Lim, Seong Chu; Suh, Dongseok; Lee, Young Hee

    2016-10-12

    Layered hexagonal boron nitride (h-BN) thin film is a dielectric that surpasses carrier mobility by reducing charge scattering with silicon oxide in diverse electronics formed with graphene and transition metal dichalcogenides. However, the h-BN effect on electron doping concentration and Schottky barrier is little known. Here, we report that use of h-BN thin film as a substrate for monolayer MoS 2 can induce ∼6.5 × 10 11 cm -2 electron doping at room temperature which was determined using theoretical flat band model and interface trap density. The saturated excess electron concentration of MoS 2 on h-BN was found to be ∼5 × 10 13 cm -2 at high temperature and was significantly reduced at low temperature. Further, the inserted h-BN enables us to reduce the Coulombic charge scattering in MoS 2 /h-BN and lower the effective Schottky barrier height by a factor of 3, which gives rise to four times enhanced the field-effect carrier mobility and an emergence of metal-insulator transition at a much lower charge density of ∼1.0 × 10 12 cm -2 (T = 25 K). The reduced effective Schottky barrier height in MoS 2 /h-BN is attributed to the decreased effective work function of MoS 2 arisen from h-BN induced n-doping and the reduced effective metal work function due to dipole moments originated from fixed charges in SiO 2 .

  13. Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

    Science.gov (United States)

    Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

    2007-09-01

    Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

  14. Low-frequency noise in multilayer MoS2 field-effect transistors: the effect of high-k passivation.

    Science.gov (United States)

    Na, Junhong; Joo, Min-Kyu; Shin, Minju; Huh, Junghwan; Kim, Jae-Sung; Piao, Mingxing; Jin, Jun-Eon; Jang, Ho-Kyun; Choi, Hyung Jong; Shim, Joon Hyung; Kim, Gyu-Tae

    2014-01-07

    Diagnosing of the interface quality and the interactions between insulators and semiconductors is significant to achieve the high performance of nanodevices. Herein, low-frequency noise (LFN) in mechanically exfoliated multilayer molybdenum disulfide (MoS2) (~11.3 nm-thick) field-effect transistors with back-gate control was characterized with and without an Al2O3 high-k passivation layer. The carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface nicely described the noise behavior in the strong accumulation regime both with and without the Al2O3 passivation layer. The interface trap density at the MoS2-SiO2 interface was extracted from the LFN analysis, and estimated to be Nit ~ 10(10) eV(-1) cm(-2) without and with the passivation layer. This suggested that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model implying the bulk conduction was found to describe the drain current fluctuations in the subthreshold regime, which is rarely observed in other nanodevices, attributed to those extremely thin channel sizes. In the case of the thick-MoS2 (~40 nm-thick) without the passivation, the HMF model was clearly observed all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS2. With the Al2O3 passivation layer, the change in the noise behavior was explained from the point of formation of the additional top channel in the MoS2 because of the fixed charges in the Al2O3. The interface trap density from the additional CNF model was Nit = 1.8 × 10(12) eV(-1) cm(-2) at the MoS2-Al2O3 interface.

  15. Signatures of Mechanosensitive Gating.

    Science.gov (United States)

    Morris, Richard G

    2017-01-10

    The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

  16. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2013-01-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  17. Tin (Sn) for enhancing performance in silicon CMOS

    KAUST Repository

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  18. Gated field-emitter cathodes for high-power microwave applications

    International Nuclear Information System (INIS)

    Barasch, E.F.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.; McIntyre, P.M.; Pang, Y.; Smith, D.D.; Trost, H.J.

    1992-01-01

    Gated field-emitter cathodes have been fabricated on silicon wafers. Two fabrication approaches have been employed: a knife-edge array and a porous silicon structure. The knife-edge array consists of a pattern of knife-edges, sharpened to ∼200 A radius, configured with an insulated metal gate structure at a gap of ∼500 A. The porous silicon cathode consists of an insulating porous layer, containing pores of ∼50 A diameter, densely spaced in the native silicon, biased for field emission by a thin gate metallization on the surface. Emission current density of 20 A/cm 2 has been obtained with only 10 V bias. Fabrication processes and test results are presented. (Author) 4 figs., tab., 12 refs

  19. Floating Gate CMOS Dosimeter With Frequency Output

    Science.gov (United States)

    Garcia-Moreno, E.; Isern, E.; Roca, M.; Picos, R.; Font, J.; Cesari, J.; Pineda, A.

    2012-04-01

    This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

  20. Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

    Science.gov (United States)

    Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

    2018-09-01

    In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

  1. Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

    Science.gov (United States)

    Brucker, G. J.; Van Gunten, O.; Stassinopoulos, E. G.; Shapiro, P.; August, L. S.; Jordan, T. M.

    1983-01-01

    This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

  2. Power mos devices: structures and modelling procedures

    Energy Technology Data Exchange (ETDEWEB)

    Rossel, P.; Charitat, G.; Tranduc, H.; Morancho, F.; Moncoqut

    1997-05-01

    In this survey, the historical evolution of power MOS transistor structures is presented and currently used devices are described. General considerations on current and voltage capabilities are discussed and configurations of popular structures are given. A synthesis of different modelling approaches proposed last three years is then presented, including analytical solutions, for basic electrical parameters such as threshold voltage, on-resistance, saturation and quasi-saturation effects, temperature influence and voltage handling capability. The numerical solutions of basic semiconductor devices is then briefly reviewed along with some typical problems which can be solved this way. A compact circuit modelling method is finally explained with emphasis on dynamic behavior modelling

  3. Transistors using crystalline silicon devices on glass

    Science.gov (United States)

    McCarthy, Anthony M.

    1995-01-01

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

  4. Operation mode switchable charge-trap memory based on few-layer MoS2

    Science.gov (United States)

    Hou, Xiang; Yan, Xiao; Liu, Chunsen; Ding, Shijin; Zhang, David Wei; Zhou, Peng

    2018-03-01

    Ultrathin layered two-dimensional (2D) semiconductors like MoS2 and WSe2 have received a lot of attention because of their excellent electrical properties and potential applications in electronic devices. We demonstrate a charge-trap memory with two different tunable operation modes based on a few-layer MoS2 channel and an Al2O3/HfO2/Al2O3 charge storage stack. Our device shows excellent memory properties under the traditional three-terminal operation mode. More importantly, unlike conventional charge-trap devices, this device can also realize the memory performance with just two terminals (drain and source) because of the unique atomic crystal electrical characteristics. Under the two-terminal operation mode, the erase/program current ratio can reach up to 104 with a stable retention property. Our study indicates that the conventional charge-trap memory cell can also realize the memory performance without the gate terminal based on novel two dimensional materials, which is meaningful for low power consumption and high integration density applications.

  5. Two-axis control of a coupled quantum dot - donor qubit in Si-MOS

    Science.gov (United States)

    Rudolph, Martin; Harvey-Collard, Patrick; Jacobson, Tobias; Wendt, Joel; Pluym, Tammy; Dominguez, Jason; Ten-Eyck, Greg; Lilly, Mike; Carroll, Malcolm

    Si-MOS based QD qubits are attractive due to their similarity to the current semiconductor industry. We introduce a highly tunable MOS foundry compatible qubit design that couples an electrostatic quantum dot (QD) with an implanted donor. We show for the first time coherent two-axis control of a two-electron spin logical qubit that evolves under the QD-donor exchange interaction and the hyperfine interaction with the donor nucleus. The two interactions are tuned electrically with surface gate voltages to provide control of both qubit axes. Qubit decoherence is influenced by charge noise, which is of similar strength as epitaxial systems like GaAs and Si/SiGe. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. The work was supported by the Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  6. The infra-red photoresponse of erbium-doped silicon nanocrystals

    International Nuclear Information System (INIS)

    Kenyon, A.J.; Bhamber, S.S.; Pitt, C.W.

    2003-01-01

    We have exploited the interaction between erbium ions and silicon nanoclusters to probe the photoresponse of erbium-doped silicon nanocrystals in the spectral region around 1.5 μm. We have produced an MOS device in which the oxide layer has been implanted with both erbium and silicon and annealed to produce silicon nanocrystals. Upon illumination with a 1480 nm laser diode, interaction between the nanocrystals and the rare-earth ions results in a modification of the conductivity of the oxide that enables a current to flow when a voltage is applied across the oxide layer

  7. Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

    Science.gov (United States)

    Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

    2018-05-01

    The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

  8. Enhanced interfacial and electrical characteristics of 4H-SiC MOS capacitor with lanthanum silicate passivation interlayer

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Qian [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system & Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050 (China); University of Chinese Academy of Sciences, Beijing 100049 (China); Cheng, Xinhong, E-mail: xh_cheng@mail.sim.ac.cn [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system & Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050 (China); Zheng, Li, E-mail: zhengli@mail.sim.ac.cn [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system & Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050 (China); University of Chinese Academy of Sciences, Beijing 100049 (China); Ye, Peiyi; Li, Menglu [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Shen, Lingyan; Li, Jingjie; Zhang, Dongliang; Gu, Ziyue [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system & Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050 (China); University of Chinese Academy of Sciences, Beijing 100049 (China); Yu, Yuehui [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system & Information Technology, Chinese Academy of Sciences, Changning Road 865, Shanghai 200050 (China)

    2017-07-15

    Highlights: • The 4H-SiC MOS capacitor with an untra-thin LaSiO{sub x} passivation layer and Al{sub 2}O{sub 3} gate dielectric was fabricated. • The detrimental SiO{sub x} interfacial layer could be effectively restrained by the LaSiO{sub x} passivation layer. • The passivation mechanism of LaSiO{sub x} was analyzed by HRTEM, XPS and electrical measurements. • The 4H-SiC MOS capacitor with a LaSiO{sub x} passivation layer shows excellent device characteristics. • This technique provides an efficient path to improve dielectrics/4H-SiC interfaces for future high-power device applications. - Abstract: The detrimental sub-oxide (SiO{sub x}) interfacial layer formed during the 4H-SiC metal-oxide-semiconductor (MOS) capacitor fabrication will drastically damage its device performance. In this work, an ultrathin lanthanum silicate (LaSiO{sub x}) passivation layer was introduced to enhance the interfacial and electrical characteristics of 4H-SiC MOS capacitor with Al{sub 2}O{sub 3} gate dielectric. The interfacial LaSiO{sub x} formation was investigated by high resolution transmission electron microscopy and X-ray photoelectron spectroscopy. The 4H-SiC MOS capacitor with ultrathin LaSiO{sub x} passivation interlayer shows excellent interfacial and electrical characteristics, including lower leakage current density, higher dielectric breakdown electric field, smaller C–V hysteresis, and lower interface states density and border traps density. The involved mechanism implies that the LaSiO{sub x} passivation interlayer can effectively restrain SiO{sub x} formation and improve the Al{sub 2}O{sub 3}/4H-SiC interface quality. This technique provides an efficient path to improve dielectrics/4H-SiC interfaces for future high-power device applications.

  9. Optical XOR gate

    Science.gov (United States)

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  10. A 77 K MOS magnetic field detector

    Energy Technology Data Exchange (ETDEWEB)

    Murphy, R S; Torres, A. [Instituto Nacional de Astrofisica Optica y Electronica, Puebla (Mexico); Garcia, P.J. [Universidad Veracruzana, Veracruz (Mexico); Gutierrez, E.A. [Motorola, Puebla (Mexico)

    2001-12-01

    An integrated MOS (metal-oxide-semiconductor)-compatible magnetic field detector (split-drain MAGFET) for operation at liquid-nitrogen temperature LNT (77 K) is presented. The measured relative magnetic sensibility (S{sub a}) is approximately 14%/T (double the value ever reported) using a non-optimized MAGFET structure (W/L) = (100 mm/125 mm). The cryo-magnetic structure was tested without a built-in preamplifier. It presents a power consumption of the order of mW. [Spanish] A traves de este articulo se presenta un detector de campo magnetico (split-drain MAGFET), basado en el transistor de efecto de campo MOS (metal-oxido-semiconductor), y totalmente compatible con procesos de fabricacion de circuitos integrados CMOS. La operacion optima de este detector es a temperaturas criogenicas. Aqui se presentan los resultados experimentales de la caracterizacion de una estructura no optimizada con dimensiones (W / L) = (100 mm/125 mm) a la temperatura del nitrogeno liquido (77 K). La sensibilidad relativa medida es de cerca del 14 % T, casi el doble del valor maximo antes reportado en la literatura. El dispositivo se midio sin un pre-amplificador integrado, mostrando un consumo de potencia del orden de microwatts.

  11. Développement de résonateurs électromécaniques en technologie Silicon On Nothing, à détection capacitive et amplifiée par transistor MOS, en vue d'une co-intégration permettant d'adresser une application de référence de temps

    OpenAIRE

    Durand , Cédric

    2009-01-01

    Due to good performances, small size, or either integration possibilities very close to transistors, electromechanical resonators offer a strong potential for quartz replacement in time reference applications.In this context, we propose to develop electromechanical resonators in a perspective of a front-end integration, for the realization of integrated oscillators. The fabricated demonstrators are based on the Silicon On Nothing CMOS technology, under R&D at STMicroelectronics. Due to the sm...

  12. Equivalent distributed capacitance model of oxide traps on frequency dispersion of C-V curve for MOS capacitors

    Science.gov (United States)

    Lu, Han-Han; Xu, Jing-Ping; Liu, Lu; Lai, Pui-To; Tang, Wing-Man

    2016-11-01

    An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C-V curve of MOS capacitors measured for a frequency range from 1 kHz to 1 MHz. The proposed model is based on the Fermi-Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal. The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data. Simulations indicate that the capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface, with negligible effects from the traps far from the interface, and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed. In addition, by excluding the negligible effect of oxide-trap conductance, the model avoids the use of imaginary numbers and complex calculations, and thus is simple and intuitive. Project supported by the National Natural Science Foundation of China (Grant Nos. 61176100 and 61274112), the University Development Fund of the University of Hong Kong, China (Grant No. 00600009), and the Hong Kong Polytechnic University, China (Grant No. 1-ZVB1).

  13. Equivalent distributed capacitance model of oxide traps on frequency dispersion of C – V curve for MOS capacitors

    International Nuclear Information System (INIS)

    Lu Han-Han; Xu Jing-Ping; Liu Lu; Lai Pui-To; Tang Wing-Man

    2016-01-01

    An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C – V curve of MOS capacitors measured for a frequency range from 1 kHz to 1 MHz. The proposed model is based on the Fermi–Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal. The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data. Simulations indicate that the capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface, with negligible effects from the traps far from the interface, and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed. In addition, by excluding the negligible effect of oxide-trap conductance, the model avoids the use of imaginary numbers and complex calculations, and thus is simple and intuitive. (paper)

  14. Laser-assisted electron emission from gated field-emitters

    CERN Document Server

    Ishizuka, H; Yokoo, K; Mimura, H; Shimawaki, H; Hosono, A

    2002-01-01

    Enhancement of electron emission by illumination of gated field-emitters was studied using a 100 mW cw YAG laser at a wavelength of 532 nm, intensities up to 10 sup 7 W/m sup 2 and mechanically chopped with a rise time of 4 mu s. When shining an array of 640 silicon emitters, the emission current responded quickly to on-off of the laser. The increase of the emission current was proportional to the basic emission current at low gate voltages, but it was saturated at approx 3 mu A as the basic current approached 100 mu A with the increase of gate voltage. The emission increase was proportional to the square root of laser power at low gate voltages and to the laser power at elevated gate voltages. For 1- and 3-tip silicon emitters, the rise and fall of the current due to on-off of the laser showed a significant time lag. The magnitude of emission increase was independent of the position of laser spot on the emitter base and reached 2 mu A at a basic current of 5 mu A without showing signs of saturation. The mech...

  15. Gate Tunable Transport in Graphene/MoS2/(Cr/Au Vertical Field-Effect Transistors

    Directory of Open Access Journals (Sweden)

    Ghazanfar Nazir

    2017-12-01

    Full Text Available Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS2/(Cr/Au vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr, the electrical transport in our Gr/MoS2/(Cr/Au vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS2 can be modified by back-gate voltage and the current bias. Vertical resistance (Rvert of a Gr/MoS2/(Cr/Au transistor is compared with planar resistance (Rplanar of a conventional lateral MoS2 field-effect transistor. We have also studied electrical properties for various thicknesses of MoS2 channels in both vertical and lateral transistors. As the thickness of MoS2 increases, Rvert increases, but Rplanar decreases. The increase of Rvert in the thicker MoS2 film is attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

  16. An analysis of radiation effects on electronics and soi-mos devices as an alternative

    International Nuclear Information System (INIS)

    Ikraiam, F. A.

    2013-01-01

    The effects of radiation on semiconductors and electronic components are analyzed. The performance of such circuitry depends upon the reliability of electronic devices where electronic components will be unavoidably exposed to radiation. This exposure can be detrimental or even fatal to the expected function of the devices. Single event effects (SEE), in particular, which lead to sudden device or system failure and total dose effects can reduce the lifetime of electronic devices in such systems are discussed. Silicon-on-insulator (SOI) technology is introduced as an alternative for radiation-hardened devices. I-V Characteristics Curves for SOI-MOS devices subjected to a different total radiation doses are illustrated. In addition, properties of some semiconductor materials such as diamond, diamond-like carbon films, SiC, GaP, and AlGaN/GaN are compared with those of SOI devices. The recognition of the potential usefulness of SOI-MOS semiconductor materials for harsh environments is discussed. A summary of radiation effects, impacts and mitigation techniques is also presented. (authors)

  17. Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate (GCDMDG) MOSFETs

    Science.gov (United States)

    Goel, Ekta; Kumar, Sanjay; Singh, Balraj; Singh, Kunal; Jit, Satyabrata

    2017-06-01

    The subthreshold performance of graded-channel dual-material double-gate (GCDMDG) MOSFETs is examined through two-dimensional (2D) analytical modeling of subthreshold-current (SC) and subthreshold-swing (SS). The potential function obtained by using the parabolic approach to solve the 2D Poisson's equation, has been used to formulate SC and SS characteristics of the device. The variations of SS against different device parameters have been obtained with the help of effective conduction path parameter. The SC and SS characteristics of the GCDMDG MOS transistor have been compared with those of the dual-material double-gate (DMDG) and simple graded-channel double-gate (GCDG) MOS structures to show its better subthreshold characteristics over the latter two devices. The results of the developed model are well-agreed with the commercially available SILVACO ATLAS™ simulator data.

  18. Three-dimensional vertical Si nanowire MOS capacitor model structure for the study of electrical versus geometrical Si nanowire characteristics

    Science.gov (United States)

    Hourdakis, E.; Casanova, A.; Larrieu, G.; Nassiopoulou, A. G.

    2018-05-01

    Three-dimensional (3D) Si surface nanostructuring is interesting towards increasing the capacitance density of a metal-oxidesemiconductor (MOS) capacitor, while keeping reduced footprint for miniaturization. Si nanowires (SiNWs) can be used in this respect. With the aim of understanding the electrical versus geometrical characteristics of such capacitors, we fabricated and studied a MOS capacitor with highly ordered arrays of vertical Si nanowires of different lengths and thermal silicon oxide dielectric, in comparison to similar flat MOS capacitors. The high homogeneity and ordering of the SiNWs allowed the determination of the single SiNW capacitance and intrinsic series resistance, as well as other electrical characteristics (density of interface states, flat-band voltage and leakage current) in relation to the geometrical characteristics of the SiNWs. The SiNW capacitors demonstrated increased capacitance density compared to the flat case, while maintaining a cutoff frequency above 1 MHz, much higher than in other reports in the literature. Finally, our model system has been shown to constitute an excellent platform for the study of SiNW capacitors with either grown or deposited dielectrics, as for example high-k dielectrics for further increasing the capacitance density. This will be the subject of future work.

  19. DC modeling of composite MOS transistors

    NARCIS (Netherlands)

    de Haan, P.; de Haan, P.E.; Klumperink, Eric A.M.; van Leeuwen, M.G.; Wallinga, Hans

    1995-01-01

    Mixed-signal circuit design on sea-of-gates arrays requires the use of composite MOSTs, combinations of in-series and in-parallel connected unit MOSTs. To avoid an increase in circuit simulation complexity these are in general replaced by artificial single MOSTs. The analysis in this paper shows

  20. Bubble gate for in-plane flow control.

    Science.gov (United States)

    Oskooei, Ali; Abolhasani, Milad; Günther, Axel

    2013-07-07

    We introduce a miniature gate valve as a readily implementable strategy for actively controlling the flow of liquids on-chip, within a footprint of less than one square millimetre. Bubble gates provide for simple, consistent and scalable control of liquid flow in microchannel networks, are compatible with different bulk microfabrication processes and substrate materials, and require neither electrodes nor moving parts. A bubble gate consists of two microchannel sections: a liquid-filled channel and a gas channel that intercepts the liquid channel to form a T-junction. The open or closed state of a bubble gate is determined by selecting between two distinct gas pressure levels: the lower level corresponds to the "open" state while the higher level corresponds to the "closed" state. During closure, a gas bubble penetrates from the gas channel into the liquid, flanked by a column of equidistantly spaced micropillars on each side, until the flow of liquid is completely obstructed. We fabricated bubble gates using single-layer soft lithographic and bulk silicon micromachining procedures and evaluated their performance with a combination of theory and experimentation. We assessed the dynamic behaviour during more than 300 open-and-close cycles and report the operating pressure envelope for different bubble gate configurations and for the working fluids: de-ionized water, ethanol and a biological buffer. We obtained excellent agreement between the experimentally determined bubble gate operational envelope and a theoretical prediction based on static wetting behaviour. We report case studies that serve to illustrate the utility of bubble gates for liquid sampling in single and multi-layer microfluidic devices. Scalability of our strategy was demonstrated by simultaneously addressing 128 bubble gates.

  1. Breakdown properties of irradiated MOS capacitors

    International Nuclear Information System (INIS)

    Paccagnella, A.; Candelori, A.; Pellizzer, F.; Fuochi, P.G.; Lavale, M.

    1996-01-01

    The authors have studied the effects of ionizing and non-ionizing radiation on the breakdown properties of different types of MOS capacitors, with thick (200 nm) and thin (down to 8 nm) oxides. In general, no large variations of the average breakdown field, time-to-breakdown at constant voltage, or charge-to-breakdown at constant voltage, or charge-to-breakdown values have been observed after high dose irradiation (20 Mrad(Si) 9 MeV electrons on thin and thick oxides, 17(Si) Mrad Co 60 gamma and 10 14 neutrons/cm 2 only on thick oxides). However, some modifications of the cumulative failure distributions have been observed in few of the oxides tested

  2. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  3. Interface properties of 4H-SiC MOS structures studied by a slow positron beam

    International Nuclear Information System (INIS)

    Maekawa, M.; Kawasuso, A.; Ichimiya, A.; Yoshikawa, M.

    2004-01-01

    Interfacial defects existing near the SiO 2 /SiC interface are an important issue for fabrication of high performance SiC devices. We investigate a thermally grown SiO 2 /SiC layer of 4H-SiC MOS structure by positron annihilation spectroscopy. The Doppler broadening of annihilation quanta was measured as a function of the incident positron energy and the gate bias. Applying a negative gate bias, significant increases in S-parameters were observed. This indicates the migration of implanted positrons towards the SiO 2 /SiC interface and annihilation at interfacial defects. Ultraviolet (UV) ray irradiation was used to extract the influence of the positron trapping to the interfacial states. S-parameters in the interface region were reduced by UV irradiation. This shows that positron trapping probability decreased because the charge state of interfacial defects changed to positive. From the recovery of S-parameters after 24 hours, the interfacial states discharge slowly and exist in large quantities, because the changes of S-parameter by the UV irradiation are larger than changes induced by bias change. (orig.)

  4. Transport spectroscopy and modeling of a clean MOS point contact tunnel barrier

    Science.gov (United States)

    Shirkhorshidian, Amir; Bishop, Nathaniel; Dominguez, Jason; Grubbs, Robert; Wendt, Joel; Lilly, Michael; Carroll, Malcolm

    2014-03-01

    We present transport spectroscopy of non-implanted and antimony-implanted tunnel barriers formed in MOS split-gate structures at 4K. The non-implanted barrier shows no signs of resonant behavior while the Sb-implanted barrier shows resonances superimposed on the clean transport. We simulate the transmission through the clean barrier over the entire gate and bias range of the experiment using a phenomenological 1D-tunneling model that includes Fowler-Nordheim tunneling and Schottky barrier lowering to capture effects at high bias. The model is qualitatively similar to experiment when the barrier height has a quadratic dependence in contrast to a linear one, which can be a sign of 2D effects such as confinement perpendicular to the transport direction. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. This work was supported by the Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

  5. On recoverable behavior of PBTI in AlGaN/GaN MOS-HEMT

    Science.gov (United States)

    Acurio, E.; Crupi, F.; Magnone, P.; Trojman, L.; Meneghesso, G.; Iucolano, F.

    2017-06-01

    This experimental study focuses on the positive bias temperature instability (PBTI) in a fully recessed-gate AlGaN/GaN MOS-HEMT. A positive stress voltage to the gate results in positive threshold voltage shift (ΔVth), which is attributed to the trapping of electrons from the GaN layer into the pre-existing oxide traps. The trapping rate exhibits a universal decreasing behavior as a function of the number of filled traps, independently of stress time, stress voltage, stress temperature, and device-to-device variability. The stress-induced ΔVth can be fully recovered by applying a small negative voltage, which causes the electron de-trapping. In the explored time window (between 1 s and thousands of s), the recovery dynamics is well described by the superimposition of two exponential functions associated with two different traps. Both trap time constants are independent of the stress voltage, decrease with temperature and increase with the recovery voltage. The activation energy of the slower trap is 0.93 eV, while the faster trap exhibits an activation energy with a large spread in the range between 0.45 eV and 0.82 eV.

  6. Modulation of the effective work function of a TiN metal gate for NMOS requisition with Al incorporation

    International Nuclear Information System (INIS)

    Han Kai; Ma Xueli; Yang Hong; Wang Wenwu

    2013-01-01

    The effect of Al incorporation on the effective work function (EWF) of TiN metal gate was systematically investigated. Metal—oxide—semiconductor (MOS) capacitors with W/TiN/Al/TiN gate stacks were used to fulfill this purpose. Different thickness ratios of Al to TiN and different post metal annealing (PMA) conditions were employed. Significant shift of work function towards to Si conduction band was observed, which was suitable for NMOS and the magnitude of shift depends on the processing conditions. (semiconductor technology)

  7. Publisher Correction: Tunnelling spectroscopy of gate-induced superconductivity in MoS2

    Science.gov (United States)

    Costanzo, Davide; Zhang, Haijing; Reddy, Bojja Aditya; Berger, Helmuth; Morpurgo, Alberto F.

    2018-06-01

    In the version of this Article originally published, an error during typesetting led to the curve in Fig. 2a being shifted to the right, and the curves in the inset of Fig. 2a being displaced. The figure has now been corrected in all versions of the Article; the original and corrected Fig. 2a are shown below.

  8. Fast and slow border traps in MOS devices

    International Nuclear Information System (INIS)

    Fleetwood, D.M.

    1996-01-01

    Convergent lines of evidence are reviewed which show that near-interfacial oxide traps (border traps) that exchange charge with the Si can strongly affect the performance, radiation response, and long-term reliability of MOS devices. Observable effects of border traps include capacitance-voltage (C-V) hysteresis, enhanced l/f noise, compensation of trapped holes, and increased thermally stimulated current in MOS capacitors. Effects of faster (switching times between ∼10 -6 s and ∼1 s) and slower (switching times greater than ∼1 s) border traps have been resolved via a dual-transistor technique. In conjunction with studies of MOS electrical response, electron paramagnetic resonance and spin dependent recombination studies suggest that E' defects (trivalent Si centers in SiO 2 associated with O vacancies) can function as border traps in MOS devices exposed to ionizing radiation or high-field stress. Hydrogen-related centers may also be border traps

  9. Monolayer MoS2 heterojunction solar cells

    KAUST Repository

    Tsai, Menglin

    2014-08-26

    We realized photovoltaic operation in large-scale MoS2 monolayers by the formation of a type-II heterojunction with p-Si. The MoS 2 monolayer introduces a built-in electric field near the interface between MoS2 and p-Si to help photogenerated carrier separation. Such a heterojunction photovoltaic device achieves a power conversion efficiency of 5.23%, which is the highest efficiency among all monolayer transition-metal dichalcogenide-based solar cells. The demonstrated results of monolayer MoS 2/Si-based solar cells hold the promise for integration of 2D materials with commercially available Si-based electronics in highly efficient devices. © 2014 American Chemical Society.

  10. Zirconates heteroepitaxy on silicon

    Science.gov (United States)

    Fompeyrine, Jean; Seo, Jin Won; Seigwart, Heinz; Rossel, Christophe; Locquet, Jean-Pierre

    2002-03-01

    In the coming years, agressive scaling in CMOS technology will probably trigger the transition to more advanced materials, for example alternate gate dielectrics. Epitaxial thin films are attractive candidates, as long as the difficult chemical and structural issues can be solved, and superior properties can be obtained. Since very few binary oxides can match the electrical, physical and structural requirements which are needed, a combination of those binaries are used here to investigate other lattice matched oxides. We will report on the growth of crystalline zirconium oxide thin films stabilized with different cationic substitutions. All films have been grown in an oxide-MBE system by direct evaporation of the elements on silicon substrates and exposure to molecular or atomic oxygen. The conditions required to obtain epitaxial thin films will be discussed, and successful examples will be presented.

  11. Ultrathin MoS2-coated Ag@Si nanosphere arrays as an efficient and stable photocathode for solar-driven hydrogen production.

    Science.gov (United States)

    Zhou, Qingwei; Su, Shaoqiang; Hu, Die; Lin, Lin; Yan, Zhibo; Gao, Xingsen; Zhang, Zhang; Liu, Jun-Ming

    2018-01-30

    Solar-driven photoelectrochemical (PEC) water splitting has attracted a great deal of attention recently. Silicon (Si) is an ideal light absorber for solar energy conversion. However, the poor stability and inefficient surface catalysis of Si photocathodes for the hydrogen evolution reaction (HER) have remained key challenges. Alternatively, MoS 2 has been reported to exhibit excellent catalysis performance if sufficient active sites for the HER are available. Here, ultrathin MoS 2 nanoflakes are directly synthesized to coat arrays of Ag-core Si-shell nanospheres (Ag@Si NSs) by using chemical vapor deposition. Due to the high surface area ratio and large curvature of these NSs, the as-grown MoS 2 nanoflakes can accommodate more active sites. In addition, the high-quality coating of MoS 2 nanoflakes on the Ag@Si NSs protects the photocathode from damage during the PEC reaction. An photocurrent density of 33.3 mA cm -2 at a voltage of -0.4 V is obtained versus the reversible hydrogen electrode. The as-prepared nanostructure as a hydrogen photocathode is evidenced to have high stability over 12 h PEC performance. This work opens up opportunities for composite photocathodes with high activity and stability using cheap and stable co-catalysts.

  12. Ultra-thin MoS2 coated Ag@Si nanosphere arrays as efficient and stable photocathode for solar-driven hydrogen production.

    Science.gov (United States)

    Zhou, Qingwei; Su, Shaoqiang; Hu, Die; Lin, Lin; Yan, Zhibo; Gao, Xingsen; Zhang, Zhang; Liu, Junming

    2018-01-02

    Solar-driven photoelectrochemical (PEC) water splitting has recently attracted much attention. Silicon (Si) is an ideal light absorber for solar energy conversion. However, the poor stability and inefficient surface catalysis of Si photocathode for hydrogen evolution reaction (HER) have been remained as the key challenges. Alternatively, MoS2 has been reported to exhibit the excellent catalysis performance if sufficient active sites for the HER are available. Here, ultra-thin MoS2 nanoflakes are directly synthesized to coat on the arrays of Ag-core Si-shell nanospheres (Ag@Si NSs) using the chemical vapor deposition (CVD). Due to the high surface area ratio and large curvature of these NSs, the as-grown MoS2 nanoflakes can accommodate more active sites. Meanwhile, the high-quality coating of MoS2 nanoflakes on the Ag@Si NSs protects the photocathode from damage during the PEC reaction. A high efficiency with a photocurrent of 33.3 mA cm-2 at a voltage of -0.4 V vs. the reversible hydrogen electrode is obtained. The as-prepared nanostructure as hydrogen photocathode is evidenced to have high stability over 12 hour PEC performance. This work opens opportunities for composite photocathode with high activity and stability using cheap and stable co-catalysts. © 2017 IOP Publishing Ltd.

  13. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    Energy Technology Data Exchange (ETDEWEB)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  14. Regulation of mariner transposition: the peculiar case of Mos1.

    Directory of Open Access Journals (Sweden)

    Jérôme Jaillet

    Full Text Available BACKGROUND: Mariner elements represent the most successful family of autonomous DNA transposons, being present in various plant and animal genomes, including humans. The introduction and co-evolution of mariners within host genomes imply a strict regulation of the transposon activity. Biochemical data accumulated during the past decade have led to a convergent picture of the transposition cycle of mariner elements, suggesting that mariner transposition does not rely on host-specific factors. This model does not account for differences of transposition efficiency in human cells between mariners. We thus wondered whether apparent similarities in transposition cycle could hide differences in the intrinsic parameters that control mariner transposition. PRINCIPAL FINDINGS: We find that Mos1 transposase concentrations in excess to the Mos1 ends prevent the paired-end complex assembly. However, we observe that Mos1 transposition is not impaired by transposase high concentration, dismissing the idea that transposase over production plays an obligatory role in the down-regulation of mariner transposition. Our main finding is that the paired-end complex is formed in a cooperative way, regardless of the transposase concentration. We also show that an element framed by two identical ITRs (Inverted Terminal Repeats is more efficient in driving transposition than an element framed by two different ITRs (i.e. the natural Mos1 copy, the latter being more sensitive to transposase concentration variations. Finally, we show that the current Mos1 ITRs correspond to the ancestral ones. CONCLUSIONS: We provide new insights on intrinsic properties supporting the self-regulation of the Mos1 element. These properties (transposase specific activity, aggregation, ITR sequences, transposase concentration/transposon copy number ratio... could have played a role in the dynamics of host-genomes invasion by Mos1, accounting (at least in part for the current low copy number of

  15. Thermochemical study of MoS2 oxidation

    International Nuclear Information System (INIS)

    Filimonov, D.S.; Topor, N.D.; Kesler, Ya.A.

    1990-01-01

    Thermochemical studies of oxidation processes of metallic molybdenum, sulfur, molybdenum disulfide under different conditions in microcalorimeter are conducted. Values of thermal effects which are used to calculate standard formation enthalpy of MoS 2 and which correlate well are obtained. Δ f H 0 (MoS 2 ,298.15 K) recommended value constitutes (-223.0±16.7) kJ/mol

  16. Annealing, temperature, and bias-induced threshold voltage instabilities in integrated E/D-mode InAlN/GaN MOS HEMTs

    Science.gov (United States)

    Blaho, M.; Gregušová, D.; Haščík, Š.; Ťapajna, M.; Fröhlich, K.; Šatka, A.; Kuzmík, J.

    2017-07-01

    Threshold voltage instabilities are examined in self-aligned E/D-mode n++ GaN/InAlN/GaN MOS HEMTs with a gate length of 2 μm and a source-drain spacing of 10 μm integrated in a logic invertor. The E-mode MOS HEMT technology is based on selective dry etching of the cap layer which is combined with Al2O3 grown by atomic-layer deposition at 380 K. In the D-mode MOS HEMT, the gate recessing is skipped. The nominal threshold voltage (VT) of E/D-mode MOS HEMTs was 0.6 and -3.4 V, respectively; the technology invariant maximal drain current was about 0.45 A/mm. Analysis after 580 K/15 min annealing step and at an elevated temperature up to 430 K reveals opposite device behavior depending on the HEMT operational mode. It was found that the annealing step decreases VT of the D-mode HEMT due to a reduced electron injection into the modified oxide. On the other hand, VT of the E-mode HEMT increases with reduced density of surface donors at the oxide/InAlN interface. Operation at the elevated temperature produces reversible changes: increase/decrease in the VT of the respective D-/E-mode HEMTs. Additional bias-induced experiments exhibit complex trapping phenomena in the devices: Coaction of shallow (˜0.1 eV below EC) traps in the GaN buffer and deep levels at the oxide/InAlN interface was identified for the E-mode device, while trapping in the D-mode HEMTs was found to be consistent with a thermo-ionic injection of electrons into bulk oxide traps (˜0.14 eV above EF) and trapping at the oxide/GaN cap interface states.

  17. MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

    Science.gov (United States)

    Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

    2018-05-21

    The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  18. Carbon nanotube transistors with graphene oxide films as gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

  19. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  20. Cardiac gated ventilation

    International Nuclear Information System (INIS)

    Hanson, C.W. III; Hoffman, E.A.

    1995-01-01

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart

  1. Formation of strain-induced quantum dots in gated semiconductor nanostructures

    Directory of Open Access Journals (Sweden)

    Ted Thorbeck

    2015-08-01

    Full Text Available A long-standing mystery in the field of semiconductor quantum dots (QDs is: Why are there so many unintentional dots (also known as disorder dots which are neither expected nor controllable. It is typically assumed that these unintentional dots are due to charged defects, however the frequency and predictability of the location of the unintentional QDs suggests there might be additional mechanisms causing the unintentional QDs besides charged defects. We show that the typical strains in a semiconductor nanostructure from metal gates are large enough to create strain-induced quantum dots. We simulate a commonly used QD device architecture, metal gates on bulk silicon, and show the formation of strain-induced QDs. The strain-induced QD can be eliminated by replacing the metal gates with poly-silicon gates. Thus strain can be as important as electrostatics to QD device operation operation.

  2. Radiation effects in LDD MOS devices

    International Nuclear Information System (INIS)

    Woodruff, R.L.; Adams, J.R.

    1987-01-01

    The purpose of this work is to investigate the response of lightly doped drain (LDD) n-channel transistors to ionizing radiation. Transistors were fabricated with conventional (non-LDD) and lightly doped drain (LDD) structures using both standard (non-hardened) and radiation hardened gate oxides. Characterization of the transistors began with a correlation of the total-dose effects due to 10 keV x-rays with Co-60 gamma rays. The authors find that for the gate oxides and transistor structures investigated in this work, 10 keV x-rays produce more fixed-charge guild-up in the gate oxide, and more interface charge than do Co-60 gamma rays. They determined that the radiation response of LDD transistors is similar to that of conventional (non-LDD) transistors. In addition, both standard and radiation-hardened transistors subjected to hot carrier stress before irradiation show a similar radiation response. After exposure to 1.0 x 10 6 rads(Si), non-hardened transistors show increased susceptibility to hot-carrier graduation, while the radiation-hardened transistors exhibit similar hot-carrier degradation to non-irradiated devices. The authors have demonstrated a fully-integrated radiation hardened process tht is solid to 1.0 x 10 6 rads(Si), and shows promise for achieving 1.0 x 10 7 rad(Si) total-dose capability

  3. Molecular logic gates: the past, present and future.

    Science.gov (United States)

    Erbas-Cakmak, Sundus; Kolemen, Safacan; Sedgwick, Adam C; Gunnlaugsson, Thorfinnur; James, Tony D; Yoon, Juyoung; Akkaya, Engin U

    2018-04-03

    The field of molecular logic gates originated 25 years ago, when A. P. de Silva published a seminal article in Nature. Stimulated by this ground breaking research, scientists were inspired to join the race to simulate the workings of the fundamental components of integrated circuits using molecules. The rules of this game of mimicry were flexible, and have evolved and morphed over the years. This tutorial review takes a look back on and provides an overview of the birth and growth of the field of molecular logics. Spinning-off from chemosensor research, molecular logic gates quickly proved themselves to be more than intellectual exercises and are now poised for many potential practical applications. The ultimate goal of this vein of research became clearer only recently - to "boldly go where no silicon-based logic gate has gone before" and seek out a new deeper understanding of life inside tissues and cells.

  4. Ultra-fine metal gate operated graphene optical intensity modulator

    Science.gov (United States)

    Kou, Rai; Hori, Yosuke; Tsuchizawa, Tai; Warabi, Kaori; Kobayashi, Yuzuki; Harada, Yuichi; Hibino, Hiroki; Yamamoto, Tsuyoshi; Nakajima, Hirochika; Yamada, Koji

    2016-12-01

    A graphene based top-gate optical modulator on a standard silicon photonic platform is proposed for the future optical telecommunication networks. On the basis of the device simulation, we proposed that an electro-absorption light modulation can be realized by an ultra-narrow metal top-gate electrode (width less than 400 nm) directly located on the top of a silicon wire waveguide. The designed structure also provides excellent features such as carrier doping and waveguide-planarization free fabrication processes. In terms of the fabrication, we established transferring of a CVD-grown mono-layer graphene sheet onto a CMOS compatible silicon photonic sample followed by a 25-nm thick ALD-grown Al2O3 deposition and Source-Gate-Drain electrodes formation. In addition, a pair of low-loss spot-size converter for the input and output area is integrated for the efficient light source coupling. The maximum modulation depth of over 30% (1.2 dB) is observed at a device length of 50 μm, and a metal width of 300 nm. The influence of the initial Fermi energy obtained by experiment on the modulation performance is discussed with simulation results.

  5. Integrated porous-silicon light-emitting diodes: A fabrication process using graded doping profiles

    International Nuclear Information System (INIS)

    Barillaro, G.; Diligenti, A.; Pieri, F.; Fuso, F.; Allegrini, M.

    2001-01-01

    A fabrication process, compatible with an industrial bipolar+complementary metal - oxide - semiconductor (MOS)+diffusion MOS technology, has been developed for the fabrication of efficient porous-silicon-based light-emitting diodes. The electrical contact is fabricated with a double n + /p doping, achieving a high current injection efficiency and thus lower biasing voltages. The anodization is performed as the last step of the process, thus reducing potential incompatibilities with industrial processes. The fabricated devices show yellow-orange electroluminescence, visible with the naked eye in room lighting. A spectral characterization of light emission is presented and briefly discussed. [copyright] 2001 American Institute of Physics

  6. Electronic detection of surface plasmon polaritons by metal-oxide-silicon capacitor

    Directory of Open Access Journals (Sweden)

    Robert E. Peale

    2016-09-01

    Full Text Available An electronic detector of surface plasmon polaritons (SPPs is reported. SPPs optically excited on a metal surface using a prism coupler are detected by using a close-coupled metal-oxide-silicon (MOS capacitor. Incidence-angle dependence is explained by Fresnel transmittance calculations, which also are used to investigate the dependence of photo-response on structure dimensions. Electrodynamic simulations agree with theory and experiment and additionally provide spatial intensity distributions on and off the SPP excitation resonance. Experimental dependence of the photoresponse on substrate carrier type, carrier concentration, and back-contact biasing is qualitatively explained by simple theory of MOS capacitors.

  7. Impact of contact resistance on the electrical properties of MoS2 transistors at practical operating temperatures

    Directory of Open Access Journals (Sweden)

    Filippo Giannazzo

    2017-01-01

    Full Text Available Molybdenum disulphide (MoS2 is currently regarded as a promising material for the next generation of electronic and optoelectronic devices. However, several issues need to be addressed to fully exploit its potential for field effect transistor (FET applications. In this context, the contact resistance, RC, associated with the Schottky barrier between source/drain metals and MoS2 currently represents one of the main limiting factors for suitable device performance. Furthermore, to gain a deeper understanding of MoS2 FETs under practical operating conditions, it is necessary to investigate the temperature dependence of the main electrical parameters, such as the field effect mobility (μ and the threshold voltage (Vth. This paper reports a detailed electrical characterization of back-gated multilayer MoS2 transistors with Ni source/drain contacts at temperatures from T = 298 to 373 K, i.e., the expected range for transistor operation in circuits/systems, considering heating effects due to inefficient power dissipation. From the analysis of the transfer characteristics (ID−VG in the subthreshold regime, the Schottky barrier height (ΦB ≈ 0.18 eV associated with the Ni/MoS2 contact was evaluated. The resulting contact resistance in the on-state (electron accumulation in the channel was also determined and it was found to increase with T as RC proportional to T3.1. The contribution of RC to the extraction of μ and Vth was evaluated, showing a more than 10% underestimation of μ when the effect of RC is neglected, whereas the effect on Vth is less significant. The temperature dependence of μ and Vth was also investigated. A decrease of μ proportional to 1/Tα with α = 1.4 ± 0.3 was found, indicating scattering by optical phonons as the main limiting mechanism for mobility above room temperature. The value of Vth showed a large negative shift (about 6 V increasing the temperature from 298 to 373 K, which was explained in terms of electron

  8. Gate valve performance prediction

    International Nuclear Information System (INIS)

    Harrison, D.H.; Damerell, P.S.; Wang, J.K.; Kalsi, M.S.; Wolfe, K.J.

    1994-01-01

    The Electric Power Research Institute is carrying out a program to improve the performance prediction methods for motor-operated valves. As part of this program, an analytical method to predict the stem thrust required to stroke a gate valve has been developed and has been assessed against data from gate valve tests. The method accounts for the loads applied to the disc by fluid flow and for the detailed mechanical interaction of the stem, disc, guides, and seats. To support development of the method, two separate-effects test programs were carried out. One test program determined friction coefficients for contacts between gate valve parts by using material specimens in controlled environments. The other test program investigated the interaction of the stem, disc, guides, and seat using a special fixture with full-sized gate valve parts. The method has been assessed against flow-loop and in-plant test data. These tests include valve sizes from 3 to 18 in. and cover a considerable range of flow, temperature, and differential pressure. Stem thrust predictions for the method bound measured results. In some cases, the bounding predictions are substantially higher than the stem loads required for valve operation, as a result of the bounding nature of the friction coefficients in the method

  9. Multi-material gate poly-crystalline thin film transistors: Modeling and simulation for an improved gate transport efficiency

    International Nuclear Information System (INIS)

    Sehgal, Amit; Mangla, Tina; Gupta, Mridula; Gupta, R.S.

    2008-01-01

    In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model

  10. Stanford, Duke, Rice,... and Gates?

    Science.gov (United States)

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  11. Optical absorption in silicon layers in the presence of charge inversion/accumulation or ion implantation

    International Nuclear Information System (INIS)

    Alloatti, L.; Lauermann, M.; Koos, C.; Freude, W.; Sürgers, C.; Leuthold, J.

    2013-01-01

    We determine the optical losses in gate-induced charge accumulation/inversion layers at a Si/SiO 2 interface. Comparison between gate-induced charge layers and ion-implanted thin silicon films having an identical sheet resistance shows that optical losses can be significantly lower for gate-induced layers. For a given sheet resistance, holes produce higher optical loss than electrons. Measurements have been performed at λ = 1550 nm

  12. Double optical gating

    Science.gov (United States)

    Gilbertson, Steve

    The observation and control of dynamics in atomic and molecular targets requires the use of laser pulses with duration less than the characteristic timescale of the process which is to be manipulated. For electron dynamics, this time scale is on the order of attoseconds where 1 attosecond = 10 -18 seconds. In order to generate pulses on this time scale, different gating methods have been proposed. The idea is to extract or "gate" a single pulse from an attosecond pulse train and switch off all the other pulses. While previous methods have had some success, they are very difficult to implement and so far very few labs have access to these unique light sources. The purpose of this work is to introduce a new method, called double optical gating (DOG), and to demonstrate its effectiveness at generating high contrast single isolated attosecond pulses from multi-cycle lasers. First, the method is described in detail and is investigated in the spectral domain. The resulting attosecond pulses produced are then temporally characterized through attosecond streaking. A second method of gating, called generalized double optical gating (GDOG), is also introduced. This method allows attosecond pulse generation directly from a carrier-envelope phase un-stabilized laser system for the first time. Next the methods of DOG and GDOG are implemented in attosecond applications like high flux pulses and extreme broadband spectrum generation. Finally, the attosecond pulses themselves are used in experiments. First, an attosecond/femtosecond cross correlation is used for characterization of spatial and temporal properties of femtosecond pulses. Then, an attosecond pump, femtosecond probe experiment is conducted to observe and control electron dynamics in helium for the first time.

  13. Radiation effects on custom MOS devices

    International Nuclear Information System (INIS)

    Harris, R.

    1999-05-01

    This Thesis consists of four chapters: The first is primarily for background information on the effects of radiation on MOS devices and the theory of wafer bonding; the second gives a full discussion of all practical work carried out for manufacture of Field Effect test Capacitors, the third discusses manufacture of vacuum insulator Field Effect Transistors (FET's) and the fourth discusses the testing of these devices. Using a thermally bonded field effect capacitor structure, a vacuum dielectric was studied for use in high radiation environments with a view to manufacturing a CMOS compatible, micro machined transistor. Results are given in the form of high frequency C-V curves before and after a 120 kGy(Si), 12 MRad(Si), dose from a Co 60 source showing a 1 Volt shift. The work is then extended to the design and manufacture of a micro machined, under-etch technique, Field Effect Transistor for use in high radiation areas. Results are shown for Threshold, Subthreshold and Transfer characteristics before and after irradiation up to a total dose of 100kGy or 10MRad. The conclusion from this work is that it should be possible to commercially manufacture practical vacuum dielectric field effect transistors which are radiation hard to at least 120 kGy(Si). (author)

  14. MOS Current Mode Logic Near Threshold Circuits

    Directory of Open Access Journals (Sweden)

    Alexander Shapiro

    2014-06-01

    Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

  15. Charge deep level transient spectroscopy study of 3 - 7 MeV/amu ion and fast neutron irradiation-induced changes in MOS structures

    International Nuclear Information System (INIS)

    Stano, J.; Skuratov, V.A.; Ziska, M.

    2001-01-01

    Radiation-induced changes in MOS capacitor structures irradiated with Bi (710 MeV), Kr (245 MeV), Ar (280, 155 MeV) ions and fast neutrons (E > 0.1 MeV) have been studied in view of Q-DLTS and C-V techniques. As was found, high energy ion and neutron irradiation enhance the induction of positive charge density in the oxide layer of MOS samples. The number of electrically active defects in this layer strongly decreases under dense electronic excitations. No dependence of vacancy-oxygen center concentration in silicon substrate normalized per number of displaced atoms by nuclear elastic collisions on projectile type have been observed

  16. Highly Enhanced Gas Adsorption Properties in Vertically Aligned MoS2 Layers.

    Science.gov (United States)

    Cho, Soo-Yeon; Kim, Seon Joon; Lee, Youhan; Kim, Jong-Seon; Jung, Woo-Bin; Yoo, Hae-Wook; Kim, Jihan; Jung, Hee-Tae

    2015-09-22

    In this work, we demonstrate that gas adsorption is significantly higher in edge sites of vertically aligned MoS2 compared to that of the conventional basal plane exposed MoS2 films. To compare the effect of the alignment of MoS2 on the gas adsorption properties, we synthesized three distinct MoS2 films with different alignment directions ((1) horizontally aligned MoS2 (basal plane exposed), (2) mixture of horizontally aligned MoS2 and vertically aligned layers (basal and edge exposed), and (3) vertically aligned MoS2 (edge exposed)) by using rapid sulfurization method of CVD process. Vertically aligned MoS2 film shows about 5-fold enhanced sensitivity to NO2 gas molecules compared to horizontally aligned MoS2 film. Vertically aligned MoS2 has superior resistance variation compared to horizontally aligned MoS2 even with same surface area exposed to identical concentration of gas molecules. We found that electrical response to target gas molecules correlates directly with the density of the exposed edge sites of MoS2 due to high adsorption of gas molecules onto edge sites of vertically aligned MoS2. Density functional theory (DFT) calculations corroborate the experimental results as stronger NO2 binding energies are computed for multiple configurations near the edge sites of MoS2, which verifies that electrical response to target gas molecules (NO2) correlates directly with the density of the exposed edge sites of MoS2 due to high adsorption of gas molecules onto edge sites of vertically aligned MoS2. We believe that this observation extends to other 2D TMD materials as well as MoS2 and can be applied to significantly enhance the gas sensor performance in these materials.

  17. Identification of protein tyrosine phosphatase 1B and casein as substrates for 124-v-Mos

    Directory of Open Access Journals (Sweden)

    Stabel Silvia

    2002-04-01

    Full Text Available Abstract Background The mos proto-oncogene encodes a cytoplasmic serine/threonine-specific protein kinase with crucial function during meiotic cell division in vertebrates. Based on oncogenic amino acid substitutions the viral derivative, 124-v-Mos, displays constitutive protein kinase activity and functions independent of unknown upstream effectors of mos protein kinase. We have utilized this property of 124-v-Mos and screened for novel mos substrates in immunocomplex kinase assays in vitro. Results We generated recombinant 124-v-Mos using the baculovirus expression system in Spodoptera frugiperda cells and demonstrated constitutive kinase activity by the ability of 124-v-Mos to auto-phosphorylate and to phosphorylate vimentin, a known substrate of c-Mos. Using this approach we analyzed a panel of acidic and basic substrates in immunocomplex protein kinase assays and identified novel in vitro substrates for 124-v-Mos, the protein tyrosine phosphatase 1B (PTP1B, alpha-casein and beta-casein. We controlled mos-specific phosphorylation of PTP1B and casein in comparative assays using a synthetic kinase-inactive 124-v-Mos mutant and further, tryptic digests of mos-phosphorylated beta-casein identified a phosphopeptide specifically targeted by wild-type 124-v-Mos. Two-dimensional phosphoamino acid analyses showed that 124-v-mos targets serine and threonine residues for phosphorylation in casein at a 1:1 ratio but auto-phosphorylation occurs predominantly on serine residues. Conclusion The mos substrates identified in this study represent a basis to approach the identification of the mos-consensus phosphorylation motif, important for the development of specific inhibitors of the Mos protein kinase.

  18. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  19. Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

    OpenAIRE

    Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

    2010-01-01

    Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

  20. Interfacial and Electrical Properties of Ge MOS Capacitor by ZrLaON Passivation Layer and Fluorine Incorporation

    Science.gov (United States)

    Huang, Yong; Xu, Jing-Ping; Liu, Lu; Cheng, Zhi-Xiang; Lai, Pui-To; Tang, Wing-Man

    2017-09-01

    Ge Metal-Oxide-Semiconductor (MOS) capacitor with HfTiON/ZrLaON stacked gate dielectric and fluorine-plasma treatment is fabricated, and its interfacial and electrical properties are compared with its counterparts without the ZrLaON passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density (3.7×1011 cm-2eV-1), small flatband voltage (0.21 V), good capacitance-voltage behavior, small frequency dispersion and low gate leakage current (4.41×10-5 A/cm2 at Vg = Vfb + 1V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate-dielectric annealing by the ZrLaON interlayer and fluorine incorporation, thus greatly reducing the defective states at/near the ZrLaON/Ge interface and improving the electrical properties of the device.

  1. Radiation effects on the electrical properties of hafnium oxide based MOS capacitors.

    Energy Technology Data Exchange (ETDEWEB)

    Petrosky, J. C. (Air Force Institute of Technology, Wright-Patterson Air Force Base, OH); McClory, J. W. (Air Force Institute of Technology, Wright-Patterson Air Force Base, OH); Bielejec, Edward Salvador; Foster, J. C. (Air Force Institute of Technology, Wright-Patterson Air Force Base, OH)

    2010-10-01

    Hafnium oxide-based MOS capacitors were investigated to determine electrical property response to radiation environments. In situ capacitance versus voltage measurements were analyzed to identify voltage shifting as a result of changes to trapped charge with increasing dose of gamma, neutron, and ion radiation. In situ measurements required investigation and optimization of capacitor fabrication to include dicing, cleaning, metalization, packaging, and wire bonding. A top metal contact of 200 angstroms of titanium followed by 2800 angstroms of gold allowed for repeatable wire bonding and proper electrical response. Gamma and ion irradiations of atomic layer deposited hafnium oxide on silicon devices both resulted in a midgap voltage shift of no more than 0.2 V toward less positive voltages. This shift indicates recombination of radiation induced positive charge with negative trapped charge in the bulk oxide. Silicon ion irradiation caused interface effects in addition to oxide trap effects that resulted in a flatband voltage shift of approximately 0.6 V also toward less positive voltages. Additionally, no bias dependent voltage shifts with gamma irradiation and strong oxide capacitance room temperature annealing after ion irradiation was observed. These characteristics, in addition to the small voltage shifts observed, demonstrate the radiation hardness of hafnium oxide and its applicability for use in space systems.

  2. A III-V nanowire channel on silicon for high-performance vertical transistors.

    Science.gov (United States)

    Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi

    2012-08-09

    Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

  3. Two-dimensional MoS2 electromechanical actuators

    Science.gov (United States)

    Hung, Nguyen T.; Nugraha, Ahmad R. T.; Saito, Riichiro

    2018-02-01

    We investigate the electromechanical properties of two-dimensional MoS2 monolayers with 1H, 1T, and 1T‧ structures as a function of charge doping by using density functional theory. We find isotropic elastic moduli in the 1H and 1T structures, while the 1T‧ structure exhibits an anisotropic elastic modulus. Moreover, the 1T structure is shown to have a negative Poisson’s ratio, while Poisson’s ratios of the 1H and 1T‧ are positive. By charge doping, the monolayer MoS2 shows a reversible strain and work density per cycle ranging from  -0.68% to 2.67% and from 4.4 to 36.9 MJ m-3, respectively, making them suitable for applications in electromechanical actuators. We also examine the stress generated in the MoS2 monolayers and we find that 1T and 1T‧ MoS2 monolayers have relatively better performance than 1H MoS2 monolayer. We argue that such excellent electromechanical performance originate from the electrical conductivity of the metallic 1T and semimetallic 1T‧ structures and also from their high Young’s modulus of about 150-200 GPa.

  4. A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

    Science.gov (United States)

    Wallace, Robert M.

    2001-03-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  5. Magnetic resonance force microscopy quantum computer with tellurium donors in silicon.

    Science.gov (United States)

    Berman, G P; Doolen, G D; Hammel, P C; Tsifrinovich, V I

    2001-03-26

    We propose a magnetic resonance force microscopy (MRFM)-based nuclear spin quantum computer using tellurium impurities in silicon. This approach to quantum computing combines well-developed silicon technology and expected advances in MRFM. Our proposal does not use electrostatic gates to realize quantum logic operations.

  6. Magnetic Resonance Force Microscopy Quantum Computer with Tellurium Donors in Silicon

    International Nuclear Information System (INIS)

    Berman, G. P.; Doolen, G. D.; Hammel, P. C.; Tsifrinovich, V. I.

    2001-01-01

    We propose a magnetic resonance force microscopy (MRFM)-based nuclear spin quantum computer using tellurium impurities in silicon. This approach to quantum computing combines well-developed silicon technology and expected advances in MRFM. Our proposal does not use electrostatic gates to realize quantum logic operations

  7. Noise Gating Solar Images

    Science.gov (United States)

    DeForest, Craig; Seaton, Daniel B.; Darnell, John A.

    2017-08-01

    I present and demonstrate a new, general purpose post-processing technique, "3D noise gating", that can reduce image noise by an order of magnitude or more without effective loss of spatial or temporal resolution in typical solar applications.Nearly all scientific images are, ultimately, limited by noise. Noise can be direct Poisson "shot noise" from photon counting effects, or introduced by other means such as detector read noise. Noise is typically represented as a random variable (perhaps with location- or image-dependent characteristics) that is sampled once per pixel or once per resolution element of an image sequence. Noise limits many aspects of image analysis, including photometry, spatiotemporal resolution, feature identification, morphology extraction, and background modeling and separation.Identifying and separating noise from image signal is difficult. The common practice of blurring in space and/or time works because most image "signal" is concentrated in the low Fourier components of an image, while noise is evenly distributed. Blurring in space and/or time attenuates the high spatial and temporal frequencies, reducing noise at the expense of also attenuating image detail. Noise-gating exploits the same property -- "coherence" -- that we use to identify features in images, to separate image features from noise.Processing image sequences through 3-D noise gating results in spectacular (more than 10x) improvements in signal-to-noise ratio, while not blurring bright, resolved features in either space or time. This improves most types of image analysis, including feature identification, time sequence extraction, absolute and relative photometry (including differential emission measure analysis), feature tracking, computer vision, correlation tracking, background modeling, cross-scale analysis, visual display/presentation, and image compression.I will introduce noise gating, describe the method, and show examples from several instruments (including SDO

  8. Silicon Quantum Dots for Quantum Information Processing

    Science.gov (United States)

    2013-11-01

    S. Lai, C. Tahan, A. Morello and A. S. Dzurak, Electron Spin lifetimes in multi-valley sil- icon quantum dots, S3NANO Winter School Few spin solid...lifetimes in multi-valley sil- icon quantum dots, International Workshop on Silicon Quantum Electronics, Grenoble, France, February 2012 (Poster). C...typically plunger gates), PMMA A5 is spun at 5000 rpm for 30 seconds, resulting in a 280 nm resist thickness. The resists are baked for 90 seconds at 180

  9. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...... that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used....

  10. A quantum Fredkin gate

    Science.gov (United States)

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  11. A quantum Fredkin gate.

    Science.gov (United States)

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

  12. Plasmons on the edge of MoS2 nanostructures

    DEFF Research Database (Denmark)

    Andersen, Kirsten; Jacobsen, Karsten Wedel; Thygesen, Kristian Sommer

    2014-01-01

    Using ab initio calculations we predict the existence of one-dimensional (1D), atomically confined plasmons at the edges of a zigzag MoS2 nanoribbon. The strongest plasmon originates from a metallic edge state localized on the sulfur dimers decorating the Mo edge of the ribbon. A detailed analysis...... of the dielectric function reveals that the observed deviations from the ideal 1D plasmon behavior result from single-particle transitions between the metallic edge state and the valence and conduction bands of the MoS2 sheet. The Mo and S edges of the ribbon are clearly distinguishable in calculated spatially...... resolved electron energy loss spectrum owing to the different plasmonic properties of the two edges. The edge plasmons could potentially be utilized for tuning the photocatalytic activity of MoS2 nanoparticles....

  13. Thermal conductivity of bulk and monolayer MoS2

    KAUST Repository

    Gandi, Appala

    2016-02-26

    © Copyright EPLA, 2016. We show that the lattice contribution to the thermal conductivity of MoS2 strongly dominates the carrier contribution in a broad temperature range from 300 to 800 K. Since theoretical insight into the lattice contribution is largely missing, though it would be essential for materials design, we solve the Boltzmann transport equation for the phonons self-consistently in order to evaluate the phonon lifetimes. In addition, the length scale for transition between diffusive and ballistic transport is determined. The low out-of-plane thermal conductivity of bulk MoS2 (2.3 Wm-1K-1 at 300 K) is useful for thermoelectric applications. On the other hand, the thermal conductivity of monolayer MoS2 (131 Wm-1K-1 at 300 K) is comparable to that of Si.

  14. Ultrafast photocurrents in monolayer MoS2

    Science.gov (United States)

    Parzinger, Eric; Wurstbauer, Ursula; Holleitner, Alexander W.

    Two-dimensional transition metal dichalcogenides such as MoS2 have emerged as interesting materials for optoelectronic devices. In particular, the ultrafast dynamics and lifetimes of photoexcited charge carriers have attracted great interest during the last years. We investigate the photocurrent response of monolayer MoS2 on a picosecond time scale utilizing a recently developed pump-probe spectroscopy technique based on coplanar striplines. We discuss the ultrafast dynamics within MoS2 including photo-thermoelectric currents and the impact of built-in fields due to Schottky barriers as well as the Fermi level pinning at the contact region. We acknowledge support by the ERC via Project 'NanoREAL', the DFG via excellence cluster 'Nanosystems Initiative Munich' (NIM), and through the TUM International Graduate School of Science and Engineering (IGSSE) and BaCaTeC.

  15. Temperature dependence of annealing on the contact resistance of MoS2 with graphene electrodes observed

    Science.gov (United States)

    Lu, Qin; Fang, Cizhe; Liu, Yan; Shao, Yao; Han, Genquan; Zhang, Jincheng; Hao, Yue

    2018-04-01

    Two-dimensional (2D) materials are promising candidates for atomically thin nanoelectronics. Among them, MoS2 has attracted considerable attention in the nanoscience and nanotechnology community owing to its unique characteristics including high electron mobility and intrinsic band gap. In this study, we experimentally explored the contact resistances of MoS2 films based on much layered graphene films as electrodes using the circular transmission line model (CTLM). The variation in the chemical composition of the material is thoroughly analyzed by Raman and X-ray photoelectric spectroscopy (XPS) measurements. Experimental results demonstrate that annealing followed by oxygen plasma treatment can effectively improve the contact resistance. Furthermore, the current-voltage curves measured after different annealing temperatures indicate good linear characteristics, which means a marked improvement in electrical property. Calculations show that a relatively low contact resistance of ˜4.177 kΩ (ignoring its size) without back gate voltage in a single-layer graphene/MoS2 structure at an optimal annealing temperature of 500 °C is achieved. This work about the effect of annealing temperature on contact resistance can also be employed for other 2D materials, which lays a foundation for further development of novel 2D material devices.

  16. Light-erasable embedded charge-trapping memory based on MoS2 for system-on-panel applications

    Science.gov (United States)

    He, Long-Fei; Zhu, Hao; Xu, Jing; Liu, Hao; Nie, Xin-Ran; Chen, Lin; Sun, Qing-Qing; Xia, Yang; Wei Zhang, David

    2017-11-01

    The continuous scaling and challenges in device integrations in modern portable electronic products have aroused many scientific interests, and a great deal of effort has been made in seeking solutions towards a more microminiaturized package assembled with smaller and more powerful components. In this study, an embedded light-erasable charge-trapping memory with a high-k dielectric stack (Al2O3/HfO2/Al2O3) and an atomically thin MoS2 channel has been fabricated and fully characterized. The memory exhibits a sufficient memory window, fast programming and erasing (P/E) speed, and high On/Off current ratio up to 107. Less than 25% memory window degradation is observed after projected 10-year retention, and the device functions perfectly after 8000 P/E operation cycles. Furthermore, the programmed device can be fully erased by incident light without electrical assistance. Such excellent memory performance originates from the intrinsic properties of two-dimensional (2D) MoS2 and the engineered back-gate dielectric stack. Our integration of 2D semiconductors in the infrastructure of light-erasable charge-trapping memory is very promising for future system-on-panel applications like storage of metadata and flexible imaging arrays.

  17. Electrical behaviour of fully solution processed HfO2 (MOS) in presence of different light illumination

    Science.gov (United States)

    Mondal, Sandip

    2018-04-01

    This experiment demonstrates the electrical behaviors of fully solution processed HfO2(MOS) in presence of different optical illumination. The capacitance voltage measurement was performed at frequency of 100 kHz with a DC gate sweep voltage of ±5V (with additional AC voltage of 100mV) in presence of deep UV (wavelength of 365nm with power of 25W) as well as white light (20W). It is found that there is a large shift in flatband voltage of 120mV due presence of white light during the CV measurement. However there is negligible change in flatband voltage (30mV) has been observed due to illumination of deep UV light.

  18. Multiple Independent Gate FETs: How Many Gates Do We Need?

    OpenAIRE

    Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

    2015-01-01

    Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

  19. Influence of O2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

    International Nuclear Information System (INIS)

    Ganapathi, Kolla Lakshmi; Bhat, Navakanta; Mohan, Sangeneni

    2014-01-01

    HfO 2  thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O 2  flow rate, during evaporation is optimized for 35 nm thick HfO 2  films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O 2  flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O 2  flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO 2  films deposited at two O 2  flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO 2  film deposited at 3 SCCM O 2  flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. (paper)

  20. The Co-60 gamma-ray irradiation effects on the Al/HfSiO4/p-Si/Al MOS capacitors

    Science.gov (United States)

    Lok, R.; Kaya, S.; Karacali, H.; Yilmaz, E.

    2017-12-01

    In this work, the initial interface trap density (Nit) to examine device compability for microelectronics and then the Co-60 gamma irradiation responses of Al/HfSiO4/p-Si/Al (MOS) capacitors were investigated in various dose ranges up to 70 Gy. Pre-irradiation response of the devices was evaluated from high frequency (HF) and low frequency (LF) capacitance method and the Nit was calculated as 9.91 × 1011 cm-2 which shows that the HfSiO4/p-Si interface quality is convenient for microelectronics applications. The irradiation responses of the devices were carried out from flat-band and mid-gap voltage shifts obtained from stretch of capacitance characteristics prior to and after irradiation. The results show that the flat band voltages very slightly shifted to positive voltage values demonstrating the enhancement of negative charge trapping in device structure. The sensitivity of the Al/HfSiO4/p-Si/Al MOS capacitors was found to be 4.41 mV/Gy for 300 nm-thick HfSiO4 gate dielectrics. This value approximately 6.5 times smaller compared to the same thickness conventional SiO2 based MOS devices. Therefore, HfSiO4 exhibits crucial irradiation tolerance in gamma irradiation environment. Consequently, HfSiO4 dielectrics may have significant usage for microelectronic technology as a radiation hard material where radiation field exists such as in space applications.

  1. Conduction quantization in monolayer MoS2

    Science.gov (United States)

    Li, T. S.

    2016-10-01

    We study the ballistic conduction of a monolayer MoS2 subject to a spatially modulated magnetic field by using the Landauer-Buttiker formalism. The band structure depends sensitively on the field strength, and its change has profound influence on the electron conduction. The conductance is found to demonstrate multi-step behavior due to the discrete number of conduction channels. The sharp peak and rectangular structures of the conductance are stretched out as temperature increases, due to the thermal broadening of the derivative of the Fermi-Dirac distribution function. Finally, quantum behavior in the conductance of MoS2 can be observed at temperatures below 10 K.

  2. Increasing sensitivity of MOS dosemeters in cascade connection

    International Nuclear Information System (INIS)

    Vychytil, F.; Cechak, T.; Gerndt, J.; Petr, I.

    1978-01-01

    The possibilities of increasing the sensitivity of MOS transistors in their cascade connection were studied theoretically and experimentally. The measurements confirmed the presumption that the instability of cascade-connected MOS transistors increased with the square of the number of transistors in the system. This allows systems to be formed with different sensitivity to ionizing radiation by encasing 10 to 10 4 transistors connected in cascade, which is technologically feasible. The procedure is also acceptable from the point of view of cost. (Z.M.)

  3. Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's

    International Nuclear Information System (INIS)

    Neamen, D.; Shedd, W.; Buchanan, B.

    1975-01-01

    The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed

  4. 100-nm gate lithography for double-gate transistors

    Science.gov (United States)

    Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

    2001-09-01

    The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

  5. CHARACTERIZATION OF THE ELECTROPHYSICAL PROPERTIES OF SILICON-SILICON DIOXIDE INTERFACE USING PROBE ELECTROMETRY METHODS

    Directory of Open Access Journals (Sweden)

    V. А. Pilipenko

    2017-01-01

    Full Text Available Introduction of submicron design standards into microelectronic industry and a decrease of the gate dielectric thickness raise the importance of the analysis of microinhomogeneities in the silicon-silicon dioxide system. However, there is very little to no information on practical implementation of probe electrometry methods, and particularly scanning Kelvin probe method, in the interoperational control of real semiconductor manufacturing process. The purpose of the study was the development of methods for nondestructive testing of semiconductor wafers based on the determination of electrophysical properties of the silicon-silicon dioxide interface and their spatial distribution over wafer’s surface using non-contact probe electrometry methods.Traditional C-V curve analysis and scanning Kelvin probe method were used to characterize silicon- silicon dioxide interface. The samples under testing were silicon wafers of KEF 4.5 and KDB 12 type (orientation <100>, diameter 100 mm.Probe electrometry results revealed uniform spatial distribution of wafer’s surface potential after its preliminary rapid thermal treatment. Silicon-silicon dioxide electric potential values were also higher after treatment than before it. This potential growth correlates with the drop in interface charge density. At the same time local changes in surface potential indicate changes in surface layer structure.Probe electrometry results qualitatively reflect changes of interface charge density in silicon-silicon dioxide structure during its technological treatment. Inhomogeneities of surface potential distribution reflect inhomogeneity of damaged layer thickness and can be used as a means for localization of interface treatment defects.

  6. Cavity-assisted quantum computing in a silicon nanostructure

    International Nuclear Information System (INIS)

    Tang Bao; Qin Hao; Zhang Rong; Xue Peng; Liu Jin-Ming

    2014-01-01

    We present a scheme of quantum computing with charge qubits corresponding to one excess electron shared between dangling-bond pairs of surface silicon atoms that couple to a microwave stripline resonator on a chip. By choosing a certain evolution time, we propose the realization of a set of universal single- and two-qubit logical gates. Due to its intrinsic stability and scalability, the silicon dangling-bond charge qubit can be regarded as one of the most promising candidates for quantum computation. Compared to the previous schemes on quantum computing with silicon bulk systems, our scheme shows such advantages as a long coherent time and direct control and readout. (general)

  7. Observation of apparent MOS regimes on Al/PECVD grown boron nitride/p-c-Si/Al MIS structure, investigated through admittance spectroscopy

    Energy Technology Data Exchange (ETDEWEB)

    Oezdemir, Orhan [Yildiz Technical University, Department of Physics, Esenler, istanbul (Turkey)

    2009-02-15

    PECVD grown boron nitride (BN) on crystalline silicon (c-Si) semiconductor was investigated by admittance measurement in the form of metal/insulator/semiconductor (MIS) structure. Apart from well-known regimes of traditional MOS structure, gradual bypassing of depletion layer was observed once ambient temperature (frequency) increased (decreased). Such an anomalous behavior was interpreted through modulations of charges located within BN film and/or at the interfacial layer of BN film/c-Si junction in terms of weighted average concept. (author)

  8. Expert Oracle GoldenGate

    CERN Document Server

    Prusinski, Ben; Chung, Richard

    2011-01-01

    Expert Oracle GoldenGate is a hands-on guide to creating and managing complex data replication environments using the latest in database replication technology from Oracle. GoldenGate is the future in replication technology from Oracle, and aims to be best-of-breed. GoldenGate supports homogeneous replication between Oracle databases. It supports heterogeneous replication involving other brands such as Microsoft SQL Server and IBM DB2 Universal Server. GoldenGate is high-speed, bidirectional, highly-parallelized, and makes only a light impact on the performance of databases involved in replica

  9. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

    International Nuclear Information System (INIS)

    Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

    2013-01-01

    A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  10. A novel optical gating method for laser gated imaging

    Science.gov (United States)

    Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

    2013-06-01

    For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

  11. Hydrophobic Ice Confined between Graphene and MoS2

    NARCIS (Netherlands)

    Bampoulis, Pantelis; Teernstra, V.J.; Lohse, Detlef; Zandvliet, Henricus J.W.; Poelsema, Bene

    2016-01-01

    The structure and nature of water confined between hydrophobic molybdenum disulfide (MoS2) and graphene (Gr) are investigated at room temperature by means of atomic force microscopy. We find the formation of two-dimensional (2D) crystalline ice layers. In contrast to the hexagonal ice “bilayers” of

  12. MOS BASED FORECAST OF 6-HOURLY AREA PRECIPITATION

    Czech Academy of Sciences Publication Activity Database

    Sokol, Zbyněk

    2006-01-01

    Roč. 50, č. 1 (2006), s. 105-120 ISSN 0039-3169 R&D Projects: GA AV ČR IBS3042101 Institutional research plan: CEZ:AV0Z30420517 Keywords : precipitation forecast * regression * statistical postprocessing * MOS Subject RIV: DG - Athmosphere Sciences, Meteorology Impact factor: 0.603, year: 2006

  13. Magnetoresistance in molybdenite (MoS2) crystals

    International Nuclear Information System (INIS)

    Chakraborty, B.R.; Dutta, A.K.

    1975-01-01

    The principal magnetoresistance ratios of molybdenite (MoS 2 ), the naturally occurring semiconducting crystal, have been investigated at magnetic fields ranging from 4.5 KOe and within the temperature range 300 0 K to 700 0 K. Unlike some previous observations, magnetoresistance has been found to be negative. (author)

  14. Influence of halo doping profiles on MOS transistor mismatch

    NARCIS (Netherlands)

    Andricciola, P.; Tuinhout, H.

    2009-01-01

    Halo implants are used in modern CMOS technology to reduce the short channel effect. However, the lateral non-uniformity of the channel doping has been proven to degenerate the mismatch performance. With this paper we want to discuss the influence of the halo profile on MOS transistor mismatch. The

  15. Tailored MoS2 nanorods: a simple microwave assisted synthesis

    Science.gov (United States)

    Reshmi, S.; Akshaya, M. V.; Satpati, Biswarup; Roy, Anupam; Basu, Palash Kumar; Bhattacharjee, K.

    2017-11-01

    We report here the synthesis of MoS2 nanostructures by a simple liquid phase exfoliation of MoS2 powder in organic solvents followed by microwave treatment. The probe sonication and the microwave treatment play an important role in rolling and curling of the MoS2 nanosheets to give rise to MoS2 spheres and rod/tube like-structures with diameter approximately 150-200 nm. The MoS2 nanorods formed in this fashion are hollow inside with a wall thickness of 15-20 nm and the length of the nanorods is found in the order of several micrometers. Synthesis of such tailored MoS2 nanorods by liquid phase exfoliation is not yet reported. Our observations suggest the 2H phase of bulk MoS2 remains preserved in the nanostructures with high crystalline quality.

  16. Fabrication of a novel silicon single electron transistor for Si:P quantum computer devices

    International Nuclear Information System (INIS)

    Angus, S.J.; Smith, C.E.A.; Gauja, E.; Dzurak, A.S.; Clark, R.G.; Snider, G.L.

    2004-01-01

    Full text: Quantum computation relies on the successful measurement of quantum states. Single electron transistors (SETs) are known to be able to perform fast and sensitive charge measurements of solid state qubits. However, due to their sensitivity, SETs are also very susceptible to random charge fluctuations in a solid-state materials environment. In previous dc transport measurements, silicon-based SETs have demonstrated greater charge stability than A1/A1 2 O 3 SETs. We have designed and fabricated a novel silicon SET architecture for a comparison of the noise characteristics of silicon and aluminium based devices. The silicon SET described here is designed for controllable and reproducible low temperature operation. It is fabricated using a novel dual gate structure on a silicon-on-insulator substrate. A silicon quantum wire is formed in a 100nm thick high-resistivity superficial silicon layer using reactive ion etching. Carriers are induced in the silicon wire by a back gate in the silicon substrate. The tunnel barriers are created electrostatically, using lithographically defined metallic electrodes (∼40nm width). These tunnel barriers surround the surface of the quantum wire, thus producing excellent electrostatic confinement. This architecture provides independent control of tunnel barrier height and island occupancy, thus promising better control of Coulomb blockade oscillations than in previously investigated silicon SETs. The use of a near intrinsic silicon substrate offers compatibility with Si:P qubits in the longer term

  17. Plasma-assisted synthesis of MoS2

    Science.gov (United States)

    Campbell, Philip M.; Perini, Christopher J.; Chiu, Johannes; Gupta, Atul; Ray, Hunter S.; Chen, Hang; Wenzel, Kevin; Snyder, Eric; Wagner, Brent K.; Ready, Jud; Vogel, Eric M.

    2018-03-01

    There has been significant interest in transition metal dichalcogenides (TMDs), including MoS2, in recent years due to their potential application in novel electronic and optical devices. While synthesis methods have been developed for large-area films of MoS2, many of these techniques require synthesis temperatures of 800 °C or higher. As a result of the thermal budget, direct synthesis requiring high temperatures is incompatible with many integrated circuit processes as well as flexible substrates. This work explores several methods of plasma-assisted synthesis of MoS2 as a way to lower the synthesis temperature. The first approach used is conversion of a naturally oxidized molybdenum thin film to MoS2 using H2S plasma. Conversion is demonstrated at temperatures as low as 400 °C, and the conversion is enabled by hydrogen radicals which reduce the oxidized molybdenum films. The second method is a vapor phase reaction incorporating thermally evaporated MoO3 exposed to a direct H2S plasma, similar to chemical vapor deposition (CVD) synthesis of MoS2. Synthesis at 400 °C results in formation of super-stoichiometric MoS2 in a beam-interrupted growth process. A final growth method relies on a cyclical process in which a small amount of Mo is sputtered onto the substrate and is subsequently sulfurized in a H2S plasma. Similar results could be realized using an atomic layer deposition (ALD) process to deposit the Mo film. Compared to high temperature synthesis methods, the lower temperature samples are lower quality, potentially due to poor crystallinity or higher defect density in the films. Temperature-dependent conductivity measurements are consistent with hopping conduction in the plasma-assisted synthetic MoS2, suggesting a high degree of disorder in the low-temperature films. Optimization of the plasma-assisted synthesis process for slower growth rate and better stoichiometry is expected to lead to high quality films at low growth temperature.

  18. Process controls for radiation hardened aluminum gate bulk silicon CMOS

    International Nuclear Information System (INIS)

    Gregory, B.L.

    1975-01-01

    Optimized dry oxides have recently yielded notable improvements in CMOS radiation-hardness. By following the proper procedures and recipes, it is now possible to produce devices which will function satisfactorily after exposure to a total ionizing dose in excess of 10 6 RADS (Si). This paper is concerned with the controls required on processing parameters once the optimized process is defined. In this process, the pre-irradiation electrical parameters must be closely controlled to insure that devices will function after irradiation. In particular, the specifications on n- and p-channel threshold voltages require tight control of fixed oxide charge, surface-state density, oxide thickness, and substrate and p-well surface concentrations. In order to achieve the above level of radiation hardness, certain processing procedures and parameters must also be closely controlled. Higher levels of cleanliness are required in the hardened process than are commonly required for commercial CMOS since, for hardened dry oxides, no impurity gettering can be employed during or after oxidation. Without such gettering, an unclean oxide is unacceptable due to bias-temperature instability. Correct pre-oxidation cleaning, residual surface damage removal, proper oxidation and annealing temperatures and times, and the correct metal sintering cycle are all important in determining device hardness. In a reproducible, hardened process, each of these processing steps must be closely controlled. (U.S.)

  19. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    International Nuclear Information System (INIS)

    Lin, Y. H.; Chou, J. C.

    2015-01-01

    We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT_s) using different high-Κ gate dielectric materials such as silicon nitride (Si_3N_4) and aluminum oxide (Al_2O_3) at low temperature process (<300 degree) and compared them with low temperature silicon dioxide (SiO_2). The IGZO device with high-Κ gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, post annealing treatment is an essential process for completing the process. The chemical reaction of the high-κ/IGZO interface due to heat formation in high-Κ/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-Κ gate dielectric materials and explained the interface effect by charge band diagram.

  20. Off-axis electron holography for the measurement of active dopants in silicon semiconductor devices

    International Nuclear Information System (INIS)

    Cooper, David

    2016-01-01

    There is a need in the semiconductor industry for a dopant profiling technique with nm-scale resolution. Here we demonstrate that off-axis electron holography can be used to provide maps of the electrostatic potential in semiconductor devices with nm-scale resolution. In this paper we will discuss issues regarding the spatial resolution and precision of the technique. Then we will discuss problems with specimen preparation and how this affects the accuracy of the measurements of the potentials. Finally we show results from experimental off-axis electron holography applied to nMOS and pMOS CMOS devices grown on bulk silicon and silicon- on-insulator type devices and present solutions to common problems that are encountered when examining these types of devices. (paper)

  1. Effects of trap density on drain current LFN and its model development for E-mode GaN MOS-HEMT

    Science.gov (United States)

    Panda, D. K.; Lenka, T. R.

    2017-12-01

    In this paper the drain current low-frequency noise (LFN) of E-mode GaN MOS-HEMT is investigated for different gate insulators such as SiO2, Al2O3/Ga2O3/GdO3, HfO2/SiO2, La2O3/SiO2 and HfO2 with different trap densities by IFM based TCAD simulation. In order to analyze this an analytical model of drain current low frequency noise is developed. The model is developed by considering 2DEG carrier fluctuations, mobility fluctuations and the effects of 2DEG charge carrier fluctuations on the mobility. In the study of different gate insulators it is observed that carrier fluctuation is the dominant low frequency noise source and the non-uniform exponential distribution is critical to explain LFN behavior, so the analytical model is developed by considering uniform distribution of trap density. The model is validated with available experimental data from literature. The effect of total number of traps and gate length scaling on this low frequency noise due to different gate dielectrics is also investigated.

  2. A radiation-tolerant, low-power non-volatile memory based on silicon nanocrystal quantum dots

    OpenAIRE

    Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; De Blauwe, J.; Green, M. L.

    2001-01-01

    Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO_2 is a critical aspect of the performance ...

  3. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

    International Nuclear Information System (INIS)

    Bhartia, Mini; Chatterjee, Arun Kumar

    2015-01-01

    A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2. (paper)

  4. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

    Science.gov (United States)

    Bhartia, Mini; Chatterjee, Arun Kumar

    2015-04-01

    A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.

  5. Design of a radiation hard silicon pixel sensor for X-ray science

    Energy Technology Data Exchange (ETDEWEB)

    Schwandt, Joern

    2014-06-15

    At DESY Hamburg the European X-ray Free-Electron Laser (EuXFEL) is presently under construction. The EuXFEL has unique properties with respect to X-ray energy, instantaneous intensity, pulse length, coherence and number of pulses/sec. These properties of the EuXFEL pose very demanding requirements for imaging detectors. One of the detector systems which is currently under development to meet these challenges is the Adaptive Gain Integrating Pixel Detector, AGIPD. It is a hybrid pixel-detector system with 1024 x 1024 p{sup +} pixels of dimensions 200 μm x 200 μm, made of 16 p{sup +}nn{sup +}- silicon sensors, each with 10.52 cm x 2.56 cm sensitive area and 500 μm thickness. The particular requirements for the AGIPD are a separation between noise and single photons down to energies of 5 keV, more than 10{sup 4} photons per pixel for a pulse duration of less than 100 fs, negligible pile-up at the EuXFEL repetition rate of 4.5 MHz, operation for X-ray doses up to 1 GGy, good efficiency for X-rays with energies between 5 and 20 keV, and minimal inactive regions at the edges. The main challenge in the sensor design is the required radiation tolerance and high operational voltage, which is required to reduce the so-called plasma effect. This requires a specially optimized sensor. The X-ray radiation damage results in a build-up of oxide charges and interface traps which lead to a reduction of the breakdown voltage, increased leakage current, increased interpixel capacitances and charge losses. Extensive TCAD simulations have been performed to understand the impact of X-ray radiation damage on the detector performance and optimize the sensor design. To take radiation damage into account in the simulation, radiation damage parameters have been determined on MOS capacitors and gate-controlled diodes as function of dose. The optimized sensor design was fabricated by SINTEF. Irradiation tests on test structures and sensors show that the sensor design is radiation hard and

  6. Penn State DOE GATE Program

    Energy Technology Data Exchange (ETDEWEB)

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  7. Piezoconductivity of gated suspended graphene

    NARCIS (Netherlands)

    Medvedyeva, M.V.; Blanter, Y.M.

    2011-01-01

    We investigate the conductivity of graphene sheet deformed over a gate. The effect of the deformation on the conductivity is twofold: The lattice distortion can be represented as pseudovector potential in the Dirac equation formalism, whereas the gate causes inhomogeneous density redistribution. We

  8. Tin - an unlikely ally for silicon field effect transistors?

    KAUST Repository

    Hussain, Aftab M.

    2014-01-13

    We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high-κ/metal gate based multi-gate-field-effect-transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. A fabrication guide for planar silicon quantum dot heterostructures

    Science.gov (United States)

    Spruijtenburg, Paul C.; Amitonov, Sergey V.; van der Wiel, Wilfred G.; Zwanenburg, Floris A.

    2018-04-01

    We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.

  10. On photonic controlled phase gates

    International Nuclear Information System (INIS)

    Kieling, K; Eisert, J; O'Brien, J L

    2010-01-01

    As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.

  11. GATE: Improving the computational efficiency

    International Nuclear Information System (INIS)

    Staelens, S.; De Beenhouwer, J.; Kruecker, D.; Maigne, L.; Rannou, F.; Ferrer, L.; D'Asseler, Y.; Buvat, I.; Lemahieu, I.

    2006-01-01

    GATE is a software dedicated to Monte Carlo simulations in Single Photon Emission Computed Tomography (SPECT) and Positron Emission Tomography (PET). An important disadvantage of those simulations is the fundamental burden of computation time. This manuscript describes three different techniques in order to improve the efficiency of those simulations. Firstly, the implementation of variance reduction techniques (VRTs), more specifically the incorporation of geometrical importance sampling, is discussed. After this, the newly designed cluster version of the GATE software is described. The experiments have shown that GATE simulations scale very well on a cluster of homogeneous computers. Finally, an elaboration on the deployment of GATE on the Enabling Grids for E-Science in Europe (EGEE) grid will conclude the description of efficiency enhancement efforts. The three aforementioned methods improve the efficiency of GATE to a large extent and make realistic patient-specific overnight Monte Carlo simulations achievable

  12. Performance of the Charge Injectors of the ALICE Silicon Drift Detectors

    Czech Academy of Sciences Publication Activity Database

    Kushpil, Svetlana

    2012-01-01

    Roč. 37, č. 37 (2012), s. 970-975 ISSN 1875-3892. [TIPP 2011 - Technology and Instrumentation in Particle Physics 2011. Chicago, 09.06.2011-14.06.2011] R&D Projects: GA MŠk LA08015 Institutional support: RVO:61389005 Keywords : semiconductor detector * silicon drift detector * MOS charge injector Subject RIV: BG - Nuclear, Atomic and Molecular Physics, Colliders http://www.sciencedirect.com/science/article/pii/S1875389212017920

  13. Photoconduction in silicon rich oxide films

    Energy Technology Data Exchange (ETDEWEB)

    Luna-Lopez, J A; Carrillo-Lopez, J; Flores-Gracia, F J; Garcia-Salgado, G [CIDS-ICUAP, Benemerita Universidad Autonoma de Puebla. Ed. 103 D and C, col. San Manuel, Puebla, Pue. Mexico 72570 (Mexico); Aceves-Mijares, M; Morales-Sanchez, A, E-mail: jluna@buap.siu.m, E-mail: jluna@inaoep.m [INAOE, Luis Enrique Erro No. 1, Apdo. 51, Tonantzintla, Puebla, Mexico 72000 (Mexico)

    2009-05-01

    Photoconduction of silicon rich oxide (SRO) thin films were studied by current-voltage (I-V) measurements, where ultraviolet (UV) and white (Vis) light illumination were applied. SRO thin films were deposited by low pressure chemical vapour deposition (LPCVD) technique, using SiH{sub 4} (silane) and N{sub 2}O (nitrous oxide) as reactive gases at 700 {sup 0}. The gas flow ratio, Ro = [N{sub 2}O]/[SiH{sub 4}] was used to control the silicon excess. The thickness and refractive index of the SRO films were 72.0 nm, 75.5 nm, 59.1 nm, 73.4 nm and 1.7, 1.5, 1.46, 1.45, corresponding to R{sub o} = 10, 20, 30 and 50, respectively. These results were obtained by null ellipsometry. Si nanoparticles (Si-nps) and defects within SRO films permit to obtain interesting photoelectric properties as a high photocurrent and photoconduction. These effects strongly depend on the silicon excess, thickness and structure type. Two different structures (Al/SRO/Si and Al/SRO/SRO/Si metal-oxide-semiconductor (MOS)-like structures) were fabricated and used as devices. The photocurrent in these structures is dominated by the generation of carriers due to the incident photon energies ({approx}3.0-1.6 eV and 5 eV). These structures showed large photoconductive response at room temperature. Therefore, these structures have potential applications in optoelectronics devices.

  14. 2-D modeling and analysis of short-channel behavior of a front high- K gate stack triple-material gate SB SON MOSFET

    Science.gov (United States)

    Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar

    2018-02-01

    This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

  15. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    KAUST Repository

    Alshareef, Husam N.

    2010-11-19

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  16. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    KAUST Repository

    Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.

    2010-01-01

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  17. Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi

    2012-01-01

    The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)

  18. Sub-50 nm gate length SOI transistor development for high performance microprocessors

    International Nuclear Information System (INIS)

    Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

    2004-01-01

    Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

  19. Gated equilibrium bloodpool scintigraphy

    International Nuclear Information System (INIS)

    Reinders Folmer, S.C.C.

    1981-01-01

    This thesis deals with the clinical applications of gated equilibrium bloodpool scintigraphy, performed with either a gamma camera or a portable detector system, the nuclear stethoscope. The main goal has been to define the value and limitations of noninvasive measurements of left ventricular ejection fraction as a parameter of cardiac performance in various disease states, both for diagnostic purposes as well as during follow-up after medical or surgical intervention. Secondly, it was attempted to extend the use of the equilibrium bloodpool techniques beyond the calculation of ejection fraction alone by considering the feasibility to determine ventricular volumes and by including the possibility of quantifying valvular regurgitation. In both cases, it has been tried to broaden the perspective of the observations by comparing them with results of other, invasive and non-invasive, procedures, in particular cardiac catheterization, M-mode echocardiography and myocardial perfusion scintigraphy. (Auth.)

  20. Geochemistry of silicon isotopes

    Energy Technology Data Exchange (ETDEWEB)

    Ding, Tiping; Li, Yanhe; Gao, Jianfei; Hu, Bin [Chinese Academy of Geological Science, Beijing (China). Inst. of Mineral Resources; Jiang, Shaoyong [China Univ. of Geosciences, Wuhan (China).

    2018-04-01

    Silicon is one of the most abundant elements in the Earth and silicon isotope geochemistry is important in identifying the silicon source for various geological bodies and in studying the behavior of silicon in different geological processes. This book starts with an introduction on the development of silicon isotope geochemistry. Various analytical methods are described and compared with each other in detail. The mechanisms of silicon isotope fractionation are discussed, and silicon isotope distributions in various extraterrestrial and terrestrial reservoirs are updated. Besides, the applications of silicon isotopes in several important fields are presented.

  1. High conductivity graphene-like MoS2/polyaniline nanocomposites and its application in supercapacitor

    International Nuclear Information System (INIS)

    Wang, Jin; Wu, Zongchao; Hu, Kunhong; Chen, Xiangying; Yin, Huabing

    2015-01-01

    Highlights: • A facile synthesis method of MoS 2 /PANI intercalated nanocomposites is developed. • There is synergistic effect between PANI and MoS 2 layer in the MoS 2 /PANI composites. • Intercalation is benefit for electrons transportation and conductivity increase. • The well-defined MoS 2 /PANI have good specific capacitances and long cyclic life. - Abstract: High conductivity nanocomposites of molybdenum disulfide (MoS 2 )/polyaniline (PANI) were prepared via direct intercalation of aniline monomer and doped with dodecyl benzene sulfonic acid (DBSA). The intercalated interaction between PANI and MoS 2 improves the conductivity and thermal stability of MoS 2 /PANI nanocomposites with the increasing fraction of MoS 2 . The conductivity and maximum weight loss velocity temperature of PANI/MoS 2 -38 sample are 2.38 S cm −1 and 353 °C, respectively. This architecture is also advantageous for enhancing the capacitance properties and cyclic stabilities of MoS 2 /PANI electrodes. In comparison to the specific capacitance of 131 F/g and 42% retained capacitance over 600 cycles of PANI electrode, the MoS 2 /PANI-38 electrode provides a specific capacitance up to 390 F/g and 86% retained capacitance over 1000 cycles. Thus it provides an improved capacitance method which synergistically combines pseudocapacitance and double-layer capacitance for supercapacitor electrodes

  2. Oxidation of atomically thin MoS2 on SiO2

    Science.gov (United States)

    Yamamoto, Mahito; Cullen, William; Einstein, Theodore; Fuhrer, Michael

    2013-03-01

    Surface oxidation of MoS2 markedly affects its electronic, optical, and tribological properties. However, oxidative reactivity of atomically thin MoS2 has yet to be addressed. Here, we investigate oxidation of atomic layers of MoS2 using atomic force microscopy and Raman spectroscopy. MoS2 is mechanically exfoliated onto SiO2 and oxidized in Ar/O2 or Ar/O3 (ozone) at 100-450 °C. MoS2 is much more reactive to O2 than an analogous atomic membrane of graphene and monolayer MoS2 is completely etched very rapidly upon O2 treatment above 300 °C. Thicker MoS2 (> 15 nm) transforms into MoO3 after oxidation at 400 °C, which is confirmed by a Raman peak at 820 cm-1. However, few-layer MoS2 oxidized below 400 °C exhibits no MoO3 Raman mode but etch pits are formed, similar to graphene. We find atomic layers of MoS2 shows larger reactivity to O3 than to O2 and monolayer MoS2 transforms chemically upon O3 treatment even below 100 °C. Work supported by the U. of Maryland NSF-MRSEC under Grant No. DMR 05-20741.

  3. Synthesis of Epitaxial Single-Layer MoS2 on Au(111).

    Science.gov (United States)

    Grønborg, Signe S; Ulstrup, Søren; Bianchi, Marco; Dendzik, Maciej; Sanders, Charlotte E; Lauritsen, Jeppe V; Hofmann, Philip; Miwa, Jill A

    2015-09-08

    We present a method for synthesizing large area epitaxial single-layer MoS2 on the Au(111) surface in ultrahigh vacuum. Using scanning tunneling microscopy and low energy electron diffraction, the evolution of the growth is followed from nanoscale single-layer MoS2 islands to a continuous MoS2 layer. An exceptionally good control over the MoS2 coverage is maintained using an approach based on cycles of Mo evaporation and sulfurization to first nucleate the MoS2 nanoislands and then gradually increase their size. During this growth process the native herringbone reconstruction of Au(111) is lifted as shown by low energy electron diffraction measurements. Within the MoS2 islands, we identify domains rotated by 60° that lead to atomically sharp line defects at domain boundaries. As the MoS2 coverage approaches the limit of a complete single layer, the formation of bilayer MoS2 islands is initiated. Angle-resolved photoemission spectroscopy measurements of both single and bilayer MoS2 samples show a dramatic change in their band structure around the center of the Brillouin zone. Brief exposure to air after removing the MoS2 layer from vacuum is not found to affect its quality.

  4. IMPROVING BANDWIDTH OF FLIPPED VOLTAGE FOLLOWER USING GATE-BODY DRIVEN TECHNIQUE

    Directory of Open Access Journals (Sweden)

    VANDANA NIRANJAN

    2017-01-01

    Full Text Available In this paper, a new approach to enhance the bandwidth of flipped voltage follower is explored. The proposed approach is based on gate-body driven technique. This technique boosts the transconductance in a MOS transistor as both gate and body/bulk terminals are tied together and used as signal input. This novel technique appears as a good solution to merge the advantages of gate-driven and bulk-driven techniques and suppress their disadvantages. The gate-body driven technique utilizes body effect to enable low voltage low power operation and improves the overall performance of flipped voltage follower, providing it with low output impedance, high input impedance and bandwidth extension ratio of 2.614. The most attractive feature is that bandwidth enhancement has been achieved without use of any passive component or extra circuitry. Simulations in PSpice environment for 180 nm CMOS technology verified the predicted theoretical results. The improved flipped voltage follower is particularly interesting for high frequency low noise signal processing applications.

  5. Silicon Carbide Emitter Turn-Off Thyristor

    Directory of Open Access Journals (Sweden)

    Jun Wang

    2008-01-01

    Full Text Available A novel MOS-controlled SiC thyristor device, the SiC emitter turn-off thyristor (ETO is a promising technology for future high-voltage switching applications because it integrates the excellent current conduction capability of a SiC thyristor with a simple MOS-control interface. Through unity-gain turn-off, the SiC ETO also achieves excellent Safe Operation Area (SOA and faster switching speeds than silicon ETOs. The world's first 4.5-kV SiC ETO prototype shows a forward voltage drop of 4.26 V at 26.5 A/cm2 current density at room and elevated temperatures. Tested in an inductive circuit with a 2.5 kV DC link voltage and a 9.56-A load current, the SiC ETO shows a fast turn-off time of 1.63 microseconds and a low 9.88 mJ turn-off energy. The low switching loss indicates that the SiC ETO could operate at about 4 kHz if 100 W/cm2 conduction and the 100 W/cm2 turn-off losses can be removed by the thermal management system. This frequency capability is about 4 times higher than 4.5-kV-class silicon power devices. The preliminary demonstration shows that the SiC ETO is a promising candidate for high-frequency, high-voltage power conversion applications, and additional developments to optimize the device for higher voltage (>5 kV and higher frequency (10 kHz are needed.

  6. Spin filling of valley-orbit states in a silicon quantum dot

    Energy Technology Data Exchange (ETDEWEB)

    Lim, W H; Yang, C H; Zwanenburg, F A; Dzurak, A S, E-mail: wee.lim@unsw.edu.au [Centre for Quantum Computation and Communication Technology, School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, NSW 2052 (Australia)

    2011-08-19

    We report the demonstration of a low-disorder silicon metal-oxide-semiconductor (Si MOS) quantum dot containing a tunable number of electrons from zero to N = 27. The observed evolution of addition energies with parallel magnetic field reveals the spin filling of electrons into valley-orbit states. We find a splitting of 0.10 meV between the ground and first excited states, consistent with theory and placing a lower bound on the valley splitting. Our results provide optimism for the realisation in the near future of spin qubits based on silicon quantum dots.

  7. SiC Power MOSFET with Improved Gate Dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Sbrockey, Nick M. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Spencer, Michael G. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Chandrashekhar, Chandra M.V. S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)

    2010-08-23

    In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

  8. Fabrication and evaluation of series-triple quantum dots by thermal oxidation of silicon nanowire

    International Nuclear Information System (INIS)

    Uchida, Takafumi; Jo, Mingyu; Tsurumaki-Fukuchi, Atsushi; Arita, Masashi; Takahashi, Yasuo; Fujiwara, Akira

    2015-01-01

    Series-connected triple quantum dots were fabricated by a simple two-step oxidation technique using the pattern-dependent oxidation of a silicon nanowire and an additional oxidation of the nanowire through the gap of the fine gates attached to the nanowire. The characteristics of multi-dot single-electron devices are obtained. The formation of each quantum dot beneath an attached gate is confirmed by analyzing the electrical characteristics and by evaluating the gate capacitances between all pairings of gates and quantum dots. Because the gate electrode is automatically attached to each dot, the device structure benefits from scalability. This technique promises integrability of multiple quantum dots with individual control gates

  9. Photon-gated spin transistor

    OpenAIRE

    Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

    2017-01-01

    Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

  10. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

    International Nuclear Information System (INIS)

    Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

    2011-01-01

    An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

  11. Neutron induced degradation in nitrided pyrogenic field oxide MOS capacitors

    CERN Document Server

    Vaidya, S J; Shaikh, A M; Chandorkar, A N

    2002-01-01

    Neutron induced oxide charge trapping and generation of interface states in MOS capacitors with pyrogenic and nitrided pyrogenic field oxides have been studied. In order to assess the damage due to neutrons alone, it is necessary to account for the damage produced by the accompanying gamma rays from neutron radiation. This is done by measuring the intensity of gamma radiation accompanying neutrons at different neutron fluences at the irradiation position. MOS capacitor structures were subjected to neutron radiation in a swimming pool type of reactor. Other samples from the same batch were then subjected to an equivalent dose of gamma radiation from a Co sup 6 sup 0 source. The difference in the damage observed was used to characterize the damage caused by neutrons. It is observed that neutrons, though uncharged, are capable of causing ionization damage. This damage is found to be significant when the radiation is performed under biased conditions. Nitridation in different ambients is found to improve the radi...

  12. Electron Emission from Ultra-Large Area MOS Electron Emitters

    DEFF Research Database (Denmark)

    Thomsen, Lasse Bjørchmar; Nielsen, Gunver; Vendelbo, Søren Bastholm

    2009-01-01

    Ultralarge metal-oxide-semiconductor (MOS) devices with an active oxide area of 1 cm2 have been fabricated for use as electron emitters. The MOS structures consist of a Si substrate, a SiO2 tunnel barrier (~5 nm), a Ti wetting layer (3–10 Å), and a Au top layer (5–60 nm). Electron emission from...... layer is varied from 3 to 10 Å which changes the emission efficiency by more than one order of magnitude. The apparent mean free path of ~5 eV electrons in Au is found to be 52 Å. Deposition of Cs on the Au film increased the electron emission efficiency to 4.3% at 4 V by lowering the work function....... Electron emission under high pressures (up to 2 bars) of Ar was observed. ©2009 American Vacuum Society...

  13. Charging effect at grain boundaries of MoS2

    Science.gov (United States)

    Yan, Chenhui; Dong, Xi; Li, Connie H.; Li, Lian

    2018-05-01

    Grain boundaries (GBs) are inherent extended defects in chemical vapor deposited (CVD) transition metal dichalcogenide (TMD) films. Characterization of the atomic structure and electronic properties of these GBs is crucial for understanding and controlling the properties of TMDs via defect engineering. Here, we report the atomic and electronic structure of GBs in CVD grown MoS2 on epitaxial graphene/SiC(0001). Using scanning tunneling microscopy/spectroscopy, we find that GBs mostly consist of arrays of dislocation cores, where the presence of mid-gap states shifts both conduction and valence band edges by up to 1 eV. Our findings demonstrate the first charging effect near GBs in CVD grown MoS2, providing insights into the significant impact GBs can have on materials properties.

  14. Ultralarge area MOS tunnel devices for electron emission

    DEFF Research Database (Denmark)

    Thomsen, Lasse Bjørchmar; Nielsen, Gunver; Vendelbo, Søren Bastholm

    2007-01-01

    density. Oxide thicknesses have been extracted by fitting a model based on Fermi-Dirac statistics to the C-V characteristics. By plotting I-V characteristics in a Fowler plot, a measure of the thickness of the oxide can be extracted from the tunnel current. These apparent thicknesses show a high degree......A comparative analysis of metal-oxide-semiconductor (MOS) capacitors by capacitance-voltage (C-V) and current-voltage (I-V) characteristics has been employed to characterize the thickness variations of the oxide on different length scales. Ultralarge area (1 cm(2)) ultrathin (similar to 5 nm oxide......) MOS capacitors have been fabricated to investigate their functionality and the variations in oxide thickness, with the use as future electron emission devices as the goal. I-V characteristics show very low leakage current and excellent agreement to the Fowler-Nordheim expression for the current...

  15. Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

    Science.gov (United States)

    Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-04-01

    Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

  16. Tin (Sn) - An Unlikely Ally to Extend Moore's Law for Silicon CMOS?

    KAUST Repository

    Hussain, Aftab M.

    2012-12-01

    There has been an exponential increase in the performance of silicon based semiconductor devices in the past few decades. This improvement has mainly been due to dimensional scaling of the MOSFET. However, physical constraints limit the continued growth in device performance. To overcome this problem, novel channel materials are being developed to enhance carrier mobility and hence increase device performance. This work explores a novel semiconducting alloy - Silicon-tin (SiSn) as a channel material for CMOS applications. For the first time ever, MOS devices using SiSn as channel material have been demonstrated. A low cost, scalable and manufacturable process for obtaining SiSn by diffusion of Sn into silicon has also been explored. The channel material thus obtained is electrically characterized by fabricating MOSCAPs and Mesa-shaped MOSFETs. The SiSn devices have been compared to similar devices fabricated using silicon as channel material.

  17. Construction of MoS2/Si nanowire array heterojunction for ultrahigh-sensitivity gas sensor

    Science.gov (United States)

    Wu, Di; Lou, Zhenhua; Wang, Yuange; Xu, Tingting; Shi, Zhifeng; Xu, Junmin; Tian, Yongtao; Li, Xinjian

    2017-10-01

    Few-layer MoS2 thin films were synthesized by a two-step thermal decomposition process. In addition, MoS2/Si nanowire array (SiNWA) heterojunctions exhibiting excellent gas sensing properties were constructed and investigated. Further analysis reveals that such MoS2/SiNWA heterojunction devices are highly sensitive to nitric oxide (NO) gas under reverse voltages at room temperature (RT). The gas sensor demonstrated a minimum detection limit of 10 ppb, which represents the lowest value obtained for MoS2-based sensors, as well as an ultrahigh response of 3518% (50 ppm NO, ˜50% RH), with good repeatability and selectivity of the MoS2/SiNWA heterojunction. The sensing mechanisms were also discussed. The performance of the MoS2/SiNWA heterojunction gas sensors is superior to previous results, revealing that they have great potential in applications relating to highly sensitive gas sensors.

  18. Enhanced monolayer MoS2/InP heterostructure solar cells by graphene quantum dots

    Science.gov (United States)

    Wang, Peng; Lin, Shisheng; Ding, Guqiao; Li, Xiaoqiang; Wu, Zhiqian; Zhang, Shengjiao; Xu, Zhijuan; Xu, Sen; Lu, Yanghua; Xu, Wenli; Zheng, Zheyang

    2016-04-01

    We demonstrate significantly improved photovoltaic response of monolayer molybdenum disulfide (MoS2)/indium phosphide (InP) van der Waals heterostructure induced by graphene quantum dots (GQDs). Raman and photoluminescence measurements indicate that effective charge transfer takes place between GQDs and MoS2, which results in n-type doping of MoS2. The doping effect increases the barrier height at the MoS2/InP heterojunction, thus the averaged power conversion efficiency of MoS2/InP solar cells is improved from 2.1% to 4.1%. The light induced doping by GQD provides a feasible way for developing more efficient MoS2 based heterostructure solar cells.

  19. Enhanced photoresponse of monolayer molybdenum disulfide (MoS2) based on microcavity structure

    Science.gov (United States)

    Lu, Yanan; Yang, Guofeng; Wang, Fuxue; Lu, Naiyan

    2018-05-01

    There is an increasing interest in using monolayer molybdenum disulfide (MoS2) for optoelectronic devices because of its inherent direct band gap characteristics. However, the weak absorption of monolayer MoS2 restricts its applications, novel concepts need to be developed to address the weakness. In this work, monolayer MoS2 monolithically integrates with plane microcavity structure, which is formed by the top and bottom chirped distributed Bragg reflector (DBR), is demonstrated to improve the absorption of MoS2. The optical absorption is 17-fold enhanced, reaching values over 70% at work wavelength. Moreover, the monolayer MoS2-based photodetector device with microcavity presents a significantly increased photoresponse, demonstrating its promising prospects in MoS2-based optoelectronic devices.

  20. Transport properties of hydrogen passivated silicon nanotubes and silicon nanotube field effect transistors

    KAUST Repository

    Montes Muñoz, Enrique

    2017-01-24

    We investigate the electronic transport properties of silicon nanotubes attached to metallic electrodes from first principles, using density functional theory and the non-equilibrium Green\\'s function method. The influence of the surface termination is studied as well as the dependence of the transport characteristics on the chirality, diameter, and length. Strong electronic coupling between nanotubes and electrodes is found to be a general feature that results in low contact resistance. The conductance in the tunneling regime is discussed in terms of the complex band structure. Silicon nanotube field effect transistors are simulated by applying a uniform potential gate. Our results demonstrate very high values of transconductance, outperforming the best commercial silicon field effect transistors, combined with low values of sub-threshold swing.

  1. Reversible logic gates on Physarum Polycephalum

    International Nuclear Information System (INIS)

    Schumann, Andrew

    2015-01-01

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum

  2. Demonstration of a Quantum Nondemolition Sum Gate

    DEFF Research Database (Denmark)

    Yoshikawa, J.; Miwa, Y.; Huck, Alexander

    2008-01-01

    The sum gate is the canonical two-mode gate for universal quantum computation based on continuous quantum variables. It represents the natural analogue to a qubit C-NOT gate. In addition, the continuous-variable gate describes a quantum nondemolition (QND) interaction between the quadrature...

  3. Visualizing a silicon quantum computer

    International Nuclear Information System (INIS)

    Sanders, Barry C; Hollenberg, Lloyd C L; Edmundson, Darran; Edmundson, Andrew

    2008-01-01

    Quantum computation is a fast-growing, multi-disciplinary research field. The purpose of a quantum computer is to execute quantum algorithms that efficiently solve computational problems intractable within the existing paradigm of 'classical' computing built on bits and Boolean gates. While collaboration between computer scientists, physicists, chemists, engineers, mathematicians and others is essential to the project's success, traditional disciplinary boundaries can hinder progress and make communicating the aims of quantum computing and future technologies difficult. We have developed a four minute animation as a tool for representing, understanding and communicating a silicon-based solid-state quantum computer to a variety of audiences, either as a stand-alone animation to be used by expert presenters or embedded into a longer movie as short animated sequences. The paper includes a generally applicable recipe for successful scientific animation production.

  4. Visualizing a silicon quantum computer

    Science.gov (United States)

    Sanders, Barry C.; Hollenberg, Lloyd C. L.; Edmundson, Darran; Edmundson, Andrew

    2008-12-01

    Quantum computation is a fast-growing, multi-disciplinary research field. The purpose of a quantum computer is to execute quantum algorithms that efficiently solve computational problems intractable within the existing paradigm of 'classical' computing built on bits and Boolean gates. While collaboration between computer scientists, physicists, chemists, engineers, mathematicians and others is essential to the project's success, traditional disciplinary boundaries can hinder progress and make communicating the aims of quantum computing and future technologies difficult. We have developed a four minute animation as a tool for representing, understanding and communicating a silicon-based solid-state quantum computer to a variety of audiences, either as a stand-alone animation to be used by expert presenters or embedded into a longer movie as short animated sequences. The paper includes a generally applicable recipe for successful scientific animation production.

  5. Visualizing a silicon quantum computer

    Energy Technology Data Exchange (ETDEWEB)

    Sanders, Barry C [Institute for Quantum Information Science, University of Calgary, Calgary, Alberta T2N 1N4 (Canada); Hollenberg, Lloyd C L [ARC Centre of Excellence for Quantum Computer Technology, School of Physics, University of Melbourne, Victoria 3010 (Australia); Edmundson, Darran; Edmundson, Andrew [EDM Studio Inc., Level 2, 850 16 Avenue SW, Calgary, Alberta T2R 0S9 (Canada)], E-mail: bsanders@qis.ucalgary.ca, E-mail: lloydch@unimelb.edu.au, E-mail: darran@edmstudio.com

    2008-12-15

    Quantum computation is a fast-growing, multi-disciplinary research field. The purpose of a quantum computer is to execute quantum algorithms that efficiently solve computational problems intractable within the existing paradigm of 'classical' computing built on bits and Boolean gates. While collaboration between computer scientists, physicists, chemists, engineers, mathematicians and others is essential to the project's success, traditional disciplinary boundaries can hinder progress and make communicating the aims of quantum computing and future technologies difficult. We have developed a four minute animation as a tool for representing, understanding and communicating a silicon-based solid-state quantum computer to a variety of audiences, either as a stand-alone animation to be used by expert presenters or embedded into a longer movie as short animated sequences. The paper includes a generally applicable recipe for successful scientific animation production.

  6. Highly sensitive MoS2 photodetectors with graphene contacts

    Science.gov (United States)

    Han, Peize; St. Marie, Luke; Wang, Qing X.; Quirk, Nicholas; El Fatimy, Abdel; Ishigami, Masahiro; Barbara, Paola

    2018-05-01

    Two-dimensional materials such as graphene and transition metal dichalcogenides (TMDs) are ideal candidates to create ultra-thin electronics suitable for flexible substrates. Although optoelectronic devices based on TMDs have demonstrated remarkable performance, scalability is still a significant issue. Most devices are created using techniques that are not suitable for mass production, such as mechanical exfoliation of monolayer flakes and patterning by electron-beam lithography. Here we show that large-area MoS2 grown by chemical vapor deposition and patterned by photolithography yields highly sensitive photodetectors, with record shot-noise-limited detectivities of 8.7 × 1014 Jones in ambient condition and even higher when sealed with a protective layer. These detectivity values are higher than the highest values reported for photodetectors based on exfoliated MoS2. We study MoS2 devices with gold electrodes and graphene electrodes. The devices with graphene electrodes have a tunable band alignment and are especially attractive for scalable ultra-thin flexible optoelectronics.

  7. Band structural properties of MoS2 (molybdenite)

    International Nuclear Information System (INIS)

    Gupta, V.P.

    1980-01-01

    Semiconductivity and superconductivity in MoS 2 (molybdenite) can be understood in terms of the band structure of MoS 2 . The band structural properties of MoS 2 are presented here. The energy dependence of nsub(eff) and epsilon(infinity)sub(eff) is investigated. Using calculated values of nsub(eff) and epsilon(infinity)sub(eff), the Penn gap has been determined. The value thus obtained is shown to be in good agreement with the reflectivity data and also with the value obtained from the band structure. The Ravindra and Srivastava formula has been shown to give values for the isobaric temperature gradient of Esub(G)[(deltaEsub(G)/deltaT)sub(P)], which are in agreement with the experimental data, and the contribution to (deltaEsub(G)/deltaT)sub(P) due to the electron lattice interaction has been evaluated. In addition, the electronic polarizability has been calculated using a modified Lorentz-Lorenz relation. (author)

  8. Study on the performance of MoS2 modified PTFE composites by molding process

    Science.gov (United States)

    Ma, Weiqiang; Hou, Genliang; Bi, Song; Li, Ping; Li, Penghui

    2017-10-01

    MoS2 filled PTFE composites were prepared by cold pressing and sintering molding. The compressive and creep properties of composite materials were analyzed by controlling the size of molded composites during molding. The results show that the composites have the best compressive and creep resistance when the molding pressure is 55 MPa in the MoS2 composites with 15% mass fraction, which is a practical reference for the preparation of MoS2-modified PTFE composites.

  9. Charge Separation at Mixed-Dimensional Single and Multilayer MoS2/Silicon Nanowire Heterojunctions.

    Science.gov (United States)

    Henning, Alex; Sangwan, Vinod K; Bergeron, Hadallia; Balla, Itamar; Sun, Zhiyuan; Hersam, Mark C; Lauhon, Lincoln J

    2018-05-16

    Layered two-dimensional (2-D) semiconductors can be combined with other low-dimensional semiconductors to form nonplanar mixed-dimensional van der Waals (vdW) heterojunctions whose charge transport behavior is influenced by the heterojunction geometry, providing a new degree of freedom to engineer device functions. Toward that end, we investigated the photoresponse of Si nanowire/MoS 2 heterojunction diodes with scanning photocurrent microscopy and time-resolved photocurrent measurements. Comparison of n-Si/MoS 2 isotype heterojunctions with p-Si/MoS 2 heterojunction diodes under varying biases shows that the depletion region in the p-n heterojunction promotes exciton dissociation and carrier collection. We measure an instrument-limited response time of 1 μs, which is 10 times faster than the previously reported response times for planar Si/MoS 2 devices, highlighting the advantages of the 1-D/2-D heterojunction. Finite element simulations of device models provide a detailed understanding of how the electrostatics affect charge transport in nanowire/vdW heterojunctions and inform the design of future vdW heterojunction photodetectors and transistors.

  10. Deep Gate Recurrent Neural Network

    Science.gov (United States)

    2016-11-22

    and Fred Cummins. Learning to forget: Continual prediction with lstm . Neural computation, 12(10):2451–2471, 2000. Alex Graves. Generating sequences...DSGU) and Simple Gated Unit (SGU), which are structures for learning long-term dependencies. Compared to traditional Long Short-Term Memory ( LSTM ) and...Gated Recurrent Unit (GRU), both structures require fewer parameters and less computation time in sequence classification tasks. Unlike GRU and LSTM

  11. Bill Gates vil redde Folkeskolen

    DEFF Research Database (Denmark)

    Fejerskov, Adam Moe

    2014-01-01

    Det amerikanske uddannelsessystem bliver for tiden udsat for hård kritik, ledt an af Microsoft stifteren Bill Gates. Gates har indtil videre brugt 3 mia. kroner på at skabe opbakning til tiltag som præstationslønning af lærere og strømlining af pensum på tværs af alle skoler i landet...

  12. Latest design of gate valves

    Energy Technology Data Exchange (ETDEWEB)

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  13. CMOS gate array characterization procedures

    Science.gov (United States)

    Spratt, James P.

    1993-09-01

    Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

  14. Analysis of optical and electronic properties of MoS2 for optoelectronics and FET applications

    Science.gov (United States)

    Ullah, Muhammad S.; Yousuf, Abdul Hamid Bin; Es-Sakhi, Azzedin D.; Chowdhury, Masud H.

    2018-04-01

    Molybdenum disulfide (MoS2) is considered as a promising alternative to conventional semiconductor materials that used in the IC industry because of its novel properties. In this paper, we explore the optical and electronic properties of MoS2 for photodetector and transistors applications. This simulation is done using `DFT materials properties simulator'. Our findings show that mono- and multi-layer MoS2 is suitable for conventional and tunnel FET applications due to direct and indirect band-gap respectively. The bulk MoS2 crystal, which are composed of stacked layers have indirect bandgap and mono-layer MoS2 crystal form direct bandgap at the K-point of Brillouin zone. Indirect bandgap of bulk MoS2 crystal implies that phonons need to be involved in band-to-band tunneling (BTBT) process. Degenerately doped semiconductor, which is basically spinning the Fermi level, changing the DOS profile, and thinning the indirect bandgap that allow tunneling from valence band to conduction band. The optical properties of MoS2 is explored in terms of Absorption coefficient, extinction coefficient and refractive index. Our results shows that a MoS2 based photodetector can be fabricate to detect light in the visible range (below 500nm). It is also observed that the MoS2 is most sensitive for the light of wavelength 450nm.

  15. Interfacial chemical reactions between MoS2 lubricants and bearing materials

    Science.gov (United States)

    Zabinski, J. S.; Tatarchuk, B. J.

    1989-01-01

    XPS and conversion-electron Moessbauer spectroscopy (CEMS) were used to examine iron that was deposited on the basal plane of MoS2 single crystals and subjected to vacuum annealing, oxidizing, and reducing environments. Iron either intercalated into the MoS2 structure or formed oriented iron sulfides, depending on the level of excess S in the MoS2 structure. CEMS data demonstrated that iron sulfide crystal structures preferentially aligned with respect to the MoS2 basal plane, and that alignment (and potentially adhesion) could be varied by appropriate high-temperature annealing procedures.

  16. Sequential structural and optical evolution of MoS2 by chemical synthesis and exfoliation

    Science.gov (United States)

    Kim, Ju Hwan; Kim, Jungkil; Oh, Si Duck; Kim, Sung; Choi, Suk-Ho

    2015-06-01

    Various types of MoS2 structures are successfully obtained by using economical and facile sequential synthesis and exfoliation methods. Spherically-shaped lumps of multilayer (ML) MoS2 are prepared by using a conventional hydrothermal method and were subsequently 1st-exfoliated in hydrazine while being kept in autoclave to be unrolled and separated into five-to-six-layer MoS2 pieces of several-hundred nm in size. The MoS2 MLs are 2nd-exfoliated in sodium naphthalenide under an Ar ambient to finally produce bilayer MoS2 crystals of ~100 nm. The sequential exfoliation processes downsize MoS2 laterally and reduce its number of layers. The three types of MoS2 allotropes exhibit particular optical properties corresponding to their structural differences. These results suggest that two-dimensional MoS2 crystals can be prepared by employing only chemical techniques without starting from high-pressure-synthesized bulk MoS2 crystals.

  17. Suspended graphene devices with local gate control on an insulating substrate

    International Nuclear Information System (INIS)

    Ong, Florian R; Cui, Zheng; Vojvodin, Cameron; Papaj, Michał; Deng, Chunqing; Bal, Mustafa; Lupascu, Adrian; Yurtalan, Muhammet A; Orgiazzi, Jean-Luc F X

    2015-01-01

    We present a fabrication process for graphene-based devices where a graphene monolayer is suspended above a local metallic gate placed in a trench. As an example we detail the fabrication steps of a graphene field-effect transistor. The devices are built on a bare high-resistivity silicon substrate. At temperatures of 77 K and below, we observe the field-effect modulation of the graphene resistivity by a voltage applied to the gate. This fabrication approach enables new experiments involving graphene-based superconducting qubits and nano-electromechanical resonators. The method is applicable to other two-dimensional materials. (paper)

  18. Channel mobility degradation and charge trapping in high-k/metal gate NMOSFETs

    International Nuclear Information System (INIS)

    Mathew, Shajan; Bera, L.K.; Balasubramanian, N.; Joo, M.S.; Cho, B.J.

    2004-01-01

    NMOSFETs with Metalo-Organic Chemical Vapor Deposited (MOCVD) HfAlO gate dielectric and TiN metal gate have been fabricated. Channel electron mobility was measured using the split-CV method and compared with SiO 2 devices. All high-k devices showed lower mobility compared with SiO 2 reference devices. High-k MOSFETs exhibited significant charge trapping and threshold instability. Threshold voltage recovery with time was studied on devices with oxide/nitride interfacial layer between high-k film and silicon substrate

  19. Buried oxide layer in silicon

    Science.gov (United States)

    Sadana, Devendra Kumar; Holland, Orin Wayne

    2001-01-01

    A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

  20. Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

    Science.gov (United States)

    Navlakha, Nupur; Kranti, Abhinav

    2017-07-01

    Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

  1. Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices

    Science.gov (United States)

    Liao, P. H.; Peng, K. P.; Lin, H. C.; George, T.; Li, P. W.

    2018-05-01

    We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5–95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5–4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1‑x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1‑x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core ‘building block’ required for the fabrication of Ge-based MOS devices.

  2. A SiC MOSFET Power Module With Integrated Gate Drive for 2.5 MHz Class E Resonant Converters

    DEFF Research Database (Denmark)

    Jørgensen, Asger Bjørn; Nair, Unnikrishnan Raveendran; Munk-Nielsen, Stig

    2018-01-01

    Industrial processes are still relying on high frequency converters based on vacuum tubes. Emerging silicon carbide semiconductor devices have potential to replace vacuum tubes and bring benefits for converters in the high frequency range. At high switching frequencies hard-switched gate drivers...

  3. MoS2-modified ZnO quantum dots nanocomposite: Synthesis and ultrafast humidity response

    International Nuclear Information System (INIS)

    Ze, Lu; Yueqiu, Gong; Xujun, Li; Yong, Zhang

    2017-01-01

    Highlights: • MoS 2 @ZnO QDs composite structure was synthesized by two-steps methods. • Ultrafast humidity sensing response is achieved by MoS 2 @ZnO QDs humidity sensor. • Sensor performs excellent cycle stability from 11% to 95% RH. • Humidity sensor could detect wide humidity range (11–95%). - Abstract: In this work, ZnO quantum dots (QDs), layered MoS 2 and MoS 2 -modified ZnO QDs (MoS 2 @ZnO QDs) nanocomposite were synthesized and then applied as humidity sensor. The crystal structure, morphology and element distribution of ZnO QDs, MoS 2 and MoS 2 @ZnO QDs were characterized by X-ray diffraction, scanning electron microscopy, transmission electron microscopy and energy dispersive X-ray spectrometry, respectively. The humidity sensing characteristics of the MoS 2 and MoS 2 @ZnO QDs against various relative humidity were measured at room temperature. The results show that the MoS 2 @ZnO QDs sensor exhibits high sensitivity with an impedance variation of three or four orders of magnitude to relative humidity range of 11–95% and it exhibits a short response-recovery time (1 s for adsorption and 20 s for desorption) and excellent repeatability. The mechanisms of the excellent performance for humidity sensing of MoS 2 @ZnO QDs sensor were discussed based on its impedance properties. Our work could offer guidelines to design higher performance especially ultrafast humidity response sensor utilizing the nanocomposite structure with two dimensional material and QDs.

  4. Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method

    Science.gov (United States)

    Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

    2018-05-01

    In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

  5. Development of an oxidized porous silicon vacuum microtriode

    Energy Technology Data Exchange (ETDEWEB)

    Smith, II, Don Deewayne [Texas A & M Univ., College Station, TX (United States)

    1994-05-01

    In order to realize a high-power microwave amplifier design known as a gigatron, a gated field emission array must be developed that can deliver a high-intensity electron beam at gigahertz frequencies. No existing field emission device meets the requirements for a gigatron cathode. In the present work, a porous silicon-based approach is evaluated. The use of porous silicon reduces the size of a single emitter to the nanometer scale, and a true two-dimensional array geometry can be approached. A wide number of applications for such a device exist in various disciplines. Oxidized porous silicon vacuum diodes were first developed in 1990. No systematic study had been done to characterize the performance of these devices as a function of the process parameters. The author has done the first such study, fabricating diodes from p<100>, p<111>, and n<100> silicon substrates. Anodization current densities from 11 mA/cm2 to 151 mA/cm2 were used, and Fowler-Nordheim behavior was observed in over 80% of the samples. In order to effectively adapt this technology to mainstream vacuum microelectronic applications, a means of creating a gated triodic structure must be found. No previous attempts had successfully yielded such a device. The author has succeeded in utilizing a novel metallization method to fabricate the first operational oxidized porous silicon vacuum microtriodes, and results are encouraging.

  6. New opening hours of the gates

    CERN Multimedia

    GS Department

    2009-01-01

    Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

  7. Interfacial characteristics and leakage current transfer mechanisms in organometal trihalide perovskite gate-controlled devices via doping of PCBM

    International Nuclear Information System (INIS)

    Wang, Yucheng; Zhang, Yuming; Liu, Yintao; Pang, Tiqiang; Luan, Suzhen; Jia, Renxu; Hu, Ziyang; Zhu, Yuejin

    2017-01-01

    Two types of perovskite (with and without doping of PCBM) based metal-oxide-semiconductor (MOS) gate-controlled devices were fabricated and characterized. The study of the interfacial characteristics and charge transfer mechanisms by doping of PCBM were analyzed by material and electrical measurements. Doping of PCBM does not affect the size and crystallinity of perovskite films, but has an impact on carrier extraction in perovskite MOS devices. The electrical hysteresis observed in capacitance–voltage and current–voltage measurements can be alleviated by doping of PCBM. Experimental results demonstrate that extremely low trap densities are found for the perovskite device without doping, while the doped sample leads to higher density of interface state. Three mechanisms including Ohm’s law, trap-filled-limit (TFL) emission, and child’s law were used to analyze possible charge transfer mechanisms. Ohm’s law mechanism is well suitable for charge transfer of both the perovskite MOS devices under light condition at large voltage, while TFL emission well addresses the behavior of charge transfer under dark at small voltage. This change of charge transfer mechanism is attributed to the impact of the ion drift within perovskites. (paper)

  8. Principles to Products: Toward Realizing MOS 2.0

    Science.gov (United States)

    Bindschadler, Duane L.; Delp, Christopher L.

    2012-01-01

    This is a report on the Operations Revitalization Initiative, part of the ongoing NASA-funded Advanced Multi-Mission Operations Systems (AMMOS) program. We are implementing products that significantly improve efficiency and effectiveness of Mission Operations Systems (MOS) for deep-space missions. We take a multi-mission approach, in keeping with our organization's charter to "provide multi-mission tools and services that enable mission customers to operate at a lower total cost to NASA." Focusing first on architectural fundamentals of the MOS, we review the effort's progress. In particular, we note the use of stakeholder interactions and consideration of past lessons learned to motivate a set of Principles that guide the evolution of the AMMOS. Thus guided, we have created essential patterns and connections (detailed in companion papers) that are explicitly modeled and support elaboration at multiple levels of detail (system, sub-system, element...) throughout a MOS. This architecture is realized in design and implementation products that provide lifecycle support to a Mission at the system and subsystem level. The products include adaptable multi-mission engineering documentation that describes essentials such as operational concepts and scenarios, requirements, interfaces and agreements, information models, and mission operations processes. Because we have adopted a model-based system engineering method, these documents and their contents are meaningfully related to one another and to the system model. This means they are both more rigorous and reusable (from mission to mission) than standard system engineering products. The use of models also enables detailed, early (e.g., formulation phase) insight into the impact of changes (e.g., to interfaces or to software) that is rigorous and complete, allowing better decisions on cost or technical trades. Finally, our work provides clear and rigorous specification of operations needs to software developers, further

  9. A Route to Permanent Valley Polarization in Monolayer MoS2

    KAUST Repository

    Singh, Nirpendra

    2016-10-24

    Realization of permanent valley polarization in Cr-doped monolayer MoS2 is found to be unfeasible because of extended moment formation. Introduction of an additional hole is suggested as a viable solution. V-doped monolayer MoS2 is demonstrated to sustain permanent valley polarization and therefore can serve as a prototype material for valleytronics.

  10. Few-layer MoS2 as nitrogen protective barrier

    Science.gov (United States)

    Akbali, B.; Yanilmaz, A.; Tomak, A.; Tongay, S.; Çelebi, C.; Sahin, H.

    2017-10-01

    We report experimental and theoretical investigations of the observed barrier behavior of few-layer MoS2 against nitrogenation. Owing to its low-strength shearing, low friction coefficient, and high lubricity, MoS2 exhibits the demeanor of a natural N-resistant coating material. Raman spectroscopy is done to determine the coating capability of MoS2 on graphene. Surface morphology of our MoS2/graphene heterostructure is characterized by using optical microscopy, scanning electron microscopy, and atomic force microscopy. In addition, density functional theory-based calculations are performed to understand the energy barrier performance of MoS2 against nitrogenation. The penetration of nitrogen atoms through a defect-free MoS2 layer is prevented by a very high vertical diffusion barrier, indicating that MoS2 can serve as a protective layer for the nitrogenation of graphene. Our experimental and theoretical results show that MoS2 material can be used both as an efficient nanocoating material and as a nanoscale mask for selective nitrogenation of graphene layer.

  11. Hydrothermal synthesis of flower-like MoS2 nanospheres for electrochemical supercapacitors.

    Science.gov (United States)

    Zhou, Xiaoping; Xu, Bin; Lin, Zhengfeng; Shu, Dong; Ma, Lin

    2014-09-01

    Flower-like MoS2 nanospheres were synthesized by a hydrothermal route. The structure and surface morphology of the as-prepared MoS2 was characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). The supercapacitive behavior of MoS2 in 1 M KCl electrolyte was studied by means of cyclic voltammetry (CV), constant current charge-discharge cycling (CD) and electrochemical impedance spectroscopy (EIS). The XRD results indicate that the as-prepared MoS2 has good crystallinity. SEM images show that the MoS2 nanospheres have uniform sizes with mean diameter about 300 nm. Many nanosheets growing on the surface make the MoS2 nanospheres to be a flower-like structure. The specific capacitance of MoS2 is 122 F x g(-1) at 1 A x g(-1) or 114 F x g(-1) at 2 mv s(-1). All the experimental results indicate that MoS2 is a promising electrode material for electrochemical supercapacitors.

  12. Morphology-controlled synthesis of MoS2 nanostructures with different lithium storage properties

    International Nuclear Information System (INIS)

    Wang, Xiwen; Zhang, Zhian; Chen, Yaqiong; Qu, Yaohui; Lai, Yanqing; Li, Jie

    2014-01-01

    Highlights: • MoS 2 nanospheres, nanoribbons and nanoparticles were prepared by hydrothermal method. • The surfactant and temperature control the shape and crystal structure of MoS 2 . • MoS 2 nanospheres exhibit the excellent lithium storage property. - Abstract: A one-step hydrothermal process was employed to prepare a series of MoS 2 nanostructures via simply altering the surfactant as soft template and hydrothermal reaction temperature. Three kinds of MoS 2 nanostructures (three-dimensional (3D) hierarchical nanospheres, one-dimensional (1D) nanoribbons, and large aggregated nanoparticles) were successfully achieved and investigated well by X-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), high resolution transmission electron microscopy (HRTEM), and Brunauer–Emmett–Teller analysis (BET). Electrochemical tests reveal that these MoS 2 samples could deliver high initial discharge capacities (higher than 1050.0 mA h g −1 ), but various cycling performances. The hierarchical MoS 2 nanospheres assembled by sheet-like subunits show the highest specific capacity of 1355.1 mA h g −1 , and 66.8% of which can be retained after 50 cycles. The good lithium storage property of hierarchical MoS 2 nanospheres can be attributed to the higher electrolyte/MoS 2 contact area and stable 3D layered structure

  13. The Interface between Gd and Monolayer MoS2: A First-Principles Study

    KAUST Repository

    Zhang, Xuejing; Mi, Wenbo; Wang, Xiaocha; Cheng, Yingchun; Schwingenschlö gl, Udo

    2014-01-01

    We analyze the electronic structure of interfaces between two-, four- and six-layer Gd(0001) and monolayer MoS2 by first-principles calculations. Strong chemical bonds shift the Fermi energy of MoS2 upwards into the conduction band. At the surface

  14. Mos1 transposon-based transformation of fish cell lines using baculoviral vectors

    International Nuclear Information System (INIS)

    Yokoo, Masako; Fujita, Ryosuke; Nakajima, Yumiko; Yoshimizu, Mamoru; Kasai, Hisae; Asano, Shin-ichiro; Bando, Hisanori

    2013-01-01

    Highlights: •The baculovirus vector infiltrates the cells of economic important fishes. •Drosophila Mos1 transposase expressed in fish cells maintains its ability to localize to the nucleus. •The baculoviral vector carrying Mos1 is a useful tool to stably transform fish cells. -- Abstract: Drosophila Mos1 belongs to the mariner family of transposons, which are one of the most ubiquitous transposons among eukaryotes. We first determined nuclear transportation of the Drosophila Mos1-EGFP fusion protein in fish cell lines because it is required for a function of transposons. We next constructed recombinant baculoviral vectors harboring the Drosophila Mos1 transposon or marker genes located between Mos1 inverted repeats. The infectivity of the recombinant virus to fish cells was assessed by monitoring the expression of a fluorescent protein encoded in the viral genome. We detected transgene expression in CHSE-214, HINAE, and EPC cells, but not in GF or RTG-2 cells. In the co-infection assay of the Mos1-expressing virus and reporter gene-expressing virus, we successfully transformed CHSE-214 and HINAE cells. These results suggest that the combination of a baculovirus and Mos1 transposable element may be a tool for transgenesis in fish cells

  15. Atomic-scale structure of single-layer MoS2 nanoclusters

    DEFF Research Database (Denmark)

    Helveg, S.; Lauritsen, J. V.; Lægsgaard, E.

    2000-01-01

    We have studied using scanning tunneling microscopy (STM) the atomic-scale realm of molybdenum disulfide (MoS2) nanoclusters, which are of interest as a model system in hydrodesulfurization catalysis. The STM gives the first real space images of the shape and edge structure of single-layer MoS2...

  16. Mos1 transposon-based transformation of fish cell lines using baculoviral vectors

    Energy Technology Data Exchange (ETDEWEB)

    Yokoo, Masako [Laboratory of Applied Molecular Entomology, Division of Applied Bioscience, Research Faculty of Agriculture, Hokkaido University, Sapporo 060-8589 (Japan); Fujita, Ryosuke [Laboratory of Applied Molecular Entomology, Division of Applied Bioscience, Research Faculty of Agriculture, Hokkaido University, Sapporo 060-8589 (Japan); Innate Immunity Laboratory, Graduate School of Life Science and Creative Research Institution, Hokkaido University, Sapporo 001-0021 (Japan); Nakajima, Yumiko [Functional Genomics Group, COMB, Tropical Biosphere Research Center, University of the Ryukyus, Okinawa 903-0213 (Japan); Yoshimizu, Mamoru; Kasai, Hisae [Faculty of Fisheries Sciences, Hokkaido University, Hakodate 041-8611 (Japan); Asano, Shin-ichiro [Laboratory of Applied Molecular Entomology, Division of Applied Bioscience, Research Faculty of Agriculture, Hokkaido University, Sapporo 060-8589 (Japan); Bando, Hisanori, E-mail: hban@abs.agr.hokudai.ac.jp [Laboratory of Applied Molecular Entomology, Division of Applied Bioscience, Research Faculty of Agriculture, Hokkaido University, Sapporo 060-8589 (Japan)

    2013-09-13

    Highlights: •The baculovirus vector infiltrates the cells of economic important fishes. •Drosophila Mos1 transposase expressed in fish cells maintains its ability to localize to the nucleus. •The baculoviral vector carrying Mos1 is a useful tool to stably transform fish cells. -- Abstract: Drosophila Mos1 belongs to the mariner family of transposons, which are one of the most ubiquitous transposons among eukaryotes. We first determined nuclear transportation of the Drosophila Mos1-EGFP fusion protein in fish cell lines because it is required for a function of transposons. We next constructed recombinant baculoviral vectors harboring the Drosophila Mos1 transposon or marker genes located between Mos1 inverted repeats. The infectivity of the recombinant virus to fish cells was assessed by monitoring the expression of a fluorescent protein encoded in the viral genome. We detected transgene expression in CHSE-214, HINAE, and EPC cells, but not in GF or RTG-2 cells. In the co-infection assay of the Mos1-expressing virus and reporter gene-expressing virus, we successfully transformed CHSE-214 and HINAE cells. These results suggest that the combination of a baculovirus and Mos1 transposable element may be a tool for transgenesis in fish cells.

  17. Non-stoichiometry of MoS2 phase prepared by sputtering

    International Nuclear Information System (INIS)

    Ito, T.; Nakajima, K.

    1978-01-01

    The lattice parameters and S/Mo atomic ratio in sputtered MoS 2 films have been examined as a function of sputtering conditions, especially the vacuum pressure in the chamber. It was found that the deposited films had a defect MoS 2 structure ranging from 1.6 to 2 in S/Mo ratio, depending on the pressure. (author)

  18. MOS current gain cells with electronically variable gain and constant bandwidth

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Seevinck, Evert

    1989-01-01

    Two MOS current gain cells are proposed that provide linear amplification of currents supplied by several linear MOS V-I converters. The gain is electronically variable by a voltage or a current and can be made insensitive to temperature and IC processing. The gain cells have a constant

  19. A Confirmatory Factor Analysis of an Abbreviated Social Support Instrument: The MOS-SSS

    Science.gov (United States)

    Gjesfjeld, Christopher D.; Greeno, Catherine G.; Kim, Kevin H.

    2008-01-01

    Objective: Confirm the factor structure of the original 18-item Medical Outcome Study Social Support Survey (MOS-SSS) as well as two abbreviated versions in a sample of mothers with a child in mental health treatment. Method: The factor structure, internal consistency, and concurrent validity of the MOS-SSS were assessed using a convenience sample…

  20. Optimal inverter logic gate using 10-nm double gate-all-around (DGAA transistor with asymmetric channel width

    Directory of Open Access Journals (Sweden)

    Myunghwan Ryu

    2016-01-01

    Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.

  1. Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

    Science.gov (United States)

    Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

    2010-01-01

    Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

  2. Respiratory gating in cardiac PET

    DEFF Research Database (Denmark)

    Lassen, Martin Lyngby; Rasmussen, Thomas; Christensen, Thomas E

    2017-01-01

    BACKGROUND: Respiratory motion due to breathing during cardiac positron emission tomography (PET) results in spatial blurring and erroneous tracer quantification. Respiratory gating might represent a solution by dividing the PET coincidence dataset into smaller respiratory phase subsets. The aim...... of our study was to compare the resulting imaging quality by the use of a time-based respiratory gating system in two groups administered either adenosine or dipyridamole as the pharmacological stress agent. METHODS AND RESULTS: Forty-eight patients were randomized to adenosine or dipyridamole cardiac...... stress (82)RB-PET. Respiratory rates and depths were measured by a respiratory gating system in addition to registering actual respiratory rates. Patients undergoing adenosine stress showed a decrease in measured respiratory rate from initial to later scan phase measurements [12.4 (±5.7) vs 5.6 (±4...

  3. Robustness of holonomic quantum gates

    International Nuclear Information System (INIS)

    Solinas, P.; Zanardi, P.; Zanghi, N.

    2005-01-01

    Full text: If the driving field fluctuates during the quantum evolution this produces errors in the applied operator. The holonomic (and geometrical) quantum gates are believed to be robust against some kind of noise. Because of the geometrical dependence of the holonomic operators can be robust against this kind of noise; in fact if the fluctuations are fast enough they cancel out leaving the final operator unchanged. I present the numerical studies of holonomic quantum gates subject to this parametric noise, the fidelity of the noise and ideal evolution is calculated for different noise correlation times. The holonomic quantum gates seem robust not only for fast fluctuating fields but also for slow fluctuating fields. These results can be explained as due to the geometrical feature of the holonomic operator: for fast fluctuating fields the fluctuations are canceled out, for slow fluctuating fields the fluctuations do not perturb the loop in the parameter space. (author)

  4. A new optimized self-firing mos-thyristor device

    Energy Technology Data Exchange (ETDEWEB)

    Breil, M.; Sanchez, J.L.; Austin, P.; Laur, J.P.

    1998-12-01

    In this paper, a new integrated self-firing and controlled turn-off MOS-thyristor structure is investigated. An analytical model describing the turn-off operation and parasitic latch-up has been developed, allowing to highlight and optimize the physical and geometrical parameters acting upon main electrical characteristics. The analytical model is validated by 2D simulations using PISCES. The technological fabrication process is optimized by 2D simulations using SUPREM IV. Electrical characterization results of fabricated test structures are presented. (authors) 6 refs.

  5. Atomic and electronic structure of MoS2 nanoparticles

    DEFF Research Database (Denmark)

    Bollinger, Mikkel; Jacobsen, Karsten Wedel; Nørskov, Jens Kehlet

    2003-01-01

    Using density-functional theory (DFT) we present a detailed theoretical study of MoS2 nanoparticles. We focus on the edge structures, and a number of different edge terminations are investigated. Several, but not all, of these configurations have one-dimensional metallic states localized at the e...... and the composition of the gas phase. Using the Tersoff-Hamann formalism, scanning-tunneling microscopy (STM) images of the edges are simulated for direct comparison with recent STM experiments. In this way we identify the experimentally observed edge structure....

  6. Plasmon-modulated bistable four-wave mixing signals from a metal nanoparticle-monolayer MoS2 nanoresonator hybrid system

    Science.gov (United States)

    Li, Jian-Bo; Tan, Xiao-Long; Ma, Jin-Hong; Xu, Si-Qin; Kuang, Zhi-Wei; Liang, Shan; Xiao, Si; He, Meng-Dong; Kim, Nam-Chol; Luo, Jian-Hua; Chen, Li-Qun

    2018-06-01

    We present a study for the impact of exciton-phonon and exciton-plasmon interactions on bistable four-wave mixing (FWM) signals in a metal nanoparticle (MNP)-monolayer MoS2 nanoresonator hybrid system. Via tracing the FWM response we predict that, depending on the excitation conditions and the system parameters, such a system exhibits ‘U-shaped’ bistable FWM signals. We also map out bistability phase diagrams within the system’s parameter space. Especially, we show that compared with the exciton-phonon interaction, a strong exciton-plasmon interaction plays a dominant role in the generation of optical bistability, and the bistable region will be greatly broadened by shortening the distance between the MNP and the monolayer MoS2 nanoresonator. In the weak exciton-plasmon coupling regime, the impact of exciton-phonon interaction on optical bistability will become obvious. The scheme proposed may be used for building optical switches and logic-gate devices for optical computing and quantum information processing.

  7. Study of interfacial strain at the α-Al2O3/monolayer MoS2 interface by first principle calculations

    Science.gov (United States)

    Yu, Sheng; Ran, Shunjie; Zhu, Hao; Eshun, Kwesi; Shi, Chen; Jiang, Kai; Gu, Kunming; Seo, Felix Jaetae; Li, Qiliang

    2018-01-01

    With the advances in two-dimensional (2D) transition metal dichalcogenides (TMDCs) based metal-oxide-semiconductor field-effect transistor (MOSFET), the interface between the semiconductor channel and gate dielectrics has received considerable attention due to its significant impacts on the morphology and charge transport of the devices. In this study, first principle calculations were utilized to investigate the strain effect induced by the interface between crystalline α-Al2O3 (0001)/h-MoS2 monolayer. The results indicate that the 1.3 nm Al2O3 can induce a 0.3% tensile strain on the MoS2 monolayer. The strain monotonically increases with thicker dielectric layers, inducing more significant impact on the properties of MoS2. In addition, the study on temperature effect indicates that the increasing temperature induces monotonic lattice expansion. This study clearly indicates that the dielectric engineering can effectively tune the properties of 2D TMDCs, which is very attractive for nanoelectronics.

  8. Plasmon-modulated bistable four-wave mixing signals from a metal nanoparticle-monolayer MoS2 nanoresonator hybrid system.

    Science.gov (United States)

    Li, Jian-Bo; Tan, Xiao-Long; Ma, Jin-Hong; Xu, Si-Qin; Kuang, Zhi-Wei; Liang, Shan; Xiao, Si; He, Meng-Dong; Kim, Nam-Chol; Luo, Jian-Hua; Chen, Li-Qun

    2018-06-22

    We present a study for the impact of exciton-phonon and exciton-plasmon interactions on bistable four-wave mixing (FWM) signals in a metal nanoparticle (MNP)-monolayer MoS 2 nanoresonator hybrid system. Via tracing the FWM response we predict that, depending on the excitation conditions and the system parameters, such a system exhibits 'U-shaped' bistable FWM signals. We also map out bistability phase diagrams within the system's parameter space. Especially, we show that compared with the exciton-phonon interaction, a strong exciton-plasmon interaction plays a dominant role in the generation of optical bistability, and the bistable region will be greatly broadened by shortening the distance between the MNP and the monolayer MoS 2 nanoresonator. In the weak exciton-plasmon coupling regime, the impact of exciton-phonon interaction on optical bistability will become obvious. The scheme proposed may be used for building optical switches and logic-gate devices for optical computing and quantum information processing.

  9. Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

    Science.gov (United States)

    Gagnard, Xavier; Bonnaud, Olivier

    2000-08-01

    We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

  10. Confocal absorption spectral imaging of MoS2: optical transitions depending on the atomic thickness of intrinsic and chemically doped MoS2.

    Science.gov (United States)

    Dhakal, Krishna P; Duong, Dinh Loc; Lee, Jubok; Nam, Honggi; Kim, Minsu; Kan, Min; Lee, Young Hee; Kim, Jeongyong

    2014-11-07

    We performed a nanoscale confocal absorption spectral imaging to obtain the full absorption spectra (over the range 1.5-3.2 eV) within regions having different numbers of layers and studied the variation of optical transition depending on the atomic thickness of the MoS2 film. Three distinct absorption bands corresponding to A and B excitons and a high-energy background (BG) peak at 2.84 eV displayed a gradual redshift as the MoS2 film thickness increased from the monolayer, to the bilayer, to the bulk MoS2 and this shift was attributed to the reduction of the gap energy in the Brillouin zone at the K-point as the atomic thickness increased. We also performed n-type chemical doping of MoS2 films using reduced benzyl viologen (BV) and the confocal absorption spectra modified by the doping showed a strong dependence on the atomic thickness: A and B exciton peaks were greatly quenched in the monolayer MoS2 while much less effect was shown in larger thickness and the BG peak either showed very small quenching for 1 L MoS2 or remained constant for larger thicknesses. Our results indicate that confocal absorption spectral imaging can provide comprehensive information on optical transitions of microscopic size intrinsic and doped two-dimensional layered materials.

  11. Growth, structure and stability of sputter-deposited MoS2 thin films

    Directory of Open Access Journals (Sweden)

    Reinhard Kaindl

    2017-05-01

    Full Text Available Molybdenum disulphide (MoS2 thin films have received increasing interest as device-active layers in low-dimensional electronics and also as novel catalysts in electrochemical processes such as the hydrogen evolution reaction (HER in electrochemical water splitting. For both types of applications, industrially scalable fabrication methods with good control over the MoS2 film properties are crucial. Here, we investigate scalable physical vapour deposition (PVD of MoS2 films by magnetron sputtering. MoS2 films with thicknesses from ≈10 to ≈1000 nm were deposited on SiO2/Si and reticulated vitreous carbon (RVC substrates. Samples deposited at room temperature (RT and at 400 °C were compared. The deposited MoS2 was characterized by macro- and microscopic X-ray, electron beam and light scattering, scanning and spectroscopic methods as well as electrical device characterization. We find that room-temperature-deposited MoS2 films are amorphous, of smooth surface morphology and easily degraded upon moderate laser-induced annealing in ambient conditions. In contrast, films deposited at 400 °C are nano-crystalline, show a nano-grained surface morphology and are comparatively stable against laser-induced degradation. Interestingly, results from electrical transport measurements indicate an unexpected metallic-like conduction character of the studied PVD MoS2 films, independent of deposition temperature. Possible reasons for these unusual electrical properties of our PVD MoS2 thin films are discussed. A potential application for such conductive nanostructured MoS2 films could be as catalytically active electrodes in (photo-electrocatalysis and initial electrochemical measurements suggest directions for future work on our PVD MoS2 films.

  12. Evaluating Mechanical Properties of Few Layers MoS2 Nanosheets-Polymer Composites

    Directory of Open Access Journals (Sweden)

    Muhammad Bilal Khan

    2017-01-01

    Full Text Available The reinforcement effects of liquid exfoliated molybdenum disulphide (MoS2 nanosheets, dispersed in polystyrene (PS matrix, are evaluated here. The range of composites (0~0.002 volume fraction (Vf MoS2-PS is prepared via solution casting. Size selected MoS2 nanosheets (3~4 layers, with a lateral dimension L 0.5~1 µm, have improved Young’s modulus up to 0.8 GPa for 0.0002 Vf MoS2-PS as compared to 0.2 GPa observed for PS only. The ultimate tensile strength (UTS is improved considerably (~×3 with a minute addition of MoS2 nanosheets (0.00002 Vf. The MoS2 nanosheets lateral dimension and number of layers are approximated using atomic force microscopy (AFM. The composites formation is confirmed using X-ray diffraction (XRD and scanning electron microscopy (SEM. Theoretical predicted results (Halpin-Tsai model are well below the experimental findings, especially at lower concentrations. Only at maximum concentrations, the experimental and theoretical results coincide. The high aspect ratio of MoS2 nanosheets, homogeneous dispersion inside polymer, and their probable planar orientation are the possible reasons for the effective stress transfer, resulting in enhanced mechanical characteristics. Moreover, the micro-Vickers hardness (HV of the MoS2-PS is also improved from 19 (PS to 23 (0.002 Vf MoS2-PS as MoS2 nanosheets inclusion may hinder the deformation more effectively.

  13. Silicon ribbon growth by a capillary action shaping technique. Annual report (Quarterly technical progress report No. 9)

    Energy Technology Data Exchange (ETDEWEB)

    Schwuttke, G.H.; Ciszek, T.F.; Kran, A.

    1977-10-01

    Progress on the technological and economical assessment of ribbon growth of silicon by a capillary action shaping technique is reported. Progress in scale-up of the process from 50 mm to 100 mm ribbon widths is presented, the use of vitreous carbon as a crucible material is analyzed, and preliminary tests of CVD Si/sub 3/N/sub 4/ as a potential die material are reported. Diffusion length measurements by SEM, equipment and procedure for defect display under MOS structure in silicon ribbon for lifetime interpretation, and an assessment of ribbon technology are discussed. (WHK)

  14. Dual-gate operation and carrier transport in SiGe p-n junction nanowires

    Science.gov (United States)

    Delker, C. J.; Yoo, J. Y.; Bussmann, E.; Swartzentruber, B. S.; Harris, C. T.

    2017-11-01

    We investigate carrier transport in silicon-germanium nanowires with an axial p-n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source-drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source-drain configuration, current is limited by the nickel/n-side Schottky contact.

  15. Strain engineering in monolayer WS2, MoS2, and the WS2/MoS2 heterostructure

    KAUST Repository

    He, Xin; Li, Hai; Zhu, Zhiyong; Dai, Zhenyu; Yang, Yang; Yang, Peng; Zhang, Qiang; Li, Peng; Schwingenschlö gl, Udo; Zhang, Xixiang

    2016-01-01

    Mechanically exfoliated monolayers of WS2, MoS2 and their van der Waals heterostructure were fabricated on flexible substrate so that uniaxial tensile strain can be applied to the two-dimensional samples. The modification of the band structure under strain was investigated by micro-photoluminescence spectroscopy at room temperature as well as by first-principles calculations. Exciton and trion emissions were observed in both WS2 and the heterostructure at room temperature, and were redshifted by strain, indicating potential for applications in flexible electronics and optoelectronics.

  16. Strain engineering in monolayer WS2, MoS2, and the WS2/MoS2 heterostructure

    KAUST Repository

    He, Xin

    2016-10-27

    Mechanically exfoliated monolayers of WS2, MoS2 and their van der Waals heterostructure were fabricated on flexible substrate so that uniaxial tensile strain can be applied to the two-dimensional samples. The modification of the band structure under strain was investigated by micro-photoluminescence spectroscopy at room temperature as well as by first-principles calculations. Exciton and trion emissions were observed in both WS2 and the heterostructure at room temperature, and were redshifted by strain, indicating potential for applications in flexible electronics and optoelectronics.

  17. THz generation from a nanocrystalline silicon-based photoconductive device

    International Nuclear Information System (INIS)

    Daghestani, N S; Persheyev, S; Cataluna, M A; Rose, M J; Ross, G

    2011-01-01

    Terahertz generation has been achieved from a photoconductive switch based on hydrogenated nanocrystalline silicon (nc-Si:H), gated by a femtosecond laser. The nc-Si:H samples were produced by a hot wire chemical vapour deposition process, a process with low production costs owing to its higher growth rate and manufacturing simplicity. Although promising ultrafast carrier dynamics of nc-Si have been previously demonstrated, this is the first report on THz generation from a nc-Si:H material

  18. Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

    International Nuclear Information System (INIS)

    Kranti, Abhinav; Hao Ying; Armstrong, G Alastair

    2008-01-01

    In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (I on /I off ). Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices

  19. Silicon: electrochemistry and luminescence

    NARCIS (Netherlands)

    Kooij, Ernst Stefan

    1997-01-01

    The electrochemistry of crystalline and porous silicon and the luminescence from porous silicon has been studied. One chapter deals with a model for the anodic dissolution of silicon in HF solution. In following chapters both the electrochemistry and various ways of generating visible

  20. Modeling of A-DLTS Spectra of MOS Structures

    Directory of Open Access Journals (Sweden)

    Peter Hockicko

    2008-01-01

    Full Text Available Acquisition of basic characteristic of defects has become possible through a wide class of measurement techniqueswhich probe the interface, the near interface, as well as the bulk of semiconductor. Results presented here are basedessentially on the acoustic version of Deep Level Transient Spectroscopy (A-DLTS measurements. This method is based onthe acoustoelectric response effect observed at the interface. The A-DLTS uses the acoustoelectric response signal (ARSproduced by MOS structure interface when a longitudal acoustic wave propagates through a structure. The ARS is extremelysensitive to external conditions of the structure and reflects any changes in the charge distribution connected with chargedtraps. The temperature dependence of ARS after bias voltage step application is investigated and the activation energies andsome other parameters of traps at the insulator – semiconductor interface are determined. The results obtained formArrhenius plots of A-DLTS spectra of selected MOS structures are compared with results obtained from modeling of ADLTS spectra using theoretical model.