Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors
Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.
2010-01-01
Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.
The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator
Jafar, N.; Soin, N.
2009-06-01
This work presents the noise behaviour due to the applied Dual Material Gate (DMG) on the 75 nm n-channel Silicon On Insulator (SOI) device operating in the fully depletion mode, particularly for microwave circuit design. Influences of DMG properties namely the gate length ratio (L1:L2) and gate material workfunction difference (ΔΦM) as well as structural and operational parameters which are silicon thickness (TSi) and threshold voltage (VTH) setting variation on the noise performance were carried out on simulation basis using ATLAS 2D. Results show better noise performance in DMG as compare to the standard gate structure of FD-SOI devices. Higher VTH for DMG design is recommended for minimized noise figure in line with the advantage of inverse VTH roll-off characteristics for short channel effects suppression.
Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava
2009-03-01
The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.
Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors
Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.
2010-01-01
Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...
Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs
International Nuclear Information System (INIS)
Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi
2012-01-01
The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)
Memory effect in silicon time-gated single-photon avalanche diodes
International Nuclear Information System (INIS)
Dalla Mora, A.; Contini, D.; Di Sieno, L.; Tosi, A.; Boso, G.; Villa, F.; Pifferi, A.
2015-01-01
We present a comprehensive characterization of the memory effect arising in thin-junction silicon Single-Photon Avalanche Diodes (SPADs) when exposed to strong illumination. This partially unknown afterpulsing-like noise represents the main limiting factor when time-gated acquisitions are exploited to increase the measurement dynamic range of very fast (picosecond scale) and faint (single-photon) optical signals following a strong stray one. We report the dependences of this unwelcome signal-related noise on photon wavelength, detector temperature, and biasing conditions. Our results suggest that this so-called “memory effect” is generated in the deep regions of the detector, well below the depleted region, and its contribution on detector response is visible only when time-gated SPADs are exploited to reject a strong burst of photons
Memory effect in silicon time-gated single-photon avalanche diodes
Energy Technology Data Exchange (ETDEWEB)
Dalla Mora, A.; Contini, D., E-mail: davide.contini@polimi.it; Di Sieno, L. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Tosi, A.; Boso, G.; Villa, F. [Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); Pifferi, A. [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy); CNR, Istituto di Fotonica e Nanotecnologie, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)
2015-03-21
We present a comprehensive characterization of the memory effect arising in thin-junction silicon Single-Photon Avalanche Diodes (SPADs) when exposed to strong illumination. This partially unknown afterpulsing-like noise represents the main limiting factor when time-gated acquisitions are exploited to increase the measurement dynamic range of very fast (picosecond scale) and faint (single-photon) optical signals following a strong stray one. We report the dependences of this unwelcome signal-related noise on photon wavelength, detector temperature, and biasing conditions. Our results suggest that this so-called “memory effect” is generated in the deep regions of the detector, well below the depleted region, and its contribution on detector response is visible only when time-gated SPADs are exploited to reject a strong burst of photons.
Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances
International Nuclear Information System (INIS)
Suat, J.P.; Borel, J.
1976-01-01
The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr
Comments on the Huang and Taylor model of ion-implanted silicon-gate depletion-mode IGFET
International Nuclear Information System (INIS)
Marciniak, W.; Madura, H.
1985-01-01
Recently the Huang and Taylor model (HT model) of built-in channel MOS transistors has been widely used in the analysis of electronic circuits because of its relative simplicity. Huang and Taylor assumed that the effects of the finite channel thickness may be represented by an average semiconductor capacitance in series with the gate oxide capacitance. The derivation of the current-voltage characteristics is based on a linear equation of surface depleted charge density Qsub(s), which is calculated as the sheet charge of constant capacitance C-bar. This is done instead of using the exact solution of the Poisson equation, which has a rather complex form of nonlinear relationship between the charge Qsub(s) and the gate voltage. The basic equation is given. (author)
Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX
Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.
2001-12-01
We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.
Silicon photonic crystal all-optical logic gates
Energy Technology Data Exchange (ETDEWEB)
Fu, Yulan [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Hu, Xiaoyong, E-mail: xiaoyonghu@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Gong, Qihuang, E-mail: qhgong@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)
2013-01-03
All-optical logic gates, including OR, XOR, NOT, XNOR, and NAND gates, are realized theoretically in a two-dimensional silicon photonic crystal using the light beam interference effect. The ingenious photonic crystal waveguide component design, the precisely controlled optical path difference, and the elaborate device configuration ensure the simultaneous realization of five types of logic gate with low-power and a contrast ratio between the logic states of “1” and “0” as high as 20 dB. High power is not necessary for operation of these logic gate devices. This offers a simple and effective approach for the realization of integrated all-optical logic devices.
Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process
Directory of Open Access Journals (Sweden)
Avi Karsenty
2015-01-01
Full Text Available Nanoscale Gate-Recessed Channel (GRC Fully Depleted- (FD- SOI MOSFET device with a silicon channel thickness (tSi as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.
A split accumulation gate architecture for silicon MOS quantum dots
Rochette, Sophie; Rudolph, Martin; Roy, Anne-Marie; Curry, Matthew; Ten Eyck, Gregory; Dominguez, Jason; Manginell, Ronald; Pluym, Tammy; King Gamble, John; Lilly, Michael; Bureau-Oxton, Chloé; Carroll, Malcolm S.; Pioro-Ladrière, Michel
We investigate tunnel barrier modulation without barrier electrodes in a split accumulation gate architecture for silicon metal-oxide-semiconductor quantum dots (QD). The layout consists of two independent accumulation gates, one gate forming a reservoir and the other the QD. The devices are fabricated with a foundry-compatible, etched, poly-silicon gate stack. We demonstrate 4 orders of magnitude of tunnel-rate control between the QD and the reservoir by modulating the reservoir gate voltage. Last electron charging energies of app. 10 meV and tuning of the ST splitting in the range 100-200 ueV are observed in two different split gate layouts and labs. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.
Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo
2017-12-23
This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e - rms , low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.
Energy Technology Data Exchange (ETDEWEB)
Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)
2015-07-28
Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.
Energy Technology Data Exchange (ETDEWEB)
Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel
2017-07-01
We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.
Priya, Anjali; Mishra, Ram Awadh
2016-04-01
In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.
Saramekala, Gopi Krishna; Tiwari, Pramod Kumar
2016-10-01
This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.
Takulapalli, Bharath R
2010-02-23
Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.
In vivo time-gated fluorescence imaging with biodegradable luminescent porous silicon nanoparticles.
Gu, Luo; Hall, David J; Qin, Zhengtao; Anglin, Emily; Joo, Jinmyoung; Mooney, David J; Howell, Stephen B; Sailor, Michael J
2013-01-01
Fluorescence imaging is one of the most versatile and widely used visualization methods in biomedical research. However, tissue autofluorescence is a major obstacle confounding interpretation of in vivo fluorescence images. The unusually long emission lifetime (5-13 μs) of photoluminescent porous silicon nanoparticles can allow the time-gated imaging of tissues in vivo, completely eliminating shorter-lived (50-fold in vitro and by >20-fold in vivo when imaging porous silicon nanoparticles. Time-gated imaging of porous silicon nanoparticles accumulated in a human ovarian cancer xenograft following intravenous injection is demonstrated in a live mouse. The potential for multiplexing of images in the time domain by using separate porous silicon nanoparticles engineered with different excited state lifetimes is discussed.
Saramekala, Gopi Krishna; Tiwari, Pramod Kumar
2017-08-01
Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.
Highly enhanced avalanche probability using sinusoidally-gated silicon avalanche photodiode
Energy Technology Data Exchange (ETDEWEB)
Suzuki, Shingo; Namekata, Naoto, E-mail: nnao@phys.cst.nihon-u.ac.jp; Inoue, Shuichiro [Institute of Quantum Science, Nihon University, 1-8-14 Kanda-Surugadai, Chiyoda-ku, Tokyo 101-8308 (Japan); Tsujino, Kenji [Tokyo Women' s Medical University, 8-1 Kawada-cho, Shinjuku-ku, Tokyo 162-8666 (Japan)
2014-01-27
We report on visible light single photon detection using a sinusoidally-gated silicon avalanche photodiode. Detection efficiency of 70.6% was achieved at a wavelength of 520 nm when an electrically cooled silicon avalanche photodiode with a quantum efficiency of 72.4% was used, which implies that a photo-excited single charge carrier in a silicon avalanche photodiode can trigger a detectable avalanche (charge) signal with a probability of 97.6%.
Electro-optical logic gates based on graphene-silicon waveguides
Chen, Weiwei; Yang, Longzhi; Wang, Pengjun; Zhang, Yawei; Zhou, Liqiang; Yang, Tianjun; Wang, Yang; Yang, Jianyi
2016-08-01
In this paper, designs of electro-optical AND/NAND, OR/ NOR, XOR/XNOR logic gates based on cascaded silicon graphene switches and regular 2×1 multimode interference combiners are presented. Each switch consists of a Mach-Zehnder interferometer in which silicon slot waveguides embedded with graphene flakes are designed for phase shifters. High-speed switching function is achieved by applying an electrical signal to tune the Fermi levels of graphene flakes causing the variation of modal effective index. Calculation results show the crosstalk in the proposed optical switch is lower than -22.9 dB within a bandwidth from 1510 nm to 1600 nm. The designed six electro-optical logic gates with the operation speed of 10 Gbit/s have a minimum extinction ratio of 35.6 dB and a maximum insertion loss of 0.21 dB for transverse electric modes at 1.55 μm.
Kapoor, V. J.; Shokrani, M.
1991-01-01
A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.
CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors
International Nuclear Information System (INIS)
Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon
2011-01-01
Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors
Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses
Energy Technology Data Exchange (ETDEWEB)
Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)
2016-06-20
Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.
Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode
Directory of Open Access Journals (Sweden)
Xiaojun Cheng
2014-05-01
Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.
Operation of heavily irradiated silicon detectors in non-depletion mode
International Nuclear Information System (INIS)
Verbitskaya, E.; Eremin, V.; Ilyashenko, I.; Li, Z.; Haerkoenen, J.; Tuovinen, E.; Luukka, P.
2006-01-01
The non-depletion detector operation mode has generally been disregarded as an option in high-energy physics experiments. In this paper, the non-depletion operation is examined by detailed analysis of the electric field distribution and the current pulse response of heavily irradiated silicon (Si) detectors. The previously reported model of double junction in heavily irradiated Si detector is further developed and a simulation of the current pulse response has been performed. It is shown that detectors can operate in a non-depletion mode due to the fact that the value of the electric field in a non-depleted region is high enough for efficient carrier drift. This electric field originates from the current flow through the detector and a consequent drop of the potential across high-resistivity bulk of a non-depleted region. It is anticipated that the electric field in a non-depleted region, which is still electrically neutral, increases with fluence that improves the non-depleted detector operation. Consideration of the electric field in a non-depleted region allows the explanation of the recorded double-peak current pulse shape of heavily irradiated Si detectors and definition of the requirements for the detector operational conditions. Detailed reconstruction of the electric field distribution gives new information on radiation effects in Si detectors
A fabrication guide for planar silicon quantum dot heterostructures
Spruijtenburg, Paul C.; Amitonov, Sergey V.; van der Wiel, Wilfred G.; Zwanenburg, Floris A.
2018-04-01
We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.
Sub-50 nm gate length SOI transistor development for high performance microprocessors
International Nuclear Information System (INIS)
Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.
2004-01-01
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI
Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C
Neudeck, Philip G.
1998-01-01
The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.
The depletion properties of silicon microstrip detectors with variable strip pitch
International Nuclear Information System (INIS)
Krizmanic, J.F.
1994-01-01
We have investigated the depletion properties of trapezoidal shaped silicon microstrip detectors which have variable strip pitch. Four types of detectors were examined: three detectors have constant strip width and a fourth has a varying strip width. The detectors are single sided with readout performed via p + strips. The depletion properties of the devices were measured using two different methods. The first used capacitance versus voltage measurements, while the second used a 1060 nm wavelength laser coupled to a single mode fiber with a mode field diameter less than 10 μm. The small laser spot size allowed for the depletion depth to be measured in a localized area of the detector. The laser induced charge on an electrode was measured as a function of reverse bias voltage using a sensitive charge preamplifier. The depletion voltages of the detectors demonstrate a strong dependence upon the ratio of strip width to strip pitch. Moreover, these measurements show that a large value of this ratio yields a lower depletion voltage and vice versa. (orig.)
Interstellar Silicon Depletion and the Ultraviolet Extinction
Mishra, Ajay; Li, Aigen
2018-01-01
Spinning small silicate grains were recently invoked to account for the Galactic foreground anomalous microwave emission. These grains, if present, will absorb starlight in the far ultraviolet (UV). There is also renewed interest in attributing the enigmatic 2175 Å interstellar extinction bump to small silicates. To probe the role of silicon in the UV extinction, we explore the relations between the amount of silicon required to be locked up in silicates [Si/H]dust and the 2175 Å bump or the far-UV extinction rise, based on an analysis of the extinction curves along 46 Galactic sightlines for which the gas-phase silicon abundance [Si/H]gas is known. We derive [Si/H]dust either from [Si/H]ISM - [Si/H]gas or from the Kramers- Kronig relation which relates the wavelength-integrated extinction to the total dust volume, where [Si/H]ISM is the interstellar silicon reference abundance and taken to be that of proto-Sun or B stars. We also derive [Si/H]dust from fi�tting the observed extinction curves with a mixture of amorphous silicates and graphitic grains. We fi�nd that in all three cases [Si/H]dust shows no correlation with the 2175 Å bump, while the carbon depletion [C/H]dust tends to correlate with the 2175 Å bump. This supports carbon grains instead of silicates as the possible carrier of the 2175 Å bump. We also �find that neither [Si/H]dust nor [C/H]dust alone correlates with the far-UV extinction, suggesting that the far-UV extinction is a combined effect of small carbon grains and silicates.
Radiation-hard silicon gate bulk CMOS cell family
International Nuclear Information System (INIS)
Gibbon, C.F.; Habing, D.H.; Flores, R.S.
1980-01-01
A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved
Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays
Energy Technology Data Exchange (ETDEWEB)
Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)
2013-12-23
Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.
DEFF Research Database (Denmark)
Pfreundt, Andrea
This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...
DEFF Research Database (Denmark)
Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria
2016-01-01
This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...
Top-gate microcrystalline silicon TFTs processed at low temperature (<200 deg. C)
International Nuclear Information System (INIS)
Saboundji, A.; Coulon, N.; Gorin, A.; Lhermite, H.; Mohammed-Brahim, T.; Fonrodona, M.; Bertomeu, J.; Andreu, J.
2005-01-01
N-type as well P-type top-gate microcrystalline silicon thin film transistors (TFTs) are fabricated on glass substrates at a maximum temperature of 200 deg. C. The active layer is an undoped μc-Si film, 200 nm thick, deposited by Hot-Wire Chemical Vapor. The drain and source regions are highly phosphorus (N-type TFTs) or boron (P-type TFTs)-doped μc-films deposited by HW-CVD. The gate insulator is a silicon dioxide film deposited by RF sputtering. Al-SiO 2 -N type c-Si structures using this insulator present low flat-band voltage,-0.2 V, and low density of states at the interface D it =6.4x10 10 eV -1 cm -2 . High field effect mobility, 25 cm 2 /V s for electrons and 1.1 cm 2 /V s for holes, is obtained. These values are very high, particularly the hole mobility that was never reached previously
Depletion voltage studies on n-in-n MCz silicon diodes after irradiation with 70 MeV protons
Holmkvist, William
2014-01-01
Silicon detectors is the main component in the pixel detectors in the ATLAS experiment at CERN in order to detect the particles and recreate their tracks after a proton-proton collision. One criteria on these detectors is to be able to operate in the high radiation field close to the particle collision. The usual behavior of the silicon detectors is that they get type inverted and an increase in the depletion voltage can be seen after exposed to significant amounts of radiation. In contrast n-type Magnetic Czochralski (MCz) silicon doesn’t follow FZ silicons pattern of getting type inverted when it comes to high energy particle irradiation, in the range of GeV. However it was observed that MCz silicon diodes that had been irradiated with 23 MeV protons followed the FZ silicon behavior and did type invert. The aim of the project is to find out how the depletion voltage of MCz silicon changes after being irradiated by 70 MeV at fluencies of 1E13, 1E14 and 5E14 neq/cm2, to give a further insight of at what en...
Design rules for RCA self-aligned silicon-gate CMOS/SOS process
1977-01-01
The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.
Uddin, Wasi; Georgiev, Yordan M.; Maity, Sarmistha; Das, Samaresh
2017-09-01
We report 1D electron transport of silicon junctionless tri-gate n-type transistor at 4.2 K. The step like curve observed in the current voltage characteristic suggests 1D transport. Besides the current steps for 1D transport, we found multiple spikes within individual steps, which we relate to inter-band single electron tunneling, mediated by the charged dopants available in the channel region. Clear Coulomb diamonds were observed in the stability diagram of the device. It is shown that a uniformly doped silicon nanowire can provide us the window for the single electron tunnelling. Back-gate versus front-gate color plot, where current is in a color scale, shows a crossover of the increased conduction region. This is a clear indication of the dopant-dopant interaction. It has been shown that back-gate biasing can be used to tune the coupling strength between the dopants.
Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices
Rojas, Jhonathan Prieto
2013-01-07
Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around
Guerfi, Youssouf; Larrieu, Guilhem
2016-04-01
Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.
Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya
2016-01-01
The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.
Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant
2016-03-01
In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.
Tin Dioxide Electrolyte-Gated Transistors Working in Depletion and Enhancement Modes.
Valitova, Irina; Natile, Marta Maria; Soavi, Francesca; Santato, Clara; Cicoira, Fabio
2017-10-25
Metal oxide semiconductors are interesting for next-generation flexible and transparent electronics because of their performance and reliability. Tin dioxide (SnO 2 ) is a very promising material that has already found applications in sensing, photovoltaics, optoelectronics, and batteries. In this work, we report on electrolyte-gated, solution-processed polycrystalline SnO 2 transistors on both rigid and flexible substrates. For the transistor channel, we used both unpatterned and patterned SnO 2 films. Since decreasing the SnO 2 area in contact with the electrolyte increases the charge-carrier density, patterned transistors operate in the depletion mode, whereas unpatterned ones operate in the enhancement mode. We also fabricated flexible SnO 2 transistors that operate in the enhancement mode that can withstand moderate mechanical bending.
Sevilla, Galo T.
2016-02-29
Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.
Top-gate organic depletion and inversion transistors with doped channel and injection contact
Energy Technology Data Exchange (ETDEWEB)
Liu, Xuhai; Kasemann, Daniel, E-mail: daniel.kasemann@iapp.de; Leo, Karl [Institut für Angewandte Photophysik, Technische Universität Dresden, George-Bähr-Strasse 1, 01069 Dresden (Germany)
2015-03-09
Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.
Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee
2014-10-01
The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.
International Nuclear Information System (INIS)
Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung
2014-01-01
The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)
A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator
International Nuclear Information System (INIS)
Park, Jea-Gun; Kim, Seong-Je; Shin, Mi-Hee; Song, Seung-Hyun; Shim, Tae-Hun; Chung, Sung-Woong; Enomoto, Hirofumi
2011-01-01
A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 μA memory margin. This is a step toward achieving a terabit volatile memory cell.
Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju
2017-12-01
This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.
Fully Depleted Charge-Coupled Devices
International Nuclear Information System (INIS)
Holland, Stephen E.
2006-01-01
We have developed fully depleted, back-illuminated CCDs that build upon earlier research and development efforts directed towards technology development of silicon-strip detectors used in high-energy-physics experiments. The CCDs are fabricated on the same type of high-resistivity, float-zone-refined silicon that is used for strip detectors. The use of high-resistivity substrates allows for thick depletion regions, on the order of 200-300 um, with corresponding high detection efficiency for near-infrared and soft x-ray photons. We compare the fully depleted CCD to the p-i-n diode upon which it is based, and describe the use of fully depleted CCDs in astronomical and x-ray imaging applications
Tiwari, Vishal A.; Divakaruni, Rama; Hook, Terence B.; Nair, Deleep R.
2016-04-01
Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.
Silicon on insulator self-aligned transistors
McCarthy, Anthony M.
2003-11-18
A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.
Saramekala, G. K.; Santra, Abirmoya; Dubey, Sarvesh; Jit, Satyabrata; Tiwari, Pramod Kumar
2013-08-01
In this paper, an analytical short-channel threshold voltage model is presented for a dual-metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first time, the advantages of recessed source/drain (Re-S/D) and of dual-metal-gate structure are incorporated simultaneously in a fully depleted SOI MOSFET. The analytical surface potential model at Si-channel/SiO2 interface and Si-channel/buried-oxide (BOX) interface have been developed by solving the 2-D Poisson’s equation in the channel region with appropriate boundary conditions assuming parabolic potential profile in the transverse direction of the channel. Thereupon, a threshold voltage model is derived from the minimum surface potential in the channel. The developed model is analyzed extensively for a variety of device parameters like the oxide and silicon channel thicknesses, thickness of source/drain extension in the BOX, control and screen gate length ratio. The validity of the present 2D analytical model is verified with ATLAS™, a 2D device simulator from SILVACO Inc.
All-optical switching via four-wave mixing Bragg scattering in a silicon platform
Directory of Open Access Journals (Sweden)
Yun Zhao
2017-02-01
Full Text Available We employ the process of non-degenerate four-wave mixing Bragg scattering to demonstrate all-optical control in a silicon platform. In our configuration, a strong, non-information-carrying pump is mixed with a weak control pump and an input signal in a silicon-on-insulator waveguide. Through the optical nonlinearity of this highly confining waveguide, the weak pump controls the wavelength conversion process from the signal to an idler, leading to a controlled depletion of the signal. The strong pump, on the other hand, plays the role of a constant bias. In this work, we show experimentally that it is possible to implement this low-power switching technique as a first step towards universal optical logic gates, and test the performance with random binary data. Even at very low powers, where the signal and control pump levels are almost equal, the eye-diagrams remain open, indicating a successful operation of the logic gates.
Temperature dependence of the radiation induced change of depletion voltage in silicon PIN detectors
International Nuclear Information System (INIS)
Ziock, H.J.; Holzscheiter, K.; Morgan, A.; Palounek, A.P.T.; Ellison, J.; Heinson, A.P.; Mason, M.; Wimpenny, S.J.; Barberis, E.; Cartiglia, N.; Grillo, A.; O'Shaughnessy, K.; Rahn, J.; Rinaldi, P.; Rowe, W.A.; Sadrozinski, H.F.W.; Seiden, A.; Spencer, E.; Webster, A.; Wichmann, R.; Wilder, M.; Coupal, D.; Pal, T.
1993-01-01
The silicon microstrip detectors that will be used in the SDC experiment at the Superconducting Super Collider (SSC) will be exposed to very large fluences of charged particles, neutrons, and gammas. The authors present a study of how temperature affects the change in the depletion voltage of silicon PIN detectors damaged by radiation. They study the initial radiation damage and the short-term and long-term annealing of that damage as a function of temperature in the range from -10 degrees C to +50 degrees C, and as a function of 800 MeV proton fluence up to 1.5 x 10 14 p/cm 2 . They express the pronounced temperature dependencies in a simple model in terms of two annealing time constants which depend exponentially on the temperature
All-optical 10 Gb/s AND logic gate in a silicon microring resonator
DEFF Research Database (Denmark)
Xiong, Meng; Lei, Lei; Ding, Yunhong
2013-01-01
An all-optical AND logic gate in a single silicon microring resonator is experimentally demonstrated at 10 Gb/s with 50% RZ-OOK signals. By setting the wavelengths of two intensity-modulated input pumps on the resonances of the microring resonator, field-enhanced four-wave mixing with a total inp...... power of only 8.5 dBm takes place in the ring, resulting in the generation of an idler whose intensity follows the logic operation between the pumps. Clear and open eye diagrams with a bit-error- ratio below 10−9 are achieved....
Ghoneim, Mohamed T.
2015-06-01
We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.
Coaxial-structured ZnO/silicon nanowires extended-gate field-effect transistor as pH sensor
International Nuclear Information System (INIS)
Li, Hung-Hsien; Yang, Chi-En; Kei, Chi-Chung; Su, Chung-Yi; Dai, Wei-Syuan; Tseng, Jung-Kuei; Yang, Po-Yu; Chou, Jung-Chuan; Cheng, Huang-Chung
2013-01-01
An extended-gate field-effect transistor (EGFET) of coaxial-structured ZnO/silicon nanowires as pH sensor was demonstrated in this paper. The oriented 1-μm-long silicon nanowires with the diameter of about 50 nm were vertically synthesized by the electroless metal deposition method at room temperature and were sequentially capped with the ZnO films using atomic layer deposition at 50 °C. The transfer characteristics (I DS –V REF ) of such ZnO/silicon nanowire EGFET sensor exhibited the sensitivity and linearity of 46.25 mV/pH and 0.9902, respectively for the different pH solutions (pH 1–pH 13). In contrast to the ZnO thin-film ones, the ZnO/silicon nanowire EGFET sensor achieved much better sensitivity and superior linearity. It was attributed to a high surface-to-volume ratio of the nanowire structures, reflecting a larger effective sensing area. The output voltage and time characteristics were also measured to indicate good reliability and durability for the ZnO/silicon nanowires sensor. Furthermore, the hysteresis was 9.74 mV after the solution was changed as pH 7 → pH 3 → pH 7 → pH 11 → pH 7. - Highlights: ► Coaxial-structured ZnO/silicon nanowire EGFET was demonstrated as pH sensor. ► EMD and ALD methods were proposed to fabricate ZnO/silicon nanowires. ► ZnO/silicon nanowire EGFET sensor achieved better sensitivity and linearity. ► ZnO/silicon nanowire EGFET sensor had good reliability and durability
The effect of gate length on SOI-MOSFETS operation | Baedi ...
African Journals Online (AJOL)
The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...
Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa
2015-01-01
We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard
Gated field-emitter cathodes for high-power microwave applications
International Nuclear Information System (INIS)
Barasch, E.F.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.; McIntyre, P.M.; Pang, Y.; Smith, D.D.; Trost, H.J.
1992-01-01
Gated field-emitter cathodes have been fabricated on silicon wafers. Two fabrication approaches have been employed: a knife-edge array and a porous silicon structure. The knife-edge array consists of a pattern of knife-edges, sharpened to ∼200 A radius, configured with an insulated metal gate structure at a gap of ∼500 A. The porous silicon cathode consists of an insulating porous layer, containing pores of ∼50 A diameter, densely spaced in the native silicon, biased for field emission by a thin gate metallization on the surface. Emission current density of 20 A/cm 2 has been obtained with only 10 V bias. Fabrication processes and test results are presented. (Author) 4 figs., tab., 12 refs
Chang, You-Tai; Peng, Kang-Ping; Li, Pei-Wen; Lin, Horng-Chih
2018-04-01
In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.
Design of a charge sensitive preamplifier on high resistivity silicon
International Nuclear Information System (INIS)
Radeka, V.; Rehak, P.; Rescia, S.; Gatti, E.; Longoni, A.; Sampietro, M.; Holl, P.; Strueder, L.; Kemmer, J.
1987-01-01
A low noise, fast charge sensitive preamplifier was designed on high resistivity, detector grade silicon. It is built at the surface of a fully depleted region of n-type silicon. This allows the preamplifier to be placed very close to a detector anode. The preamplifier uses the classical input cascode configuration with a capacitor and a high value resistor in the feedback loop. The output stage of the preamplifier can drive a load up to 20pF. The power dissipation of the preamplifier is 13mW. The amplifying elements are ''Single Sided Gate JFETs'' developed especially for this application. Preamplifiers connected to a low capacitance anode of a drift type detector should achieve a rise time of 20ns and have an equivalent noise charge (ENC), after a suitable shaping, of less than 50 electrons. This performance translates to a position resolution better than 3μm for silicon drift detectors. 6 refs., 9 figs
Boron diffusion into nitrogen doped silicon films for P{sup +} polysilicon gate structures
Energy Technology Data Exchange (ETDEWEB)
Mansour, Farida; Mahamdi, Ramdane; Jalabert, Laurent; Temple-Boyer, Pierre
2003-06-23
This paper deals with the study of the boron diffusion in nitrogen doped silicon (NIDOS) deposited from disilane Si{sub 2}H{sub 6} and ammonia NH{sub 3} for the development of P{sup +} polysilicon gate metal oxide semiconductor (MOS) devices. NIDOS films with varied nitrogen content have been boron implanted, then annealed and finally analysed by secondary ion mass spectroscopy (SIMS). In order to simulate the experimental SIMS of boron concentration profiles in the NIDOS films, a model adapted to the particular conditions of the samples elaboration, i.e. the very high boron concentration and the nitrogen content, has been established. The boron diffusion reduction in NIDOS films with increasing nitrogen rates has been evidenced by the profiles as well as by the obtained diffusion coefficients, which shows that the nitrogen incorporation reduces the boron diffusion. This has been confirmed by capacitance-voltage (C-V) measurements performed on MOS capacitors: the higher the nitrogen content, the lower the flat-band voltage. Finally, these results demonstrate that the improvement of the gate oxide quality occurs with the suppression of the boron penetration.
International Nuclear Information System (INIS)
Tiwari Pramod Kumar; Saramekala Gopi Krishna; Mukhopadhyay Anand Kumar; Dubey Sarvesh
2014-01-01
The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon—germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS™ by Silvaco Inc. (semiconductor devices)
Electron mobility in the inversion layers of fully depleted SOI films
Energy Technology Data Exchange (ETDEWEB)
Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)
2017-04-15
The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.
Chae, Hee Jae; Seok, Ki Hwan; Lee, Sol Kyu; Joo, Seung Ki
2018-04-01
A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.
An analytic model for gate-all-around silicon nanowire tunneling field effect transistors
International Nuclear Information System (INIS)
Liu Ying; He Jin; Chan Mansun; Ye Yun; Zhao Wei; Wu Wen; Deng Wan-Ling; Wang Wen-Ping; Du Cai-Xia
2014-01-01
An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane's expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)
Memristive device based on a depletion-type SONOS field effect transistor
Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.
2017-06-01
State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.
Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa
2011-01-01
We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.
Fahad, Hossain M.
2011-10-12
We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.
A high performance gate drive for large gate turn off thyristors
Energy Technology Data Exchange (ETDEWEB)
Szilagyi, C.P.
1993-01-01
Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.
Rojas, Jhonathan Prieto
2013-02-12
In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.
Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.
2013-01-01
In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.
Matsuura, Hideharu
2015-04-01
High-resolution silicon X-ray detectors with a large active area are required for effectively detecting traces of hazardous elements in food and soil through the measurement of the energies and counts of X-ray fluorescence photons radially emitted from these elements. The thicknesses and areas of commercial silicon drift detectors (SDDs) are up to 0.5 mm and 1.5 cm2, respectively. We describe 1.5-mm-thick gated SDDs (GSDDs) that can detect photons with energies up to 50 keV. We simulated the electric potential distributions in GSDDs with a Si thickness of 1.5 mm and areas from 0.18 to 168 cm2 at a single high reverse bias. The area of a GSDD could be enlarged simply by increasing all the gate widths by the same multiple, and the capacitance of the GSDD remained small and its X-ray count rate remained high.
A III-V nanowire channel on silicon for high-performance vertical transistors.
Tomioka, Katsuhiro; Yoshimura, Masatoshi; Fukui, Takashi
2012-08-09
Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.
International Nuclear Information System (INIS)
Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.
2005-01-01
AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators
Mesoscopic Field-Effect-Induced Devices in Depleted Two-Dimensional Electron Systems
Bachsoliani, N.; Platonov, S.; Wieck, A. D.; Ludwig, S.
2017-12-01
Nanoelectronic devices embedded in the two-dimensional electron system (2DES) of a GaAs /(Al ,Ga )As heterostructure enable a large variety of applications ranging from fundamental research to high-speed transistors. Electrical circuits are thereby commonly defined by creating barriers for carriers by the selective depletion of a preexisting 2DES. We explore an alternative approach: we deplete the 2DES globally by applying a negative voltage to a global top gate and screen the electric field of the top gate only locally using nanoscale gates placed on the wafer surface between the plane of the 2DES and the top gate. Free carriers are located beneath the screen gates, and their properties can be controlled by means of geometry and applied voltages. This method promises considerable advantages for the definition of complex circuits by the electric-field effect, as it allows us to reduce the number of gates and simplify gate geometries. Examples are carrier systems with ring topology or large arrays of quantum dots. We present a first exploration of this method pursuing field effect, Hall effect, and Aharonov-Bohm measurements to study electrostatic, dynamic, and coherent properties.
SWNT array resonant gate MOS transistor.
Arun, A; Campidelli, S; Filoramo, A; Derycke, V; Salet, P; Ionescu, A M; Goffman, M F
2011-02-04
We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.
SWNT array resonant gate MOS transistor
International Nuclear Information System (INIS)
Arun, A; Salet, P; Ionescu, A M; Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F
2011-01-01
We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.
An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant
2016-11-01
Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.
X-ray radiation damage studies and design of a silicon pixel sensor for science at the XFEL
Energy Technology Data Exchange (ETDEWEB)
Zhang, Jiaguo
2013-06-15
Experiments at the European X-ray Free Electron Laser (XFEL) require silicon pixel sensors which can withstand X-ray doses up to 1 GGy. For the investigation of Xray radiation damage up to these high doses, MOS capacitors and gate-controlled diodes built on high resistivity n-doped silicon with crystal orientations left angle 100 right angle and left angle 111 right angle produced by four vendors, CiS, Hamamatsu, Canberra and Sintef have been irradiated with 12 keV X-rays at the DESY DORIS III synchrotron-light source. Using capacitance/ conductance-voltage, current-voltage and thermal dielectric relaxation current measurements, the densities of oxide charges and interface traps at the Si-SiO{sub 2} interface, and the surface-current densities have been determined as function of dose. Results indicate that the dose dependence of the oxide-charge density, the interface-trap density and the surface-current density depend on the crystal orientation and producer. In addition, the influence of the voltage applied to the gates of the MOS capacitor and the gate-controlled diode during X-ray irradiation on the oxide-charge density, the interface-trap density and the surface-current density has been investigated at doses of 100 kGy and 100 MGy. It is found that both strongly depend on the gate voltage if the electric field in the oxide points from the surface of the SiO{sub 2} to the Si-SiO{sub 2} interface. To verify the long-term stability of irradiated silicon sensors, annealing studies have been performed at 60 C and 80 C on MOS capacitors and gate-controlled diodes irradiated to 5 MGy as well, and the annealing kinetics of oxide charges and surface current were determined. Moreover, the macroscopic electrical properties of segmented sensors have slao been investigated as function of dose. It is found that the defects introduced by X-rays increase the full depletion voltage, the surface leakage current and the inter-electrode capacitance of the segmented sensor. An
X-ray radiation damage studies and design of a silicon pixel sensor for science at the XFEL
International Nuclear Information System (INIS)
Zhang, Jiaguo
2013-06-01
Experiments at the European X-ray Free Electron Laser (XFEL) require silicon pixel sensors which can withstand X-ray doses up to 1 GGy. For the investigation of Xray radiation damage up to these high doses, MOS capacitors and gate-controlled diodes built on high resistivity n-doped silicon with crystal orientations left angle 100 right angle and left angle 111 right angle produced by four vendors, CiS, Hamamatsu, Canberra and Sintef have been irradiated with 12 keV X-rays at the DESY DORIS III synchrotron-light source. Using capacitance/ conductance-voltage, current-voltage and thermal dielectric relaxation current measurements, the densities of oxide charges and interface traps at the Si-SiO 2 interface, and the surface-current densities have been determined as function of dose. Results indicate that the dose dependence of the oxide-charge density, the interface-trap density and the surface-current density depend on the crystal orientation and producer. In addition, the influence of the voltage applied to the gates of the MOS capacitor and the gate-controlled diode during X-ray irradiation on the oxide-charge density, the interface-trap density and the surface-current density has been investigated at doses of 100 kGy and 100 MGy. It is found that both strongly depend on the gate voltage if the electric field in the oxide points from the surface of the SiO 2 to the Si-SiO 2 interface. To verify the long-term stability of irradiated silicon sensors, annealing studies have been performed at 60 C and 80 C on MOS capacitors and gate-controlled diodes irradiated to 5 MGy as well, and the annealing kinetics of oxide charges and surface current were determined. Moreover, the macroscopic electrical properties of segmented sensors have slao been investigated as function of dose. It is found that the defects introduced by X-rays increase the full depletion voltage, the surface leakage current and the inter-electrode capacitance of the segmented sensor. An electron
Local gate control in carbon nanotube quantum devices
Biercuk, Michael Jordan
This thesis presents transport measurements of carbon nanotube electronic devices operated in the quantum regime. Nanotubes are contacted by source and drain electrodes, and multiple lithographically-patterned electrostatic gates are aligned to each device. Transport measurements of device conductance or current as a function of local gate voltages reveal that local gates couple primarily to the proximal section of the nanotube, hence providing spatially localized control over carrier density along the nanotube length. Further, using several different techniques we are able to produce local depletion regions along the length of a tube. This phenomenon is explored in detail for different contact metals to the nanotube. We utilize local gating techniques to study multiple quantum dots in carbon nanotubes produced both by naturally occurring defects, and by the controlled application of voltages to depletion gates. We study double quantum dots in detail, where transport measurements reveal honeycomb charge stability diagrams. We extract values of energy-level spacings, capacitances, and interaction energies for this system, and demonstrate independent control over all relevant tunneling rates. We report rf-reflectometry measurements of gate-defined carbon nanotube quantum dots with integrated charge sensors. Aluminum rf-SETs are electrostatically coupled to carbon nanotube devices and detect single electron charging phenomena in the Coulomb blockade regime. Simultaneous correlated measurements of single electron charging are made using reflected rf power from the nanotube itself and from the rf-SET on microsecond time scales. We map charge stability diagrams for the nanotube quantum dot via charge sensing, observing Coulomb charging diamonds beyond the first order. Conductance measurements of carbon nanotubes containing gated local depletion regions exhibit plateaus as a function of gate voltage, spaced by approximately 1e2/h, the quantum of conductance for a single
Silicon based ultrafast optical waveform sampling
DEFF Research Database (Denmark)
Ji, Hua; Galili, Michael; Pu, Minhao
2010-01-01
A 300 nmx450 nmx5 mm silicon nanowire is designed and fabricated for a four wave mixing based non-linear optical gate. Based on this silicon nanowire, an ultra-fast optical sampling system is successfully demonstrated using a free-running fiber laser with a carbon nanotube-based mode-locker as th......A 300 nmx450 nmx5 mm silicon nanowire is designed and fabricated for a four wave mixing based non-linear optical gate. Based on this silicon nanowire, an ultra-fast optical sampling system is successfully demonstrated using a free-running fiber laser with a carbon nanotube-based mode......-locker as the sampling source. A clear eye-diagram of a 320 Gbit/s data signal is obtained. The temporal resolution of the sampling system is estimated to 360 fs....
High-performance silicon nanotube tunneling FET for ultralow-power logic applications
Fahad, Hossain M.; Hussain, Muhammad Mustafa
2013-01-01
To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.
SWNT array resonant gate MOS transistor
Energy Technology Data Exchange (ETDEWEB)
Arun, A; Salet, P; Ionescu, A M [NanoLab, Ecole Polytechnique Federale de Lausanne, CH-1015, Lausanne (Switzerland); Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F, E-mail: marcelo.goffman@cea.fr [Laboratoire d' Electronique Moleculaire, SPEC (CNRS URA 2454), IRAMIS, CEA, Gif-sur-Yvette (France)
2011-02-04
We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.
Laser-assisted electron emission from gated field-emitters
Ishizuka, H; Yokoo, K; Mimura, H; Shimawaki, H; Hosono, A
2002-01-01
Enhancement of electron emission by illumination of gated field-emitters was studied using a 100 mW cw YAG laser at a wavelength of 532 nm, intensities up to 10 sup 7 W/m sup 2 and mechanically chopped with a rise time of 4 mu s. When shining an array of 640 silicon emitters, the emission current responded quickly to on-off of the laser. The increase of the emission current was proportional to the basic emission current at low gate voltages, but it was saturated at approx 3 mu A as the basic current approached 100 mu A with the increase of gate voltage. The emission increase was proportional to the square root of laser power at low gate voltages and to the laser power at elevated gate voltages. For 1- and 3-tip silicon emitters, the rise and fall of the current due to on-off of the laser showed a significant time lag. The magnitude of emission increase was independent of the position of laser spot on the emitter base and reached 2 mu A at a basic current of 5 mu A without showing signs of saturation. The mech...
The distribution of silicon on BP Boo
International Nuclear Information System (INIS)
Hatzes, A.P.
1990-01-01
A version of the Doppler imaging technique which incorporates the principles of maximum entropy reconstruction is used to derive the silicon distribution on the Ap star BP Boo (HR 5857). The method used made it possible to detect an error in the published photometric period and a new value of 1.29557 d was determined. The silicon distribution consists of two depleted spots of unequal area separated by about 180deg in longitude. These spots may coincide with the location of the magnetic poles of the star as in the case of γ 2 Ari. Near the larger of the depleted silicon spots is a spot of enhanced abundance. The unequal area of the depleted spots as well as the close proximity of the enhanced spot to one of the depleted regions suggests the presence of non-axisymmetric magnetic field lines. (author)
High-performance silicon nanotube tunneling FET for ultralow-power logic applications
Fahad, Hossain M.
2013-03-01
To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET\\'s effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.
Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond
Doris, B.; DeSalvo, B.; Cheng, K.; Morin, P.; Vinet, M.
2016-03-01
This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint development program between IBM, ST Microelectronics and CEA-LETI. In particular, we review the technological developments ranging from substrate engineering to process modules that enable functionality and improve FDSOI performance over several generations. Various multi Vt integration schemes to maximize the benefits of the thin BOX FDSOI platform are discussed. Manufacturability as well as scalability concerns are highlighted and addressed. In addition, this work provides understanding of the performance/power trade-offs for FDSOI circuits and device variability. Finally, clear directions for future application-specific products are given, demonstrating that FDSOI is an attractive CMOS option for next generation high performance and low-power applications.
A self-aligned gate definition process with submicron gaps
Warmerdam, L.F.P.; Aarnink, Antonius A.I.; Holleman, J.; Wallinga, Hans
1989-01-01
A self-aligned gate definition process is proposed. Spacings between adjacent gates of 0.5 µm and smaller are fabricated. The spacing is realized by an edge-etch technique, combined with anisotropic plasma etching of the single poly-silicon layer. Straight gaps with minor width variation are
Cleaning Challenges of High-κ/Metal Gate Structures
Hussain, Muhammad Mustafa; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.
2010-01-01
High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.
Cleaning Challenges of High-κ/Metal Gate Structures
Hussain, Muhammad Mustafa
2010-12-20
High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.
Formation of strain-induced quantum dots in gated semiconductor nanostructures
Directory of Open Access Journals (Sweden)
Ted Thorbeck
2015-08-01
Full Text Available A long-standing mystery in the field of semiconductor quantum dots (QDs is: Why are there so many unintentional dots (also known as disorder dots which are neither expected nor controllable. It is typically assumed that these unintentional dots are due to charged defects, however the frequency and predictability of the location of the unintentional QDs suggests there might be additional mechanisms causing the unintentional QDs besides charged defects. We show that the typical strains in a semiconductor nanostructure from metal gates are large enough to create strain-induced quantum dots. We simulate a commonly used QD device architecture, metal gates on bulk silicon, and show the formation of strain-induced QDs. The strain-induced QD can be eliminated by replacing the metal gates with poly-silicon gates. Thus strain can be as important as electrostatics to QD device operation operation.
International Nuclear Information System (INIS)
Landen, O.L.; Bell, P.M.; Satariano, J.J.; Oertel, J.A.; Bradley, D.K.
1994-01-01
The pulsed characteristics of gated, stripline configuration microchannel-plate (MCP) detectors used in X-ray framing cameras deployed on laser plasma experiments worldwide are examined in greater detail. The detectors are calibrated using short (20 ps) and long (500 ps) pulse X-ray irradiation and 3--60 ps, deep UV (202 and 213 nm), spatially-smoothed laser irradiation. Two-dimensional unsaturated gain profiles show 5 in irradiation and fitted using a discrete dynode model. Finally, a pump-probe experiment quantifying for the first time long-suspected gain depletion by strong localized irradiation was performed. The mechanism for the extra voltage and hence gain degradation is shown to be associated with intense MCP irradiation in the presence of the voltage pulse, at a fluence at least an order of magnitude above that necessary for saturation. Results obtained for both constant pump area and constant pump fluence are presented. The data are well modeled by calculating the instantaneous electrical energy loss due to the intense charge extraction at the pump site and then recalculating the gain downstream at the probe site given the pump-dependent degradation in voltage amplitude
Development and characterization of vertical double-gate MOS field-effect transistors
International Nuclear Information System (INIS)
Trellenkamp, S.
2004-07-01
Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)
Poly-silicon quantum-dot single-electron transistors
International Nuclear Information System (INIS)
Kang, Kwon-Chil; Lee, Joung-Eob; Lee, Jung-Han; Lee, Jong-Ho; Shin, Hyung-Cheol; Park, Byung-Gook
2012-01-01
For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also, to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.
Saha, Priyanka; Banerjee, Pritha; Dash, Dinesh Kumar; Sarkar, Subir Kumar
2018-03-01
This paper presents an analytical model of an asymmetric junctionless double-gate (asymmetric DGJL) silicon-on-nothing metal-oxide-semiconductor field-effect transistor (MOSFET). Solving the 2-D Poisson's equation, the expressions for center potential and threshold voltage are calculated. In addition, the response of the device toward the various short-channel effects like hot carrier effect, drain-induced barrier lowering and threshold voltage roll-off has also been examined along with subthreshold swing and drain current characteristics. Performance analysis of the present model is also demonstrated by comparing its short-channel behavior with conventional DGJL MOSFET. The effect of variation of the device features due to the variation of device parameters is also studied. The simulated results obtained using 2D device simulator, namely ATLAS, are in good agreement with the analytical results, hence validating our derived model.
Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi
2018-05-01
The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.
Thin-barrier enhancement-mode AlGaN/GaN MIS-HEMT using ALD Al2O3 as gate insulator
International Nuclear Information System (INIS)
Wang Zheli; Zhou Jianjun; Kong Yuechan; Kong Cen; Dong Xun; Yang Yang; Chen Tangsheng
2015-01-01
A high-performance enhancement-mode (E-mode) gallium nitride (GaN)-based metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT) that employs a 5-nm-thick aluminum gallium nitride (Al 0.3 Ga 0.7 N) as a barrier layer and relies on silicon nitride (SiN) passivation to control the 2DEG density is presented. Unlike the SiN passivation, aluminum oxide (Al 2 O 3 ) by atomic layer deposition (ALD) on AlGaN surface would not increase the 2DEG density in the heterointerface. ALD Al 2 O 3 was used as gate insulator after the depletion by etching of the SiN in the gate region. The E-mode MIS-HEMT with gate length (L G ) of 1 μm showed a maximum drain current density (I DS ) of 657 mA/mm, a maximum extrinsic transconductance (g m ) of 187 mS/mm and a threshold voltage (V th ) of 1 V. Comparing with the corresponding E-mode HEMT, the device performances had been greatly improved due to the insertion of Al 2 O 3 gate insulator. This provided an excellent way to realize E-mode AlGaN/GaN MIS-HEMTs with both high V th and I DS . (paper)
International Nuclear Information System (INIS)
Servanton, G; Clement, L; Lepinay, K; Lorut, F; Pantel, R; Pofelski, A; Bicais, N
2013-01-01
The growing demand for wireless multimedia applications (smartphones, tablets, digital cameras) requires the development of devices combining both high speed performances and low power consumption. A recent technological breakthrough making a good compromise between these two antagonist conditions has been proposed: the 28-14nm CMOS transistor generations based on a fully-depleted Silicon-on-Insulator (FD-SOI) performed on a thin Si film of 5-6nm. In this paper, we propose to review the TEM characterization challenges that are essential for the development of extremely power-efficient System on Chip (SoC)
Ultra-fine metal gate operated graphene optical intensity modulator
Kou, Rai; Hori, Yosuke; Tsuchizawa, Tai; Warabi, Kaori; Kobayashi, Yuzuki; Harada, Yuichi; Hibino, Hiroki; Yamamoto, Tsuyoshi; Nakajima, Hirochika; Yamada, Koji
2016-12-01
A graphene based top-gate optical modulator on a standard silicon photonic platform is proposed for the future optical telecommunication networks. On the basis of the device simulation, we proposed that an electro-absorption light modulation can be realized by an ultra-narrow metal top-gate electrode (width less than 400 nm) directly located on the top of a silicon wire waveguide. The designed structure also provides excellent features such as carrier doping and waveguide-planarization free fabrication processes. In terms of the fabrication, we established transferring of a CVD-grown mono-layer graphene sheet onto a CMOS compatible silicon photonic sample followed by a 25-nm thick ALD-grown Al2O3 deposition and Source-Gate-Drain electrodes formation. In addition, a pair of low-loss spot-size converter for the input and output area is integrated for the efficient light source coupling. The maximum modulation depth of over 30% (1.2 dB) is observed at a device length of 50 μm, and a metal width of 300 nm. The influence of the initial Fermi energy obtained by experiment on the modulation performance is discussed with simulation results.
Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook
2018-09-01
In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.
Distribution of electric field and charge collection in silicon strip detectors
International Nuclear Information System (INIS)
Anokhin, I.E.; Zinets, O.S.
1995-01-01
The distribution of electric field in silicon strip detectors is analyzed in the case of dull depletion as well as for partial depletion. Influence of inhomogeneous electric fields on the charge collection and performances of silicon strip detectors is discussed
A new memory effect (MSD) in fully depleted SOI MOSFETs
Bawedin, M.; Cristoloveanu, S.; Yun, J. G.; Flandre, D.
2005-09-01
We demonstrate that the transconductance and drain current of fully depleted MOSFETs can display an interesting time-dependent hysteresis. This new memory effect, called meta-stable dip (MSD), is mainly due to the long carrier generation lifetime in the silicon film. Our parametric analysis shows that the memory window can be adjusted in view of practical applications. Various measurement conditions and devices with different doping, front oxide and silicon film thicknesses are systematically explored. The MSD effect can be generalized to several fully depleted CMOS technologies. The MSD mechanism is discussed and validated by two-dimensional simulations results.
Tin - an unlikely ally for silicon field effect transistors?
Hussain, Aftab M.
2014-01-13
We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high-κ/metal gate based multi-gate-field-effect-transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.
2016-11-01
Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.
Persistent depletion of plasma gelsolin (pGSN) after exposure of mice to heavy silicon ions
Rithidech, Kanokporn Noy; Reungpatthanaphong, Paiboon; Tungjai, Montree; Jangiam, Witawat; Honikel, Louise; Whorton, Elbert B.
2018-05-01
Little is known about plasma proteins that can be used as biomarkers for early and late responses to radiation. The purpose of this study was to determine a link between depletion of plasma gelsolin (pGSN) and cell-death as well as inflammatory responses in the lung (one of the tissues known to be radiosensitive) of the same exposed CBA/CaJ mice after exposure to heavy silicon (28Si) ions. To prevent the development of multiple organ dysfunctions, pGSN (an important component of the extracellular actin-scavenging system) is responsible for the removal of actin that is released into the circulation during inflammation and from dying cells. We evaluated the levels of pGSN in plasma collected from groups of mice (5 mice in each) at 1 week (wk) and 1 month (1 mo) after exposure whole body to different doses of 28Si ions, i.e. 0, 0.1, 0.25, or 0.5 Gy (2 fractionated exposures, 15 days apart that totaled each selected dose). In the same mouse, the measurements of pGSN levels were coupled with the quantitation of injuries in the lung, determined by (a) the levels of cleaved poly (ADP-ribose) polymerase (cleaved-PARP), a marker of apoptotic cell-death, (b) the levels of activated nuclear factor-kappa B (NF-κB) and selected cytokines, i.e. tumor necrosis factor-alpha (TNF-α), interleukin-1 beta (IL-1β), and IL-6, from tissue-lysates of the lung. Further, the ratio of neutrophils and lymphocytes (N/L) was determined in the same mouse. Our data indicated: (i) the magnitude of pGSN depletion was dependent to radiation dose at both harvest times, (ii) a persistent depletion of pGSN up to 1 mo post-exposure to 0.25 or 0.5 Gy of 28Si ions, (iii) an inverse-correlation between pGSN depletion and increased levels of cleaved-PARP, including activated NF-κB/pro-inflammatory cytokines in the lung, and (iv) at both harvest times, statistically significant increases in the N/L ratio in groups of mice exposed to 0.5 Gy only. Our findings suggested that depletion in pGSN levels
International Nuclear Information System (INIS)
Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y
2008-01-01
The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter
High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor.
Al-Hardan, Naif H; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N
2016-06-07
In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.
Simulation of atomistic processes during silicon oxidation
Bongiorno, Angelo
2003-01-01
Silicon dioxide (SiO2) films grown on silicon monocrystal (Si) substrates form the gate oxides in current Si-based microelectronics devices. The understanding at the atomic scale of both the silicon oxidation process and the properties of the Si(100)-SiO2 interface is of significant importance in state-of-the-art silicon microelectronics manufacturing. These two topics are intimately coupled and are both addressed in this theoretical investigation mainly through first-principles calculations....
Energy Technology Data Exchange (ETDEWEB)
Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu; Gouker, Pascale M.
2013-09-01
Fully depleted silicon-on-insulator transistors coated with gadolinium oxide are shown to be effective thermal neutron dosimeters. The theoretical neutron detection efficiency is calculated to be higher for Gd{sub 2}O{sub 3} than for other practical converter materials. Proof-of-concept dosimeter devices were fabricated and tested during thermal neutron irradiation. The transistor current changes linearly with neutron dose, consistent with increasing positive charge in the SOI buried oxide layer generated by ionization from high energy {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. The measured neutron sensitivity is approximately 1/6 the maximum theoretical value, possibly due to electron–hole recombination or conversion electron loss in interconnect wiring above the transistors. -- Highlights: • A novel Gd{sub 2}O{sub 3} coated FDSOI MOSFET thermal neutron dosimeter is presented. • Dosimeter can detect charges generated from {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. • Measured neutron sensitivity is comparable to that calculated theoretically. • Dosimeter requires zero power during operation, enabling new application areas.
International Nuclear Information System (INIS)
Rancoita, P.G.; Seidman, A.
1985-01-01
Large-size silicon detectors employing relatively low resistivity material can be used in electromagnetic calorimetry. They can operate in strong magnetic fields, under geometric constraints and with microstrip detectors a high resolution can be achieved. Low noise large capacitance oriented electronics was developed to enable good signal-to-noise ratio for single relativistic particles traversing large area detectors. In undepleted silicon detectors, the charge migration from the field-free region has been investigated by comparing the expected peak position (from the depleted layer only) of the energy-loss of relativistic electrons with the measured one. Furthermore, the undepleted detectors have been employed in a prototype of Si/W electromagnetic colorimeter. The sensitive layer was found to be systematically larger than the depleted one
Silicon quantum processor with robust long-distance qubit couplings
Energy Technology Data Exchange (ETDEWEB)
Tosi, Guilherme; Mohiyaddin, Fahd A.; Schmitt, Vivien; Tenberg, Stefanie; Rahman, Rajib; Klimeck, Gerhard; Morello, Andrea
2017-09-06
Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowing selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.
Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET
Ramezani, Zeinab; Orouji, Ali A.
2016-10-01
For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.
Gate protective device for SOS array
Meyer, J. E., Jr.; Scott, J. H.
1972-01-01
Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.
High Sensitivity pH Sensor Based on Porous Silicon (PSi Extended Gate Field-Effect Transistor
Directory of Open Access Journals (Sweden)
Naif H. Al-Hardan
2016-06-01
Full Text Available In this study, porous silicon (PSi was prepared and tested as an extended gate field-effect transistor (EGFET for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.
Transformational silicon electronics
Rojas, Jhonathan Prieto
2014-02-25
In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.
Active silicon x-ray for measuring electron temperature
International Nuclear Information System (INIS)
Snider, R.T.
1994-07-01
Silicon diodes are commonly used for x-ray measurements in the soft x-ray region between a few hundred ev and 20 keV. Recent work by Cho has shown that the charge collecting region in an underbiased silicon detector is the depletion depth plus some contribution from a region near the depleted region due to charge-diffusion. The depletion depth can be fully characterized as a function of the applied bias voltage and is roughly proportional to the squart root of the bias voltage. We propose a technique to exploit this effect to use the silicon within the detector as an actively controlled x-ray filter. With reasonable silicon manufacturing methods, a silicon diode detector can be constructed in which the sensitivity of the collected charge to the impinging photon energy spectrum can be changed dynamically in the visible to above the 20 keV range. This type of detector could be used to measure the electron temperature in, for example, a tokamak plasma by sweeping the applied bias voltage during a plasma discharge. The detector samples different parts of the energy spectrum during the bias sweep, and the data collected contains enough information to determine the electron temperature. Benefits and limitations of this technique will be discussed along with comparisons to similar methods for measuring electron temperature and other applications of an active silicon x-ray filter
International Nuclear Information System (INIS)
Huang Pengcheng; Chen Shuming; Chen Jianjun
2016-01-01
In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout. (paper)
Simulation of dual-gate SOI MOSFET with different dielectric layers
Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.
2016-04-01
The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).
Ballistic transport of graphene pnp junctions with embedded local gates
International Nuclear Information System (INIS)
Nam, Seung-Geol; Ki, Dong-Keun; Kim, Youngwook; Kim, Jun Sung; Lee, Hu-Jong; Park, Jong Wan
2011-01-01
We fabricated graphene pnp devices, by embedding pre-defined local gates in an oxidized surface layer of a silicon substrate. With neither deposition of dielectric material on the graphene nor electron-beam irradiation, we obtained high-quality graphene pnp devices without degradation of the carrier mobility even in the local-gate region. The corresponding increased mean free path leads to the observation of ballistic and phase-coherent transport across a local gate 130 nm wide, which is about an order of magnitude wider than reported previously. Furthermore, in our scheme, we demonstrated independent control of the carrier density in the local-gate region, with a conductance map very much distinct from those of top-gated devices. This was caused by the electric field arising from the global back gate being strongly screened by the embedded local gate. Our scheme allows the realization of ideal multipolar graphene junctions with ballistic carrier transport.
Thin film silicon on silicon nitride for radiation hardened dielectrically isolated MISFET's
International Nuclear Information System (INIS)
Neamen, D.; Shedd, W.; Buchanan, B.
1975-01-01
The permanent ionizing radiation effects resulting from charge trapping in a silicon nitride isolation dielectric have been determined for a total ionizing dose up to 10 7 rads (Si). Junction FET's, whose active channel region is directly adjacent to the silicon-silicon nitride interface, were used to measure the effects of the radiation induced charge trapping in the Si 3 N 4 isolation dielectric. The JFET saturation current and channel conductance versus junction gate voltage and substrate voltage were characterized as a function of the total ionizing radiation dose. The experimental results on the Si 3 N 4 are compared to results on similar devices with SiO 2 dielectric isolation. The ramifications of using the silicon nitride for fabricating radiation hardened dielectrically isolated MIS devices are discussed
Carbon nanotube transistors with graphene oxide films as gate dielectrics
Institute of Scientific and Technical Information of China (English)
无
2010-01-01
Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.
Threshold stoichiometry for beam induced nitrogen depletion of SiN
International Nuclear Information System (INIS)
Timmers, H.; Weijers, T.D.M.; Elliman, R.G.; Uribasterra, J.; Whitlow, H.J.; Sarwe, E.-L.
2002-01-01
Measurements of the stoichiometry of silicon nitride films as a function of the number of incident ions using heavy ion elastic recoil detection (ERD) show that beam-induced nitrogen depletion depends on the projectile species, the beam energy, and the initial stoichiometry. A threshold stoichiometry exists in the range 1.3>N/Si≥1, below which the films are stable against nitrogen depletion. Above this threshold, depletion is essentially linear with incident fluence. The depletion rate correlates non-linearly with the electronic energy loss of the projectile ion in the film. Sufficiently long exposure of nitrogen-rich films renders the mechanism, which prevents depletion of nitrogen-poor films, ineffective. Compromising depth-resolution, nitrogen depletion from SiN films during ERD analysis can be reduced significantly by using projectile beams with low atomic numbers
International Nuclear Information System (INIS)
Xu Songlin; Sun Zhiwen; Chen Arthur; Qian Xueyu; Podlesnik, Dragan
2001-01-01
Addition of CF 4 into HBr-based plasma for polycrystalline-silicon gate etching reduces the deposition of an etch byproduct, silicon oxide, onto the chamber wall but tends to generate organic polymer. In this work, a detailed study has been carried out to analyze the mechanism of polymerization and to characterize the polymer composition and quantity. The study has shown that the polymer formation is due to the F-radical depletion by H atoms dissociated from HBr. The composition of the polymer changes significantly with CF 4 concentration in the gas feed, and the polymer deposition rate depends on CF 4 % and other process conditions such as source power, bias power, and pressure. Surface temperature also affects the polymer deposition rate. Adding O 2 into the plasma can clean the organic polymer, but the O 2 amount has to be well controlled in order to prevent the formation of silicon oxide. Based on a series of tests to evaluate polymer deposition and oxide cleaning with O 2 addition, an optimized process regime in terms of O 2 -to-CF 4 ratio has been identified to simultaneously suppress the polymer and oxide deposition so that the etch process becomes self-cleaning
International Nuclear Information System (INIS)
Sehgal, Amit; Mangla, Tina; Gupta, Mridula; Gupta, R.S.
2008-01-01
In this work, a two-dimensional potential distribution formulation is presented for multi-material gate poly-crystalline silicon thin film transistors. The developed formulation incorporates the effects due to traps and grain-boundaries. In short-channel devices, short-channel effects and drain-induced barrier lowering (DIBL) effect exists, and are accounted for in the analysis. The work aims at the reduction of DIBL effect and grain-boundary effects i.e. to reduce the potential barriers generated in the channel by employing gate-engineered structures. A study of work-functions and electrode lengths of multi-material gate electrode is done to suppress the potential barriers, hot electron effect and to improve the carrier transport efficiency. Green's function approach is adopted for the two-dimensional potential solution. The results obtained show a good agreement with simulated results, thus, demonstrating the validity of our model
Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors
Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor
2013-06-01
The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.
Tin (Sn) for enhancing performance in silicon CMOS
Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa
2013-01-01
We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
Tin (Sn) for enhancing performance in silicon CMOS
Hussain, Aftab M.
2013-10-01
We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
Single-electron transistors fabricated with sidewall spacer patterning
Park, Byung-Gook; Kim, Dae Hwan; Kim, Kyung Rok; Song, Ki-Whan; Lee, Jong Duk
2003-09-01
We have implemented a sidewall spacer patterning method for novel dual-gate single-electron transistor (DGSET) and metal-oxide-semiconductor-based SET (MOSET) based on the uniform SOI wire, using conventional lithography and processing technology. A 30 nm wide silicon quantum wire is defined by a sidewall spacer patterning method, and depletion gates for two tunnel junctions of the DGSET are formed by the doped polycrystalline silicon sidewall. The fabricated DGSET and MOSET show clear single-electron tunneling phenomena at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. On the basis of the phase control capability of the sidewall depletion gates, we have proposed a complementary self-biasing method, which enables the SET/CMOS hybrid multi-valued logic (MVL) to operate perfectly well at high temperature, where the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical DGSET model, and it is confirmed that even DGSETs with a large Si island can be utilized efficiently in the multi-valued logic.
Heterojunction fully depleted SOI-TFET with oxide/source overlap
Chander, Sweta; Bhowmick, B.; Baishya, S.
2015-10-01
In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.
Magnetic resonance force microscopy quantum computer with tellurium donors in silicon.
Berman, G P; Doolen, G D; Hammel, P C; Tsifrinovich, V I
2001-03-26
We propose a magnetic resonance force microscopy (MRFM)-based nuclear spin quantum computer using tellurium impurities in silicon. This approach to quantum computing combines well-developed silicon technology and expected advances in MRFM. Our proposal does not use electrostatic gates to realize quantum logic operations.
Magnetic Resonance Force Microscopy Quantum Computer with Tellurium Donors in Silicon
International Nuclear Information System (INIS)
Berman, G. P.; Doolen, G. D.; Hammel, P. C.; Tsifrinovich, V. I.
2001-01-01
We propose a magnetic resonance force microscopy (MRFM)-based nuclear spin quantum computer using tellurium impurities in silicon. This approach to quantum computing combines well-developed silicon technology and expected advances in MRFM. Our proposal does not use electrostatic gates to realize quantum logic operations
Montes Muñoz, Enrique
2017-01-24
We investigate the electronic transport properties of silicon nanotubes attached to metallic electrodes from first principles, using density functional theory and the non-equilibrium Green\\'s function method. The influence of the surface termination is studied as well as the dependence of the transport characteristics on the chirality, diameter, and length. Strong electronic coupling between nanotubes and electrodes is found to be a general feature that results in low contact resistance. The conductance in the tunneling regime is discussed in terms of the complex band structure. Silicon nanotube field effect transistors are simulated by applying a uniform potential gate. Our results demonstrate very high values of transconductance, outperforming the best commercial silicon field effect transistors, combined with low values of sub-threshold swing.
Influence of the device geometry on the Schottky gate characteristics of AlGaN/GaN HEMTs
International Nuclear Information System (INIS)
Lu, C Y; Chang, E Y; Bahat-Treidel, E; Hilt, O; Lossy, R; Chaturvedi, N; Würfl, J; Tränkle, G
2010-01-01
In this work, we investigate the relevance of device geometry to the Schottky gate characteristics of AlGaN/GaN high electron mobility transistors. Changes of three-terminal gate turn-on voltage and gate leakage current on the gate—drain spacing, source—gate spacing and recess depth have been observed. Further examinations comparing device simulations and measurements suggest that gate turn-on voltage is influenced by the distribution of electric potential under the gate region which is related to the geometry. By proper design of the device, high gate turn-on voltage can be obtained for both depletion-mode and recessed enhancement-mode devices
Energy Technology Data Exchange (ETDEWEB)
Suat, J. P.; Peccoud, L.; Le Goascoz, V.; Garcia, M.; Mackowiak, E.
1975-01-31
The advantages resulting from a SOS (Silicon-on-Sapphire) MOS technology are demonstrated. Experimental results giving the performance of C.MOS and depletion-enrichment P-channel technologies are presented, with an application of Silicon on insulator on development, that is to say a 1024 bits MNOS memory, peripheral circuits being developed according to the depletion-enrichment technology.
Tunnel field-effect transistor with two gated intrinsic regions
Directory of Open Access Journals (Sweden)
Y. Zhang
2014-07-01
Full Text Available In this paper, we propose and validate (using simulations a novel design of silicon tunnel field-effect transistor (TFET, based on a reverse-biased p+-p-n-n+ structure. 2D device simulation results show that our devices have significant improvements of switching performance compared with more conventional devices based on p-i-n structure. With independent gate voltages applied to two gated intrinsic regions, band-to-band tunneling (BTBT could take place at the p-n junction, and no abrupt degenerate doping profile is required. We developed single-side-gate (SSG structure and double-side-gate (DSG structure. SSG devices with HfO2 gate dielectric have a point subthreshold swing of 9.58 mV/decade, while DSG devices with polysilicon gate electrode material and HfO2 gate dielectric have a point subthreshold swing of 16.39 mV/decade. These DSG devices have ON-current of 0.255 μA/μm, while that is lower for SSG devices. Having two nano-scale independent gates will be quite challenging to realize with good uniformity across the wafer and the improved behavior of our TFET makes it a promising steep-slope switch candidate for further investigations.
International Nuclear Information System (INIS)
Duan Bao-Xing; Yang Yin-Tang
2012-01-01
In this paper, two-dimensional electron gas (2DEG) regions in AlGaN/GaN high electron mobility transistors (HEMTs) are realized by doping partial silicon into the AlGaN layer for the first time. A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge. The high electric field near the gate for the complete silicon doping structure is effectively decreased, which makes the surface electric field uniform. The high electric field peak near the drain results from the potential difference between the surface and the depletion regions. Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer. The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain. The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field. (condensed matter: electronic structure, electrical, magnetic, and optical properties)
Experimental and theoretical study of the signal electron motion in fully depleted silicon
International Nuclear Information System (INIS)
Kimmel, N.; Andritschke, R.; Hartmann, R.; Holl, P.; Meidinger, N.; Richter, R.; Strueder, L.
2010-01-01
Imaging spectrometers based on a fully depleted silicon substrate are sensitive over the whole device volume. Therefore, a high detection efficiency for X-rays of up to 20 keV is achieved. Our experimental method facilitates measurements of the detected signal pulse height in a pixel as a function of the photon conversion position in the pixel array. Further analysis of the measurements delivers the size of a signal electron cloud after its drift from the photon conversion position to the storage cells. These results can be used to reconstruct the conversion position of each detected X-ray photon. A reconstruction accuracy of 1μm can be achieved with a pixel size of 51μm. Complementary to the measurements, we have created a physical model of the signal electron collection process. The change of the drift mobility with the electric drift field strength in the detection volume is considered in order to correctly describe the drift speed of the charge cloud. The electric field values and the values of the charge density in the detector volume are delivered by numerical device simulations with the software package 'TeSCA'. Comparisons of the simulations with the measurements confirmed the correctness of the applied physical model. We have thus established a method which enables device designers to simulate the process of signal charge collection in future detector concepts.
Directory of Open Access Journals (Sweden)
Yu-Hsien Lin
2015-01-01
Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.
International Nuclear Information System (INIS)
Lin, Y. H.; Chou, J. C.
2015-01-01
We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT_s) using different high-Κ gate dielectric materials such as silicon nitride (Si_3N_4) and aluminum oxide (Al_2O_3) at low temperature process (<300 degree) and compared them with low temperature silicon dioxide (SiO_2). The IGZO device with high-Κ gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, post annealing treatment is an essential process for completing the process. The chemical reaction of the high-κ/IGZO interface due to heat formation in high-Κ/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-Κ gate dielectric materials and explained the interface effect by charge band diagram.
Ultra-low specific on-resistance SOI double-gate trench-type MOSFET
International Nuclear Information System (INIS)
Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji
2011-01-01
An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)
Bubble gate for in-plane flow control.
Oskooei, Ali; Abolhasani, Milad; Günther, Axel
2013-07-07
We introduce a miniature gate valve as a readily implementable strategy for actively controlling the flow of liquids on-chip, within a footprint of less than one square millimetre. Bubble gates provide for simple, consistent and scalable control of liquid flow in microchannel networks, are compatible with different bulk microfabrication processes and substrate materials, and require neither electrodes nor moving parts. A bubble gate consists of two microchannel sections: a liquid-filled channel and a gas channel that intercepts the liquid channel to form a T-junction. The open or closed state of a bubble gate is determined by selecting between two distinct gas pressure levels: the lower level corresponds to the "open" state while the higher level corresponds to the "closed" state. During closure, a gas bubble penetrates from the gas channel into the liquid, flanked by a column of equidistantly spaced micropillars on each side, until the flow of liquid is completely obstructed. We fabricated bubble gates using single-layer soft lithographic and bulk silicon micromachining procedures and evaluated their performance with a combination of theory and experimentation. We assessed the dynamic behaviour during more than 300 open-and-close cycles and report the operating pressure envelope for different bubble gate configurations and for the working fluids: de-ionized water, ethanol and a biological buffer. We obtained excellent agreement between the experimentally determined bubble gate operational envelope and a theoretical prediction based on static wetting behaviour. We report case studies that serve to illustrate the utility of bubble gates for liquid sampling in single and multi-layer microfluidic devices. Scalability of our strategy was demonstrated by simultaneously addressing 128 bubble gates.
Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering
Ferain, I.; Duffy, R.; Collaert, N.; van Dal, M. J. H.; Pawlak, B. J.; O'Sullivan, B.; Witters, L.; Rooyackers, R.; Conard, T.; Popovici, M.; van Elshocht, S.; Kaiser, M.; Weemaes, R. G. R.; Swerts, J.; Jurczak, M.; Lander, R. J. P.; De Meyer, K.
2009-07-01
At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263-5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110-1 [1,2
Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar
2018-02-01
This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.
International Nuclear Information System (INIS)
Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar
2014-01-01
We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)
Floating Gate CMOS Dosimeter With Frequency Output
Garcia-Moreno, E.; Isern, E.; Roca, M.; Picos, R.; Font, J.; Cesari, J.; Pineda, A.
2012-04-01
This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.
International Nuclear Information System (INIS)
Jiang Xiang-Wei; Li Shu-Shen
2012-01-01
By using the linear combination of bulk band (LCBB) method incorporated with the top of the barrier splitting (TBS) model, we present a comprehensive study on the quantum confinement effects and the source-to-drain tunneling in the ultra-scaled double-gate (DG) metal—oxide—semiconductor field-effect transistors (MOSFETs). A critical body thickness value of 5 nm is found, below which severe valley splittings among different X valleys for the occupied charge density and the current contributions occur in ultra-thin silicon body structures. It is also found that the tunneling current could be nearly 100% with an ultra-scaled channel length. Different from the previous simulation results, it is found that the source-to-drain tunneling could be effectively suppressed in the ultra-thin body thickness (2.0 nm and below) by the quantum confinement and the tunneling could be suppressed down to below 5% when the channel length approaches 16 nm regardless of the body thickness. (condensed matter: electronic structure, electrical, magnetic, and optical properties)
2016-08-19
limiters, MEMS, NEMS, field emission, cold cathodes (Some figures may appear in colour only in the online journal) 1. Introduction Dense arrays of silicon... attention has been given to densely packed, highly ordered, top-down fabricated, single crystal vertical silicon nanowire devices that are embedded
Directory of Open Access Journals (Sweden)
V. А. Pilipenko
2017-01-01
Full Text Available Introduction of submicron design standards into microelectronic industry and a decrease of the gate dielectric thickness raise the importance of the analysis of microinhomogeneities in the silicon-silicon dioxide system. However, there is very little to no information on practical implementation of probe electrometry methods, and particularly scanning Kelvin probe method, in the interoperational control of real semiconductor manufacturing process. The purpose of the study was the development of methods for nondestructive testing of semiconductor wafers based on the determination of electrophysical properties of the silicon-silicon dioxide interface and their spatial distribution over wafer’s surface using non-contact probe electrometry methods.Traditional C-V curve analysis and scanning Kelvin probe method were used to characterize silicon- silicon dioxide interface. The samples under testing were silicon wafers of KEF 4.5 and KDB 12 type (orientation <100>, diameter 100 mm.Probe electrometry results revealed uniform spatial distribution of wafer’s surface potential after its preliminary rapid thermal treatment. Silicon-silicon dioxide electric potential values were also higher after treatment than before it. This potential growth correlates with the drop in interface charge density. At the same time local changes in surface potential indicate changes in surface layer structure.Probe electrometry results qualitatively reflect changes of interface charge density in silicon-silicon dioxide structure during its technological treatment. Inhomogeneities of surface potential distribution reflect inhomogeneity of damaged layer thickness and can be used as a means for localization of interface treatment defects.
Effective carrier sweepout in a silicon waveguide by a metal-semiconductor-metal structure
DEFF Research Database (Denmark)
Ding, Yunhong; Hu, Hao; Ou, Haiyan
2015-01-01
We demonstrate effective carrier depletion by metal-semiconductor-metal junctions for a silicon waveguide. Photo-generated carriers are efficiently swept out by applying bias voltages, and a shortest carrier lifetime of only 55 ps is demonstrated.......We demonstrate effective carrier depletion by metal-semiconductor-metal junctions for a silicon waveguide. Photo-generated carriers are efficiently swept out by applying bias voltages, and a shortest carrier lifetime of only 55 ps is demonstrated....
Low-resistivity photon-transparent window attached to photo-sensitive silicon detector
International Nuclear Information System (INIS)
Holland, S.E.
2000-01-01
The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels
Large volume cryogenic silicon detectors
International Nuclear Information System (INIS)
Braggio, C.; Boscardin, M.; Bressi, G.; Carugno, G.; Corti, D.; Galeazzi, G.; Zorzi, N.
2009-01-01
We present preliminary measurements for the development of a large volume silicon detector to detect low energy and low rate energy depositions. The tested detector is a one cm-thick silicon PIN diode with an active volume of 31 cm 3 , cooled to the liquid helium temperature to obtain depletion from thermally-generated free carriers. A thorough study has been done to show that effects of charge trapping during drift disappears at a bias field value of the order of 100V/cm.
Physics of fully depleted CCDs
International Nuclear Information System (INIS)
Holland, S E; Bebek, C J; Kolbe, W F; Lee, J S
2014-01-01
In this work we present simple, physics-based models for two effects that have been noted in the fully depleted CCDs that are presently used in the Dark Energy Survey Camera. The first effect is the observation that the point-spread function increases slightly with the signal level. This is explained by considering the effect on charge-carrier diffusion due to the reduction in the magnitude of the channel potential as collected signal charge acts to partially neutralize the fixed charge in the depleted channel. The resulting reduced voltage drop across the carrier drift region decreases the vertical electric field and increases the carrier transit time. The second effect is the observation of low-level, concentric ring patterns seen in uniformly illuminated images. This effect is shown to be most likely due to lateral deflection of charge during the transit of the photo-generated carriers to the potential wells as a result of lateral electric fields. The lateral fields are a result of space charge in the fully depleted substrates arising from resistivity variations inherent to the growth of the high-resistivity silicon used to fabricate the CCDs
Transistors using crystalline silicon devices on glass
McCarthy, Anthony M.
1995-01-01
A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.
Silicon integrated circuits part A : supplement 2
Kahng, Dawon
1981-01-01
Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public
Fully depleted back-illuminated p-channel CCD development
Energy Technology Data Exchange (ETDEWEB)
Bebek, Chris J.; Bercovitz, John H.; Groom, Donald E.; Holland, Stephen E.; Kadel, Richard W.; Karcher, Armin; Kolbe, William F.; Oluseyi, Hakeem M.; Palaio, Nicholas P.; Prasad, Val; Turko, Bojan T.; Wang, Guobin
2003-07-08
An overview of CCD development efforts at Lawrence Berkeley National Laboratory is presented. Operation of fully-depleted, back-illuminated CCD's fabricated on high resistivity silicon is described, along with results on the use of such CCD's at ground-based observatories. Radiation damage and point-spread function measurements are described, as well as discussion of CCD fabrication technologies.
Development of an oxidized porous silicon vacuum microtriode
Energy Technology Data Exchange (ETDEWEB)
Smith, II, Don Deewayne [Texas A & M Univ., College Station, TX (United States)
1994-05-01
In order to realize a high-power microwave amplifier design known as a gigatron, a gated field emission array must be developed that can deliver a high-intensity electron beam at gigahertz frequencies. No existing field emission device meets the requirements for a gigatron cathode. In the present work, a porous silicon-based approach is evaluated. The use of porous silicon reduces the size of a single emitter to the nanometer scale, and a true two-dimensional array geometry can be approached. A wide number of applications for such a device exist in various disciplines. Oxidized porous silicon vacuum diodes were first developed in 1990. No systematic study had been done to characterize the performance of these devices as a function of the process parameters. The author has done the first such study, fabricating diodes from p<100>, p<111>, and n<100> silicon substrates. Anodization current densities from 11 mA/cm2 to 151 mA/cm2 were used, and Fowler-Nordheim behavior was observed in over 80% of the samples. In order to effectively adapt this technology to mainstream vacuum microelectronic applications, a means of creating a gated triodic structure must be found. No previous attempts had successfully yielded such a device. The author has succeeded in utilizing a novel metallization method to fabricate the first operational oxidized porous silicon vacuum microtriodes, and results are encouraging.
Molecular logic gates: the past, present and future.
Erbas-Cakmak, Sundus; Kolemen, Safacan; Sedgwick, Adam C; Gunnlaugsson, Thorfinnur; James, Tony D; Yoon, Juyoung; Akkaya, Engin U
2018-04-03
The field of molecular logic gates originated 25 years ago, when A. P. de Silva published a seminal article in Nature. Stimulated by this ground breaking research, scientists were inspired to join the race to simulate the workings of the fundamental components of integrated circuits using molecules. The rules of this game of mimicry were flexible, and have evolved and morphed over the years. This tutorial review takes a look back on and provides an overview of the birth and growth of the field of molecular logics. Spinning-off from chemosensor research, molecular logic gates quickly proved themselves to be more than intellectual exercises and are now poised for many potential practical applications. The ultimate goal of this vein of research became clearer only recently - to "boldly go where no silicon-based logic gate has gone before" and seek out a new deeper understanding of life inside tissues and cells.
Large volume cryogenic silicon detectors
Energy Technology Data Exchange (ETDEWEB)
Braggio, C. [Dipartimento di Fisica, Universita di Padova, via Marzolo 8, 35131 Padova (Italy); Boscardin, M. [Fondazione Bruno Kessler (FBK), via Sommarive 18, I-38100 Povo (Italy); Bressi, G. [INFN sez. di Pavia, via Bassi 6, 27100 Pavia (Italy); Carugno, G.; Corti, D. [INFN sez. di Padova, via Marzolo 8, 35131 Padova (Italy); Galeazzi, G. [INFN lab. naz. Legnaro, viale dell' Universita 2, 35020 Legnaro (Italy); Zorzi, N. [Fondazione Bruno Kessler (FBK), via Sommarive 18, I-38100 Povo (Italy)
2009-12-15
We present preliminary measurements for the development of a large volume silicon detector to detect low energy and low rate energy depositions. The tested detector is a one cm-thick silicon PIN diode with an active volume of 31 cm{sup 3}, cooled to the liquid helium temperature to obtain depletion from thermally-generated free carriers. A thorough study has been done to show that effects of charge trapping during drift disappears at a bias field value of the order of 100V/cm.
Density dependence of electron mobility in the accumulation mode for fully depleted SOI films
Energy Technology Data Exchange (ETDEWEB)
Naumova, O. V., E-mail: naumova@isp.nsc.ru; Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)
2015-10-15
The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.
Channel mobility degradation and charge trapping in high-k/metal gate NMOSFETs
International Nuclear Information System (INIS)
Mathew, Shajan; Bera, L.K.; Balasubramanian, N.; Joo, M.S.; Cho, B.J.
2004-01-01
NMOSFETs with Metalo-Organic Chemical Vapor Deposited (MOCVD) HfAlO gate dielectric and TiN metal gate have been fabricated. Channel electron mobility was measured using the split-CV method and compared with SiO 2 devices. All high-k devices showed lower mobility compared with SiO 2 reference devices. High-k MOSFETs exhibited significant charge trapping and threshold instability. Threshold voltage recovery with time was studied on devices with oxide/nitride interfacial layer between high-k film and silicon substrate
Fabrication of a novel silicon single electron transistor for Si:P quantum computer devices
International Nuclear Information System (INIS)
Angus, S.J.; Smith, C.E.A.; Gauja, E.; Dzurak, A.S.; Clark, R.G.; Snider, G.L.
2004-01-01
Full text: Quantum computation relies on the successful measurement of quantum states. Single electron transistors (SETs) are known to be able to perform fast and sensitive charge measurements of solid state qubits. However, due to their sensitivity, SETs are also very susceptible to random charge fluctuations in a solid-state materials environment. In previous dc transport measurements, silicon-based SETs have demonstrated greater charge stability than A1/A1 2 O 3 SETs. We have designed and fabricated a novel silicon SET architecture for a comparison of the noise characteristics of silicon and aluminium based devices. The silicon SET described here is designed for controllable and reproducible low temperature operation. It is fabricated using a novel dual gate structure on a silicon-on-insulator substrate. A silicon quantum wire is formed in a 100nm thick high-resistivity superficial silicon layer using reactive ion etching. Carriers are induced in the silicon wire by a back gate in the silicon substrate. The tunnel barriers are created electrostatically, using lithographically defined metallic electrodes (∼40nm width). These tunnel barriers surround the surface of the quantum wire, thus producing excellent electrostatic confinement. This architecture provides independent control of tunnel barrier height and island occupancy, thus promising better control of Coulomb blockade oscillations than in previously investigated silicon SETs. The use of a near intrinsic silicon substrate offers compatibility with Si:P qubits in the longer term
OTFT with pentacene-gate dielectric interface modified by silicon nanoparticles
International Nuclear Information System (INIS)
Jakabovic, J.; Kovac, J.; Srnanek, R.; Guldan, S.; Donoval, D.; Weis, M.; Sokolsky, M.; Cirak, J.; Broch, K.; Schreiber, F.
2011-01-01
We have for the first time investigated the structural and electrical properties of pentacene OTFT deposited on the semiconductor-gate insulator interface covered with SiNPs monolayer prepared by the LB method and compared these to a reference sample (without SiNPs). The micro-Raman, AFM and XRD measurements confirmed that the pentacene layer deposited on the semiconductor-gate insulator interface covered with a SiNPs monolayer on both hydrophobic and hydrophilic surfaces changes the structure. The Raman measurements show that the average value of α is between 0.8 and 1.0. The different structural quality of pentacene leads to better OTFTs electrical characteristics mainly saturation current of OTFTs with SiNPs increasing (∼ 2.5 x) with storing time (85 days) in comparison to OTFTs without SiNPs, which decrease similarly after 85 days.
International Nuclear Information System (INIS)
Bhartia, Mini; Chatterjee, Arun Kumar
2015-01-01
A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2. (paper)
Bhartia, Mini; Chatterjee, Arun Kumar
2015-04-01
A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.
Behavior of ion-implanted cesium in silicon dioxide films
International Nuclear Information System (INIS)
Fishbein, B.J.
1988-01-01
Charged impurities in silicon dioxide can be used to controllably shift the flatband voltage of metal-oxide-semiconductor devices independently of the substrate doping, the gate oxide thickness and the gate-electrode work function. Cesium is particularly well suited for this purpose because it is immobile in SiO 2 at normal device operating temperatures, and because it can be controllably introduced into oxide films by ion implantation. Cesium is positively charged in silicon dioxide, resulting in a negative flatband voltage shift. Possible applications for cesium technology include solar cells, devices operated at liquid nitrogen temperature, and power devices. The goal of this work has been to characterize as many aspects of cesium behavior in silicon dioxide as are required for practical applications. Accordingly, cesium-ion implantation, cesium diffusion, and cesium electrical activation in SiO 2 were studied over a broad range of processing conditions. The electrical properties of cesium-containing oxides, including current-voltage characteristics, interface trap density, and inversion-layer carrier mobility were examined, and several potential applications for cesium technology have been experimentally demonstrated
Fabrication and evaluation of series-triple quantum dots by thermal oxidation of silicon nanowire
International Nuclear Information System (INIS)
Uchida, Takafumi; Jo, Mingyu; Tsurumaki-Fukuchi, Atsushi; Arita, Masashi; Takahashi, Yasuo; Fujiwara, Akira
2015-01-01
Series-connected triple quantum dots were fabricated by a simple two-step oxidation technique using the pattern-dependent oxidation of a silicon nanowire and an additional oxidation of the nanowire through the gap of the fine gates attached to the nanowire. The characteristics of multi-dot single-electron devices are obtained. The formation of each quantum dot beneath an attached gate is confirmed by analyzing the electrical characteristics and by evaluating the gate capacitances between all pairings of gates and quantum dots. Because the gate electrode is automatically attached to each dot, the device structure benefits from scalability. This technique promises integrability of multiple quantum dots with individual control gates
Directory of Open Access Journals (Sweden)
K.E. Kaharudin
2015-12-01
Full Text Available This paper presents a study of optimizing input process parameters on leakage current (IOFF in silicon-on-insulator (SOI Vertical Double-Gate,Metal Oxide Field-Effect-Transistor (MOSFET by using L36 Taguchi method. The performance of SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF value. An orthogonal array, main effects, signal-to-noise ratio (SNR and analysis of variance (ANOVA are utilized in order to analyze the effect of input process parameter variation on leakage current (IOFF. Based on the results, the minimum leakage current ((IOFF of SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION value at 434 µA/µm. Both the drive current (ION and leakage current (IOFF values yield a higher ION/IOFF ratio (48.22 x 106 for low power consumption application. Meanwhile, polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors with each of the contributing factor effects percentage of 59% and 25%.
Characterization of oxygen dimer-enriched silicon detectors
Boisvert, V; Moll, M; Murin, L I; Pintilie, I
2005-01-01
Various types of silicon material and silicon p+n diodes have been treated to increase the concentration of the oxygen dimer (O2i) defect. This was done by exposing the bulk material and the diodes to 6 MeV electrons at a temperature of about 350 °C. FTIR spectroscopy has been performed on the processed material confirming the formation of oxygen dimer defects in Czochralski silicon pieces. We also show results from TSC characterization on processed diodes. Finally, we investigated the influence of the dimer enrichment process on the depletion voltage of silicon diodes and performed 24 GeV/c proton irradiations to study the evolution of the macroscopic diode characteristics as a function of fluence.
Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs
Directory of Open Access Journals (Sweden)
Michael Loong Peng Tan
2013-01-01
Full Text Available Long channel carbon nanotube transistor (CNT can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL effects in silicon MOSFET while sustaining the same unit area at higher current density.
Dual-gate operation and carrier transport in SiGe p-n junction nanowires
Delker, C. J.; Yoo, J. Y.; Bussmann, E.; Swartzentruber, B. S.; Harris, C. T.
2017-11-01
We investigate carrier transport in silicon-germanium nanowires with an axial p-n junction doping profile by fabricating these wires into transistors that feature separate top gates over each doping segment. By independently biasing each gate, carrier concentrations in the n- and p-side of the wire can be modulated. For these devices, which were fabricated with nickel source-drain electrical contacts, holes are the dominant charge carrier, with more favorable hole injection occurring on the p-side contact. Channel current exhibits greater sensitivity to the n-side gate, and in the reverse biased source-drain configuration, current is limited by the nickel/n-side Schottky contact.
Back-illuminated, fully-depleted CCD image sensors for use in optical and near-IR astronomy
Groom, D E; Levi, M E; Palaio, N P; Perlmutter, S; Stover, R J; Wei, M
2000-01-01
Charge-coupled devices (CCDs) of novel design have been fabricated at Lawrence Berkeley National Laboratory (LBNL), and the first large-format science-grade chips for astronomical imaging are now being characterized at Lick Observatory. They are made on 300-mu m thick n-type high-resistivity (approx 10 000 OMEGA cm) silicon wafers, using a technology developed at LBNL to fabricate low-leakage silicon microstrip detectors for high-energy physics. A bias voltage applied via a transparent contact on the back side fully depletes the substrate, making the entire volume photosensitive and ensuring that charge reaches the potential wells with minimal lateral diffusion. The development of a thin, transparent back-side contact compatible with fully depleted operation permits blue response comparable to that obtained with thinned CCDs. Since the entire region is active, high quantum efficiency is maintained to nearly lambda=1000 nm, above which the silicon band gap effectively truncates photoproduction. Early character...
MOS structures containing silicon nanoparticles for memory device applications
International Nuclear Information System (INIS)
Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S
2008-01-01
Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability
Gurov, Yu B; Sandukovsky, V G; Yurkovski, J
2005-01-01
The results of research and development of special silicon detectors with a large active area ($> 8 cm^{2}$) for multilayer telescope spectrometers (fulfilled in the Laboratory of Nuclear Problems, JINR) are reviewed. The detector parameters are listed. The production of totally depleted surface barrier detectors (identifiers) operating under bias voltage two to three times higher than depletion voltage is described. The possibility of fabrication of lithium drifted counters with a very thin entrance window on the diffusion side of the detector (about 10--20 $\\mu$m) is shown. The detector fabrication technique has allowed minimizing detector dead regions without degradation of their spectroscopic characteristics and reliability during long time operation in charge particle beams.
Cavity-assisted quantum computing in a silicon nanostructure
International Nuclear Information System (INIS)
Tang Bao; Qin Hao; Zhang Rong; Xue Peng; Liu Jin-Ming
2014-01-01
We present a scheme of quantum computing with charge qubits corresponding to one excess electron shared between dangling-bond pairs of surface silicon atoms that couple to a microwave stripline resonator on a chip. By choosing a certain evolution time, we propose the realization of a set of universal single- and two-qubit logical gates. Due to its intrinsic stability and scalability, the silicon dangling-bond charge qubit can be regarded as one of the most promising candidates for quantum computation. Compared to the previous schemes on quantum computing with silicon bulk systems, our scheme shows such advantages as a long coherent time and direct control and readout. (general)
Solar cell array for driving MOS type FET gate. MOS gata EFT gate kudoyo taiyo denchi array
Energy Technology Data Exchange (ETDEWEB)
Murakami, S; Yoshida, K; Yoshiki, T; Yamaguchi, Y; Nakayama, T; Owada, Y
1990-03-12
There has been a semiconductor relay utilizing MOS type FET (field effect transistor). Concerning the solar cells used for a semiconductor relay, it is required to separate the cells by forming insulating oxide films first and to form semiconductor layers by using many mask patterns, since a crystal semiconductor is used. Thereby its manufacturing process becomes complicated and laminification as well as thin film formation are difficult, In view of the above, this invention proposes a solar cell array for driving a MOS type FET gate consisting of amorphous silicon semiconductor cells, which are used for a semiconductor relay with solar cells generating electromotive power by the light of a light emitting diode and a MOS type FET that the power output of the above solar cells is supplied to its gate, and which are connected in series with many steps. 9 figs.
Orbach, Ron; Remacle, Françoise; Levine, R D; Willner, Itamar
2012-12-26
The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg(2+)-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli's and Fredkin's logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine.
International Nuclear Information System (INIS)
Alloatti, L.; Lauermann, M.; Koos, C.; Freude, W.; Sürgers, C.; Leuthold, J.
2013-01-01
We determine the optical losses in gate-induced charge accumulation/inversion layers at a Si/SiO 2 interface. Comparison between gate-induced charge layers and ion-implanted thin silicon films having an identical sheet resistance shows that optical losses can be significantly lower for gate-induced layers. For a given sheet resistance, holes produce higher optical loss than electrons. Measurements have been performed at λ = 1550 nm
International Nuclear Information System (INIS)
Hyun, Youngmin; Kim, Heesan
2013-01-01
Ti-stabilized 11 wt% Cr ferritic stainless steels (FSSs) for automotive exhaust systems have been experienced intergranular corrosion (IC) in some heat-affected zone (HAZ). The effects of sensitizing heat-treatment and silicon on IC were studied. Time-Temperature-Sensitization (TTS) curves showed that sensitization to IC was observed at the steels heat-treated at the temperature lower than 650 .deg. C and that silicon improved IC resistance. The sensitization was explained by chromium depletion theory, where chromium is depleted by precipitation of chromium carbide during sensitizing heat-treatment. It was confirmed with the results from the analysis of precipitates as well as the thermodynamical prediction of stable phases. In addition, the role of silicon on IC was explained with the stabilization of grain boundary. In other words, silicon promoted the formation of the grain boundaries with low energy where precipitation was suppressed and consequently, the formation of Cr-depleted zone was retarded. The effect of silicon on the formation of grain boundaries with low energy was proved by the analysis of coincidence site lattice (CSL) grain boundary, which is a typical grain boundary with low energy
Energy Technology Data Exchange (ETDEWEB)
Hyun, Youngmin; Kim, Heesan [Hongik Univ., Sejong (Korea, Republic of)
2013-06-15
Ti-stabilized 11 wt% Cr ferritic stainless steels (FSSs) for automotive exhaust systems have been experienced intergranular corrosion (IC) in some heat-affected zone (HAZ). The effects of sensitizing heat-treatment and silicon on IC were studied. Time-Temperature-Sensitization (TTS) curves showed that sensitization to IC was observed at the steels heat-treated at the temperature lower than 650 .deg. C and that silicon improved IC resistance. The sensitization was explained by chromium depletion theory, where chromium is depleted by precipitation of chromium carbide during sensitizing heat-treatment. It was confirmed with the results from the analysis of precipitates as well as the thermodynamical prediction of stable phases. In addition, the role of silicon on IC was explained with the stabilization of grain boundary. In other words, silicon promoted the formation of the grain boundaries with low energy where precipitation was suppressed and consequently, the formation of Cr-depleted zone was retarded. The effect of silicon on the formation of grain boundaries with low energy was proved by the analysis of coincidence site lattice (CSL) grain boundary, which is a typical grain boundary with low energy.
Surface effects in segmented silicon sensors
Energy Technology Data Exchange (ETDEWEB)
Kopsalis, Ioannis
2017-05-15
Silicon detectors in Photon Science and Particle Physics require silicon sensors with very demanding specifications. New accelerators like the European X-ray Free Electron Laser (EuXFEL) and the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), pose new challenges for silicon sensors, especially with respect to radiation hardness. High radiation doses and fluences damage the silicon crystal and the SiO{sub 2} layers at the surface, thus changing the sensor properties and limiting their life time. Non-Ionizing Energy Loss (NIEL) of incident particles causes silicon crystal damage. Ionizing Energy Loss (IEL) of incident particles increases the densities of oxide charge and interface traps in the SiO{sub 2} and at the Si-SiO{sub 2} interface. In this thesis the surface radiation damage of the Si-SiO{sub 2} system on high-ohmic Si has been investigated using circular MOSFETs biased in accumulation and inversion at an electric field in the SiO{sub 2} of about 500 kV/cm. The MOSFETs have been irradiated by X-rays from an X-ray tube to a dose of about 17 kGy(SiO{sub 2}) in different irradiation steps. Before and after each irradiation step, the gate voltage has been cycled from inversion to accumulation conditions and back. From the dependence of the drain-source current on gate voltage the threshold voltage of the MOSFET and the hole and electron mobility at the Si-SiO{sub 2} interface were determined. In addition, from the measured drain-source current the change of the oxide charge density during irradiation has been determined. The interface trap density and the oxide charge has been determined separately using the subthreshold current technique based on the Brews charge sheet model which has been applied for first time on MOSFETs built on high-ohmic Si. The results show a significant field-direction dependence of the surface radiation parameters. The extracted parameters and the acquired knowledge can be used to improve simulations of the surface
Surface effects in segmented silicon sensors
International Nuclear Information System (INIS)
Kopsalis, Ioannis
2017-05-01
Silicon detectors in Photon Science and Particle Physics require silicon sensors with very demanding specifications. New accelerators like the European X-ray Free Electron Laser (EuXFEL) and the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), pose new challenges for silicon sensors, especially with respect to radiation hardness. High radiation doses and fluences damage the silicon crystal and the SiO 2 layers at the surface, thus changing the sensor properties and limiting their life time. Non-Ionizing Energy Loss (NIEL) of incident particles causes silicon crystal damage. Ionizing Energy Loss (IEL) of incident particles increases the densities of oxide charge and interface traps in the SiO 2 and at the Si-SiO 2 interface. In this thesis the surface radiation damage of the Si-SiO 2 system on high-ohmic Si has been investigated using circular MOSFETs biased in accumulation and inversion at an electric field in the SiO 2 of about 500 kV/cm. The MOSFETs have been irradiated by X-rays from an X-ray tube to a dose of about 17 kGy(SiO 2 ) in different irradiation steps. Before and after each irradiation step, the gate voltage has been cycled from inversion to accumulation conditions and back. From the dependence of the drain-source current on gate voltage the threshold voltage of the MOSFET and the hole and electron mobility at the Si-SiO 2 interface were determined. In addition, from the measured drain-source current the change of the oxide charge density during irradiation has been determined. The interface trap density and the oxide charge has been determined separately using the subthreshold current technique based on the Brews charge sheet model which has been applied for first time on MOSFETs built on high-ohmic Si. The results show a significant field-direction dependence of the surface radiation parameters. The extracted parameters and the acquired knowledge can be used to improve simulations of the surface radiation damage of silicon sensors.
Directory of Open Access Journals (Sweden)
Myunghwan Ryu
2016-01-01
Full Text Available We investigate the electrical characteristics of a double-gate-all-around (DGAA transistor with an asymmetric channel width using three-dimensional device simulation. The DGAA structure creates a silicon nanotube field-effect transistor (NTFET with a core-shell gate architecture, which can solve the problem of loss of gate controllability of the channel and provides improved short-channel behavior. The channel width asymmetry is analyzed on both sides of the terminals of the transistors, i.e., source and drain. In addition, we consider both n-type and p-type DGAA FETs, which are essential to forming a unit logic cell, the inverter. Simulation results reveal that, according to the carrier types, the location of the asymmetry has a different effect on the electrical properties of the devices. Thus, we propose the N/P DGAA FET structure with an asymmetric channel width to form the optimal inverter. Various electrical metrics are analyzed to investigate the benefits of the optimal inverter structure over the conventional inverter structure. Simulation results show that 27% delay and 15% leakage power improvement are enabled in the optimum structure.
Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.
2007-01-01
We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.
A radiation-tolerant, low-power non-volatile memory based on silicon nanocrystal quantum dots
Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; De Blauwe, J.; Green, M. L.
2001-01-01
Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO_2 is a critical aspect of the performance ...
Suspended graphene devices with local gate control on an insulating substrate
International Nuclear Information System (INIS)
Ong, Florian R; Cui, Zheng; Vojvodin, Cameron; Papaj, Michał; Deng, Chunqing; Bal, Mustafa; Lupascu, Adrian; Yurtalan, Muhammet A; Orgiazzi, Jean-Luc F X
2015-01-01
We present a fabrication process for graphene-based devices where a graphene monolayer is suspended above a local metallic gate placed in a trench. As an example we detail the fabrication steps of a graphene field-effect transistor. The devices are built on a bare high-resistivity silicon substrate. At temperatures of 77 K and below, we observe the field-effect modulation of the graphene resistivity by a voltage applied to the gate. This fabrication approach enables new experiments involving graphene-based superconducting qubits and nano-electromechanical resonators. The method is applicable to other two-dimensional materials. (paper)
A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics
Wallace, Robert M.
2001-03-01
Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.
Triangulating the Position of Antimony Donors Implanted in Silicon
Bureau-Oxton, Chloe; Nielsen, Erik; Luhman, Dwight; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Pioro-Ladrière, Michel; Lilly, Michael; Carroll, Malcolm
2015-03-01
A potential candidate for a quantum bit is a single Sb atom implanted in silicon. A single-electron-transistor (SET) situated close to an Sb donor can be used to measure the occupancy and spin of the electron on the donor while the lithographically patterned poly-silicon gates defining the SET can be used to control donor occupancy. In our samples two clusters of Sb donors have been implanted adjacent to opposite sides of the SET through a self-aligned process. In this talk, we will present experimental results that allow us to determine the approximate position of different donors by determining their relative capacitance to pairs of the SET's poly-silicon gates. We will present the results of capacitive-based modeling calculations that allow us to further locate the position of the donors. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.
Review on analog/radio frequency performance of advanced silicon MOSFETs
Passi, Vikram; Raskin, Jean-Pierre
2017-12-01
Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.
Silicon sensor probing and radiation studies for the LHCb silicon tracker
International Nuclear Information System (INIS)
Lois, Cristina
2006-01-01
The LHCb Silicon Tracker (ST) will be built using silicon micro-strip technology. A total of 1400 sensors, with strip pitches of approximately 200μm and three different substrate thicknesses, will be used to cover the sensitive area with readout strips up to 38cm in length. We present the quality assurance program followed by the ST group together with the results obtained for the first batches of sensors from the main production. In addition, we report on an investigation of the radiation hardness of the sensors. Prototype sensors were irradiated with 24GeV/c protons up to fluences equivalent to 20 years of LHCb operation. The damage coefficient for the leakage current was studied, and full depletion voltages were determined
Bishop, Nathaniel; Young, Ralph; Borras Pinilla, Carlos; Stalford, Harold; Nielsen, Erik; Muller, Richard; Rahman, Rajib; Tracy, Lisa; Wendt, Joel; Lilly, Michael; Carroll, Malcolm
2012-02-01
We discuss trade-offs of different double quantum dot and charge sensor lay-outs using computer assisted design (CAD). We use primarily a semi-classical model, augmented with a self-consistent configuration interaction method. Although CAD for quantum dots is difficult due to uncontrolled factors (e.g., disorder), different ideal designs can still be compared. Comparisons of simulation and measured dot characteristics, such as capacitance, show that CAD can agree well with experiment for relevant cases. CAD results comparing several different designs will be discussed including a comparison to measurement results from the same designs. Trade-offs between poly-silicon and metal gate lay-outs will also be discussed. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. The work was supported by the Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.
ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon
Tracy, Lisa; Luhman, Dwight; Carr, Stephen; Borchardt, John; Bishop, Nathaniel; Ten Eyck, Gregory; Pluym, Tammy; Wendt, Joel; Witzel, Wayne; Blume-Kohout, Robin; Nielsen, Erik; Lilly, Michael; Carroll, Malcolm
In this talk we will discuss electron spin resonance experiments in single donor silicon qubit devices fabricated at Sandia National Labs. A self-aligned device structure consisting of a polysilicon gate SET located adjacent to the donor is used for donor electron spin readout. Using a cryogenic HEMT amplifier next to the silicon device, we demonstrate spin readout at 100 kHz bandwidth and Rabi oscillations with 0.96 visibility. Electron spin resonance measurements on these devices show a linewidth of 30 kHz and coherence times T2* = 10 us and T2 = 0.3 ms. We also discuss estimates of the fidelity of our donor electron spin qubit measurements using gate set tomography. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000. ESR Experiments on a Single Donor Electron in Isotopically Enriched Silicon.
Sterol Regulation of Voltage-Gated K+ Channels.
Balajthy, Andras; Hajdu, Peter; Panyi, Gyorgy; Varga, Zoltan
2017-01-01
Cholesterol is an essential lipid building block of the cellular plasma membrane. In addition to its structural role, it regulates the fluidity and raft structure of the membrane and influences the course of numerous membrane-linked signaling pathways and the function of transmembrane proteins, including ion channels. This is supported by a vast body of scientific data, which demonstrates the modulation of ion channels with a great variety of ion selectivity, gating, and tissue distribution by changes in membrane cholesterol. Here, we review what is currently known about the modulation of voltage-gated K + (Kv) channels by changes in membrane cholesterol content, considering raft association of the channels, the roles of cholesterol recognition sites, and those of adaptor proteins in cholesterol-Kv channel interactions. We specifically focus on Kv1.3, the dominant K + channel of human T cells. Effects of cholesterol depletion and enrichment and 7-dehydrocholesterol enrichment on Kv1.3 gating are discussed in the context of the immunological synapse and the comparison of the in vitro effects of sterol modifications on Kv1.3 function with ex vivo effects on cells from hypercholesterolemic and Smith-Lemli-Opitz patients. © 2017 Elsevier Inc. All rights reserved.
A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process
Energy Technology Data Exchange (ETDEWEB)
Hemperek, Tomasz, E-mail: hemperek@uni-bonn.de; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert
2015-10-01
An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.
Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics
Alshareef, Husam N.
2010-11-19
Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.
Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics
Alshareef, Husam N.; Caraveo-Frescas, J. A.; Cha, D. K.
2010-01-01
Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.
Cobalt micro-magnet integration on silicon MOS quantum dots
Camirand Lemyre, Julien; Rochette, Sophie; Anderson, John; Manginell, Ronald P.; Pluym, Tammy; Ward, Dan; Carroll, Malcom S.; Pioro-Ladrière, Michel
Integration of cobalt micro-magnets on silicon metal-oxide-semiconductor (MOS) quantum dot devices has been investigated. The micro-magnets are fabricated in a lift-off process with e-beam lithography and deposited directly on top of an etched poly-silicon gate stack. Among the five resist stacks tested, one is found to be compatible with our MOS specific materials (Si and SiO2) . Moreover, devices with and without additional Al2O3 insulating layer show no additional gate leakage after processing. Preliminary transport data indicates electrostatic stability of our devices with integrated magnets. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.
Radiation damage in silicon detectors
Lindström, G
2003-01-01
Radiation damage effects in silicon detectors under severe hadron and gamma-irradiation are surveyed, focusing on bulk effects. Both macroscopic detector properties (reverse current, depletion voltage and charge collection) as also the underlying microscopic defect generation are covered. Basic results are taken from the work done in the CERN-RD48 (ROSE) collaboration updated by results of recent work. Preliminary studies on the use of dimerized float zone and Czochralski silicon as detector material show possible benefits. An essential progress in the understanding of the radiation-induced detector deterioration had recently been achieved in gamma irradiation, directly correlating defect analysis data with the macroscopic detector performance.
Bindal, Ahmet
2016-01-01
This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types...
International Nuclear Information System (INIS)
Xie Yuanbin; Quan Si; Ma Xiaohua; Zhang Jincheng; Li Qingmin; Hao Yue
2011-01-01
Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer. Direct-coupled FET logic circuits, such as an E/D HEMT inverter, NAND gate and D flip-flop, were fabricated on an AlGaN/GaN heterostructure. The D flip-flop and NAND gate are demonstrated in a GaN system for the first time. The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area, integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate. E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure. At a supply voltage of 2 V, the E/D inverter shows an output logic swing of 1.7 V, a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V. The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs. (semiconductor integrated circuits)
The two sides of silicon detectors
International Nuclear Information System (INIS)
Devine, S.R.
2001-10-01
Results are presented on in situ irradiation of silicon detector's at cryogenic temperature. The results show that irradiation at cryogenic temperatures does not detrimentally effect a silicon detectors performance when compared to its irradiation at room temperature. Operation of silicon devices at cryogenic temperatures offers the advantage of reducing radiation-induced leakage current to levels of a few pA, while at 130K the Lazarus Effect plays an important role i.e. minimum voltage required for full depletion. Performing voltage scans on a 'standard' silicon pad detector pre- and post annealing, the charge collection efficiency was found to be 60% at 200V and 95% at 200V respectively. Time dependence measurements are presented, showing that for a dose of 6.5x10 14 p/cm 2 (450GeV protons) the time dependence of the charge collection efficiency is negligible. However, for higher doses, 1.2x10 15 p/cm 2 , the charge collection efficiency drops from an initial measured value of 67% to a stable value of 58% over a period of 15 minutes for reversed biased diodes. An analysis of the 'double junction' effect is also presented. A comparison between the Transient Current Technique and an X-ray technique is presented. The double junction has been observed in p + /n/n + silicon detectors after irradiation beyond 'type inversion', corresponding to a fluence equivalent to ∼3x10 13 cm -2 1MeV neutrons, producing p + /p/n + and essentially two p-n junctions within one device. With increasing bias voltage, as the electric field is extending into the detector bulk from opposite sides of the silicon detector, there are two distinct depletion regions that collect charge signal independently. Summing the signal charge from the two regions, one is able to reconstruct the initial energy of the incident particle. From Transient Current measurements it is apparent that E-field manipulation is possible by excess carrier injection, enabling a high enough E-field to extend across the
The optimal design of 15 nm gate-length junctionless SOI FinFETs for reducing leakage current
International Nuclear Information System (INIS)
Liu, Xi; Wu, Meile; Jin, Xiaoshi; Chuai, Rongyan; Lee, Jung-Hee; Lee, Jong-Ho
2013-01-01
Junctionless (JL) transistors need to be heavily doped to have large drain current in the ON-state, which engenders the effect of band-to-band tunneling (BTBT) in the OFF-state simultaneously. It causes an obvious increase of the leakage current in the OFF-state. This paper presents an effective method of reducing the leakage current by changing the geometrical shape and dimension of the oxide layer under the edge of the gate. The optimal design of 15 nm gate-length JL silicon-on-insulator FinFETs with the triple-gate structure is performed for reducing the effect of BTBT through simulation and analysis by this means. (paper)
Novel Concepts for Silicon Based Photovoltaics and Photoelectrochemistry
Han, L.
2015-01-01
Long term concerns about climate change and fossil fuel depletion will require a transition towards energy systems powered by solar radiation or other renewable sources. Novel concepts based on silicon materials and devices are investigated for applications in the next generation photovoltaic (PV)
Neutron irradiation test of depleted CMOS pixel detector prototypes
International Nuclear Information System (INIS)
Mandić, I.; Cindro, V.; Gorišek, A.; Hiti, B.; Kramberger, G.; Mikuž, M.; Zavrtanik, M.; Hemperek, T.; Daas, M.; Hügging, F.; Krüger, H.; Pohl, D.-L.; Wermes, N.; Gonella, L.
2017-01-01
Charge collection properties of depleted CMOS pixel detector prototypes produced on p-type substrate of 2 kΩ cm initial resistivity (by LFoundry 150 nm process) were studied using Edge-TCT method before and after neutron irradiation. The test structures were produced for investigation of CMOS technology in tracking detectors for experiments at HL-LHC upgrade. Measurements were made with passive detector structures in which current pulses induced on charge collecting electrodes could be directly observed. Thickness of depleted layer was estimated and studied as function of neutron irradiation fluence. An increase of depletion thickness was observed after first two irradiation steps to 1 · 10 13 n/cm 2 and 5 · 10 13 n/cm 2 and attributed to initial acceptor removal. At higher fluences the depletion thickness at given voltage decreases with increasing fluence because of radiation induced defects contributing to the effective space charge concentration. The behaviour is consistent with that of high resistivity silicon used for standard particle detectors. The measured thickness of the depleted layer after irradiation with 1 · 10 15 n/cm 2 is more than 50 μm at 100 V bias. This is sufficient to guarantee satisfactory signal/noise performance on outer layers of pixel trackers in HL-LHC experiments.
Dual-Input AND Gate From Single-Channel Thin-Film FET
Miranda, F. A.; Pinto, N. J.; Perez, R.; Mueller, C. H.
2008-01-01
A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.
Influence of the gate edge on the reverse leakage current of AlGaN/GaN HEMTs
Directory of Open Access Journals (Sweden)
YongHe Chen
2015-09-01
Full Text Available By comparing the Schottky diodes of different area and perimeter, reverse gate leakage current of AlGaN/GaN high mobility transistors (HEMT at gate bias beyond threshold voltage is studied. It is revealed that reverse current consists of area-related and perimeter-related current. An analytical model of electric field calculation is proposed to obtain the average electric field around the gate edge at high revers bias and estimate the effective range of edge leakage current. When the reverse bias increases, the increment of electric field is around the gate edge of a distance of ΔL, and perimeter-related gate edge current keeps increasing. By using the calculated electric field and the temperature-dependent current-voltage measurements, the edge gate leakage current mechanism is found to be Fowler-Nordheim tunneling at gate bias bellows -15V caused by the lateral extended depletion region induced barrier thinning. Effective range of edge current of Schottky diodes is about hundred to several hundred nano-meters, and is different in different shapes of Schottky diodes.
Observation of soliton compression in silicon photonic crystals
Blanco-Redondo, A.; Husko, C.; Eades, D.; Zhang, Y.; Li, J.; Krauss, T.F.; Eggleton, B.J.
2014-01-01
Solitons are nonlinear waves present in diverse physical systems including plasmas, water surfaces and optics. In silicon, the presence of two photon absorption and accompanying free carriers strongly perturb the canonical dynamics of optical solitons. Here we report the first experimental demonstration of soliton-effect pulse compression of picosecond pulses in silicon, despite two photon absorption and free carriers. Here we achieve compression of 3.7 ps pulses to 1.6 ps with photonic crystal waveguide and an ultra-sensitive frequency-resolved electrical gating technique to detect the ultralow energies in the nanostructured device. Strong agreement with a nonlinear Schrödinger model confirms the measurements. These results further our understanding of nonlinear waves in silicon and open the way to soliton-based functionalities in complementary metal-oxide-semiconductor-compatible platforms. PMID:24423977
Asoka-Kumar, P.; Leung, T. C.; Lynn, K. G.; Nielsen, B.; Forcier, M. P.; Weinberg, Z. A.; Rubloff, G. W.
1992-06-01
The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions.
International Nuclear Information System (INIS)
Asoka-Kumar, P.; Leung, T.C.; Lynn, K.G.; Nielsen, B.; Forcier, M.P.; Weinberg, Z.A.; Rubloff, G.W.
1992-01-01
The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions
A low on-resistance SOI LDMOS using a trench gate and a recessed drain
International Nuclear Information System (INIS)
Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji
2012-01-01
An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)
Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira
2018-04-01
We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.
International Nuclear Information System (INIS)
Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto
2015-01-01
Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)
The paradox of characteristics of silicon detectors operated at temperature close to liquid helium
Eremin, V.; Shepelev, A.; Verbitskaya, E.; Zamantzas, C.; Galkin, A.
2018-05-01
The aim of this study is to give characterization of silicon p+/n/n+ detectors for the monitoring systems of the Large Hadron Collider machine at CERN with the focus on justifying the choice of silicon resistivity for the detector operation at the temperature of 1.9-10 K. The detectors from n-type silicon with the resistivity of 10, 4.5, and 0.5 kΩ cm were investigated at the temperature from 293 up to 7 K by the Transient Current Technique with a 660 nm pulse laser and alpha-particles. The shapes of the detector current pulse response allowed revealing a paradox in the properties of shallow donors of phosphorus, i.e., native dopants in the n-type Si. There was no carrier freeze-out on the phosphorus energy levels in the space charge region (SCR), and they remained positively charged irrespective of temperature, thus limiting the depleted region depth. As for the base region of a partially depleted detector, the levels became neutral at T < 28 K, which transformed silicon to an insulator. The reduction of the activation energy for carrier emission in the detector SCR estimated in the scope of the Poole-Frenkel effect failed to account for the impact of the electric field on the properties of phosphorus levels. The absence of carrier freeze-out in the SCR justifies the choice of high resistivity silicon as the only proper material for detector operation in a fully depleted mode at extremely low temperature.
Ion-step method for surface potential sensing of silicon nanowires
Chen, S.; van Nieuwkasteele, Jan William; van den Berg, Albert; Eijkel, Jan C.T.
2016-01-01
This paper presents a novel stimulus-response method for surface potential sensing of silicon nanowire (Si NW) field-effect transistors. When an "ion-step" from low to high ionic strength is given as a stimulus to the gate oxide surface, an increase of double layer capacitance is therefore expected.
Multiple batch recharging for industrial CZ silicon growth
Fickett, B.; Mihalik, G.
2001-05-01
The Czochralski (CZ) crystal growth process used in the Siemens Solar Industries’ (SSI) Vancouver, WA facility was non-continuous. Each furnace run's production was limited by the size of the starting charge. Once the charge was depleted, the furnace was shut down, cooled, and set back up for the next run. A recharge system was developed which transforms standard CZ growth into a semi-continuous process. Now when the charge is depleted, the crucible can be refilled in situ as the grown ingot is being removed from the furnace. SSI has demonstrated up to 14 recharge cycles in a single run. The resulting benefits included: significant cost reduction, increased yield, increased throughput, reduced energy consumption, improved process capability, reduced material handling requirements, and reduced labor. The recharge system also enables the use of granular silicon, which requires less than 30% of the energy required when manufacturing silicon-starting materials. This significantly reduces the energy “pay-back” time associated with SSI's finished product, photovoltaic panels.
A low specific on-resistance SOI MOSFET with dual gates and a recessed drain
International Nuclear Information System (INIS)
Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun
2013-01-01
A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)
Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan
2016-01-01
Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.
Catheter-based time-gated near-infrared fluorescence/OCT imaging system
Lu, Yuankang; Abran, Maxime; Cloutier, Guy; Lesage, Frédéric
2018-02-01
We developed a new dual-modality intravascular imaging system based on fast time-gated fluorescence intensity imaging and spectral domain optical coherence tomography (SD-OCT) for the purpose of interventional detection of atherosclerosis. A pulsed supercontinuum laser was used for fluorescence and OCT imaging. A double-clad fiber (DCF)- based side-firing catheter was designed and fabricated to have a 23 μm spot size at a 2.2 mm working distance for OCT imaging. Its single-mode core is used for OCT, while its inner cladding transports fluorescence excitation light and collects fluorescent photons. The combination of OCT and fluorescence imaging was achieved by using a DCF coupler. For fluorescence detection, we used a time-gated technique with a novel single-photon avalanche diode (SPAD) working in an ultra-fast gating mode. A custom-made delay chip was integrated in the system to adjust the delay between the excitation laser pulse and the SPAD gate-ON window. This technique allowed to detect fluorescent photons of interest while rejecting most of the background photons, thus leading to a significantly improved signal to noise ratio (SNR). Experiments were carried out in turbid media mimicking tissue with an indocyanine green (ICG) inclusion (1 mM and 100 μM) to compare the time-gated technique and the conventional continuous detection technique. The gating technique increased twofold depth sensitivity, and tenfold SNR at large distances. The dual-modality imaging capacity of our system was also validated with a silicone-based tissue-mimicking phantom.
Electrical Control of g-Factor in a Few-Hole Silicon Nanowire MOSFET.
Voisin, B; Maurand, R; Barraud, S; Vinet, M; Jehl, X; Sanquer, M; Renard, J; De Franceschi, S
2016-01-13
Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred mega-Hertz.
International Nuclear Information System (INIS)
Yuan, Yang; Yong, Gao; Peng-Liang, Gong
2008-01-01
A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)
A monolithic active pixel sensor for ionizing radiation using a 180 nm HV-SOI process
Energy Technology Data Exchange (ETDEWEB)
Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany)
2016-07-01
An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-180 nm High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. Standard FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to trapped charge in the buried oxide layer and charged interface states created at the silicon oxide boundaries (back gate effect). The X-FAB 180 nm HV-SOI technology offers an additional isolation using a deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection. The design and measurement results from first prototypes are presented including radiation tolerance to total ionizing dose and charge collection properties of neutron irradiated samples.
International Nuclear Information System (INIS)
Hemed, Nofar Mintz; Inberg, Alexandra; Shacham-Diamand, Yosi
2013-01-01
We herein report on the stability of Electrolyte/Insulator/Semiconductor (EIS) devices with Self-Assembled Monolayer (SAM) gate insulator layers, i.e. Electrolyte/SAM/Semiconductor (ESS) devices. ESS devices can be functionalized creating highly specific sensors that can be integrated on standard silicon platform. However, biosensors by their nature are in contact with biological solutions that contain ions and molecules that may affect the device characteristics and cause electrical instability. In this paper we present a list of potential hazards to ESS devices and a study of the device stability under common testing conditions analyzing possible causes for the instabilities. ESS capacitors under open circuit conditions (i.e. open circuit bias of ∼0.6 V vs. Ag/AgCl reference electrode) were periodically characterized. We measured the complex impedance of the capacitors versus bias and extracted the effective capacitance vs. voltage (C–V) curves using two methods. We observed a parallel shift of the C–V curves toward negative bias; showing an effective accumulation of positive charge. The quantitative analysis of the drift vs. time was found to depend on the effective capacitance evaluation method. This effect is discussed and a best-known method is proposed. The devices surface composition was tested before and after the stress experiment by X-ray Photoelectron Spectroscopy (XPS) and sodium accumulation was observed. To further explore the flat-band voltage drift effect and to challenge the assumption that alkali ions are involved in the drift we conceived a novel alkali-free phosphate buffer saline (AF-PBS) where the sodium and potassium ions are replaced by ammonium ion and tested the capacitor under similar conditions to standard PBS. We found that the drift of the AF-PBS solution was much less at the first hour but was similar to that of the conventional PBS for longer stress times; hence, AF-PBS does not solve the long-term instability problem
SO-limited mobility in a germanium inversion channel with non-ideal metal gate
International Nuclear Information System (INIS)
Shah, Raheel; De Souza, M.M.
2008-01-01
Germanium is an attractive candidate for ultra fast CMOS technology due to its potential for doubling electron mobility and quadrupling hole mobility in comparison to silicon. To maintain the requirements of the International Technology Roadmap for Semiconductors (ITRS), high-κ insulators and metal gates will be required in conjunction with Ge technology. Key issues which will have to be addressed in achieving Ge technology are: trap free insulators, assessment of appropriate crystallographic orientations and the selection of gate metals for the best mobility. In this work mobilities are evaluated for Ge-nMOSFET with two metal gates (Al and TiN) and high-κ (HfO 2 ) insulator. Scattering with bulk phonons, surface roughness and high-κ phonons are taken into account. It is predicted that Al as the gate material on Ge {100} substrate performs 50% better than Ge {111} orientation at a sheet concentration of 1 x 10 13 cm -2 . Surface roughness is likely to be the most damaging mobility degradation mechanism at high fields for Ge {111}
Directory of Open Access Journals (Sweden)
Jia Ge
2014-01-01
Full Text Available We present an alternative method of depositing a high-quality passivation film for heterojunction silicon wafer solar cells, in this paper. The deposition of hydrogenated intrinsic amorphous silicon suboxide is accomplished by decomposing hydrogen, silane, and carbon dioxide in an industrial remote inductively coupled plasma platform. Through the investigation on CO2 partial pressure and process temperature, excellent surface passivation quality and optical properties are achieved. It is found that the hydrogen content in the film is much higher than what is commonly reported in intrinsic amorphous silicon due to oxygen incorporation. The observed slow depletion of hydrogen with increasing temperature greatly enhances its process window as well. The effective lifetime of symmetrically passivated samples under the optimal condition exceeds 4.7 ms on planar n-type Czochralski silicon wafers with a resistivity of 1 Ωcm, which is equivalent to an effective surface recombination velocity of less than 1.7 cms−1 and an implied open-circuit voltage (Voc of 741 mV. A comparison with several high quality passivation schemes for solar cells reveals that the developed inductively coupled plasma deposited films show excellent passivation quality. The excellent optical property and resistance to degradation make it an excellent substitute for industrial heterojunction silicon solar cell production.
Two-electron states of a group-V donor in silicon from atomistic full configuration interactions
Tankasala, Archana; Salfi, Joseph; Bocquel, Juanita; Voisin, Benoit; Usman, Muhammad; Klimeck, Gerhard; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.; Rogge, Sven; Rahman, Rajib
2018-05-01
Two-electron states bound to donors in silicon are important for both two-qubit gates and spin readout. We present a full configuration interaction technique in the atomistic tight-binding basis to capture multielectron exchange and correlation effects taking into account the full band structure of silicon and the atomic-scale granularity of a nanoscale device. Excited s -like states of A1 symmetry are found to strongly influence the charging energy of a negative donor center. We apply the technique on subsurface dopants subjected to gate electric fields and show that bound triplet states appear in the spectrum as a result of decreased charging energy. The exchange energy, obtained for the two-electron states in various confinement regimes, may enable engineering electrical control of spins in donor-dot hybrid qubits.
Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs
Bischoff, Paul
The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.
Hwang, Wang-Taek; Min, Misook; Jeong, Hyunhak; Kim, Dongku; Jang, Jingon; Yoo, Daekyung; Jang, Yeonsik; Kim, Jun-Woo; Yoon, Jiyoung; Chung, Seungjun; Yi, Gyu-Chul; Lee, Hyoyoung; Wang, Gunuk; Lee, Takhee
2016-11-25
We investigated the electrical characteristics and the charge transport mechanism of pentacene vertical hetero-structures with graphene electrodes. The devices are composed of vertical stacks of silicon, silicon dioxide, graphene, pentacene, and gold. These vertical heterojunctions exhibited distinct transport characteristics depending on the applied bias direction, which originates from different electrode contacts (graphene and gold contacts) to the pentacene layer. These asymmetric contacts cause a current rectification and current modulation induced by the gate field-dependent bias direction. We observed a change in the charge injection barrier during variable-temperature current-voltage characterization, and we also observed that two distinct charge transport channels (thermionic emission and Poole-Frenkel effect) worked in the junctions, which was dependent on the bias magnitude.
Fazzi, A
2000-01-01
The performance of a near room temperature X-ray spectroscopic system is reported. The system is based on a charge preamplifier with the first transistor having two separated gates. The preamplifier operates in a continuous reset mode without any physical resistor connected to the input node. The leakage current and the current due to the rate of X-rays is neutralized by an average current of holes, flowing under the control of an additional feedback, from the bottom to the top gate. The preamplifier is followed by a simple circuit which exactly cancels the long tail of the impulse response of a pure double-gate preamplifier. The compensation of this tail, due to the very principle of the preamplifier's continuous reset through the double-gate mechanism, improves substantially the high-rate performance of the system. The preamplifier based on a commercially available double-gate front JFET MX-40 (MOXTEK) coupled to a silicon drift detector produced at BNL achieved ENC of 13 electrons at -30 deg. C. The analys...
Impacts of gate bias and its variation on gamma-ray irradiation resistance of SiC MOSFETs
Energy Technology Data Exchange (ETDEWEB)
Murata, Koichi; Mitomo, Satoshi; Matsuda, Takuma; Yokoseki, Takashi [Saitama University, Sakuraku (Japan); National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Makino, Takahiro; Onoda, Shinobu; Takeyama, Akinori; Ohshima, Takeshi [National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Okubo, Shuichi; Tanaka, Yuki; Kandori, Mikio; Yoshie, Toru [Sanken Electric Co., Ltd., Niiza, Saitama (Japan); Hijikata, Yasuto [Saitama University, Sakuraku (Japan)
2017-04-15
Gamma-ray irradiation into vertical type n-channel hexagonal (4H)-silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) was performed under various gate biases. The threshold voltage for the MOSFETs irradiated with a constant positive gate bias showed a large negative shift, and the shift slightly recovered above 100 kGy. For MOSFETs with non- and a negative constant biases, no significant change in threshold voltage, V{sub th}, was observed up to 400 kGy. By changing the gate bias from positive bias to either negative or non-bias, the V{sub th} significantly recovered from the large negative voltage shift induced by 50 kGy irradiation with positive gate bias after only 10 kGy irradiation with either negative or zero bias. It indicates that the positive charges generated in the gate oxide near the oxide-SiC interface due to irradiation were removed or recombined instantly by the irradiation under zero or negative biases. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)
A SiC MOSFET Power Module With Integrated Gate Drive for 2.5 MHz Class E Resonant Converters
DEFF Research Database (Denmark)
Jørgensen, Asger Bjørn; Nair, Unnikrishnan Raveendran; Munk-Nielsen, Stig
2018-01-01
Industrial processes are still relying on high frequency converters based on vacuum tubes. Emerging silicon carbide semiconductor devices have potential to replace vacuum tubes and bring benefits for converters in the high frequency range. At high switching frequencies hard-switched gate drivers...
Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng
2018-04-09
As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 10 6 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.
Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.
2017-11-01
To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to
High-κ gate dielectrics: Current status and materials properties considerations
Wilk, G. D.; Wallace, R. M.; Anthony, J. M.
2001-05-01
Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.
Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method
Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito
2018-05-01
In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.
Silicon nanowire hot carrier electroluminescence
Energy Technology Data Exchange (ETDEWEB)
Plessis, M. du, E-mail: monuko@up.ac.za; Joubert, T.-H.
2016-08-31
Avalanche electroluminescence from silicon pn junctions has been known for many years. However, the internal quantum efficiencies of these devices are quite low due to the indirect band gap nature of the semiconductor material. In this study we have used reach-through biasing and SOI (silicon-on-insulator) thin film structures to improve the internal power efficiency and the external light extraction efficiency. Both continuous silicon thin film pn junctions and parallel nanowire pn junctions were manufactured using a custom SOI technology. The pn junctions are operated in the reach-through mode of operation, thus increasing the average electric field within the fully depleted region. Experimental results of the emission spectrum indicate that the most dominant photon generating mechanism is due to intraband hot carrier relaxation processes. It was found that the SOI nanowire light source external power efficiency is at least an order of magnitude better than the comparable bulk CMOS (Complementary Metal Oxide Semiconductor) light source. - Highlights: • We investigate effect of electric field on silicon avalanche electroluminescence. • With reach-through pn junctions the current and carrier densities are kept constant. • Higher electric fields increase short wavelength radiation. • Higher electric fields decrease long wavelength radiation. • The effect of the electric field indicates intraband transitions as main mechanism.
Kim, Young-Hee
Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is
SiC Power MOSFET with Improved Gate Dielectric
Energy Technology Data Exchange (ETDEWEB)
Sbrockey, Nick M. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Spencer, Michael G. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Chandrashekhar, Chandra M.V. S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)
2010-08-23
In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.
Silicon Quantum Dots for Quantum Information Processing
2013-11-01
S. Lai, C. Tahan, A. Morello and A. S. Dzurak, Electron Spin lifetimes in multi-valley sil- icon quantum dots, S3NANO Winter School Few spin solid...lifetimes in multi-valley sil- icon quantum dots, International Workshop on Silicon Quantum Electronics, Grenoble, France, February 2012 (Poster). C...typically plunger gates), PMMA A5 is spun at 5000 rpm for 30 seconds, resulting in a 280 nm resist thickness. The resists are baked for 90 seconds at 180
100-nm gate lithography for double-gate transistors
Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.
2001-09-01
The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.
Directory of Open Access Journals (Sweden)
Jaehoon Park
2010-06-01
Full Text Available We investigated the electrical stabilities of two types of pentacene-based organic thin-film transistors (OTFTs with two different polymeric dielectrics: polystyrene (PS and poly(4-vinyl phenol (PVP, in terms of the interfacial charge depletion. Under a short-term bias stress condition, the OTFT with the PVP layer showed a substantial increase in the drain current and a positive shift of the threshold voltage, while the PS layer case exhibited no change. Furthermore, a significant increase in the off-state current was observed in the OTFT with the PVP layer which has a hydroxyl group. In the presence of the interfacial hydroxyl group in PVP, the holes are not fully depleted during repetitive operation of the OTFT with the PVP layer and a large positive gate voltage in the off-state regime is needed to effectively refresh the electrical characteristics. It is suggested that the depletion-limited holes at the interface, i.e., interfacial charge depletion, between the PVP layer and the pentacene layer play a critical role on the electrical stability during operation of the OTFT.
High temperature study of flexible silicon-on-insulator fin field-effect transistors
Diab, Amer El Hajj
2014-09-29
We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.
Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid
2018-03-01
We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.
Laux, S. E.; Kumar, A.; Fischetti, M. V.
2004-05-01
A two-dimensional device simulation program which self consistently solves the Schrödinger and Poisson equations with current flow is described in detail. Significant approximations adopted in this work are the absence of scattering and a simple six-valley, parabolic band structure for silicon. A modified version of the quantum transmitting boundary method is used to describe open boundary conditions permitting current flow in device solutions far from equilibrium. The continuous energy spectrum of the system is discretized by temporarily imposing two different forms of closed boundary conditions, resulting in energies which sample the density-of-states and establish the wave function normalization conditions. These standing wave solutions ("normal modes") are decomposed into their traveling wave constituents, each of which represents injection from only one of the open boundary contacts ("traveling eigencomponents"). These current-carrying states are occupied by a drifted Fermi distribution associated with their injecting contact and summed to form the electron density in the device. Holes are neglected in this calculation. The Poisson equation is solved on the same finite element computational mesh as the Schrödinger equation; devices of arbitrary geometry can be modeled. Computational performance of the program including characterization of a "Broyden+Newton" algorithm employed in the iteration for self consistency is described. Device results are presented for a narrow silicon resonant tunneling diode (RTD) and many variants of idealized silicon double-gate field effect transistors (DGFETs). The RTD results show two resonant conduction peaks, each of which demonstrates hysteresis. Three 7.5 nm channel length DGFET structures with identical intrinsic device configurations but differing access geometries (straight, taper and "dog bone") are studied and found to have differing current flows owing to quantum-mechanical reflection in their access regions
Wadhwa, Girish; Raj, Balwinder
2018-05-01
Nanoscale devices are emerging as a platform for detecting biomolecules. Various issues were observed during the fabrication process such as random dopant fluctuation and thermal budget. To reduce these issues charge-plasma-based concept is introduced. This paper proposes the implementation of charge-plasma-based gate underlap dielectric modulated junctionless tunnel field effect transistor (DM-JLTFET) for the revelation of biomolecule immobilized in the open cavity gate channel region. In this p+ source and n+ drain regions are introduced by employing different work function over the intrinsic silicon. Also dual material gate architecture is implemented to reduce short channel effect without abandoning any other device characteristic. The sensitivity of biosensor is studied for both the neutral and charge-neutral biomolecules. The effect of device parameters such as channel thickness, cavity length and cavity thickness on drain current have been analyzed through simulations. This paper investigates the performance of charge-plasma-based gate underlap DM-JLTFET for biomolecule sensing applications while varying dielectric constant, charge density at different biasing conditions.
Gating-ML: XML-based gating descriptions in flow cytometry.
Spidlen, Josef; Leif, Robert C; Moore, Wayne; Roederer, Mario; Brinkman, Ryan R
2008-12-01
The lack of software interoperability with respect to gating due to lack of a standardized mechanism for data exchange has traditionally been a bottleneck, preventing reproducibility of flow cytometry (FCM) data analysis and the usage of multiple analytical tools. To facilitate interoperability among FCM data analysis tools, members of the International Society for the Advancement of Cytometry (ISAC) Data Standards Task Force (DSTF) have developed an XML-based mechanism to formally describe gates (Gating-ML). Gating-ML, an open specification for encoding gating, data transformations and compensation, has been adopted by the ISAC DSTF as a Candidate Recommendation. Gating-ML can facilitate exchange of gating descriptions the same way that FCS facilitated for exchange of raw FCM data. Its adoption will open new collaborative opportunities as well as possibilities for advanced analyses and methods development. The ISAC DSTF is satisfied that the standard addresses the requirements for a gating exchange standard.
Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices
Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa
2013-01-01
(100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree
Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.
2018-02-01
A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.
Top-gated field-effect LaAlO{sub 3}/SrTiO{sub 3} devices made by ion-irradiation
Energy Technology Data Exchange (ETDEWEB)
Hurand, S.; Jouan, A.; Feuillet-Palma, C.; Singh, G.; Malnou, M.; Lesueur, J.; Bergeal, N. [Laboratoire de Physique et d' Etude des Matériaux-CNRS-ESPCI ParisTech-UPMC, PSL Research University, 10 Rue Vauquelin - 75005 Paris (France); Lesne, E.; Reyren, N.; Barthélémy, A.; Bibes, M.; Villegas, J. E. [Unité Mixte de Physique CNRS-Thales, 1 Av. A. Fresnel, 91767 Palaiseau (France); Ulysse, C. [Laboratoire de Photonique et de Nanostructures LPN-CNRS, Route de Nozay, 91460 Marcoussis and Universit Paris Sud, 91405 Orsay (France); Pannetier-Lecoeur, M. [DSM/IRAMIS/SPEC - CNRS UMR 3680, CEA Saclay, F-91191 Gif-sur-Yvette Cedex (France)
2016-02-01
We present a method to fabricate top-gated field-effect devices in a LaAlO{sub 3}/SrTiO{sub 3} two-dimensional electron gas (2-DEG). Prior to the gate deposition, the realisation of micron size conducting channels in the 2-DEG is achieved by an ion-irradiation with high-energy oxygen ions. After identifying the ion fluence as the key parameter that determines the electrical transport properties of the channels, we demonstrate the field-effect operation. At low temperature, the normal state resistance and the superconducting T{sub c} can be tuned over a wide range by a top-gate voltage without any leakage. A superconductor-to-insulator quantum phase transition is observed for a strong depletion of the 2-DEG.
Li, Fu-Hai; Chiu, Yung-Yueh; Lee, Yen-Hui; Chang, Ru-Wei; Yang, Bo-Jun; Sun, Wein-Town; Lee, Eric; Kuo, Chao-Wei; Shirota, Riichiro
2013-04-01
In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon-oxide-nitride-oxide-silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.
Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method
International Nuclear Information System (INIS)
Kobayashi, H.; Kim, W. B.; Matsumoto, T.
2011-01-01
We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)
International Nuclear Information System (INIS)
Wang, Tun; Liu, Bin; Jiang, Shusen; Rong, Hao; Lu, Miao
2014-01-01
A device including a pair of top electrodes and a local gate in the bottom of an SU-8 trench was fabricated on a glass substrate for dielectrophoresis assembly and electrical characterization of suspended nanomaterials. The three terminals were made of gold electrodes and electrically isolated from each other by an air gap. Compared to the widely used global back-gate silicon device, the parasitic capacitance between the three terminals was significantly reduced and an individual gate was assigned to each device. In addition, the spacing from the bottom-gate to either the source or drain was larger than twice the source-drain gap, which guaranteed that the electric field between the source and drain in the dielectrophoresis assembly was not distinguished by the bottom-gate. To prove the feasibility and versatility of the device, a suspended carbon nanotube and graphene film were assembled by dielectrophoresis and characterized successfully. Accordingly, the proposed device holds promise for the electrical characterization of suspended nanomaterials, especially in a high frequency resonator or transistor configuration. (paper)
Navlakha, Nupur; Kranti, Abhinav
2017-07-01
Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.
Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs
Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.
2009-12-01
The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.
Islam, R.; Uddin, M. M.; Hossain, M. Mofazzal; Matin, M. A.
The design of a 1μm gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42m2V-1s-1 at Vg=0V, a small pinch off gate voltage (Vp) of -0.25V, a maximum extrinsic transconductance (gm) of ˜4.85mS/μm and a drain current density of more than 3.34mA/μm. A short-circuit current-gain cut-off frequency (fT) of 374GHz and a maximum oscillation frequency (fmax) of 645GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.
Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang
2016-12-01
Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.
Energy Technology Data Exchange (ETDEWEB)
Mikhaylova, A. I., E-mail: m.aleksey.spb@gmail.com; Afanasyev, A. V.; Ilyin, V. A.; Luchinin, V. V. [St. Petersburg State Electrotechnical University LETI (Russian Federation); Sledziewski, T. [Friedrich–Alexander–Universität Erlangen–Nürnberg (Germany); Reshanov, S. A.; Schöner, A. [Ascatron AB (Sweden); Krieger, M. [Friedrich–Alexander–Universität Erlangen–Nürnberg (Germany)
2016-01-15
The effect of phosphorus implantation into a 4H-SiC epitaxial layer immediately before the thermal growth of a gate insulator in an atmosphere of dry oxygen on the reliability of the gate insulator is studied. It is found that, together with passivating surface states, the introduction of phosphorus ions leads to insignificant weakening of the dielectric breakdown field and to a decrease in the height of the energy barrier between silicon carbide and the insulator, which is due to the presence of phosphorus atoms at the 4H-SiC/SiO{sub 2} interface and in the bulk of silicon dioxide.
Heo, Jun-Woo; Kim, Young-Jin; Kim, Hyun-Seok
2014-12-01
We report two approaches to fabricating high performance normally-off AIGaN/GaN high-electron mobility transistors (HEMTs). The fabrication techniques employed were based on recessed-metal-insulator-semiconductor (MIS) gate and recessed fluoride-based plasma treatment. They were selectively applied to the area under the gate electrode to deplete the two-dimensional electron gas (2-DEG) density. We found that the recessed gate structure was effective in shifting the threshold voltage by controlling the etching depth of gate region to reduce the AIGaN layer thickness to less than 8 nm. Likewise, the CF4 plasma treatment effectively incorporated negatively charged fluorine ions into the thin AIGaN barrier so that the threshold voltage shifted to higher positive values. In addition to the increased threshold voltage, experimental results showed a maximum drain current and a maximum transconductance of 315 mA/mm and 100 mS/mm, respectively, for the recessed-MIS gate HEMT, and 340 mA/mm and 330 mS/mm, respectively, for the fluoride-based plasma treated HEMT.
International Nuclear Information System (INIS)
Kapetanakis, E.; Skarlatos, D.; Tsamis, C.; Normand, P.; Tsoukalas, D.
2003-01-01
Metal-oxide-semiconductor tunnel diodes with gate oxides, in the range of 2.5-3.5 nm, grown either on 25 or 3 keV nitrogen-implanted Si substrates at (0.3 or 1) x10 15 cm -2 dose, respectively, are investigated. The dependence of N 2 + ion implant energy on the electrical quality of the growing oxide layers is studied through capacitance, equivalent parallel conductance, and gate current measurements. Superior electrical characteristics in terms of interface state trap density, leakage current, and breakdown fields are found for oxides obtained through 3 keV nitrogen implants. These findings together with the full absence of any extended defect in the silicon substrate make the low-energy nitrogen implantation technique an attractive option for reproducible low-cost growth of nanometer-thick gate oxides
Graphene barristor, a triode device with a gate-controlled Schottky barrier.
Yang, Heejun; Heo, Jinseong; Park, Seongjun; Song, Hyun Jae; Seo, David H; Byun, Kyung-Eun; Kim, Philip; Yoo, InKyeong; Chung, Hyun-Jong; Kim, Kinam
2012-06-01
Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.
International Nuclear Information System (INIS)
Briere, M.A.
1993-07-01
Resonant nuclear reaction analysis, using the 1 H( 15 N, αγ) 12 C reaction at 6.4 MeV, has been successfully applied to the investigation of hydrogen incorporation and radiation induced migration in metal-oxide-silicon structures. A preliminary study of the influence of processing parameters on the H content of thermal oxides, with and without gate material present, has been performed. It is found that the dominant source of hydrogen in Al gate devices and dry oxides is often contamination, likely in the form of adsorbed water vapor, formed upon exposure to room air after removal from the oxidation furnace. Concentrations of hydrogen in the bulk oxide as high as 3 10 20 cm -3 (Al gate), and as low as 1 10 18 cm -3 (poly Si-gate) have been observed. Hydrogen accumulation at the Si-SiO 2 interface has been reproducibly demonstrated for as-oxidized samples, as well as for oxides exposed to H 2 containing atmospheres during subsequent thermal processing. The migration of hydrogen, from the bulk oxide to the silicon-oxide interface during NRA, has been observed and intensively investigated. A direct correlation between the hydrogen content of the bulk oxide and the radiation generated oxide charges and interface states is presented. These data provide strong support for the important role of hydrogen in determining the radiation sensitivity of electronic devices. (orig.)
Characterization procedures for double-sided silicon microstrip detectors
Energy Technology Data Exchange (ETDEWEB)
Bruner, N.L. [New Mexico Univ., Albuquerque, NM (United States). New Mexico Center for Particle Phys.; Frautschi, M.A. [New Mexico Univ., Albuquerque, NM (United States). New Mexico Center for Particle Phys.; Hoeferkamp, M.R. [New Mexico Univ., Albuquerque, NM (United States). New Mexico Center for Particle Phys.; Seidel, S.C. [New Mexico Univ., Albuquerque, NM (United States). New Mexico Center for Particle Phys.
1995-08-15
Since double-sided silicon microstrip detectors are still evolving technologically and are not yet commercially available, they require extensive electrical evaluation by the user to ensure they were manufactured to specifications. In addition, measurements must be performed to determine detector operating conditions. Procedures for measuring the following quantities are described: - Leakage current, - Depletion voltage, - Bias resistance, - Interstrip resistance, - Coupling capacitance, - Coupling capacitor breakdown voltage. (orig.).
Characterization procedures for double-sided silicon microstrip detectors
International Nuclear Information System (INIS)
Bruner, N.L.; Frautschi, M.A.; Hoeferkamp, M.R.; Seidel, S.C.
1995-01-01
Since double-sided silicon microstrip detectors are still evolving technologically and are not yet commercially available, they require extensive electrical evaluation by the user to ensure they were manufactured to specifications. In addition, measurements must be performed to determine detector operating conditions. Procedures for measuring the following quantities are described: - Leakage current, - Depletion voltage, - Bias resistance, - Interstrip resistance, - Coupling capacitance, - Coupling capacitor breakdown voltage. (orig.)
Ellinger, Frank; Mikolajick, Thomas; Fettweis, Gerhard; Hentschel, Dieter; Kolodinski, Sabine; Warnecke, Helmut; Reppe, Thomas; Tzschoppe, Christoph; Dohl, Jan; Carta, Corrado; Fritsche, David; Tretter, Gregor; Wiatr, Maciej; Detlef Kronholz, Stefan; Mikalo, Ricardo Pablo; Heinrich, Harald; Paulo, Robert; Wolf, Robert; Hübner, Johannes; Waltsgott, Johannes; Meißner, Klaus; Richter, Robert; Michler, Oliver; Bausinger, Markus; Mehlich, Heiko; Hahmann, Martin; Möller, Henning; Wiemer, Maik; Holland, Hans-Jürgen; Gärtner, Roberto; Schubert, Stefan; Richter, Alexander; Strobel, Axel; Fehske, Albrecht; Cech, Sebastian; Aßmann, Uwe; Pawlak, Andreas; Schröter, Michael; Finger, Wolfgang; Schumann, Stefan; Höppner, Sebastian; Walter, Dennis; Eisenreich, Holger; Schüffny, René
2013-07-01
An overview about the German cluster project Cool Silicon aiming at increasing the energy efficiency for semiconductors, communications, sensors and software is presented. Examples for achievements are: 1000 times reduced gate leakage in transistors using high-fc (HKMG) materials compared to conventional poly-gate (SiON) devices at the same technology node; 700 V transistors integrated in standard 0.35 μm CMOS; solar cell efficiencies above 19% at cars Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.
International Nuclear Information System (INIS)
Cho, Seongjae; Shim, Wonbo; Park, Ilhan; Kim, Yoon; Park, Byunggook
2010-01-01
In this work, a nonvolatile memory (NVM) device of novel structure in 3 dimensions is introduced, and its operation physics is validated. It is based on a pillar structure in which two identical storage nodes are located for dual-bit operation. The two storage nodes on neighboring pillars are controlled by using one common control gate so that the space between silicon pillars can be further reduced. For compatibility with conventional memory operations, an additional cut-off gate is constructed under the common control gate. This is considered as the ultimate form for a 3-D nonvolatile memory device based on a double-gate structure. The underlying physics is explained, and the operational schemes are validated in various aspects by using a numerical device simulation. Also, critical issues in device design for higher reliability are discussed.
Thermal Stress of Surface of Mold Cavities and Parting Line of Silicone Molds
Directory of Open Access Journals (Sweden)
Bajčičák Martin
2014-06-01
Full Text Available The paper is focused on the study of thermal stress of surface of mold cavities and parting line of silicone molds after pouring. The silicone mold White SD - THT was thermally stressed by pouring of ZnAl4Cu3 zinc alloy with pouring cycle 20, 30 and 40 seconds. The most thermally stressed part of surface at each pouring cycle is gating system and mold cavities. It could be further concluded that linear increase of the pouring cycle time leads to the exponential increasing of the maximum temperature of mold surface after its cooling. The elongated pouring cycle increases the temperature accumulated on the surface of cavities and the ability of silicone mold to conduct the heat on its surface decreases, because the low thermal conductivity of silicone molds enables the conduction of larger amount of heat into ambient environment.
Ultraclean single, double, and triple carbon nanotube quantum dots with recessed Re bottom gates
Jung, Minkyung; Schindele, Jens; Nau, Stefan; Weiss, Markus; Baumgartner, Andreas; Schoenenberger, Christian
2014-03-01
Ultraclean carbon nanotubes (CNTs) that are free from disorder provide a promising platform to manipulate single electron or hole spins for quantum information. Here, we demonstrate that ultraclean single, double, and triple quantum dots (QDs) can be formed reliably in a CNT by a straightforward fabrication technique. The QDs are electrostatically defined in the CNT by closely spaced metallic bottom gates deposited in trenches in Silicon dioxide by sputter deposition of Re. The carbon nanotubes are then grown by chemical vapor deposition (CVD) across the trenches and contacted using conventional electron beam lithography. The devices exhibit reproducibly the characteristics of ultraclean QDs behavior even after the subsequent electron beam lithography and chemical processing steps. We demonstrate the high quality using CNT devices with two narrow bottom gates and one global back gate. Tunable by the gate voltages, the device can be operated in four different regimes: i) fully p-type with ballistic transport between the outermost contacts (over a length of 700 nm), ii) clean n-type single QD behavior where a QD can be induced by either the left or the right bottom gate, iii) n-type double QD and iv) triple bipolar QD where the middle QD has opposite doping (p-type). Research at Basel is supported by the NCCR-Nano, NCCR-QIST, ERC project QUEST, and FP7 project SE2ND.
International Nuclear Information System (INIS)
Huffer, E.; Nifenecker, H.
2001-02-01
This document deals with the physical, chemical and radiological properties of the depleted uranium. What is the depleted uranium? Why do the military use depleted uranium and what are the risk for the health? (A.L.B.)
First tests with fully depleted PN-CCD's
International Nuclear Information System (INIS)
Strueder, L.; Lutz, G.; Sterzik, M.; Holl, P.; Kemmer, J.; Prechtel, U.; Ziemann, T.; Rehak, P.
1987-01-01
We have fabricated 280 μm thick fully depletable pn CCD's on high resistivity silicon (/rho/ ∼ 2.5 kΩcm). Its operation is based on the semiconductor drift chamber principle proposed by Gatti and Rheak. They are designed as energy and position sensitive radiation detector for (minimum) ionizing particles and X-ray imaging. Two dimensional semiconductor device modeling demonstrates the basic charge transer mechanisms. Prototypes of the detectors have been tested in static and dynamic conditions. A preliminary charge transfer inefficiency was determined to 6 x 10/sup/minus/3/. The charge loss during the transfer is discussed and as a consequence we have developed an improved design for a second fabrication iteration which is now being produced. 4 refs., 15 figs
A novel optical gating method for laser gated imaging
Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer
2013-06-01
For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.
Zhang, Xian-Jun; Yang, Yin-Tang; Duan, Bao-Xing; Chai, Chang-Chun; Song, Kun; Chen, Bin
2012-09-01
Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET).
International Nuclear Information System (INIS)
Zhang Xian-Jun; Yang Yin-Tang; Duan Bao-Xing; Chai Chang-Chun; Song Kun; Chen Bin
2012-01-01
Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET)
Monitoring radiation damage in the LHCb Silicon Tracker
Graverini, Elena
2018-01-01
The purpose of LHCb is to search for indirect evidence of new physics in decays of heavy hadrons. The LHCb detector is a single-arm forward spectrometer with precise silicon-strip detectors in the regions with highest particle occupancies. The non-uniform exposure of the LHCb sensors makes it an ideal laboratory to study radiation damage effects in silicon detectors. The LHCb Silicon Tracker is composed of an upstream tracker, the TT, and of the inner part of the downstream tracker (IT). Dedicated scans are regularly taken, which allow a precise measurement of the charge collection efficiency (CCE) and the calibration of the operational voltages. The measured evolution of the effective depletion voltage $V_{depl}$ is shown, and compared with the Hamburg model prediction. The magnitudes of the sensor leakage current are also analysed and compared to their expected evolution according to phenomenological models. Our results prove that both the TT and the IT will withstand normal operation until the end of the L...
Depleted Monolithic Pixels (DMAPS) in a 150 nm technology: lab and beam results
International Nuclear Information System (INIS)
Obermann, T.; Hemperek, T.; Hügging, F.; Krüger, H.; Pohl, D.-L.; Wermes, N.; Schwenker, B.
2017-01-01
The fully depleted monolithic active pixel sensor (DMAPS) is a new concept integrating full CMOS circuitry onto a fully depletable silicon substrate wafer. The realization of prototypes of the DMAPS concept relies on the availability of multiple well CMOS processes and high resistive substrates. The CMOS foundry ESPROS Photonics offers both and was chosen for prototyping. Two prototypes, EPCB01 and EPCB02, were developed in a 150 nm process on a high resistive n-type wafer of 50 μm thickness. The prototypes have 352 square pixels of 40 μm pitch and small n-well charge collection node with very low capacitance (n + -implantation size: 5 μm by 5 μm) and about 150 transistors per pixel (CSA and discriminator plus a small digital part).
Mechanics of silicon nitride thin-film stressors on a transistor-like geometry
Directory of Open Access Journals (Sweden)
S. Reboh
2013-10-01
Full Text Available To understand the behavior of silicon nitride capping etch stopping layer stressors in nanoscale microelectronics devices, a simplified structure mimicking typical transistor geometries was studied. Elastic strains in the silicon substrate were mapped using dark-field electron holography. The results were interpreted with the aid of finite element method modeling. We show, in a counterintuitive sense, that the stresses developed by the film in the vertical sections around the transistor gate can reach much higher values than the full sheet reference. This is an important insight for advanced technology nodes where the vertical contribution of such liners is predominant over the horizontal part.
International Nuclear Information System (INIS)
Karimov, A.V.; Yodgorova, D.M.; Kamanov, B.M.; Giyasova, F.A.; Yakudov, A.A.
2012-01-01
The silicon field-effect transistors were investigated to use in circuits for stabilization of current and voltage. As in gallium arsenide field-effect transistors, in silicon field-effect transistors with p-n-junction a new mechanism of saturation of the drain current is experimentally found out due to both transverse and longitudinal compression of channel by additional resistance between the source and the gate of the transistor. The criteria for evaluating the coefficients of stabilization of transient current suppressors and voltage stabilizator based on the field-effect transistor are considered. (authors)
Dynamic gating window for compensation of baseline shift in respiratory-gated radiation therapy
International Nuclear Information System (INIS)
Pepin, Eric W.; Wu Huanmei; Shirato, Hiroki
2011-01-01
Purpose: To analyze and evaluate the necessity and use of dynamic gating techniques for compensation of baseline shift during respiratory-gated radiation therapy of lung tumors. Methods: Motion tracking data from 30 lung tumors over 592 treatment fractions were analyzed for baseline shift. The finite state model (FSM) was used to identify the end-of-exhale (EOE) breathing phase throughout each treatment fraction. Using duty cycle as an evaluation metric, several methods of end-of-exhale dynamic gating were compared: An a posteriori ideal gating window, a predictive trend-line-based gating window, and a predictive weighted point-based gating window. These methods were evaluated for each of several gating window types: Superior/inferior (SI) gating, anterior/posterior beam, lateral beam, and 3D gating. Results: In the absence of dynamic gating techniques, SI gating gave a 39.6% duty cycle. The ideal SI gating window yielded a 41.5% duty cycle. The weight-based method of dynamic SI gating yielded a duty cycle of 36.2%. The trend-line-based method yielded a duty cycle of 34.0%. Conclusions: Dynamic gating was not broadly beneficial due to a breakdown of the FSM's ability to identify the EOE phase. When the EOE phase was well defined, dynamic gating showed an improvement over static-window gating.
Radiation hardness of silicon detectors manufactured on wafers from various sources
International Nuclear Information System (INIS)
Dezillie, B.; Bates, S.; Glaser, M.; Lemeilleur, F.; Leroy, C.
1997-01-01
Impurity concentrations in the initial silicon material are expected to play an important role for the radiation hardness of silicon detectors, during their irradiation and for their evolution with time after irradiation. This work reports on the experimental results obtained with detectors manufactured using various float-zone (FZ) and epitaxial-grown material. Preliminary results comparing the changes in leakage current and full depletion voltage of FZ and epitaxial detectors as a function of fluence and of time after 10 14 cm -2 proton irradiation are given. The measurement of charge collection efficiency for epitaxial detectors is also presented. (orig.)
Caraveo-Frescas, J. A.
2012-03-09
It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.
THz generation from a nanocrystalline silicon-based photoconductive device
International Nuclear Information System (INIS)
Daghestani, N S; Persheyev, S; Cataluna, M A; Rose, M J; Ross, G
2011-01-01
Terahertz generation has been achieved from a photoconductive switch based on hydrogenated nanocrystalline silicon (nc-Si:H), gated by a femtosecond laser. The nc-Si:H samples were produced by a hot wire chemical vapour deposition process, a process with low production costs owing to its higher growth rate and manufacturing simplicity. Although promising ultrafast carrier dynamics of nc-Si have been previously demonstrated, this is the first report on THz generation from a nc-Si:H material
A monolithically integrated detector-preamplifier on high-resistivity silicon
International Nuclear Information System (INIS)
Holland, S.; Spieler, H.
1990-02-01
A monolithically integrated detector-preamplifier on high-resistivity silicon has been designed, fabricated and characterized. The detector is a fully depleted p-i-n diode and the preamplifier is implemented in a depletion-mode PMOS process which is compatible with detector processing. The amplifier is internally compensated and the measured gain-bandwidth product is 30 MHz with an input-referred noise of 15 nV/√Hz in the white noise regime. Measurements with an Am 241 radiation source yield an equivalent input noise charge of 800 electrons at 200 ns shaping time for a 1.4 mm 2 detector with on-chip amplifier in an experimental setup with substantial external pickup
Electrostatically Gated Graphene-Zinc Oxide Nanowire Heterojunction.
You, Xueqiu; Pak, James Jungho
2015-03-01
This paper presents an electrostatically gated graphene-ZnO nanowire (NW) heterojunction for the purpose of device applications for the first time. A sub-nanometer-thick energy barrier width was formed between a monatomic graphene layer and electrochemically grown ZnO NWs. Because of the narrow energy barrier, electrons can tunnel through the barrier when a voltage is applied across the junction. A near-ohmic current-voltage (I-V) curve was obtained from the graphene-electrochemically grown ZnO NW heterojunction. This near-ohmic contact changed to asymmetric I-V Schottky contact when the samples were exposed to an oxygen environment. It is believed that the adsorbed oxygen atoms or molecules on the ZnO NW surface capture free electrons of the ZnO NWs, thereby creating a depletion region in the ZnO NWs. Consequentially, the electron concentration in the ZnO NWs is dramatically reduced, and the energy barrier width of the graphene-ZnO NW heterojunction increases greatly. This increased energy barrier width reduces the electron tunneling probability, resulting in a typical Schottky contact. By adjusting the back-gate voltage to control the graphene-ZnO NW Schottky energy barrier height, a large modulation on the junction current (on/off ratio of 10(3)) was achieved.
A radiation detector fabricated from silicon photodiode.
Yamamoto, H; Hatakeyama, S; Norimura, T; Tsuchiya, T
1984-12-01
A silicon photodiode is converted to a low energy charged particle radiation detector. The window thickness of the fabricated detector is evaluated to be 50 micrograms/cm2. The area of the depletion region is 13.2 mm2 and the depth of it is estimated to be about 100 microns. The energy resolution (FWHM) is 14.5 ke V for alpha-particles from 241Am and 2.5 ke V for conversion electrons from 109Cd, respectively.
Sasaki, Kohei; Thieu, Quang Tu; Wakimoto, Daiki; Koishikawa, Yuki; Kuramata, Akito; Yamakoshi, Shigenobu
2017-12-01
We developed depletion-mode vertical Ga2O3 trench metal-oxide-semiconductor field-effect transistors by using n+ contact and n- drift layers. These epilayers were grown on an n+ (001) Ga2O3 single-crystal substrate by halide vapor phase epitaxy. Cu and HfO2 were used for the gate metal and dielectric film, respectively. The mesa width and gate length were approximately 2 and 1 µm, respectively. The devices showed good DC characteristics, with a specific on-resistance of 3.7 mΩ cm2 and clear current modulation. An on-off ratio of approximately 103 was obtained.
Martínez, C; Lozano, M; Campabadal, F; Santander, J; Fonseca, L; Ullán, M; Moreno, A
2002-01-01
This work presents the latest results on electrical properties degradation of silicon radiation detectors manufactured at IMB-CNM (Institut de Microelectronica de Barcelona) subjected to proton irradiation at CERN for high energy physics applications. The evolution of full depletion voltage and leakage current with fluence, as well as their annealing behaviour with time, were studied. The results obtained extend the previous understanding of the role played by technology and oxygenated material in hardening silicon radiation detectors. (15 refs).
ATLAS irradiation studies of n-in-n and p-in-n silicon microstrip detectors
Allport, P P; Buttar, C M; Carter, J; Drage, L M; Ferrère, D; Morgan, D; Riedler, P; Robinson, D
1999-01-01
Prior to the module production of the ATLAS silicon microstrip tracker for the barrel and the forward wheels, the characterisation of full-size prototype silicon detectors after radiation to fluences corresponding to 10 years of ATLAS operation is required. The behaviour of p-in-n and n-in-n detectors produced by several manufacturers before and after irradiation to a fluence of 3*10/sup 14/ protons/cm/sup 2/ at the CERN PS facility is discussed. This article summarises some recent results from the ATLAS SCT collaboration. The measurements of leakage current, full depletion voltage, signal-to-noise ratio and charge collection efficiency are presented. Despite the better efficiency performance of n-in-n detectors below depletion, the collaboration chose the p-in-n technology due to its simpler and less costly production since good charge collection efficiencies were achieved at the desired maximum bias voltage. (14 refs).
International Nuclear Information System (INIS)
Kranti, Abhinav; Hao Ying; Armstrong, G Alastair
2008-01-01
In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (I on /I off ). Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices
International Nuclear Information System (INIS)
Koo, Jae Bon; Lim, Jung Wook; Kim, Seong Hyun; Yun, Sun Jin; Ku, Chan Hoe; Lim, Sang Chul; Lee, Jung Hun
2007-01-01
The performances of pentacene thin-film transistor with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al 2 O 3 dielectric are reported. Saturation mobility of 0.38 cm 2 /V s, threshold voltage of 1 V, subthreshold swing of 0.6 V/decade, and on/off current ratio of about 10 8 have been obtained. Both depletion and enhancement mode inverter have been realized with the change of treatment method of hexamethyldisilazane on PEALD Al 2 O 3 gate dielectric. Full swing depletion mode inverter has been demonstrated at input voltages ranging from 5 V to - 5 V at supply voltage of - 5 V
Radiation damage status of the ATLAS silicon strip detectors (SCT)
Kondo, Takahiko; The ATLAS collaboration
2017-01-01
The Silicon microstrip detector system (SCT) of the ATLAS experiment at LHC has been working well for about 7 years since 2010. The innermost layer has already received a few times of 10**13 1-MeV neutron-equivalent fluences/cm2. The evolutions of the radiation damage effects on strip sensors such as leakage current and full depletion voltages will be presented.
International Nuclear Information System (INIS)
Hutagalung, S.D.; Lew, K.C.
2012-01-01
Atomic force microscopy (AFM) lithography was applied to produce nano scale pattern for silicon nano wire transistor fabrication. This technique takes advantage of imaging facility of AFM and the ability of probe movement controlling over the sample surface to create nano patterns. A conductive AFM tip was used to grow the silicon oxide nano patterns on silicon on insulator (SOI) wafer. The applied tip-sample voltage and writing speed were well controlled in order to form pre-designed silicon oxide nano wire transistor structures. The effect of tetra methyl ammonium hydroxide (TMAH) etching duration on the oxide covered silicon nano wire transistor structure has been investigated. A completed silicon nano wire transistor was obtained by removing the oxide layer via hydrofluoric acid etching process. The fabricated silicon nano wire transistor consists of a silicon nano wire that acts as a channel with source and drain pads. A lateral gate pad with a nano wire head was fabricated very close to the channel in the formation of transistor structures. (author)
New insights into fully-depleted SOI transistor response during total-dose irradiation
International Nuclear Information System (INIS)
Schwank, J.R.; Shaneyfelt, M.R.; Dodd, P.E.; Burns, J.A.; Keast, C.L.; Wyatt, P.W.
1999-01-01
In this paper, we present irradiation results on 2-fully depleted processes (HYSOI6, RKSOI) that show SOI (silicon on insulator) device response can be more complicated than originally suggested by others. The major difference between the 2 process versions is that the RKSOI process incorporates special techniques to minimize pre-irradiation parasitic leakage current from trench sidewalls. Transistors were irradiated at room temperature using 10 keV X-ray source. Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. It appears that the worst-case bias for HYPOI6 process is the bias that causes the largest increase in sidewall leakage. The RKSOI process shows a different response during irradiation, the transition response appears to be dominated by charge trapping in the buried oxide. These results have implications for hardness assurance testing. (A.C.)
Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang
2018-04-01
Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.
Martínez, C; Lozano, M; Campabadal, F; Santander, J; Fonseca, L; Ullán, M; Moreno, A J D
2002-01-01
This work presents the latest results on electrical properties degradation of silicon radiation detectors manufactured at the Institut de Microelectronica de Barcelona (IMB-CNM) subjected to proton irradiation at CERN, Switzerland, for high-energy physics (HEP) applications. The evolution of full depletion voltage and leakage current with fluence as well as their annealing behavior with time were studied. The results obtained extend the previous understanding of the role played by technology and oxygenated material in hardening silicon radiation detectors. (15 refs).
High-speed all-optical logic inverter based on stimulated Raman scattering in silicon nanocrystal.
Sen, Mrinal; Das, Mukul K
2015-11-01
In this paper, we propose a new device architecture for an all-optical logic inverter (NOT gate), which is cascadable with a similar device. The inverter is based on stimulated Raman scattering in silicon nanocrystal waveguides, which are embedded in a silicon photonic crystal structure. The Raman response function of silicon nanocrystal is evaluated to explore the transfer characteristic of the inverter. A maximum product criterion for the noise margin is taken to analyze the cascadability of the inverter. The time domain response of the inverter, which explores successful inversion operation at 100 Gb/s, is analyzed. Propagation delay of the inverter is on the order of 5 ps, which is less than the delay in most of the electronic logic families as of today. Overall dimension of the device is around 755 μm ×15 μm, which ensures integration compatibility with the matured silicon industry.
International Nuclear Information System (INIS)
Ford, E.C.; Mageras, G.S.; Yorke, E.; Rosenzweig, K.E.; Wagman, R.; Ling, C.C.
2002-01-01
Purpose: To evaluate the effectiveness of a commercial system in reducing respiration-induced treatment uncertainty by gating the radiation delivery. Methods and Materials: The gating system considered here measures respiration from the position of a reflective marker on the patient's chest. Respiration-triggered planning CT scans were obtained for 8 patients (4 lung, 4 liver) at the intended phase of respiration (6 at end expiration and 2 at end inspiration). In addition, fluoroscopic movies were recorded simultaneously with the respiratory waveform. During the treatment sessions, gated localization films were used to measure the position of the diaphragm relative to the vertebral bodies, which was compared to the reference digitally reconstructed radiograph derived from the respiration-triggered planning CT. Variability was quantified by the standard deviation about the mean position. We also assessed the interfraction variability of soft tissue structures during gated treatment in 2 patients using an amorphous silicon electronic portal imaging device. Results: The gated localization films revealed an interfraction patient-averaged diaphragm variability of 2.8±1.0 mm (error bars indicate standard deviation in the patient population). The fluoroscopic data yielded a patient-averaged intrafraction diaphragm variability of 2.6±1.7 mm. With no gating, this intrafraction excursion became 6.9±2.1 mm. In gated localization films, the patient-averaged mean displacement of the diaphragm from the planning position was 0.0±3.9 mm. However, in 4 of the 8 patients, the mean (over localization films) displacement was >4 mm, indicating a systematic displacement in treatment position from the planned one. The position of soft tissue features observed in portal images during gated treatments over several fractions showed a mean variability between 2.6 and 5.7 mm. The intrafraction variability, however, was between 0.6 and 1.4 mm, indicating that most of the variability was
Detailed characterisation of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures
Boudier, D.; Cretu, B.; Simoen, E.; Veloso, A.; Collaert, N.
2018-05-01
In this work, Gate-All-Around Nanowire MOSFETs have been studied at very low temperatures. DC behaviors have been investigated in the linear operation and saturation regions, giving access to several analog parameters. Static characteristics at 4.2 K and low polarization exhibit step- like variations of the drain current, which can be linked to energy subband scattering. First results on the impact of quantum transport mechanism on the low frequency noise are shown. Finally the low frequency noise spectroscopy has led to the identification of silicon film traps.
Directory of Open Access Journals (Sweden)
Erin K Purcell
Full Text Available The influence of membrane cholesterol content on a variety of ion channel conductances in numerous cell models has been shown, but studies exploring its role in auditory hair cell physiology are scarce. Recent evidence shows that cholesterol depletion affects outer hair cell electromotility and the voltage-gated potassium currents underlying tall hair cell development, but the effects of cholesterol on the major ionic currents governing auditory hair cell excitability are unknown. We investigated the effects of a cholesterol-depleting agent (methyl beta cyclodextrin, MβCD on ion channels necessary for the early stages of sound processing. Large-conductance BK-type potassium channels underlie temporal processing and open in a voltage- and calcium-dependent manner. Voltage-gated calcium channels (VGCCs are responsible for calcium-dependent exocytosis and synaptic transmission to the auditory nerve. Our results demonstrate that cholesterol depletion reduced peak steady-state calcium-sensitive (BK-type potassium current by 50% in chick cochlear hair cells. In contrast, MβCD treatment increased peak inward calcium current (~30%, ruling out loss of calcium channel expression or function as a cause of reduced calcium-sensitive outward current. Changes in maximal conductance indicated a direct impact of cholesterol on channel number or unitary conductance. Immunoblotting following sucrose-gradient ultracentrifugation revealed BK expression in cholesterol-enriched microdomains. Both direct impacts of cholesterol on channel biophysics, as well as channel localization in the membrane, may contribute to the influence of cholesterol on hair cell physiology. Our results reveal a new role for cholesterol in the regulation of auditory calcium and calcium-activated potassium channels and add to the growing evidence that cholesterol is a key determinant in auditory physiology.
Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate
Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Yang, Zhaonian
2017-03-01
In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.
Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate.
Li, Wei; Liu, Hongxia; Wang, Shulong; Chen, Shupeng; Yang, Zhaonian
2017-12-01
In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N + pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.
Study of the effects of neutron irradiation on silicon strip detectors
International Nuclear Information System (INIS)
Giubellino, P.; Panizza, G.; Hall, G.; Sotthibandhu, S.; Ziock, H.J.; Ferguson, P.; Sommer, W.F.; Edwards, M.; Cartiglia, N.; Hubbard, B.; Leslie, J.; Pitzl, D.; O'Shaughnessy, K.; Rowe, W.; Sadrozinski, H.F.W.; Seiden, A.; Spencer, E.
1992-01-01
Silicon strip detectors and test structures were exposed to neutron fluences up to Φ=6.1x10 14 n/cm 2 , using the ISIS neutron source at the Rutherford Appleton Laboratory (UK). In this paper we report some of our results concerning the effects of displacement damage, with a comparison of devices made of silicon of different resistivity. The various samples exposed showed a very similar dependence of the leakage current on the fluence received. We studied the change of effective doping concentration, and observed a behaviour suggesting the onset of type inversion at a fluence of ∝2.0x10 13 n/cm 2 , a value which depends on the initial doping concentration. The linear increase of the depletion voltage for fluences higher than the inversion point could eventually determine the maximum fluence tolerable by silicon detectors. (orig.)
Flexible high-κ/Metal gate metal/insulator/metal capacitors on silicon (100) fabric
Rojas, Jhonathan Prieto
2013-10-01
Implementation of memory on bendable substrates is an important step toward a complete and fully developed notion of mechanically flexible computational systems. In this paper, we have demonstrated a simple fabrication flow to build metal-insulator-metal capacitors, key components of dynamic random access memory, on a mechanically flexible silicon (100) fabric. We rely on standard microfabrication processes to release a thin sheet of bendable silicon (area: 18 {\\ m cm}2 and thickness: 25 \\\\mu{\\ m m}) in an inexpensive and reliable way. On such platform, we fabricated and characterized the devices showing mechanical robustness (minimum bending radius of 10 mm at an applied strain of 83.33% and nominal strain of 0.125%) and consistent electrical behavior regardless of the applied mechanical stress. Furthermore, and for the first time, we performed a reliability study suggesting no significant difference in performance and showing an improvement in lifetime projections. © 1963-2012 IEEE.
International Nuclear Information System (INIS)
Suwono.
1978-01-01
A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)
Out-of-plane strain effect on silicon-based flexible FinFETs
Ghoneim, Mohamed T.; Alfaraj, Nasir; Sevilla, Galo T.; Fahad, Hossain M.; Hussain, Muhammad Mustafa
2015-01-01
Summary form only given. We report out-of-plane strain effect on silicon based flexible FinFET, with sub 20 nm wide fins and hafnium silicate based high-κ gate dielectric. Since ultra-thin inorganic solid state substrates become flexible with reduced thickness, flexing induced strain does not enhance performance. However, detrimental effects arise as the devices are subject to various out-of-plane stresses (compressive and tensile) along the channel length.
Out-of-plane strain effect on silicon-based flexible FinFETs
Ghoneim, Mohamed T.
2015-06-21
Summary form only given. We report out-of-plane strain effect on silicon based flexible FinFET, with sub 20 nm wide fins and hafnium silicate based high-κ gate dielectric. Since ultra-thin inorganic solid state substrates become flexible with reduced thickness, flexing induced strain does not enhance performance. However, detrimental effects arise as the devices are subject to various out-of-plane stresses (compressive and tensile) along the channel length.
Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions
Directory of Open Access Journals (Sweden)
Keyvan Narimani
2018-04-01
Full Text Available In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET with gate-all-around (GAA structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm Optimized devices also show excellent current saturation, an important feature for analog performance.
Electric field strength and plasma delay in silicon surface barrier detector
International Nuclear Information System (INIS)
Kanno, I.; Inbe, T.; Kanazawa, S.; Kimura, I.
1994-01-01
The resistivity change of a silicon irradiated by high energy neutrons became an interest of study associated with the large scale accelerator projects . The increase of the resistivity of the silicon of a silicon surface barrier detector (SSBD) was studied as a function of neutron fluence. The plasma delay, which was an interesting but not favorite timing property of the SSBD, was reported being dependent on the resistivity of silicon . The neutron irradiation brings the change of timing property as well as the resistivity change on the SSBD. The resistivity dependence of the plasma delay should be studied for the purpose of high energy accelerator experiments. Some empirical formulae of the plasma delay were reported, however, there were no discussions on the physical meanings of the resistivity dependence of the plasma delay. The plasma delay in a SSBD is discussed in the light of electric field strength in the depletion layer of the SSBD. The explanation of the plasma delay is presented taking into account of the competing two electric forces. The resistivity of the silicon affects the plasma delay through the electric forces. 3 figs, 3 refs. (author)
Multipurpose silicon photonics signal processor core.
Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José
2017-09-21
Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.
Silicon-ion-implanted PMMA with nanostructured ultrathin layers for plastic electronics
Hadjichristov, G. B.; Ivanov, Tz E.; Marinov, Y. G.
2014-12-01
Being of interest for plastic electronics, ion-beam produced nanostructure, namely silicon ion (Si+) implanted polymethyl-methacrylate (PMMA) with ultrathin nanostructured dielectric (NSD) top layer and nanocomposite (NC) buried layer, is examined by electric measurements. In the proposed field-effect organic nanomaterial structure produced within the PMMA network by ion implantation with low energy (50 keV) Si+ at the fluence of 3.2 × 1016 cm-2 the gate NSD is ion-nanotracks-modified low-conductive surface layer, and the channel NC consists of carbon nanoclusters. In the studied ion-modified PMMA field-effect configuration, the gate NSD and the buried NC are formed as planar layers both with a thickness of about 80 nm. The NC channel of nano-clustered amorphous carbon (that is an organic semiconductor) provides a huge increase in the electrical conduction of the material in the subsurface region, but also modulates the electric field distribution in the drift region. The field effect via the gate NSD is analyzed. The most important performance parameters, such as the charge carrier field-effect mobility and amplification of this particular type of PMMA- based transconductance device with NC n-type channel and gate NSD top layer, are determined.
Sensibility analysis of fuel depletion using different nuclear fuel depletion codes
Energy Technology Data Exchange (ETDEWEB)
Martins, F.; Velasquez, C.E.; Castro, V.F.; Pereira, C.; Silva, C. A. Mello da, E-mail: felipmartins94@gmail.com, E-mail: carlosvelcab@hotmail.com, E-mail: victorfariascastro@gmail.com, E-mail: claubia@nuclear.ufmg.br, E-mail: clarysson@nuclear.ufmg.br [Universidade Federal de Minas Gerais (UFMG), Belo Horizonte, MG (Brazil). Departamento de Engenharia Nuclear
2017-07-01
Nowadays, the utilization of different nuclear codes to perform the depletion and criticality calculations has been used to simulated nuclear reactors problems. Therefore, the goal is to analyze the sensibility of the fuel depletion of a PWR assembly using three different nuclear fuel depletion codes. The burnup calculations are performed using the codes MCNP5/ORIGEN2.1 (MONTEBURNS), KENO-VI/ORIGEN-S (TRITONSCALE6.0) and MCNPX (MCNPX/CINDER90). Each nuclear code performs the burnup using different depletion codes. Each depletion code works with collapsed energies from a master library in 1, 3 and 63 groups, respectively. Besides, each code uses different ways to obtain neutron flux that influences the depletions calculation. The results present a comparison of the neutronic parameters and isotopes composition such as criticality and nuclides build-up, the deviation in results are going to be assigned to features of the depletion code in use, such as the different radioactive decay internal libraries and the numerical method involved in solving the coupled differential depletion equations. It is also seen that the longer the period is and the more time steps are chosen, the larger the deviation become. (author)
Sensibility analysis of fuel depletion using different nuclear fuel depletion codes
International Nuclear Information System (INIS)
Martins, F.; Velasquez, C.E.; Castro, V.F.; Pereira, C.; Silva, C. A. Mello da
2017-01-01
Nowadays, the utilization of different nuclear codes to perform the depletion and criticality calculations has been used to simulated nuclear reactors problems. Therefore, the goal is to analyze the sensibility of the fuel depletion of a PWR assembly using three different nuclear fuel depletion codes. The burnup calculations are performed using the codes MCNP5/ORIGEN2.1 (MONTEBURNS), KENO-VI/ORIGEN-S (TRITONSCALE6.0) and MCNPX (MCNPX/CINDER90). Each nuclear code performs the burnup using different depletion codes. Each depletion code works with collapsed energies from a master library in 1, 3 and 63 groups, respectively. Besides, each code uses different ways to obtain neutron flux that influences the depletions calculation. The results present a comparison of the neutronic parameters and isotopes composition such as criticality and nuclides build-up, the deviation in results are going to be assigned to features of the depletion code in use, such as the different radioactive decay internal libraries and the numerical method involved in solving the coupled differential depletion equations. It is also seen that the longer the period is and the more time steps are chosen, the larger the deviation become. (author)
GS Department
2009-01-01
Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department
ISAC's Gating-ML 2.0 data exchange standard for gating description.
Spidlen, Josef; Moore, Wayne; Brinkman, Ryan R
2015-07-01
The lack of software interoperability with respect to gating has traditionally been a bottleneck preventing the use of multiple analytical tools and reproducibility of flow cytometry data analysis by independent parties. To address this issue, ISAC developed Gating-ML, a computer file format to encode and interchange gates. Gating-ML 1.5 was adopted and published as an ISAC Candidate Recommendation in 2008. Feedback during the probationary period from implementors, including major commercial software companies, instrument vendors, and the wider community, has led to a streamlined Gating-ML 2.0. Gating-ML has been significantly simplified and therefore easier to support by software tools. To aid developers, free, open source reference implementations, compliance tests, and detailed examples are provided to stimulate further commercial adoption. ISAC has approved Gating-ML as a standard ready for deployment in the public domain and encourages its support within the community as it is at a mature stage of development having undergone extensive review and testing, under both theoretical and practical conditions. © 2015 International Society for Advancement of Cytometry.
International Nuclear Information System (INIS)
Vedam, S.; Archambault, L.; Starkschall, G.; Mohan, R.; Beddar, S.
2007-01-01
Four-dimensional (4D) computed tomography (CT) imaging has found increasing importance in the localization of tumor and surrounding normal structures throughout the respiratory cycle. Based on such tumor motion information, it is possible to identify the appropriate phase interval for respiratory gated treatment planning and delivery. Such a gating phase interval is determined retrospectively based on tumor motion from internal tumor displacement. However, respiratory-gated treatment is delivered prospectively based on motion determined predominantly from an external monitor. Therefore, the simulation gate threshold determined from the retrospective phase interval selected for gating at 4D CT simulation may not correspond to the delivery gate threshold that is determined from the prospective external monitor displacement at treatment delivery. The purpose of the present work is to establish a relationship between the thresholds for respiratory gating determined at CT simulation and treatment delivery, respectively. One hundred fifty external respiratory motion traces, from 90 patients, with and without audio-visual biofeedback, are analyzed. Two respiratory phase intervals, 40%-60% and 30%-70%, are chosen for respiratory gating from the 4D CT-derived tumor motion trajectory. From residual tumor displacements within each such gating phase interval, a simulation gate threshold is defined based on (a) the average and (b) the maximum respiratory displacement within the phase interval. The duty cycle for prospective gated delivery is estimated from the proportion of external monitor displacement data points within both the selected phase interval and the simulation gate threshold. The delivery gate threshold is then determined iteratively to match the above determined duty cycle. The magnitude of the difference between such gate thresholds determined at simulation and treatment delivery is quantified in each case. Phantom motion tests yielded coincidence of simulation
Silicon isotopes in angrites and volatile loss in planetesimals
Moynier, Frédéric; Savage, Paul S.; Badro, James; Barrat, Jean-Alix
2014-01-01
Inner solar system bodies, including the Earth, Moon, and asteroids, are depleted in volatile elements relative to chondrites. Hypotheses for this volatile element depletion include incomplete condensation from the solar nebula and volatile loss during energetic impacts. These processes are expected to each produce characteristic stable isotope signatures. However, processes of planetary differentiation may also modify the isotopic composition of geochemical reservoirs. Angrites are rare meteorites that crystallized only a few million years after calcium–aluminum-rich inclusions and exhibit extreme depletions in volatile elements relative to chondrites, making them ideal samples with which to study volatile element depletion in the early solar system. Here we present high-precision Si isotope data that show angrites are enriched in the heavy isotopes of Si relative to chondritic meteorites by 50–100 ppm/amu. Silicon is sufficiently volatile such that it may be isotopically fractionated during incomplete condensation or evaporative mass loss, but theoretical calculations and experimental results also predict isotope fractionation under specific conditions of metal–silicate differentiation. We show that the Si isotope composition of angrites cannot be explained by any plausible core formation scenario, but rather reflects isotope fractionation during impact-induced evaporation. Our results indicate planetesimals initially formed from volatile-rich material and were subsequently depleted in volatile elements during accretion. PMID:25404309
Analysis of reproducibility of respiration-triggered gated radiotherapy for lung tumors
International Nuclear Information System (INIS)
Spoelstra, Femke O.B.; Soernsen de Koste, John R. van; Cuijpers, Johan P.; Lagerwaard, Frank J.; Slotman, Ben J.; Senan, Suresh
2008-01-01
Purpose: Respiration-gated radiotherapy (RGRT) can decrease the toxicity of chemo-radiotherapy (CT-RT) by allowing use of smaller treatment fields. RGRT requires a predictable relationship between tumor position and external surrogate, which must be verified during treatment. Time-integrated electronic portal imaging (TI-EPI) identifies mean intra-fractional positions of moving structures, and was used to study reproducibility of anatomy during RGRT for lung tumors. Materials and methods: TI-EPIs were acquired using an amorphous silicon-based electronic portal imaging system (EPID, aS500) in continuous image acquisition mode in 11 patients treated with audio-coached RGRT at end-inspiration. The Varian Real-time Position Management (RPM) system was used for 4DCT imaging and RGRT delivery. All TI-EPI portals were co-registered to corresponding digitally reconstructed radiographs (DRR) of the planning 4DCT using the spinal column. Displacements in tumor position or that of an adjacent bronchus during RGRT was measured relative to the reference structure on the DRR. Results: Vertebra-matched portals revealed systematic (Σ) and random (σ) errors of 1.8 and 1.3 mm in medial-lateral direction and 1.7 and 1.7 mm in cranial-caudal direction, indicating a reproducible tumor/bronchus position during the RPM-triggered gates. Conclusions: RGRT delivery at end-inspiration can achieve reproducible internal anatomy in 'gated' fields delivered with audio-coaching
Wang, Kai; Ou, Hai; Chen, Jun
2015-06-01
Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The "smart" pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients.
International Nuclear Information System (INIS)
Wang, Kai; Ou, Hai; Chen, Jun
2015-01-01
Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The 'smart' pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients. (paper)
Directory of Open Access Journals (Sweden)
Paul C. McIntyre
2012-07-01
Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.
Salmon, Stefanie J; Adriaanse, Marieke A; De Vet, Emely; Fennis, Bob M; De Ridder, Denise T D
2014-01-01
Self-control relies on a limited resource that can get depleted, a phenomenon that has been labeled ego-depletion. We argue that individuals may differ in their sensitivity to depleting tasks, and that consequently some people deplete their self-control resource at a faster rate than others. In three studies, we assessed individual differences in depletion sensitivity, and demonstrate that depletion sensitivity moderates ego-depletion effects. The Depletion Sensitivity Scale (DSS) was employed to assess depletion sensitivity. Study 1 employs the DSS to demonstrate that individual differences in sensitivity to ego-depletion exist. Study 2 shows moderate correlations of depletion sensitivity with related self-control concepts, indicating that these scales measure conceptually distinct constructs. Study 3 demonstrates that depletion sensitivity moderates the ego-depletion effect. Specifically, participants who are sensitive to depletion performed worse on a second self-control task, indicating a stronger ego-depletion effect, compared to participants less sensitive to depletion.
When the Going Gets Tough, Who Keeps Going? Depletion Sensitivity Moderates the Ego-Depletion Effect
Directory of Open Access Journals (Sweden)
Stefanie J. Salmon
2014-06-01
Full Text Available Self-control relies on a limited resource that can get depleted, a phenomenon that has been labeled ego-depletion. We argue that individuals may differ in their sensitivity to depleting tasks, and that consequently some people deplete their self-control resource at a faster rate than others. In three studies, we assessed individual differences in depletion sensitivity, and demonstrate that depletion sensitivity moderates ego-depletion effects. The Depletion Sensitivity Scale (DSS was employed to assess depletion sensitivity. Study 1 employs the DSS to demonstrate that individual differences in sensitivity to ego-depletion exist. Study 2 shows moderate correlations of depletion sensitivity with related self-control concepts, indicating that these scales measure conceptually distinct constructs. Study 3 demonstrates that depletion sensitivity moderates the ego-depletion effect. Specifically, participants who are sensitive to depletion performed worse on a second self-control task, indicating a stronger ego-depletion effect, compared to participants less sensitive to depletion.
Developments in Silicon Detectors and their impact on LHCb Physics Measurements
Gouldwell-Bates, A
2005-01-01
The LHCb experiment is a high energy physics detector at the Large Hadron Collider (LHC) which will probe the current understanding of the Standard Model through precise measurements of CP violation and rare decays. The LHCb detector heavily depends on the silicon vertexing (VELO) sub-detector for excellent vertex and proper decay time resolutions. The VELO detector sits at a position of only 7 mm from the LHC proton beams. However, the proximity of the silicon sensors to the proton beams results in the detectors suffering radiation damage. Radiation damage results in three changes in the macroscopic properties of the silicon detector: an increase of the leakage current, a decrease in the charge collection efficiency, and changes in the operation voltage required to fully deplete the silicon detector of the free charge carriers. Due to this radiation damage, it is expected that a replacement or upgrade of the LHCb vertex detector will be required by 2010, only 3 years after the turn-on of the LHC. This thesis...
Modeling of Temperature-Dependent Noise in Silicon Nanowire FETs including Self-Heating Effects
Directory of Open Access Journals (Sweden)
P. Anandan
2014-01-01
Full Text Available Silicon nanowires are leading the CMOS era towards the downsizing limit and its nature will be effectively suppress the short channel effects. Accurate modeling of thermal noise in nanowires is crucial for RF applications of nano-CMOS emerging technologies. In this work, a perfect temperature-dependent model for silicon nanowires including the self-heating effects has been derived and its effects on device parameters have been observed. The power spectral density as a function of thermal resistance shows significant improvement as the channel length decreases. The effects of thermal noise including self-heating of the device are explored. Moreover, significant reduction in noise with respect to channel thermal resistance, gate length, and biasing is analyzed.
High-stability transparent amorphous oxide TFT with a silicon-doped back-channel layer
Energy Technology Data Exchange (ETDEWEB)
Lee, Hyoung-Rae; Park, Jea-Gun [Hanyang University, Seoul (Korea, Republic of)
2014-10-15
We significantly reduced various electrical instabilities of amorphous indium gallium zinc oxide thin-film transistors (TFTs) by using the co-deposition of silicon on an a-IGZO back channel. This process showed improved stability of the threshold voltage (V{sub th}) under high temperature and humidity and negative gate-bias illumination stress (NBIS) without any reduction of IDS. The enhanced stability was achieved with silicon, which has higher metal-oxide bonding strengths than gallium does. Additionally, SiO{sub x} distributed on the a-IGZO surface reduced the adsorption and the desorption of H{sub 2}O and O{sub 2}. This process is applicable to the TFT manufacturing process with a variable sputtering target.
High resolution medium energy ion scattering study of silicon oxidation and oxy nitridation
International Nuclear Information System (INIS)
Gusev, E.P.; Lu, H.C.; Garfunkel, E.; Gustafsson, T.
1998-01-01
Full text: Silicon oxide is likely to remain the material of choice for gate oxides in microelectronics for the foreseeable future. As device become ever smaller and faster, the thickness of these layers in commercial products is predicted to be less than 50 Angstroms in just a few years. An understanding of such devices will therefore likely to be based on microscopic concepts and should now be investigated by atomistic techniques. With medium energy ion scattering (MEIS) using an electrostatic energy analyzer, depth profiling of thin (<60 Angstroms) silicon oxide films on Si(100) with 3 - 5 Angstroms depth resolution in the near region has been done. The growth mechanism of thin oxide films on Si(100) has been studied, using sequential oxygen isotope exposures. It is found that the oxide films are stoichiometric to within approx. 10 Angstroms of the interface. It is also found that the oxidation reactions occur at the surface, in the transition region and at interface, with only the third region being included in the conventional (Deal-Grove) model for oxide formation. Nitrogen is sometimes added to gate oxides, as it has been found empirically that his improves some of the electrical properties. The role, location and even the amount of nitrogen that exists in such films are poorly understood, and represent interesting analytical challenges. MEIS data will be presented that address these questions, measured for a number of different processing conditions. We have recently demonstrated how to perform nitrogen nano-engineering in such ultrathin gate dielectrics, and these results will also be discussed
Temperature dependence of the work function of ruthenium-based gate electrodes
International Nuclear Information System (INIS)
Alshareef, H.N.; Wen, H.C.; Luan, H.F.; Choi, K.; Harris, H.R.; Senzaki, Y.; Majhi, P.; Lee, B.H.; Foran, B.; Lian, G.
2006-01-01
The effect of device fabrication temperature on the work function of ruthenium (Ru) metal gate and its bilayers was investigated. The work function shows strong temperature dependence when Ru electrodes are deposited on silicon oxide, SiO 2 , but not on hafnium silicates (HfSiO x ). Specifically, the work function of Ru on SiO 2 increased from 4.5 eV at 500 deg. C to 5.0 eV at 700 deg. C. On further annealing to 900 deg. C or higher, the work function dropped to about 4.4 eV. In the case of HfSiO x , the work function of Ru changed by less than 100 mV over the same temperature range. Identical temperature dependence was observed using hafnium (Hf)/Ru and tantalum (Ta)/Ru bilayers. However, the peak values of the work function decreased with increasing Hf/Ru and Ta/Ru thickness ratios. Materials analysis suggests that these trends are driven by interactions at the Ru metal gate-dielectric interface
The bipolar silicon microstrip detector: A proposal for a novel precision tracking device
International Nuclear Information System (INIS)
Horisberger, R.
1990-01-01
It is proposed to combine the technology of fully depleted microstrip detectors fabricated on n doped high resistivity silicon with the concept of the bipolar transistor. This is done by adding a n ++ doped region inside the normal p + implanted region of the reverse biased p + n diode. The resulting structure has amplifying properties and is referred to as bipaolar pixel transistor. The simplest readout scheme of a bipolar pixel array by an aluminium strip bus leads to the bipolar microstrip detector. The bipolar pixel structure is expected to give a better signal-to-noise performance for the detection of minimum ionizing charged particle tracks than the normal silicon diode strip detector and therefore should allow in future the fabrication of thinner silicon detectors for precision tracking. (orig.)
Study of the effects of neutron irradiation on silicon strip detectors
Energy Technology Data Exchange (ETDEWEB)
Giubellino, P.; Panizza, G. (INFN Torino (Italy)); Hall, G.; Sotthibandhu, S. (Imperial Coll., London (United Kingdom)); Ziock, H.J.; Ferguson, P.; Sommer, W.F. (Los Alamos National Lab., NM (United States)); Edwards, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Cartiglia, N.; Hubbard, B.; Leslie, J.; Pitzl, D.; O' Shaughnessy, K.; Rowe, W.; Sadrozinski, H.F.W.; Seiden, A.; Spencer, E. (Santa Cruz Inst. for Particle Physics, Univ. California, CA (United States))
1992-05-01
Silicon strip detectors and test structures were exposed to neutron fluences up to {Phi}=6.1x10{sup 14} n/cm{sup 2}, using the ISIS neutron source at the Rutherford Appleton Laboratory (UK). In this paper we report some of our results concerning the effects of displacement damage, with a comparison of devices made of silicon of different resistivity. The various samples exposed showed a very similar dependence of the leakage current on the fluence received. We studied the change of effective doping concentration, and observed a behaviour suggesting the onset of type inversion at a fluence of {proportional to}2.0x10{sup 13} n/cm{sup 2}, a value which depends on the initial doping concentration. The linear increase of the depletion voltage for fluences higher than the inversion point could eventually determine the maximum fluence tolerable by silicon detectors. (orig.).
A refractory metal gate approach for micronic CMOS technology
International Nuclear Information System (INIS)
Lubowiecki, V.; Ledys, J.L.; Plossu, C.; Balland, B.
1987-01-01
In the future, devices scaling down, integration density and performance improvements are going to bring a number of conventional circuit design and process techniques to their fundamental limits. To avoid any severe limitations in MOS ULSI (Ultra Large Scale Integration) technologies, interconnection materials and schemes are required to emerge, in order to face the Megabits memory field. Among those, the gate approach will obviously take a keyrole, when the operating speed of ULSI chips will reach the practical upper limits imposed by parasitic resistances and capacitances which stem from the circuit interconnect wiring. Even if fairly suitable for MOS process, doped polycrystalline silicon is being gradually replaced by refractory metal silicide or polycide structures, which match better with low resistivity requirements. However, as we approach the submicronic IC's, higher conductivity materials will be paid more and more attention. Recently, works have been devoted and published on refractory metal gate technologies. Molybdenum or tungsten, deposited either by CVD or PVD methods, are currently reported even if some drawbacks in their process integration still remain. This paper is willing to present such an approach based on tungsten (more reliable than Molybdenum deposited by LPCVD (giving more conductive and more stable films than PVD). Deposition process will be first described. Then CMOS process flow will allow us to focus on specific refractory metal gate issues. Finally, electrical and physical properties will be assessed, which will demonstrate the feasibility of such a technology as well as the compatibility of the tungsten with most of the usual techniques
International Nuclear Information System (INIS)
Li Cong; Zhuang Yi-Qi; Zhang Li; Jin Gang
2014-01-01
A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate (JLDMCSG) metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. It is derived by solving the two-dimensional Poisson's equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electrostatic potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD
Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties
International Nuclear Information System (INIS)
Gasparyan, F.; Khondkaryan, H.; Arakelyan, A.; Zadorozhnyi, I.; Pud, S.; Vitusevich, S.
2016-01-01
The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p"+-p-p"+ field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2–4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculating the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 10"5. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.
Quantum conductance staircase of holes in silicon nanosandwiches
Directory of Open Access Journals (Sweden)
Nikolay T. Bagraev
2017-03-01
Full Text Available The results of studying the quantum conductance staircase of holes in one-dimensional channels obtained by the split-gate method inside silicon nanosandwiches that are the ultra-narrow quantum well confined by the delta barriers heavily doped with boron on the n-type Si (100 surface are reported. Since the silicon quantum wells studied are ultra-narrow (~2 nm and confined by the delta barriers that consist of the negative-U dipole boron centers, the quantized conductance of one-dimensional channels is observed at relatively high temperatures (T>77 K. Further, the current-voltage characteristic of the quantum conductance staircase is studied in relation to the kinetic energy of holes and their sheet density in the quantum wells. The results show that the quantum conductance staircase of holes in p-Si quantum wires is caused by independent contributions of the one-dimensional (1D subbands of the heavy and light holes. In addition, the field-related inhibition of the quantum conductance staircase is demonstrated in the situation when the energy of the field-induced heating of the carriers become comparable to the energy gap between the 1D subbands. The use of the split-gate method made it possible to detect the effect of a drastic increase in the height of the quantum conductance steps when the kinetic energy of holes is increased; this effect is most profound for quantum wires of finite length, which are not described under conditions of a quantum point contact. In the concluding section of this paper we present the findings for the quantum conductance staircase of holes that is caused by the edge channels in the silicon nanosandwiches prepared within frameworks of the Hall geometry. This longitudinal quantum conductance staircase, Gxx, is revealed by the voltage applied to the Hall contacts, with the plateaus and steps that bring into correlation respectively with the odd and even fractional values.
International Nuclear Information System (INIS)
Kim, Minsoo; Kim, Younghyun; Yokoyama, Masafumi; Nakane, Ryosho; Kim, SangHyeon; Takenaka, Mitsuru; Takagi, Shinichi
2014-01-01
We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al 2 O 3 -based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower I ON /I OFF ratio of 10 3 –10 4 were obtained. It is expected that these device characteristics can be improved by further process optimization. - Highlights: • Layer by layer growth of Ge • Uniform interface between Ge and the insulator • Gate leakage current and drain current saturation seem to be well controlled. • The output characteristics show good saturation
DEFF Research Database (Denmark)
Dalal, Dipen Narendrabhai; Christensen, Nicklas; Jørgensen, Asger Bjørn
2017-01-01
Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification...
Gate current for p+-poly PMOS devices under gate injection conditions
Hof, A.J.; Holleman, J.; Woerlee, P.H.
2001-01-01
In current CMOS processing both n+-poly and p+-poly gates are used. The I-V –relationship and reliability of n+-poly devices are widely studied and well understood. Gate currents and reliability for p+-poly PMOS devices under gate injection conditions are not well understood. In this paper, the
Free-standing silicon micro machined resistors from (110) substrate
International Nuclear Information System (INIS)
Bernardini, R.; Diligenti, A.; Nannini, A.; Piotto, M.
1998-01-01
A simple process to obtain silicon planes released from the substrate and provided with large area pads for ohmic contacts is described. Resistors 500 μm long with a 40 μm x 1 μm cross section were obtained. Resistance measurements showed that the current flows in a reduced cross section, probably owing to the presence of a superficial depletion layer. Preliminary magnetoresistance measurements are presented. Reduction of the resistor cross section can be obtained by thermal oxidation
Multiple Independent Gate FETs: How Many Gates Do We Need?
Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni
2015-01-01
Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...
Energy Technology Data Exchange (ETDEWEB)
Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars [Solid State Physics, Nanometer Structure Consortium, Lund University, Box 118, S-221 00 Lund (Sweden)
2013-12-04
We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.
Hussain, Aftab M.
2013-08-16
We demonstrate a simple, low-cost, and scalable process for obtaining uniform, smooth surfaced, high quality mono-crystalline germanium (100) thin films on silicon (100). The germanium thin films were deposited on a silicon substrate using plasma-assisted sputtering based physical vapor deposition. They were crystallized by annealing at various temperatures ranging from 700 °C to 1100 °C. We report that the best quality germanium thin films are obtained above the melting point of germanium (937 °C), thus offering a method for in-situ Czochralski process. We show well-behaved high-κ /metal gate metal-oxide-semiconductor capacitors (MOSCAPs) using this film. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.
Bae, Jong-Ho; Lee, Jong-Ho
2016-05-01
A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.
Perkins, Charles M.; Triplett, Baylor B.; McIntyre, Paul C.; Saraswat, Krishna C.; Haukka, Suvi; Tuominen, Marko
2001-04-01
Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10-5 A/cm2 at a bias of -1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ˜3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.
Research on total-dose hardening for H-gate PD NMOSFET/SIMOX by ion implanting into buried oxide
International Nuclear Information System (INIS)
Qian Cong; Zhang Zhengxuan; Zhang Feng; Lin Chenglu
2008-01-01
In this work, we investigate the back-gate I-V characteristics for two kinds of NMOSFET/SIMOX transistors with H gate structure fabricated on two different SOI wafers. A transistors are made on the wafer implanted with Si + and then annealed in N 2 , and B transistors are made on the wafer without implantation and annealing. It is demonstrated experimentally that A transistors have much less back-gate threshold voltage shift ΔV th than B transistors under X-ray total close irradiation. Subthreshold charge separation technique is employed to estimate the build-up of oxide charge and interface traps during irradiation, showing that the reduced ΔV th for A transistors is mainly due to its less build-up of oxide charge than B transistors. Photo-luminescence (PL) research indicates that Si implantation results in the formation of silicon nanocrystalline (nanocluster) whose size increases with the implant dose. This structure can trap electrons to compensate the positive charge build-up in the buried oxide during irradiation, and thus reduce the threshold voltage negative shift. (authors)
Synthesis of silicon nanocomposite for printable photovoltaic devices on flexible substrate
Odo, E. A.; Faremi, A. A.
2017-06-01
Renewed interest has been established in the preparation of silicon nanoparticles for electronic device applications. In this work, we report on the production of silicon powders using a simple ball mill and of silicon nanocomposite ink for screen-printable photovoltaic device on a flexible substrate. Bulk single crystalline silicon was milled for 25 h in the ball mill. The structural properties of the produced silicon nanoparticles were investigated using X-ray diffraction (XRD) and transmission electron microscopy. The results show that the particles remained highly crystalline, though transformed from their original single crystalline state to polycrystalline. The elemental composition using energy dispersive X-ray florescence spectroscopy (EDXRF) revealed that contamination from iron (Fe) and chromium (Cr) of the milling media and oxygen from the atmosphere were insignificant. The size distribution of the nanoparticles follows a lognormal pattern that ranges from 60 nm to about 1.2 μm and a mean particle size of about 103 nm. Electrical characterization of screen-printed PN structures of the nanocomposite formed by embedding the powder into a suitable water-soluble polymer on Kapton sheet reveals an enhanced photocurrent transport resulting from photo-induced carrier generation in the depletion region with energy greater that the Schottky barrier height at the metal-composite interface.
Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator
Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro
2018-02-01
The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.
International Nuclear Information System (INIS)
Stefanescu, Ion; Steflea, Dumitru; Saros-Rogobete, Irina; Titescu, Gheorghe; Tamaian, Radu
2001-01-01
Deuterium-depleted water represents water that has an isotopic content smaller than 145 ppm D/(D+H) which is the natural isotopic content of water. Deuterium depleted water is produced by vacuum distillation in columns equipped with structured packing made from phosphor bronze or stainless steel. Deuterium-depleted water, the production technique and structured packing are patents of National Institute of Research - Development for Cryogenics and Isotopic Technologies at Rm. Valcea. Researches made in the last few years showed the deuterium-depleted water is a biological active product that could have many applications in medicine and agriculture. (authors)
A surface code quantum computer in silicon
Hill, Charles D.; Peretz, Eldad; Hile, Samuel J.; House, Matthew G.; Fuechsle, Martin; Rogge, Sven; Simmons, Michelle Y.; Hollenberg, Lloyd C. L.
2015-01-01
The exceptionally long quantum coherence times of phosphorus donor nuclear spin qubits in silicon, coupled with the proven scalability of silicon-based nano-electronics, make them attractive candidates for large-scale quantum computing. However, the high threshold of topological quantum error correction can only be captured in a two-dimensional array of qubits operating synchronously and in parallel—posing formidable fabrication and control challenges. We present an architecture that addresses these problems through a novel shared-control paradigm that is particularly suited to the natural uniformity of the phosphorus donor nuclear spin qubit states and electronic confinement. The architecture comprises a two-dimensional lattice of donor qubits sandwiched between two vertically separated control layers forming a mutually perpendicular crisscross gate array. Shared-control lines facilitate loading/unloading of single electrons to specific donors, thereby activating multiple qubits in parallel across the array on which the required operations for surface code quantum error correction are carried out by global spin control. The complexities of independent qubit control, wave function engineering, and ad hoc quantum interconnects are explicitly avoided. With many of the basic elements of fabrication and control based on demonstrated techniques and with simulated quantum operation below the surface code error threshold, the architecture represents a new pathway for large-scale quantum information processing in silicon and potentially in other qubit systems where uniformity can be exploited. PMID:26601310
A surface code quantum computer in silicon.
Hill, Charles D; Peretz, Eldad; Hile, Samuel J; House, Matthew G; Fuechsle, Martin; Rogge, Sven; Simmons, Michelle Y; Hollenberg, Lloyd C L
2015-10-01
The exceptionally long quantum coherence times of phosphorus donor nuclear spin qubits in silicon, coupled with the proven scalability of silicon-based nano-electronics, make them attractive candidates for large-scale quantum computing. However, the high threshold of topological quantum error correction can only be captured in a two-dimensional array of qubits operating synchronously and in parallel-posing formidable fabrication and control challenges. We present an architecture that addresses these problems through a novel shared-control paradigm that is particularly suited to the natural uniformity of the phosphorus donor nuclear spin qubit states and electronic confinement. The architecture comprises a two-dimensional lattice of donor qubits sandwiched between two vertically separated control layers forming a mutually perpendicular crisscross gate array. Shared-control lines facilitate loading/unloading of single electrons to specific donors, thereby activating multiple qubits in parallel across the array on which the required operations for surface code quantum error correction are carried out by global spin control. The complexities of independent qubit control, wave function engineering, and ad hoc quantum interconnects are explicitly avoided. With many of the basic elements of fabrication and control based on demonstrated techniques and with simulated quantum operation below the surface code error threshold, the architecture represents a new pathway for large-scale quantum information processing in silicon and potentially in other qubit systems where uniformity can be exploited.
Ireland, R. M.; Wu, Liang; Salehi, M.; Oh, S.; Armitage, N. P.; Katz, H. E.
2018-04-01
We demonstrate the ability to reduce the carrier concentration of thin films of the topological insulator (TI) Bi2 Se3 by utilizing a nonvolatile electrostatic gating via corona charging of electret polymers. Sufficient electric field can be imparted to a polymer-TI bilayer to result in significant electron density depletion, even without the continuous connection of a gate electrode or the chemical modification of the TI. We show that the Fermi level of Bi2 Se3 is shifted toward the Dirac point with this method. Using terahertz spectroscopy, we find that the surface chemical potential is lowered into the bulk band gap (approximately 50 meV above the Dirac point and 170 meV below the conduction-band minimum), and it is stabilized in the intrinsic regime while enhancing electron mobility. The mobility of surface state electrons is enhanced to a value as high as approximately 1600 cm2/V s at 5 K.
Characterization of X3 Silicon Detectors for the ELISSA Array at ELI-NP
Chesnevskaya, S.; Balabanski, D. L.; Choudhury, D.; Cognata, M. La; Constantin, P.; Filipescu, D. M.; Ghita, D. G.; Guardo, G. L.; Lattuada, D.; Matei, C.; Rotaru, A.; Spitaleri, C.; State, A.; Xu, Y.
2018-01-01
Position-sensitive silicon strip detectors represent one of the best solutions for the detection of charged particles as they provide good energy and position resolution over a large range of energies. A silicon array coupled with the gamma beams at the ELI-NP facility would allow measuring photodissociation reactions of interest for Big Bang Nucleosynthesis and on heavy nuclei intervening in the p-process. Forty X3 detectors for our ELISSA (ELI-NP Silicon Strip Detectors Array) project have been recently purchased and tested. We investigated several specifications, such as leakage currents, depletion voltage, and detector stability under vacuum. The energy and position resolution, and ballistic deficit were measured and analyzed. This paper presents the main results of our extensive testing. The measured energy resolution for the X3 detectors is better than results published for similar arrays (ANASEN or ORRUBA).
International Nuclear Information System (INIS)
Yurkov, S N; Mnatsakanov, T T; Levinshtein, M E; Cheng, L; Palmour, J W
2014-01-01
The specific features of the temperature and bias dependences of the switch-on gate current in SiC thyristors are examined analytically for two possible switching mechanisms. The so-called γ-mechanism, which is highly typical of the conventional Si thyristors, is characterized by very weak temperature and bias dependences. By contrast, the so-called α-mechanism, which is very characteristic of SiC thyristors, is highly sensitive to changes in temperature and bias. If the thyristor is switched on by the α-mechanism, the switch-on gate current density decreases very steeply with increasing temperature. As a result, the thyristor can lose its working capacity at elevated temperatures due to the instability against even very weak impacts. With decreasing the bias voltage U a , the gate switch-on current increases very steeply, which can make switching the thyristor on difficult. The unintentional shunting, which is apparently present in high-voltage SiC thyristors, causes the transition from the α- to the γ-mechanism at elevated temperatures and high biases. It can be supposed that introduction of a controllable technological shunting of the emitter–thin base junction allows stabilization of the temperature and bias parameters of SiC thyristors. The analytical results are confirmed by computer simulations performed in wide temperature and bias ranges for a 4H-SiC thyristor of the 18 kV class. (paper)
Mesoporous Silicon with Modified Surface for Plant Viruses and Their Protein Particle Sensing
Directory of Open Access Journals (Sweden)
Kae Dal Kwack
2008-10-01
Full Text Available Changes in electric parameters of a mesoporous silicon treated by a plasma chemical etching with fluorine and hydrogen ions, under the adsorption of NEPO (Nematodetransmitted Polyhedral plant viruses such as TORSV (Tomato Ringspot Virus, GFLV (Grapevine Fan Leaf Virus and protein macromolecule from TORSV particles are described. The current response to the applied voltage is measured for each virus particle to investigate the material parameters which are sensitive to the adsorbed particles. The peculiar behaviors of the response are modeled by the current-voltage relationship in a MOSFET. This model explains the behavior well and the double gate model of the MOSFET informs that the mesoporous silicon is a highly sensitive means of detecting the viruses in the size range less than 50 nm.
International Nuclear Information System (INIS)
Lin, Jyi-Tsong; Huang, Kuo-Dong; Hu, Shu-Fen
2008-01-01
In this paper, a polycrystalline silicon (polysilicon) thin-film transistor with a block oxide enclosing body, BTFT, is fabricated and investigated. By utilizing the block-oxide structure of thin-film transistors, the BTFT is shown to suppress the short channel effect. This proposed structure is formed by burying self-aligned oxide spacers along the sidewalls of the source and drain junctions, which reduces the P–N junction area, thereby reducing the junction capacitance and leakage current. Measurements demonstrate that the BTFT eliminates the punch-through effect even down to gate lengths of 1.5 µm, whereas the conventional TFT suffers serious short channel effects at this gate length
Madan, Jaya; Gupta, R. S.; Chaujar, Rishu
2015-09-01
In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.
Lamotrigine effects sensorimotor gating in WAG/Rij rats
Directory of Open Access Journals (Sweden)
Ipek Komsuoglu Celikyurt
2012-01-01
Full Text Available Introduction: Prepulse inhibition (PPI is a measurable form of sensorimotor gating. Disruption of PPI reflects the impairment in the neural filtering process of mental functions that are related to the transformation of an external stimuli to a response. Impairment of PPI is reported in neuropsychiatric illnesses such as schizophrenia, Huntington′s disease, Parkinson′s diseases, Tourette syndrome, obsessive compulsive disorder, and temporal lobe epilepsy with psychosis. Absence epilepsy is the most common type of primary generalized epilepsy. Lamotrigine is an antiepileptic drug that is preferred in absence epilepsy and acts by stabilizing the voltage-gated sodium channels. Aim: In this study, we have compared WAG-Rij rats (genetically absence epileptic rats with Wistar rats, in order to clarify if there is a deficient sensorimotor gating in absence epilepsy, and have examined the effects of lamotrigine (15, 30 mg/kg, i.p. on this phenomenon. Materials and Methods: Depletion in PPI percent value is accepted as a disruption in sensory-motor filtration function. The difference between the Wistar and WAG/Rij rats has been evaluated with the student t test and the effects of lamotrigine on the PPI percent have been evaluated by the analysis of variance (ANOVA post-hoc Dunnett′s test. Results: The PPI percent was low in the WAG/Rij rats compared to the controls (P<0.0001, t:9,612. Although the PPI percent value of the control rats was not influenced by lamotrigine, the PPI percent value of the WAG/Rij rats was raised by lamotrigine treatment (P<0.0001, F:861,24. Conclusions: As a result of our study, PPI was disrupted in the WAG/Rij rats and this disruption could be reversed by an antiepileptic lamotrigine.
Silicon carbide: A unique platform for metal-oxide-semiconductor physics
Energy Technology Data Exchange (ETDEWEB)
Liu, Gang [Institute for Advanced Materials, Devices and Nanotechnology, Rutgers University, Piscataway, New Jersey 08854 (United States); Tuttle, Blair R. [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Dhar, Sarit [Department of Physics, Auburn University, Auburn, Alabama 36849 (United States)
2015-06-15
A sustainable energy future requires power electronics that can enable significantly higher efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide (4H-SiC) is one of the most technologically advanced wide bandgap semiconductor that can outperform conventional silicon in terms of power handling, maximum operating temperature, and power conversion efficiency in power modules. While SiC Schottky diode is a mature technology, SiC power Metal Oxide Semiconductor Field Effect Transistors are relatively novel and there is large room for performance improvement. Specifically, major initiatives are under way to improve the inversion channel mobility and gate oxide stability in order to further reduce the on-resistance and enhance the gate reliability. Both problems relate to the defects near the SiO{sub 2}/SiC interface, which have been the focus of intensive studies for more than a decade. Here we review research on the SiC MOS physics and technology, including its brief history, the state-of-art, and the latest progress in this field. We focus on the two main scientific problems, namely, low channel mobility and bias temperature instability. The possible mechanisms behind these issues are discussed at the device physics level as well as the atomic scale, with the support of published physical analysis and theoretical studies results. Some of the most exciting recent progress in interface engineering for improving the channel mobility and fundamental understanding of channel transport is reviewed.
Zirconates heteroepitaxy on silicon
Fompeyrine, Jean; Seo, Jin Won; Seigwart, Heinz; Rossel, Christophe; Locquet, Jean-Pierre
2002-03-01
In the coming years, agressive scaling in CMOS technology will probably trigger the transition to more advanced materials, for example alternate gate dielectrics. Epitaxial thin films are attractive candidates, as long as the difficult chemical and structural issues can be solved, and superior properties can be obtained. Since very few binary oxides can match the electrical, physical and structural requirements which are needed, a combination of those binaries are used here to investigate other lattice matched oxides. We will report on the growth of crystalline zirconium oxide thin films stabilized with different cationic substitutions. All films have been grown in an oxide-MBE system by direct evaporation of the elements on silicon substrates and exposure to molecular or atomic oxygen. The conditions required to obtain epitaxial thin films will be discussed, and successful examples will be presented.
Chen, Qi; Yoo, Si-Youl; Chung, Yong-Ho; Lee, Ji-Young; Min, Junhong; Choi, Jeong-Woo
2016-10-01
Various bio-logic gates have been studied intensively to overcome the rigidity of single-function silicon-based logic devices arising from combinations of various gates. Here, a simple control tool using electrochemical signals from quantum dots (QDs) was constructed using DNA and organic materials for multiple logic functions. The electrochemical redox current generated from QDs was controlled by the DNA structure. DNA structure, in turn, was dependent on the components (organic materials) and the input signal (pH). Independent electrochemical signals from two different logic units containing QDs were merged into a single analog-type logic gate, which was controlled by two inputs. We applied this electrochemical biodevice to a simple logic system and achieved various logic functions from the controlled pH input sets. This could be further improved by choosing QDs, ionic conditions, or DNA sequences. This research provides a feasible method for fabricating an artificial intelligence system. Copyright © 2016 Elsevier B.V. All rights reserved.
International Nuclear Information System (INIS)
Sah, C.-T.; Jie Binbin
2009-01-01
This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.
Ego depletion in visual perception: Ego-depleted viewers experience less ambiguous figure reversal.
Wimmer, Marina C; Stirk, Steven; Hancock, Peter J B
2017-10-01
This study examined the effects of ego depletion on ambiguous figure perception. Adults (N = 315) received an ego depletion task and were subsequently tested on their inhibitory control abilities that were indexed by the Stroop task (Experiment 1) and their ability to perceive both interpretations of ambiguous figures that was indexed by reversal (Experiment 2). Ego depletion had a very small effect on reducing inhibitory control (Cohen's d = .15) (Experiment 1). Ego-depleted participants had a tendency to take longer to respond in Stroop trials. In Experiment 2, ego depletion had small to medium effects on the experience of reversal. Ego-depleted viewers tended to take longer to reverse ambiguous figures (duration to first reversal) when naïve of the ambiguity and experienced less reversal both when naïve and informed of the ambiguity. Together, findings suggest that ego depletion has small effects on inhibitory control and small to medium effects on bottom-up and top-down perceptual processes. The depletion of cognitive resources can reduce our visual perceptual experience.
International Nuclear Information System (INIS)
Dawood, Mohammad; Buether, Florian; Lang, Norbert; Schober, Otmar; Schaefers, Klaus P
2007-01-01
Respiratory gating is used for reducing the effects of breathing motion in a wide range of applications from radiotherapy treatment to diagnostical imaging. Different methods are feasible for respiratory gating. In this study seven gating methods were developed and tested on positron emission tomography (PET) listmode data. The results of seven patient studies were compared quantitatively with respect to motion and noise. (1) Equal and (2) variable time-based gating methods use only the time information of the breathing cycle to define respiratory gates. (3) Equal and (4) variable amplitude-based gating approaches utilize the amplitude of the respiratory signal. (5) Cycle-based amplitude gating is a combination of time and amplitude-based techniques. A baseline correction was applied to methods (3) and (4) resulting in two new approaches: Baseline corrected (6) equal and (7) variable amplitude-based gating. Listmode PET data from seven patients were acquired together with a respiratory signal. Images were reconstructed applying the seven gating methods. Two parameters were used to quantify the results: Motion was measured as the displacement of the heart due to respiration and noise was defined as the standard deviation of pixel intensities in a background region. The amplitude-based approaches (3) and (4) were superior to the time-based methods (1) and (2). The improvement in capturing the motion was more than 30% (up to 130%) in all subjects. The variable time (2) and amplitude (4) methods had a more uniform noise distribution among all respiratory gates compared to equal time (1) and amplitude (3) methods. Baseline correction did not improve the results. Out of seven different respiratory gating approaches, the variable amplitude method (4) captures the respiratory motion best while keeping a constant noise level among all respiratory phases
A gate drive circuit for gate-turn-off (GTO) devices in series stack
International Nuclear Information System (INIS)
Despe, O.
1999-01-01
A gate-turn-off (GTO) switch is under development at the Advanced Photon Source as a replacement for a thyratron switch in high power pulsed application. The high voltage in the application requires multiple GTOs connected in series. One component that is critical to the success of GTO operation is the gate drive circuit. The gate drive circuit has to provide fast high-current pulses to the GTO gate for fast turn-on and turn-off. It also has to be able to operate while floating at high voltage. This paper describes a gate drive circuit that meets these requirements
Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks
Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.
2013-06-01
In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.
Subthreshold currents in CMOS transistors made on oxygen-implanted silicon
International Nuclear Information System (INIS)
Foster, D.J.
1983-01-01
Kinks have been observed in subthreshold current plots of mesa-shaped n-channel transistors made on oxygen-implanted silicon substrates. The kinks represent additional current flow and are due to overlapping fields from the gate electrode causing early corner inversion and to a Qsub(ss) side-wall effect. Subthreshold currents in n-channel transistors are dominated by the two effects which, as a consequence, reduce threshold voltages especially in narrow n-channel transistors. The subthreshold characteristics of p-channel transistors were not affected in the same way. (author)
Quality assurance and irradiation studies on CMS silicon strip sensors
Furgeri, Alexander
The high luminosity at the Large Hadron Collider at the European Particle Physics Laboratory CERN in Geneva causes a harsh radiation environment for the detectors. The most inner layers of the tracker are irradiated to an equivalent fluence of 1.6e14 1MeV-neutrons per cmˆ2. The radiation causes damage in the silicon lattice of the sensors. This increases the leakage current and changes the full depletion voltage. Both of these parameters are after irradiation neither stable with time nor with temperatures above 0oC. This thesis presents the changes of the leakage currents, the full depletion voltages, and all strip parameters of the sensors after proton and neutron irradiation. After irradiation annealing studies have been carried out. All observed effects are used to simulate the evolution of full depletion voltage for different annealing times and annealing temperatures in order to keep the power consumption as low as possible. From the observed radiation damage and annealing effects the sensors of the tra...
International Nuclear Information System (INIS)
Wu, Woei-Cherng; Chao, Tien-Sheng; Yang, Tsung-Yu; Peng, Wu-Chin; Yang, Wen-Luh; Chen, Jian-Hao; Ma, Ming Wen; Lai, Chao-Sung; Lee, Chien-Hsing; Hsieh, Tsung-Min; Liou, Jhyy Cheng; Chen, Tzu Ping; Chen, Chien Hung; Lin, Chih Hung; Chen, Hwi Huang; Ko, Joe
2008-01-01
In this paper, highly reliable wrapped-select-gate (WSG) silicon–oxide–nitride–oxide–silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V TH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance
Salmon, Stefanie J.; Adriaanse, Marieke A.; De Vet, Emely; Fennis, Bob M.; De Ridder, Denise T. D.
2014-01-01
Self-control relies on a limited resource that can get depleted, a phenomenon that has been labeled ego-depletion. We argue that individuals may differ in their sensitivity to depleting tasks, and that consequently some people deplete their self-control resource at a faster rate than others. In three studies, we assessed individual differences in depletion sensitivity, and demonstrate that depletion sensitivity moderates ego-depletion effects. The Depletion Sensitivity Scale (DSS) was employed to assess depletion sensitivity. Study 1 employs the DSS to demonstrate that individual differences in sensitivity to ego-depletion exist. Study 2 shows moderate correlations of depletion sensitivity with related self-control concepts, indicating that these scales measure conceptually distinct constructs. Study 3 demonstrates that depletion sensitivity moderates the ego-depletion effect. Specifically, participants who are sensitive to depletion performed worse on a second self-control task, indicating a stronger ego-depletion effect, compared to participants less sensitive to depletion. PMID:25009523
Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; LI, LIANG; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I.; Alshareef, Husam N.; Zhang, Yafei; Zhang, Xixiang
2014-01-01
Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. This journal is © the Partner Organisations 2014.
International Nuclear Information System (INIS)
Lee, Jae-Hoon; Shin, Kwang-Sub; Park, Joong-Hyun; Han, Min-Koo
2006-01-01
An experimental scheme for validating the cause of the hysteresis phenomenon in hydrogenated amorphous-silicon-thin-film transistors (a-Si:H TFTs) is reported. A different gate starting voltage to the desired gate voltage has been considered to prove an effect of filling an acceptor-like or donor-like state in the interface. The integration time of the semiconductor parameter analyzer has also been controlled to investigate the effect between the de-trapping rate and hysteresis. The experimental results show that the previous data voltage in the (n-1)th frame affects the OLED current in the (n)th frame.
Technology of fabrication of silicon-lithium detector with superficial junction
International Nuclear Information System (INIS)
Cabal Rodriguez, A.E.; Diaz Garcia, A.; Noriega Scull, C.
1997-01-01
The Silicon nuclear radiation detectors transform the charge produced within the semiconductor crystal, product of the impinges of particles and X rays, in pulses of voltage at the output of the preamplifier. The planar Silicon-Lithium (Si(Li)) detector with superficial junction is basically a Pin structure diode. By mean of the diffusion and drift of Lithium in the Silicon a compensated or depletion region was created. There the incident radiation interacts with the Silicon, producing an electric signal proportional to the detector's energy deposited in the semiconductor. The technological process of fabrication this kind of detectors comprises several stages, some of them complex and of long duration. They also demand a systematic control. The technological process of Si(Li) detector's fabrication was carried out. The detector's fabrication electric characteristics were measured in some steps. An obtained device was mounted in the holder within a cryostat, in order to work to temperature of the liquid nitrogen. The energy resolution of the detector was measured and the value was 180 eV for the line of 5.9 KeV of an Fe-55 source. This value has allowed to work with the detector in energy disperse X-rays fluorescence. (author) [es
Sevilla, Galo T.; Almuslem, A. S.; Gumus, Abdurrahman; Hussain, Aftab M.; Hussain, Aftab M.; Cruz, Melvin; Hussain, Muhammad Mustafa
2016-01-01
shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using
Localization effects in the tunnel barriers of phosphorus-doped silicon quantum dots
Directory of Open Access Journals (Sweden)
T. Ferrus
2012-06-01
Full Text Available We have observed a negative differential conductance with singular gate and source-drain bias dependences in a phosphorus-doped silicon quantum dot. Its origin is discussed within the framework of weak localization. By measuring the current-voltage characteristics at different temperatures as well as simulating the tunneling rates dependences on energy, we demonstrate that the presence of shallow energy defects together with an enhancement of localization satisfactory explain our observations. Effects observed in magnetic fields are also discussed.
International Nuclear Information System (INIS)
Zhang Xiangao; Fang Zhonghui; Chen Kunji; Xu Jun; Huang Xinfan
2011-01-01
We present an approach to fabricate a silicon nanowire relying on the proximity effect in electron beam lithography with a low acceleration voltage system by designing the exposure patterns with a rhombus sandwiched between two symmetric wedges. The reproducibility is investigated by changing the number of rhombuses. A device with a silicon nanowire is constructed on a highly doped silicon-on-insulator wafer to measure the electronic transport characteristics. Significant nonlinear behavior of current-voltage curves is observed at up to 150 K. The dependence of current on the drain voltage and back-gate voltage shows Coulomb blockade oscillations at 5.4 K, revealing a Coulomb island naturally formed in the nanowire. The mechanism of formation of the Coulomb island is discussed.
International Nuclear Information System (INIS)
Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon
2009-01-01
Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.
International Nuclear Information System (INIS)
Kramberger, G.; Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M.
2010-01-01
A set of 44 pad detectors produced on p- and n-type MCz and Fz wafers was irradiated with 23 GeV protons, 200 MeV pions and reactor neutrons up to the equivalent fluences of Φ eq =3x10 15 cm -2 . The evolution of the full depletion voltage and the leakage current were monitored during short- and long-term annealing. At selected representative annealing steps, charge collection measurements were performed for all samples with LHC speed electronics. Measurements of full depletion voltage, leakage current and charge collection efficiency were compared for different irradiation particles and silicon materials.
Energy Technology Data Exchange (ETDEWEB)
Kramberger, G., E-mail: Gregor.Kramberger@ijs.s [Jozef Stefan Institute and Department of Physics, University of Ljubljana, SI-1000 Ljubljana (Slovenia); Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M. [Jozef Stefan Institute and Department of Physics, University of Ljubljana, SI-1000 Ljubljana (Slovenia)
2010-01-01
A set of 44 pad detectors produced on p- and n-type MCz and Fz wafers was irradiated with 23 GeV protons, 200 MeV pions and reactor neutrons up to the equivalent fluences of PHI{sub eq}=3x10{sup 15}cm{sup -2}. The evolution of the full depletion voltage and the leakage current were monitored during short- and long-term annealing. At selected representative annealing steps, charge collection measurements were performed for all samples with LHC speed electronics. Measurements of full depletion voltage, leakage current and charge collection efficiency were compared for different irradiation particles and silicon materials.
Energy Technology Data Exchange (ETDEWEB)
Ma, Yao [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Gao, Bo, E-mail: gaobo@scu.edu.cn [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Gong, Min [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Willis, Maureen [College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Yang, Zhimei [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); Guan, Mingyue [College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Li, Yun [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China)
2017-04-01
In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO{sub 2}/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO{sub 2} and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.
Energy Technology Data Exchange (ETDEWEB)
Kim, Minsoo, E-mail: minsoo@mosfet.t.u-tokyo.ac.jp; Kim, Younghyun; Yokoyama, Masafumi; Nakane, Ryosho; Kim, SangHyeon; Takenaka, Mitsuru; Takagi, Shinichi
2014-04-30
We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al{sub 2}O{sub 3}-based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower I{sub ON}/I{sub OFF} ratio of 10{sup 3}–10{sup 4} were obtained. It is expected that these device characteristics can be improved by further process optimization. - Highlights: • Layer by layer growth of Ge • Uniform interface between Ge and the insulator • Gate leakage current and drain current saturation seem to be well controlled. • The output characteristics show good saturation.
Prusinski, Ben; Chung, Richard
2011-01-01
Expert Oracle GoldenGate is a hands-on guide to creating and managing complex data replication environments using the latest in database replication technology from Oracle. GoldenGate is the future in replication technology from Oracle, and aims to be best-of-breed. GoldenGate supports homogeneous replication between Oracle databases. It supports heterogeneous replication involving other brands such as Microsoft SQL Server and IBM DB2 Universal Server. GoldenGate is high-speed, bidirectional, highly-parallelized, and makes only a light impact on the performance of databases involved in replica
International Nuclear Information System (INIS)
Gong Yibin; Dai Pengfei; Gao Anran; Li Tie; Zhou Ping; Wang Yuelin
2011-01-01
Nanoscale refinement on a (100) oriented silicon-on-insulator (SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide (TMAH, 25 wt%) anisotropic silicon etchant, with temperature kept at 50 °C to achieve precise etching of the (111) crystal plane. Specifically for a silicon nanowire (SiNW) with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral (2.3 nm/min) and vertical (1.7 nm/min) dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor (FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the (111) plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields. (semiconductor materials)
Performance of 3-D architecture silicon sensors after intense proton irradiation
Parker, S I
2001-01-01
Silicon detectors with a three-dimensional architecture, in which the n- and p-electrodes penetrate through the entire substrate, have been successfully fabricated. The electrodes can be separated from each other by distances that are less than the substrate thickness, allowing short collection paths, low depletion voltages, and large current signals from rapid charge collection. While no special hardening steps were taken in this initial fabrication run, these features of three dimensional architectures produce an intrinsic resistance to the effects of radiation damage. Some performance measurements are given for detectors that are fully depleted and working after exposures to proton beams with doses equivalent to that from slightly more than ten years at the B-layer radius (50 mm) in the planned Atlas detector at the Large Hadron Collider at CERN. (41 refs).
Czech Academy of Sciences Publication Activity Database
Jandová, V.; Pokorná, D.; Kupčík, Jaroslav; Bezdička, Petr; Křenek, T.; Netrvalová, M.; Cuřínová, P.; Pola, J.
2018-01-01
Roč. 44, č. 1 (2018), s. 503-516 ISSN 0922-6168 Institutional support: RVO:61388980 Keywords : Silicon monoxide * Titanium monoxide * High-temperature * Oxygen-transfer reactions * Titanium suboxides * Titanium silicide * Methylene blue depletion Subject RIV: CA - Inorganic Chemistry OBOR OECD: Inorganic and nuclear chemistry Impact factor: 1.369, year: 2016
Design and simulation of nanoscale double-gate TFET/tunnel CNTFET
Bala, Shashi; Khosla, Mamta
2018-04-01
A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.
Two-electron spin correlations in precision placed donors in silicon.
Broome, M A; Gorman, S K; House, M G; Hile, S J; Keizer, J G; Keith, D; Hill, C D; Watson, T F; Baker, W J; Hollenberg, L C L; Simmons, M Y
2018-03-07
Substitutional donor atoms in silicon are promising qubits for quantum computation with extremely long relaxation and dephasing times demonstrated. One of the critical challenges of scaling these systems is determining inter-donor distances to achieve controllable wavefunction overlap while at the same time performing high fidelity spin readout on each qubit. Here we achieve such a device by means of scanning tunnelling microscopy lithography. We measure anti-correlated spin states between two donor-based spin qubits in silicon separated by 16 ± 1 nm. By utilising an asymmetric system with two phosphorus donors at one qubit site and one on the other (2P-1P), we demonstrate that the exchange interaction can be turned on and off via electrical control of two in-plane phosphorus doped detuning gates. We determine the tunnel coupling between the 2P-1P system to be 200 MHz and provide a roadmap for the observation of two-electron coherent exchange oscillations.
Opening of K+ channels by capacitive stimulation from silicon chip
Ulbrich, M. H.; Fromherz, P.
2005-10-01
The development of stable neuroelectronic systems requires a stimulation of nerve cells from semiconductor devices without electrochemical effects at the electrolyte/solid interface and without damage of the cell membrane. The interaction must rely on a reversible opening of voltage-gated ion channels by capacitive coupling. In a proof-of-principle experiment, we demonstrate that Kv1.3 potassium channels expressed in HEK293 cells can be opened from an electrolyte/oxide/silicon (EOS) capacitor. A sufficient strength of electrical coupling is achieved by insulating silicon with a thin film of TiO2 to achieve a high capacitance and by removing NaCl from the electrolyte to enhance the resistance of the cell-chip contact. When a decaying voltage ramp is applied to the EOS capacitor, an outward current through the attached cell membrane is observed that is specific for Kv1.3 channels. An open probability up to fifty percent is estimated by comparison with a numerical simulation of the cell-chip contact.
International Nuclear Information System (INIS)
Heo, Jinhee; Kim, Deoksu; Kim, Chung woo; Chung, Ilsub
2005-01-01
Continuous shrinkage in the memory devices demands further understanding about the doping concentration variations at shallow junction and channel region. Scanning capacitance microscopy (SCM) and scanning spread resistance microscopy (SSRM) can provide reliable information about the electrical and physical junction structure simultaneously. In this work, we attempt to visualize the doping concentration variations of split-gate structure silicon-oxide-nitride-oxide-silicon (SONOS) transistor with thin oxide-nitride-oxide (ONO; 4/7/11 nm). From SCM image, we could identify the source and drain region, which have different doping concentrations from that at channel region. In addition, a gate oxide layer and a depletion region were also identified. Similar results were obtained using SSRM. However, SSRM shows a better resolution, in particular, for highly doped region. For this experiment, the cross-sectional sample has been prepared using focused ion beam (FIB) and hand-polishing method. The results show that SCM and SSRM are very useful methods to analyze the doping profile near the junction as well as the channel
Evaluation of a silicon 5 MHz p–n diode actuator with a laterally vibrating extensional mode
Miyazaki, Fumito; Baba, Kazuki; Tanigawa, Hiroshi; Furutsuka, Takashi; Suzuki, Kenichiro
2018-05-01
In this paper, we describe p–n diode actuators that are laterally driven by the force induced in a depletion layer. The previously reported p–n diode actuators have been vertically driven. Because the resonant frequency depends on the thickness of the vibrating plate, the integration of resonators with different frequencies on a chip has been difficult. The resonators in this work are driven laterally by using length-extensional vibration. We have developed a compact model based on an analytical expression, in which p–n diode actuators are driven by the forces induced by the spread of the depletion layer. The deflection generated by the p–n diode actuators was proportional to the ratio of the depletion layer width to the resonator thickness as well as the position of the p–n junction. Good agreement of experimental results with the theory was confirmed by comparing the measured values for silicon p–n diode rectangular-plate actuators fabricated using a silicon-on-insulator (SOI) substrate. The displacement amplitude of the actuators was proportional to the DC bias, while the resonant frequency was independent of the DC bias. The latter characteristic is very different from that of widely used electrostatic actuators. Although the amplitude of the actuator measured in this work was very small, it is expected that the amplitude will increase greatly by increasing the doping of the p–n diode actuators.
International Nuclear Information System (INIS)
Bindal, Ahmet; Hamedi-Hagh, Sotoudeh
2006-01-01
This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits
All-electric control of donor nuclear spin qubits in silicon
Sigillito, Anthony J.; Tyryshkin, Alexei M.; Schenkel, Thomas; Houck, Andrew A.; Lyon, Stephen A.
2017-10-01
The electronic and nuclear spin degrees of freedom of donor impurities in silicon form ultra-coherent two-level systems that are potentially useful for applications in quantum information and are intrinsically compatible with industrial semiconductor processing. However, because of their smaller gyromagnetic ratios, nuclear spins are more difficult to manipulate than electron spins and are often considered too slow for quantum information processing. Moreover, although alternating current magnetic fields are the most natural choice to drive spin transitions and implement quantum gates, they are difficult to confine spatially to the level of a single donor, thus requiring alternative approaches. In recent years, schemes for all-electrical control of donor spin qubits have been proposed but no experimental demonstrations have been reported yet. Here, we demonstrate a scalable all-electric method for controlling neutral 31P and 75As donor nuclear spins in silicon. Using coplanar photonic bandgap resonators, we drive Rabi oscillations on nuclear spins exclusively using electric fields by employing the donor-bound electron as a quantum transducer, much in the spirit of recent works with single-molecule magnets. The electric field confinement leads to major advantages such as low power requirements, higher qubit densities and faster gate times. Additionally, this approach makes it possible to drive nuclear spin qubits either at their resonance frequency or at its first subharmonic, thus reducing device bandwidth requirements. Double quantum transitions can be driven as well, providing easy access to the full computational manifold of our system and making it convenient to implement nuclear spin-based qudits using 75As donors.
International Nuclear Information System (INIS)
Pinsonneault, M. H.; Walker, T. P.; Steigman, G.; Narayanan, Vijay K.
1999-01-01
The depletion of lithium during the pre-main-sequence and main-sequence phases of stellar evolution plays a crucial role in the comparison of the predictions of big bang nucleosynthesis with the abundances observed in halo stars. Previous work has indicated a wide range of possible depletion factors, ranging from minimal in standard (nonrotating) stellar models to as much as an order of magnitude in models that include rotational mixing. Recent progress in the study of the angular momentum evolution of low-mass stars permits the construction of theoretical models capable of reproducing the angular momentum evolution of low-mass open cluster stars. The distribution of initial angular momenta can be inferred from stellar rotation data in young open clusters. In this paper we report on the application of these models to the study of lithium depletion in main-sequence halo stars. A range of initial angular momenta produces a range of lithium depletion factors on the main sequence. Using the distribution of initial conditions inferred from young open clusters leads to a well-defined halo lithium plateau with modest scatter and a small population of outliers. The mass-dependent angular momentum loss law inferred from open cluster studies produces a nearly flat plateau, unlike previous models that exhibited a downward curvature for hotter temperatures in the 7Li-Teff plane. The overall depletion factor for the plateau stars is sensitive primarily to the solar initial angular momentum used in the calibration for the mixing diffusion coefficients. Uncertainties remain in the treatment of the internal angular momentum transport in the models, and the potential impact of these uncertainties on our results is discussed. The 6Li/7Li depletion ratio is also examined. We find that the dispersion in the plateau and the 6Li/7Li depletion ratio scale with the absolute 7Li depletion in the plateau, and we use observational data to set bounds on the 7Li depletion in main-sequence halo
Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.
Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György
2007-03-01
A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.
On the timing performance of thin planar silicon sensors
Akchurin, N.; Ciriolo, V.; Currás, E.; Damgov, J.; Fernández, M.; Gallrapp, C.; Gray, L.; Junkes, A.; Mannelli, M.; Martin Kwok, K. H.; Meridiani, P.; Moll, M.; Nourbakhsh, S.; Pigazzini, S.; Scharf, C.; Silva, P.; Steinbrueck, G.; de Fatis, T. Tabarelli; Vila, I.
2017-07-01
We report on the signal timing capabilities of thin silicon sensors when traversed by multiple simultaneous minimum ionizing particles (MIP). Three different planar sensors, with depletion thicknesses 133, 211, and 285 μm, have been exposed to high energy muons and electrons at CERN. We describe signal shape and timing resolution measurements as well as the response of these devices as a function of the multiplicity of MIPs. We compare these measurements to simulations where possible. We achieve better than 20 ps timing resolution for signals larger than a few tens of MIPs.
Visualizing a silicon quantum computer
International Nuclear Information System (INIS)
Sanders, Barry C; Hollenberg, Lloyd C L; Edmundson, Darran; Edmundson, Andrew
2008-01-01
Quantum computation is a fast-growing, multi-disciplinary research field. The purpose of a quantum computer is to execute quantum algorithms that efficiently solve computational problems intractable within the existing paradigm of 'classical' computing built on bits and Boolean gates. While collaboration between computer scientists, physicists, chemists, engineers, mathematicians and others is essential to the project's success, traditional disciplinary boundaries can hinder progress and make communicating the aims of quantum computing and future technologies difficult. We have developed a four minute animation as a tool for representing, understanding and communicating a silicon-based solid-state quantum computer to a variety of audiences, either as a stand-alone animation to be used by expert presenters or embedded into a longer movie as short animated sequences. The paper includes a generally applicable recipe for successful scientific animation production.
Visualizing a silicon quantum computer
Sanders, Barry C.; Hollenberg, Lloyd C. L.; Edmundson, Darran; Edmundson, Andrew
2008-12-01
Quantum computation is a fast-growing, multi-disciplinary research field. The purpose of a quantum computer is to execute quantum algorithms that efficiently solve computational problems intractable within the existing paradigm of 'classical' computing built on bits and Boolean gates. While collaboration between computer scientists, physicists, chemists, engineers, mathematicians and others is essential to the project's success, traditional disciplinary boundaries can hinder progress and make communicating the aims of quantum computing and future technologies difficult. We have developed a four minute animation as a tool for representing, understanding and communicating a silicon-based solid-state quantum computer to a variety of audiences, either as a stand-alone animation to be used by expert presenters or embedded into a longer movie as short animated sequences. The paper includes a generally applicable recipe for successful scientific animation production.
Visualizing a silicon quantum computer
Energy Technology Data Exchange (ETDEWEB)
Sanders, Barry C [Institute for Quantum Information Science, University of Calgary, Calgary, Alberta T2N 1N4 (Canada); Hollenberg, Lloyd C L [ARC Centre of Excellence for Quantum Computer Technology, School of Physics, University of Melbourne, Victoria 3010 (Australia); Edmundson, Darran; Edmundson, Andrew [EDM Studio Inc., Level 2, 850 16 Avenue SW, Calgary, Alberta T2R 0S9 (Canada)], E-mail: bsanders@qis.ucalgary.ca, E-mail: lloydch@unimelb.edu.au, E-mail: darran@edmstudio.com
2008-12-15
Quantum computation is a fast-growing, multi-disciplinary research field. The purpose of a quantum computer is to execute quantum algorithms that efficiently solve computational problems intractable within the existing paradigm of 'classical' computing built on bits and Boolean gates. While collaboration between computer scientists, physicists, chemists, engineers, mathematicians and others is essential to the project's success, traditional disciplinary boundaries can hinder progress and make communicating the aims of quantum computing and future technologies difficult. We have developed a four minute animation as a tool for representing, understanding and communicating a silicon-based solid-state quantum computer to a variety of audiences, either as a stand-alone animation to be used by expert presenters or embedded into a longer movie as short animated sequences. The paper includes a generally applicable recipe for successful scientific animation production.
Energy Technology Data Exchange (ETDEWEB)
Jan, S; Becheva, E [DSV/I2BM/SHFJ, Commissariat a l' Energie Atomique, Orsay (France); Benoit, D; Rehfeld, N; Stute, S; Buvat, I [IMNC-UMR 8165 CNRS-Paris 7 and Paris 11 Universities, 15 rue Georges Clemenceau, 91406 Orsay Cedex (France); Carlier, T [INSERM U892-Cancer Research Center, University of Nantes, Nantes (France); Cassol, F; Morel, C [Centre de physique des particules de Marseille, CNRS-IN2P3 and Universite de la Mediterranee, Aix-Marseille II, 163, avenue de Luminy, 13288 Marseille Cedex 09 (France); Descourt, P; Visvikis, D [INSERM, U650, Laboratoire du Traitement de l' Information Medicale (LaTIM), CHU Morvan, Brest (France); Frisson, T; Grevillot, L; Guigues, L; Sarrut, D; Zahra, N [Universite de Lyon, CREATIS, CNRS UMR5220, Inserm U630, INSA-Lyon, Universite Lyon 1, Centre Leon Berard (France); Maigne, L; Perrot, Y [Laboratoire de Physique Corpusculaire, 24 Avenue des Landais, 63177 Aubiere Cedex (France); Schaart, D R [Delft University of Technology, Radiation Detection and Medical Imaging, Mekelweg 15, 2629 JB Delft (Netherlands); Pietrzyk, U, E-mail: buvat@imnc.in2p3.fr [Reseach Center Juelich, Institute of Neurosciences and Medicine and Department of Physics, University of Wuppertal (Germany)
2011-02-21
GATE (Geant4 Application for Emission Tomography) is a Monte Carlo simulation platform developed by the OpenGATE collaboration since 2001 and first publicly released in 2004. Dedicated to the modelling of planar scintigraphy, single photon emission computed tomography (SPECT) and positron emission tomography (PET) acquisitions, this platform is widely used to assist PET and SPECT research. A recent extension of this platform, released by the OpenGATE collaboration as GATE V6, now also enables modelling of x-ray computed tomography and radiation therapy experiments. This paper presents an overview of the main additions and improvements implemented in GATE since the publication of the initial GATE paper (Jan et al 2004 Phys. Med. Biol. 49 4543-61). This includes new models available in GATE to simulate optical and hadronic processes, novelties in modelling tracer, organ or detector motion, new options for speeding up GATE simulations, examples illustrating the use of GATE V6 in radiotherapy applications and CT simulations, and preliminary results regarding the validation of GATE V6 for radiation therapy applications. Upon completion of extensive validation studies, GATE is expected to become a valuable tool for simulations involving both radiotherapy and imaging.
Boomer, Kristen; Hammoud, Ahmad
2015-01-01
Silicon carbide (SiC) devices are becoming widely used in electronic power circuits as replacement for conventional silicon parts due to their attractive properties that include low on-state resistance, high temperature tolerance, and high frequency operation. These attributes have a significant impact by reducing system weight, saving board space, and conserving power. In this work, the performance of an automotive-grade high speed gate driver with potential use in controlling SiC FETs (field-Effect Transistors) in converters or motor control applications was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.
Salmon, Stefanie J.; Adriaanse, Marieke A.; De Vet, Emely; Fennis, Bob M.; De Ridder, Denise T D
2014-01-01
Self-control relies on a limited resource that can get depleted, a phenomenon that has been labeled ego-depletion. We argue that individuals may differ in their sensitivity to depleting tasks, and that consequently some people deplete their self-control resource at a faster rate than others. In
Salmon, Stefanie J.; Adriaanse, Marieke A.; De Vet, Emely; Fennis, Bob M.; De Ridder, Denise T. D.
2014-01-01
Self-control relies on a limited resource that can get depleted, a phenomenon that has been labeled ego-depletion. We argue that individuals may differ in their sensitivity to depleting tasks, and that consequently some people deplete their self-control resource at a faster rate than others. In
The modality effect of ego depletion: Auditory task modality reduces ego depletion.
Li, Qiong; Wang, Zhenhong
2016-08-01
An initial act of self-control that impairs subsequent acts of self-control is called ego depletion. The ego depletion phenomenon has been observed consistently. The modality effect refers to the effect of the presentation modality on the processing of stimuli. The modality effect was also robustly found in a large body of research. However, no study to date has examined the modality effects of ego depletion. This issue was addressed in the current study. In Experiment 1, after all participants completed a handgrip task, one group's participants completed a visual attention regulation task and the other group's participants completed an auditory attention regulation task, and then all participants again completed a handgrip task. The ego depletion phenomenon was observed in both the visual and the auditory attention regulation task. Moreover, participants who completed the visual task performed worse on the handgrip task than participants who completed the auditory task, which indicated that there was high ego depletion in the visual task condition. In Experiment 2, participants completed an initial task that either did or did not deplete self-control resources, and then they completed a second visual or auditory attention control task. The results indicated that depleted participants performed better on the auditory attention control task than the visual attention control task. These findings suggest that altering task modality may reduce ego depletion. © 2016 Scandinavian Psychological Associations and John Wiley & Sons Ltd.
Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro
2017-06-01
Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.
Hybrid graphene/silicon Schottky photodiode with intrinsic gating effect
Di Bartolomeo, Antonio; Luongo, Giuseppe; Giubileo, Filippo; Funicello, Nicola; Niu, Gang; Schroeder, Thomas; Lisker, Marco; Lupina, Grzegorz
2017-06-01
We propose a hybrid device consisting of a graphene/silicon (Gr/Si) Schottky diode in parallel with a Gr/SiO2/Si capacitor for high-performance photodetection. The device, fabricated by transfer of commercial graphene on low-doped n-type Si substrate, achieves a photoresponse as high as 3 \\text{A} {{\\text{W}}-1} and a normalized detectivity higher than 3.5× {{10}12} \\text{cm} \\text{H}{{\\text{z}}1/2} {{\\text{W}}-1} in the visible range. It exhibits a photocurrent exceeding the forward current because photo-generated minority carriers, accumulated at Si/SiO2 interface of the Gr/SiO2/Si capacitor, diffuse to the Gr/Si junction. We show that the same mechanism, when due to thermally generated carriers, although usually neglected or disregarded, causes the increased leakage often measured in Gr/Si heterojunctions. We perform extensive I-V and C-V characterization at different temperatures and we measure a zero-bias Schottky barrier height of 0.52 eV at room temperature, as well as an effective Richardson constant A ** = 4× {{10}-5} \\text{A} \\text{c}{{\\text{m}}-2} {{\\text{K}}-2} and an ideality factor n≈ 3.6 , explained by a thin (<1 nm) oxide layer at the Gr/Si interface.
Performance of silicon pad detectors after mixed irradiations with neutrons and fast charged hadrons
Energy Technology Data Exchange (ETDEWEB)
Kramberger, G. [Jozef Stefan Institute, Department of Physics, University of Ljubljana, Jamova 39, SI-1000 Ljubljana (Slovenia)], E-mail: Gregor.Kramberger@ijs.si; Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M. [Jozef Stefan Institute, Department of Physics, University of Ljubljana, Jamova 39, SI-1000 Ljubljana (Slovenia)
2009-10-11
A large set of silicon pad detectors produced on MCz and FZ wafer of p- and n-type was irradiated in two steps, first by fast charged hadrons followed by reactor neutrons. In this way the irradiations resemble the real irradiation fields at LHC. After irradiations controlled annealing started in steps during which the evolution of full depletion voltage, leakage current and charge collection efficiency was monitored. The damage introduced by different irradiation particles was found to be additive. The most striking consequence of that is a decrease of the full depletion voltage for n-type MCz detectors after additional neutron irradiation. This confirms that effective donors introduced by charged hadron irradiation are compensated by acceptors from neutron irradiation.
Performance of silicon pad detectors after mixed irradiations with neutrons and fast charged hadrons
International Nuclear Information System (INIS)
Kramberger, G.; Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M.
2009-01-01
A large set of silicon pad detectors produced on MCz and FZ wafer of p- and n-type was irradiated in two steps, first by fast charged hadrons followed by reactor neutrons. In this way the irradiations resemble the real irradiation fields at LHC. After irradiations controlled annealing started in steps during which the evolution of full depletion voltage, leakage current and charge collection efficiency was monitored. The damage introduced by different irradiation particles was found to be additive. The most striking consequence of that is a decrease of the full depletion voltage for n-type MCz detectors after additional neutron irradiation. This confirms that effective donors introduced by charged hadron irradiation are compensated by acceptors from neutron irradiation.
Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators
Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.
2009-08-01
This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.
The Toxicity of Depleted Uranium
Directory of Open Access Journals (Sweden)
Wayne Briner
2010-01-01
Full Text Available Depleted uranium (DU is an emerging environmental pollutant that is introduced into the environment primarily by military activity. While depleted uranium is less radioactive than natural uranium, it still retains all the chemical toxicity associated with the original element. In large doses the kidney is the target organ for the acute chemical toxicity of this metal, producing potentially lethal tubular necrosis. In contrast, chronic low dose exposure to depleted uranium may not produce a clear and defined set of symptoms. Chronic low-dose, or subacute, exposure to depleted uranium alters the appearance of milestones in developing organisms. Adult animals that were exposed to depleted uranium during development display persistent alterations in behavior, even after cessation of depleted uranium exposure. Adult animals exposed to depleted uranium demonstrate altered behaviors and a variety of alterations to brain chemistry. Despite its reduced level of radioactivity evidence continues to accumulate that depleted uranium, if ingested, may pose a radiologic hazard. The current state of knowledge concerning DU is discussed.
International Nuclear Information System (INIS)
Pereira, L.; Barquinha, P.; Fortunato, E.; Martins, R.
2005-01-01
In this work, metal induced crystallization using nickel was employed to obtain polycrystalline silicon by crystallization of amorphous films for thin film transistor applications. The devices were produced through only one lithographic process with a bottom gate configuration using a new gate dielectric consisting of a multi-layer of aluminum oxide/titanium oxide produced by atomic layer deposition. The best results were obtained for TFTs with the active layer of poly-Si crystallized for 20 h at 500 deg. C using a nickel layer of 0.5 nm where the effective mobility is 45.5 cm 2 V -1 s -1 . The threshold voltage, the on/off current ratio and the sub-threshold voltage are, respectively, 11.9 V, 5.55x10 4 and 2.49 V/dec
New opening hours of the gates
GS Department
2009-01-01
Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department
The behavior of silicon and boron in the surface of corroded nuclear waste glasses: an EFTEM study
International Nuclear Information System (INIS)
Buck, E. C.; Smith, K. L.; Blackford, M. G.
1999-01-01
Using electron energy-loss filtered transmission electron microscopy (EFTEM), we have observed the formation of silicon-rich zones on the corroded surface of a West Valley (WV6) glass. This layer is approximately 100-200 nm thick and is directly underneath a precipitated smectite clay layer. Under conventional (C)TEM illumination, this layer is invisible; indeed, more commonly used analytical techniques, such as x-ray energy dispersive spectroscopy (EDS), have failed to describe fully the localized changes in the boron and silicon contents across this region. Similar silicon-rich and boron-depleted zones were not found on corroded Savannah River Laboratory (SRL) borosilicate glasses, including SRL-EA and SRL-51, although they possessed similar-looking clay layers. This study demonstrates a new tool for examining the corroded surfaces of materials
The oxidized porous silicon field emission array
International Nuclear Information System (INIS)
Smith, D.D.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.K.; McIntyre, P.M.; Pang, Y.; Trost, H.J.
1993-01-01
The goal of developing a highly efficient microwave power source has led the authors to investigate new methods of electron field emission. One method presently under consideration involves the use of oxidized porous silicon thin films. The authors have used this technology to fabricate the first working field emission arrays from this substance. This approach reduces the diameter of an individual emitter to the nanometer scale. Tests of the first samples are encouraging, with extracted electron currents to nearly 1 mA resulting from less than 20 V of pulsed DC gate voltage. Modulated emission at 5 MHz was also observed. Developments of a full-scale emission array capable of delivering an electron beam at 18 GHz of minimum density 100 A/cm 2 is in progress
Vawter, G. Allen
2013-11-12
An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.
Intrinsic respiratory gating in small-animal CT
International Nuclear Information System (INIS)
Bartling, Soenke H.; Dinkel, Julien; Kauczor, Hans-Ulrich; Stiller, Wolfram; Semmler, Wolfhard; Grasruck, Michael; Madisch, Ijad; Gupta, Rajiv; Kiessling, Fabian
2008-01-01
Gating in small-animal CT imaging can compensate artefacts caused by physiological motion during scanning. However, all published gating approaches for small animals rely on additional hardware to derive the gating signals. In contrast, in this study a novel method of intrinsic respiratory gating of rodents was developed and tested for mice (n=5), rats (n=5) and rabbits (n=2) in a flat-panel cone-beam CT system. In a consensus read image quality was compared with that of non-gated and retrospective extrinsically gated scans performed using a pneumatic cushion. In comparison to non-gated images, image quality improved significantly using intrinsic and extrinsic gating. Delineation of diaphragm and lung structure improved in all animals. Image quality of intrinsically gated CT was judged to be equivalent to extrinsically gated ones. Additionally 4D datasets were calculated using both gating methods. Values for expiratory, inspiratory and tidal lung volumes determined with the two gating methods were comparable and correlated well with values known from the literature. We could show that intrinsic respiratory gating in rodents makes additional gating hardware and preparatory efforts superfluous. This method improves image quality and allows derivation of functional data. Therefore it bears the potential to find wide applications in small-animal CT imaging. (orig.)
High sensitivity pH sensing on the BEOL of industrial FDSOI transistors
Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader
2017-08-01
In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.
Signatures of Mechanosensitive Gating.
Morris, Richard G
2017-01-10
The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.
Management of depleted uranium
International Nuclear Information System (INIS)
2001-01-01
Large stocks of depleted uranium have arisen as a result of enrichment operations, especially in the United States and the Russian Federation. Countries with depleted uranium stocks are interested in assessing strategies for the use and management of depleted uranium. The choice of strategy depends on several factors, including government and business policy, alternative uses available, the economic value of the material, regulatory aspects and disposal options, and international market developments in the nuclear fuel cycle. This report presents the results of a depleted uranium study conducted by an expert group organised jointly by the OECD Nuclear Energy Agency and the International Atomic Energy Agency. It contains information on current inventories of depleted uranium, potential future arisings, long term management alternatives, peaceful use options and country programmes. In addition, it explores ideas for international collaboration and identifies key issues for governments and policy makers to consider. (authors)
Quantum gate decomposition algorithms.
Energy Technology Data Exchange (ETDEWEB)
Slepoy, Alexander
2006-07-01
Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.
International Nuclear Information System (INIS)
Kamenev, D. I.; Berman, G. P.; Tsifrinovich, V. I.
2006-01-01
The errors caused by qubit displacements from their prescribed locations in an ensemble of spin chains are estimated analytically and calculated numerically for a quantum computer based on phosphorus donors in silicon. We show that it is possible to polarize (initialize) the nuclear spins even with displaced qubits by using controlled-NOT gates between the electron and nuclear spins of the same phosphorus atom. However, a controlled-NOT gate between the displaced electron spins is implemented with large error because of the exponential dependence of exchange interaction constant on the distance between the qubits. If quantum computation is implemented on an ensemble of many spin chains, the errors can be small if the number of chains with displaced qubits is small
Comparative Analysis of VERA Depletion Problems
International Nuclear Information System (INIS)
Park, Jinsu; Kim, Wonkyeong; Choi, Sooyoung; Lee, Hyunsuk; Lee, Deokjung
2016-01-01
Each code has its own solver for depletion, which can produce different depletion calculation results. In order to produce reference solutions for depletion calculation comparison, sensitivity studies should be preceded for each depletion solver. The sensitivity tests for burnup interval, number of depletion zones, and recoverable energy per fission (Q-value) were performed in this paper. For the comparison of depletion calculation results, usually the multiplication factors are compared as a function of burnup. In this study, new comparison methods have been introduced by using the number density of isotope or element, and a cumulative flux instead of burnup. In this paper, optimum depletion calculation options are determined through the sensitivity study of the burnup intervals and the number of depletion intrazones. Because the depletion using CRAM solver performs well for large burnup intervals, smaller number of burnup steps can be used to produce converged solutions. It was noted that the depletion intra-zone sensitivity is only pin-type dependent. The 1 and 10 depletion intra-zones for the normal UO2 pin and gadolinia rod, respectively, are required to obtain the reference solutions. When the optimized depletion calculation options are used, the differences of Q-values are found to be a main cause of the differences of solutions. In this paper, new comparison methods were introduced for consistent code-to-code comparisons even when different kappa libraries were used in the depletion calculations
A silicon pixel detector with routing for external VLSI read-out
International Nuclear Information System (INIS)
Thomas, S.L.; Seller, P.
1988-07-01
A silicon pixel detector with an array of 32 by 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector. The detailed design of the pixels, their layout and method of read-out are discussed. A number of test structures have been incorporated onto the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future. (author)
Radiation hardness and charge collection efficiency of lithium irradiated thin silicon diodes
Boscardin, Maurizio; Bruzzi, Mara; Candelori, Andrea; Focardi, Ettore; Khomenkov, Volodymyr P; Piemonte, Claudio; Ronchin, S; Tosi, C; Zorzi, N
2005-01-01
Due to their low depletion voltage, even after high particle fluences, improved tracking precision and momentum resolution, and reduced material budget, thin substrates are one of the possible choices to provide radiation hard detectors for future high energy physics experiments. In the framework of the CERN RD50 Collaboration, we have developed PIN diode detectors on membranes obtained by locally thinning the silicon substrate by means of TMAH etching from the wafer backside. Diodes of different shapes and sizes have been fabricated on 50- mu m and 100- mu m thick membranes and tested, showing a low leakage current (of 300 nA/cm/sup 3/) and a very low depletion voltage (in the order of 1 V for the 50 mu m membrane) before irradiation. Radiation damage tests have been performed with 58 MeV lithium (Li) ions up to the fluence of 10/sup 14/ Li/cm/sup 2/ in order to determine the depletion voltage and leakage current density increase after irradiation. Charge collection efficiency tests carried out with a beta /...
Self-gated fat-suppressed cardiac cine MRI.
Ingle, R Reeve; Santos, Juan M; Overall, William R; McConnell, Michael V; Hu, Bob S; Nishimura, Dwight G
2015-05-01
To develop a self-gated alternating repetition time balanced steady-state free precession (ATR-SSFP) pulse sequence for fat-suppressed cardiac cine imaging. Cardiac gating is computed retrospectively using acquired magnetic resonance self-gating data, enabling cine imaging without the need for electrocardiogram (ECG) gating. Modification of the slice-select rephasing gradients of an ATR-SSFP sequence enables the acquisition of a one-dimensional self-gating readout during the unused short repetition time (TR). Self-gating readouts are acquired during every TR of segmented, breath-held cardiac scans. A template-matching algorithm is designed to compute cardiac trigger points from the self-gating signals, and these trigger points are used for retrospective cine reconstruction. The proposed approach is compared with ECG-gated ATR-SSFP and balanced steady-state free precession in 10 volunteers and five patients. The difference of ECG and self-gating trigger times has a variability of 13 ± 11 ms (mean ± SD). Qualitative reviewer scoring and ranking indicate no statistically significant differences (P > 0.05) between self-gated and ECG-gated ATR-SSFP images. Quantitative blood-myocardial border sharpness is not significantly different among self-gated ATR-SSFP ( 0.61±0.15 mm -1), ECG-gated ATR-SSFP ( 0.61±0.15 mm -1), or conventional ECG-gated balanced steady-state free precession cine MRI ( 0.59±0.15 mm -1). The proposed self-gated ATR-SSFP sequence enables fat-suppressed cardiac cine imaging at 1.5 T without the need for ECG gating and without decreasing the imaging efficiency of ATR-SSFP. © 2014 Wiley Periodicals, Inc.
Ion beam induces nitridation of silicon
International Nuclear Information System (INIS)
Petravic, M.; Williams, J.S.; Conway, M.
1998-01-01
High dose ion bombardment of silicon with reactive species, such as oxygen and nitrogen, has attracted considerable interest due to possible applications of beam-induced chemical compounds with silicon. For example, high energy oxygen bombardment of Si is now routinely used to form buried oxide layers for device purposes, the so called SIMOX structures. On the other hand, Si nitrides, formed by low energy ( 100 keV) nitrogen beam bombardment of Si, are attractive as oxidation barriers or gate insulators, primarily due to the low diffusivity of many species in Si nitrides. However, little data exists on silicon nitride formation during bombardment and its angle dependence, in particular for N 2 + bombardment in the 10 keV range, which is of interest for analytical techniques such as SIMS. In SIMS, low energy oxygen ions are more commonly used as bombarding species, as oxygen provides stable ion yields and enhances the positive secondary ion yield. Therefore, a large body of data can be found in the literature on oxide formation during low energy oxygen bombardment. Nitrogen bombardment of Si may cause similar effects to oxygen bombardment, as nitrogen and oxygen have similar masses and ranges in Si, show similar sputtering effects and both have the ability to form chemical compounds with Si. In this work we explore this possibility in some detail. We compare oxide and nitride formation during oxygen and nitrogen ion bombardment of Si under similar conditions. Despite the expected similar behaviour, some large differences in compound formation were found. These differences are explained in terms of different atomic diffusivities in oxides and nitrides, film structural differences and thermodynamic properties. (author)
International Nuclear Information System (INIS)
Datta, Deepanjan; Ganguly, Samiran; Dasgupta, S
2007-01-01
Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p + poly-n + poly-p + poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime
Contini, D.; Dalla Mora, A.; Di Sieno, L.; Cubeddu, R.; Tosi, A.; Boso, G.; Pifferi, A.
2013-03-01
In recent years, emerging applications, such as diffuse optical imaging and spectroscopy (e.g., functional brain imaging and optical mammography), in which a wide dynamic range is crucial, have turned the interest towards Single-Photon Avalanche Diode (SPAD). In these fields, the use of a fast-gated SPAD has proven to be a successful technique to increase the measurement sensitivity of different orders of magnitude. However, an unknown background noise has been observed at high illumination during the gate-OFF time, thus setting a limit to the maximum increase of the dynamic range. In this paper we describe this noise in thin-junction silicon single-photon avalanche diode when a large amount of photons reaches the gated detector during the OFF time preceding the enabling time. This memory effect increases the background noise with respect to primary dark count rate similarly to a classical afterpulsing process, but differently it is not related to a previous avalanche ignition in the detector. We discovered that memory effect increases linearly with the power of light impinging on the detector and it has an exponential trend with time constants far different from those of afterpulsing and independently of the bias voltage applied to the junction. For these reasons, the memory effect is not due to the same trapping states of afterpulsing and must be described as a different process.
International Nuclear Information System (INIS)
Tsai, I.C.; Lee, Tain; Chen, Min-Chi; Fu, Yun-Ching; Jan, Sheng-Lin; Wang, Chung-Chi; Chang, Yen
2007-01-01
Multidetector CT (MDCT) seems to be a promising tool for detection of neonatal coronary arteries, but whether the ECG-gated or non-ECG-gated technique should be used has not been established. To compare the detection rate and image quality of neonatal coronary arteries on MDCT using ECG-gated and non-ECG-gated techniques. Twelve neonates with complex congenital heart disease were included. The CT scan was acquired using an ECG-gated technique, and the most quiescent phase of the RR interval was selected to represent the ECG-gated images. The raw data were then reconstructed without the ECG signal to obtain non-ECG-gated images. The detection rate and image quality of nine coronary artery segments in the two sets of images were then compared. A two-tailed paired t test was used with P values <0.05 considered as statistically significant. In all coronary segments the ECG-gated technique had a better detection rate and produced images of better quality. The difference between the two techniques ranged from 25% in the left main coronary artery to 100% in the distal right coronary artery. For neonates referred for MDCT, if evaluation of coronary artery anatomy is important for the clinical management or surgical planning, the ECG-gated technique should be used because it can reliably detect the coronary arteries. (orig.)
Microcrystalline silicon deposition: Process stability and process control
International Nuclear Information System (INIS)
Donker, M.N. van den; Kilper, T.; Grunsky, D.; Rech, B.; Houben, L.; Kessels, W.M.M.; Sanden, M.C.M. van de
2007-01-01
Applying in situ process diagnostics, we identified several process drifts occurring in the parallel plate plasma deposition of microcrystalline silicon (μc-Si:H). These process drifts are powder formation (visible from diminishing dc-bias and changing spatial emission profile on a time scale of 10 0 s), transient SiH 4 depletion (visible from a decreasing SiH emission intensity on a time scale of 10 2 s), plasma heating (visible from an increasing substrate temperature on a time scale of 10 3 s) and a still puzzling long-term drift (visible from a decreasing SiH emission intensity on a time scale of 10 4 s). The effect of these drifts on the crystalline volume fraction in the deposited films is investigated by selected area electron diffraction and depth-profiled Raman spectroscopy. An example shows how the transient depletion and long-term drift can be prevented by suitable process control. Solar cells deposited using this process control show enhanced performance. Options for process control of plasma heating and powder formation are discussed
International Nuclear Information System (INIS)
Choi, H.Y.; Wong, H.; Filip, V.; Sen, B.; Kok, C.W.; Chan, M.; Poon, M.C.
2006-01-01
It was recently found that the silicon oxynitride prepared by oxidation of silicon-rich silicon nitride (SRN) has several important features. The high nitrogen and extremely low hydrogen content of this material allows it to have a high dielectric constant and a low trap density. The present work investigates in further detail the electrical reliability of this kind of gate dielectric films by studying the charge trapping and interface state generation induced by constant current stressing. Capacitance-voltage (C-V) measurements indicate that for oxidation temperatures of 850 and 950 deg. C, the interface trap generation is minimal because of the high nitrogen content at the interface. At a higher oxidation temperature of 1050 deg. C, a large flatband shift is found for constant current stressing. This observation can be explained by the significant reduction of the nitrogen content and the phase separation effect at this temperature as found by X-ray photoelectron spectroscopy study. In addition to the high nitrogen content, the Si atoms at the interface exist in the form of random bonding to oxygen and nitrogen atoms for samples oxidized at 850 and 950 deg. C. This structure reduces the interface bonding constraint and results in the low interface trap density. For heavily oxidized samples the trace amount of interface nitrogen atoms exist in the form of a highly constraint SiN 4 phase and the interface oxynitride layer is a random mixture of SiO 4 and SiN 4 phases, which consequently reduces the reliability against high energy electron stressing
Selective porous gates made from colloidal silica nanoparticles
Directory of Open Access Journals (Sweden)
Roberto Nisticò
2015-11-01
Full Text Available Highly selective porous films were prepared by spin-coating deposition of colloidal silica nanoparticles on an appropriate macroporous substrate. Silica nanoparticles very homogenous in size were obtained by sol–gel reaction of a metal oxide silica precursor, tetraethyl orthosilicate (TEOS, and using polystyrene-block-poly(ethylene oxide (PS-b-PEO copolymers as soft-templating agents. Nanoparticles synthesis was carried out in a mixed solvent system. After spin-coating onto a macroporous silicon nitride support, silica nanoparticles were calcined under controlled conditions. An organized nanoporous layer was obtained characterized by a depth filter-like structure with internal porosity due to interparticle voids. Permeability and size-selectivity were studied by monitoring the diffusion of probe molecules under standard conditions and under the application of an external stimulus (i.e., electric field. Promising results were obtained, suggesting possible applications of these nanoporous films as selective gates for controlled transport of chemical species in solution.
Energy Technology Data Exchange (ETDEWEB)
Datta, Deepanjan [Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 (United States); Ganguly, Samiran [Department of Electronics Engineering, Indian School of Mines, Dhanbad-826004 (India); Dasgupta, S [Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee-247667 (India)
2007-05-30
Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p{sup +} poly-n{sup +} poly-p{sup +} poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime.
CODA : Compact front-end analog ASIC for silicon detectors
International Nuclear Information System (INIS)
Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.
2004-01-01
The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)
Ozone-depleting Substances (ODS)
U.S. Environmental Protection Agency — This site includes all of the ozone-depleting substances (ODS) recognized by the Montreal Protocol. The data include ozone depletion potentials (ODP), global warming...
Sliding-gate valve for use with abrasive materials
Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.
1985-01-01
The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.
High-speed carrier-depletion silicon Mach-Zehnder optical modulators with lateral PN junctions
Directory of Open Access Journals (Sweden)
Graham Trevor Reed
2014-12-01
Full Text Available This paper presents new experimental data from a lateral PN junction silicon Mach-Zehnder optical modulator. Efficiencies in the 1.4V.cm to 1.9V.cm range are demonstrated for drive voltages between 0V and 6V. High speed operation up to 52Gbit/s is also presented. The performance of the device which has its PN junction positioned in the centre of the waveguide is then compared to previously reported data from a lateral PN junction device with the junction self-aligned to the edge of the waveguide rib. An improvement in modulation efficiency is demonstrated when the junction is positioned in the centre of the waveguide. Finally we propose schemes for achieving high modulation efficiency whilst retaining self-aligned formation of the PN junction.
International Nuclear Information System (INIS)
Shuleiko, D V; Ilin, A S
2016-01-01
Photoluminescence and electrical properties of superlattices with thin (1 to 5 nm) alternating silicon-rich silicon oxide or silicon-rich silicon nitride, and silicon oxide or silicon nitride layers containing silicon nanocrystals prepared by plasma-enhanced chemical vapor deposition with subsequent annealing were investigated. The entirely silicon oxide based superlattices demonstrated photoluminescence peak shift due to quantum confinement effect. Electrical measurements showed the hysteresis effect in the vicinity of zero voltage due to structural features of the superlattices from SiOa 93 /Si 3 N 4 and SiN 0 . 8 /Si 3 N 4 layers. The entirely silicon nitride based samples demonstrated resistive switching effect, comprising an abrupt conductivity change at about 5 to 6 V with current-voltage characteristic hysteresis. The samples also demonstrated efficient photoluminescence with maximum at ∼1.4 eV, due to exiton recombination in silicon nanocrystals. (paper)
Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng
2017-01-01
Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...
On photonic controlled phase gates
International Nuclear Information System (INIS)
Kieling, K; Eisert, J; O'Brien, J L
2010-01-01
As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.
Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs
International Nuclear Information System (INIS)
Li Jin; Liu Hongxia; Li Bin; Cao Lei; Yuan Bo
2010-01-01
For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a 'rollup' in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. (semiconductor devices)
International Nuclear Information System (INIS)
Kim, Myong Seop; Park, Sang Jun
2008-01-01
By using this doping method, silicon semiconductors with an extremely uniform dopant distribution can be produced. They are usually used for high power devices such as thyristor (SCR), IGBT, IGCT and GTO. Now, the demand for high power semiconductor devices has increased rapidly due to the rapid increase of the green energy technologies. Among them, the productions of hybrid cars or fuel cell engines are excessively increased to reduce the amount of discharged air pollution substances, such as carbon dioxide which causes global warming. It is known that the neutron-transmutation-doped floating-zone (FZ) silicon wafers are used in insulated-gate bipolar transistors (IGBTs) which control the speed of the electric traction motors equipped in hybrid or fuel cell vehicles. Therefore, inevitably, it can be supposed that the demand of the NTD silicon is considerably increased. However, it is considered likely that the irradiation capacity will not be large enough to meet the increasing demand. After all, the large irradiation capacity for NTD such as a reactor dedicated to the silicon irradiation will be constructed depending on the industrial demand for NTD silicon. In this work, we investigated the relationship between the hybrid electric vehicle (HEV) industry and the NTD silicon production. Also, we surveyed the prospect for the production of the HEV. Then, we deduced the worldwide demand for the NTD silicon associated with the HEV production. This work can be utilized as the basic material for the construction of the new irradiation facility such as NTD-dedicated neutron source
Reversible logic gates on Physarum Polycephalum
International Nuclear Information System (INIS)
Schumann, Andrew
2015-01-01
In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum
International Nuclear Information System (INIS)
Chen, Chao-Nan; Huang, Jung-Jie
2013-01-01
This study explored the removal of silicon nitride using KrF laser ablation technology with a high threshold fluence of 990 mJ/cm 2 . This technology was used for contact hole patterning to fabricate SiN x -passivation-based amorphous-silicon thin films in a transistor device. Compared to the photolithography process, laser direct patterning using KrF laser ablation technology can reduce the number of process steps by at least three. Experimental results showed that the mobility and threshold voltages of thin film transistors patterned using the laser process were 0.16 cm 2 /V-sec and 0.2 V, respectively. The device performance and the test results of gate voltage stress reliability demonstrated that laser direct patterning is a promising alternative to photolithography in the panel manufacturing of thin-film transistors for liquid crystal displays. - Highlights: ► KrF laser ablation technology is used to remove silicon nitride. ► A simple method for direct patterning contact-hole in thin-film-transistor device. ► Laser technology reduced processing by at least three steps
Spin Measurements of an Electron Bound to a Single Phosphorous Donor in Silicon
Luhman, D. R.; Nguyen, K.; Tracy, L. A.; Carr, S. M.; Borchardt, J.; Bishop, N. C.; Ten Eyck, G. A.; Pluym, T.; Wendt, J.; Carroll, M. S.; Lilly, M. P.
2014-03-01
The spin of an electron bound to a single donor implanted in silicon is potentially useful for quantum information processing. We report on our efforts to measure and manipulate the spin of an electron bound to a single P donor in silicon. A low number of P donors are implanted using a self-aligned process into a silicon substrate in close proximity to a single-electron-transistor (SET) defined by lithographically patterned polysilicon gates. The SET is used to sense the occupancy of the electron on the donor and for spin read-out. An adjacent transmission line allows the application of microwave pulses to rotate the spin of the electron. We will present data from various experiments designed to exploit these capabilities. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. The work was supported by Sandia National Laboratories Directed Research and Development Program. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.
Thick silicon microstrip detectors simulation for PACT: Pair and Compton Telescope
Khalil, M.; Laurent, P.; Lebrun, F.; Tatischeff, V.; Dolgorouky, Y.; Bertoli, W.; Breelle, E.
2016-11-01
PACT is a space borne Pair and Compton Telescope that aims to make a sensitive survey of the gamma-ray sky between 100 keV and 100 MeV. It is based upon two main components: a silicon-based gamma-ray tracker and a crystal-based calorimeter. In this paper we will explain the imaging technique of PACT as a Multi-layered Compton telescope (0.1-10 MeV) and its major improvements over its predecessor COMPTEL. Then we will present a simulation study to optimize the silicon tracker of PACT. This tracker is formed of thousands of identical silicon double sided strip detectors (DSSDs). We have developed a simulation model (using SILVACO) to simulate the DSSD performance while varying its thickness, impurity concentration of the bulk material, electrode pitch, and electrode width. We will present a comprehensive overview of the impact of each varied parameter on the DSSD performance, in view of the application to PACT. The considered DSSD parameters are its depletion voltage, capacitance, and leakage current. After the selection of the PACT DSSD, we will present a simulation of the performance of the PACT telescope in the 0.1-10 MeV range.
Thick silicon microstrip detectors simulation for PACT: Pair and Compton Telescope
International Nuclear Information System (INIS)
Khalil, M.; Laurent, P.; Lebrun, F.; Tatischeff, V.; Dolgorouky, Y.; Bertoli, W.; Breelle, E.
2016-01-01
PACT is a space borne Pair and Compton Telescope that aims to make a sensitive survey of the gamma-ray sky between 100 keV and 100 MeV. It is based upon two main components: a silicon-based gamma-ray tracker and a crystal-based calorimeter. In this paper we will explain the imaging technique of PACT as a Multi-layered Compton telescope (0.1–10 MeV) and its major improvements over its predecessor COMPTEL. Then we will present a simulation study to optimize the silicon tracker of PACT. This tracker is formed of thousands of identical silicon double sided strip detectors (DSSDs). We have developed a simulation model (using SILVACO) to simulate the DSSD performance while varying its thickness, impurity concentration of the bulk material, electrode pitch, and electrode width. We will present a comprehensive overview of the impact of each varied parameter on the DSSD performance, in view of the application to PACT. The considered DSSD parameters are its depletion voltage, capacitance, and leakage current. After the selection of the PACT DSSD, we will present a simulation of the performance of the PACT telescope in the 0.1–10 MeV range.
Thick silicon microstrip detectors simulation for PACT: Pair and Compton Telescope
Energy Technology Data Exchange (ETDEWEB)
Khalil, M., E-mail: khalilmohammad@hotmail.com [APC Laboratory, 10rue Alice Domon et Léonie Duquet, 75205 Paris Cedex 13 (France); Laurent, P.; Lebrun, F. [APC Laboratory, 10rue Alice Domon et Léonie Duquet, 75205 Paris Cedex 13 (France); CEA, Centre de Saclay, 91191 Gif-Sur-Yvette Cedex (France); Tatischeff, V. [CSNSM, IN2P3/CNRSand Paris-Sud University, 91405 Orsay Campus (France); Dolgorouky, Y.; Bertoli, W.; Breelle, E. [APC Laboratory, 10rue Alice Domon et Léonie Duquet, 75205 Paris Cedex 13 (France)
2016-11-01
PACT is a space borne Pair and Compton Telescope that aims to make a sensitive survey of the gamma-ray sky between 100 keV and 100 MeV. It is based upon two main components: a silicon-based gamma-ray tracker and a crystal-based calorimeter. In this paper we will explain the imaging technique of PACT as a Multi-layered Compton telescope (0.1–10 MeV) and its major improvements over its predecessor COMPTEL. Then we will present a simulation study to optimize the silicon tracker of PACT. This tracker is formed of thousands of identical silicon double sided strip detectors (DSSDs). We have developed a simulation model (using SILVACO) to simulate the DSSD performance while varying its thickness, impurity concentration of the bulk material, electrode pitch, and electrode width. We will present a comprehensive overview of the impact of each varied parameter on the DSSD performance, in view of the application to PACT. The considered DSSD parameters are its depletion voltage, capacitance, and leakage current. After the selection of the PACT DSSD, we will present a simulation of the performance of the PACT telescope in the 0.1–10 MeV range.
International Nuclear Information System (INIS)
Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak
2011-01-01
Silicon nanowire field effect transistor sensors with SiO 2 /HfO 2 as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO 2 as the sensing surface and an optimized fabrication process compatible with silicon processing technology.
Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak
2011-10-07
Silicon nanowire field effect transistor sensors with SiO(2)/HfO(2) as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO(2) as the sensing surface and an optimized fabrication process compatible with silicon processing technology.
Silicon/HfO2 interface: Effects of proton irradiation
International Nuclear Information System (INIS)
Maurya, Savita; Radhakrishna, M.
2015-01-01
Substrate oxide interfaces are of paramount importance in deciding the quality of the semiconductor devices. In this work we have studied how 200 keV proton irradiation affects the interface of a 13 nm thick, atomic layer deposited hafnium dioxide on silicon substrate. Pre- and post-irradiation electrical measurements are used to quantify the effect of proton irradiation for varying electrode geometries. Proton irradiation introduces positive charge in the oxide and at the interface of Si/HfO 2 interface. The gate current is not very much affected under positive injection since the induced positive charge is compensated by the injected electrons. Current voltage characteristics under negative bias get affected by the proton irradiation
A fast ADC system for silicon μstrips readout
International Nuclear Information System (INIS)
Inzani, P.; Pedrini, D.; Sala, S.
1986-01-01
A new fast ADC module has been designed. It is part of a large readout system for a high resolution vertex detector consisting of 12 silicon microstrip planes with more than 8000 channels. The module employs a set of monolithic gated integrators on input (LeCroy MIQ 401) multiplexed on a single 8 bit FADC (Thompson EFX8308). A built-in preprocessing, performed through look up tables, accomplishes equalization and reduction of the data and makes high level trigger feasible. As an additional feature, fast histogramming of all the channels in parallel has been made possible with an internal memory. Special care has been paid to realize a low cost and low power consumption system
Stanford, Duke, Rice,... and Gates?
Carey, Kevin
2009-01-01
This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…
Operating characteristics of radiation-hardened silicon pixel detectors for the CMS experiment
Hyosung, Cho
2002-01-01
The Compact Muon Solenoid (CMS) experiment at the CERN Large Hadron Collider (LHC) will have forward silicon pixel detectors as its innermost tracking device. The pixel devices will be exposed to the harsh radiation environment of the LHC. Prototype silicon pixel detectors have been designed to meet the specification of the CMS experiment. No guard ring is required on the n/sup +/ side, and guard rings on the p/sup +/ side are always kept active before and after type inversion. The whole n/sup +/ side is grounded and connected to readout chips, which greatly simplifies detector assembling and improves the stability of bump-bonded readout chips on the n/sup +/ side. Operating characteristics such as the leakage current, the full depletion voltage, and the potential distributions over guard rings were tested using standard techniques. The tests are discussed in this paper. (9 refs).
Benchmarking gate-based quantum computers
Michielsen, Kristel; Nocon, Madita; Willsch, Dennis; Jin, Fengping; Lippert, Thomas; De Raedt, Hans
2017-11-01
With the advent of public access to small gate-based quantum processors, it becomes necessary to develop a benchmarking methodology such that independent researchers can validate the operation of these processors. We explore the usefulness of a number of simple quantum circuits as benchmarks for gate-based quantum computing devices and show that circuits performing identity operations are very simple, scalable and sensitive to gate errors and are therefore very well suited for this task. We illustrate the procedure by presenting benchmark results for the IBM Quantum Experience, a cloud-based platform for gate-based quantum computing.
International Nuclear Information System (INIS)
Frolov, D.; Perevertailo, V.; Frolov, O.; Kononenko, Yu.; Pugatch, V.; Rozenfeld, A.
1995-01-01
Full text: Investigation of detector and special test structures made on detector wafers was carried out. Si wafer with a diameter of 76 mm, n-type, specific resistance 2-6 kΩ·cm, made of Si produced at a titanium-magnesium factory in Zaporozh'e (Ukraine) were used. C-V curves were measured on p + -n-junctions of various areas (0.1 cm 2 to 20 cm 2 ) and various configuration. In coordinated C 3 (dC/dV) -1 vs V initial parts of the curves are horizontal lines, that indicates a uniform dopant concentration into the depth of a sample, while starting with some voltage a rise is observed associated with full depletion of the sample. However this rise is more smooth then one described by a simple model. The smooth rise is due to non-uniformity of the depletion depth over the p + -n-junction area caused by non-uniform distribution of dopant concentration over the wafer surface. As a results, full depletion doesn't occur simultaneously in all regions of the junction and is stretched along the voltage scale. A theory is developed to define a distribution of the sample areas over full depletion voltage V fd or over dopant concentration N and, given a fixed voltage, to define the distribution of non-depleted junction ares over a thickness of non-depleted area. Results show possibility of non uniform N and, correspondingly, V fd by up to 2 times with big junction sizes. A high level of non-uniformity was observed not only on Si made in Zaporozh'e, but also on Wacker Si. This method of measurements and analysis may be helpful both in working with detectors and detector Si quality control. Measurements of current and capacitance in a gate-controlled junction (a MOS structure partially overlapped with a p + -n-junction) allowed division of surface into the depth of the crystal. Some peculiarities are observed in current curves compared to previous reports associated with low dopant concentration in our experiments. Local defect areas near the p-n-junction encouraging avalanche
Salmon, S.J.; Adriaanse, M.A.; Vet, de E.W.M.L.; Fennis, B.M.; Ridder, de D.T.D.
2014-01-01
Self-control relies on a limited resource that can get depleted, a phenomenon that has been labeled ego-depletion. We argue that individuals may differ in their sensitivity to depleting tasks, and that consequently some people deplete their self-control resource at a faster rate than others. In
Palviainen, T; Tuuva, T; Eranen, S; Härkönen, J; Luukka, P; Tuovinen, E
2006-01-01
The structure of silicon semi three-dimensional radiation detector is simulated on purpose to find out its electrical characteristics such as the depletion voltage and electric field. Two-dimensional simulation results are compared to voltage and electric field measurements done by a scanning electron microscope.
Gate Engineering in SOI LDMOS for Device Reliability
Directory of Open Access Journals (Sweden)
Aanand
2016-01-01
Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..
Energy Technology Data Exchange (ETDEWEB)
Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 02447 (Korea, Republic of)
2016-07-15
We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.
Wolf, M.; Noel, G. T.; Stirn, R. J.
1977-01-01
Difficulties in relating observed current-voltage characteristics of individual silicon solar cells to their physical and material parameters were underscored by the unexpected large changes in the current-voltage characteristics telemetered back from solar cells on the ATS-1 spacecraft during their first year in synchronous orbit. Depletion region recombination was studied in cells exhibiting a clear double-exponential dark characteristic by subjecting the cells to proton irradiation. A significant change in the saturation current, an effect included in the Sah, Noyce, Shockley formulation of diode current resulting from recombination in the depletion region, was caused by the introduction of shallow levels in the depletion region by the proton irradiation. This saturation current is not attributable only to diffusion current from outside the depletion region and only its temperature dependence can clarify its origin. The current associated with the introduction of deep-lying levels did not change significantly in these experiments.
CMOS gate array characterization procedures
Spratt, James P.
1993-09-01
Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.
GATE: Improving the computational efficiency
International Nuclear Information System (INIS)
Staelens, S.; De Beenhouwer, J.; Kruecker, D.; Maigne, L.; Rannou, F.; Ferrer, L.; D'Asseler, Y.; Buvat, I.; Lemahieu, I.
2006-01-01
GATE is a software dedicated to Monte Carlo simulations in Single Photon Emission Computed Tomography (SPECT) and Positron Emission Tomography (PET). An important disadvantage of those simulations is the fundamental burden of computation time. This manuscript describes three different techniques in order to improve the efficiency of those simulations. Firstly, the implementation of variance reduction techniques (VRTs), more specifically the incorporation of geometrical importance sampling, is discussed. After this, the newly designed cluster version of the GATE software is described. The experiments have shown that GATE simulations scale very well on a cluster of homogeneous computers. Finally, an elaboration on the deployment of GATE on the Enabling Grids for E-Science in Europe (EGEE) grid will conclude the description of efficiency enhancement efforts. The three aforementioned methods improve the efficiency of GATE to a large extent and make realistic patient-specific overnight Monte Carlo simulations achievable
Energy Technology Data Exchange (ETDEWEB)
Maslova, O. [Keldysh Institute of Applied Mathematics, Russian Academy of Sciences, Miusskaya sq., 4, Moscow 125047 (Russian Federation); GeePs (Group of electrical engineering of Paris), CNRS UMR 8507, CentraleSupélec, Univ Paris-Sud, Sorbonne Universités-UPMC Univ Paris 06, 11 rue Joliot-Curie, Plateau de Moulon, F-91192 Gif-sur-Yvette Cedex (France); Brézard-Oudot, A.; Gueunier-Farret, M.-E.; Alvarez, J.; Kleider, J.-P. [GeePs (Group of electrical engineering of Paris), CNRS UMR 8507, CentraleSupélec, Univ Paris-Sud, Sorbonne Universités-UPMC Univ Paris 06, 11 rue Joliot-Curie, Plateau de Moulon, F-91192 Gif-sur-Yvette Cedex (France)
2015-09-21
We develop a fully analytical model in order to describe the temperature dependence of the low frequency capacitance of heterojunctions between hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si). We demonstrate that the slope of the capacitance-temperature (C-T) curve is strongly enhanced if the c-Si surface is under strong inversion conditions compared to the usually assumed depletion layer capacitance. We have extended our analytical model to integrate a very thin undoped (i) a-Si:H layer at the interface and the finite thickness of the doped a-Si:H layer that are used in high efficiency solar cells for the passivation of interface defects and to limit short circuit current losses. Finally, using our calculations, we analyze experimental data on high efficiency silicon heterojunction solar cells. The transition from the strong inversion limited behavior to the depletion layer behavior is discussed in terms of band offsets, density of states in a-Si:H, and work function of the indium tin oxide (ITO) front electrode. In particular, it is evidenced that strong inversion conditions prevail at the c-Si surface at high temperatures down to 250 K, which can only be reproduced if the ITO work function is larger than 4.7 eV.
Dual-gated cardiac PET-clinical feasibility study
Energy Technology Data Exchange (ETDEWEB)
Teraes, Mika; Kokki, Tommi; Noponen, Tommi; Hoppela, Erika; Sipilae, Hannu T.; Knuuti, Juhani [Turku PET Centre, PO BOX 52, Turku (Finland); Durand-Schaefer, Nicolas [General Electric Medical Systems, Buc (France); Pietilae, Mikko [Turku University Hospital, Department of Internal Medicine, Turku (Finland); Kiss, Jan [Turku University Hospital, Department of Surgery, Turku (Finland)
2010-03-15
Both respiratory and cardiac motions reduce image quality in myocardial imaging. For accurate imaging of small structures such as vulnerable coronary plaques, simultaneous cardiac and respiratory gating is warranted. This study tests the feasibility of a recently developed robust method for cardiac-respiratory gating. List-mode data with triggers from respiratory and cardiac cycles are rearranged into dual-gated segments and reconstructed with standard algorithms of a commercial PET/CT scanner. Cardiac gates were defined as three fixed phases and one variable diastolic phase. Chest motion was measured with a respiratory gating device and post-processed to determine gates. Preservation of quantification in dual-gated images was tested with an IEC whole-body phantom. Minipig and human studies were performed to evaluate the feasibility of the method. In minipig studies, a coronary catheter with radioactive tip was guided in coronary artery for in vivo and ex vivo acquisitions. Dual gating in humans with suspected cardiac disorders was performed using 18-F-FDG as a tracer. The method was found feasible for in vivo imaging and the radioactive catheter tip was better resolved in gated images. In human studies, the dual gating was found feasible and easy for clinical routine. Maximal movement of myocardial surface in cranio-caudal direction was over 20 mm. The shape of myocardium was clearly different between the gates and papillary muscles become more visible in diastolic images. The first clinical experiences using robust cardiac-respiratory dual gating are encouraging. Further testing in larger clinical populations using tracers designed especially for plaque imaging is warranted. (orig.)
Dual-gated cardiac PET-clinical feasibility study
International Nuclear Information System (INIS)
Teraes, Mika; Kokki, Tommi; Noponen, Tommi; Hoppela, Erika; Sipilae, Hannu T.; Knuuti, Juhani; Durand-Schaefer, Nicolas; Pietilae, Mikko; Kiss, Jan
2010-01-01
Both respiratory and cardiac motions reduce image quality in myocardial imaging. For accurate imaging of small structures such as vulnerable coronary plaques, simultaneous cardiac and respiratory gating is warranted. This study tests the feasibility of a recently developed robust method for cardiac-respiratory gating. List-mode data with triggers from respiratory and cardiac cycles are rearranged into dual-gated segments and reconstructed with standard algorithms of a commercial PET/CT scanner. Cardiac gates were defined as three fixed phases and one variable diastolic phase. Chest motion was measured with a respiratory gating device and post-processed to determine gates. Preservation of quantification in dual-gated images was tested with an IEC whole-body phantom. Minipig and human studies were performed to evaluate the feasibility of the method. In minipig studies, a coronary catheter with radioactive tip was guided in coronary artery for in vivo and ex vivo acquisitions. Dual gating in humans with suspected cardiac disorders was performed using 18-F-FDG as a tracer. The method was found feasible for in vivo imaging and the radioactive catheter tip was better resolved in gated images. In human studies, the dual gating was found feasible and easy for clinical routine. Maximal movement of myocardial surface in cranio-caudal direction was over 20 mm. The shape of myocardium was clearly different between the gates and papillary muscles become more visible in diastolic images. The first clinical experiences using robust cardiac-respiratory dual gating are encouraging. Further testing in larger clinical populations using tracers designed especially for plaque imaging is warranted. (orig.)
Ego Depletion Impairs Implicit Learning
Thompson, Kelsey R.; Sanchez, Daniel J.; Wesley, Abigail H.; Reber, Paul J.
2014-01-01
Implicit skill learning occurs incidentally and without conscious awareness of what is learned. However, the rate and effectiveness of learning may still be affected by decreased availability of central processing resources. Dual-task experiments have generally found impairments in implicit learning, however, these studies have also shown that certain characteristics of the secondary task (e.g., timing) can complicate the interpretation of these results. To avoid this problem, the current experiments used a novel method to impose resource constraints prior to engaging in skill learning. Ego depletion theory states that humans possess a limited store of cognitive resources that, when depleted, results in deficits in self-regulation and cognitive control. In a first experiment, we used a standard ego depletion manipulation prior to performance of the Serial Interception Sequence Learning (SISL) task. Depleted participants exhibited poorer test performance than did non-depleted controls, indicating that reducing available executive resources may adversely affect implicit sequence learning, expression of sequence knowledge, or both. In a second experiment, depletion was administered either prior to or after training. Participants who reported higher levels of depletion before or after training again showed less sequence-specific knowledge on the post-training assessment. However, the results did not allow for clear separation of ego depletion effects on learning versus subsequent sequence-specific performance. These results indicate that performance on an implicitly learned sequence can be impaired by a reduction in executive resources, in spite of learning taking place outside of awareness and without conscious intent. PMID:25275517
Ego depletion impairs implicit learning.
Directory of Open Access Journals (Sweden)
Kelsey R Thompson
Full Text Available Implicit skill learning occurs incidentally and without conscious awareness of what is learned. However, the rate and effectiveness of learning may still be affected by decreased availability of central processing resources. Dual-task experiments have generally found impairments in implicit learning, however, these studies have also shown that certain characteristics of the secondary task (e.g., timing can complicate the interpretation of these results. To avoid this problem, the current experiments used a novel method to impose resource constraints prior to engaging in skill learning. Ego depletion theory states that humans possess a limited store of cognitive resources that, when depleted, results in deficits in self-regulation and cognitive control. In a first experiment, we used a standard ego depletion manipulation prior to performance of the Serial Interception Sequence Learning (SISL task. Depleted participants exhibited poorer test performance than did non-depleted controls, indicating that reducing available executive resources may adversely affect implicit sequence learning, expression of sequence knowledge, or both. In a second experiment, depletion was administered either prior to or after training. Participants who reported higher levels of depletion before or after training again showed less sequence-specific knowledge on the post-training assessment. However, the results did not allow for clear separation of ego depletion effects on learning versus subsequent sequence-specific performance. These results indicate that performance on an implicitly learned sequence can be impaired by a reduction in executive resources, in spite of learning taking place outside of awareness and without conscious intent.
Ego depletion impairs implicit learning.
Thompson, Kelsey R; Sanchez, Daniel J; Wesley, Abigail H; Reber, Paul J
2014-01-01
Implicit skill learning occurs incidentally and without conscious awareness of what is learned. However, the rate and effectiveness of learning may still be affected by decreased availability of central processing resources. Dual-task experiments have generally found impairments in implicit learning, however, these studies have also shown that certain characteristics of the secondary task (e.g., timing) can complicate the interpretation of these results. To avoid this problem, the current experiments used a novel method to impose resource constraints prior to engaging in skill learning. Ego depletion theory states that humans possess a limited store of cognitive resources that, when depleted, results in deficits in self-regulation and cognitive control. In a first experiment, we used a standard ego depletion manipulation prior to performance of the Serial Interception Sequence Learning (SISL) task. Depleted participants exhibited poorer test performance than did non-depleted controls, indicating that reducing available executive resources may adversely affect implicit sequence learning, expression of sequence knowledge, or both. In a second experiment, depletion was administered either prior to or after training. Participants who reported higher levels of depletion before or after training again showed less sequence-specific knowledge on the post-training assessment. However, the results did not allow for clear separation of ego depletion effects on learning versus subsequent sequence-specific performance. These results indicate that performance on an implicitly learned sequence can be impaired by a reduction in executive resources, in spite of learning taking place outside of awareness and without conscious intent.
International Nuclear Information System (INIS)
Clement, J.J.
1980-01-01
The use of plasma-deposited silicon nitride as a final passivation over metal-gate CMOS integrated circuits degrades the radiation hardness of these devices. The hardness degradation is manifested by increased radiation-induced threshold voltage shifts caused principally by the charging of new interface states and, to a lesser extent, by the trapping of holes created upon exposure to ionizing radiation. The threshold voltage shifts are a strong function of the deposition temperature, and show very little dependence on thickness for films deposited at 300 0 C. There is some correlation between the threshold voltage shifts and the hydrogen content of the PECVD silicon nitride films used as the final passivation layer as a function of deposition temperature. The mechanism by which the hydrogen contained in these films may react with the Si/SiO 2 interface is not clear at this point
Exposure to nature counteracts aggression after depletion.
Wang, Yan; She, Yihan; Colarelli, Stephen M; Fang, Yuan; Meng, Hui; Chen, Qiuju; Zhang, Xin; Zhu, Hongwei
2018-01-01
Acts of self-control are more likely to fail after previous exertion of self-control, known as the ego depletion effect. Research has shown that depleted participants behave more aggressively than non-depleted participants, especially after being provoked. Although exposure to nature (e.g., a walk in the park) has been predicted to replenish resources common to executive functioning and self-control, the extent to which exposure to nature may counteract the depletion effect on aggression has yet to be determined. The present study investigated the effects of exposure to nature on aggression following depletion. Aggression was measured by the intensity of noise blasts participants delivered to an ostensible opponent in a competition reaction-time task. As predicted, an interaction occurred between depletion and environmental manipulations for provoked aggression. Specifically, depleted participants behaved more aggressively in response to provocation than non-depleted participants in the urban condition. However, provoked aggression did not differ between depleted and non-depleted participants in the natural condition. Moreover, within the depletion condition, participants in the natural condition had lower levels of provoked aggression than participants in the urban condition. This study suggests that a brief period of nature exposure may restore self-control and help depleted people regain control over aggressive urges. © 2017 Wiley Periodicals, Inc.
Demonstration of a Quantum Nondemolition Sum Gate
DEFF Research Database (Denmark)
Yoshikawa, J.; Miwa, Y.; Huck, Alexander
2008-01-01
The sum gate is the canonical two-mode gate for universal quantum computation based on continuous quantum variables. It represents the natural analogue to a qubit C-NOT gate. In addition, the continuous-variable gate describes a quantum nondemolition (QND) interaction between the quadrature...
Looking behind the scenes: Raman spectroscopy of top-gated epitaxial graphene through the substrate
International Nuclear Information System (INIS)
Fromm, F; Wehrfritz, P; Seyller, Th; Hundhausen, M
2013-01-01
Raman spectroscopy is frequently used to study the properties of epitaxial graphene grown on silicon carbide (SiC). In this work, we present a confocal micro-Raman study of epitaxial graphene on SiC(0001) in top-down geometry, i.e. in a geometry where both the primary laser light beam as well as the back-scattered light is guided through the SiC substrate. Compared to the conventional top-up configuration, in which confocal micro-Raman spectra are measured from the air side, we observe a significant intensity enhancement in top-down configuration, indicating that most of the Raman-scattered light is emitted into the SiC substrate. The intensity enhancement is explained in terms of dipole radiation at a dielectric surface. The new technique opens the possibility to probe graphene layers in devices where the graphene layer is covered by non-transparent materials. We demonstrate this by measuring gate-modulated Raman spectra of a top-gated epitaxial graphene field effect device. Moreover, we show that these measurements enable us to disentangle the effects of strain and charge on the positions of the prominent Raman lines in epitaxial graphene on SiC. (paper)
Multi-gated field emitters for a micro-column
International Nuclear Information System (INIS)
Mimura, Hidenori; Kioke, Akifumi; Aoki, Toru; Neo, Yoichiro; Yoshida, Tomoya; Nagao, Masayoshi
2011-01-01
We have developed a multi-gated field emitter (FE) such as a quadruple-gated FE with a three-stacked electrode lens and a quintuple-gated FE with a four-stacked electrode lens. Both the FEs can focus the electron beam. However, the quintuple-gated FE has a stronger electron convergence than the quadruple-gated FE, and a beam crossover is clearly observed for the quintuple-gated FE.
International Nuclear Information System (INIS)
Hildesheim, W.; Seidel, M.
1995-07-01
The silicon detectors used in the H1-PLUG calorimeter have shown increasing aging effects during the '94 run period of the electron proton storage ring HERA. These effects were particularly manifest as degradation of the signal to noise level and the calibration stability. The reasons for this behaviour have been found to be correlated with radiation damage to the silicon oxide passivation edges of the detectors in strong and fluctuating increases of the leakage currents and in severe changes of the flat band voltages. Depletion voltages however are found to be stable and therefore bulk damage of the silicon can be excluded. A comparison with measurements made by thermoluminescence dosimeters as well as related laboratory experiments suggest that the aging is due to very low energetic electrons and photons. (orig.)
International Nuclear Information System (INIS)
Hugo, Geoffrey D.; Agazaryan, Nzhde; Solberg, Timothy D.
2002-01-01
A respiratory gating system has been developed based on a commercial patient positioning system. The purpose of this study is to investigate the ability of the gating system to reproduce normal, nongated IMRT operation and to quantify the errors produced by delivering a nongated IMRT treatment onto a moving target. A moving phantom capable of simultaneous two-dimensional motion was built, and an analytical liver motion function was used to drive the phantom. Studies were performed to assess the effect of gating window size and choice of delivery method (segmented and dynamic multileaf collimation). Additionally, two multiple field IMRT cases were delivered to quantify the error in gated and nongated IMRT with motion. Dosimetric error between nonmoving and moving deliveries is related to gating window size. By reducing the window size, the error can be reduced. Delivery error can be reduced for both dynamic and segmented delivery with gating. For the implementation of dynamic IMRT delivery in this study, dynamic delivery was found to generate larger delivery errors than segmented delivery in most cases studied. For multiple field IMRT delivery, the largest errors were generated in regions where high field modulation was present parallel to the axis of motion. Gating was found to reduce these large errors to clinically acceptable levels
Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications
Nagaiah, Padmaja
As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p
Slade, Holly Claudia
Hydrogenated amorphous silicon thin film transistors (TFTs) are now well-established as switching elements for a variety of applications in the lucrative electronics market, such as active matrix liquid crystal displays, two-dimensional imagers, and position-sensitive radiation detectors. These applications necessitate the development of accurate characterization and simulation tools. The main goal of this work is the development of a semi- empirical, analytical model for the DC and AC operation of an amorphous silicon TFT for use in a manufacturing facility to improve yield and maintain process control. The model is physically-based, in order that the parameters scale with gate length and can be easily related back to the material and device properties. To accomplish this, extensive experimental data and 2D simulations are used to observe and quantify non- crystalline effects in the TFTs. In particular, due to the disorder in the amorphous network, localized energy states exist throughout the band gap and affect all regimes of TFT operation. These localized states trap most of the free charge, causing a gate-bias-dependent field effect mobility above threshold, a power-law dependence of the current on gate bias below threshold, very low leakage currents, and severe frequency dispersion of the TFT gate capacitance. Additional investigations of TFT instabilities reveal the importance of changes in the density of states and/or back channel conduction due to bias and thermal stress. In the above threshold regime, the model is similar to the crystalline MOSFET model, considering the drift component of free charge. This approach uses the field effect mobility to take into account the trap states and must utilize the correct definition of threshold voltage. In the below threshold regime, the density of deep states is taken into account. The leakage current is modeled empirically, and the parameters are temperature dependent to 150oC. The capacitance of the TFT can be
Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels
Ghoneim, Mohamed T.; Fahad, Hossain M.; Hussain, Aftab M.; Rojas, Jhonathan Prieto; Sevilla, Galo T.; Alfaraj, Nasir; Lizardo, Ernesto B.; Hussain, Muhammad Mustafa
2015-01-01
In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.
Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels
Ghoneim, Mohamed T.
2015-12-11
In today’s digital world, complementary metal oxide semiconductor (CMOS) technology enabled scaling of bulk mono-crystalline silicon (100) based electronics has resulted in their higher performance but with increased dynamic and off-state power consumption. Such trade-off has caused excessive heat generation which eventually drains the charge of battery in portable devices. The traditional solution utilizing off-chip fans and heat sinks used for heat management make the whole system bulky and less mobile. Here we show, an enhanced cooling phenomenon in ultra-thin (>10 μm) mono-crystalline (100) silicon (detached from bulk substrate) by utilizing deterministic pattern of porous network of vertical “through silicon” micro-air channels that offer remarkable heat and weight management for ultra-mobile electronics, in a cost effective way with 20× reduction in substrate weight and a 12% lower maximum temperature at sustained loads. We also show the effectiveness of this event in functional MOS field effect transistors (MOSFETs) with high-κ/metal gate stacks.
Kink effect and noise performance in isolated-gate InAs/AlSb high electron mobility transistors
International Nuclear Information System (INIS)
Vasallo, B G; González, T; Mateos, J; Rodilla, H; Moschetti, G; Grahn, J
2012-01-01
The kink effect can spoil the otherwise excellent low noise performance of InAs/AlSb high electron mobility transistors. It has its origin in the pile-up of holes (generated by impact ionization) taking place mainly at the drain side of the buffer, which leads to a reduction of the gate-induced channel depletion and results in a drain current enhancement. Our results indicate that the generation of holes by impact ionization and their further recombination lead to fluctuations in the charge of the hole pile-up, which provoke an important increase in the drain current noise, even when the kink effect is hardly perceptible in the output characteristics. (paper)
\\title{Development of Radiation Damage Models for Irradiated Silicon Sensors Using TCAD Tools}
Bhardwaj, Ashutosh; Lalwani, Kavita; Ranjan, Kirti; Printz, Martin; Ranjeet, Ranjeet; Eber, Robert; Eichhorn, Thomas; Peltola, Timo Hannu Tapani
2014-01-01
Abstract. During the high luminosity upgrade of the LHC (HL-LHC) the CMS tracking system will face a more intense radiation environment than the present system was designed for. In order to design radiation tolerant silicon sensors for the future CMS tracker upgrade it is fundamental to complement the measurement with device simulation. This will help in both the understanding of the device performance and in the optimization of the design parameters. One of the important ingredients of the device simulation is to develop a radiation damage model incorporating both bulk and surface damage. In this paper we will discuss the development of a radiation damage model by using commercial TCAD packages (Silvaco and Synopsys), which successfully reproduce the recent measurements like leakage current, depletion voltage, interstrip capacitance and interstrip resistance, and provides an insight into the performance of irradiated silicon strip sensors.
Cadilha Marques, Gabriel; Garlapati, Suresh Kumar; Dehm, Simone; Dasgupta, Subho; Hahn, Horst; Tahoori, Mehdi; Aghassi-Hagmann, Jasmin
2017-09-01
Printed electronic components offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, to be compatible to the fields of smart sensors, Internet of Things, and wearables, it is essential that devices operate at small supply voltages. In printed electronics, mostly silicon dioxide or organic dielectrics with low dielectric constants have been used as gate isolators, which in turn have resulted in high power transistors operable only at tens of volts. Here, we present inkjet printed circuits which are able to operate at supply voltages as low as ≤2 V. Our transistor technology is based on lithographically patterned drive electrodes, the dimensions of which are carefully kept well within the printing resolutions; the oxide semiconductor, the electrolytic insulator and the top-gate electrodes have been inkjet printed. Our inverters show a gain of ˜4 and 2.3 ms propagation delay time at 1 V supply voltage. Subsequently built 3-stage ring oscillators start to oscillate at a supply voltage of only 0.6 V with a frequency of ˜255 Hz and can reach frequencies up to ˜350 Hz at 2 V supply voltage. Furthermore, we have introduced a systematic methodology for characterizing ring oscillators in the printed electronics domain, which has been largely missing. Benefiting from this procedure, we are now able to predict the switching capacitance and driver capability at each stage, as well as the power consumption of our inkjet printed ring oscillators. These achievements will be essential for analyzing the performance and power characteristics of future inkjet printed digital circuits.
Directory of Open Access Journals (Sweden)
Judith M. Reichel
2015-01-01
Full Text Available GABAergic interneurons are essential for a functional equilibrium between excitatory and inhibitory impulses throughout the CNS. Disruption of this equilibrium can lead to various neurological or neuropsychiatric disorders such as epileptic seizures or schizophrenia. Schizophrenia itself is clinically defined by negative- (e.g. depression and positive- (e.g. hallucinations symptoms as well as cognitive dysfunction. GABAergic interneurons are proposed to play a central role in the etiology and progression of schizophrenia; however, the specific mechanisms and the time-line of symptom development as well as the distinct involvement of cortical and hippocampal GABAergic interneurons in the etiology of schizophrenia-related symptoms are still not conclusively resolved.Previous work demonstrated that GABAergic interneurons can be selectively depleted in adult mice by means of saporin-conjugated anti-vesicular GABA transporter antibodies (SAVAs in vitro and in vivo. Given their involvement in Schizophrenia-related disease etiology, we ablated GABAergic interneurons in the medial prefrontal cortex (mPFC and dorsal hippocampus (dHPC in adult male C57BL/6N mice. Subsequently we assessed alterations in anxiety, sensory processing, hyperactivity and cognition after long-term (>14 days and short-term (< 14 days GABAergic depletion. Long-term GABAergic depletion in the mPFC resulted in a decrease in sensorimotor-gating and impairments in cognitive flexibility. Notably, the same treatment at the level of the dHPC completely abolished spatial learning capabilities. Short-term GABAergic depletion in the dHPC revealed a transient hyperactive phenotype as well as marked impairments regarding the acquisition of a spatial memory. In contrast, recall of a spatial memory was not affected by the same intervention. These findings emphasize the importance of functional local GABAergic networks for the encoding but not the recall of hippocampus-dependent spatial memories.
Gilbertson, Steve
The observation and control of dynamics in atomic and molecular targets requires the use of laser pulses with duration less than the characteristic timescale of the process which is to be manipulated. For electron dynamics, this time scale is on the order of attoseconds where 1 attosecond = 10 -18 seconds. In order to generate pulses on this time scale, different gating methods have been proposed. The idea is to extract or "gate" a single pulse from an attosecond pulse train and switch off all the other pulses. While previous methods have had some success, they are very difficult to implement and so far very few labs have access to these unique light sources. The purpose of this work is to introduce a new method, called double optical gating (DOG), and to demonstrate its effectiveness at generating high contrast single isolated attosecond pulses from multi-cycle lasers. First, the method is described in detail and is investigated in the spectral domain. The resulting attosecond pulses produced are then temporally characterized through attosecond streaking. A second method of gating, called generalized double optical gating (GDOG), is also introduced. This method allows attosecond pulse generation directly from a carrier-envelope phase un-stabilized laser system for the first time. Next the methods of DOG and GDOG are implemented in attosecond applications like high flux pulses and extreme broadband spectrum generation. Finally, the attosecond pulses themselves are used in experiments. First, an attosecond/femtosecond cross correlation is used for characterization of spatial and temporal properties of femtosecond pulses. Then, an attosecond pump, femtosecond probe experiment is conducted to observe and control electron dynamics in helium for the first time.
Silicon drift detectors with on-chip electronics for x-ray spectroscopy.
Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L
1997-01-01
The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.
Kinetics of depletion interactions
Vliegenthart, G.A.; Schoot, van der P.P.A.M.
2003-01-01
Depletion interactions between colloidal particles dispersed in a fluid medium are effective interactions induced by the presence of other types of colloid. They are not instantaneous but built up in time. We show by means of Brownian dynamics simulations that the static (mean-field) depletion force
International Nuclear Information System (INIS)
Kristiansen, Joanna; Guenther, Anne; Aalokken, Trond Mogens; Andersen, Rune
2011-01-01
Purpose: Motion artifacts may degrade a conventional CT examination of the ascending aorta and hinder accurate diagnosis. We quantitatively compared retrospectively electrocardiographic (ECG) -gated multi detector computed tomography (MDCT) with non-ECG-gated MDCT in order to demonstrate whether or not one of the methods should be preferred. Method: The study included seventeen patients with surgically reconstructed aortic root and reimplanted coronary arteries. All patients had undergone both non-gated MDCT and retrospectively ECG-gated MDCT employing a stringently modulated tube current with single phase image reconstruction. The incidence of motion artifacts in the left main coronary artery (LM), proximal right coronary artery (RCA), and aortic root and ascending aorta were rated using a four point scale. The effective dose for each scan was calculated and normalized to a 15 cm scan length. Statistical analysis of motion artifacts and radiation dose was performed using Wilcoxon matched pairs signed rank sum test. Results: A significant reduction in motion artifacts was found in all three vessels in images from the retrospectively ECG-gated scans (LM: P = 0.005, RCA: P = 0.015, aorta: P = 0.003). The mean normalized effective radiation dose was 3.69 mSv (±1.03) for the non-ECG-gated scans and 16.37 mSv (±2.53) for the ECG-gated scans. Conclusion: Retrospective ECG-gating with single phase reconstruction significantly reduces the incidence of motion artifacts in the aortic root and the proximal portion of the coronary arteries but at the expense of a fourfold increase in radiation dose.
International Nuclear Information System (INIS)
Hanson, C.W. III; Hoffman, E.A.
1995-01-01
There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart
18O isotopic tracer studies of silicon oxidation in dry oxygen
International Nuclear Information System (INIS)
Han, C.J.
1986-01-01
Oxidation of silicon in dry oxygen has been an important process in the integrated circuit industry for making gate insulators on metal-oxide-semiconductory (MOS) devices. This work examines this process using isotopic tracers of oxygen to determine the transport mechanisms of oxygen through silicon dioxide. Oxides were grown sequentially using mass-16 and mass-18 oxygen gas sources to label the oxygen molecules from each step. The resulting oxides are analyzed using secondary ion mass spectrometry (SIMS). The results of these analyses suggest two oxidant species are present during the oxidation, each diffuses and oxidizes separately during the process. A model from this finding using a sum of two linear-parabolic growth rates, each representing the growth rate from one of the oxidants, describes the reported oxidation kinetics in the literature closely. A fit of this relationship reveals excellent fits to the data for oxide thicknesses ranging from 30 A to 1 μm and for temperatures ranging from 800 to 1200 0 C. The mass-18 oxygen tracers also enable a direct observation of the oxygen solubility in the silicon dioxide during a dry oxidation process. The SIMS profiles establish a maximum solubility for interstitial oxygen at 1000 0 C at 2 x 10 20 cm -3 . Furthermore, the mass-18 oxygen profiles show negligible network diffusion during an 1000 0 C oxidation
Energy Technology Data Exchange (ETDEWEB)
Maghribi, Mariam N. (Livermore, CA); Krulevitch, Peter (Pleasanton, CA); Hamilton, Julie (Tracy, CA)
2008-12-09
A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.
Wang, Nan; Fricke-Begemann, Th.; Peretzki, P.; Ihlemann, J.; Seibt, M.
2018-03-01
Silicon nanocrystals embedded in silicon oxide that show room temperature photoluminescence (PL) have great potential in silicon light emission applications. Nanocrystalline silicon particle formation by laser irradiation has the unique advantage of spatially controlled heating, which is compatible with modern silicon micro-fabrication technology. In this paper, we employ continuous wave laser irradiation to decompose substrate-bound silicon-rich silicon oxide films into crystalline silicon particles and silicon dioxide. The resulting microstructure is studied using transmission electron microscopy techniques with considerable emphasis on the formation and properties of laser damaged regions which typically quench room temperature PL from the nanoparticles. It is shown that such regions consist of an amorphous matrix with a composition similar to silicon dioxide which contains some nanometric silicon particles in addition to pores. A mechanism referred to as "selective silicon ablation" is proposed which consistently explains the experimental observations. Implications for the damage-free laser decomposition of silicon-rich silicon oxides and also for controlled production of porous silicon dioxide films are discussed.
Double-gated spectral snapshots for biomolecular fluorescence
International Nuclear Information System (INIS)
Nakamura, Ryosuke; Hamada, Norio; Ichida, Hideki; Tokunaga, Fumio; Kanematsu, Yasuo
2007-01-01
A versatile method to take femtosecond spectral snapshots of fluorescence has been developed based on a double gating technique in the combination of an optical Kerr gate and an image intensifier as an electrically driven gate set in front of a charge-coupled device detector. The application of a conventional optical-Kerr-gate method is limited to molecules with the short fluorescence lifetime up to a few hundred picoseconds, because long-lifetime fluorescence itself behaves as a source of the background signal due to insufficiency of the extinction ratio of polarizers employed for the Kerr gate. By using the image intensifier with the gate time of 200 ps, we have successfully suppressed the background signal and overcome the application limit of optical-Kerr-gate method. The system performance has been demonstrated by measuring time-resolved fluorescence spectra for laser dye solution and the riboflavin solution as a typical sample of biomolecule
Deuterium - depleted water. Achievements and perspectives
International Nuclear Information System (INIS)
Titescu, Gh.; Stefanescu, I.; Saros-Rogobete, I.
2001-01-01
Deuterium - depleted water represents water that has an isotopic content lower than 145 ppm D/(D+H) which is the natural isotopic content of water. The research conducted at ICSI Ramnicu Valcea, regarding deuterium - depleted water were completed by the following patents: - technique and installation for deuterium - depleted water production; - distilled water with low deuterium content; - technique and installation for the production of distilled water with low deuterium content; - mineralized water with low deuterium content and technique to produce it. The gold and silver medals won at international salons for inventions confirmed the novelty of these inventions. Knowing that deuterium content of water has a big influence on living organisms, beginning with 1996, the ICSI Ramnicu Valcea, deuterium - depleted water producer, co-operated with Romanian specialized institutes for biological effects' evaluation of deuterium - depleted water. The role of natural deuterium in living organisms was examined by using deuterium - depleted water instead of natural water. These investigations led to the following conclusions: 1. deuterium - depleted water caused a tendency towards the increase of the basal tone, accompanied by the intensification of the vasoconstrictor effects of phenylefrine, noradrenaline and angiotensin; the increase of the basal tone and vascular reactivity produced by the deuterium - depleted water persists after the removal of the vascular endothelium; -2. animals treated with deuterium - depleted water showed an increase of the resistance both to sublethal and to lethal gamma radiation doses, suggesting a radioprotective action by the stimulation of non-specific immune defence mechanism; 3, deuterium - depleted water stimulates immune defence reactions, represented by the opsonic, bactericidal and phagocyte capacity of the immune system, together with increase in the numbers of polymorphonuclear neutrophils; 4. investigations regarding artificial
International Nuclear Information System (INIS)
Yau, A.W.; Whalen, B.A.; Harris, F.R.; Gattinger, R.L.; Pongratz, M.B.; Bernhardt, P.A.
1985-01-01
In an ionospheric depletion experiment where chemically reactive vapors such as H 2 O and CO 2 are injected into the O + dominant F region to accelerate the plasma recombination rate and to reduce the plasma density, the ion composition in the depleted region is modified, and photometric emissions are produced. We compare in situ ion composition, density, and photometric measurements from two ionospheric depletion experiments with predictions from chemical modeling. The two injections, Waterhole I and III, were part of an auroral perturbation experiment and occurred in different ambient conditions. In both injections a core region of greater than fivefold plasma depletion was observed over roughly-equal5-km diameter within seconds of the injection, surrounded by an outer region of less drastic and slower depletion. In Waterhole I the plasma density was depleted tenfold over a 30-km diamter region after 2 min. The ambient O + density was drastically reduced, and the molecular O + 2 abundance was enhanced fivehold in the depletion region. OH airglow emission associated with the depletion was observed with a peak emission intensity of roughly-equal1 kR. In Waterhole III the ambient density was a decade lower, and the plasma depletion was less drastic, being twofold over 30 km after 2 min. The airglow emissions were also much less intense and below measurement sensitivity (30 R for the OH 306.4-nm emission; 50 R for the 630.0-nm emission)
Energy Technology Data Exchange (ETDEWEB)
Xie, X; Cao, D; Housley, D; Mehta, V; Shepard, D [Swedish Cancer Institute, Seattle, WA (United States)
2014-06-01
Purpose: In this work, we have tested the performance of new respiratory gating solutions for Elekta linacs. These solutions include the Response gating and the C-RAD Catalyst surface mapping system.Verification measurements have been performed for a series of clinical cases. We also examined the beam on latency of the system and its impact on delivery efficiency. Methods: To verify the benefits of tighter gating windows, a Quasar Respiratory Motion Platform was used. Its vertical-motion plate acted as a respiration surrogate and was tracked by the Catalyst system to generate gating signals. A MatriXX ion-chamber array was mounted on its longitudinal-moving platform. Clinical plans are delivered to a stationary and moving Matrix array at 100%, 50% and 30% gating windows and gamma scores were calculated comparing moving delivery results to the stationary result. It is important to note that as one moves to tighter gating windows, the delivery efficiency will be impacted by the linac's beam-on latency. Using a specialized software package, we generated beam-on signals of lengths of 1000ms, 600ms, 450ms, 400ms, 350ms and 300ms. As the gating windows get tighter, one can expect to reach a point where the dose rate will fall to nearly zero, indicating that the gating window is close to beam-on latency. A clinically useful gating window needs to be significantly longer than the latency for the linac. Results: As expected, the use of tighter gating windows improved delivery accuracy. However, a lower limit of the gating window, largely defined by linac beam-on latency, exists at around 300ms. Conclusion: The Response gating kit, combined with the C-RAD Catalyst, provides an effective solution for respiratorygated treatment delivery. Careful patient selection, gating window design, even visual/audio coaching may be necessary to ensure both delivery quality and efficiency. This research project is funded by Elekta.
Voltage-Gated Potassium Channels: A Structural Examination of Selectivity and Gating
Kim, Dorothy M.; Nimigean, Crina M.
2016-01-01
Voltage-gated potassium channels play a fundamental role in the generation and propagation of the action potential. The discovery of these channels began with predictions made by early pioneers, and has culminated in their extensive functional and structural characterization by electrophysiological, spectroscopic, and crystallographic studies. With the aid of a variety of crystal structures of these channels, a highly detailed picture emerges of how the voltage-sensing domain reports changes in the membrane electric field and couples this to conformational changes in the activation gate. In addition, high-resolution structural and functional studies of K+ channel pores, such as KcsA and MthK, offer a comprehensive picture on how selectivity is achieved in K+ channels. Here, we illustrate the remarkable features of voltage-gated potassium channels and explain the mechanisms used by these machines with experimental data. PMID:27141052
MIS gas sensors based on porous silicon with Pd and WO{sub 3}/Pd electrodes
Energy Technology Data Exchange (ETDEWEB)
Solntsev, V.S. [Institute of Semiconductor Physics, National Academy of Science of Ukraine, 03028, Kiev (Ukraine); Gorbanyuk, T.I., E-mail: tatyanagor@mail.r [Institute of Semiconductor Physics, National Academy of Science of Ukraine, 03028, Kiev (Ukraine); Litovchenko, V.G.; Evtukh, A.A. [Institute of Semiconductor Physics, National Academy of Science of Ukraine, 03028, Kiev (Ukraine)
2009-09-30
Pd and WO{sub 3}/Pd gate metal-oxide-semiconductor (MIS) gas sensitive structures based on porous silicon layers are studied by the high frequency C(V) method. The chemical compositions of composite WO{sub 3}/Pd electrodes are characterized by secondary-ion mass spectrometry (SIMS). The atomic force microscopy (AFM) was used for morphologic studies of WO{sub 3}/Pd films. As shown in the experiments, WO{sub 3}/Pd structures are more sensitive and selective to the adsorption of hydrogen sulphide compared to Pd gate. The analyses of kinetic characteristics allow us to determine the response and characteristic times for these structures. The response time of MIS-structures with thin composite WO{sub 3}/Pd electrodes (the thickness of Pd is about 50 nm with WO{sub 3} clusters on its surface) is slower compared to the structures with Pd electrodes. Slower sensor responses of WO{sub 3}-based gas sensors may be associated with different mechanism of gas sensitivity of given structures. The enhanced sensitivity and selectivity to H{sub 2}S action of WO{sub 3}/Pd MIS-structures can also be explained by the chemical reaction that occurs at the catalytic active surface of gate electrodes. The possible mechanisms of enhanced sensitivity and selectivity to H{sub 2}S adsorption of MIS gas sensors with WO{sub 3}/Pd composite gate electrodes compared to pure Pd have been analyzed.
International Nuclear Information System (INIS)
George, Rohini; Chung, Theodore D.; Vedam, Sastry S.; Ramakrishnan, Viswanathan; Mohan, Radhe; Weiss, Elisabeth; Keall, Paul J.
2006-01-01
Purpose: Respiratory gating is a commercially available technology for reducing the deleterious effects of motion during imaging and treatment. The efficacy of gating is dependent on the reproducibility within and between respiratory cycles during imaging and treatment. The aim of this study was to determine whether audio-visual biofeedback can improve respiratory reproducibility by decreasing residual motion and therefore increasing the accuracy of gated radiotherapy. Methods and Materials: A total of 331 respiratory traces were collected from 24 lung cancer patients. The protocol consisted of five breathing training sessions spaced about a week apart. Within each session the patients initially breathed without any instruction (free breathing), with audio instructions and with audio-visual biofeedback. Residual motion was quantified by the standard deviation of the respiratory signal within the gating window. Results: Audio-visual biofeedback significantly reduced residual motion compared with free breathing and audio instruction. Displacement-based gating has lower residual motion than phase-based gating. Little reduction in residual motion was found for duty cycles less than 30%; for duty cycles above 50% there was a sharp increase in residual motion. Conclusions: The efficiency and reproducibility of gating can be improved by: incorporating audio-visual biofeedback, using a 30-50% duty cycle, gating during exhalation, and using displacement-based gating
Electronics and readout of a large area silicon detector for LHC
International Nuclear Information System (INIS)
Borer, K.; Munday, D.J.; Parker, M.A.; Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Scampoli, P.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Spiwoks, R.; Tsesmelis, E.; Benslama, K.; Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; Wu, X.; Fretwurst, E.; Lindstroem, G.; Schultz, T.; Bardos, R.A.; Gorfine, G.W.; Moorhead, G.F.; Taylor, G.N.; Tovey, S.N.; Bibby, J.H.; Hawkings, R.J.; Kundu, N.; Weidberg, A.; Campbell, D.; Murray, P.; Seller, P.; Teiger, J.
1994-01-01
The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquisition systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0-10 C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture. (orig.)
Haynes, Ashleigh; Kemps, Eva; Moffitt, Robyn
2016-11-01
The process model proposes that the ego depletion effect is due to (a) an increase in motivation toward indulgence, and (b) a decrease in motivation to control behaviour following an initial act of self-control. In contrast, the reflective-impulsive model predicts that ego depletion results in behaviour that is more consistent with desires, and less consistent with motivations, rather than influencing the strength of desires and motivations. The current study sought to test these alternative accounts of the relationships between ego depletion, motivation, desire, and self-control. One hundred and fifty-six undergraduate women were randomised to complete a depleting e-crossing task or a non-depleting task, followed by a lab-based measure of snack intake, and self-report measures of motivation and desire strength. In partial support of the process model, ego depletion was related to higher intake, but only indirectly via the influence of lowered motivation. Motivation was more strongly predictive of intake for those in the non-depletion condition, providing partial support for the reflective-impulsive model. Ego depletion did not affect desire, nor did depletion moderate the effect of desire on intake, indicating that desire may be an appropriate target for reducing unhealthy behaviour across situations where self-control resources vary. © 2016 The International Association of Applied Psychology.